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? semiconductor MSM6262-xx 1/52 general description the MSM6262-xx is a dot matrix lcd controller which is fabricated by oki's low power consumption cmos silicon gate technology. in combination with 8-bit microcontroller, the MSM6262-xx can control the dot matrix character type lcd module. the MSM6262-xx is provided with a serial data transfer output. so, a maximum of 160 characters can be controlled by combining this device with the msm5259, msm5839c, or msm5260. the MSM6262-xx is recommended for use in an lcd panel which is capable of displaying 81 to 160 characters. if an lcd panel of which display capacity is 80 characters or less is used, the msm6222b-xx is recommended. the MSM6262-xx is best suited to be used as an lcd controller for applications such as electronic typewriters, pos system terminals, and data banks. features ? dot matrix lcd controller/driver for three different font configuration (5 x 7 dots, 5 x 11 dots and 5 x 12 dots) ? up to 160 characters can be controlled (display data ram ... 160 x 9-bit) ? on-chip character generator rom (cgrom) for 256 different characters 5 x 7 dots ... 128 characters 5 x 11 dots ... 96 characters 5 x 12 dots ... 32 characters ? on-chip character generator ram (cgram) (32 x 8-bit) 5 x 8 dots ... 4 kinds 5 x 12 dots ... 2 kinds ? easy interface with z80, 6809, 80c49, and 80c51 ? underline function ? shift function for g, i, p, q and y ? selectable driving duty ? semiconductor MSM6262-xx dot matrix lcd controller with 48-dot common driver e2b0033-27-y2 duty font configuration (dots) cursor display display (characters x lines) 1/16 5 x 7 80 x 2 1/24 5 x 11 80 x 2 1/32 5 x 7 40 x 4 1/48 5 x 11 40 x 4 available available available available ? package : 80-pin plastic qfp (qfp80-p-1420-0.80-bk) (product name : MSM6262-xxgs-bk) xx indicates code number. this version: nov. 1997 previous version: mar. 1996
? semiconductor MSM6262-xx 2/52 block diagram v dd v ss osc1 osc2 osc3 reset 68 series/80 series cs r/w ( wr ) e ( rd ) a0 a1 8 db 0 - db 7 test1 test2 test3 v 1 v 4 v 5 lcd driving voltage input/ output buffer 9 6 8 8 2 instruc- tion register (i/r) instruc- tion decoder 9 8 address counter (adc) 8 display data ram (ddram) 160 x 9 bits 8 timing generator 48 48 cp load df do busy1 out busy2 out 48-bit shift register com- mon signal driver 1 1 cursor blink, under-line function control character generator rom (cgrom), 11,680 bits 8 9 5 parallel / serial converter 5 8 5 character generator ram (cgram), 256 bits 9 busy flag data register (dr) 2 com1 - com48
? semiconductor MSM6262-xx 3/52 v dd to the inside of the device osc1, 68 series/80 series, cs r/w ( wr ), e ( rd ) a0, a1 v dd v dd to the inside of the device applicable pin: applicable pins: reset v dd from the inside of the device v dd v dd to the inside of of the device v dd to the inside of the device osc2, osc3 applicable pins: v dd from the inside of the device applicable pins: db 0 - db 7 input and output configuration input pin input /output pin
? semiconductor MSM6262-xx 4/52 from the inside of the device cp, load, df, do, busy1 out, busy2 out applicable pins: output pin
? semiconductor MSM6262-xx 5/52 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 com 46 com 47 com 48 v ss (gnd) osc1 osc2 osc3 test1 test2 test3 reset 68 series/80 series cs e ( rd ) r/w ( wr) a0 a1 db 0 db 1 db 2 db 3 db 4 db 5 db 6 com 29 com 28 com 27 com 26 com 25 com 24 com 23 com 22 com 21 com 20 com 19 com 18 com 17 com 16 com 15 com 14 com 13 com 12 com 11 com 10 com 9 com 8 com 7 com 6 com 45 com 44 com 43 com 42 com 41 com 40 com 39 com 38 com 37 com 36 com 35 com 34 com 33 com 32 com 31 com 30 db 7 busy 1 out busy 2 out df load cp do v dd v 1 v 4 v 5 com 1 com 2 com 3 com 4 com 5 80-pin plastic qfp
? semiconductor MSM6262-xx 6/52 pin descriptions symbol type osc1 osc2, osc3 reset 68 series/80 series cs r/w ( wr ) e ( rd ) a0, a1 db 0 - db 7 test1 - test3 v dd , v ss v 1 , v 4, v 5 do cp load df com1 - com48 busy1 out busy2 out i/o i i i i i i i/o i o o o o o o o clock oscillating pins required for internal operation upon receipt of the lcd drive signal and cpu instruction. reset pin selection pin for either 68 series cpu or 80 series cpu chip select pin. by setting cs at "l" level, MSM6262-xx is set at selecting condition. r/w pin of 68 series cpu shall be connected to this pin, while wr pin shall be connected to this pin in the case of 80 series cpu. e pin of 68 series cpu shall be connected to this pin, while rd pin shall be connected to this pin in the case of 80 series cpu. the address bus of cpu shall be connected to these pins. instruction code is set by these pins. the data bus of cpu shall be connected to these pins. these pins are used to set the data of the instruction or to read the data. test pins. normally these pins should be set at v ss or open. voltage supply pins. v dd is also used for the common bias voltage level to drive the lcd. common bias voltage input pins to drive the lcd serial data output pin for segment drivers clock pulse output pin. the clock output from this pin enables the character pattern data, which is output from do, to input to the segment drivers (msm5839c or msm5259). load signal output pin. the character pattern data to the segment drivers, which was output from do and cp, is loaded to the lcd output of the segment drivers, synchronized with the common signal. b-type ac signal output pin to drive the lcd common signal output pins to drive the lcd this pin shows the internal condition of MSM6262-xx. "h" shows that MSM6262-xx is in internal operation, while "l" shows that MSM6262-xx is ready to receive the instruction from the cpu. this pin shows that MSM6262-xx is in internal operation based on the instruction from the cpu, or MSM6262-xx is in display revising operation based on the instruction from the cpu. "h" shows that MSM6262-xx is in internal operation, while "l" shows that the display on the lcd has been established and the MSM6262-xx is ready to receive an instruction. description
? semiconductor MSM6262-xx 7/52 absolute maximum ratings parameter symbol condition rating unit applicable pin supply voltage v dd ta = 25c, v dd Cv ss v C0.3 to +7.0 v dd, v ss supply voltage for driving lcd v 1 , v 4 , v 5 ta = 25c v dd C 12 to v dd + 0.3 vv 1 , v 4 , v 5 input voltage v in ta = 25c C0.3 to v dd + 0.3 v osc1, reset 68 series / 80 series cs , a0, a1, r/w ( wr ) e ( rd ), db 0 - db 7 power dissipation p d ta = 25c 500 mw storage temperature t stg CC C55 to +125 c CC CC recommended operating conditoins parameter symbol condition range unit applicable pin supply voltage v dd v 4.5 to 5.5 v dd, gnd lcd driving voltage v lcd 1/5 bias, v dd Cv 5 3.0 to 11 v operating temperature c CC 1/6, 1/7 bias, v dd Cv 5 4.0 to 11 1/8 bias, v dd Cv 5 4.5 to 11 v v v dd, v 1 , v 4 , v 5 C20 to +75 CC CC note: for bias, refer to *3 in the section "dc characteristics". t op
? semiconductor MSM6262-xx 8/52 electrical characteristics dc characteristics *1. this is applicable to the voltage drop which is caused between v dd , v 1 , v 4 , v 5 and com1 - com48 when a current of 50 m a is flowed in/out to/from all of com1 - com48. (when the output level is either v dd or v 1 , it should be applied only when the current flows in. when the output level is either v 4 or v 5 , it should be applied only when the current flows in. in this case, +5v is applied to v dd and v 1 , while C6 v is applied to v 4 and v 5 .) *2. this is applicable to the current which flows in to v dd under following conditions. v dd = 5 v, v ss = 0 v, v 1 = 2.8 v, v 4 = -3.8 v, v 5 = C6 v, no load, no interface with cpu *3. v 1 to v 5 should be set at as follows. parameter symbol condition min. typ. max. unit applicable pin cs , r/w ( wr ) e ( rd ), a0, a1 db 0 - db 7 db 0 - db 7 osc1, reset 68series/80series do, load, df cp busy1 out busy2 out i o = 50 m a com1 - com48 cs , r/w ( wr ) e ( rd ), a0, a1 osc1, 68series/ 80series supply current i dd1 i dd2 *2 *2 v dd (v dd = 4.5 to 5.5 v , ta = C20 to +75c) lcd driving voltage v dd Cv 5 v 1 , v 4 , v 5 reset "h" input voltage "l" input voltage "h" output voltage "l" output voltage "h" input voltage "l" input voltage "h" output voltage "l" output voltage "h" output voltage "l" output voltage "h" output voltage "l" output voltage v ih1 v il1 v oh1 v ol1 v ih2 v il2 v oh2 v ol2 v oh3 v ol3 v oh4 com voltage drop "h" input current "l" input current "h" input current v ol4 v com i ilh1 i ill1 v lcd i ilh2 i ill2 CC CC i o = C250 m a i o = 1.8 ma CC CC i o = C500 m a i o = 500 m a i o = C1 ma i o = 1 ma i o = C100 m a i o = 1.6 ma v in = v dd v in = v ss 1/5 bias 1/6-1/7 bias 1/8 bias v in = v dd v in = v ss ,v dd = 5 v 2.2 C0.3 2.4 CC C0.3 v dd C0.8 0.85 v dd CC 0.85 v dd CC 2.4 CC CC CC CC CC CC 3.0 4.0 4.5 CC C8 CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC C20 CC v dd 0.7 CC 0.4 v dd 0.8 CC 0.15 v dd CC 0.15 v dd CC 0.4 2.9 1 C1 1.5 1.5 11 11 11 2 C60 v v v v v v v v v v v v m a m a ma ma v v v m a m a "l" input current *3 *1 v dd = 5 v, f osc = 500 khz (rc oscillation) v dd = 5 v, f in = 500 khz (external oscillation) v
? semiconductor MSM6262-xx 9/52 2 lines 4 lines 5 x 8 5 x 12 5 x 8 5 x 12 v 1 v 4 v 5 no. of lines (n) pin font configuration v dd C CC v lcd v dd C CC v lcd v dd C v lcd 1 5 4 5 v dd C CC v lcd v dd C CC v lcd v dd C v lcd 1 6 5 6 v dd C CC v lcd v dd C CC v lcd v dd C v lcd 1 7 6 7 v dd C CC v lcd v dd C CC v lcd v dd C v lcd 1 8 7 8 v lcd = lcd driving voltage ac characteristics *2 *3 *1 open open osc3 osc2 osc1 oscillation source r f c f osc3 osc2 osc1 r f = 39 k w 5% c f = 22 pf 10% (keep the wiring from osc1, osc2, and osc3 to r f and c f as short as possible.) t h t l v dd C0.8 v 0.5 v dd 0.8 v t r t f v dd C0.8 v 0.5 v dd 0.5 v dd 0.8 v f duty = CCCCCCC x 100% t h t h + t l parameter symbol condition min. typ. max. unit applicable pin (v dd = 4.5 to 5.5v , ta = C20 to +75c) v in = v ss v dd = 5 v osc1, osc2, osc3 db 0 - db 7 v in = v dd 45 300 CC input frequency input clock duty input clock rise time input clock fall time rc oscillation frequency "h" input current "l" input current f in f duty t r t f f cr i ilh3 i ill3 *1, *2 *2 *2 *2 *3 CC 300 CC C45 osc1 50 500 CC CC 500 CC C120 55 700 100 100 700 1 C250 % khz ns ns khz m a m a
? semiconductor MSM6262-xx 10/52 timing diagram interface with 80 series cpu (v dd = 4.5 to 5.5v, ta = C20 to +75c) parameter symbol min. max. unit address set-up time cs set-up time wr "l" pulse width rd "l" pulse width wr , rd "h" pulse width address hold time cs hold time data set-up time data hold time (write operation) wr , rd fall time wr , rd rise time data delay time data hold time (read operation) busy output delay time t sa1 t sa2 t wwr t wrd t wh t ha1 t ha2 t swd t hwd t f t r t srd t hrd t bd 110 100 320 320 210 25 25 300 20 CC CC CC 0 CC CC CC CC CC CC CC CC CC CC 25 25 190 CC 410 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
? semiconductor MSM6262-xx 11/52 write operation read operation a0,a1 v ih v il v ih v il cs v il v il t sa1 t ha1 t ha2 t wrd t sa2 e ( rd ) v ih v il v ih t wh t r t f t srd t hrd v ih v il v oh v ol valid data db0 - db7 v oh v ol refer to the dc characteristics for the definition of v ih , v il , v oh and v ol . a0,a1 v ih v il v ih v il cs v il v il t sa1 t ha1 t ha2 t w wr t sa2 r/w ( wr ) v ih v il v ih t wh t r t f t swd t hwd v ih v il v ih v il v ih v il t bd v oh valid data db0 - db7 busy 1 out, busy 2 out
? semiconductor MSM6262-xx 12/52 z80 MSM6262-xx a 0 - a 15 wr db 0 - db 7 db 0 - db 7 a0, a1 cs r/w ( wr ) e ( rd ) 68 series/80 series v ss address decoder * a pull-up resistor of about 50 k w is required when the output of cpu becomes high impedance. * * * rd * iorq * ? interface with z80
? semiconductor MSM6262-xx 13/52 ? interface with 80c49 ? interface with 80c51 msm80c49 MSM6262-xx wr db 0 - db 7 db 0 - db 7 a0, a1 cs r/w ( wr ) e ( rd ) 68 series/80 series v ss address decoder * a pull-up resistor of about 50 k w is required when the output of cpu becomes high impedance. * rd * * stb 8282 ale p20 - p22 * msm80c51 MSM6262-xx wr p00 - p07 db 0 - db 7 a0, a1 cs r/w ( wr ) e ( rd ) 68 series/80 series v ss address decoder * a pull-up resistor of about 50 k w is required when the output of cpu becomes high impedance. * rd * stb 8282 ale p20 - p22 * *
? semiconductor MSM6262-xx 14/52 interface with 68 series cpu (v dd = 4.5 to 5.5 v, ta = C20 to +75c) parameter symbol min. max. unit cycle time address, r/w set-up time cs set-up time e signal "h" pulse width e signal "l" pulse width address, r/w hold time cs hold time data set-up time data hold time (write operation) e signal rise time e signal fall time data delay time data hold time (read operation) busy output delay time t c t b1 t b2 t w t l t a1 t a2 t i t h t r t f t d t o t bd 500 100 90 220 210 20 20 225 30 CC CC CC 10 CC CC CC CC CC CC CC CC CC CC 25 25 180 CC 410 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
? semiconductor MSM6262-xx 15/52 read operation a0, a1 r/w ( wr ) e ( rd ) db0 - db7 cs v ih v il v ih v il t b1 t a1 v ih v ih t w t l v ih v il v il v ih v il t r t f t o v oh v ol valid data t a2 t b2 v il v il t c v oh v ol t d refer to the dc characteristics for the definition of v ih , v il , v oh , and v ol . write operation a0, a1 r/w ( wr ) e ( rd ) db0 - db7 cs busy 1 out, busy 2 out v ih v il v ih v il t b1 t a1 v il v il t w t l v ih v il v il v ih v il t r t f t i t h v ih v il v ih v il valid data t a2 t b2 v il v il t c t bd v oh
? semiconductor MSM6262-xx 16/52 6809 MSM6262-xx a 0 - a 15 e r/w o db 0 - db 7 db 0 - db 7 a0, a1 cs r/w( wr ) e ( rd ) 68 series/80 series v dd address decoder * a pull-up resistor of about 50 k w is required when the output of cpu becomes high impedance. * * * * ? interface with 6809
? semiconductor MSM6262-xx 17/52 interface with segment driver do cp load df v oh v ol v oh v ol v oh v ol v ol v oh v oh t setup t hold v oh v oh v ol v oh v ol t lw(cp) t hw(cp) t cl t lc t m t hw (l) refer to the dc characteristics for the definition of v ih , v il , v oh , and v ol . (v dd = 4.5 to 5.5 v, ta = C20 to +75c, f osc = 500 khz) parameter symbol min. max. unit clock "l" pulse width clock "h" pulse width do set-up time do hold time load, clock set-up time load, clock hold time load, "h" pulse width df delay time t lw(cp) 400 ns t hw(cp) 400 ns t setup 200 ns t hold 200 ns t cl 200 ns t lc 100 ns t hw(l) 400 ns t m C500 500 ns
? semiconductor MSM6262-xx 18/52 reset waveform v dd reset 4.5 v 0 v t rr1 t rr2 t rr2 v il v ih v il v il v ih t rlw refer to the dc characteristics for the definition of v ih , v il , v oh , and v ol . (v dd = 4.5 to 5.5 v, ta = C20 to +75c) parameter symbol min. max. unit "l" input time upon power on "l" input width when in operation rise time t rr1 0.25 CC ms t rlw 0.5 CC ms t rr2 0.1 200 ms
? semiconductor MSM6262-xx 19/52 functional description 1. instruction register (ir) and data register (dr) the MSM6262-xx has two registers, instruction register (ir) and data register (dr). ir is used to store the address code or instruction code of display data ram (dd ram) or character generator ram (cg ram). this register can be written by the cpu, but cannot be read out by the cpu. dr is used to store the data to write into (or read out) the data to/from dd ram or cg ram. the data written into dr by the cpu is automatically written into the dd ram or cg ram. when an address code is written into ir, the data of the specified address is automatically transferred to the dr from either dd ram or cg ram. by having the cpu subsequently read the dr, it is possible to verify dd ram or cg ram data. after the writing of dr by the cpu, the dd ram or cg ram of the next address is selected to be ready for the next cpu writing. likewise, after the reading operation of the cpu, dd ram or cg ram data of the next address is transferred to the dr, when cpu is ready for the next reading operation. 2. busy flag (bf) when the output of busy 1 out is "h", MSM6262-xx is engaged in internal operation. when the output of busy 2 out is "h", it indicates that MSM6262-xx is engaged in internal operation or MSM6262-xx is engaged in the revising of the display starting line on the lcd. (refer to the instruction table.) when the output of busy 1 out is "h", any input of new instruction is ignored. so, before setting a new instruction, it is necessary to check whether busy 1 out and busy 2 out are at "l". 3. address counter (adc) the address counter (adc) allocates the address for the dd ram and cg ram write/read and also for the cursor display. when the instruction code for a dd ram address or cg ram address setting is input to ir, after deciding whether it is dd ram or cg ram, the address counter code is transferred from ir to adc. after writing (reading) the display data to (from) the dd ram or cg ram, the adc increments (or decrements) by 1 automatically as its internal operation.
? semiconductor MSM6262-xx 20/52 4. timing generator circuit this circuit generates the timing signal for the internal operation by cpu's instruction as well as to operate the internal circuit of dd ram, cg ram, cg rom and so forth. it also generates the transfer signal to the segment driver (msm5839c or msm5259). the internal operation accessed by the cpu and internal operation for lcd display is independent. so, a manipulation such as writing data from cpu to dd ram will not have an influence such as display flickering upon any part other than the display part to which the data is written. 5. display data ram (dd ram) dd ram is used to store the 8-bit character code (refer to table 1) and 1-bit under-line data. the address of dd ram corresponds to the display position on the lcd. the correspondence is described below. dd ram address (set to adc) is described as hexadecimal. (1) relation between dd ram and display position in 2-line display mode 1 2 3 4 5 C C C 79 80 C C C C C C 00 80 01 81 02 82 03 83 04 84 4e ce 4f cf 1st line 2nd line digit display position dd ram address (hexadecimal) 1st line 2nd line 00 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 81 02 82 03 83 04 84 05 85 06 86 07 87 08 88 09 89 0a 8a 0b 8b 0c 8c 0d 8d 0e 8e 0f 8f digit msm5839c (2) msm5259 (2) } msm5839c (1) msm5259 (1) { or note: the address of the last digit of the first line and the first digit of the second line does not have any continuity. db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 msb lsb hexadecimal hexadecimal example: when dd ram address is 3a 3a ll lhhhl h adc (2) when 2 pieces of msm5389c(or msm5259) are connected to MSM6262-xx, 32 characters can be displayed from the first digit to yhe 16th degit.
? semiconductor MSM6262-xx 21/52 when the display is shifted by an instruction, the relation between the dd ram address and the display position becomes as follows. (4) relation between the dd ram and display position in 4-line display mode 1st line 2nd line 4f cf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 80 01 81 02 82 03 83 04 84 05 85 06 86 07 87 08 88 09 89 0a 8a 0b 8b 0c 8c 0d 8d 0e 8e digit msm5839c (2) msm5259 (2) } msm5839c (1) msm5259 (1) { or 1st line 2nd line 01 81 02 82 03 83 04 84 05 85 06 86 07 87 08 88 09 89 0a 8a 0b 8b 0c 8c 0d 8d 0e 8e 0f 8f 10 90 (shift to the left) (shift to the right) 1st line 2nd line digit msm5839c (2) msm5259 (2) msm5839c (1) msm5259 (1) { or 00 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 C C C 73 74 75 76 77 78 79 80 01 81 02 82 03 83 04 84 05 85 06 86 07 87 08 88 09 89 0a 8a 0b 8b 0c 8c 0d 8d 0e 8e 0f 8f 10 90 11 91 48 c8 49 c9 4a ca 4b cb 4c cc 4d cd 4e ce 4f cf C C C C C C msm5839c (3)-(9) msm5259 (3)-(9) msm5839c (10) msm5259 (10) } 1st line 2nd line digit display position dd ram address (hexadecimal) note: the address of the last digit of the previous line and the first digit of the next line does not have any continuity. 3rd line 4th line 12345 3940 00 40 80 c0 01 41 81 c1 02 42 82 c2 03 43 83 c3 04 44 84 c4 26 66 a6 e6 27 67 a7 e7 C C C C C C C C C C C C C C C (3) the maximum dd ram capacity of MSM6262-xx is for 160 characters. so, up to 10 pieces of msm5839c (or msm5259) can be connected in the case of 2-line display mode.
? semiconductor MSM6262-xx 22/52 when the display is shifted by an instruction, the relation between the dd ram address and the display position becomes as follows. 1 2 3 4 5 6 7 8 9 10 11121314151617 18 C C C 33343536 373839 40 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 C C C 20 21 22 23 24 25 26 27 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 C C C 60 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 C C C a0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 C C C e0 40 80 c0 61 a1 e1 62 a2 e2 63 a3 e3 64 a4 e4 65 a5 e5 66 a6 e6 67 a7 e7 1st line digit 2nd line 3rd line 4th line msm5839c (1) msm5259 (1) or msm5839c (2) msm5259 (2) msm5839c (3),(4) msm5259 (3),(4) msm5839c (5) msm5259 (5) 1st line 2nd line 00 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 0a 4a 0b 4b 0c 4c 0d 4d 0e 4e 0f 4f digit msm5839c (2) msm5259 (2) } msm5839c (1) msm5259 (1) { or 3rd line 4th line 80 c0 81 c1 82 c2 83 c3 84 c4 85 c5 86 c6 87 c7 88 c8 89 c9 8a ca 8b cb 8c cc 8d cd 8e cb 8f cf (6) the maximum dd ram capacity of MSM6262-xx is for 160 characters. so, up to 5pieces of msm5839c (or msm5259) can be connected in the case of 4-line display mode. (5) when 2 pieces of msm5839c (or msm5259) are connected to MSM6262-xx, 64 characters can be displayed from the first digit to the 16th digit. 1st line 2nd line 27 67 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 40 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 0a 4a 0b 4b 0c 4c 0d 4d 0e 4e digit msm5839c (2) msm5259 (2) } msm5839c (1) msm5259 (1) 3rd line 4th line e7 a7 c0 80 c1 81 c2 82 c3 83 c4 84 c5 85 c6 86 c7 87 c8 88 c9 89 ca 8a cb 8b cc 8c cd 8d ce (shift to right direction) 1st line 2nd line 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 0a 4a 0b 4b 0c 4c 0d 4d 0e 4e 0f 4f 10 50 3rd line 4th line 81 c1 82 c2 83 c3 84 c4 85 c5 86 c6 87 c7 88 c8 89 c9 8a ca 8b cb 8c cc 8d cd 8e ce 8f cf 90 d0 ( shift to left direction ) 8e { or
? semiconductor MSM6262-xx 23/52 6. cursor/blink control circuit this is the circuit to control the generation of cursor and its blinking. this circuit is controlled by the program of the cpu. the position of the cursor and its blink appears on the position according to the adc contents, which correspond to the address of dd ram. for example, when the adc is set as "07" (hex.), the position of cursor and its blinking becomes as follows. 7. underline control circuit first, either underline display mode or underline blinking mode has to be set by the cpu. when an instruction to enable the underline function is input from the cpu, the cursor display shifts to the right direction (increment) or left direction (decrement). display of underline appears (or disappears) on the same position where cursor was displayed. an input of "h" data enables the underline display, while an input of "l" data deletes the underline. 8. character generator rom (cg rom) cg rom stores the character pattern. MSM6262-xx has 128 kinds of 5 x 7-dot patterns, 96 kinds of 5 x 11-dot patterns and 32 kinds of 5 x 12-dot patterns. the character pattern corresponds to the character code which is written into the dd ram. the relation between 8-bit character code and character pattern is described in table 1. when the 8-bit character code of cg rom is written into the dd ram, the character pattern of the corresponding character code of the cg rom is displayed on the lcd position corresponding to the dd ram address. when all of the upper 4 bits of cg rom code are "l", cg rom can be switched to cg ram. db7 db0 adc 00000111 07 C C C 00 80 01 81 02 82 03 83 04 84 05 85 06 86 07 87 08 88 12 34 67 8 9 5 digit cursor and its blinking position 79 80 C C C C C C 4e ce 4f cf 2-line display 12 34 67 8 9 5 digit cursor and its blinking position 4-line display 00 01 02 03 04 05 06 07 08 40 80 c0 41 81 c1 42 82 c2 43 83 c3 44 84 c4 45 85 c5 47 87 c7 46 86 c6 48 88 c8 C C C C C C C C C C C C C C C 39 40 26 27 66 67 a6 a7 e6 e7 note: cursor display and blinking can be performed even when the cg ram address is set in the adc. so, it is necessary to disable the cursor display and blinking when the cg ram address is set in the adc.
? semiconductor MSM6262-xx 24/52 table 1 character code and character pattern of standard code (MSM6262-04)
? semiconductor MSM6262-xx 25/52 9. character generator ram (cg ram) the cg ram is used to display user's original character pattern other than cg rom. the cg ram has capacity (32 bytes = 256 bits) to write 4 kinds of 5 x 8 dots and 2 kinds of 5 x 12 dots. in displaying the character pattern stored in the cg ram, cg ram has to be enabled by an instruction. when cg ram is enabled, cg rom code for 16 characters cannot be read out since the cgrom code with all "l" on the upper 4 bits is used as cg ram code. the following describes how to write character patterns into the cg ram and how to display them on the lcd. (1) when the character pattern is 5 x 8 dots (see table 2-1) ? a method to write character pattern into the cg ram by the cpu the lower 3 bits (0 - 2) of the cg ram address correspond to the line position of the character pattern. the upper 2 bits (3, 4) of the cg ram address correspond to the lower 2 bits (0, 1) of the character code. first, set increment of decrement by the cpu, and then input cg ram address. after this, write character pattern data into cg ram through db0 to db7 line by line. db0 - db7 correspond to cg ram data 0 - 7 in table 2-1. display is turned on when "h" is set as input data and turned off when "l" is set as input data. since the adc is automatically incremented or decremented by 1 after the writing of data to the cg ram, it is not necessary to set the cg ram address again. to enable cursor display, set all input data on the line where the lower 3 bits of the cg ram (0-2) are all "h" to "l". 0 - 4 bits of cg ram data are output to the lcd as the display data; however, 5 - 7 bits of cg ram data are not. but it can be used as the data ram because the data can be written/ read through db0 to db7. ? a method to display the cg ram character pattern to the lcd first, an instruction to enable the cg ram has to be input from the cpu. cg ram is selected only when all of the upper 4 bits of the character code is "l". so, the character pattern of cg ram is displayed on the lcd position that corresponds to the dd ram address, when the character code shown in table 2-1 is written into dd ram. since the bits 2 and 3 of the character code are regarded as invalid, "k" is displayed when the character codes "01", "05", "'09", and "0d" are selected. (2) when the character pattern is 5 x 12 dots (see table 2-2) ? a method to write character pattern into the cg ram by the cpu the lower 4 bits of cg ram address (0 - 3) correspond to the line position of the character pattern. the upper 1 bit of cg ram address bit 4 corresponds to the bit 1 of the character code. first, set increment or decrement by the cpu, and then input cg ram address. after this, write the character pattern data into cg ram through db 0 to db 7 line by line. db 0 - db 7 correspond to cg ram data 0 - 7 in table 2-2. display is turned on when "h" is set as the input data and turned off when "l" is set
? semiconductor MSM6262-xx 26/52 as the input data. since the adc is automatically incremented or decremented by 1 after the writing of data to the cg ram, it is not necessary to set the cg ram address again. to enable cursor display, set all input data on the line where the cg ram address is "0b" or "1b" (hex.) to "l". the addresses "0" to "b" (hexadecimal) in the bits 0 to 4 of the cg ram data are output on the lcd as the display data. however, the addresses "c" to "f" (hexadecimal) in the bits 0 to 4, and 5 to 7 of the cg ram data are not output on the lcd. but these cg ram data can be used as the data ram so that they can be written into or read out through db0 to db7. ? a method to display the cg ram character pattern on the lcd first, an instruction to enable the cg ram has to be input from the cpu. cg ram is selected only when all of the upper 4 bits of the character code is "l". so, the character pattern of cg ram is displayed on the lcd position corresponding to the dd ram address, when the character code shown in table 2-2 is written into the dd ram. since bits 0, 2 and 3 of the character code are regarded as invalid, the character of " m " is displayed when the character codes "00", "01", "04", "05", "08", "09", "0c" and "0d" are selected. (3) a method to read out the cg ram data first, set the cg ram address by inputting a cg ram address set instruction from the cpu. then, execute the cg ram/dd ram data read instruction. the set data of cg ram address is output from the db0 to db7. the 8-bit data, read out from the MSM6262-xx, corresponds to the data which is written into the cg ram. since the cg ram address is automatically incremented or decremented by 1, the cg ram read out instruction c a n be successfully input. it is necessary, however, to set the dd ram at data transferring condition by executing the dd ram address set instruction after all of cg ram data are read out.
? semiconductor MSM6262-xx 27/52 cg ram data (character pattern ) dd ram data cg ram address (character code ) 7 6 5 4 3 2 1 0 l l l l l 7 6 5 4 3 2 1 0 lsb msb lsb msb lsb l l l h h h h x x x l h h h l h h l l l l x x l l h h l l 4 3 2 1 0 h l h l l l l l l h h h h x x x h l l l h l l l l x x l h h h l l l l l l h h h h x x x l h h h l l l l l x x h h x: don't care l h hl h h l l l h h l hh lh hl hh l l lh hl hh l h h l l h h h l h l h l h l l h l l l h l l l h l l l h l l l h l h h l h l l l l h h h h h l h l h l l l l l h h l l l l l l h l h l l l l l l l l l h l l l l l l l l l l h l l l h l l l h l l l h l l l h h h h l l l l l table 2-1 relation between cg ram data (character pattern) vs. cgram address and ddram data vs. character pattern when the character pattern is 5 8 dots.
? semiconductor MSM6262-xx 28/52 table 2-2 relation between cgram data (character pattern) vs. cgram address and ddram data vs. character pattern when the character pattern is 5 12 dots. 7 6 5 4 3 2 1 0 l 7 6 5 4 3 2 1 0 lsb msb lsb msb lsb l l l h h h h x x x l l l l l 4 3 2 1 0 l l l l l h h h h l l l h h h h x x x l l l l x x h x: don't care l h hl h h l l l h h l hh ll lh hl h h ll lh hl l h h l l h h h l h l h l h l l l l l l l l h l l l h h h h l h l l h h h h hh l l h l l l h h h h l h l l l l l l l l l l l l l h h l l l l l l l l l l l l l l l l l l l l h l l l l h h l l h hhh l l l l l h l h l l l h l l l h h l l l l l l l l h h l l l l l h h h h l l h h l h l h x x x x x l l l l l l l h h h h h h h h l l l l l l l h h h h h h h h l l l l l l l l l lll l l l l l l x l l l l x x l x cg ram data (character pattern) dd ram data cg ram address ( character code) h x x x x x b b
? semiconductor MSM6262-xx 29/52 9. lcd display circuit (com1 to com48, do, cp, load, df) the MSM6262-xx is provided with common signal output. so, maximum 160 characters can be displayed when it is used together with segment drivers (msm5259 or msm5839c). interface between MSM6262-xx and segment drivers can be done by using do, cp, load and df. the segment data is serially output from do pin, synchronized with the pulse which is output from the cp pin. this data, input to the segment driver, is converted from serial data to parallel data by the latch pulse which is output from the load pin of MSM6262-xx and this converted data is used as the display data. this parallel/serial conversion is performed synchronized with the common signal of MSM6262-xx and lcd display ac signal which is output from df pin. so, this signal can drive dot matrix lcd panel. 10. reset circuit power-on-reset is required for MSM6262-xx when it is powered-on. so, a capacitor has to be connected between reset pin and v ss pin. it is also advisable to connect a diode between reset pin and v dd pin when it is required to connect a capacitor of more than 3.3 m f to reset pin. when the power-on reset circuit normally operates, the busy flags 1 and 2 become at "h" level for about 10 ms after the power-on. during this period, a initialization of MSM6262-xx is performed by following procedures. 1 display is cleared 2 cg rom becomes enabled 3 no display shift 4 adc is incremented 5 2-line display mode 6 5 x 8 dots font configuration 7 no display shift for "g", "j", "p", "q" and "y" 8 display off 9 no display of cursor, blinking and underline 11. data bus with cpu MSM6262-xx can be interfaced with 8-bit cpu, such as 6809, z80, 80c49 and 80c51. when MSM6262-xx is connected with 6809, the 68 series/80 series pin has to be connected to v dd . when MSM6262-xx is connected with z80, 80c49 or 80c51, the 68 series/80 series pin has to be connected to v ss . the level at 68 series/80 series cannot be switched during MSM6262-xx's operation. it must be connected with either v dd or v ss before MSM6262-xx is turned on. note: it is possible, indeed, to change the 68 series/ 80 series pin's level when a reset signal is being input to reset pin. however, the 68 series /80 series pin does not have characteristics to have an interface with mcu, nor does it have an antichattering circuit. further, if a reset signal is input, the MSM6262-xx is initialized as described above. so, in this case, changing the 68 series/80 series pin level is not recommended.
? semiconductor MSM6262-xx 30/52 80 series cpu data transfer e ( rd ) r/w ( wr ) a 1 a 0 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 busy1 (internal operation) busy2 (internal operation) write an instruction (ir) read the busy flag * : don't care write the data register (rd) ir 7 ir 6 ir 5 ir 4 ir 3 ir 2 ir 1 ir 0 busy1 busy2 * * * * * * no busy1 no busy2 cg/dd i/d s a/o d ud dr 7 dr 6 dr 5 dr 4 dr 3 dr 2 dr 1 dr 0
? semiconductor MSM6262-xx 31/52 68 series cpu data transfer a 1 a 0 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 busy1 (internal operation) busy2 (internal operation) write an instruction (ir) read the busy flag * : don't care write the data register (rd) ir 7 ir 6 ir 5 ir 4 ir 3 ir 2 ir 1 ir 0 busy1 busy2 * * * * * * no busy1 no busy2 cg/dd i/d s a/o d ud dr 7 dr 6 dr 5 dr 4 dr 3 dr 2 dr 1 dr 0 e ( rd ) r/w ( wr )
? semiconductor MSM6262-xx 32/52 instruction table 80series cpu 68series cpu note 1 r/w a 1 a 0 db 0 explanation execution time (max), when fosc = 500khz db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 a 1 a 0 display clear return under line entry mode set display/cursor shift cg ram address set function set display control cg ram/dd ram data write dd ram address set read the underlined data read the cg ram/ dd ram data read the address counter content read busy flag l l l l l l l l l l h h h h l l l l l l l l l h l l h h l l l l l l l l h l l h l h l l l l l l l h uld b1f l l l l l l h d b2f cg/ dd i/d s a/o d ud l l l l l h n c l l l l h * b l l l h s/c f 1 uc l l h i/d ud/ rl f 2 ub l h ul s d 2 ur/ dl f 3 * h cr/c * a/o d 1 ( ) * * * 3.22 ms 1.62 ms 20 m s 20 m s 20 m s 20 m s 20 m s 20 m s 20 m s 20 m s 20 m s 20 m s 0 m s 0 m s when fosc = 600 khz, execution time becomes 20 m s CCCC = 16.7 m s 500 600 * : don't care note 1: in the case of 80 series cpu , access to MSM6262-xx is done b y wr and rd . so , a bit for p art of the read/write code is not re q uired. clears all of the display. and sets address 0 of dd ram in the address counter. cr/c = l: cursor home cr/c = h: carriage return ul = h: writes the underline in the cursor part before executing this instruction. ul = l : erases the underline in the cursor part before executing this instruction. sets whether the display of the direction of cursor (i/d) move should be shifted or not. when the data is being written or read, this operation is performed. this instruction also sets whether the character code of dd ram is used as cg rom or cg ram.(a/o) shifts the cursor and display without changing the dd ram contents. (s/c, ud/rl,ur/dl) the line to be displayed in the uppermost position can be set. sets the cg ram address. the dara, which will be sent/received after the cg ram address is set, is cg ram data. a cg write data a dd read data read data a dc sets the following: no. of display digits (n), character font (f 1 ), cursor line font (f 2 ), font shift of "g, j, p, q, y" (f 3 ) sets the following: all display on/off (d), cursor display on/off (c), character on the cursor position blink on/off (b), underline display on/off (uc), character, on the underline, blink on/off (ub) writes a data in either dd ram or cg ram. sets dd ram address. the data which is sent/received after that is dd ram data. reads following data: data on the underline, dd ram or cg from ram data. reads the data either from dd ram or from cg ram. reads the address counter contents. busy 1 flag (b1f) shows that MSM6262-xx's internal operation is going on. busy 2 flag (b2f) shows that the revising of display starting line is going on. cg/dd shows whether the data, being transmitted or received, is of cg ram or dd ram. i/d shows the direction in which cursor moves. s shows the display shift. a/o shows that the dd ram character code is cg ram character code or cg ram character code. d shows the all display on/off. ud shows underline display on/off. cr/c = h ul = h i/d = h s = h a/o = l s/c = h ud/rl = h d 2 ,d 1 ur/dl = h n = l n = h f 1 = h f 2 = l f 3 = h uld = h b1f = h b2f = h cg/dd = h : : : : : : : : : : : : : : : : : : carriage return write underline increment accompany display shift cg rom enable display move up/down move the bit to set the line to be displayed in the uppermost position. d 1 is lsb. d 2 is msb. upper-right move 2 lines 4 lines 5 x 11 dots 5 x 12 dots or 5 x 8 dots shift "g, j, p, q, y" to the lower position by 1 dot. underline data exists internal operation going on revising the display starting line or internal operation going on transmit /receive cg ram data cr/c = l ul = l i/d = l a/o = h s/c = l ud/rl = l ur/dl = l f 1 = l f 2 = h f 3 = l uld = l b1f = l b2f = l cg/dd = l : : : : : : : : : : : : : : : cursor home underline erase decrement cg ram enable cursor move left/right move down-left move 5 x 7 dots 5 x 11 dots or 5 x 7 dots disable character shift no underline data ready to receive instruction no revision on display starting line transmit/receive of dd ram data dd ram cg ram a cg a dd a dc : : : : : display data ram character generator ram cg ram address dd ram address address counter which is used for both dd ram and cg ram ( )
? semiconductor MSM6262-xx 33/52 when this instruction is executed, cursor and blinking position moves to the left end of the lcd. (in the case of 2-line or 4-line display mode, it moves to the left end of the first line.) when display is being shifted, the display returns to its original position for both horizontally and vertically. adc becomes "00" (hex.). ? cr/c = h (carriage return) when this instruction is executed, cursor and blinking position moves to the left end of the line on which the cursor and brink were positioned before execution of instruction. if the display is being shifted when this instruction was executed, the cursor and blinking position moves to the original position before it was shifted only concerning to the shift to the right and left. all bits other than line specifying bit of adc will be reset to "0" (hex.). instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 llllllll l h instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 llllllll hcr/c 12. instruction code the instruction code is defined as the signal through which the MSM6262-xx is accessed by the cpu. MSM6262-xx starts its operation upon receipt of the instruction code. the internal processing operation starts with a timing that does not affect the lcd display, so, the busy condition is longer than that of cycle time. in the busy condition, MSM6262-xx does not execute any instruction other than the reading of busy flag. therefore, make certain that busy flag is set at "l" before inputting the instruc- tion code. (1) display clear when this instruction is executed, the lcd display is cleared. when cursor display and/or character blink is being performed, their display position moves to the left end of the lcd. (in the case of 2-line or 4-line display mode, it moves to the left end of the first line.) all of the dd ram data becomes "20" (hex), while adc data becomes "00" (hex.). if the display is on a shifted position, it returns to the original position. data for underline is re-written as "l" and display turns off. (2) return ? cr/c = l (cursor home)
? semiconductor MSM6262-xx 34/52 ? i/d (increment/decrement) when this instruction is executed, dd ram address will be incremented (i/d = "h") or decremented (i/d = "l") by 1, after the character code or underline code is written into (or read out from) the dd ram. in the case of increment, cursor moves to the right, while the cursor moves to the left in the case of decrement. processing for writing/reading the data into/from cg ram is performed the same way. ? s (display shift upon writing) when s = "h" and data is written into dd ram, display is shifted either to the right or left. when i/d = "h", the whole display shifts to the left, while it shifts to the right when i/d = "l". so, display of cursor looks being stopped and display itself looks being shifted. in the case of reading the data from dd ram, display is not shifted. also in the case of reading/writing the data from/to cg ram, display shall not be shifted. when s = "l", display is not be shifted. ? a/o (cg ram enable/cg rom enable) when a/o is "l", cg rom will be enabled, and all cg rom contets on table 2 becomes selectable and cg ram cannot be selected. cg ram cannot be used as character code for display. but it can be used as data ram. when a/o = "h", cg ram is enabled. when the upper 4 bits of the character code in table 1 are "00" (hex.), the bit pattern of cg ram is displayed on the lcd. (cg ram has a ram area for 4 kinds of 5 x 8 dots and 2 kinds of 5 x 12 dots) cg rom is selected when the upper 4 bits of the character code in table 1 are "01" - "0f" (hex.). instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 lllllllhul * *: don't care instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 l l l l l l h i/d s a/o (3) underline ? ul = h (write underline) when this instruction is executed, the underline appears on the cursor position. cursor will move to the right or left if either increment or decrement is specified. ? ul = l (erase underline) when this instruction is executed, the underline on the cursor position disappears. cursor will move to the right or left if either increment or decrement is specified. when this instruction is executed, adc will be automatically incremented by +1 or decremented by C1. display is shifted accordingly. (4) entry mode set
? semiconductor MSM6262-xx 35/52 ? s/c (display move/cursor move) this is the bit to select either display or cursor to move. s/c = "h" enables the display movement, while s/c = "l" enables the cursor movement. ? ud/rl (upward or downward move/right or left move) ud/rl = "h" enables upward or downward move. ud/rl = "l" enables right or left move. ?d 2 , d 1 (starting line of display) upward or downward movement is enabled by setting the starting line of display. d 1 is lsb and d 2 is msb. both d 1 and d 2 are expressed in 2-bit binary data. only d 1 is valid in 2-line mode. both d 1 and d 2 are valid in 4-line mode. instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 lllllhs/c ud/ rl d 1 ( ) * d 2 (ur/ dl) *: don't care dd ram display of the lcd 1st line 2nd line 1st line 2nd line 1st line 2nd line 1st line 2nd line d 2 = * , d 1 = "l" d 2 = * , d 1 = "h" [ 2-line mode ] * : don't care (5) display/cursor move
? semiconductor MSM6262-xx 36/52 [ 4-line mode ] dd ram d 2 = "l", d 1 = "l" display of the lcd 1st line 2nd line 3rd line 4th line 1st line 2nd line 3rd line 4th line d 2 = "l", d 1 = "h" 1st line 2nd line 3rd line 4th line 1st line 2nd line 3rd line 4th line d 2 = "h", d 1 = "l" 1st line 2nd line 3rd line 4th line 1st line 2nd line 3rd line 4th line d 2 = "h", d 1 = "h" 1st line 2nd line 3rd line 4th line 1st line 2nd line 3rd line 4th line
? semiconductor MSM6262-xx 37/52 (6) cg ram address set s/c ud/ explanation rl d 1 * l l l l h h h h h h ll* l h h l l h h h h h l h l h l l h h * * * * * l h l h move the cursor to the left by 1 digit move the cursor to the right by 1 digit move the cursor downward by 1 digit move the cursor upward by 1 digit move the display to the left by 1 digit move the display to the right by 1 digit set the first line as the display starting line set the 2nd line as the display starting line set the 3rd line as the display starting line s set the 4th line as the display starting line s s : invalid in 2-line mode l lllhac 4 ac 3 ac 2 ac 1 ac 0 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 a 0 a 1 instruction code d 2 (ur/ dr) * : don't care ? ur/dl (up-right move/down-left move) ur/dl = "h" enables up-right movement. ur/dl = "l" enables down-left movement. combination of bit for display/cursor movement is as follwes set the cg ram address which consists of 5 bits of ac 4 - ac 0 . the data which will be transferred after this instruction is set will be limited to the cg ram data (character font data).
? semiconductor MSM6262-xx 38/52 ?f 1 (5 x 11 dots/5 x 7 dots) when f 1 = "h", 5 x 12-dot font is selected. when f 1 = "l", 5 x 8-dot font is selected. ?f 2 (font assignment of cursor line) when f 2 = "l" and if character code, which has a display dot on the cursor position, is selected, it is displayed on the cursor line of lcd. when f 2 = "h" and if character code, which has a display dot on the cursor position, is selected, cursor is displayed but the bit on the cursor position is not displayed. however, this function does not apply to cg ram and the bit on the cursor position is also displayed. ?f 3 (character shift of "g, j, p, q, y") when f 3 = "h", each character of "g, j, p, q, y" is displayed shifted downward by 1 dot for the whole character. when f 3 = "l", display of these characters is the same as other characters, as shown in table 1. this bit is valid only for 5 x 12-dot font. example l llhn f 1 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 a 0 a 1 instruction code f 2 f 3 * * *: don't care n l h lcd lines 2-line mode 4-line mode (7) function set ? n (selection of lcd lines to be displayed) 5 x 7-dot font rom 5 x 11- or 5 x 12-dot font rom 3 dots 7 dots 1 or 2 dots not displayed cursor cursor position q f 1 = "l" (5 x 8-dot/font)
? semiconductor MSM6262-xx 39/52 5 x 7-dot font rom 5 x 11-dot font rom 3 dots (1 dot) cursor p osition 5 x 12-dot font rom 1 dot 7 dots w f 1 = "h" (5 x 12-dot/font) cursor position cursor position shifted downward by 1 dot y f 3 = "h" (5 x 12-dot font only) t f 3 = "l" r f 2 = "l" e f 2 = "h"
? semiconductor MSM6262-xx 40/52 instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 l l h d c b uc ub * * *: don't care ? d (all display on/off) when d = "h", display on the lcd is enabled. when d = "l", display is disabled. when display was disabled by setting d at "l", character code in the dd ram does not change. so, when d becomes "h" again, display is enabled immediately. ? c (cursor display on/off) c = "h", cursor display appears. when c = "l", cursor display disappears. ? b (cursor blinking) when b = "h", blinking of character on the position corresponding to the cursor position, starts. blinking of all-dot's-on and character (and cursor)-on is performed alternately for every 409.6 ms in case of fosc = 500 khz and 5 x 8 dots font configuration (every 614.4 ms in case of 5 x 12 dots font configuration) when b = "l", blinking stops. cursor and blinking can be set together. ? uc (underline display) when uc = "h", underline is displayed on the cursor position. when uc = "l", underline display is disabled. ? ub (underlined character blinking) when ub = "h", blinking of character on the position corresponding to the underline position, starts. blinking of character stops when ub = "l". cursor, blink, underline, and blinking of character on the underline can be set together. (9) cg ram and dd ram data write (8) display control instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 lhd i 7 d i 6 d i 5 d i 4 d i 3 d i 2 d i 1 d i 0 write the 8-bit data (d i 7 - d i 0 ) into either cg ram or dd ram. determination of either cg ram or dd ram is made by the previously set cc ram or dd ram address set. after the data is written into the ram, it is incremented or decremented by 1 according to the entry mode of the address. display shift is also determined by the entry mode.
? semiconductor MSM6262-xx 41/52 this instruction reads underline data, and cg ram or dd ram data. determination of cg ram or dd ram is made by the previously set cg ram or dd ram address set. the first data read by this instruction is an invalied data. normal data is read out from the second instruction onward if the read instruction is executed continuously. this instruction address will be incremented or decremented by 1 according to the entry mode. display shift is, however, not performed. underline data is output to db7 as either "h" (when display is on) or "l" (when display is off). the msb of ram data is not read. ram data consists of 7 bits (db0 to db6). instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 ll d 0 6 d 0 5 d 0 4 d 0 3 d 0 2 d 0 1 d 0 0 uld instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 hla i 7 a i 6 a i 5 a i 4 a i 3 a i 2 a i 1 a i 0 (10) dd ram address set this instruction code sets the dd ram address, which consists of 8 bits (a i7 to a i0 ). the data which is received after this instruction is set is limited to the dd ram data (character code data). do not input any address code other than those below. 2-line mode : 1st line 00 - 4f 2nd line 80 - cf 4-line mode : 1st line 00 - 27 2nd line 40 - 67 3rd line 80 - a7 4th line c0 - e7 (11) underline data read
? semiconductor MSM6262-xx 42/52 ? b1f (busy 1 flag) when b1f = "h", MSM6262-xx is engaged in internal operation and next instruction is not accepted until when b1f becomes "l". so, subsequent instruction has to be input after b1f is confirmed at "l". during b1f = "h", db 5 to db 0 are undefined. ? b2f (busy 2 flag) b2f indicates that MSM6262-xx is engaged in its internal operation and it also indicates that the display starting line is under being revised. instruction contents of b1f and b2f are the same except when setting the starting line of display. b2f = "h" indicates that MSM6262-xx is engaged in its internal operation. b2f = "l" indicates that mam6262-xx is ready for accepting new instruction. even when b2f = "h", new instruction can be accepted if b1f = "l". however, if the starting line of display is revised under this condition, the previous set data about starting line of display becomes invalid and the newly input data about starting line becomes valid. instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 lh d 0 6 d 0 5 d 0 4 d 0 3 d 0 2 d 0 1 d 0 0 d 0 7 instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 hl a 0 6 a 0 5 a 0 4 a 0 3 a 0 2 a 0 1 a 0 0 a 0 7 instruction code a 1 a 0 db 7 db 6 db 5 db 3 db 2 db 1 db 0 db 4 h h b1f cg/ b2f dd i/d s a/o d ud (12) cg ram and dd ram data read this instruction reads the 8-bit data (d o 7 to d o 0 ) from either cg ram or dd ram. determination of cg ram or dd ram is made by the previously set cg ram or dd ram address set. the cg ram address set instruction or dd ram address set instruction has to be input just before executing this read instruction. if it is not input, the first output of the data becomes invalid. when this read instruction is performed continuously, normal data is output from the 2nd data onward. in the case of dd ram data read, normal data is output from the first data even if the address set is not input, provided that cursor is moved by the cursor shift instruction. after reading the data, the address is incremented or decremented by 1 by the entry mode. the shift of the display, however, is not performed. (13) address counter read this instruction reads the 8-bit data (a o 7 to a o 0 ) . address counter is determined by the previously set address set because it is used for both cg ram and dd ram. (14) busy flag read
? semiconductor MSM6262-xx 43/52 ? cg/dd (cg ram/dd ram) this bit indicates whether the address counter contents are cg ram or dd ram when b1f = "l". it indicates that cg ram data has been selected when cg/dd = "h" and that dd ram data has been selected when cg/dd = "l". ? i/d (increment/decrement) this bit indicates which has been set in the entry mode set, increment or decrement, when b1f = "l". it indicates that increment has been set when i/d = "h" and that decrement has been set when i/d = "l". ? s (shift) this bit reads the shift condition in the entry mode when b1f = "l". it indicates that shift is set when s = "h" and shift is disabled when s = "l". ? a/o (cg ram enable/cg rom enable) this bit indicates which has been selected in the entry mode, cg rom or cg ram, when bif = "l". it indicates the cg rom selected state when a/o = "l" and cg ram selected state when a/o = "h". ? d (display) this bit indicates which has been set by display control instruction, lcd display on or off, when b1f = "l". it indicates that the display is on when d = "h" and the display is off when d = "l". ? ud (underline) this is the bit to indicate the condition of underline or blinking on the underline, both of which were set by display control instruction, when b1f = "l". when ud = "h", either (or both of) underline display or blinking on the underline is being executed. when ud = "l", it indicates neither of underline display nor blinking on the underline is performed.
? semiconductor MSM6262-xx 44/52 application circuits lcd o 1 o 40 di 1 cp load df do 20 di 21 msm5259 o 1 o 40 di 1 cp load df do 20 di 21 msm5259 do 40 df load cp do com48 com17 com16 com1 MSM6262-xx 1 2-line display mode 5 x 7 dots, 2 lines 16 characters (note: com17 - com48 should be left open)
? semiconductor MSM6262-xx 45/52 lcd o 1 o 40 di 1 cp load df do 20 di 21 msm5259 o 1 o 40 di 1 cp load df do 20 di 21 msm5259 do 40 df load cp do com48 com25 com24 com1 MSM6262-xx 2 2-line display mode 5 x 11 dots, 2 lines 16 characters (note: com25 - com48 should be left open) underline cursor
? semiconductor MSM6262-xx 46/52 lcd o 1 o 40 di 1 cp load df do 20 di 21 msm5839c o 1 o 40 di 1 cp load df do 20 di 21 msm5839c do 40 df load cp do com48 com33 com32 com1 MSM6262-xx 3 4-line display mode 5 x 7 dots, 4 lines 16 characters (note: com33 - com48 should be left open)
? semiconductor MSM6262-xx 47/52 lcd o 1 o 40 di 1 cp load df do 20 di 21 msm5839c o 1 o 40 di 1 cp load df do 20 di 21 msm5839c do 40 df load cp do com48 com1 MSM6262-xx 4 4-line display mode 5 x 11 dots, 4 lines 16 characters
? semiconductor MSM6262-xx 48/52 ? example of connection with msm5839c and bias circuit di 1 o 1 ~ o 40 do 40 msm5839c cp load df v dd v ss di 21 do 20 di 1 o 1 ~ o 40 do 40 msm5839c cp load df v dd v ss di 21 do 20 di 1 o 1 ~ o 40 do 40 msm5839c cp load df v dd v ss v 3 v ee di 21 do 20 lcd MSM6262-xx com1 com48 do cp load df v dd v ss v 1 v 4 v 5 0 v 5 v C5 v c c c c c c c r r 4r r r vr r v 2 v 3 v ee v 2 v 3 v ee v 2 v 3 v ee v 2
? semiconductor MSM6262-xx 49/52 ? example of bias circuit v dd v 1 v 4 v 5 MSM6262-xx r r rr r r vr r v lcd v 2 v 3 v ee to segment driver 1/5 - 1/8 bias example 2. bias rr 1/5 1/6 1/7 1/8 r 2r3r4r v lcd : lcd driving voltage v dd v 1 v 4 v 5 MSM6262-xx r r rr r r vr r v lcd v 2 v 3 v ee to segment driver c c c c c c c 1/5 - 1/8 bias example 1. bias rr 1/5 1/6 1/7 1/8 r 2r3r4r v lcd : lcd driving voltage
? semiconductor MSM6262-xx 50/52 ? lcd duty and bias no. of lines 2 lines 4 lines duty bias 1/16 1/24 1/32 1/48 1/5 1/6 1/7 1/8 above are examples of relation between lcd duty and bias. use these values for reference, for they vary depending on the characteristics of lcd panel. the value of resistor on bias circuit is determined by the operational margin and power consumption. to make the power consumption lower, the value of resistor has to be larger, but it makes the lcd driving output impedance high and causes the distortion on the lcd driving waveform. if a large lcd panel is used, the value of the resistor should be much lower because the lcd capacitance increases. connecting a bypass capacitor to the bias resistor in parallel can improve the distortion of lcd driving waveform. however, connecting a capacitor of too large value may cause a level shift of the bias voltage. so, it has to be determined carefully after checking experimentally. followings are the reference values. r = 2 to 10 k w v r = 10 to 50 k w r = 0.2 to 2 k w c = 0.0022 to 0.047 m f
? semiconductor MSM6262-xx 51/52 ? lcd driving waveform (at 1/5 to 1/8 bias) selecting a segment driver ic v dd v 1 v 2 v 3 v 4 v 5 com1 12 12 12 v dd v 1 v 2 v 3 v 4 v 5 com2 v dd v 1 v 2 v 3 v 4 v 5 seg lighting waveform duty 1/16 1/24 1/32 1/48 frame frequency 78.125 hz 52.08 hz 78.125 hz 52.08 hz df 1 frame note: f osc = 500 khz when v lcd is within the voltage range of v dd and that of v ss , msm5259 is recommendable as segment driver. when v lcd is beyond the voltage range of v dd and that of v ss , msm5839c or msm5260 is recommendable as segment driver.
? semiconductor MSM6262-xx 52/52 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.27 typ. mirror finish

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