1 ps8135b 11/06/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch16652 16-bit bus transceiver and register with 3-state outputs product description pericom semiconductor?s pi74alvch series of logic circuits are produced in the company?s advanced 0.5 micron cmos technology, achieving industry leading speed. the pi74alvch16652 is a 16-bit bus transceiver and register designed for low 2.3v to 3.6v vcc operation. it consists of d-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. the device can be used as two 8-bit transceivers or one 16- bit transceiver. complementary output enable (oeab and oeba) inputs are provided to control the transceiver functions. select control (sab and sba) inputs are provided to select whether real-time or stored data is transferred. a low input level selects real-time data, and a high input level selects stored data. circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. data on the a or b bus, or both, can be stored in the internal d flip- flops by low-to-high transitions at the appropriate clock (clkab or clkba) inputs regardless of the levels on the select control or output enable inputs. when sab and sba are in the real-time transfer mode, it also is possible to store data without using the internal d-type flip-lops by simultaneously enabling oeab and oeba. in this configuration, each output reinforces its input. thus, when all other data sources to the two sets of bus lines are in the high- impedance state, each set of bus lines remains at its last level configuration. active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. to ensure the high-impedance state during power up or power down, oeba should be tied to vcc through a pull-up resistor and oeab should be tied to gnd through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking current sourcing capability of the driver. product features pi74alvch16652 is designed for low voltage operation v cc = 2.3v to 3.6v hysteresis on all inputs typical v olp (output ground bounce) < 0.8v at v cc = 3.3v, t a = 25c typical v ohv (output v oh undershoot) < 2.0v at v cc = 3.3v, t a = 25c bus hold retains last active bus state during 3-state, eliminating the need for external pullup resistors industrial operation at ?40c to +85c packages available: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 300 mil wide plastic ssop (v) product pin configuration 1 oeab 1 1 clkab 2 1 sab 3 gnd 4 1 a 1 5 1 a 2 6 v cc 7 1 a 3 8 1 a 4 9 1 a 5 10 gnd 11 1 a 6 12 1 a 7 13 1 a 8 14 2 a 1 15 2 a 2 16 2 a 3 17 gnd 18 2 a 4 19 2 a 5 20 2 a 6 21 v cc 22 2 a 7 23 2 a 8 24 1 oeba 56 1 clkba 55 1 sba 54 gnd 53 1 b 1 52 1 b 2 51 v cc 50 1 b 3 49 1 b 4 48 1 b 5 47 gnd 46 1 b 6 45 1 b 7 44 1 b 8 43 2 b 1 42 2 b 2 41 2 b 3 40 gnd 39 2 b 4 38 2 b 5 37 2 b 6 36 v cc 35 2 b 7 34 2 b 8 33 gnd 25 2 sab 26 2 clkab 27 2 oeab 28 gnd 32 2 sba 31 2 clkba 30 2 oeba 29 56-pin a,v
2 ps8135b 11/06/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch16652 3.3v 20-bit flip-flop with 3-state outputs logic block diagrams 1oeba c1 1d to seven other channels 1oeab 1clkba 56 1 55 1sba 1clkab 1sab 54 2 3 5 1a1 c1 1d 52 1b1 one of eight channels 2oeba c1 1d to seven other channels 2oeab 2clkba 29 28 30 2sba 2clkab 2sab 31 27 26 15 2a1 c1 1d 42 2b1 one of eight channels
3 ps8135b 11/06/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch16652 3.3v 20-bit flip-flop with 3-state outputs product pin description notes: 1. h = high voltage level, x = don?t care, l = low voltage level, - = low-to-high transition * the data output functions may be enabled or disabled by a varietyof level combinations at the oeab or oeba inputs. data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to -high transition on the clock inputs. ** select control = l; clocks can occur simultaneously. select control = h; to load both registers, clocks must be staggered. s t u p n i* o / i a t a d n o i t c n u f r o n o i t a r e p o b a e oa b e ob a k l ca b k l cb a sa b s8 a - 1 a8 b - 1 b lh l r o hl r o hxx t u p n it u p n in o i t a l o s i lh -- xx t u p n it u p n ia t a d b d n a a e r o t s xh - l r o hxx t u p n i* * d e i f i c e p s n ub d l o h , a e r o t s hh -- * * xx t u p n it u p t u os r e t s i g e r h t o b n i a e r o t s lx l r o h - xx * * d e i f i c e p s n ut u p n ib e r o t s , a d l o h ll -- x* * xt u p t u ot u p n is r e t s i g e r h t o b n i b e r o t s ll x xxl t u p t u ot u p n is u b a o t a t a d b e m i t - l a e r ll x l r o hxh t u p t u ot u p n is u b a o t a t a d b d e r o t s hh x x lx t u p n it u p t u os u b b o t a t a d a e m i t - l a e r hh l r o hxhx t u p n it u p t u os u b b o t a t a d a d e r o t s hl l r o hl r o hhh t u p t u ot u p t u os u b a o t a t a d b d e r o t s & s u b b o t a t a d a d e r o t s e m a n n i pn o i t p i r c s e d b a e o) h g i h e v i t c a ( s t u p n i e l b a n e t u p t u o a b e o) w o l e v i t c a ( s t u p n i e l b a n e t u p t u o a b k l c x , b a k l c xs t u p n i e s l u p k c o l c a b s x , b a s xs t u p n i l o r t n o c t c e l e s x a xs t u p t u o b r e t s i g e r a t a d , s t u p n i a r e t s i g e r a t a d x b xs t u p t u o a r e t s i g e r a t a d , s t u p n i b r e t s i g e r a t a d d n gd n u o r g v cc r e w o p truth table ( 1)
4 ps8135b 11/06/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch16652 3.3v 20-bit flip-flop with 3-state outputs real-time transfer bus b to a oeab oeba xclkab xclkba xsab xsba llxxxl real-time transfer bus a to b oeab oeba xclkab xclkba xsab xsba hh x x l x storage from a and/or b transfer stored data to a and/or b oeab oeba xclkab xclkba xsab xsba xh - xxx lx x - xx lh -- xx oeab oeba xclkab xclkba xsab xsba h l h or l h or l h x bus a bus b bus a bus b bus a bus b bus a bus b note: 1. cannot transfer data to a bus and b bus simultaneously.
5 ps8135b 11/06/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch16652 3.3v 20-bit flip-flop with 3-state outputs storage temperature ................................................. ?65c to +150c ambient temperature with power applied ................. ?40c to +85c input voltage range, v in ............................................ ?0.5v to v cc +0.5v output voltage range, v out ..................................... ?0.5v to v cc +0.5v dc input voltage .......................................................... ?0.5v to +5.0v dc output current ................................................................... 100 ma power dissipation ........................................................................ 1.0w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 3.3v 10%) maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t ) 1 ( . n i m. p y t ) 2 ( . x a ms t i n u v c c e g a t l o v y l p p u s3 . 26 . 3 v v h i ) 3 ( e g a t l o v h g i h t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 7 . 2 =0 . 2 v l i ) 3 ( e g a t l o v w o l t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 7 . 2 =8 . 0 v n i ) 3 ( e g a t l o v t u p n i0v c c v t u o ) 3 ( e g a t l o v t u p t u o0v c c v h o e g a t l o v h g i h t u p t u o i h o 0 0 1 - = m v , a c c =. x a m o t . n i mv c c ?2 . 0 v h i i , v 7 . 1 = h o =?6 v , a m c c =v 3 . 20 . 2 v h i i , v 7 . 1 = h o =? 2 1v , a m c c =v 3 . 27 . 1 v h i i , v 0 . 2 = h o =? 2 1v , a m c c =v 7 . 22 . 2 v h i i , v 0 . 2 = h o =? 2 1v , a m c c =v 0 . 34 . 2 v h i i , v 0 . 2 = h o =? 4 2v , a m c c =v 0 . 30 . 2 v l o t u p t u o w o l e g a t l o v i l o 0 0 1 = m v , a l i =. x a m o t . n i m2 . 0 v l i i , v 7 . 0 = l o 6 =v , a m c c =v 3 . 24 . 0 v l i i , v 7 . 0 = l o 2 1 =v , a m c c =v 3 . 27 . 0 v l i i , v 8 . 0 = l o 2 1 =v , a m c c =v 7 . 24 . 0 v l i i , v 8 . 0 = l o 4 2 =v , a m c c =v 0 . 35 5 . 0 i h o ) 3 ( t u p t u o h g i h t n e r r u c v c c v 3 . 2 =2 1 - a m v c c v 7 . 2 =2 1 - v c c v 0 . 3 =4 2 - i l o ) 3 ( t u p t u o w o l t n e r r u c v c c v 3 . 2 =2 1 v c c v 7 . 2 =2 1 v c c v 0 . 3 =4 2
6 ps8135b 11/06/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch16652 3.3v 20-bit flip-flop with 3-state outputs notes: 1. for max or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 3.3v, +25c ambient and maximum loading. 3. unused control inputs must be held high or low to prevent them from floating. dc electrical characteristics- continued (over the operating range, t a = ?40c to +85c, v cc = 3.3v 10%) s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t ) 1 ( . n i m. p y t ) 2 ( . x a ms t i n u i n i t n e r r u c t u p n iv n i v = c c v , d n g r o c c v 6 . 3 =5 m a i n i ( hold )t n e r r u c d l o h t u p n i v n i v , v 7 . 0 = c c v 3 . 2 =5 4 v n i v , v 7 . 1 = c c v 3 . 2 =5 4 ? v n i v , v 8 . 0 = c c v 0 . 3 =5 7 v n i v , v 0 . 2 = c c v 0 . 3 =5 7 ? v n i 0 =o tv , v 6 . 3 c c v 6 . 3 =0 0 5 i z o ) s t u p t u o e t a t s - 3 ( t n e r r u c t u p t u ov t u o v = c c r o, d n gv c c v 6 . 3 =0 1 i c c t n e r r u c y l p p u s v c c =v 6 . 3i , t u o 0 = m , a v n i v r o d n g = c c 0 4 d i c c t u p n i r e p t n e r r u c y l p p u s h g i h l t t @ v c c v 0 . 3 =o t6 . 3v v t a t u p n i e n o c c -v 6 . 0 v t a s t u p n i r e h t o c c d n g r o 0 5 7 c i s t u p n i l o r t n o cv n i v = c c v , d n g r o c c v 3 . 3 =5 . 3 f p c o i s t r o p b r o av o v = c c v , d n g r o c c v 3 . 3 =5 . 8 s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c v c c v 2 . 0 v 5 . 2 =v c c v 7 . 2 = v c c v 3 . 3 = v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m f k c o l c y c n e u q e r f k c o l c c l f p 0 5 = r l 0 0 5 = w 00 5 100 5 10 0 5 1z h m t w n o i t a r u d e s l u p a b k l c r o b a k l c w o l r o h g i h 5 . 2 s n t u s e m i t p u t e s b a k l c e r o f e b a - r o a b k l c e r o f e b b - 9 . 0 t h e m i t d l o h b a k l c r e t f a a - r o a b k l c r e t f a b - 9 . 0 timing requirements over operating range note: 1. unused control inputs must be held high or low to prevent them from floating.
7 ps8135b 11/06/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvch16652 3.3v 20-bit flip-flop with 3-state outputs s r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( s n o i t i d n o c v c c v 7 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u . n i m. x a m. n i m ) 2 ( . x a m f x a m c l f p 0 5 = r l 0 0 5 = w 0 5 10 5 1z h m t d p b r o aa r o b7 . 54 . 12 . 5 s n a b k l c r o b a k l cb r o a3 . 74 . 26 . 6 a b s r o b a sa o t b4 . 79 . 17 . 6 t n e e o r o e ob r o a0 . 56 . 15 . 4 t s i d e o r o e ob r o a3 . 52 . 18 . 4 n o i t p i r c s e d d / t d v ) 3 ( l l a f r o e s i r n o i t i s n a r t t u p n i00 10 0 1v / s n switching characteristics over operating range (1) pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com operating characteristics, t a = 25 o c r e t e m a r a ps n o i t i d n o c t s e t v c c v 2 . 0 v 5 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u l a c i p y t c d p n o i t a p i s s i d r e w o p e c n a t i c a p a c d e l b a n e s t u p t u o c l f p 0 5 = z h m 0 1 = f f p d e l b a s i d s t u p t u o notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays.
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