1 ps8126a 05/07/01 product description pericom semiconductor?s pi74alvch series of logic circuits are produced using the company?s advanced 0.5 micron cmos technology, achieving industry leading speed. the PI74ALVCH16820, a 10-bit flip-flop designed for 2.3v to 3.3v v cc operation, features edge-triggered d-type flip-flops. on the positive transition of clock (clk) input, the device provides true data at the q outputs. a buffered output-enable (oe) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high- impedance state. in high-impedance state, outputs neither load nor drive the bus lines significantly. the high-impedance state and increased drive are able to drive bus lines without interface or pullup components. oe does not affect the internal operation of the flip-flops. old data can be retained or new data can be entered while the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor whose minimum value is determined by the current sinking capability of the driver. to prevent ?floating? inputs and to eliminate the need for pullup/ down resistors, the PI74ALVCH16820 has ?bus hold? which retains the data input?s last state whenever the data input goes to high- impedance . active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product features ? PI74ALVCH16820 is designed for low-voltage operation ?v cc = 2.3v to 3.6v ? hysteresis on all inputs ? typical v olp (output ground bounce) < 0.8v at v cc = 3.3v, t a = 25c ? typical v ohv (output v oh undershoot) < 2.0v at v cc = 3.3v, t a = 25c ? bus hold retains last active bus state during 3-state eliminating the need for external pullup resistors ? industrial operation: ?40c to +85c ? packages available: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 300 mil wide plastic ssop (v) PI74ALVCH16820 3.3v 10-bit flip-flop with dual outputs and 3-state outputs logic block diagram 1 oe 2 oe 1 q 2 c 1 1 d clk to 9 other channels d 1 1 q 1 1 28 56 55 2 3
2 ps8126a 05/07/01 PI74ALVCH16820 3.3v 10-bit flip-flop with dual and 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s t u p n is t u p t u o n e ok l cd n q l? h h l? l l llx q 0 hx x z product pin description truth table (1) note: 1. h = high signal level l = low signal level x = irrelevant z = high impedance - = low-to-high transition n=1,2 product pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 1oe 1q1 1q2 gnd 2q1 2q2 v cc 3q1 3q2 4q1 gnd 4q2 5q1 5q2 6q1 6q2 7q1 gnd 7q2 8q1 8q2 v cc 9q1 9q2 gnd 10q1 10q2 2oe clk d1 nc gnd d2 nc v cc d3 nc d4 gnd nc d5 nc d6 nc d7 gnd nc d8 nc v cc d9 nc gnd d10 nc nc 56-pin a, v e m a n n i pn o i t p i r c s e d e o) w o l e v i t c a ( t u p n i e l b a n e t u p t u o k l c) h g i h e v i t c a ( t u p n i k c o l c x ds t u p n i a t a d x qs t u p t u o e t a t s - 3 d n gd n u o r g v c c r e w o p maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature .................................... ?65c to +150c ambient temperature with power applied ... ?40c to +85c input voltage range, v in .................................. ?0.5v to v cc +0.5v output voltage range, v out .......................... ?0.5v to v cc +0.5v dc input voltage ............................................. ?0.5v to +5.0v dc output current ...................................................... 100ma power dissipation ........................................................... 1.0w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
PI74ALVCH16820 3.3v 10-bit flip-flop with dual and 3-state outputs 3 ps8126a 05/07/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 3.3v 10%) notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 3.3v, +25c ambient and maximum loading. 3. unused control inputs must be held high or low to prevent them from floating. s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t ) 1 ( . n i m. p y t ) 2 ( . x a ms t i n u v c c e g a t l o v y l p p u s3 . 26 . 3 v v h i ) 3 ( e g a t l o v h g i h t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 7 . 2 =0 . 2 v l i ) 3 ( e g a t l o v w o l t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 7 . 2 = 8 . 0 v n i ) 3 ( e g a t l o v t u p n i0v c c v t u o ) 3 ( e g a t l o v t u p t u o0v c c v h o t u p t u o h g i h e g a t l o v i h o 0 0 1 ? = m v , a c c =. x a m o t . n i mv c c 2 . 0 - v h i i , v 7 . 1 = h o 6 ? =v , a m c c =v 3 . 20 . 2 v h i i , v 7 . 1 = h o 2 1 ? =v , a m c c =v 3 . 27 . 1 v h i i , v 0 . 2 = h o 2 1 ? =v , a m c c =v 7 . 2 2 . 2 v h i i , v 0 . 2 = h o 2 1 ? =v , a m c c =v 0 . 34 . 2 v h i i , v 0 . 2 = h o 4 2 ? =v , a m c c =v 0 . 3 0 . 2 v l o t u p t u o w o l e g a t l o v i l o 0 0 1 = m v , a l i =. x a m o t . n i m 2 . 0 v l i i , v 7 . 0 = l o 6 =v , a m c c =v 3 . 2 4 . 0 v l i i , v 7 . 0 = l o 2 1 =v , a m c c =v 3 . 2 7 . 0 v l i i , v 8 . 0 = l o 2 1 =v , a m c c =v 7 . 2 4 . 0 v l i i , v 8 . 0 = l o 4 2 =v , a m c c =v 0 . 3 5 5 . 0 i h o ) 3 ( t u p t u o h g i h t n e r r u c v c c v 3 . 2 = 2 1 ? a m v c c v 7 . 2 = 2 1 ? v c c v 0 . 3 = 4 2 ? i l o ) 3 ( t u p t u o w o l t n e r r u c v c c v 3 . 2 =2 1 v c c v 7 . 2 =4 2 v c c v 0 . 3 =4 2 i n i t n e r r u c t u p n i v n i v = c c v , d n g r o c c v 6 . 3 = 5 m a i ) d l o h ( n i t u p n i d l o h t n e r r u c v n i v , v 7 . 0 = c c v 3 . 2 =5 4 v n i v , v 7 . 1 = c c v 3 . 2 = 5 4 ? v n i v , v 8 . 0 = c c v 0 . 3 = 5 7 v n i v , v 0 . 2 = c c v 0 . 3 = 5 7 ? v n i 0 =o tv , v 6 . 3 c c v 6 . 3 = 0 0 5 i z o t n e r r u c t u p t u o ) s t u p t u o e t a t s - 3 ( v t u o v = c c r o, d n gv c c v 6 . 3 =0 1 i c c t n e r r u c y l p p u s v c c =v 6 . 3i , t u o 0 = m a, v n i v r o d n g = c c 0 4 d i c c r e p t n e r r u c y l p p u s h g i h l t t @ t u p n i v c c v 0 . 3 =o t6 . 3v v t a t u p n i e n o c c -v 6 . 0 v t a s t u p n i r e h t o c c d n g r o 0 5 7 c i s t u p n i l o r t n o c v n i v = c c v , d n g r o c c v 3 . 3 = 5 . 3 f p s t u p n i a t a d 6 c o s t u p t u o v o v = c c v , d n g r o c c v 3 . 3 = 7
4 ps8126a 05/07/01 PI74ALVCH16820 3.3v 10-bit flip-flop with dual and 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 2 . 0 v 5 . 2 =v c c v 7 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u . n i m ) 2 ( . x a m . n i m ) 2 ( . x a m . n i m ) 2 ( . x a m f x a m 0 5 10 5 10 5 1z h m t d p k l cq0 . 15 . 65 . 50 . 18 . 4s n t n e e oq0 . 19 . 61 . 60 . 10 . 5s n t s i d e oq3 . 19 . 50 . 50 . 15 . 4s n timing requirements over operating range switching characteristics over operating range (1) operating characteristics, t a = 25c pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. recommended operating condition. s r e t e m a r a pn o i t p i r c s e d 0 2 8 6 1 h c v l a 4 7 i p s t i n u v c c v 2 . 0 v 5 . 2 =v c c v 7 . 2 =v c c v 3 . 0 v 3 . 3 = . n i m. x a m. n i m. x a m. n i m. x a m f k c o l c y c n e u q e r f k c o l c00 5 100 5 10 0 5 1z h m t w w o l r o h g i h k l c n o i t a r u d e s l u p3 . 33 . 33 . 3 s n t u s k l c e r o f e b a t a d e m i t p u t e s - 7 . 18 . 14 . 1 t h e m i t d l o hk l c r e t f a a t a d - 1 . 11 . 10 . 1 d t / d v ) 3 ( l l a f r o e s i r n o i t i s n a r t t u p n i 00 1v / s n s r e t e m a r a ps n o i t i d n o c t s e t v c c v 2 . 0 v 5 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u l a c i p y tl a c i p y t c d p n o i t a p i s s i d r e w o p e c n a t i c a p a c d e l b a n e s t u p t u o c l z h m 0 1 = f , f p 0 5 = 0 63 6 f p d e l b a s i d s t u p t u o8 36 4
|
