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a ad8079 features factory set gain ad8079a: gain = +2.0 (also +1.0 & C1.0) ad8079b: gain = +2.2 (also +1 & C1.2) gain of 2.2 compensates for system gain loss minimizes external components tight control of gain and gain matching (0.1%) optimum dual pinout simplifies pcb layout low crosstalk of C70 db @ 5 mhz excellent video specifications (r l = 150 v ) gain flatness 0.1 db to 50 mhz 0.01% differential gain error 0.02 8 differential phase error low power of 50 mw/amplifier (5 ma) high speed and fast settling 260 mhz, C3 db bandwidth 750 v/ m s slew rate (2 v step), 800 v/ m s (4 v step) 40 ns settling time to 0.1% (2 v step) low distortion of C65 dbc thd, f c = 5 mhz high output drive of over 70 ma drives up to 8 back-terminated 75 v loads (4 loads/ side) while maintaining good differential gain/ phase performance (0.01%/0.17 8 ) high esd tolerance (5 kv) available in small 8-pin soic applications differential a-to-d driver video line driver differential line driver professional cameras video switchers special effects rf receivers functional block diagram 8-pin plastic soic 1 2 3 4 5 6 7 8 ad8079 +in1 gnd gnd +in2 out1 +v s ? s out2 dual 260 mhz gain = +2.0 & +2.2 buffer rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. product description the ad8079 is a dual, low power, high speed buffer designed to operate on 5 v supplies. the ad8079s pinout offers excel- lent input and output isolation compared to the traditional dual amplifier pin configuration. with two ac ground pins separating both the inputs and outputs, the ad8079 achieves very low crosstalk of less than C70 db at 5 mhz. additionally, the ad8079 contains gain setting resistors factory set at g = +2.0 (a grade) or gain = +2.2 (b grade) allowing circuit configurations with minimal external components. the b grade gain of +2.2 compensates for gain loss through a system by providing a single-point trim. using active laser trimming of these resistors, the ad8079 guarantees tight control of gain and channel-channel gain matching. with its performance and con- figuration, the ad8079 is well suited for driving differential cables and transformers. its low distortion and fast settling are ideal for buffering high speed dual or differential a-to-d con- verters. the ad8079 features a unique transimpedance linearization circuitry. this allows it to drive video loads with excellent differ- ential gain and phase performance of 0.01% and 0.02 on only 50 mw of power per amplifier. it features gain flatness of 0.1 db to 50 mhz. this makes the ad8079 ideal for professional video electronics such as cameras and video switchers. the ad8079 offers low power of 5 ma/amplifier (v s = 5 v) and can run on a single +12 v power supply while delivering over 70 ma of load current. all of this is offered in a small 8-pin soic package. these features make this amplifier ideal for por- table and battery powered applications where size and power are critical. the outstanding bandwidth of 260 mhz along with 800 v/ m s of slew rate make the ad8079 useful in many general purpose high speed applications where dual power supplies of 3 v to 6 v are required. the ad8079 is available in the industrial temperature range of C40 c to +85 c. frequency ?hz 1m normalized flatness ?db 1g 10m 100m ?.5 0.1 0 ?.1 ?.2 ?.3 ?.4 1 0 ? ? ? ? ? ? ? ? ? normalized frequency response ?db side 2 side 1 side 2 side 1 r l = 100 w v in = 50mv rms 50 w 50 w figure 1. frequency response and flatness one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996
ad8079Cspecifications ad8079a/ad8079b parameter conditions min typ max units dynamic performance C3 db small signal bandwidth v in = 50 mv rms 260 mhz bandwidth for 0.1 db flatness v in = 50 mv rms 50 mhz large signal bandwidth v in = 1 v rms 100 mhz slew rate v o = 2 v step 750 v/ m s v o = 4 v step 800 v/ m s settling time to 0.1% v o = 2 v step 40 ns rise & fall time v o = 2 v step 2.5 ns noise/harmonic performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p C65 dbc crosstalk, output to output f = 5 mhz C70 db input voltage noise f = 10 khz 2.0 nv/ ? hz input current noise f = 10 khz, +in 2.0 pa/ ? hz differential gain error ntsc, r l = 150 w 0.01 % ntsc, r l = 75 w 0.01 % differential phase error ntsc, r l = 150 w 0.02 degree r l = 75 w 0.07 degree dc performance offset voltage, rto 10 15 mv t min Ct max 10 20 mv offset drift, rto 20 m v/ c +input bias current 3.0 6.0 m a t min Ct max 10 m a gain no load 1.998/2.198 2.0/2.2 2.002/2.202 v/v r l = 150 w 1.995/2.195 2.0/2.2 2.005/2.205 v/v gain matching channel-to-channel, no load 0.1 % channel-to-channel, r l = 150 w 0.5 % input characteristics +input resistance +input 10 m w +input capacitance +input 1.5 pf output characteristics output voltage swing r l = 150 w 2.7 3.1 v r l = 75 w 2.8 v output current 1 70 ma short circuit current 1 85 110 ma power supply operating range 3.0 6.0 v quiescent current/both amplifiers t min Ct max 10.0 11.5 ma power supply rejection ratio, rto +v s = +4 v to +6 v, Cv s = C5 v 49 69 db Cv s = C 4 v to C6 v, +v s = +5 v 40 50 db +input current t min Ct max 0.1 0.5 m a/v notes 1 output current is limited by the maximum power dissipation in the package. see the power derating curves. specifications subject to change without notice. C2C rev. a (@ t a = +25 8 c, v s = 6 5 v, r l = 100 v , unless otherwise noted)
9 rev. a ad8079 C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v internal power dissipation 2 small outline package (r) . . . . . . . . . . . . . . . . . . 0.9 watts input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range . . . . . . . . . . . . . C65 c to +125 c operating temperature range (a grade) . . . C40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-pin soic package: q ja = 160 c/watt maximum power dissipation the maximum power that can be safely dissipated by the ad8079 is limited by the associated rise in junction tempera- ture. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition tem- perature of the plastic, approximately +150 c. exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of +175 c for an ex tended period can result in device failure. while the ad8079 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves. maximum power dissipation ?watts ambient temperature ? c 2.0 1.5 0 ?0 90 ?0 ?0 ?0 ?0 0 10 20 30 40 50 60 70 1.0 0.5 80 t j = +150 c 8-pin soic package figure 2. plot of maximum power dissipation vs. temperature caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8079 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature package package model gain range description option AD8079AR g = +2.0 C40 c to +85 c 8-pin plastic soic so-8 AD8079AR-reel g = +2.0 C40 c to +85 c reel soic so-8 AD8079AR-reel7 g = +2.0 C40 c to +85 c reel 7 soic so-8 ad8079br g = +2.2 C40 c to +85 c 8-pin plastic soic so-8 ad8079br-reel g = +2.2 C40 c to +85 c reel soic so-8 ad8079br-reel7 g = +2.2 C40 c to +85 c reel 7 soic so-8
ad8079 rev. a C4C frequency ?hz 1m normalized flatness ?db 1g 10m 100m ?.5 0.1 0 ?.1 ?.2 ?.3 ?.4 1 0 ? ? ? ? ? ? ? ? ? normalized frequency response ?db side 2 side 1 side 2 side 1 r l = 100 w v in = 50mv rms 50 w 50 w figure 6. frequency response and flatness frequency ?hz ?0 ?0 distortion ?dbc ?10 10k 100m 100k 1m 10m ?0 ?0 ?00 ?0 2nd harmonic 3rd harmonic r l = 100 w figure 7. distortion vs. frequency, r l = 100 w ?0 ?0 ?20 ?00 ?10 ?0 ?0 100k 100m 10m 1m 10k frequency ?hz distortion ?dbc r l = 1k w v out = 2vp-p 2nd harmonic 3rd harmonic figure 8. distortion vs. frequency, r l = 1 k w 8 7 6 2 1 ad8079 +5v 10? 0.1? 50 w v in pulse generator 0.1? 10? ?v r l = 100 w t r /t f = 250ps figure 3. test circuit 20mv 5ns side 2 side 1 100mv step figure 4. 100 mv step response 200mv 5ns side 2 side 1 1v step figure 5. 1 v step response
9 rev. a ad8079 C5C crosstalk ?db frequency ?hz 100k 200m 0.1m 1m 10m 100m ?0 ?0 ?10 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 v in = 2v p-p r l = 100 w v s = 5v figure 9. crosstalk (output-to-output) vs. frequency ire 0.02 0.06 0.00 12 diff phase ?degrees 34567891011 0.01 0.08 0.04 0.02 0.00 ?.02 ?.01 diff gain ?% 2 back terminated loads (75 w ) 1 back terminated load (150 w ) 2 back terminated loads (75 w ) 1 back terminated load (150 w ) ntsc ntsc ire 123 45678 91011 figure 10. differential gain and differential phase (per amplifier) notes: side 1: v in = 0v; 8mv/div rto side 2: 1v step rto; 400mv/div 5ns side 2 side 1 r l = 100 w figure 11. pulse crosstalk, worst case, 1 v step frequency ?hz 1m 500m 10m 100m 3 0 ?7 ? ? ? ?2 ?5 ?8 ?1 ?4 3 0 ?7 ? ? ? ?2 ?5 ?8 ?1 ?4 normalized output level ?dbv input level ?dbv v in = 1.0v rms v in = 0.5v rms v in = 0.25v rms v in = 125mv rms v in = 62.5mv rms v s = 5v r l = 100 w figure 12. large signal frequency response time ?ns 0.1%/div 5 ? 0 120 20 40 60 80 100 4 1 ? ? ? 3 2 0 ? 2v step r c = 100 w r l = 150 w figure 13. short-term settling time 400mv 2? input output error, (0.05%/div) 2v step r l = 100 w figure 14. long-term settling time
ad8079 rev. a C6C 3.4 2.5 125 2.7 2.6 ?5 ?5 2.8 2.9 3.0 3.1 3.2 3.3 105 85 65 45 25 5 ?5 junction temperature ? c output swing ?volts +v out |? out | v s = 5v r l = 150 w figure 15. output swing vs. temperature junction temperature ? c input bias current ?? 7 ? ?5 125 ?5 ?5 5 25 45 65 85 105 6 3 2 1 0 5 4 +in figure 16. input bias current vs. temperature 8 ? 0 ? ? 6 2 4 125 ?5 ?5 105 85 65 45 25 5 ?5 junction temperature ? c input offset voltage rto ?mv device #1 device #2 device #3 figure 17. input offset voltage vs. temperature 11.5 9.0 125 10.5 9.5 ?5 10.0 ?5 11.0 105 85 65 45 25 5 ?5 junction temperature ? c total supply current ?ma v s = 5v figure 18. total supply current vs. temperature 120 75 125 85 80 ?5 ?5 90 95 100 105 110 115 105 85 65 45 25 5 ?5 junction temperature ? c short circuit current ?ma |sink i sc | source i sc 70 figure 19. short circuit current vs. temperature frequency ?hz 100 10 1 10 100k 100 noise voltage, rti ?nv/ hz 1k 10k 100 10 1 noise current ?pa/ hz noninverting current v s = 5v voltage noise v s = 5v figure 20. noise vs. frequency
9 rev. a ad8079 C7C resistance ? w frequency ?hz 10k 1g 100k 1m 10m 100m 100 10 1 0.1 0.01 v s = 5.0v power = 0dbm (223.6mv rms) r bt = 50 w r bt = 0 w figure 21. output resistance vs. frequency ?4.0 ?6.5 125 ?1.5 ?4.0 ?5 ?5 ?9.0 ?6.5 ?4.0 ?1.5 ?9.0 ?6.5 105 85 65 45 25 5 ?5 junction temperature ? c psrr ?db ?9.0 ?srr +psrr 2v span curves are for worst case condition where one supply is varied while the other is held constant. figure 22. psrr vs. temperature psrr ?db frequency ?hz 0 ? ?4 30k 500m 100k 1m 10m 100m ?4 ?4 ?4 ?4 ?4 ?4 ?4 v in = 200mv ?srr +psrr figure 23. psrr vs. frequency theory of operation the ad8079, a dual current feedback amplifier, is internally configured for a gain of either +2 (ad8079a) or +2.2 (ad8079b). the internal gain-setting resistors effectively elimi- nate any parasitic capacitance associated with the inverting in- put pin, accounting for the ad8079s excellent gain flatness response. the carefully chosen pinout greatly reduces the cross- talk between each amplifier. up to four back-terminated 75 w video loads can be driven by each amplifier, with a typical dif- ferential gain and phase performance of 0.01%/0.17 , respec- tively. the ad8079b, with a gain of +2.2, can be employed as a single gain-trimming element in a video signal chain. finally, the ad8079a/b used in conjunction with our ad8116 cross- point matrix, provides a complete turn-key solution to video distribution. printed circuit board layout considerations as to be expected for a wideband amplifier, pc board parasitics can affect the overall closed-loop performance. if a ground plane is to be used on the same side of the board as the signal traces, a space (5 mm min) should be left around the signal lines to minimize coupling. line lengths on the order of less than 5 mm are recommended. if long runs of coaxial cable are being driven, dispersion and loss must be considered. power supply bypassing adequate power supply bypassing can be critical when optimiz- ing the performance of a high frequency circuit. inductance in the power supply leads can form resonant circuits that produce peaking in the amplifiers response. in addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 m f) will be required to provide the best settling time and lowest distortion. a parallel combination of 4.7 m f and 0.1 m f is recommended. some brands of electrolytic capacitors will require a small series damping resistor ? 4.7 w for optimum results. dc errors and noise there are three major noise and offset terms to consider in a current feedback amplifier. for offset errors refer to the equa- tion below. for noise error the terms are root-sum-squared to give a net output error. in the circuit below (figure 24) they are input offset (v io ) which appears at the output multiplied by the noise gain of the circuit (1 + r f /r i ), noninverting input current (i bn r n ) also multiplied by the noise gain, and the inverting input current, which when divided between r f and r i and sub- sequently multiplied by the noise gain always appears at the out- put as i bn r f . the input voltage noise of the ad8079 is a low 2 nv/ ? hz . at low gains though the inverting input current noise times r f is the dominant noise source. careful layout and de- vice matching contribute to better offset and drift specifications for the ad8079 compared to many other current feedback am- plifiers. the typical performance curves in conjunction with the equations below can be used to predict the performance of the ad8079 in any application. v out = v io 1 + r f r i ? ? ? ? ? i bn r n 1 + r f r i ? ? ? ? ? i bi r f where: r f = r i = 750 w for ad8079a r f = 750 w , r i = 625 w for ad8079b
ad8079 rev. a C8C 8 7 6 2 1 5 4 3 v out #1 75 w 75 w cable 75 w v out #2 75 w 75 w cable 75 w 75 w 75 w cable v in +v s ? s v out #3 75 w 75 w cable 75 w v out #4 75 w 75 w cable 75 w 1/2 ad8079 1/2 ad8079 4.7? 4.7? 0.1? 0.1? figure 26. video line driver single-ended to differential driver using an ad8079 the two halves of an ad8079 can be configured to create a single-ended to differential high speed driver with a C3 db band- width in excess of 110 mhz as shown in figure 27. although the individual op amps are each current feedback with internal feedback resistors, the overall architecture yields a circuit with attributes normally associated with voltage feedback amplifiers, while offering the speed advantages inherent in current feedback amplifiers. in addition, the gain of the circuit can be changed by varying a single resistor, r f , which is often not possible in a dual op amp differential driver. 50 w output #1 50 w output #2 r g 750 w r f 750 w 1/2 ad8079 1/2 ad8079 op amp #1 op amp #2 v in c c = 1.5pf figure 27. differential line driver v out r f ( internal) r n i bi i bn r i ( internal) r series c l figure 24. output offset voltage driving capacitive loads the ad8079 was designed primarily to drive nonreactive loads. if driving loads with a capacitive component is desired, best frequency response is obtained by the addition of a small series output resistance (r series ). the graph in figure 25 shows the optimum value for r series vs. capacitive load. it is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of r series and c l . c l ?pf 40 30 0 025 5 r series ? w 10 15 20 20 10 figure 25. recommended r series vs. capacitive load operation as a video line driver the ad8079 has been designed to offer outstanding perfor- mance as a video line driver. the important specifications of differential gain (0.01%) and differential phase (0.02 ) meet the most exacting hdtv demands for driving one video load with each amplifier. the ad8079 also drives four back terminated loads (two each), as shown in figure 26, with equally impressive performance (0.01%, 0.07 ). another important consideration is isolation between loads in a multiple load application. the ad8079 has more than 40 db of isolation at 5 mhz when driv- ing two 75 w back terminated loads.
9 rev. a ad8079 C9C the current feedback nature of the op amps, in addition to enabling the wide bandwidth, provides an output drive of more than 3 v p-p into a 20 w load for each output at 20 mhz. on the other hand, the voltage feedback nature provides symmetri- cal high impedance inputs and allows the use of reactive compo- nents in the feedback network. the circuit consists of the two op amps each configured as a unity gain follower by the 750 w feedback resistors between each op amps output and inverting input. the output of each op amp has a 750 w resistor to the inverting input of the other op amp. thus, each output drives the other op amp through a unity gain inverter configuration. by connecting the two ampli- fiers as cross-coupled inverters, their outputs are free to be equal and opposite, assuring zero-output common-mode voltage. with this circuit configuration, the common-mode signal of the outputs is reduced. if one output moves slightly higher, the negative input to the other op amp drives its output to go slightly lower and thus preserves the symmetry of the comple- mentary outputs which reduces the common-mode signal. the resulting architecture offers several advantages. first, the gain can be changed by changing a single resistor. changing either r f or r g will change the gain as in an inverting op amp circuit. for most types of differential circuits, more than one resistor must be changed to change gain and still maintain good cmr. reactive elements can be used in the feedback network. this is in contrast to current feedback amplifiers that restrict the use of reactive elements in the feedback. the circuit described requires about 1.3 pf of capacitance in shunt across r f in order to opti- mize peaking and realize a C3 db bandwidth of more than 110 mhz. the peaking exhibited by the circuit is very sensitive to the value of this capacitor. parasitics in the board layout on the or- der of tenths of picofarads will influence the frequency response and the value required for the feedback capacitor, so a good lay- out is essential. the shunt capacitor type selection is also critical. good micro- wave type chip capacitors with high q were found to yield best performance. frequency ?hz 0.1m 1g 1m 10m 100m c c = 1.3pf v in = 10dbm 6 4 2 0 ? ? ? ? ?0 ?2 ?4 output ?db out+ out figure 28. differential driver frequency response layout considerations the specified high speed performance of the ad8079 requires careful attention to board layout and component selection. proper rf design techniques and low parasitic component se- lection are mandatory. the pcb should have a ground plane covering all unused por- tions of the component side of the board to provide a low im- pedance ground path. the ground plane should be removed from the area near the input pins to reduce stray capacitance. chip capacitors should be used for supply bypassing (see figure 29). one end should be connected to the ground plane and the other within 1/8 in. of each power pin. an additional large (4.7 m fC10 m f) tantalum electrolytic capacitor should be con- nected in parallel, but not necessarily so close, to supply current for fast, large-signal changes at the output. stripline design techniques should be used for long signal traces (greater than about 1 in.). these should be designed with a characteristic impedance of 50 w or 75 w and be properly termi- nated at each end.
ad8079 rev. a C10C +v s ? s r t in 50 w out +v s ? s c1 0.1? c3 10? c2 0.1? c4 10? +v s ? s r t 50 w out in * see table i supply bypassing inverting configuration noninverting configuration (g = +2) +v s ? s r t out in tie input pins together to minimize peaking noninverting configuration (g = +1) r t out in ad8079b trim 200 w optional gain trim (g = +2 ? + 2.2) figure 29. inverting and noninverting configurations table i. recommended component values component C1 +1 +2/+2.2 r t (nominal) ( w ) 53.6 49.9 49.9 small signal bw (mhz) 220 750 260 0.1 db flatness (mhz) 50 100 50 figure 30. board layout (silkscreen) figure 31. board layout (component layer) figure 32. board layout (solder side; looking through the board)
9 rev. a ad8079 C11C outline dimensions dimensions shown in inches and (mm). 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45
c2185aCxxC11/96 printed in u.s.a. C12C

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