general description the gd16546b is a high performance monolithic integrated clock and data re - covery (cdr) device applicable for opti - cal communication systems including: sdh stm-16 sonet oc-48 the cdr contains all circuits needed for reliable acquisition and lock of the vco phase to the incoming data-stream. the electrical input sensitivity is better than 8 mv (ber <10 -10 ). optical re - ceivers with sensitivity better than -34 dbm have been obtained without op- tical pre-amplifiers. the device meets all itu-t jitter require - ments when used with the recommended loop filter (jitter tolerance, -transfer and -generation). the 2.5 ghz output clock is maintained within 500 ppm tolerance even in ab - sence of data. the gd16546b is available in a 48 lead 77mm tqfp power enhanced plastic package. an intel company data sheet rev.: 10 features clock and data recovery covering 2.3 gbit/s to 2.7 gbit/s. sdh stm-16, sonet oc-48 compatible. differential data inputs with 8 mv sensitivity. differential cml data and clock outputs. acquisition time: < 500 s. few external passive components needed. 50 loop-through data inputs for higher sensitivity. single supply operation. power dissipation: 1 w. available in a 48 lea d77mm tqfp plastic package. applications clock and data recovery for optical communication systems including: ? sdh stm-16 ? sonet oc-48 2.5 gbit/s clock and data recovery gd16546b ck do u d u r d v d lock detect charge pump vco phase frequency detector bang bang phase detector mux direfn din limiter di diref refckn sel1 sel2 refck cko do ckon don vdd seltc k tck reset vee vdda vddl vctl pctl lock
functional details the main application of the gd16546b is as a receiver for: sdh stm-16 sonet oc-48 optical communica - tion systems. it integrates: a voltage controlled oscillator (vco) a lock detect circuit a frequency detector (pfd) a bang-bang phase detector into a phase locked loop (pll) - based clock and data recovery circuit with differ - ential cml data and clock outputs. vco the vco is a low noise lc-type differen - tial oscillator with a tuning range from 2.3 to 2.7 ghz. tuning is done by applying a voltage to the vctl pin. lock detect circuit the lock detect circuit continuously moni - tors the difference between the reference clock and the divided vco clock. if the reference clock and the divided vco fre- quency differs by more than 500 ppm (or 2000 ppm, selectable), it switches the pfd into the pll in order to pull the vco back inside the lock-in range. this mode is called the acquisition mode. the pfd is used to ensure predictable lock up conditions for the gd16546b by locking the vco to an external reference clock source. it is only used during acqui- sition and pulls the vco into the lock range where the bang-bang phase de - tector is capable of acquiring lock. the pfd is made with digital set/reset cells giving it a true phase and frequency characteristic. once the vco is inside the lock-range the lock-detection circuit switches the bang-bang phase detector into the pll in order to lock to the data signal. this mode is called cdr mode . the reference clock input, refck, to the pfd is at 1/64 of the data rate. bang-bang phase detector the bang-bang phase detector is used in cdr mode as a true digital type de - tector, producing a binary output. it sam - ples the incoming data twice each bit period: once in the transition of the (pre - vious) bit period and once in the middle of the bit period. when a transition oc - curs between 2 consecutive bits - the value of the sample in the transition be - tween the bits will show whether the vco clock leads or lags the data. hence the pll is controlled by the bit transition point, thereby ensuring that data is sam - pled in the middle of the eye, once the system is in cdr mode. the external loop filter components control the chara - cteristics of the pll. the binary output of either the pfd or the bang-bang phase detector (depend - ing of the mode of the lock-detection cir - cuit) is fed to a charge pump capable of sinking or sourcing current or tristating. the output of the charge pump is filtered through the loop filter and controls the tune-voltage of the vco. as a result of the continuous monitoring lock-detect circuit the vco frequency never deviates more than 500 ppm (2000 ppm) from the reference clock be - fore the pll is considered to be ?out of lock?. hence the acquisition time is pre - dictable and short and the output clock ckout is always kept within the 500 ppm (2000 ppm) limits, ensuring safe clocking of down stream circuitry. the lock signal the status of the lock-detection circuit is given by the lock signal. in cdr mode lock is steady high. in acquisition mode lock is alternating indicating the con- tinuous shifts between the bang-bang detector (high) and the pfd (low). the lock output may be used to gener- ate loss of signal (los). the time for lock to assert is predictable and short, equal to the time to go into lock, but the time for lock to de-assert must be con - sidered. when the line is down (i.e. no in - formation received) the optical receiver circuit may produce random noise. it is possible that this random noise will keep the gd16546b within the 500 ppm (2000 ppm) range of the line frequency, hence lock will remain asserted for a non-deterministic time. this may be pre - vented by injecting a small current at the loop filter node, which actively pulls the pll out of the lock range when the out - put of the phase detector acts randomly. the negligible penalty paid is a static phase error on the sampling time in the decision gate. however, due to the na - ture of the phase detector the error will be small (few degrees), forcing the loop to be at one edge of the error-function shaped transfer characteristic of the de - tector. inputs the input amplifier (pins di / din) is de - signed as a limiting amplifier with a sen - sitivity better than 8 mv (differential). the inputs may be either ac or dc cou - pled. in both cases input termination is made through pins diref / direfn. if the inputs are ac coupled the amplifier features an internal offset cancelling dc feedback. notice that the offset cancella - tion will only work when the input is dif - ferential and ac-coupled as shown in the figures on page 3 . following the cdr block the data is out - put together with a 2.5 ghz clock. the data and clock outputs are differential cml outputs with on-chip 100 back terminations. the outputs can externally be either ac- or dc-coupled. package the gd16546b is provided in a 48 lead power enhanced tqfp package. data sheet rev.: 10 gd16546b page 2 of 9
figure 1. dc coupled input (ignoring internal offset compensation) figure 2. ac coupled input (using internal offset compensation) figure 3. loop filter figure 4. dc coupled outputs figure 5. ac coupled outputs data sheet rev.: 10 gd16546b page 3 of 9 diref 50r from line from line vtt vtt 50r 8k 8k 26db direfn din di + - diref 50r from line from line vtt vtt 50r 8k 8k 26db direfn din di + - 33r vctl pctl vdda charge pump vco ext. loop filter veea vdda 2.2 f 50 50 100 100 vdd 50 50 100 100 vdd
pin list mnemonic: pin no.: pin type: description: do, don 31, 32 cml out data output, differential 2.5 gbit/s, with internal back termination. refck, refckn 18 19 ecl in differential 38 mhz reference clock input. sel1, sel2 16, 15 ecl in clock and data recovery set-up. sel1 sel2 0 0 auto lock, 500 ppm. 0 1 auto lock, 2000 ppm. 1 0 manual phase freq. detector pfc. 1 1 manual bang-bang phase detector. di, din 8, 6 data in differential ac or dc coupled 2.5 gbit/s data input. pins di/din may be swapped with pins diref/direfn respectively. diref, direfn 9 5 termination termination for di and din. normally terminated to vdd through 47 nf. for dc connected inputs connect to reference voltage. cko, ckon 29, 28 cml out clock output, differential 2.5 ghz, with internal back termination. lock 22 cml out lock-detect output. when low, the divided vco frequency deviates more than 500/2000 ppm from refck / refckn. pctl 42 analog out charge pump control. vctl 46 analog in vco voltage control input. reset 21 ecl in not needed on power up. connect to vee. only used for test purposes. tck 38 ecl in leave open for normal operation. only used at dc test. seltck 35 ecl in test-clock select. connect to vdd for normal operation. only used for test purposes. vdd 1, 7, 12, 13, 24, 25, 27, 30, 33, 36, 37, 48 pwr positive supply voltage. vdda 44, 47 pwr positive supply voltage for pll section. vddl 4, 11 pwr positive supply voltage. vee 2, 10, 14, 17, 26, 34, 39, 43, 45 pwr negative supply voltage. nc 3, 20, 23, 40, 41 nc not connected. heat sink floating potential. data sheet rev.: 10 gd16546b page 4 of 9
pin outline figure 6. 48 lead tqfp, top view maximum ratings these are the limits beyond which the component may be damaged. all voltages in the table are referred to vdd. all currents in the table are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit.: v ee ,v eea supply voltage -6 0 v v 0 max output voltage v ee - 0.5 0.5 v i 0 max, cml output current 16 ma i 0 max, pctl output current 0.5 ma v i max input voltage v ee - 0.5 0.5 v i i max input current -1.0 1.0 ma t 0 operating temperature junction -55 125 c t s storage temperature -65 150 c data sheet rev.: 10 gd16546b page 5 of 9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 24 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd vdda vctl vee vdda vee pctl nc nc vee tck vdd vdd seltck vee vdd don do vdd cko ckon vdd vee vdd nc vdd lock reset nc refckn refck vee sel1 sel2 vee vdd vdd vddl vee diref di vdd din direfn vddl nc vee vdd
dc characteristics t case =-5 cto95 c, v ee = -4.5 v to -5.5 v. all voltages in the table are referred to vdd. all input signal and power currents in the table are defined positive into the pin. all output signal currents are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit.: v ee supply voltage -5.5 -5.0 -4.5 v i ee supply current note 1 200 ma v diff di/din data input sensitivity, differential/single-ended note 2, 5 5 8 mv v diff max, di/din maximum input voltage, differential note 7 500 mv v cm di/din data common mode note 6 -2 -1.3 -1 v v ih ecl ecl input high voltage note 1 -1.1 0 v v il ecl ecl input low voltage note 1 v ee -1.5 v i ih ecl ecl input high current v i = -1.1 v 30 a i il ecl ecl input low current v i = -1.5 v 30 a v i vctl vco control voltage i vctl <30 a v ee -1 v v o cko/ckon , v o do/don cml output voltage swing note 3 500 600 mv v oh cml cml output high voltage note 3 -50 50 mv v ol cml cml output low voltage note 3 -800 -600 -500 mv v o lock cml output voltage swing note 8 500 600 mv i oh pctl source current note 4 100 a i ol pctl sink current note 4 100 a note 1: v ee = -5.0 v note 2: ac-coupled, p-p voltage for differential coupling, ber 10 -10 . data eye diagram in accordance with itu g.957, 2 23 - 1 prbs, terminated via loop through 50 . note 3: r l =50 to v dd on both outputs. note 4: output terminated to -2.5 v during test. note 5: v diff = vv pn note 6: v cm = vv pn 2 note 7: ac coupled input, p-p voltage. note 8: r l = 560 to v dd . data sheet rev.: 10 gd16546b page 6 of 9 v n v p
ac characteristics t case =-5 cto95 c, v ee = -4.5 v to -5.5 v. symbol: characteristic : conditions: min.: typ.: max.: unit.: j tol jitter tolerance note 1. see figure 7 2 hz < f < 100 khz 1mhz2 >0.35 ui p-p note 2 j trf jitter transfer note 1. see figure 8 12khz package outline figure 9. 48 lead tqfp, power enchanced (all dimensions are in mm). external references itu-t g.825 (03/93) control of jitter and wander within digital networks based on sdh itu-t g.957 (07/95) optical interfaces for equip. and systems relating to sdh itu-t g.958 (11/94) digital line systems based on sdh for use on optical fibre cables data sheet rev.: 10 gd16546b page 8 of 9
device marking figure 10. device marking ordering information to order, please specify as shown below: product name: intel order number: package type: case temperature range: option (wide temp. range): GD16546B-48BA fagd16546b48ba mm#: 836067 48 lead tqfp, edquad -5..95 c -40..85 c note: if extended temperature range (-40..85 c) is required, the purchase order must include the temperature specification. gd16546b, data sheet rev.: 10 - date: 31 july 2001 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.intel.com/ixa please check our internet web site for latest version of this data sheet. distributor: copyright ? 2001 giga aps an intel company all rights reserved an intel company gd16546b - - pin 1 - mark
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