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version update nr. edition confirmed all information contained in this document is property of mazet gmbh. no parts may be reproduced or copied, neither electronically nor mechanically, ex cept with explicit permission o f mazet gmbh. all mentioned company names and trade marks as well as product names obey the rules of trade marks and intellectual property. 1 v 2.1 2003-04-17 approvals date mazet gmbh compiled: 2002-04-30 checked: 2003-04-10 status: valid mazet gmbh sales g?schwitzer stra?e 32 07745 jena / germany phone: +49 3641 2809-0 fax: +49 3641 2809-12 e-mail: sales@mazet.de url: http://www.mazet.de released: 2003-04-17 doc. nr.: db-99-031e page 1 of 45 data sheet mmi 4832 integrated circuit for position measuring systems interfacing table of contents 1 introduction 3 1.1 ?endat ?, ?ssi? transfer mode 3 1.2 ?incremental? transfer mode: 5 1.3 functions available in both transfer modes 5 1.4 block diagram 6 2 parallel interface 6 3endat -interface 7 3.1 transfer formats (endat )7 3.2 registers 9 4 incremental interface 11 4.1 digital input filters 11 4.2 edge evaluation 12 4.3 counter 12 4.4 preset register 13 4.5 strobe register 13 4.6 reference register 14 5 general-purpose registers 14 5.1 receive register 14 5.2 multifunction register (mfr) 15 5.3 control register 16 5.4 status register 18 5.5 interrupt mask 20 5.6 timer 20 6 pin description 21 7package 22 8 general operating conditions 23 9 time relationships 24 1 c port addressation 29 1.1 intel, no autoincrement 29 1.2 intel, with autoincrement 30 1.3 motorola, no autoincrement 31 1.4 motorola, with autoincrement 32 .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 2 of 45 data sheet MMI4832 2 application examples 33 2.1 isa 33 2.2 transceivers 34 3 programming examples 34 3.1 reading of parameter ?data word length of encoder? (endat mode) 34 3.2 position value transfer with 13-bit encoder roc413 (endat mode) 36 3.3 position value transfer with 25-bit encoder eqn1325 (endat mode) 38 3.4 incremental measured-value transfer with hardware strobe 39 3.5 incremental measured-value transfer with reference strobe 40 3.6 incremental measured-value transfer with add offset 41 3.7 measured-value tr ansfer with ssi 44 3.8 setting of endat transfer rate 45 4faq?s 45 .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 3 of 45 data sheet MMI4832 1 introduction integrated circuit for position measuring systems interfacing via: ssi square-wave incremental signals (bidirectional interface for absolute encoders as defined by dr. j. heidenhain gmbh) (unidirectional interface for absolute encoders) (incremental z-track interface with 32-bit encoder counter) features outline mrs/address checking crc checking alarm bit checking parity bit checking gray-to-binary code conversion optionally selectable edge evaluation for square-wave incremental signals 32-bit control register, 8-bit status register, 8-bit interrupt mask 8-/16-bit microcontroller interface (intel or motorola mode) internal 18-bit timer system clock rate up to 33 mhz (endat: 24 mhz) the MMI4832 is an integrated circuit to provide interfacing for absolute encoders, i.e. sensors with an endat interface or a ssi port and/or encoders (of incremental mode type) alternatively. in endat interface transfer mode, it operates in accordance with the transfer protocol as defined by the endat interface documentation v2.1 of dr. j. heidenhain. 1.1 ?endat ?, ?ssi? transfer mode ?endat ? or ?ssi? transfer mode means that the serial data from an encoder is received by a data_rc pin. in endat-interface mode, the data are sent via pin data_dv. for communication with a pickup sensor, a clock is provided via pin tclk. the clock signals which are necessary to transfer any of the mode commands 1, 2, 3, 4, 5, 6 (compare with endat documentation) are automatically generated (compare with section: 3). for mode command 0 (telling the measuring system to send absolute position value(s)), a width must be defined for the expected position value via control register bit (24:29) ? data word 2). the desired transfer rate can be specified via control register bit (17:8) (compare with section: 5.3.1). transfer rates ifrom 100 khz to 2 mhz are supported. 24 mhz is the recommended system rate setting. .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 4 of 45 data sheet MMI4832 data transfer principle in endat and ssi mode data transfer can be initiated in three different ways: by an external strobe (h/l-edge), by a timer strobe (h/l-edge) or by a software strobe. figure 1-1 shows a principal data transfer diagram. configure control register configure send register y es princi p al data transfer se q uence in endat mode no external strobe, timer strobe software strobe data transfer read status register without reset data valid ? read receive register read status register with reset wait figure 1-1: principal data transfer diagram for endat and ssi mode .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 5 of 45 data sheet MMI4832 1.2 ?incremental? transfer mode: a direction discriminator uses the two 90-square-wave signals (cha, chb) as input to generate pulses which are then further processed in a downline 32-bit counter. this may be accomplished with selectable single-, double- or quadruple-edge evaluation. chc and chd serve as index tracks. optionally, the MMI4832 may also be operated in pulse direction mode. for explanations on how counting signals are generated and selected, you should refer to section 4.2. to reduce the influence of interferences, programmable digital input filters can be selectively connected to the four counter inputs cha, chb, chc and chd, the filter length being selectable in integer multiples of the system clock. the counter has a downline strobe register for the counter content to be written into this register with a hardware strobe or a software strobe without any need to interrupt the counting process. the counter is reset to zero if an index pulse is applied to any of the measuring system inputs (cha*chb*chc *chd) with a concurrent software en able signal (control register bit (3), control register bit (4)) or when the zero input is active (zero = low). /nia is a low-active signal to serve as the reset output of a counter circuit which functions as a master, in order to allow synchronization of several measuring systems. on selection of ?set-by-reference? (control register bit (6)), an index pulse arriving at (cha*chb*chc*chd) will cause the counter to be loaded with the preset register value. if ?reset? and ?set-by-reference? are active at the same time, the ?reset? function will prevail. on selection of ?reference strobe? (control register bit (1)), the latest counter values at the moment of an index pulse arriving at (cha*chb*chc*chd) will be loaded into the strobe register. ?reference compare? (control register bit (2)) allows the current counter reading to be compared with the value in the offset register. if the two values are found to be equal, status register bit (2) will be set. on selection of ?add offset?, an offset is added to the incremental value. this function is enabled by bit 10 of the control register. the full offset value (receive register + offset) is read from the multifunction register address. in ?incremental? transfer mode, the status register keeps track of reset, reference strobe, strobe and interference events at the inputs of the measuring system. 1.3 functions available in both transfer modes acting in conjunction with the 8-bit status register and the 8-bit interrupt mask, the control register supports easy recording and monitoring of the measured values. the interrupt mask makes it possible to selectively trigger an interrupt request for messages from a measuring system. the two inputs /ir6 and /ir7 are recorded by the status register. they allow specific application events (such as supply voltage availability, temperature, cable breakage, etc.) to be monitored. in all three modes (endat, ssi, incremental), a timer for selection of a desired sampling repeat rate (sampling rate) is available (compare with section 5.6 ). for a system clock rate of 24 mhz, the selected sampling rate may be in the range of 0.417s to 10.9 ms. alternatively, measured values can also be requested via the /str input or a software strobe. .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 6 of 45 data sheet MMI4832 1.4 block diagram figure 1-2 shows a block diagram of the MMI4832: figure 1-2: MMI4832 block diagram 2 parallel interface the MMI4832 has a multiplexed data/address bus. with pin cmd=1, the desired operating mode (8-/16-bit port, autoincrement) and the resource address need to be written into the internal address register. once this has happened, data access cycles (writing/reading of a resource e.g. the control register) may follow with cmd = 0. address register: cmd = 1 read/write bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 m16 ainc (auto increment) address a4 addres s a3 addres s a2 addres s a1 address a0 the number of cycles required to access a given resource depends both on the selected port width (8 or 16 bits, where 16-bit port width is set with m16 = 1) and the resource?s width. if multiple access cycles are required for a given resource, writing in parallel-port mode (?intel?) must begin with the least significant and in port mode (?motorola?) with the most significant data word/byte. with the l/h-edge (/wr) of each last access cycle to a resource, the access date will be written into this resource. in ?motorola? port mode, the two control signals /wr, /rd acquire a new meaning: /wr -> r_/w: switching between read/write /rd -> /ads: address or data strobe respectively. for reading cycles, one should consider that the current content of the resource being accessed is already loaded into the output register on writing into the address register. accordingly, in order to obtain a value of latest validity, it is necessary to enter the resource?s base address into the address register again before reading this resource for the next time. timer (16bits) endat-interface ? ssi-interface incremental interface send / preset register strobe register control reg. status reg. (8bits) offset register interrupt mask (8bits) reference register receive register (48 bit) control unit p a r a l l e l p o r t d(15:0) /rd /wr /cs tclk data_dv data_rc cha chb chc chd *** unmarked registers = 32 bits .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 7 of 45 data sheet MMI4832 table 1 shows how resources are addressed: register base address a(4:2) access cycles 8-/16-bit port comment send/preset rg w/r 0 4/2 32 bits receive rg ro 1 4/2 data word length 32 bits multifunction rg w/r 3 4/2 32 bits control rg w/r 4 4/2 32 bits status rg ro 5 1/1 8 bits software strobe wo 5 1/1 ---- (function, no resource) interrupt mask w/r 6 1/1 8 bits timer wo 7 2/1 16 bits status rg ro 7 1/1 8 bits table 1: adressation of resources when working in autoincrement mode (ainc=1), the base address (a(4:2)) of a resource needs to be entered into the address register and /wr or /rd be repeated for a number of ?n? times respectively. the byte/word address [a(1:0)] is automatically incremented after each access operation. on full completion of an access cycle, the address pointer will again refer to the base address, i.e. a(1:0)=0/dec. an incomplete access cycle may at any time be terminated by ?read status register with reset? [a(4:2)=5/dec] or by writing into the address register (cmd = 1). this will also reset the address pointer a(1:0). with autoincrement mode turned off (ainc=0), the byte/word addresses a(1:0) must be set by the user. 3 endat -interface 3.1 transfer formats (endat ) 3.1.1 transfer or position values mode command: 0 tells measuring system to send absolute position value(s) interrupted clock: d a t e n f o r m a t m 2 m 1 m 0 / m 2 / m1 / m 0 s t a a l a l s b .... m s b c r c c r c c r c c r c c r c .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 8 of 45 data sheet MMI4832 uninterrupted clock: new receive cycle: d a t e n f o r m a t c r c c r c c r c c r c c r c s t a a l a l s b .... m s b c r c c r c c r c c r c c r c 3.1.2 transfer of parameters mode command: 1 selects memory range d a t e n f o r m a t m 2 .. / m 0 c 7 .. c 0 d 1 5 .. d 0 s t a c 7 .. c 0 d 1 5 .. d 0 c r c c r c c r c c r c c r c mode command: 3 tells measuring system to receive parameters mode command: 4 tells measuring system to send parameters mode command: 5 tells measuring system to receive reset d a t e n f o r m a t m 2 .. / m 0 a 7 .. a 0 d 1 5 .. d 0 s t a a 7 .. a 0 d 1 5 .. d 0 c r c c r c c r c c r c c r c 3.1.3 start-up diagnosis (test in idle state) for start-up diagnosis, three steps are required: a) mode command: 6 tells measuring system to re ceive test command (with port address to be queried) d a t e n f o r m a t m 2 .. / m 0 a 7 .. p 0 d 1 5 .. d 0 s t a a 7 .. p 0 d 1 5 .. d 0 c r c c r c c r c c r c c r c b) mode command: 2 tells measuring system to send test values d a t e n f o r m a t m 2 .. / m 0 s t a a l a d 3 9 .. d 0 c r c c r c c r c c r c c r c c ) mode command: 6 resets port addresses on in structing the measuring system to receive test command (wit h address xx000000/b) d a t e n f o r m a t m 2 .. / m 0 a 7 .. p 0 d 1 5 .. d 0 s t a a 7 .. p 0 d 1 5 .. d 0 c r c c r c c r c c r c c r c .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 9 of 45 data sheet MMI4832 legend: send receive 3.2 registers 3.2.1 send register base address: 0/h, r/w, 30 bits, reset value: 0000 0000 /h the send register contains a mode command with related addresses and data: ?byte 4? bit (29:24) byte 3 bit (23:16) byte 2 bit (15:8) byte 1 (bit (7:0) mode command d (5:0) selects memory/ addresses data high date low its task is to perform sequencing control of clock transfer processes to an encoder. the content of this register is automatically transferred to the psc (compare with 3.2.2). a new value is only strobed into the send register if the writing cycle was completed and the transfer cycle to/from the encoder was completed (compare with 3.2.2). this prevents interruption of a running transfer cycle to or from a measured-value transmitter. the various mode commands for measuring system control need to be defined in bits (29:24). bit(29:24): 07/h tells measuring system to send position values (mode command 0) 0e/h selects memory range (mode command 1) 1c/h tells measuring system to receive parameters (mode command 3) 23/h tells measuring system to send parameters (mode command 4) 2a/h tells measuring system to receive reset (mode command 5) 15/h tells measuring system to send test values (mode command 2) 31/h tells measuring system to receive test command (mode command 6) byte (23:16) is available for storing related mrs codes, addresses and port addresses of the desired resources of a measuring system. bit(23:16): mode command 1: mrs code c(7:0) mode commands 3,4,5: addresses a(7:0) mode command 6: port addresses p(7:0) bits(15:0) are reserved for the data to be sent to the measuring system (mode command 3 telling the measuring system to receive parameters). in ?incremental? transfer mode, the send register functions like a 32-bit preset register (compare with sections: 4.3.2, 4.3.3). .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 10 of 45 data sheet MMI4832 3.2.2 parallel-to-serial converter (psc) has no base address of its own, 30 bits, reset value: 0 /h with a bit length of 30 bits, the parallel-to-serial converter generates a serial data stream that is transferred via the data_dv pin to a measured-value transducer. data can only be written into the converter via the send register (indirectly). a new value from the send register is only allowed to enter the psc if the corresponding transfer cycle to or from the measured-value transducer was completed (compare with 3.2). ?byte 4? bit (29:24) byte 3 bit (23:16) byte 2 bit (15:8) byte 1 (bit (7:0) mode command d (5:0) selects memory/ addresses data high data low 3.2.3 seriell-to-parallel converter (spc) has no base address of its own, 48 bits, reset value: 0 /h the serial-to-parallel converter has 48 bits. it rece ives a stream of serial data from an absolute encoder via pin data_rc. data recording begins when a start bit that was sent by the encoder has been identified and the alarm bit status been inquired, provided that an alarm bit is transferred as part of a selected mode command. 3.2.3.1 receive mode 1 measuring system is told to send ab solute position values m(2:0) = 0/h the number of required transfer clocks is determined by the ?data word length? as defined in control register bit(29:24). the maximum allowed transfer length is 48 bits. sending begins with the lsb. depending on the data word length which was set in the control register, the msb position will shift more or less in this register. once the msb has been received, the crc hardware(*) will be enabled to receive a crc code. 3.2.3.2 receive mode 2 selects memory range m(2:0) = 1/h tells measuring system to receive parameters m(2:0) = 3/h tells measuring system to send paramters m(2:0) = 4/h tells measuring system to receive reset m(2:0) = 5/h tells measuring system to receive test command m(2:0) = 6/h tells measuring system to send test data m(2:0) = 7/h the number of required transfer clocks is automatically generated. in contrast to receive mode 1, always eight mrs or address bits and sixteen parameter bits are received in this mode. sending begins with the msb. once the lsb was received, the crc hardware is enabled to receive a crc code. .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 11 of 45 data sheet MMI4832 3.2.3.3 receive mode 3 tells measuring system to send test values m(2:0) = 2/h the number of required transfer clocks is automatically generated. the test data word to be received has a width of forty bits. sending begins with the msb. once the lsb has been received, the crc hardware is enabled to receive a crc code. 3.2.3.4 crc in each of the three receive modes described before, the crc bits are compared with those crc bits which have been generated from the data stream that was received. on completion of a crc test, the serial-to-parallel converter is again operational. 3.2.3.5 data loading into the receive register a value received from the spc is loaded into the receive register on completion of a serial-to- parallel conversion process and completion of a crc check, unless an error bit (compare with status register) was set. a new and valid will only overwrite a previous value if the status bit 0 was reset (read status register with reset). (compare with section: 5.1.1.1 ) * crc test hardware according to endat definition v2.1 appendix a4 of dr.j.heidenhain gmbh 4 incremental interface 4.1 digital input filters programmable digital filters are provided for the four input signals cha, chd, chc, chd to allow interferences to be removed. for a signal to be iden tified as a useful signal, it must have a certain minimum duration. if a signal fails to last for this minimum prescribed time, it will be detected as an interference. filter programming, i.e. definition of the minimum required duration for a signal to qualify as ?useful signal? is made via the control register bits (15:11). preselection of value [wt usable ] for a desired minimum useful signal duration [t usable ] [wt usable ] = (t nutz / 2*t sys ) ? 1or [wt usable ] = (f sys / 2*f usable ) - 1 t usable - is the minimum duration of a useful signal f usable - is the maximum frequency of a useful signal f sys - is the system clock rate t sys - is the period of a system clock example: in order to detect only signals with a frequency 312.5 khz as useful input signals if a system clock of 20 mhz was set, 1f/h must be written into the control register bits (15:11) for wtusable. following a reset, the filters are turned off as a standard measure. on defining a value of 0/dec for the control register bits (15:11), the filter will also be turned off. .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 12 of 45 data sheet MMI4832 4.2 edge evaluation selections for counting pulse generation can be made through bits (9:8) of the control register. selection code assignments are as shown in table 2 below. reset will select pulse direction mode. cha chb pulse dir bit(9:8)=0 single bit(9:8)=1 double bit(9:8)=2 quadruple bit(9:8)=1 hvz l vz vz lvz vz h vz vz vz h rz rz rz lrz l rz rz hrz rz table 2: generation of counting pulses vz: counter increments rz: counter decrements 4.3 counter base address: 1/h, r/w, 32 bits, reset value: 0 /h reading: via strobe register (base address: 1/h) writing: via preset register (base address: 0/h ->1/h) the reversible counter is loadable. it counts the counting pulses which are generated by the discriminator. 4.3.1 reset resetting (zeoring) fulfils three functions: a) if the "reset" bit (control register bit (3)) is set, the counter will be reset once with cha*chb*chc*chd. this will set status bit (3) "res et". if "repeat" (control register bit 4) is unset, no more resets will follow with a next index pulse cha*chb*chc*chd (only via bypass path conditions of preset register=0/h and "set-by-ref" (control register bit 6) ? also compare with section: 4.3.2, 4.3.3). b) if bits "repeat" and "reset" are set, the counter will be reset to 0/h with each cha*chb*chc*chd. c) an external /null signal will set the counter to 0/h. it is intended for measuring systems with master-slave structures. .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 13 of 45 data sheet MMI4832 4.3.2 set-by-reference if function "set-by-ref" is enabled (control register bit (6) = 1), the preset register value will be loaded into the counter on a cha*chb*chc*chd. note: if "reset" and "set-by-ref" are enabled at the same time, "reset" will prevail. 4.3.3 counter loading via parallel port writing into the counter can not be accomplished directly from the parallel port. on writing to the counter?s base address (1/h), a given value is loaded from the preset register into the counter. 4.3.4 reference compare on selection of this function (control register bit (2)) the current counter reading (value) will be permanently compared with the value that is contained in the multifunction register. if both values are found to be equal, status register bit (2) will be set. 4.3.5 add offset an offset is added to the incremental value. this function is enabled via control register bit (10). the full offset value (receive register + offset) is read from the address of the multifunction register. 4.4 preset register basa address: 0/h, r/w, 32 bits, reset value: 0 /h a value which is temporarily stored in the preset register can be loaded into the counter by writing to the counter?s base address (1/h) (compare with section: 4.3.2, 4.3.3). in ?endat ? transfer mode, the preset register functions like a 30-bit send register (compare with section: 3.2). 4.5 strobe register base address: 1/h, *ro, 32 bits, reset value: 0 /h control register bit (16) = 0 current counter values can be loaded into the strobe register via hardware strobe or software strobe: 4.5.1 hardware strobe if strobe is enabled (control register bit (0) = 1) and status register bit (0)=0) reset, the counter value will be loaded into the strobe register with a falling edge at the external strobe input /str or at the timer (internal signal derived from /srb). this will set status register bit (0)=1. .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 14 of 45 data sheet MMI4832 4.5.2 software strobe on "writing" to the base address 5/h, a counter value will be loaded into the strobe register. however, no data is written from the parallel port into the MMI4832! the software strobe is independent of the control register bit (0). it is being reflected in the status register. 4.5.3 signal transit time when working with digital input filters in the case of a hardware strobe, the internal strobe pulse is delayed by a certain amount of transit time depending on what input filter option has been enabled. this option has been incorporated, in order to ensure a precisely timed (and, hence, precisely positioned) loading of the counter information. in the case of a software strobe, the internal strobe pulse is derived from the falling edge of a /wr writing signal without any correlated delay. 4.6 reference register base address: 1/h,* ro, 32 bits, reset value: 0 /h control register bit (16) = 1 the reference register supports the reference strobe function : if ?reference strobe? (control register bit (1)) is enabled, the current counter values will be loaded into the reference register on occurrence of an index pulse (cha*chb*chc*chd). * strobe and reference register are read via the receive register address! 5 general-purpose registers 5.1 receive register base address: 1/h, ro, version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 15 of 45 data sheet MMI4832 5.1.1.1.2 software strobe a software strobe (writing to base address 5/h) will trigger a transfer start independently of the state of control register bit (0).it will also load a previously received valid value (no error message) into the receive register. after this value has been read, the status register bit (0) needs to be reset, in order to allow a new value to be loaded into the receive register! 5.1.1.2 mapping of transfer packages in receive register the following tables show what position the various transfer packages will occupy in the receive register. measuring system is told to send ab solute position values m(2:0) = 0/h byte 6 bit (47:40) byte 5 bit (39:32) byte 4 bit (31:24) byte 3 bit (23:16) byte 2 bit (15:8) byte 1 bit (7:0) m s b* . . . . . . . . . . . . l s b * the msb position will shift depending on the length of a position value. memory range is selected m(2:0) = 1/h measuring system is told to receive parameters m(2:0) = 3/h measuring system is told to send parameters m(2:0) = 4/h measuring system is told to receive reset m(2:0) = 5/h measuring system is told to receive test command m(2:0) = 6/h measuring system is told to send test data m(2:0) = 7/h bit (47:40) byte 5 bit (39:32) byte 4 bit (31:24) byte 3 bit (23:16) byte 2 bit (15:8) byte 1 bit (7:0) --- --- --- d (15:8) d (7:0) a (7:0) a7...p0 measuring system is told to send test values m(2:0) = 2/h byte 6 bit(47:40) byte 5 bit(39:32) byte 4 bit(31:24) byte 3 bit(23:16) byte 2 bit(15:8) byte 1 bit(7:0) --- d (39:32) d (31:24) d (23:16) d (15:8) d (7:0) 5.1.2 ?incremental? transfer mode both the strobe register and the reference register are read via the receive register (compare with section: 4.5, 4.6). 5.2 multifunction register (mfr) base address: 3/h, ro, r/w, 32 bits, reset value: 0 /h .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 16 of 45 data sheet MMI4832 5.2.1 ?endat ?, ?ssi? transfer mode the multifunction register contains specific ic test values. 5.2.2 ?incremental? transfer mode the multifunction register (r/w) supports ?reference compare? and ?add offset?. these functions are only available in incremental transfer mode (compare with section: 4.3.4, 4.3.5). 5.3 control register base address: 4/h, r/w, 32 bits, reset value: 0000 0000 /h * the control register allows you to set the various required transfer modes and functions: 5.3.1 ?endat ?, ?ssi? transfer mode with bit (7) = 0 the MMI4832 will work in ?endat ? transfer mode. in this case, the control register will contain all required or available setups and functions for endat mode: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 1 0 gray2 binary parity even /odd parity check error check off uninter rupted clock reserved hardware strobe allowed bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 2 division factor division factor division factor division factor division factor division factor division factor division factor bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 3 reserved reserved reserved reserved reserved reserved division factor division factor bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 4 disable 500ms endat interface / ssi data word length 2 data word length 2 data word length 2 data word length 2 data word length 2 data word length 2 the following functions may be called up (bit x = 1 ): bit 0: measured value loading allowed: on selection of timer or external strobe input /str, a new value (found to represent no error signal) will only be loaded into the receive register if bit 0 = 1 and status register bit (0) = 0. a software strobe will, independently of the state of bit 0, cause the current (found to be faultless) value to be loaded into the receive register if status register bit (0) = 0. bit 2: as part of mode command ?0? absolute position values are transferred with uninterrupted clock rhythm. this function is intended for fast measured value recording, e.g. where surface profiles have to be scanned (only ?endat-interface ? mode). if control register bits (0)=1 while this function runs, the receive register will automatically be updated. only a single strobe is necessary to trigger a transfer! bit 3: no check for mrs, address or crc errors is performed and no error message writtten into the status register (only ?endat-interface ? mode). a received value is loaded into the receive register. bit (5:4): in ?ssi? mode: parity check is allowed (bit 5= 0: even, bit 5= 1: odd) bit 6: gray-to-binary conversion of serial data stream (only for "ssi") bit 7: switches between modes: "incremental" (bit 7 = 1) or "endat-interface " and "ssi" (bit 7 = 0 ) bit (17:8): selects clock rate fo r measured-value transmitter * .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 17 of 45 data sheet MMI4832 bit (29:24): selects data word length 2 (in accordance with connected transmitter/encoder)**: allows defining the length of a data word to be received in both modes ?ssi? and ?endat- interface ? (receives position values with random programming). bit (31:30): bit 31 = 0/1: skips the turn-on procedure (500ms). the internal engine for encoder clock control will change to ?endat-interface ? mode if bit 30 = 0, and to ?ssi? if bit30 = 1. this function is performed once on setting of bit 31. * for the desired division factor, a value of 1 2 f f clk tclk needs to be set. (expl: d(17:8) = 8/dec delivers a transmitter clock rate (tclk) of 1 mhz for fsys = 16 mhz) ** for ?endat-interface ? mode, the desired data word length must be specified. (expl.: d(29:24) = 011000/b for transferring a 24-bit data word). for ?ssi? mode, the desired data word length + 1 must be defined. (expl.: d(29:24) = 011001/b for transferring a 24-bit data word). 5.3.2 ?incremental? transfer mode in ?incremental? transfer mode (bit(7)=1), a number of mode selections are required or can be made. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 1 1 set-by- reference counter stop repeat reset reset referenc e compare referece strobe allowed hardware strobe allowed bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 2 filter filter filter filter filter add offset ipf1 ipf0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 3 reserved reserved reserved reserved reserved reserved reserved strobe/ reference bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 4 reserved reserved data word length 2 data word length 2 data word length 2 data word length 2 data word length 2 data word length 2 the following functions can be selected (bit x = 1): bit 0: measured-value loading allowed. on selection of timer or external strobe input /str, a new value will only be loaded into the receive register if bit 0 = 1 and status register bit (0) = 0. a software strobe will, independently of the state of bit 0, cause the current (found to be faultless) value to be loaded into the receive register if status register bit (0) = 0. bit 1: reference strobe is allowed (with cha*chb*chc*chd - edge-sensitive). bit 2: reference compare (if value is found to be identical with that of the offset register, status register bit (2) will be set ? edge-sensitive) * bit 3: one-time counter reset with cha*chb*chc*chd - edge-sensitive. bit 4: with bit 3 = 1: repeated reset is allowed with each cha*chb*chc*chd - edge- sensitive. bit 5: counter inputs are disabled. bit 6: set-by-reference enabled (with cha*chb*chc*chd) ? edge-sensitive. bit (9:8): edge evaluation for increment signals at cha and chb * bit 10: adds an offset value to the strobe register value as part of reading bit (15:11): filter setting ** bit (29:24): sets data word length 2 = counter widt h = 20/h ensures proper counter reading via receive register. note: if "reset" and "set-by-ref" are simultaneously enabled, "reset" will prevail. * following a reset, pulse direction mode is set as the default version. count events are 0/1 transition edges at cha. chb=0 is defined as forward direction. . .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 18 of 45 data sheet MMI4832 in edge evaluation mode, single, double and quadruple evaluation can be programmed via control register bit (9:8). counting pulses are generated as shown in table 2. ** in order to allow the suppression of interference sign als at the signal inputs cha, chb, chd, chd, easily programmable digital filters have been implemented. if a signal fails to reach a certain minimum required duration, it will be detected as an interference. filter programming, i.e. definition of the minimum duration for a signal to be recognized as a useful signal, is accomplished with the help of control register bit (15:11). given a system clock rate of 20 mhz, pulses lasting from 1.5 s to 200 ns can be defined for suppression range. formula for setting the [wtnutz] value for a desired minimum useful signal duration [tnutz] [wtnutz] = (tnutz / tsys) - 1 or [wtnutz] = (fsys / 2*fnutz) - 1 tnutz - mininimum required duration for a useful signal tsys - period of a system clock fnutz - maximum rate of a useful signal fsys - system clock rate example: in order to detect only signals with a frequency 312.5 khz as useful input signals when a system clock of 20 mhz is set, 1f/h must be written into th e control register bi ts (15:11) for wtnutz. following the MMI4832 reset, all filters are turned off by default. defining 0/dec value for control register (15:11) will turn the filters off. while ?endat-interface ? and ? ssi ? modes are active, the encoder component will work with the standard quadruple edge evaluation. this makes it possible to switch to incremental mode without loss of data on completion of a transfer cy cle of absolute position values. all reserved bits must be filled with ?0?. 5.4 status register base address: 5/h, ro (reading with reset), 8 bits, reset value: 0/h base address: 7/h, ro (reading without reset) the status register informs about the various events that have occurred during a recording procedure of measured-values (d(x)=1). its content is different for ?endat-interface ? and incremental transfer mode. 5.4.1 ?endat ?, ?ssi? transfer mode the status register informs about events regarding the endat measuring system and free interrupt inputs: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 endat- interface /ssi /ir7 /ir6 ssi parity error crc error address mrs error alarm pv valid bit(0): parallel value is valid if enabled in control register or on a software strobe bit(1): alarm bit was set by measuring system if enabled in control register (only in ?endat-interface ?) bit(2): error on transferring mrs or address codes (memory select) to/from the measuring system if enabled in control register (only in endat-interface ) -> acknowledged code is not identical with transmitted code -> acknowledged address is not identical with transmitted address bit(3): crc error: error on te sting a crc code that was received from the measuring system if enabled in control register (only in ?endat-interface ?) bit(4): parity check if enabled in control register (only for ssi) .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 19 of 45 data sheet MMI4832 bit(5): ic works in ?ssi? transfer mode bit(6): detects h/l-edge at input pin /ir6 bit(7): detects low level at input pin /ir7 the "parallel value valid" bit is set at the end of a transfer process. however, if the timer or external strobe input /str is involved, it will only be set ? and, hence a new value (which was found to be faultless) only be loaded into the receive register ? if bit (0) of the control register is ?1? and the status register had been reset to zero before. independently of the state of control register bit (0), a software strobe will cause the current value (which was found to be faultless) to be loaded into the receive register if the status register bit (0) had been reset to zero before. bits (1:4) in set (error!) state will in any case prevent the setting of the "parallel value valid" bit. 5.4.2 ?incremental? transfer mode the status register informs about incremental measuring-system events and the free interrupt inputs: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 incremental /ir7 /ir6 spike, track errors repeat reset reset reference compare reference strobe strobe bit(0): measured value is valid if enabled in control register or on software strobe bit(1): performs reference strobe (with cha*chb*chc*chd ? edge-sensitive) bit(2): performs reference compare (if value fo und to be equal to the value of the offset register ? edge-sensitive) bit(3): performs reset (one-time counter reset (with cha*chb*chc*chd - edge-sensitive) bit(4): performs repeat (with cha*chb*chc*chd ? edge-sensitive) bit(5): spike or track errors at cha, chb, chc, chd bit(6): detects h/l-edge at input pin /ir6 bit(7): detects low level at input pin /ir7 if the timer or external strobe input /str is used, status bit (0) will only be set and a new value only be loaded into the receive register if bit (0) of the control register is ?1? and the status register had been reset earlier. regardless of the state of control register bit (0), a software strobe will cause the current value (which was found to be faultless) to be loaded into the receive register, provided that bit (0) of the status register had been reset earlier. 5.4.3 /ir6, ir7 in all operating modes (?endat ? , ?ssi?, ?incremental?) bits (6,7) inform about events at the two inputs /ir6 (h/l-edge-sensitive) and /ir7 (low active). these inputs are available for specific customer applications, for example, to monitor supply voltages, temperatures, to detect cable breakage, etc. on reading of the status register (base address: 5/h), its content is reset to 00/h. .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 20 of 45 data sheet MMI4832 5.5 interrupt mask base address: 6/h, r/w, 8 bits, reset value: 0/h the interrupt mask is intended to allow masking of the various sources that may cause an interrupt for the MMI4832. each bit contained in the status register is able to create an interrupt. the bit assignments of the interrupt mask is identical with that of the status register. if a bit is set, the corresponding interrupt will be enabled (d(x)=1). 5.6 timer base address: 7/h, wo, 16 bits, reset value: 0/h the MMI4832 has its own internal timer. it is cpable of creating a programmable output frequency at pin /srb. this frequency can be used as a repeat rate (sampling rate) for the measured values. the following table shows some selected sample frequencies. bit(15:0) /hex bit(15:0) /dec sampling rate 00 stop 2 2 0.416 s (2.4 mhz) 12c 300 50 s ( 20 khz) 1770 6000 1000 s ( 1 khz) ffff 65535 10.9 ms (91.7 hz) 5.6.1 transfer start in "endat " , "ssi" mode a h/l-edge of /srb will trigger the transfer clock for the encoder if control register bit (0) is enabled. in addition, the hardware strobe input /str must be disabled (/str = 1), because /str and internal timer output are ?or?-ed. 5.6.2 setting a desired sampling rate to set a desired sampling rate, you need to define a value [wttf] = ? (f clk / f timer -2 )) in the timer preset register. in other terms, the relationship between t timer and t clk = 4 * wttf + 2. .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 21 of 45 data sheet MMI4832 6 pin description symbol type MMI4832 (tqfp44) description function pins data_dv o 40 data drive (data send ing to measured-value encoder) d(0) i/o 41 data d(1) i/o 42 data d(2) i/o 43 data d(3) i/o 44 data d(4) i/o 1 data d(5) i/o 2 data d(6) i/o 3 data d(7) i/o 4 data d(8) i/o 7 data d(9) i/o 8 data d(10) i/o 9 data d(11) i/o 10 data d(12) i/o 11 data d(13) i/o 12 data d(14) i/o 13 data d(15) i/o 14 data /wr r_/w i 15 write request, low-active (intel mode) switching between read and write (motorola mode) /rd /ads i 16 read request, low-active address data strobe, low-active (motorola mode) /cs i 17 chip select, low-active de o 18 drive enable (for external transceiver) * clk i 20 system clock data_rc i 22 data receive (data receiv ed from measured-value encoder) /res i 23 reset signal for MMI4832, low-active /null i 24 external counter reset (low-active) cmd i 25 address select mot i 26 parallel port mode: mot=0: ?intel?, mot=1: ?motorola? /ir6 i 27 sensitive input for interrupt request, h/l-active /ir7 i 28 sensitive input for interrupt request, low-active /str_syn o 29 test pin for MMI4832 manufacturer nia_tclk o 30 transfer clock (?endat-interface ? and ?ssi ) zero output ( incremental mode) /int o 31 interrupt re quest (low/tristate) /srb o 32 timer output, low-active /str i 35 strobe input, h/l-active cha i 36 track a chb i 37 track b chc i 38 track c (index) chd i 39 track d (index) system pins: v dd i 5, 19, 33 operating voltage (5v) v ss i 6, 21, 34 earthground table 3: pin assigments of MMI4832 circuit .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 22 of 45 data sheet MMI4832 note: each pair of supply pins must be blocked with a 100nf ceramic multi-layer capacitor. we also recommend installing an electrolytic capacitor (220f) near the MMI4832. de=1: ic sends data (via data_dv) to a measured-value encoder. 7 package figure 7-1 shows the package of the MMI4832. h d d 1 n e e h e a a 2 p b c a 1 p l 0,1 0,2 m figure 7-1: designation of package: tqfp44 .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 23 of 45 data sheet MMI4832 table 4 contains all essential package dimensions: tqfp-44 description symbol min. nom. max. unit of measure pin number n - 44 - - pitch e 0.80 mm overall height a 1.60 mm pin width b p 0.30 0.45 mm pin length l p 0.45 mm side length, total h d 11.85 12.15 mm side length, total h e 11.85 12.15 mm package spacing a 1 0.05 0.15 mm package thickness a 2 1.35 1.45 mm pin thickness c 0.09 0.20 mm side length, body d 9.75 10.25 mm side length, body e 9.75 10.25 mm pin inclination 07 ground m0.5g package material plastic materials pin materials feni-alloy, electro-tin-platedt pin shape z-shaped table 4: package dimensions 8 general operating conditions table 5 provides a summary of the MMI4832?s general operating conditions: characteristic values (nominal: ucc=5v) symbol min. max. unit comment supply voltage ucc 4.75 5.25 v input voltage for h-level (cmos) uih 0.7 * u cc u cc + 0.5 v input voltage for l-level (cmos) uil -0.5 0.3 * u cc v l-output voltage uol 0.4 v iol = 4ma h-output voltage uoh 2.4 v ioh = 4ma operating temperature tamb 0 70 c system clock rate fclk - 33 mhz incremental mode system clock rate fclk typically: 24 mhz endat mode esd strength 2 kv human body model table 5: general conditions for MMI4832 operation .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 24 of 45 data sheet MMI4832 9 time relationships - (general description of parallel port) - parallel port mode: ?intel? read cycle: symbol parameter min. [ns] max. [ns] t1 address-valid-to-rd-active 20 --- t2 rd-active-to-data-valid --- 1/f clk +20 t3 data-float-after-rd --- 35 t4 rd-pulse-width 1/f clk +20 --- t5 address-float-after-rd 0 --- t6 recover 1/f clk --- /rd t 1 t 2 t 5 data valid t 3 t 4 adr, /cs figure 9-1: signal diagram for ppm intel read cycle write cycle : symbol parameter min. [ns] max. [ns] t1 address-valid-to-wr-active 20 --- t2 data-valid-to-wr-transition 1/f clk +20 --- t3 data-hold-after-wr 0 --- t4 wr-pulse-width 1/f clk +20 --- t5 address-hold-after-wr 0 --- t6 recover 1/f clk --- .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 25 of 45 data sheet MMI4832 /wr t 1 t 2 t 5 data t 3 t 4 valid adr, /cs figure 9-2: signal diagram for ppm intel write cycle figure 9-3: signal diagram for ppm intel recovery recovery /wr, /rd t 6 .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 26 of 45 data sheet MMI4832 parallel port mode: ?motorola? read cycle: symbol parameter min. [ns] max. [ns] t1 address-valid-to-/ads -active 20 --- t2 data-valid-to-/ads-transition --- 1/f clk +20 t3 data-hold-after-/ads --- 35 t4 /ads -pulse-width 1/f clk +20 --- t5 address-hold-after-/ads 0 --- t6 recover 1/f clk --- t7 r_/w-valid to /ads asserted 0 --- t8 /ads negated to r_/w-invalid 0 --- read cycle r/ w t 1 t 2 t 5 data vali d t 7 t 4 /ads t 3 cmd, / cs t 8 figure 9-4: signal diagram for ppm motorola read cycle write cycle : symbol parameter min. [ns] max. [ns] t1 address-valid-to-/ads-active 20 --- t2 data-valid-to-/ads-transition 1/f clk +20 --- t3 data-hold-after-/ads 0 --- t4 /ads -pulse-width 1/f clk +20 --- t5 address-hold-after-/ads 0 --- t6 recover 1/f clk --- t7 r_/w-valid to /ads asserted 0 --- t8 /ads negated to r_/w-invalid 0 --- .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 27 of 45 data sheet MMI4832 write cycle r_/w t 1 t 2 t 5 data t 3 t 4 valid cmd, /cs /ads t 7 t 8 figure 9-5: signal diagram for ppm motorola write cycle recovery: recovery /ads t 6 figure 9-6: signal diagram for ppm motorola recovery .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 28 of 45 data sheet MMI4832 appendix mmi 4832 table of contents 1 c port addressation 29 1.1 intel, no autoincrement 29 1.2 intel, with autoincrement 30 1.3 motorola, no autoincrement 31 1.4 motorola, with autoincrement 32 2 application examples 33 2.1 isa 33 2.2 transceivers 34 3 programming examples 34 3.1 reading of parameter ?data word length of encoder? (endat mode) 34 3.2 position value transfer with 13-bit encoder roc413 (endat mode) 36 3.3 position value transfer with 25-bit encoder eqn1325 (endat mode) 38 3.4 incremental measured-value transfer with hardware strobe 39 3.5 incremental measured-value transfer with reference strobe 40 3.6 incremental measured-value transfer with add offset 41 3.7 measured-value tr ansfer with ssi 44 3.8 setting of endat transfer rate 45 4faq?s 45 .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 29 of 45 data sheet MMI4832 1 c port addressation 1.1 intel, no autoincrement a(4:2) a(1:0) resource 16-bit write port 8-bit port 16-bit read port 8-bit port parallel-serial converter sets send register reads send register 0 0 sets d(0:15) d(0:7) reads d(0:15) d(0:7) 1 sets d(7:15) reads d(7:15) 2 sets d(16:31) d(16:23) reads d(16:31) d(16:23) 3 sets d(24:31) reads d(24:31) 2 4 2 4 receive register loads serial-parallel converter value reads receive register, strobe rg 10 into receive register reads d(0:15) d(0:7) 1 --- --- reads d(7:15) 2 --- --- reads d(16:31) d(16:23) 3 --- --- reads d(24:31) 1 1 receive register reads receive register, strobe rg 2 0 --- --- reads d(32:47) d(32:39) 1 --- --- reads d(40:47) 1 - 3 ** 2 - 6 ** multifunction register (mfr) sets mfr reads mfr 3 0 sets d(0:15) d(0:7) reads d(0:15) d(0:7) 1 sets d(7:15) reads d(7:15) 2 sets d(16:31) d(16:23) reads d(16:31) d(16:23) 3 sets d(24:31) reads d(24:31) 2 4 2 4 control register sets control register reads control register 4 0 sets d(0:15) d(0:7) reads d(0:15) d(0:7) 1 sets d(7:15) reads d(7:15) 2 sets d(16:31) d(16:23) reads d(16:31) d(16:23) 3 sets d(24:31) reads d(24:31) 2 4 2 4 status register software strobe reads status register with reset 5 0 --- reads d(0:7) d(0:7) 1 1 1 1 interrupt mask sets interrupt mask reads iterrupt mask 6 0 sets d(0:7) d(0:7) reads d(0:7) d(0:7) 1 1 1 1 timer + status sets timer register reads status register wihout reset 7 0 sets d(0:15) d(0:7) reads d(0:7) d(0:7) 1 sets d(7:15) --- --- 2 ---- --- --- --- 3 ---- --- --- --- 1 2 1 1 table 6: parallel port mode ?intel?: no autoincrement (mot= low, ainc = low) .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 30 of 45 data sheet MMI4832 1.2 intel, with autoincrement a(4:2) /wr-, /rd access resource 16-bit write port 8-bit port 16-bit read port 8-bit port send register sets send register reads send register 0 1 sets d(0:15) d(0:7) reads d(0:15) d(0:7) 2 sets d(16:31) d(7:15) reads d(16:31) d(7:15) 3 sets d(16:23) reads d(16:23) 4 sets d(24:31) reads d(24:31) 2 4 2 4 receive register loads value of serial- parallel coverter reads receive register, strobe rg ** 11 into receive register reads d(0:15) d(0:7) 2 --- --- reads d(16:31) d(7:15) 3 --- --- reads d(32:47) d(16:23) 4 --- --- reads d(24:31) 5 --- --- reads d(32:39) 6 --- --- reads d(40:47) 1 1 1 - 3 ** 2 - 6 ** 2 --- --- --- --- --- multifunction register (mfr) sets mfr reads mfr 3 1 sets d(0:15) d(0:7) reads d(0:15) d(0:7) 2 sets d(16:31) d(7:15) reads d(16:31) d(7:15) 3 sets d(16:23) reads d(16:23) 4 sets d(24:31) reads d(24:31) 2 4 2 4 control register sets control register reads control register 4 1 sets d(0:15) d(0:7) reads d(0:15) d(0:7) 2 sets d(16:31) d(7:15) reads d(16:31) d(7:15) 3 sets d(16:23) reads d(16:23) 4 sets d(24:31) reads d(24:31) 2 4 2 4 status register software strobe reads status register with reset 5 1 --- --- reads d(0:7) d(0:7) 1 1 1 1 interrupt mask sets interrupt mask reads interrupt mask 6 1 sets d(0:7) d(0:7) reads d(0:7) d(0:7) 1 1 1 1 timer + status sets timer register reads status register without reset 7 1 sets d(0:15) d(0:7) lesen d(0:7) d(0:7) 2 sets d(7:15) --- --- 3 ---- --- --- --- 4 ---- --- --- --- 1 2 1 1 table 7: parallel port mode ?intel?: autoincrement (mot= low, ainc = high) ** the number of required access cycles is determined by the width that has been preset for the data word to be received (control register (bit 24:29)). .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 31 of 45 data sheet MMI4832 1.3 motorola, no autoincrement a(4:2) a(1:0) resource 16-bit write port 8-bit port 16-bit read port 8-bit port send register sets send register reads send register 0 0 sets d(16:31) d(24:31) reads d(16:31) d(24:31) 1 sets d(16:23) reads d(16:23) 2 sets d(0:15) d(7:15) reads d(0:15) d(7:15) 3 sets d(0:7) reads d(0:7) 2 4 2 4 receive register loads value of serial- parallel converter reads receive register, strobe rg 10 into receive register reads d(32:47) d(40:47) 1 --- --- reads d(32:39) 2 --- --- reads d(16:31) d(24:31) 3 --- --- reads d(16:23) 1 1 receive register reads receive register, strobe rg *** 2 0 --- --- reads d(0:15) d(7:15) 1 --- --- reads d(0:7) 1 - 3 ** 2 - 6 ** multifunction register (mfr) sets mfr reads mfr 3 0 sets d(16:31) d(24:31) reads d(16:31) d(24:31) 1 sets d(16:23) reads d(16:23) 2 sets d(0:15) d(7:15) reads d(0:15) d(7:15) 3 sets d(0:7) reads d(0:7) 2 4 2 4 control register sets control register reads control register 4 0 sets d(16:31) d(24:31) reads d(16:31) d(24:31) 1 sets d(16:23) reads d(16:23) 2 sets d(0:15) d(7:15) reads d(0:15) d(7:15) 3 sets d(0:7) reads d(0:7) 2 4 2 4 status register software strobe reads status register with reset 5 0 --- reads d(0:7) d(0:7) 1 1 1 1 interrupt mask sets interrupt mask reads interrupt mask 6 0 sets d(0:7) d(0:7) reads d(0:7) d(0:7) 1 1 1 1 timer + status sets timer register reads status register without reset 7 0 sets d(0:15) d(7:15) reads d(0:7) d(0:7) 1 sets d(0:7) --- --- 2 ---- --- --- --- 3 ---- --- --- --- 1 2 1 1 table 8: parallel-port mode ?motorola?: no autoincrement (mot = high, ainc = low) .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 32 of 45 data sheet MMI4832 reads receive register by the example of a 24-bit long data word: a(4:2) a(1:0) resource 16-bit write port 8-bit port 16-bit read port 8-bit port receive register loads value of serial- parallel converter reads receive register, strobe rg 11 into receive register reads d(16:23) d(16:23) 2 --- --- reads d(0:15) d(7:15) 3 --- --- reads d(0:7) 1 1 2 3 1.4 motorola, with autoincrement a(4:2) access resource 16-bit write port 8-bit port 16-bit read port 8-bit port send register sets send register reads send register 0 1 sets d(16:31) d(24:31) reads d(16:31) d(24:31) 2 sets d(0:15) d(16:23) reads d(0:15) d(16:23) 3 sets d(7:15) reads d(7:15) 4 sets d(0:7) reads d(0:7) 2 4 2 4 receive register loads value of serial- parallel converter reads receive register, strobe rg 11 into receive register reads d(32:47) d(40:47) 2 --- --- reads d(16:31) d(32:39) 3 --- --- reads d(0:15) d(24:31) 4 --- --- reads d(16:23) 5 --- --- reads d(7:15) 6 --- --- reads d(0:7) 1 1 1 - 3 * * 2 - 6 * * 2 --- --- --- --- --- --- multifunction register (mfr) sets mfr reads mfr 3 1 sets d(16:31) d(24:31) reads d(16:31) d(24:31) 2 sets d(0:15) d(16:23) reads d(0:15) d(16:23) 3 sets d(7:15) reads d(7:15) 4 sets d(0:7) reads d(0:7) 2 4 2 4 control register sets control register reads control register 4 1 sets d(16:31) d(24:31) reads d(16:31) d(24:31) 2 sets d(0:15) d(16:23) reads d(0:15) d(16:23) 3 sets d(7:15) reads d(7:15) 4 sets d(0:7) reads d(0:7) 2 4 2 4 5 status register software strobe reads status register with reset 1 --- --- reads d(0:7) d(0:7) 1 1 1 1 6 interrupt mask sets interrupt mask reads interrupt mask 1 sets d(0:7) d(0:7) reads d(0:7) d(0:7) 1 1 1 1 7timer + status sets timer register reads status register without reset 1 sets d(0:15) d(7:15) reads d(0:7) d(0:7) 2 sets d(0:7) --- --- 3 ---- --- --- --- 4 ---- --- --- --- 1 2 1 1 table 9: parallel-port mode ?motorola?: autoincrement (mot= high, ainc = high) .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 33 of 45 data sheet MMI4832 ** the number of required access cycles is determined by the width that has been preset for the data word to be received (control register (bit 24:29)). working in ?motorola? or ?autoincrement? mode (mot=1 and ainc=1 resp.), the MMI4832 w ill at first read or write the most significant byte or word, whereas the least significant byte or word is read or written after ?n? access cycles have been completed (depending on word length). example: 24-bit long data word being received a(4:2) access resource 16-bit write port 8-bit port 16-bit read port 8-bit port receive register loads value of serial- parallel converter reads receive register, strobe rg 11 into receive register reads d(16:23) d(16:23) 2 --- --- reads d(0:15) d(7:15) 3 --- --- reads d(0:7) 1 1 2 3 2 application examples 2.1 isa figure 2-1 shows a block diagram for an MMI4832 applied as an interface for measuring systems which are equipped with endat-interface and isa bus. figure 2-1: application example: MMI4832 with endat-interface , measuring system and isa bus 74 als 245 d0 ...d15 MMI4832 a1...a3 data_dv sn75176b d0 d15 /ir6 /rd /cs /wr tclk sd0 ...sd15 gal 16v8 2 x wr_m /res 74 als 688 sa0 ...sa9 sa4 ...sa9 res_m cs_m rd_m cs_m rd_m res_m jp iow\, ior\, resdrv clk /ir7 ainc mot /str iochrdy cmd wr_m : 74 als 245 sa0 ...sa3 endat encoder clk+ clk - crystal oscillator +5v gnd iocs16 m16 strobe input timer, switch de de /re d sn75176b de /re d +5v d+ d- data_rc r i s a - b u s a1 .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 34 of 45 data sheet MMI4832 2.2 transceivers figure 2-2 shows a recommended transceiver wiring interconnections diagram. MMI4832 data_dv sn75176b d0 d15 /ir6 /rd /cs /wr tclk /res cs_m rd_m res_m clk /ir7 ainc mot /str cmd wr_m : encoder with endat- interface clk+ clk - +5v gnd m16 de de /re d sn75176b de /re d +5v d+ d- data_rc r < > > a1 120 5v 1 k 1 k 2 x 330 pf empfohlene eingangsbeschaltung figure 2-2: wiring interconnections for transceivers 3 programming examples 3.1 reading of parameter ?data word length of encoder? (endat mode) file name: roc413pl.c #include #include int krg_rg_l; int krg_rg_h; int sen_rg_l; int sen_rg_h; int empf_rg_l; int empf_rg_h; int sta_rg; main () { int i; /* status clearing */ outpw (0x302,0x74); sta_rg=inpw (0x300); .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 35 of 45 data sheet MMI4832 /* control rg */ outpw (0x302,0x70); outpw (0x300,0x3201); outpw (0x300,0x0000); outpw (0x302,0x70); krg_rg_l=inpw (0x300); krg_rg_h=inpw (0x300); printf ("krg : %4x", krg_rg_h); printf (" %4x\n", krg_rg_l); /* send rg ? selection of encoder memory range */ outpw (0x302,0x60); outpw (0x300,0x0000); outpw (0x300,0x0e00); outpw (0x302,0x60); sen_rg_l=inpw (0x300); sen_rg_h=inpw (0x300); printf ("sen : %4x", sen_rg_h); printf (" %4x\n", sen_rg_l); /* software strobe (start of 1st transfer) */ outpw (0x302,0x74); outpw (0x300,0x0000); for (i=0; i<20000; i+=1) printf ("wait\r"); /* status clearing */ outpw (0x302,0x74); sta_rg=inpw (0x300); /* send rg ? selection of parameter addr ess (inquiry about encoder bit length) */ outpw (0x302,0x60); outpw (0x300,0x0000); outpw (0x300,0x2300); outpw (0x302,0x60); sen_rg_l=inpw (0x300); sen_rg_h=inpw (0x300); printf ("sen : %4x", sen_rg_h); printf (" %4x\n", sen_rg_l); .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 36 of 45 data sheet MMI4832 /* software strobe (start of 2nd transfer) */ outpw (0x302,0x74); outpw (0x300,0x0000); for (i=0; i<20000; i+=1) printf ("wait\r"); /* reading of receive rg (received value is encoder bit length) */ outpw (0x302,0x64); empf_rg_l=inpw (0x300); empf_rg_h=inpw (0x300); outpw (0x302,0x74); sta_rg=inpw (0x300); printf ("sta: %4x ", sta_rg); printf ("empf: %4x", empf_rg_h); printf (" %4x\r", empf_rg_l); } 3.2 position value transfer with 13- bit encoder roc413 (endat mode) file name: roc413_m.c #include #include int krg_rg_l; int krg_rg_h; int sen_rg_l; int sen_rg_h; int empf_rg_l; int empf_rg_h; int sta_rg; main () { int i; /* status clearing */ outpw (0x302,0x74); sta_rg=inpw (0x300); .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 37 of 45 data sheet MMI4832 /* control rg */ outpw (0x302,0x70); outpw (0x300,0x3201); outpw (0x300,0x0d00); outpw (0x302,0x70); krg_rg_l=inpw (0x300); krg_rg_h=inpw (0x300); printf ("krg : %4x", krg_rg_h); printf (" %4x\n", krg_rg_l); /* send rg */ outpw (0x302,0x60); outpw (0x300,0x0000); outpw (0x300,0x0700); outpw (0x302,0x60); sen_rg_l=inpw (0x300); sen_rg_h=inpw (0x300); printf ("sen : %4x", sen_rg_h); printf (" %4x\n", sen_rg_l); /* timer start */ outpw (0x302,0x7c); outpw (0x300,0x800); /* receive rg */ while (!kbhit()) { outpw (0x302,0x64); empf_rg_l=inpw (0x300); empf_rg_h=inpw (0x300); outpw (0x302,0x74); sta_rg=inpw (0x300); outpw (0x302,0x70); krg_rg_l=inpw (0x300); krg_rg_h=inpw (0x300); printf ("krg : %4x", krg_rg_h); printf (" %4x ", krg_rg_l); printf ("sta: %4x ", sta_rg); printf ("empf: %4x", empf_rg_h); printf (" %4x\r", empf_rg_l); } } .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 38 of 45 data sheet MMI4832 3.3 position value transfer with 25- bit encoder eqn1325 (endat mode) file name: eqn1325m.c #include #include int krg_rg_l; int krg_rg_h; int sen_rg_l; int sen_rg_h; int empf_rg_l; int empf_rg_h; int sta_rg; main () { int i; /* status clearing */ outpw (0x302,0x74); sta_rg=inpw (0x300); /* control rg */ outpw (0x302,0x70); outpw (0x300,0x3201); outpw (0x300,0x1900); outpw (0x302,0x70); krg_rg_l=inpw (0x300); krg_rg_h=inpw (0x300); printf ("krg : %4x", krg_rg_h); printf (" %4x\n", krg_rg_l); /* send rg */ outpw (0x302,0x60); outpw (0x300,0x0000); outpw (0x300,0x0700); outpw (0x302,0x60); sen_rg_l=inpw (0x300); sen_rg_h=inpw (0x300); printf ("sen : %4x", sen_rg_h); printf (" %4x\n", sen_rg_l); .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 39 of 45 data sheet MMI4832 /* timer start */ outpw (0x302,0x7c); outpw (0x300,0x800); /* receive rg */ while (!kbhit()) { outpw (0x302,0x64); empf_rg_l=inpw (0x300); empf_rg_h=inpw (0x300); outpw (0x302,0x74); sta_rg=inpw (0x300); outpw (0x302,0x70); krg_rg_l=inpw (0x300); krg_rg_h=inpw (0x300); printf ("krg : %4x", krg_rg_h); printf (" %4x ", krg_rg_l); printf ("sta: %4x ", sta_rg); printf ("empf: %4x", empf_rg_h); printf (" %4x\r", empf_rg_l); } } 3.4 incremental measured-value transfer with hardware strobe file name: hw_str.c #include #include int krg_rg_l; int krg_rg_h; int empf_rg_l; int empf_rg_h; int sta_rg; main () { int i; /* clearing of status rg */ outpw (0x302,0x74); sta_rg=inpw (0x300); .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 40 of 45 data sheet MMI4832 /* control rg*/ outpw (0x302,0x70); outpw (0x300,0x0381); outpw (0x300,0x2000); outpw (0x302,0x70); krg_rg_l=inpw (0x300); krg_rg_h=inpw (0x300); printf ("krg : %4x", krg_rg_h); printf (" %4x\n", krg_rg_l); /* timer start */ outpw (0x302,0x7c); outpw (0x300,0x0800); /* receive rg */ while (!kbhit()) { /* reading of receive rg (ct content is read via receive rg) */ outpw (0x302,0x64); empf_rg_l=inpw (0x300); empf_rg_h=inpw (0x300); outpw (0x302,0x74); sta_rg=inpw (0x300); printf ("sta: %4x ", sta_rg); printf ("empf: %4x", empf_rg_h); printf (" %4x\r", empf_rg_l); } } 3.5 incremental measured-value transfer with reference strobe file name: ref_str.c #include #include int krg_rg_l; int krg_rg_h; int empf_rg_l; int empf_rg_h; int sta_rg; main () { int i; .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 41 of 45 data sheet MMI4832 /* control rg */ outpw (0x302,0x70); outpw (0x300,0x0382); outpw (0x300,0x2001); outpw (0x302,0x70); krg_rg_l=inpw (0x300); krg_rg_h=inpw (0x300); printf ("krg : %4x", krg_rg_h); printf (" %4x\n", krg_rg_l); /* receive rg */ while (!kbhit()) { outpw (0x302,0x64); empf_rg_l=inpw (0x300); empf_rg_h=inpw (0x300); outpw (0x302,0x7c); sta_rg=inpw (0x300); printf ("sta: %4x ", sta_rg); printf ("empf: %4x", empf_rg_h); printf (" %4x\r", empf_rg_l); } } 3.6 incremental measured-value transfer with add offset file name: add_off.c #include #include int pre_rg_l; int pre_rg_h; int ref_rg_l; int ref_rg_h; int krg_rg_l; int krg_rg_h; int empf_rg_l; int empf_rg_h; int sta_rg; main () { int i; .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 42 of 45 data sheet MMI4832 /* clearing of status rg */ outpw (0x302,0x74); sta_rg=inpw (0x300); /* clearing old counter value (counter+receive rg) */ outpw (0x302,0x60); outpw (0x300,0x0000); outpw (0x300,0x0000); outpw (0x302,0x64); outpw (0x300,0x0000); outpw (0x302,0x74); outpw (0x300,0x0000); /* control rg*/ /* add-offset bit set for ref. rg to be readable */ /* -> otherwise test bits contained under this address (e.g. eclk automat) */ outpw (0x302,0x70); outpw (0x300,0x0584); outpw (0x300,0x2000); outpw (0x302,0x70); krg_rg_l=inpw (0x300); krg_rg_h=inpw (0x300); printf ("krg : %4x", krg_rg_h); printf (" %4x\n", krg_rg_l); /* offset rg */ outpw (0x302,0x6c); outpw (0x300,0x4444); outpw (0x300,0x3333); outpw (0x302,0x6c); ref_rg_l=inpw (0x300); ref_rg_h=inpw (0x300); printf ("off : %4x", ref_rg_h); printf (" %4x\n", ref_rg_l); .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 43 of 45 data sheet MMI4832 /* preset rg */ outpw (0x302,0x60); outpw (0x300,0x3333); outpw (0x300,0xcccc); outpw (0x302,0x60); pre_rg_l=inpw (0x300); pre_rg_h=inpw (0x300); printf ("pre : %4x", pre_rg_h); printf (" %4x\n", pre_rg_l); /* loading preset into counter */ outpw (0x302,0x64); outpw (0x300,0x0000); /* receive rg */ while (!kbhit()) { /* sw strobe counter -> str-rg */ outpw (0x302,0x74); outpw (0x300,0x0000); /* reading receive rg (ct content is read via receive-rg) */ outpw (0x302,0x64); empf_rg_l=inpw (0x300); empf_rg_h=inpw (0x300); outpw (0x302,0x6c); ref_rg_l=inpw (0x300); ref_rg_h=inpw (0x300); outpw (0x302,0x7c); sta_rg=inpw (0x300); printf ("sta: %4x ", sta_rg); printf ("empf: %4x", empf_rg_h); printf (" %4x ", empf_rg_l); printf ("empf + off: %4x", ref_rg_h); printf (" %4x\r", ref_rg_l); } } .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003-04-17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 44 of 45 data sheet MMI4832 3.7 measured-value transfer with ssi #include #include int krg_rg_l1; int krg_rg_h1; int sen_rg_l1; int sen_rg_h1; int empf_rg1; int sta_rg1; int int_rg; main () { int i; /* clearing of status rg */ outpw (0x302,0x74); /* kanal1 */ sta_rg1=inpw (0x300); /* control rg channel1 */ outpw (0x302,0x70); outpw (0x300,0x3201); outpw (0x300,0x4d00); outpw (0x302,0x70); krg_rg_l1=inpw (0x300); krg_rg_h1=inpw (0x300); printf ("krg1 : %4x", krg_rg_h1); printf (" %4x\n", krg_rg_l1); /* timer start */ outpw (0x302,0x7c); outpw (0x300,0x1000); /* receive rg */ while (!kbhit()) { outpw (0x302,0x64); empf_rg1=inpw (0x300); outpw (0x302,0x74); sta_rg1=inpw (0x300); outpw (0x302,0x70); krg_rg_l1=inpw (0x300); krg_rg_h1=inpw (0x300); .com .com .com .com 4 .com u datasheet
version nr. edition confirmed 1 v 2.1 2003/04/17 all information contained in this document relate to the technology available on date of release and is preliminary. mazet gmbh reserves the right to technological changes of devices and components described in this documentation. doc. nr: db-99-031e page 45 of 45 data sheet MMI4832 printf ("krg1: %4x", krg_rg_h1); printf (" %4x ", krg_rg_l1); printf ("sta1: %2x", sta_rg1); printf (" empf1: %4x \r", empf_rg1); } } 3.8 setting of endat transfer rate table 10 shows the control register (17:8) values to be selected for recommended endat transfer rates: bit(17:8) /hex bit(17:8) /dec sampling rate 00inactive 332 mhz 661 mhz 3c 60 200 khz 78 120 100 khz table 10 : endat transfer rates 4 faq?s for further information and answers to frequently asked questions (faq?s), you are referred to mazet?s websites at: http://www.mazet.de we will also be glad to send you supporting material or provide answers on special request. for further information, pleas feel free to contact: mazet gmbh sales office: dr. winfried mahler g?schwitzer stra?e 32 07745 jena germany phone: +49 3641 2809-0 fax: +49 3641 2809-12 e-mail: mahler@mazet.de url: http://www.mazet.de .com .com .com 4 .com u datasheet

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