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rev: 2.06 8/2000 1/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. nobl is a trademark of cypress semiconductor corp.. ntram is a trademark of samsung electronics co.. zbt is a trademark of integ rated device technology, inc. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 16mb pipelined and flow through synchronous nbt sram 225 mhz ? 133 mhz 2.5 v v dd 2.5 v or 3.3 v i/o 100-pin tqfp commercial temp industrial temp features ? user-configurable pipeline and flow through mode ? nbt (no bus turn around) functionality allows zero wait read-write-read bus utilization; fully pin-compatible with both pipelined and flow through ntram?, nobl? and zbt? srams ? 2.5 v +10%/ ? 5% core power supply ? 2.5 v or 3.3 v i/o supply ? 3.3 v-compatible inputs ? lbo pin for linear or interleave burst mode ? pin compatible with 2m, 4m, and 8m devices ? byte write operation (9-bit bytes) ? 3 chip enable signals for easy depth expansion ? clock control, registered, address, data, and control ? zz pin for automatic power-down ? jedec-standard 100-lead tqfp package functional description the gs 8160z 18/36 t is a 16mbit synchronous static sram. gsi's nbt srams, like zbt, ntram, nobl or other pipelined read/double late write or flow through read/single late write srams, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. burst order control ( lbo ) must be tied to a power rail for proper operation. asynchronous inputs include the sleep mode enable (zz) and output enable. output enable can be used to override the synchronous control of the output drivers and turn the ram's output drivers off at any time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation required by asynchronous srams and simplifies input signal timing. the gs 8160z 18/36 t may be configured by the user to operate in pipeline or flow through mode. operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. for read cycles, pipelined sram output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. the gs 8160z 18/36 t is implemented with gsi's high performance cmos technology and is available in a jedec- standard 100-pin tqfp package. -225 - 200 - 180 - 166 - 150 - 133 unit pipeline 3-1-1-1 tcycle t kq i dd 4.4 2.5 410 5 3.0 375 5.5 3.2 340 6 3.5 310 6.6 3.8 290 7.5 4.0 260 ns ns ma flow through 2-1-1-1 t kq tcycle i dd 7.0 8.5 255 7.5 10 235 8 10 235 8.5 10 235 10 10 235 11 15 220 ns ns ma a b c d e f r w r w r w q a d b q c d d q e q a d b q c d d q e clock address read/write flow through data i/o pipelined data i/o flow through and pipelined nbt sram back-to-back read/write cycles
rev: 2.06 8/2000 2/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 gs8160z18t pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b1 dq b2 v ss v ddq dq b3 dq b4 ft v dd v dd v ss dq b5 dq b6 v ddq v ss dq b7 dq b8 dq b9 v ss v ddq v ddq v ss dq a8 dq a7 v ss v ddq dq a6 dq a5 v ss nc v dd zz dq a4 dq a3 v ddq v ss dq a2 dq a1 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 n c n c v s s v d d n c n c a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 n c n c b b b a e 3 c k w c k e v d d v s s g a d v a 1 8 a 1 7 a 8 a 9 a 1 5 1m x 18 top view dq a9 a 19 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
rev: 2.06 8/2000 3/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 gs8160z36t pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 ft v dd v dd v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss nc v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 n c n c v s s v d d n c n c a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 b d b c b b b a e 3 c k w c k e v d d v s s g a d v a 1 8 a 1 7 a 8 a 9 a 1 5 512k x 36 top view dq b5 dq b9 dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 dq a9 dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 dq d9 dq c5 dq c9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
rev: 2.06 8/2000 4/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 100 pin tqfp pin descriptions pin location symbol type description 37, 36 a 0 , a 1 in burst address inputs; preload the burst counter 35, 34, 33, 32, 100, 99, 84, 83, 82, 81, 44, 45, 46,47, 48, 49, 50 a 2 ? a 18 in address inputs 80 a 19 in address input (x18 version only) 89 ck in clock input signal 93 b a in byte write signal for data inputs dq a1 -dq a9 ; active low 94 b b in byte write signal for data inputs dq b1 -dq b9 ; active low 95 b c in byte write signal for data inputs dq c1 -dq c9 ; active low (x36 versions only) 96 b d in byte write signal for data inputs dq d1 -dq d9 ; active low (x36 versions only) 88 w in write enable; active low 98 e 1 in chip enable; active low 97 e 2 in chip enable; active high. for self decoded depth expansion 92 e 3 in chip enable; active low. for self decoded depth expansion 86 g in output enable; active low 85 adv in advance/ load ; burst address counter control pin 87 cke in clock input buffer enable; active low 58, 59, 62,63, 68, 69, 72, 73, 74 dq a1 ? dq a9 i/o byte a data input and output pins (x18 version only) 8, 9, 12, 13, 18, 19, 22, 23, 24 dq b1 ? dq b9 i/o byte b data input and output pins (x18 version only) 51, 52, 53, 56, 57, 75, 78, 79, 1, 2, 3, 6, 7, 25, 28, 29, 30 nc ? no connect (x18 version only) 51, 52, 53, 56, 57, 58, 59, 62,63 dq a1 ? dq a9 i/o byte a data input and output pins (x36 versions only) 68, 69, 72, 73, 74, 75, 78, 79, 80 dq b1 ? dq b9 i/o byte b data input and output pins (x36 versions only) 1, 2, 3, 6, 7, 8, 9, 12, 13 dq c1 ? dq c9 i/o byte c data input and output pins (x36 versions only) 18, 19, 22, 23, 24, 25, 28, 29, 30 dq d1 ? dq d9 i/o byte d data input and output pins (x36 versions only) 64 zz in power down control; active high 14 ft in pipeline/flow through mode control; active low 31 lbo in linear burst order; active low 15, 16, 41, 65, 91 v dd in 3.3 v power supply 5,10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss in ground 4, 11, 20, 27, 54, 61, 70, 77 v ddq in 3.3 v output power supply for noise reduction 38, 39, 42, 43, 66 nc ? no connect
rev: 2.06 8/2000 5/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 gs8160z18/36 nbt sram functional block diagram k s a 1 s a 0 b u r s t c o u n t e r l b o a d v m e m o r y a r r a y e 3 e 2 e 1 g w b d b c b b b a c k c k e d q f t d q a ? d q n k s a 1 ? s a 0 ? d q m a t c h w r i t e a d d r e s s r e g i s t e r 2 w r i t e a d d r e s s r e g i s t e r 1 w r i t e d a t a r e g i s t e r 2 w r i t e d a t a r e g i s t e r 1 k k k k k k s e n s e a m p s w r i t e d r i v e r s r e a d , w r i t e a n d d a t a c o h e r e n c y c o n t r o l l o g i c f t a 0 ? a n
rev: 2.06 8/2000 6/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 functional details clocking deassertion of the clock enable ( cke ) input blocks the clock input from reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observe clock enable set-up or hold requirements will result in erratic operation. pipeline mode read and write operations all inputs (with the exception of output enable, linear burst order and sleep) are synchronized to rising clock edges. single cy cle read and write operations must be initiated with the advance/ load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting all three of the chip enable inputs ( e 1 , e 2 and e 3 ). deassertion of any one of the enable inputs will deactivate the device. read operation is initiated when the following conditions are satisfied at the rising edge of clock: cke is asserted low, all three chip enables ( e 1 , e 2, and e 3 ) are active, the write enable input signals w is deasserted high, and adv is asserted low. the address presented to the address inputs is latched in to address register and presented to the memory core and control logic. the contro l logic determines that a read access is in progress and allows the requested data to propagate to the input of the output registe r. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operation occurs when the ram is selected, cke is active, and the write input is sampled low at the rising edge of clock. the byte write enable inputs ( b a , b b , b c, & b d ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. the pipelined nbt sram provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). at the first rising edge of clock, enable, write, byte write(s), and address are registered. the data in associated with that addre ss is required at the third rising edge of clock. flow through mode read and write operations operation of the ram in flow through mode is very similar to operations in pipeline mode. activation of a read cycle and the use of the burst address counter is identical. in flow through mode the device may begin driving out new data immediately after new address are clocked into the ram, rather than holding new data until the following (second) clock edge. therefore, in flow through mode the read pipeline is one cycle shorter than in pipeline mode. write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving t he ability to turn the bus from reads to writes without inserting any dead cycles. while the pipelined nbt rams implement a double late write protocol, in flow through mode a single late write protocol mode is observed. therefore, in flow through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. function w b a b b b c b d read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h
rev: 2.06 8/2000 7/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 synchronous truth table operation type address e 1 e 2 e 3 zz adv w bx g cke ck dq notes deselect cycle, power down d none h x x l l x x x l l-h high-z deselect cycle, power down d none x x h l l x x x l l-h high-z deselect cycle, power down d none x l x l l x x x l l-h high-z deselect cycle, continue d none x x x l h x x x l l-h high-z 1 read cycle, begin burst r external l h l l l h x l l l-h q read cycle, continue burst b next x x x l h x x l l l-h q 1,10 nop/read, begin burst r external l h l l l h x h l l-h high-z 2 dummy read, continue burst b next x x x l h x x h l l-h high-z 1,2,10 write cycle, begin burst w external l h l l l l l x l l-h d 3 write cycle, continue burst b next x x x l h x l x l l-h d 1,3,10 nop/write abort, begin burst w none l h l l l l h x l l-h high-z 2,3 write abort, continue burst b next x x x l h x h x l l-h high-z 1,2,3,10 clock edge ignore, stall current x x x l x x x x h l-h - 4 sleep mode none x x x h x x x x x x high-z notes: 1. continue burst cycles, whether read or write, use the same control inputs. a deselect continue cycle can only be entered into if a dese- lect cycle is executed first. 2. dummy read and write abort can be considered nops because the sram performs no operation. a write abort occurs when the w pin is sampled low but no byte write pins are active so no write operation is performed. 3. g can be wired low to minimize the number of control signals provided to the sram. output drivers will automatically turn off dur ing write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensures all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminated for all burst continue cycles.
rev: 2.06 8/2000 8/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 deselect new read new write burst read burst write w r b r b w d d b b w r d b w r d d pipeline and flow through read write control state diagram current state (n) next state (n+1) transition ? input command code key notes: 1. the hold command ( cke low) is not shown because it prevents any state change. 2. w, r, b and d represent input command codes , as indicated in the synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ? ? ? current state and next state definition for pipeline and flow through read/write control state diagram w r
rev: 2.06 8/2000 9/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 intermediate intermediate intermediate intermediate intermediate intermediate high z (data in) data out (q valid) high z b w b r b d r w r w d d pipeline mode data i/o state diagram current state (n) next state (n+2) transition ? input command code key transition intermediate state (n+1) notes: 1. the hold command ( cke low) is not shown because it prevents any state change. 2. w, r, b , and d represent input command codes as indicated in the truth tables. clock (ck) command current state intermediate ? n n+1 n+2 n+3 ? ? ? current state and next state definition for pipeline mode data i/o state diagram next state state
rev: 2.06 8/2000 10/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command ( cke low) is not shown because it prevents any state change. 2. w, r, b and d represent input command codes as indicated in the truth tables. flow through mode data i/o state diagram clock (ck) command current state next state ? n n+1 n+2 n+3 ? ? ? current state and next state definition for: pipeline and flow through read write control state diagram
rev: 2.06 8/2000 11/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 burst cycles although nbt rams are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. nbt srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the counter generated address to read or write the sram. the starting address for the first cycle in a burst cycle series is loaded into the sram by driving the adv pin low, i nto load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the linear burst order pin ( lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pin tied high, interleaved burst sequence is selected. see the tabl es below for details. note: there are pull-up device s on the lbo and ft pin s and a pull-down device on the zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences bpr 1999.05.18 sleep mode during normal operation, zz must be pulled low, either by the user or by it?s internal pull down resistor. when zz is pulled hig h, the sram will enter a power sleep mode after 2 cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram operates normally after 2 cycles of wake up time. mode pin functions mode name pin name state function burst order control lbo l linear burst h or nc interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 2.06 8/2000 12/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an asynchronous, active high input that causes the device to enter sleep mod e. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiate d until valid pending operations are completed. similarly, when exiting sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram designing for compatibility the gsi nbt srams offer users a configurable selection between flow through mode and pipeline mode via the ft signal found on pin 14 . not all vendors offer this option, however most mark pin 14 as v dd or v ddq on pipelined parts and v ss on flow through parts. gsi nbt srams are fully compatible with these sockets. pin 66, a no connect (nc) on gsi?s gs8160z18/36 nbt sram, the parity error open drain output on gsi?s gs8161z18/36 nbt sram, is often marked as a power pin on other vendor?s nbt compatible srams. specifically, it is marked v dd or v ddq on pipelined parts and v ss on flow through parts. users of gsi nbt devices who are not actually using the bytesafe? parity feature may want to design the board site for the ram with pin 66 tied high through a 1k ohm resistor in pipeline mode applications or tied low in flow through mode applications in order to keep the option to use non-configurable devices open. by using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to gsi?s bytesafe nbt srams (gs8161z18/36), featuring parity error detection and jtag boundary scan, will be ready for connection to the active low, open drain parity error output driver at pin 66 on gsi?s tqfp bytesafe rams. ck zz tzzr tzzh tzzs ~ ~ ~ ~ sleep
rev: 2.06 8/2000 13/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recommended operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an extended period of time, may affect reliability of this component. note: 1. the part number of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v dd +2 v with a pulse width not to exceed 20% tkc. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 3.6 v v ddq voltage in v ddq pins ? 0.5 to 3.6 v v ck voltage on clock input pin ? 0.5 to 6 v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( 3.6 v max.) v v in voltage on other input pins ? 0.5 to 3.6 v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c recommended operating conditions parameter symbol min. typ. max. unit notes supply voltage v dd 2.375 2.5 2.7 v i/o supply voltage v ddq 2.375 2.5 3.6 v input high voltage v ih 0.7 * v dd ? 3.6 v 1 input low voltage v il ? 0.3 ? 0.3 * vdd v 1 ambient temperature (commercial range versions) t a 0 25 70 c 2 ambient temperature (industrial range versions) t a ? 40 25 85 c 2
rev: 2.06 8/2000 14/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 note: this parameter is sample tested. notes: 1. junction temperature is a function of sram power dissipation, package thermal resistance, mounting board temperature, ambient. t emper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 capacitance (t a = 25 o c , f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit control input capacitance c i v dd = 2.5 v 3 4 pf input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r q ja 40 c/w 1,2 junction to ambient (at 200 lfm) four r q ja 24 c/w 1,2 junction to case (top) ? r q jc 9 c/w 3 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 2.06 8/2000 15/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz 4. device is deselected as defined by the truth table. ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz input current i in zz v dd 3 v in 3 v ih 0 v v in v ih ? 1 ua ? 1 ua 1 ua 300 ua mode pin input current i in m v dd 3 v in 3 v il 0 v v in v il ? 300 ua ? 1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v dq vt = 1.25 v 50 w 30pf * dq 2.5 v output load 1 output load 2 225 w 225 w 5pf * * distributed test jig capacitance
rev: 2.06 8/2000 16/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 o p e r a t i n g c u r r e n t s p a r a m e t e r t e s t c o n d i t i o n s m o d e s y m b o l - 2 2 5 - 2 0 0 - 1 8 0 - 1 6 6 - 1 5 0 - 1 3 3 u n i t 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c o p e r a t i n g c u r r e n t d e v i c e s e l e c t e d ; a l l o t h e r i n p u t s 3 v i h o r v i l o u t p u t o p e n ( x 3 6 ) p i p e l i n e i d d i d d q 3 3 5 7 4 3 4 5 8 4 3 0 3 6 6 3 1 3 7 6 2 7 8 5 9 2 8 8 6 9 2 6 0 5 5 2 7 0 6 5 2 4 0 5 0 2 5 0 6 0 2 1 8 4 4 2 2 8 5 4 m a f l o w t h r o u g h i d d i d d q 1 9 9 3 9 2 0 9 4 9 1 7 7 3 3 1 8 7 4 3 1 7 7 3 3 1 8 7 4 3 1 7 7 3 3 1 8 7 4 3 1 7 7 3 3 1 8 7 4 3 1 3 4 2 2 1 4 4 3 2 m a ( x 1 8 ) p i p e l i n e i d d i d d q 3 1 0 3 7 3 2 0 4 7 2 8 1 3 3 2 9 1 4 3 2 5 8 3 0 2 6 8 4 0 2 4 2 2 7 2 5 2 3 7 2 2 3 2 5 2 3 3 3 5 2 0 4 2 2 2 1 4 3 2 m a f l o w t h r o u g h i d d i d d q 1 8 6 1 9 1 9 6 2 9 1 6 6 1 7 1 7 6 2 7 1 6 6 1 7 1 7 6 2 7 1 6 6 1 7 1 7 6 2 7 1 6 6 1 7 1 7 6 2 7 1 2 7 1 1 1 3 7 2 1 m a s t a n d b y c u r r e n t z z 3 v d d ? 0 . 2 v ? p i p e l i n e i s b 1 0 2 0 1 0 2 0 1 0 2 0 1 0 2 0 1 0 2 0 1 0 2 0 m a f l o w t h r o u g h i s b 1 0 2 0 1 0 2 0 1 0 2 0 1 0 2 0 1 0 2 0 1 0 2 0 m a d e s e l e c t c u r r e n t d e v i c e d e s e l e c t e d ; a l l o t h e r i n p u t s 3 v i h o r v i l ? p i p e l i n e i d d 8 0 8 5 7 5 8 0 7 0 7 5 6 4 7 0 6 0 6 5 5 0 5 5 m a f l o w t h r o u g h i d d 6 0 6 5 5 0 5 5 5 0 5 5 5 0 5 5 5 0 5 5 4 5 5 0 m a
rev: 2.06 8/2000 17/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 ac electrical characteristics parameter symbol - 225 - 200 - 180 - 166 - 150 - 133 unit min max min max min max min max min max min max pipeline clock cycle time tkc 4.4 ? 5.0 ? 5.5 ? 6.0 ? 6.7 ? 7.5 ? ns clock to output valid tkq ? 2.5 ? 3.0 ? 3.2 ? 3.5 ? 3.8 ? 4.0 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow through clock cycle time tkc 8.5 ? 10.0 ? 10.0 ? 10.0 ? 10.0 ? 15.0 ? ns clock to output valid tkq ? 7.0 ? 7.5 ? 8.0 ? 8.5 ? 10.0 ? 11.0 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? 1.5 ? 1.7 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.7 ? 2 ? ns clock to output in high-z thz 1 1.5 2.5 1.5 3.0 1.5 3.2 1.5 3.5 1.5 3.8 1.5 4.0 ns g to output valid toe ? 2.5 ? 3.2 ? 3.2 ? 3.5 ? 3.8 ? 4.0 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.5 ? 3.0 ? 3.2 ? 3.5 ? 3.8 ? 4.0 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 100 ? 100 ? 100 ? 100 ? 100 ? 100 ? ns
rev: 2.06 8/2000 18/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 pipeline mode read/write cycle timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 th ts th ck cke e * adv tkh w tkl tkc ts b n a 0 ? an a1 th ts a2 a3 d(a1) d(a2) q(a3) q q(a6) th ts d d(a5) tkqlz tkq tkqhz toehz toelz tkqx tkhqz tglqv g 1 2 3 4 5 6 7 8 9 10 command write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect don?t care undefined dq a ? dq d th ts th ts th ts a4 a5 a6 a7 q(a4) (a4+1) (a2+1)
rev: 2.06 8/2000 19/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 pipeline mode no-op, stall and deselect timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv w bn a 0 ? an a1 a5 d(a1) q(a2) q(a3) q(a5) dq 1 2 3 4 5 6 7 8 9 10 command write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) continue don?t care undefined d(a4) tkhqz tkqhz deselect deselect th ts a2 a3 a4 th ts th ts th ts
rev: 2.06 8/2000 20/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 flow through mode read/write cycle timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv tkh w tkl tkc b n a 0 ? an th ts a7 dq 1 2 3 4 5 6 7 8 9 10 command write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect don?t care undefined th ts th ts th ts th ts th ts a1 a2 a3 a4 a5 a6 d(a1) d(a2) q(a3) q q(a6) th ts d d(a5) tkqlz tkq tkqhz toehz toelz tkqx tkhqz tglqv q(a4) (a4+1) (a2+1) g
rev: 2.06 8/2000 21/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 flow through mode no-op, stall and deselect timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv w bn a 0 ? an q(a5) dq 1 2 3 4 5 6 7 8 9 10 command write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) continue don?t care undefined d(a4) tkhqz tkqhz deselect deselect d(a1) q(a2) q(a3) a1 a5 a2 a3 a4 th ts th ts th ts
rev: 2.06 8/2000 22/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 tqfp package drawing bpr 1999.05.18 d 1 d e1 e p i n 1 b e c l l1 a2 a1 y q notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 20.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity ? ? 0.10 q lead angle 0 ? 7
rev: 2.06 8/2000 23/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 ordering information ? gsi nbt synchronous sram org part number 1 type package speed 2 (mhz/ns) t a 3 status 1m x 18 gs8160z18t-225 nbt pipeline/flow through tqfp 225/7 c 1m x 18 gs8160z18t-200 nbt pipeline/flow through tqfp 200/7.5 c 1m x 18 gs8160z18t-180 nbt pipeline/flow through tqfp 180/8 c 1m x 18 gs8160z18t-166 nbt pipeline/flow through tqfp 166/8.5 c 1m x 18 gs8160z18t-150 nbt pipeline/flow through tqfp 150/10 c 1m x 18 gs8160z18t-133 nbt pipeline/flow through tqfp 133/11 c 512k x 36 gs8160z36t-225 nbt pipeline/flow through tqfp 225/7 c 512k x 36 gs8160z36t-200 nbt pipeline/flow through tqfp 200/7.5 c 512k x 36 gs8160z36t-180 nbt pipeline/flow through tqfp 180/8 c 512k x 36 gs8160z36t-166 nbt pipeline/flow through tqfp 166/8.5 c 512k x 36 gs8160z36t-150 nbt pipeline/flow through tqfp 150/10 c 512k x 36 gs8160z36t-133 nbt pipeline/flow through tqfp 133/11 c 1m x 18 gs8160z18t-225i nbt pipeline/flow through tqfp 225/7 i not available 1m x 18 gs8160z18t-200i nbt pipeline/flow through tqfp 200/7.5 i not available 1m x 18 gs8160z18t-180i nbt pipeline/flow through tqfp 180/8 i 1m x 18 gs8160z18t-166i nbt pipeline/flow through tqfp 166/8.5 i 1m x 18 gs8160z18t-150i nbt pipeline/flow through tqfp 150/10 i 1m x 18 gs8160z18t-133i nbt pipeline/flow through tqfp 133/11 i 512k x 36 gs8160z36t-225i nbt pipeline/flow through tqfp 225/7 i not available 512k x 36 gs8160z36t-200i nbt pipeline/flow through tqfp 200/7.5 i not available 512k x 36 GS8160Z36T-180I nbt pipeline/flow through tqfp 180/8 i 512k x 36 gs8160z36t-166i nbt pipeline/flow through tqfp 166/8.5 i 512k x 36 gs8160z36t-150i nbt pipeline/flow through tqfp 150/10 i 512k x 36 gs8160z36t-133i nbt pipeline/flow through tqfp 133/11 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs816 0 z36 t -100it. 2. the speed column indicates the cycle frequency (mhz) of the device in pipeline mode and the latency (ns) in flow through mode. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only s ome of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings
rev: 2.06 8/2000 24/24 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8160z 18/36 t -225/200/180/166/150/133 0.18u 16m sync sram data sheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason gs 8160z 18/36 t 1.00 9/ 1999a;gs 8160z 18/36 t 2.0012/ 1999b content ? converted from 0.25u 3.3v process to 0.18u 2.5v process. master file rev b ? added x72 pinout. gs 8160z 18/36 t 2.00 12/ 1999bgs 8160z 18/36 t 2.01 1/ 2000c format ? added new gsi logo gs 8160z 18/36 t 2.0 1 1/ 2000dgs 8160z 18/36 t 2.03 2/ 2000e ? front page; features - changed 2.5v i/o supply to 2.5v or3.3v i/o supply; completeness ? absolute maximum ratings; changed vddq - value: from: -.05 to vdd : to : -.05 to 3.6; completeness. ? recommended operating conditions;changed: i/o supply voltage- max. from vdd to 3.6; input high voltage- max. from vdd +0.3 to 3.6; same page - took out note 1;completeness ? electrical characteristics - added second output high voltage line to table; completeness. ? note: there was not a rev 2.02 for the 8160z or the 8161z. gs 8160z 18/36 t 2.03 2/2000e; 8160z18_r2_04 content ? removed pin 14 from v ss in pin description table. ? adv changed to pin 85 in pin description table. 8160z18_r2_04; 8160z18_r2_05 content ? changed the value of zz recovery in the ac electrical characteristics table on page 17 from 20 ns to 100 ns 8160z18_r2_05; 8160z18_r2_06 content ? added 225 mhz speed bin ? updated pg. 1 table, ac characteristics table, and operating cur- rents table to match 815xxx ? updated format to comply with technical publications standards

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