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wideband switched-input operational amplifier features l fast settling: 9ns (1%) l wide bandwidth: 185mhz (a v = 10) l low offset voltage: 250 m v l two logic selectable inputs l fast input switching: 8ns (ttl) l 16-pin dip package applications l programmable-gain amplifier l fast 2-input multiplexer l synchronous demodulator l pulse/rf amplifiers l video amplifiers l active filters description the opa675 and opa676 are wideband monolithic operational amplifiers with two independent differen- tial inputs. either input can be selected by an external logic signal. the opa675 is compatible with ecl logic while the opa676 is ttl compatible. both amplifiers are externally compensated and feature very fast input selection speed: ecl = 4ns, ttl = 6ns. this amplifier features fully symmetrical differential inputs due to its classical operational amplifier circuit architecture. unlike current-feedback amplifier designs, the opa675/676 may be used in all op amp applications requiring high speed and precision. low distortion and crosstalk make these amplifiers suitable for rf and video applications. the opa675 and opa676 are available in kg (0 c to +70 c) and sg (C55 c to +125 c) grades. all grades are packaged in a 16-pin dip. opa675 opa676 + _ a ttl: opa676 ecl: opa675 b + _ input a input b output compensation international airport industrial park ? mailing address: po box 11400 ? tucson, az 85734 ? street address: 6730 s. tucson blvd. ? tucson, az 85706 tel: (520) 746-1111 ? twx: 910-952-1111 ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? immediate product info: (800) 548-6132 ? 1988 burr-brown corporation pds-864d printed in u.s.a. october, 1993
opa675/676 2 specifications electrical at v cc = 5vdc, r l = 150 w , and t a = +25 c, unless otherwise noted. opa675/676jg, sg opa675/676kg parameter conditions min typ max min typ max units input noise (1) voltage: f o = 10hz r s = 0 w 27 * nv/ ? hz f o = 100hz 10 * nv/ ? hz f o = 1khz 3.8 * nv/ ? hz f o = 10khz 2.6 * nv/ ? hz f o = 100khz 2.4 * nv/ ? hz f b = 10hz to 10mhz 7.9 * m vrms current: f o = 10hz to 1mhz 2.7 * pa/ ? hz offset voltage (1) input offset voltage v cm = 0vdc 500 2mv 250 1mv m v average drift t a = t min to t max 3 10 1 5 m v/ c supply rejection v cc = 4.5v to 5.5v 65 86 70 * db bias current (1) input bias current v cm = 0vdc 23 35 * 30 m a offset current (1) input offset current v cm = 0vdc 0.8 5 * * m a input impedance (1) differential 4k 2* w pf common-mode 10 5 5* w pf input voltage range (1) common-mode input range 1.25 2.5 * * v common-mode rejection v in = 0.5vdc, v o = 1.25v 75 100 85 * db open loop gain, dc (1) open-loop voltage gain 65 70 * * db frequency response closed-loop bandwidth gain = +2v/v 100 * mhz gain = +5v/v 145 * mhz gain = +10v/v 185 * mhz gain = +50v/v 60 * mhz crosstalk gain = +10v/v, f = 100khz C100 * dbc (2) f = 1mhz C80 * dbc f = 10mhz C68 * dbc f = 100mhz C35 * dbc harmonic distortion: 10mhz g = +10v/v, r l = 50 w , v o = 0.5vp-p second harmonic C61 * dbc third harmonic C73 * dbc full power response v o = 2.5vp-p, gain = +10v/v 25 44 30 * mhz slew rate gain = +10v/v 200 350 240 * v/ m s settling time: 1% 9*ns 0.1% gain = +10v/v 15 * ns 0.01% 0.625v output step 25 * ns input selection (3) transition time ecl: opa675 5 * ns 50% in to 50% out ttl: opa676 7.5 * ns digital input ttl logic levels: v il logic lo 0 +0.8 * * v v ih logic hi +2.0 +5 * * v i il logic lo, v il = 0v C0.05 C0.2 * * ma i ih logic hi, v ih = +2.7v 1 20 * * m a ecl logic levels: v il logic lo C1.81 C1.475 * * v v ih logic hi C1.15 C 0.88 * * v i il logic lo, v il = C1.6v C50 C100 * * m a i ih logic hi, v ih = C1.0v C50 C100 * * m a rated output voltage output r l = 150 w 2.1 2.6 * * v r l = 50 w +1.25 +1.8 * * v C0.95 C1.1 C1.0 * v current output 30 * ma output resistance 1mhz, open-loop, c c = 5pf 5 * w load capacitance stability gain = +2v/v 50 * pf short circuit current continuous to gnd +45 * ma C25 * ma * same specifications as for jg.
opa675/676 3 specifications (cont) electrical at v cc = 5vdc, r l = 150 w , and t a = +25 c, unless otherwise noted. opa675/676jg, sg opa675/676kg parameter conditions min typ max min typ max units power supply rated voltage v cc 5 * vdc derated performance v cc 4.5 6.5 * * vdc current, quiescent i o = 0madc 22 30 * * ma temperature range specification ambient temp jg, kg 0 +70 * * c sg C55 +125 c operating: ambient temp jg, kg, sg C55 +125 * * c q ja 125 * c/w * same specifications as for jg. electrical (full temperature range specifications) at v cc = 5vdc, r l = 150 w , and t a = t min to t max , unless otherwise noted. opa675/676jg, sg opa675/676kg parameter conditions min typ max min typ max units temperature range specification ambient temp jg, kg 0 +70 * * c sg C55 +125 c offset voltage average drift t a = t min to t max 3 10 1 5 m v/ c supply rejection v cc = 4.5v to 5.5v 60 85 65 * db bias current input bias current v cm = 0vdc 29 50 * * m a offset current input offset current v cm = 0vdc 0.8 10 * * m a input voltage range common-mode input range 2.0 2.3 * * v common-mode rejection v in = 0.5vdc, v o = 1.25v 60 80 65 * db open loop gain, dc open-loop voltage gain 60 68 63 69 db digital input ttl logic levels: v il logic lo 0 +0.8 * * v v ih logic hi +2.0 +5 * * v i il logic lo", v il = 0v C0.08 C0.4 * * ma i ih logic hi, v ih = +2.7v 5 50 * * m a ecl logic levels: v il logic lo C1.81 C1.475 * * v v ih logic hi C1.15 C0.88 * * v i il logic lo, v il = C1.6v C50 * m a i ih logic hi, v ih = C1.0v C50 * m a rated output voltage output r l = 150 w 2.0 2.5 * * v r l = 50 w +1.25 +1.6 * * v C0.8 C1.0 C0.9 * v power supply current, quiescent i o = 0madc 25 35 * * ma * same specifications as for jg. notes: (1) specifications are for both inputs (a and b). (2) dbc = level referred to carrier-input signal. (3) switching time from application of digital logic signal to input signal selection. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or omissions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems.
opa675/676 4 ab 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 +in a ?n a offset trim offset trim nc +v output compensation capacitor +in b ?n b dnc cha (ecl) cha (ecl) common ? nc + + cc cc ab 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 +in a ?n a offset trim offset trim nc +v output compensation capacitor +in b ?n b dnc dnc cha (ttl) common ? nc + + cc cc pin configurations ordering information opa675 opa676 basic model number performance grade code j, k: 0 c to +70 c s: C55 c to +125 c package code g: 16-pin ceramic dip supply ............................................................................................. 7vdc differential input voltage ............................................................. total v cc input voltage range (analog and digital) .......................................... v cc storage temperature range ....................................... C65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c output short circuit to ground (+25 c) ................... continuous to ground junction temperature .................................................................... +175 c absolute maximum ratings 1 +in a 2 Cin a 3 offset trim 4 offset trim 5 compensation capacitor 6nc 7+v cc 8 output dnc = do not connect 16 +in b 15 Cin b 14 dnc 13 dnc 12 cha (ttl) 11 common 10 Cv cc 9nc nc = no internal connection 1 +in a 2 Cin a 3 offset trim 4 offset trim 5 compensation capacitor 6nc 7+v cc 8 output dnc = do not connect 16 +in b 15 Cin b 14 dnc 13 cha (ecl) 12 cha (ecl) 11 common 10 Cv cc 9nc nc = no internal connection pin assignments: opa675 pin assignments: opa676 opa675 opa676 *capacitance on this node slows channel select. * ()() ()() package information package drawing model package number (1) opa675/76jg 16-pin hermetic dip 109 opa675/76sg 16-pin hermetic dip 109 opa675/76kg 16-pin hermetic dip 109 note: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix d of burr-brown ic data book.
opa675/676 5 50 45 40 35 30 25 20 15 10 5 0 0.3 1 1000 gain (db) frequency (mhz) 10 100 0 ?5 ?0 ?35 ?80 phase (? c = none f gain f bw = 60.6 mhz = ?0.5 c f a v = +50v/v closed-loop small signal bandwidth ?0 ?0 ?0 ?0 ?0 ?0 0.1 1 10 100 3f 2f harmonic distortion (dbc) frequency (mhz) gain = +10v/v r?= 50 v?= 0.5vp-p w l o small signal harmonic distortion vs frequency dice information typical performance curves pad function pad function 1 ttl set 15 +v cc 2 Cin b 16 +v cc 3 +in b 17 v out 4nc18nc 5nc19nc 6 +in a 20 nc 7 Cin a 21 nc 8nc22Cv cc 9v os adjust 23 Cv cc 10 v os adjust 24 ground 11 nc 25 cha (ttl) 12 comp cap 26 ecl out 13 nc 27 cha (ecl) 14 nc 28 cha (ecl) nc : no connection (do not connect). opa675 -do not use pads 1, 25, 26. opa676 -connect pad 26 to pad 27. connect pad 1 to pad 28. substrate bias: Cv cc mechanical information mils (0.001") die size 103 x 90 5 die thickness 20 3 opa675/676 die topography a v = +10v/v closed-loop small signal bandwidth frequency (mhz) gain (db) 30 27 24 21 18 15 12 9 6 3 0 0.3 1 10 100 1000 0 ?5 ?0 ?35 ?80 phase (? c c = 6.5pf bw = 185mhz f = ?39.5 f gain f ?0 ?0 ?0 ?0 ?0 ?0 0.1 3f 2f harmonic distortion (dbc) frequency (mhz) gain = +10v/v r?= 1k v?= 2.5vp-p w l o 100 10 1 large signal harmonic distortion vs frequency
opa675/676 6 10 9 8 7 6 5 4 3 2 1 0 0.3 1 1000 gain (db) frequency (mhz) 10 100 0 ?5 ?0 ?35 ?80 phase (? c = 35pf gain f bw = 100.3mhz = ?2.5 f f c a v = +2v/v closed-loop small signal bandwidth typical performance curves (cont) 20 18 16 14 12 10 8 6 4 2 0 0.3 1 1000 gain (db) frequency (mhz) 10 100 0 ?5 ?0 ?35 ?80 phase (? c c = 16pf f gain f bw = 145.5mhz = ?9.6 f a v = +5v/v closed-loop small signal bandwidth ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?5 0 +15 distortion (dbc) power output (dbm) ?0 ? +5 +10 2f 3f 0.125vp-p 0.25vp-p 0.5vp-p 1vp-p 2vp-p a? +10v/v (20db) c? 6.5pf r? 50 ?= 1mhz v c l c w 1mhz harmonic distortion vs power output ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?5 0 +15 distortion (dbc) power output (dbm) ?0 ? +5 +10 2f 3f 0.125vp-p 0.25vp-p 0.5vp-p 1vp-p 2vp-p a? +10v/v (20db) c? 6.5pf r? 50 ?= 5mhz v c l c w 5mhz harmonic distortion vs power output ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?5 0 +15 distortion (dbc) power output (dbm) ?0 ? +5 +10 2f 3f 0.125vp-p 0.25vp-p 0.5vp-p 1vp-p 2vp-p a? +10v/v (20db) c? 6.5pf r? 50 ??= 10mhz v c l c w 10mhz harmonic distortion vs power output ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?5 0 +15 distortion (dbc) power output (dbm) ?0 ? +5 +10 2f 3f v c l c w 20mhz harmonic distortion vs power output a v ? +10v/v (20db) c c ? 6.5pf r l ? 50 ? c ? 20mhz 0.125vp-p 0.25vp-p 0.5vp-p 1vp-p 2vp-p
opa675/676 7 110 100 90 80 70 60 50 ?0 ?5 +50 +125 a,psr, and cmr (db) temperature (?) 0 +25 +75 +100 cmr psr a ol ol open-loop gain, cmr and psr vs temperature 1 2 100 compensation capacitor (pf) noise gain (v/v) 10 34568 2030 5070 35 30 25 20 15 10 5 0 nominal frequency compensation vs noise gain 0 ?5 ?0 ?5 ?0 ?5 ?0 ?05 ?20 0.3 1 1000 crosstalk (dbc) frequency (mhz) 10 100 10.0mhz ?8.3db channel-to-channel crosstalk vs frequency typical performance curves (cont) theory of operation an opa675 simplified circuit is shown in figure 1. it is a classical high-speed op-amp architecture with one impor- tant exception the amplifier has two ecl logic selectable differential input stages. an appropriate differential ecl logic signal on a and a (labeled b select) will turn on either q5 or q6, steering operating (tail) current to either differen- tial input pair q1 and q2 or q3 and q4. the input pair receiving the tail current operates as a conventional op-amp input stage while the de-selected input pair receiving no tail current appears as an open circuit. the de-selected inputs have only a few pf parasitic capacitance and in the off condition exhibit only a very low leakage (bias) current of about 100pa. two feedback networks can be connected to each input separately allowing a wide range of circuit applications. the feedback network connected to the se- lected input operates in a normal op amp fashion while the feedback network connected to the de-selected input is totally inactive, appearing only as an additional load to the amplifiers output stage. the switched-input op amp (swop amp) circuit of the opa676 is basically the same as the opa675 but a ttl compatible level shifter (figure 2) has been added to its input selection logic circuit. standard ttl (opa676) and ecl (opa675) logic levels may be applied to each input selection circuit but only 2 4812 frequency (mhz) 610 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 output power (dbm) gain = +10v/v v out = 500mvp-p r l = 50 w 2.5mhz small-signal harmonic distortion spectrum
opa675/676 8 b select a select q7 q8 q1 q2 a q3 q4 b + + q5 q6 +v cc bias comp i tail ? cc out +v cc ecl out ttl in ecl threshold figure 1. opa675 simplified circuit diagram. fpo figure 3. 1% settling time. figure 2. internal opa676 ttl logic level shifter. fpo 350mv is typically required to switch between inputs. this logic input sensitivity allows simpler high-speed logic driver circuitry and it minimizes digital noise coupling into adja- cent wideband analog circuitry and allows single ended ecl inputs to be used with v bb applied to the other input. the opa675 and opa676 are designed to be frequency compensated by a single capacitor connected from pin 5 to ground. recommended compensation is shown in typical performance curves. a small variable capacitor may be trimmed for best bandwidth, settling time, and gain peaking. this amplifier is designed for optimum performance in gains of 5v/v to 20v/v, but it can also be used over a far wider range of gains with excellent results. closed-loop gain/phase (bode) plots are shown in the typical performance curves. offset trim input offset voltage is low enough for many video applica- tions. if desired, offset voltage can be trimmed with a 1k w potentiometer connected to +v cc . trimming offset voltage in this manner will effect both input a and input b; independent control of input offset will require that trim adjust current be summed into one or both inputs. this technique is shown in a few applications circuits on the pages to follow.
opa675/676 9 500 w 100 100 5-30pf 75 ww 2 1 5 8 w + + 500 50 w w to scope 1mhz square wave +0.5v ?.5v 100 w 1k 6.5pf 10mhz 50mvp-p w 2 1 5 8 opa676 + + 16 15 11 100 w 1k w 3mhz ttl 100 w r l 12 tektronix sg503 to scope figure 5. opa676 input selection transition time test circuit. figure 4. opa675/676 settling time test circuit. 6. wirewound resistors (even non-inductive types) are absolutely unacceptable in high frequency circuits. 7. avoid overloading the output. remember that output current must be provided by the amplifier to drive its own feedback network as well as to drive its load. lowest distortion is achieved with high impedance loads. 8. pc board traces for signal and power lines should be wide to reduce impedance or inductance. 9. dont forget that these amplifiers use 5v supplies. although they will operate perfectly well with +5v and C5.2v, the use of 15v supplies will result in destruction. 10. standard commercial test equipment has not been de- signed to test devices in the opa675/676 speed range. benchtop op amp testers and ate systems will require a special test head to successfully test these amplifiers. 11. high-speed amplifiers can drive only a limited amount of capacitance. if the load exceeds 10 to 20pf consider using a fast buffer or a small resistor to isolate the capacitance from the amplifiers output. capacitive loads will cause loop instability if not compensated for. 12. terminate transmission line loads. unterminated lines, such as coaxial cable, can appear to the amplifier to be a capacitive or inductive load. by terminating a trans- mission line with its characteristic impedance, the amplifiers load then appears as a purely resistive impedance. 13. for clean, fast input selection the logic input pins should be terminated with appropriate resistors. resistors should be connected from input selection pins to ground plane with short leads. failure to terminate long lines will result in ringing and poor high frequency switching. 14. plug-in prototype boards and wire-wrap boards will not be satisfactory. a clean layout using rf techniques is required; there is no shortcut. application tips wideband amplifier circuits require good layout techniques to be successful. the use of short, direct signal paths and heavy (2 oz. copper recommended) ground planes are abso- lutely necessary to achieve the performance level inherent in the opa675/676. oscillation, ringing, poor bandwidth and settling, gain peaking, and instability are typical problems that plague all high-speed amplifiers when they are used in poor layouts. the opa675 and opa676 are no different in this respectany amplifier with a gain bandwidth product of a few ghz requires some care be taken in its application. points to remember: 1. use a heavy copper ground plane on the component side of your pc board. this provides a low inductance ground and it also conducts heat from active circuit package pins into ambient air by convection. 2. bypass power supply pins directly at the active device. the use of tantalum capacitors (1 to 10 m f/10v) with very short leads is highly recommended. supply pins should not be left unbypassed. 3. signal paths should be short and direct. feedback resistors, compensation capacitors, termination resis- tors, etc., should have lead lengths no longer than 1/4 inch (6cm). 4. surface-mount components (chip resistors, capacitors, etc.) have low inductance and are therefore recom- mended. parasitic inductance and capacitance should be avoided if best performance is to be achieved. 5. resistors used in feedback networks should have values of a few hundred ohms for best performance. shunt capacitance problems limit the acceptable range to about 1k w or on the high resistance end and to a value that is within the amplifiers output drive limits on the low end. metal film and carbon compensation resistors will be satisfactory.
opa675/676 10 1mhz ttl carrier feedthrough vs frequency 0 2610 frequency (mhz) 48 +10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 carrier feedthrough (dbm) 16 2 8 opa676 316 w 1 15 a b 12 5 12pf + + 4 49.9 w 50 w output 1k w +5v offset trim 49.9 w 50 w input 10 11 + 2.2? 10v* ?v * tantalum + 2.2? 10v* 7 3 100 w 1k 6.5pf 10mhz 50mvp-p w 2 3 5 8 opa675 + + to scope 3mhz ecl 16 15 11 100 w 1k w ?.2v 300 w 300 w 50 w 4 5 12 13 2 3 mc10105 16 2 11 8 5-30pf opa676 499 w 10k w 1 499 w 15 a b 5 + + oscilloscope or spectrum analyzer w to 50 50 w 49.9 w 49.9 w 49.9 w 40.2 w offset trim ?v +5v 5k w 10 w +2.8v +0.4v input: ttl rise and fall time = 10ns frequency = 1mhz 12 ttl 1 figure 6. opa675 input selection transition time test circuit. figure 9. carrier feedthrough from 1mhz ttl logic. offset trimmed for maximum carrier rejec- tion figure 7. opa676 carrier feedthrough and switching transient test circuit. figure 8. opa676 switching transient. top trace: ttl input (2v/cm). bottom trace: amplifier output (2mv/cm). input b offset voltage has been trimmed to match input a offset voltage. figure 10. opa676 used as a conventional op amp: a 10db gain wideband video amplifier with 50 w input/output impedance.
opa675/676 11 16 2 8 opa676 301 w 20 w 1 15 a b 11 5 3pf + + 12 output ttl 301 w 20 w 301 w input 3 4 +5v 1k w 20 w bandwidth = ~200mhz input 49.9 12 16 2 7 4.7?* + 845 46 * tantalum adc603 signal input analog common +5v w opa676 10k w offset trim 100 w 100 w 1 412 w 59 w 15 a b 4.7?* + -5v 10 5 11 gain select (ttl) 3 4 39 pf + + 16 3 6 opa675 1k w 100 w 1 15 a b 11 5 ~5pf + + ttl 12 100 w opa621 + out opa621 + 1k w 200 w 200 w 200 w differential input 2 opa621 + opa621 + 200 w 200 w 200 w differential input 1 1k w 100 w 1k w 2 3 6 2 2 6 3 2 6 3 100 w 2 8 opa676 figure 12. programmable-gain +2v/v (6db) or +8v/v (18db) buffer amplifier for floating-point conversion. figure 13. high input impedance differential input multiplexer with gain of 30v/v (30db). figure 11. very fast programmable gain amplifier with voltage gains of +1v/v and +16v/v (0db and 24db).
opa675/676 12 input a 49.9 12 16 2 7 4.7?* + 845 46 * tantalum adc603 signal input analog common +5v w opa676 10k w offset trim 383 w 383 w 51.1 w 1 383 w 383 w 51.1 w input b 15 a b 4.7?* + ?v 10 5 11 input select (ttl) 3 4 4.7 pf 49.9 w + + 200 40 in 200 95.3 out 100 16pf 10 gain trim 10k +5v ?v ww 40 w w w w w 10k w 2 1 16 15 5 8 w ttl 12 11 opa676 + + offset trim 16 2 8 opa676 909 w 90.9 w 1 15 a b 11 5 6.5pf + + 12 49.9 w 50 w rf or if out 10 w 5k w 4.99k w +5v ?v 49.9 w ttl in noise blanking pulse input 909 w 100 w 49.9 w 49.9 w 50 w rf or if in 16 2 8 opa676 1k w 100 w 1 15 a b 11 5 ~5pf + + output 1k w 1k w in 1 100 w 13 diff ecl 12 in 2 100 w 100 w 1k w + + aa r 2 r 1 in c r 2 r 1 out c 2 1 16 15 5 8 opa676 ttl 12 11 + + opa675 figure 15. multiplexed input +16v/v gain (24db) buffer amplifier. figure 14. synchronous modulator/demodulator with car- rier balance trim (gain = 5v/v). figure 16. receiver noise blanker: a wideband gated video amplifier. figure 17. differential input multiplexer with gain of 10v/v (20db). voltage gain r 1 r 2 c c (v/v) ( w )( w ) (pf) +2 200 200 35 +5 49.9 200 16 +10 22.1 200 6.5 figure 18. programmable-gain amplifier.
opa675/676 13 r 2 r 1 2 1 16 15 5 8 out in r 3 c c r 4 ttl 12 11 opa676 + + 16 2 8 opa675 909 w 90.2 w 1 15 a b 11 5 6.5pf + + 13 1.5k w 10 w 5k w 4.99k w +5v diff ecl 909 w ?v 12 100 w 1k w opa620 + 1k w 300hz to 3khz audio input aa 455khz carrier input 49.9 w 455khz bp filter* opa620 + 1.5k w 1k w 1k w 50 w rf out * murata erie cfs455c (carrier suppression) offset trim r 2 r 1 r 2 r 1 in 1 in 2 c out c 2 1 16 15 5 8 ttl 12 11 opa676 + + voltage gain r 1 r 2 r 3 r 4 c c (v/v) ( w )( w )( w )( w ) (pf) 2 100 200 200 200 35 5 40 200 50 200 16 10 20 200 25 225 6.5 figure 21. synchronous modulator/demodulator (with gain). figure 19. single sideband suppressed carrier generator. voltage gain r 1 r 2 c c (v/v) ( w )( w ) (pf) +2 200 200 35 +4 75 226 22 +8 28 196 10 +16 20 301 3 +32 10 309 0 figure 20. two-input multiplexer (with gain).

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