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functional block diagram reg a shift register decode vouta voutb voutc voutd 2 3 6 7 8 15 16 9 gnd clsel 4 vreflo vss 5 vrefhi vdd 10 12 11 13 14 sdi clk nc cs ld reg a 1 dac a reg b dac b reg c dac c reg d dac d clr 12 4 2 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a quad 12-bit serial voltage output dac dac8420 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features guaranteed monotonic over temperature excellent matching between dacs unipolar or bipolar operation buffered voltage outputs high speed serial digital interface reset to zero- or center-scale wide supply range, +5 v-only to 6 15 v low power consumption (35 mw max) available in 16-pin dip and sol packages applications software controlled calibration servo controls process control and automation ate the dac8420 is available in 16-pin epoxy dip, cerdip, and wide-body sol (small-outline surface mount) packages. opera- tion is specified with supplies ranging from +5 v-only to 15 v, with references of +2.5 v to 10 v respectively. power dissipa- tion when operating from 15 v supplies is less than 255 mw (max), and only 35 mw (max) with a +5 v supply. for applications requiring product meeting mil-std-883, contact your local sales office for the dac8420/883 data sheet, which specifies operation over the C55 c to +125 c tempera- ture range. general description the dac8420 is a quad, 12-bit voltage-output dac with serial digital interface, in a 16-pin package. utilizing bicmos tech- nology, this monolithic device features unusually high circuit density and low power consumption. the simple, easy-to-use serial digital input and fully buffered analog voltage outputs require no external components to achieve specified performance. the three-wire serial digital input is easily interfaced to micro- processors running at 10 mhz rates, with minimal additional circuitry. each dac is addressed individually by a 16-bit serial word consisting of a 12-bit data word and an address header. the user-programmable reset control clr forces all four dac outputs to either zero or midscale, asynchronously overriding the current dac register values. the output voltage range, de- termined by the inputs vrefhi and vreflo, is set by the user for positive or negative unipolar or bipolar signal swings within the supplies allowing considerable design flexibility.
dac8420Cspecifications electrical characteristics rev. 0 C2C (at v dd = +5.0 v 6 5%, v ss = 0.0 v, v vrefhi = +2.5 v, v vrefld = 0.0 v, and v ss = C5.0 v 6 5%, v vreflo = C2.5 v, C40 8 c t a +85 8 c unless otherwise noted. see note 1 for supply variations.) parameter symbol condition min typ max units static accuracy integral linearity e inl 1/4 1 lsb integral linearity e inl note 2, v ss = 0 v 1/2 3 lsb integral linearity f inl 3/4 2 lsb integral linearity f inl note 2, v ss = 0 v 1 4 lsb differential linearity dnl monotonic over temperature 1/4 1 lsb min-scale error zse r l = 2 k w , v ss = C5 v 4 lsb full-scale error fse r l = 2 k w , v ss = C5 v 4 lsb min-scale error zse note 2, r l = 2 k w , v ss = 0 v 8 lsb full-scale error fse note 2, r l = 2 k w , v ss = 0 v 8 lsb min-scale tempco tc zse note 3, r l = 2 k w , v ss = C5 v 10 ppm/ c full-scale tempco tc fse note 3, r l = 2 k w , v ss = C5 v 10 ppm/ c matching performance linearity matching 1 lsb reference positive reference input range v vrefhi note 4 v vreflo +2.5 v dd C2.5 v negative reference input range v vreflo note 4 v ss v vrefhi C2.5 v negative reference input range v vreflo note 4, v ss = 0 v 0 v vrefhi C2.5 v reference high input current i vrefhi codes 000 h , 555 h C0.75 0.25 +0.75 ma reference low input current i vreflo codes 000 h , 555 h , v ss = C5 v C1.0 C0.6 ma amplifier characteristics output current i out v ss = C5 v C1.25 +1.25 ma settling time t s to 0.01%, note 5 8 m s slew rate sr 10% to 90%, note 5 1.5 v/ m s logic characteristics logic input high voltage v inh 2.4 v logic input low voltage v inl 0.8 v logic input current i in 10 m a input capacitance c in note 3 13 pf logic timing char acteristics 3, 6 data setup time t ds 25 ns data hold t dh 55 ns clock pulse width high t ch 90 ns clock pulse width low t cl 120 ns select time t css 90 ns deselect delay t csh 5ns load disable time t ld1 130 ns load delay t ld2 35 ns load pulse width t ldw 80 ns clear pulse width t clrw 150 ns supply characteristics power supply sensitivity psrr 0.002 0.01 %/% positive supply current i dd 47 ma negative supply current i ss C6 C3 ma power dissipation p diss v ss = 0 v 20 35 mw notes 1 all supplies can be varied 5% and operation is guaranteed. device is tested with v dd = +4.75 v. 2 for single-supply operation (v vreflo = 0 v, v ss = 0 v), due to internal offset errors inl and dnl are measured beginning at code 003 h . 3 guaranteed but not tested. 4 operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 5 v out swing between +2.5 v and C2.5 v with v dd = 5.0 v. 6 all input control signals are specified with tr = tf =5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 7 typical values indicate performance measured at +25 c. specifications subject to change without notice.
electrical characteristics parameter symbol condition min typ max units static accuracy integral linearity e inl 1/4 1/2 lsb integral linearity f inl 1/2 1 lsb differential linearity dnl monotonic over temperature 1/4 1 lsb min-scale error zse r l = 2 k w 2 lsb full-scale error fse r l = 2 k w 2 lsb min-scale tempco tc zse note 2, r l = 2 k w 4 ppm/ c full-scale tempco tc fse note 2, r l = 2 k w 4 ppm/ c matching performance linearity matching 1 lsb reference positive reference input range v vrefhi note 3 v vreflo +2.5 v dd C2.5 v negative reference input range v vreflo note 3 C10 v vrefhi C2.5 v reference high input current i vrefhi codes 000 h , 555 h C2.0 1.0 +2.0 ma reference low input current i vreflo codes 000 h , 555 h C3.5 C2.0 ma amplifier characteristics output current i out C5 +5 ma settling time t s to 0.01%, note 4 13 m s slew rate sr 10% to 90%, note 4 2 v/ m s dynamic performance analog crosstalk note 2 >64 db digital feedthrough note 2 >72 db large signal bandwidth 3 db, v vrefhi = 5 v + 10 v p-p, 90 khz v vreflo = C10 v, note 2 glitch impulse code transition = 7ff h to 800 h , note 2 64 nv-s logic characteristics logic input high voltage v inh 2.4 v logic input low voltage v inl 0.8 v logic input current i in 10 m a input capacitance c in note 2 13 pf logic timing characteristics 2, 5 data setup time t ds 25 ns data hold t dh 20 ns clock pulse width high t ch 30 ns clock pulse width low t cl 50 ns select time t css 55 ns deselect delay t csh 15 ns load disable time t ld1 40 ns load delay t ld2 15 ns load pulse width t ldw 45 ns clear pulse width t clrw 70 ns supply characteristics power supply sensitivity psrr 0.002 0.01 %/% positive supply current i dd 69 ma negative supply current i ss C8 C5 ma power dissipation p diss 255 mw notes 1 all supplies can be varied 5% and operation is guaranteed. 2 guaranteed but not tested. 3 operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4 v out swing between +10 v and C10 v. 5 all input control signals are specified with tr = tf =5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 6 typical values indicate performance measured at +25 c. specifications subject to change without notice. dac8420 rev. 0 C3C (at v dd = +15.0 v 6 5%, v ss = C15.0 v 6 5%, v vrefhi = +10.0 v, v vreflo = C10.0 v, C40 8 c t a +85 8 c unless otherwise noted. see note 1 for supply variations.)
dac8420 rev. 0 C4C wafer test limits dac8420g parameter symbol conditions limit units integral linearity inl 1 lsb max differential linearity dnl 1 lsb max min-scale offset 1 lsb max max-scale offset 1 lsb max logic input high voltage v inh 2.4 v min logic input low voltage v inl 0.8 v max logic input current i in 1 m a max positive supply current i dd 8 ma max negative supply current i ss 7 ma max note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. absolute maximum ratings (t a = +25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +18.0 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v, C18.0 v v ss to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +36.0 v v ss to v vreflo . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v ss C 2.0 v v vrefhi to v vreflo . . . . . . . . . . . . . . . . . . . +2.0 v, v dd C v ss v vrefhi to v dd . . . . . . . . . . . . . . . . . . . . . . . +2.0 v, +33.0 v i vrefhi , i vreflo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ma digital input voltage to gnd . . . . . . . . . C0.3 v, v dd + 0.3 v output short circuit duration . . . . . . . . . . . . . . . . indefinite operating temperature range ep, fp, es, fs, eq, fq . . . . . . . . . . . . . . C40 c to +85 c dice junction temperature . . . . . . . . . . . . . . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mw lead temperature (soldering, 60 sec) . . . . . . . . . . . . . +300 c thermal resistance package type q ja q jc units 16-pin plastic dip (p) 70 1 27 c/w 16-pin hermetic dip (q) 82 1 9 c/w 16-lead small outline surface mount (s) 86 2 22 c/w notes 1 q ja is specified for worst case mounting conditions, i.e., q ja is specified for device in socket. 2 q ja is specified for device on board. caution 1. stresses above those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation at or above this specification is not implied. exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. digital inputs and outputs are protected, however, permanent damage may occur on unprotected units from high-energy electrostatic fields. keep units in conductive foam or packaging at all times until ready to use. use proper antistatic handling procedures. 3. remove power before inserting or removing units from their sockets. 4. analog outputs are protected from short circuits to ground or either supply. dice characteristics 10 sdi 9 gnd 8 vss 7 vouta clr 15 clsel 16 (substrate) vdd 1 voutd 2 voutc 3 vreflo 4 vrefhi 5 voutb 6 11 clk 12 cs 14 ld 13 nc nc = no connect die size 0.119 0.283 inch, 33,677 sq. mils (3.023 7.188 mm, 21.73 sq. mm) transistor count 2,207 for additional dice ordering information, refer to databook. (at v dd = +15.0 v, v ss = C15.0 v, v refhi = +10.0 v, v reflo = C10.0 v, t a = +25 8 c unless otherwise noted)
dac8420 rev. 0 C5C t csh t ld2 t css t ld1 a1 a0 x x d11 d10 d9 d8 d4 d3 d2 d1 d0 cs sdi clk ld data load sequence t ds t dh ?lsb t s t ldw t ld2 t cl t ch t csh sdi clk cs ld v out data load timing t clrw ?lsb t s clsel clr v out clear timing timing diagram 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dut 10? 0.1? + 1n4001 ?0v nc nc 5k w 10 w 10? 0.1? + 1n4001 +10v 10 w 10? 0.1? + 1n4001 +15v 10 w 10? 0.1? + 1n4001 ?5v 10 w nc nc nc 10k w 5k w nc = no connect burn-in diagram ordering guide temperature inl package package model 1 range ( 6 lsb) description option 2 dac8420ep C40 c to +85 c 0.5 plastic dip p dac8420eq C40 c to +85 c 0.5 cerdip q dac8420es C40 c to +85 c 0.5 soic sol dac8420fp C40 c to +85 c 1.0 plastic dip p dac8420fq C40 c to +85 c 1.0 cerdip q dac8420fs C40 c to +85 c 1.0 soic sol DAC8420QBC C40 c to +85 c 1.0 dice 3 notes 1 a complete /883 data sheet is available. for availability and burn-in informa- tion, contact your local sales office. 2 pmi division letter designator. 3 dice tested at +25 c only.
dac8420 rev. 0 C6C pin configurations pin function description power supplies vdd: positive supply, +5 v to +15 v. vss: negative supply, 0 v to C15 v. gnd: digital ground. clock clk: system serial data clock input, ttl/cmos levels. data presented to the input sdi is shifted into the internal serial-parallel input register on the rising edge of clock. this input is logically ored with cs . control inputs (all are cmos/ttl compatible.) clr : asynchronous clear, active low. sets internal data registers a-d to zero or midscale, depending on cur- rent state of clsel. the data in the serial input shift register is unaffected by this control. clsel: determines action of clr . if high, a clear command will set the internal dac registers a-d to midscale (800 h ). if low, the registers are set to zero (000 h ). cs : device chip select, active low. this input is logically ored with the clock and disables the serial data register input when high. when low, data input clocking is enabled, see the control function table. ld : asynchronous dac register load control, active low. the data currently contained in the serial input shift register is shifted out to the dac data registers on the falling edge of ld , independent of cs . input data must remain stable while ld is low. data input (all are cmos/ttl compatible.) sdi: serial data input. data presented to this pin is loaded into the internal serial-parallel shift register, which shifts data in beginning with dac address bit a1. this input is ignored when cs is high. the format of the 16-bit serial word is: (first) (last) b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 a1 a0 nc nc d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address word (msb) dac data word (lsb) nc = dont care. reference inputs v refhi: upper dac ladder reference voltage input. allowable range is (v dd C 2.5 v) to (v vreflo +2.5 v). vreflo: lower dac ladder reference voltage input, equal to zero scale output. allowable range is v ss to (v vrefhi C 2.5 v). analog outputs vouta through voutd: four buffered dac voltage outputs. dip 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view (not to scale) dac8420 vdd voutd voutc vreflo vrefhi voutb vouta vss clsel nc clk sdi gnd clr ld cs nc = no connect sol 1 2 3 4 8 7 6 5 top view (not to scale) dac-8420 top view (not to scale) dac-8420 9 16 15 14 13 12 11 10 nc = no connect vdd voutd voutc vreflo vrefhi voutb vouta vss clsel nc clk sdi gnd clr ld cs top view (not to scale) dac8420
dac8420 rev. 0 C7C table i. control function logic table clk 1 c s 1 ld clr clsel serial input shift register dac registers a-d nc h h l h no change loads midscale value (800 h ) nc h h l l no change loads zero-scale value (000 h ) nc h h - h/l no change latches value - l h h nc shifts register one bit no change l - h h nc shifts register one bit no change h nc ( - ) h nc no change loads the serial data word 2 h nc l h nc no change transparent 3 nc h h h nc no change no change nc = dont care. notes 1 cs and clk are interchangeable. 2 returning cs high while clk is high avoids an additional false clock of serial input data. see note 1. 3 do not clock in serial data while ld is low. operation introduction the dac8420 is a quad, voltage-output 12-bit dac with serial digital input, capable of operating from a single +5 v supply. the straightforward serial interface can be connected directly to most popular microprocessors and microcontrollers, and can ac- cept data at a 10 mhz clock rate when operating from 15 v supplies. a unique voltage reference structure assures maximum utilization of dac output resolution by allowing the user to set the zero- and full-scale output levels within the supply rails. the analog voltage outputs are fully buffered, and are capable of driving a 2 k w load. output glitch impulse during major code transitions is a very low 64 nv-s (typ). digital interface operation the serial input of the dac-8420, consisting of cs , sdi, and ld , is easily interfaced to a wide variety of microprocessor serial ports. as shown in table i and the timing diagram, while cs is low the data presented to the input sdi is shifted into the internal serial/parallel shift register on the rising edge of the clock, with the address msb first, data lsb last. the data for- mat, shown above, is two bits of dac address and two dont care fill bits, followed by the 12-bit dac data word. once all 16 bits of the serial data word have been input, the load control ld is strobed and the word is parallel-shifted out onto the inter- nal data bus. the two address bits are decoded and used to route the 12-bit data word to the appropriate dac data regis- ter, see the applications information. correct operation of cs and clk as mentioned in table i, the control pins clk and cs require some attention during a data load cycle. since these two inputs are fed to the same logical or gate, their operation is in fact identical. the user must take care to operate them accordingly in order to avoid clocking in false data bits. as shown in the timing diagram, clk must be either halted high, or cs brought high during the last high portion of the clk fol- lowing the rising edge which latched in the last data bit. other- wise, an additional rising edge is generated by cs rising while clk is low, causing cs to act as the clock and allowing a false data bit into the serial input register. the same issue must be considered in the beginning of the data load sequence also. using clr and clsel the clear ( clr ) control allows the user to perform an asyn- chronous reset function. asserting clr loads all four dac data word registers, forcing the dac outputs to either zero-scale (000 h ) or midscale (800 h ), depending on the state of clsel as shown in the digital function table. the clear function is asynchronous and is totally independent of cs . when clr returns high, the dac outputs remain latched at the reset value until ld is strobed, reloading the individual dac data word registers with either the data held in the serial input r egister p rior to the reset, or new data loaded through the serial interface. table ii. dac address word decode table a1 a0 dac addressed 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d programming the analog outputs the unique differential reference structure of the dac8420 allows the user to tailor the output voltage range precisely to the needs of the application. instead of spending dac resolution on an unused region near the positive or negative rail, the dac8420 allows the user to determine both the upper and lower limits of the analog output voltage range. thus, as shown in table iii and figure 1, the outputs of dacs a through d range between vrefhi and vreflo, within the limits speci- fied in the electrical characteristics tables. note also that vrefhi must be greater than vreflo. 1 lsb fff h 000 h 2.5v min 2.5v min 0v min v dd v vrefhi v vreflo v ss ?0v min figure 1. output voltage range programming
dac8420 rev. 0 C8C table iii. analog output code dac data word (hex) v out note fff vreflo + ( vrefhi vreflo ) 4096 4095 full-scale output 801 vreflo + ( vrefhi vreflo ) 4096 2049 midscale + 1 800 vreflo + ( vrefhi vreflo ) 4096 2048 midscale 7ff vreflo + ( vrefhi vreflo ) 4096 2047 midscale C 1 000 vreflo + ( vrefhi vreflo ) 4096 0 zero scale typical performance characteristics 0.3 ?.3 14 0 ?.2 ? ?.1 ? 0.2 0.1 12 10 8 6 4 2 0 ? v vrefhi ?v inl ?lsb t a = +25? v dd = +15v, v ss = ?5v v vreflo = ?0v figure 4. inl vs. vrefhi ( 15 v) 0.3 ?.3 14 0 ?.2 ? ?.1 ? 0.2 0.1 12 10 8 6 4 2 0 ? v vrefhi ?v dnl ?lsb t a = +25? v dd = +15v, v ss = ?5v v vreflo = ?0v figure 2. differential linearity vs. vrefhi ( 15 v) 0.10 ?.30 ?.20 ?.25 1.5 ?.10 ?.15 ?.05 0 0.05 3.5 3.0 2.5 2.0 v vrefhi ?v dnl ?lsb t a = +25? v dd = +5v, v ss = 0v v vreflo = 0v figure 3. differential linearity vs. vrefhi (+5 v) 0.4 ?.4 ?.2 ?.3 1.5 0 ?.1 0.1 0.2 0.3 3.5 3.0 2.5 2.0 v vrefhi ?v inl ?lsb t a = +25? v dd = +5v, v ss = 0v v vreflo = 0v figure 5. inl vs. vrefhi (+5 v) 0.7 ?.5 1000 0.1 ?.3 200 ?.1 0 0.5 0.3 800 600 400 t = hours of operation at +125 c full-scale error with r l = 2k ?lsb x + 3 s x x ?3 s curves not normalized v dd = +15v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v w figure 6. full-scale error vs. time accelerated by burn-in 1.2 0 1000 0.6 0.2 200 0.4 0 1.0 0.8 800 600 400 t = hours of operation at +125 c zero-scale error with r l = 2k ?lsb x + 3 s x x ?3 s curves not normalized v dd = +15v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v w figure 7. zero-scale error vs. time accelerated by burn-in
dac8420 rev. 0 C9C 0.2 ?.6 125 ?.4 ?.5 ?0 ?5 ?.2 ?.3 ?.1 0 0.1 100 75 50 25 0 ?5 temperature ? c full-scale error ?lsb dac a dac d dac c dac b v dd = +15v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v figure 8. full-scale error vs. temperature 1.2 ?.4 125 0 ?.2 ?0 ?5 0.4 0.2 0.6 0.8 1.0 100 75 50 25 0 ?5 temperature ? c zero-scale error ?lsb v dd = +15v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v dac c dac b dac d dac a figure 9. zero-scale error vs. temperature 0.9 ?.9 4500 ?.5 ?.7 500 0 ?.1 ?.3 0.1 0.3 0.5 0.7 4000 3500 3000 2500 2000 1500 1000 t a = +25? v dd = +15v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v digital input code error ??sb figure 10. channel-to-channel matching 15/ 10 +1.5 ?.0 +0.5 ?.5 500 0 0 +1.0 4000 3500 3000 2500 2000 1500 1000 i vrefhi ?ma digital input code t a = +25? v dd = +15v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v figure 14. i vrefhi vs. code 6.5mv ?.5mv +45.1? ?.9? +5?/div t sett 8? ?.22mv 0mv 1 lsb clr t a = +25? v dd = +5v, v ss = ?v v vrefhi = +2.5v v vreflo = ?.5v figure 16. settling time (C)( 5 v) ?50? ?0.25mv 45.1? ?.9? 5?/div ld t sett 8? 1.22mv 0mv 1 lsb t a = +25? v dd = +5v, v ss = ?v v vrefhi = +2.5v v vreflo = ?.5v figure 15. settling time (+)( 5 v) ?.5 ?.5 500 ?.0 0 +1.0 0 +0.5 4000 3500 3000 2500 2000 1500 1000 +1.5 t a = +25? v dd = +5v, v ss = 0v v vrefhi = +2.5v v vreflo = 0v digital input code error ?lsb 4500 figure 11. channel-to-channel matching +5/+2.5 +0.8 ?.2 ?.4 500 0 +0.1 ?.1 0 +0.2 +0.3 +0.4 +0.6 +0.5 +0.7 3500 4000 3000 2500 2000 1500 1000 t a = +25, ?5, 125? v dd = +15v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v digital input code inl ?lsb ?.3 4500 figure 13. inl vs. code 15/ 10 13 4 13 6 5 ? ? 8 7 9 10 11 12 11 9 7 5 3 1 ? ? 0 i dd ?ma v vrefhi ?v t a = +25? v dd = +15v, v ss = ?5v v vreflo = ?0v figure 12. i dd vs. v vrefhi , all dacs high
dac8420 rev. 0 C10C +31.25mv ?8.75mv +90.2? ?.8? +10?/div t sett 13? ld 0mv 4.88mv 1 lsb t a = +25? v dd = +15v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v figure 17. settling time (+)( 15 v) +43.75mv ?.25mv +90.2? ?.8? +10?/div t sett 13? ?.88mv 0mv 1 lsb clr t a = +25? v dd = +15v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v figure 18. settling time (C)( 15 v) +5v ?v 152.4? ?7.6? +1v /div 0 20?/div sr rise = 1.65 sr fall = 1.17 v ? v ? t a = +25? v dd = +5v, v ss = ?v v vrefhi = +2.5v v vreflo = ?.5v figure 19. slew rate ( 5 v) ?0 10 100 10m 1m 100k 10k 1k ?0 0 +10 ?0 t a = +25? v dd = +15v, v ss = ?5v v vrefhi = 0 ?100mv v vreflo = ?0v all bits high 200mv p-p gain ?db frequency ?hz figure 21. small-signal response +25v ?5v 166.4? ?3.6? +5v /div 0 20?/div sr rise = 1.9 v ? sr fall = 2.02 v ? ld clr t a = +25? v dd = +15v, v ss = ?5v v vrefhi = +10v, v vreflo = ?0v figure 20. slew rate ( 15 v) 100 10 50 0 100 1k 10k 100k 1m 60 70 80 90 10 20 30 40 t a = +25? data = 000 h v dd = +15v ?v, v ss = ?5v v vrefhi = +10v v vreflo = ?0v psrr ?db frequency ?hz figure 22. psrr vs. frequency 6 ? 150 0 ? ? ?5 4 2 75 0 temperature ?? power supply current ?ma i dd i ss v dd = +15v v ss = ?5v v vrefhi = +10v v vreflo = ?0v all dacs high (full scale) figure 23. power supply current vs. temperature 10ma/div vouta through voutd t a = +25 c v dd = +15v v ss = ?5v v vrefhi = +10v v vreflo = ?0v data = 800 h 5v/div figure 24. dac output current vs. voutx 10 100 10k 1k 10 8 0 6 4 2 load resistance ? w v out peak ?v t a = +25 c v dd = +15v v ss = ?5v v vrefhi = +10v v vreflo = ?0v data = fff h or 000 h figure 25. output swing vs. load resistance
dac8420 rev. 0 C11C vrefhi input requirements the dac8420 utilizes a unique, patented dac switch driver circuit which compensates for different supply, reference volt- age, and digital code inputs. this ensures that all dac ladder switches are always biased equally, ensuring excellent linearity under all conditions. thus, as indicated in the specifications, the vrefhi input of the dac8420 will require both sourcing and sinking current capability from the reference voltage source. many positive voltage references are intended as current sources only, and offer little sinking capability. the user should consider references such as the ad584, ad586, ad587, ad588, ad780, and ref43 in this application. applications power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the dac8420 has a single ground pin that is internally connected to the digital section as the logic reference level. the first thought may be to connect this pin to the digital ground; however, in large systems the digital ground is often noisy because of the switching currents of other digital circuitry. any noise that is introduced at the ground pin could couple into the analog output. thus, to avoid error causing digital noise in the sensitive analog circuitry, the ground pin should be connected to the system analog ground. the ground path (circuit board trace) should be as wide as possible to re- duce any effects of parasitic inductance and ohmic drops. a ground plane is recommended if possible. the noise immunity of the onboard digital circuitry, typically in the hundreds of mil- livolts, is well able to reject the common-mode noise typically seen b etween system analog and digital grounds. finally, the analog and digital ground should be connected together at a single point in the system to provide a common reference. this is preferably done at the power supply. good grounding practice is essential to maintaining analog performance in the surrounding analog support circuitry as well. with two reference inputs, and four analog outputs capable of moderate bandwidth and output current, there is a significant potential for ground loops. again, a ground plane is recom- mended as the most effective solution to minimizing errors due to noise and ground offsets. 1 89 vdd vss gnd 0.1? 10? ? s 0.1? 10? +v s 10? = tantalum 0.1? = ceramic figure 26. recommended supply bypassing scheme the dac8420 should have ample supply bypassing, located as close to the package as possible. figure 26 shows the recom- mended capacitor values of 10 m f in parallel with 0.1 m f. the 0.1 m f cap should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in order to preserve the specified analog perfor- mance of the device, the supply should be as noise free as pos- sible. in the case of 5 v only systems it is desirable to use the same 5 v supply for both the analog circuitry and the digital portion of the circuit. unfortunately, the typical 5 v supply is extremely noisy due to the fast edge rates of the popular cmos logic families which induce large inductive voltage spikes, and busy microcontroller or microprocessor busses which commonly have large current spikes during bus activity. however, by prop- erly filtering the supply as shown in figure 27, the digital 5 v supply can be used. the inductors and capacitors generate a fil- ter that not only rejects noise due to the digital circuitry, but also filters out the lower frequency noise of switch mode power supplies. the analog supply should be connected as close as possible to the origin of the digital supply to minimize noise pickup from the digital section. 100? elect. 10?2? tant. 0.1? cer. ttl/cmos logic circuits +5v power supply +5v +5v return ferrite beads: 2 turns, fair-rite #2677006301 figure 27. single-supply analog supply filter analog outputs the dac8420 features buffered analog voltage outputs capable of sourcing and sinking up to 5 ma when operating from 15 v supplies, eliminating the need for external buffer amplifiers in most applications while maintaining specified accuracy over the rated operating conditions. the buffered outputs are simply an op amp connected as a voltage follower, and thus have output characteristics very similar to the typical operational amplifier. these amplifiers are short-circuit protected. the designer should verify that the output load meets the capabilities of the device, in terms of both output current and load capacitance. the dac8420 is stable with capacitive loads up to 2 nf typical. however, any capacitive load will increase the settling time, and should be minimized if speed is a concern. the output stage includes a p-channel mosfet to pull the output voltage down to the negative supply. this is very impor- tant in single supply systems, where vreflo usually has the same potential as the negative supply. with no load, the zero-scale output voltage in these applications will be less than 500 m v typically, or less than 1 lsb when v vrefhi = 2.5 v. however, when sinking current this voltage does increase because of the finite impedance of the output stage. the effec- tive value of the pull-down resistor in the output stage is typically 320 w . with a 100 k w resistor connected to +5 v, the resulting zero-scale output voltage is 16 mv. thus, the best
dac8420 rev. 0 C12C single supply operation is obtained with the output load connected to ground, so the output stage does not have to sink current. like all amplifiers, the dac8420 output buffers do generate voltage noise, 52 nv/ ? hz typically. this is easily reduced by adding a simple rc low-pass filter on each output. reference configuration the two reference inputs of the dac8420 allow a great deal of flexibility in circuit design. the user must take care, however, to observe the minimum voltage input levels on vrefhi and vreflo to maintain the accuracy shown in the data sheet. these input voltages can be set anywhere across a wide range within the supplies, but must be a minimum of 2.5 v apart in any case. see figure 1. a wide output voltage range can be obtained with 5 v references, which can be provided by the ad588 as shown in figure 28. many applications utilize the dacs to synthesize symmetric bipolar wave forms, which requires an accurate, low drift bipolar reference. the ad588 provides both voltages and needs no external components. ad- ditionally, the part is trimmed in production for 12-bit accuracy over the full temperature range without user calibration. per- forming a clear with the reset select clsel high allows the user to easily reset the dac outputs to midscale, or zero volts in these applications. when driving the reference inputs vrefhi and vreflo, it is important to note that vrefhi both sinks and sources current, and that the input currents of both are code dependent. many voltage reference products have limited current sinking capabil- ity and must be buffered with an amplifier to drive vrefhi, in order to maintain overall system accuracy. the input vreflo, however, has no such requirement. ?5v supply dac-8420 digital control 4 9 15 16 14 12 11 10 8 2 3 6 7 1 5 dac a dac b dac c dac d vouta voutb voutc voutd digital inputs gnd vreflo ?v 0.1? 0.1? +15v supply +5v vrefhi 7 r5 r4 r6 6 r b r1 r2 r3 a2 a1 a3 a4 7 6 4 3 1 14 15 11 8 12 9 5 13 2 16 0.1? 0.1? system ground ad588 ?5v supply +15v supply +5v ?v 1? 10 +v s ? s figure 28. 10 v bipolar reference configuration using the ad588
dac8420 rev. 0 C13C for a single 5 v supply, v vrefhi is limited to at most 2.5 v, and must always be at least 2.5 v less than the positive supply to ensure linearity of the device. for these applications, the ref43 is an excellent low drift 2.5 v reference that consumes only 450 m a (max). it works well with the dac8420 in a single 5 v system as shown in figure 29. dac-8420 digital control 4 9 15 16 14 12 11 10 8 2 3 6 7 1 5 dac a dac b dac c dac d vouta voutb voutc voutd digital inputs gnd vreflo 0.1? +5v supply vrefhi ref-43 vout gnd vin +5v supply 2.5v 0.1? 6 2 4 figure 29. +5 v single supply operation using ref43 isolated digital interface because the dac8420 is ideal for generating accurate voltages in process control and industrial applications, due to noise, safety requirements, or distance, it may be necessary to isolate it from the central controller. this can be easily achieved by using opto-isolators, which are commonly used to provide electrical isolation in excess of 3 kv. figure 30 shows a simple 3-wire interface scheme to control the clock, data, and load pulse. for normal operation, cs is tied permanently low so that the dac8420 is always selected. the resistor and capacitor on the c lr pin provide a power-on reset with 10 ms time constant. the three opto-isolators are used for the sdi, clk, and ld lines. one opto-isolated line ( ld ) can be eliminated from this circuit by adding an inexpensive 4-bit ttl counter to generate the load pulse for the dac8420 after 16 clock cycles. the counter is used to count of the number of clock cycles loading serial data to the dac8420. after all 16 bits have been clocked into the converter, the counter resets, and a load pulse is generated on clock 17. in either circuit, the dac8420s serial interface pro- vides a simple, low cost method of isolating the digital control. 10k w 10k w +5v 10k w ld sclk sdi +5v reg +5v power high voltage isolation +5v +5v 0.1? +5v clr clsel clk sdi ld cs 4 5 vrefhi vreflo vss gnd 1? 10k w dac-8420 vouta voutb voutc voutd ref-43 vout gnd vin +5v 6 2 4 2.5v 9 8 1 6 7 3 2 11 10 14 16 15 12 vdd figure 30. opto-lsolated 3-wire interface dual window comparator often a comparator is needed to signal an out-of-range warning. combining the dac8420 with a quad comparator such as the cmp04 provides a simple dual window comparator with adjust- able trip points as shown in figure 31. this circuit can be operated with either a dual or a single supply. for the a input channel, dac b sets the low trip point and dac a sets the up- per trip point. the cmp04 has open-collector outputs that are connected together in wired-or configuration to generate an out-of-range signal. for example, when vina goes below the trip point set by dac b, comparator c2 pulls the output down, turning the red led on. the output can also be used as a logic signal for further processing.
dac8420 rev. 0 C14C dac-8420 digital control 4 9 15 16 14 12 11 10 8 2 3 6 7 1 5 dac a dac b dac c dac d vouta voutb voutc voutd digital inputs gnd vreflo 0.1? +5v supply vrefhi vss 5 4 6 9 8 11 10 2 1 14 3 12 cmp-04 13 0.1? +5v +5v 604 w +5v red led 604 w out a out b vina vinb red led ref-43 v out gnd vin +5v supply 2.5v 0.1? 6 2 4 7 c1 c2 c3 c4 figure 31. dual programmable window comparator mc68hc11 microcontroller interfacing figure 32 shows a serial interface between the dac8420 and the mc68hc11 8-bit microcontroller. the sck output of the 68hc11 drives the clk input of the dac, and the mosi port outputs the serial data to load into the sdi input of the dac. the port lines pd5, pc0, pc1, and pc2 provide the controls to the dac as shown. pc2 pc1 pc0 (pd5) ss sck mosi mc68hc11* clsel clr cs ld clk sdi dac-8420* *additional pins omitted for clarity figure 32. mc68hc11 microcontroller interface for correct operation, the 68hc11 should be configured such that its cpol bit and cpha bit are both set to 1. in this con- figuration, serial data on mosi of the 68hc11 is valid on the rising edge of the clock, which is the required timing for the dac8420 data is transmitted in 8-bit bytes (msb first), with only eight rising clock edges occurring in the transmit cycle. to load data to the dac8420s input register, pc0 is taken low and held low during the entire loading cycle. the first 8 bits are shifted in address first, immediately followed by another 8 bits in the second least-significant byte to load the complete 16-bit word. at the end of the second byte load, pc0 is then taken high. to prevent an additional advancing of the internal shift register, sck must already be asserted before pc0 is taken high. to transfer the contents of the input shift register to the dac register, pd5 is then taken low, asserting the ld input of the dac and completing the loading process. pd5 should re- turn high before the next load cycle begins. the dac8420s clr input, controlled by the output pc1, provides an asyn- chronous clear function.
dac8420 rev. 0 C15C dac8420 to m68hc11 interface assembly program * m68hc11 register definitions portc equ $1003 port c control register * 0,0,0,0;0,clsel, clr , cs ddrc equ $1007 port c data direction portd equ $1008 port d data register * 0,0, ld ,sclk;sdi,0,0,0 ddrd equ $1009 port d data direction spcr equ $1028 spi control register * spie,spe,dwom,mstr;cpol,cpha,spr1,spr0 spsr equ $1029 spi status register * spif,wcol,0,modf;0,0,0,0 spdr equ $102a spi data register; read-buffer; write-shifter * * sdi ram variables: sdi1 is encoded from 0 (hex) to cf (hex) * to select: dac a C set sdi1 to $0x dac b C set sdi1 to $4x dac c C set sdi1 to $8x dac d C set sdi1 to $cx sdi2 is encoded from 00 (hex) to ff (hex) * dac requires two 8-bit loads C address + 12 bits sdi1 equ $00 sdi packed byte 1 a1,a0,0,0;msb,db10,db9,db8 sdi2 equ $01 sdi packed byte 2 db7,db6,db5,db4;db3,db2,db1,db0 * main program org $c000 start of users ram in evb init lds #$cfff top of c page ram * initialize port c outputs ldaa #$07 0,0,0,0;0,1,1,1 * clsel-hi, clr -hi, cs-hi * to reset dac to zero-scale, set clsel-lo ($03) * to reset dac to mid-scale, set clsel-hi ($07) staa portc initialize port c outputs ldaa #$07 0,0,0,0;0,1,1,1 staa ddrc clsel, clr , and cs are now enabled as outputs * initialize port d outputs ldaa #$30 0,0,1,1;0,0,0,0 * ld -hi,sclk-hi,sdi-lo staa portd initialize port d outputs ldaa #$38 0,0,1,1;1,0,0,0 staa ddrd ld ,sclk, and sdi are now enabled as outputs * initialize spi interface ldaa #$5f staa spcr spi is master,cpha=1,cpol=1,clk rate=e/32 * call update subroutine bsr update xfer 2 8-bit words to dac-8420 jmp $e000 restart buffalo * subroutine update update pshx save registers x, y, and a pshy psha * enter contents of sdi1 data register (dac# and 4 msbs) ldaa #$80 1,0,0,0;0,0,0,0 staa sdi1 sdi1 is set to 80 (hex) * enter contents of sdi2 data register ldaa #$00 0,0,0,0;0,0,0,0 staa sdi2 sdi2 is set to 00 (hex) ldx #sdi1 stack pointer at 1st byte to send via sdi ldy #$1000 stack pointer at on-chip registers * clear dac output to zero bclr portc,y $02 assert clr bset portc,y $02 deassert clr * get dac ready for data input bclr portc,y $01 assert cs tfrlp ldaa 0,x get a byte to transfer via spi staa spdr write sdi data reg to start xfer wait ldaa spsr loop to wait for spif bpl wait spif is the msb of spsr * (when spif is set, spsr is negated) inx increment counter to next byte for xfer cpx #sdi2+ 1 are we done yet ? bne tfrlp if not, xfer the second byte * update dac output with contents of dac register bclr portd,y 520 assert ld bset portd,y $20 latch dac register bset portc,y $01 de-assert cs pula when done, restore registers x, y & a puly pulx rts ** return to main program **
dac8420 rev. 0 C16C c1836C18C9/93 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 16-pin epoxy dip (p suffix) 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc pin 1 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) seating plane 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.840 (21.33) 0.745 (18.93) 9 16 1 8 16-pin wide-body sol (sol) pin 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 16 9 8 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.1043 (2.65) 0.0926 (2.35) 0.4133 (10.50) 0.3977 (10.00) 0.0118 (0.30) 0.0040 (0.10) 16-pin cerdip (q suffix) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15 0 0.005 (0.13) min pin 1 0.080 (2.03) max 0.310 (7.87) 0.220 (5.59) 1 8 9 0.840 (21.34) max 0.200 (5.08) max 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane 16

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