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lxt9784 low-power octal phy datasheet the lxt9784 is an eight-port fast ethernet phy transceiver supporting ieee 802.3 10mbps and 100mbps physical layer applications. it provides both a reduced media independent interface (rmii) and a serial media independent interface (smii) for switching and other independent port applications. in rmii mode, each phy has a discrete exposed rmii interface, and in smii mode a discrete exposed smii interface. all network ports provide a twisted-pair (tp) interface for a 10/100base-tx connection. the lxt9784 provides three discrete led driver outputs for each port. the device supports both half- and full-duplex 10mbps and 100mbps operation, and requires only a single 3.3v power supply. for low power applications the devices may be powered by a single 3.0v power supply. advanced design techniques result in very low power requirements. the lxt9784 also supports an auto-mdix feature as well as an integrated hardware integrity (hwi) feature that utilizes a time domain reflectometry (tdr) technique to locate and report problems with the cable plant. product features eight ieee 802.3 standard-compliant 10base-t or 100base-tx ports with integrated filters. automatic mdi/mdix switch over capability. integrated hardware integrity (hwi): device ports detect and report cabling problems via mdio. uses 1:1 magnetic device for 10/100 mbps operation, allowing low-cost design. supports both ieee 802.3u auto- negotiation and parallel detection operation. controls all 8 ports through one single ieee 802.3 standard compliant mii management bus. automatic polarity correction at 10m data rate. robust baseline wander correction for improved 100base-tx performance. eight reduced mii (rmii) and serial mii (smii) ports for independent phy port operation. low power consumption, 3.0v and 3.3v operation. 324-lead pbga package. ? LXT9784BC - commercial (0 to 70 c ambient). ? lxt9784be - extended (-40 to 85 c ambient). as of january 15, 2001, this document replaces the level one document order number: 249272-001 lxt9784 low-power octal phy datasheet . january 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt9784 may contain design defects or errors known as errata which may cause the product to deviate from published specific ations. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 low-power octal phy ? lxt9784 contents 1.0 pin assignments and signal descriptions ....................................................10 2.0 functional description ...........................................................................................29 2.1 introduction..........................................................................................................29 2.2 lxt9784 configuration .......................................................................................29 2.3 100base-tx mode .............................................................................................30 2.3.1 100base-tx receiver ...........................................................................30 2.3.1.1 digital adaptive equalizer .........................................................30 2.3.1.2 receive clock and data recovery............................................30 2.3.1.3 baseline wander correction .....................................................31 2.3.1.4 decoder .....................................................................................31 2.3.1.5 100base-tx receive framing .................................................31 2.3.1.6 100base-tx rmii data reception...........................................31 2.3.1.7 100base-tx smii data reception ...........................................31 2.3.1.8 100base-tx receive error detection and reporting ..............32 2.3.2 100base-tx transmitter.......................................................................33 2.3.2.1 100base-tx 4b/5b encoder ....................................................33 2.3.2.2 100base-tx scrambler and mlt-3 encoder ...........................33 2.3.2.3 transmit driver ..........................................................................35 2.3.2.4 100base-tx transmit framing ................................................35 2.4 10base-t mode .................................................................................................36 2.4.1 10base-t receiver ...............................................................................36 2.4.1.1 10base-t manchester decoder ...............................................36 2.4.1.2 10base-t receive buffer and filter .........................................37 2.4.1.3 10base-t error detection and reporting.................................37 2.4.1.4 10base-t link integrity ............................................................37 2.4.1.5 10base-t jabber control function ..........................................37 2.4.1.6 10base-t full duplex ..............................................................38 2.4.2 10base-t transmit ...............................................................................38 2.4.2.1 10base-t manchester encoder ...............................................38 2.4.2.2 10base-t driver and filter .......................................................38 2.5 mdi/mdi-x function............................................................................................38 2.5.1 mdi/mdi-x auto switching activation ....................................................39 2.5.2 mdi/mdi-x algorithm .............................................................................39 2.6 hardware control interface .................................................................................40 2.6.1 mdi-x (mdi crossover) ..........................................................................40 2.6.2 frclnk (force link).............................................................................40 2.6.3 frc34 (force 34 transmit pattern) .......................................................40 2.6.4 bp4b5b (4b/5b bypass)........................................................................40 2.6.5 scrmbp (scrambler bypass) ...............................................................41 2.7 phy addresses ...................................................................................................41 2.8 link status interrupt ............................................................................................41 2.9 reset ...................................................................................................................42 2.10 led operation.....................................................................................................42 2.11 mii management interface operation..................................................................43 2.12 test port operation .............................................................................................44 2.12.1 nand-tree test.....................................................................................44 2.12.2 xnor-tree test ....................................................................................45
lxt9784 ? low-power octal phy 4 datasheet 2.12.3 nand/xnor tree chain order............................................................. 45 3.0 application information ......................................................................................... 48 3.1 magnetics............................................................................................................ 48 3.2 analog references (rbias) ............................................................................... 48 3.3 rmii applications ................................................................................................ 48 3.3.1 rmii clock.............................................................................................. 49 3.4 smii applications ................................................................................................ 49 3.4.1 smii clock .............................................................................................. 50 4.0 test specifications .................................................................................................. 51 4.1 dc characteristics .............................................................................................. 52 4.2 ac characteristics .............................................................................................. 53 4.2.1 common characteristics ........................................................................ 54 4.3 rmii interface...................................................................................................... 56 4.4 smii interface...................................................................................................... 57 4.5 reset timing parameters ................................................................................... 58 4.6 clock specifications ............................................................................................ 59 4.6.1 mclk specifications .............................................................................. 59 5.0 register definitions ................................................................................................ 60 6.0 mechanical specifications ................................................................................... 68
datasheet 5 low-power octal phy ? lxt9784 figures 1 lxt9784 block diagram ....................................................................................... 9 2 lxt9784 ball assignments - rmii mode ............................................................10 3 lxt9784 ball assignments - smii mode.............................................................11 4 lxt9784 phy in a 10/100 mbps ethernet solution ............................................29 5 rmii data reception ...........................................................................................32 6 false carrier detect ............................................................................................32 7 smii received serial data stream......................................................................33 8 nrz to mlt-3 encoding diagram ........................................................................34 9 rmii data transmission......................................................................................36 10 smii transmit data serial stream.......................................................................36 11 simplified interrupt structure...............................................................................42 12 typical rbias circuit ..........................................................................................48 13 typical rmii application......................................................................................49 14 typical smii application ......................................................................................50 15 ac testing level conditions ...............................................................................54 16 mdc clock ac timing ........................................................................................54 17 mii management timing parameters: mdc/mdio .............................................54 18 normal link pulse timings..................................................................................55 19 fast link pulse timings ......................................................................................55 20 rmii ac testing level conditions ......................................................................56 21 rmii rise and fall timings .................................................................................56 22 rmii timing parameters .....................................................................................57 23 smii mode - ac testing level conditions ..........................................................57 24 smii timing parameters......................................................................................58 25 reset timing parameters....................................................................................58 26 master clock specifications ................................................................................59 27 master clock slope specifications ......................................................................59 28 package specifications .......................................................................................68
lxt9784 ? low-power octal phy 6 datasheet tables 1 signal types ....................................................................................................... 11 2 numeric pad assignments.................................................................................. 12 3 network interface signal descriptions ................................................................ 22 4 mdio signal descriptions ................................................................................... 23 5 led signal descriptions ..................................................................................... 23 6 power supply signal descriptions ...................................................................... 24 7 miscellaneous signal descriptions...................................................................... 25 8 rmii mode signal descriptions........................................................................... 26 9 smii mode signal descriptions ........................................................................... 27 10 unused pins........................................................................................................ 28 11 lxt9784 modes of operation ............................................................................. 30 12 smii rxd_[7:0] contents.................................................................................... 32 13 4b/5b coding ...................................................................................................... 34 14 straight-through pin assignments....................................................................... 39 15 crossed-over pin assignments........................................................................... 39 16 phy addresses................................................................................................... 41 17 led functionality ................................................................................................ 43 18 activity led blink rates...................................................................................... 43 19 mii management frame format ......................................................................... 43 20 glossary of protocol terms................................................................................. 44 21 test mode configuration..................................................................................... 44 22 test scan chain.................................................................................................. 45 23 magnetics module vendor .................................................................................. 48 24 absolute maximum ratings ................................................................................ 51 25 operating conditions .......................................................................................... 51 26 clock dc characteristics .................................................................................... 52 27 rmii/smii and general interface1 dc characteristics ....................................... 52 28 led dc characteristics ...................................................................................... 52 29 10base-t receiver voltage/current dc characteristics................................... 52 30 10base-t transmitter voltage/current dc characteristics ............................... 53 31 100base-tx receiver voltage/current dc characteristics .............................. 53 32 100base-tx transmitter voltage/current dc characteristics .......................... 53 33 mii management clock specifications ................................................................ 54 34 mii management interface timing parameters................................................... 55 35 10base-t normal link pulse (nlp) timing parameters ................................... 55 36 auto-negotiation fast link pulse (flp) timing parameters .............................. 55 37 100base-tx transmitter ac specifications ...................................................... 56 38 rmii interface timing parameters ...................................................................... 57 39 smii interface timing parameters ...................................................................... 58 40 reset timing parameters ................................................................................... 58 41 mclk specifications ........................................................................................... 59 42 bit type designations ......................................................................................... 60 43 control register (register 0) bit definitions ....................................................... 60 44 status register (register 1) bit definitions......................................................... 61 45 phy identifier register (register 2) bit definitions ............................................. 62 46 phy identifier register (register 3) bit definitions ............................................. 62 47 auto-negotiation advertisement register (register 4) bit definitions ................ 62 48 auto-negotiation link partner ability register (base page) (register 5) bit definitions .................................................................................. 63
datasheet 7 low-power octal phy ? lxt9784 49 auto-negotiation expansion register (register 6) bit definitions.......................63 50 register 16 (10 hex) status and control ............................................................64 51 register 17 (11 hex) special control..................................................................64 52 register 18 (12 hex) phy interrupt register ......................................................65 53 reg 19 (13 hex) 100 base-tx rcv false carrier counter ..............................65 54 reg 20 (14 hex) 100basetx receive disconnect counter...............................66 55 reg 21 (15 hex) 100basetx receive error frame counter .............................66 56 reg 22 (16 hex) receive symbol error counter ................................................66 57 reg 23 (17 hex) 100basetx receive premature end of frame error counter 66 58 reg 24 (18 hex) 10baset receive end of frame error counter......................66 59 reg 25 (19 hex) 10baset transmit jabber detect counter .............................66 60 reg 26 (1a hex) reserved .................................................................................67 61 register 27 (1b hex) phy special control .........................................................67
lxt9784 ? low-power octal phy 8 datasheet revision history revision date description
low-power octal phy ? lxt9784 datasheet 9 figure 1. lxt9784 block diagram digital equalizer adaptation equalizer & blw correction digital clock recovery (100) 100base- tx pcs crs/link10 detection digital clock recovery (10) 10base-t pcs mdi / mdi-x xmit dac 10/100 rmii i/f smii i/f auto- negotiation tpip/tpin tpop/tpon mii mgmt i/f mii register set mdio mdc id<1:0> per-port led drivers leda ledb ledc mode [2:0] rmii / smii port 1 of 8 lxt9784
lxt9784 ? low-power octal phy 10 datasheet 1.0 pin assignments and signal descriptions figure 2. lxt9784 ball assignments - rmii mode nc crsdv7 crsdv5 txd5_1 txen6 rxd6_0 mode_0 txen4 rxd4_0 txd4 frclnk txen3 rxd1_0 txen1 txd2_1 crsdv2 rxd3_0 crsdv0 txd0_1 nc txd7_1 txen7 rxd7_0 txd6_1 txen5 crsdv4 rxd5_0 mode_1 txd4_1 mode_2 txd3_0 rxd3_1 txd2_0 rxd2_1 txd0_0 rxd0_1 rxd1_1 txd1_0 nc nc txd7_0 rxd4_1 rxd6_1 rxd7_1 txd5_0 txd6_0 rxd5_1 mclk txd4_0 frc34 txd3_1 txen2 rxd2_0 crsdv3 txen0 rxd0_0 crsdv1 txd1_1 nc nc nc nc nc gnd gnd vccio gnd vccio vccio gnd vccio gnd vccio gnd vccio nc nc nc nc tpon7 nc vcc vcc vcc vcc vcc vcc gnd nc vcc vcc nc gnd tpipo tpop0 gnd gnd tpin7 nc tpip7 tpop7 nc nc vcc nc nc vccr tpon0 vcc vccr nc tpino nc nc nc nc nc gnd nc nc nc nc gnd gnd tpin6 tpon6 tpip1 gnd gnd tpop1 nc nc gnd rbias 10_1 rbias 10_0 gnd vcc gnd gnd vcc gnd gnd gnd gnd gnd gnd gnd gnd tpop2 nc tpip2 gnd tpon5 gnd tpin5 nc gnd gnd gnd gnd gnd gnd nc nc nc nc nc nc nc nc gnd nc gnd tpop3 nc gnd tpip3 nc nc gnd tpin4 nc tpon4 gnd nc tpon3 nc vcc vccr tpin3 nc vcc vcc vcc vcc vcc vcc vcc vcc vcc nc tpop4 tpip4 vccr nc nc nc vccio gnd gnd nc nc vccio gnd vccio vccio gnd vcc gnd nc nc nc nc gnd vccio nc led0_c nc nc led1_c rxer6 rxer3 led2_c led3_c rxer0 mdi-x texec nc reset nc int led7_b led6_b led5_b led4_b nc nc nc led0_b led1_b rxer2 rxer5 led2_b led3_b id_1 bp4b5b nc ti nc mdc led7_a led6_a led5_a led4_a led3_a nc led2_a rxer7 nc led0_a nc rxer1 led1_a tck nc scrmbp id_0 rxer4 nc tout mdio led7_c led6_c led5_c led4_c vcc tpon2 nc tpin2 vccr tpop5 tpip5 nc vcc vccr vcc rbias 100_1 rbias 100_0 gnd vcc gnd vcc gnd vcc gnd gnd gnd gnd gnd gnd gnd gnd gnd tpop6 nc vcc tpin1 nc vccr tpon1 tpip6 vcc vccr a b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y 12345678 1112 14151617181920 13 10 9 12345678 1112 14151617181920 13 10 9 crsdv6
low-power octal phy ? lxt9784 datasheet 11 figure 3. lxt9784 ball assignments - smii mode table 1. signal types type name definition i input standard input only signal. o output standard output-only signal. i/o bidirectional this is an input and output ball. nc nc nc nc nc rxd6 mode_0 nc rxd4 sync frclnk nc rxd1 nc nc nc rxd3 nc nc nc nc nc rxd7 nc nc nc nc rxd5 mode_1 nc mode_2 txd3 nc txd2 nc txd0 nc nc txd1 nc nc txd7 nc nc nc txd5 txd6 nc mclk txd4 frc34 nc nc rxd2 nc nc rxd0 nc nc nc nc nc nc nc gnd gnd vccio gnd vccio vccio gnd vccio gnd vccio gnd vccio nc nc nc nc tpon7 nc vcc vcc vcc vcc vcc vcc gnd nc vcc vcc nc gnd tpipo tpop0 gnd gnd tpin7 nc tpip7 tpop7 nc nc vcc nc nc vccr tpon0 vcc vccr nc tpino nc nc nc nc nc gnd nc nc nc nc gnd gnd tpin6 tpon6 tpip1 gnd gnd tpop1 nc nc gnd rbias 10_1 rbias 10_0 gnd vcc gnd gnd vcc gnd gnd gnd gnd gnd gnd gnd gnd tpop2 nc tpip2 gnd tpon5 gnd tpin5 nc gnd gnd gnd gnd gnd gnd nc nc nc nc nc nc nc nc gnd nc gnd tpop3 nc gnd tpip3 nc nc gnd tpin4 nc tpon4 gnd nc tpon3 nc vcc vccr tpin3 nc vcc vcc vcc vcc vcc vcc vcc vcc vcc nc tpop4 tpip4 vccr nc nc nc vccio gnd gnd nc nc vccio gnd vccio vccio gnd vcc gnd nc nc nc nc gnd vccio nc led0_c nc nc led1_c nc nc led2_c led3_c nc mdi-x texec nc reset nc int led7_b led6_b led5_b led4_b nc nc nc led0_b led1_b nc nc led2_b led3_b id_1 bp4b5b nc ti nc mdc led7_a led6_a led5_a led4_a led3_a nc led2_a nc nc led0_a nc nc led1_a tck nc scrmbp id_0 nc nc tout mdio led7_c led6_c led5_c led4_c vcc tpon2 nc tpin2 vccr tpop5 tpip5 nc vcc vccr vcc rbias 100_1 rbias 100_0 gnd vcc gnd vcc gnd vcc gnd gnd gnd gnd gnd gnd gnd gnd gnd tpop6 nc vcc tpin1 nc vccr tpon1 tpip6 vcc vccr a b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y 12345678 1112 14151617181920 13 10 9 1 2 3 4 5 6 7 8 11 12 14 15 16 17 18 19 20 13 10 9
lxt9784 ? low-power octal phy 12 datasheet od open-drain output this open drain ball allows multiple devices to share this signal as a wired-ored. oz tri-state output high impedance pu internal weak pull-up input ball, external pull-up device is not required. pd internal weak pull-down input ball, external pull-down device is not required. epu external pull up pull this ball up to 3.3v through a 10k ohm resistor. epd external pull down pull this ball down to ground through a 10k ohm resistor. mlt multi-level analog i/o presented on mdi balls while in 100m mode of operation. a_pwr power (analog) connect the marked balls to separate analog planes. nc no connect this ball is not used and can be left floating. table 2. numeric pad assignments ball symbol type 1 reference for full description a1 - nc - a2 txd7_1 (rmii) i table 8 on page 26 not used (smii) nc - a3 - nc - a4 - nc - a5 tpon7 mlt table 3 on page 22 a6 tpop7 mlt table 3 on page 22 a7 - nc - a8 tpon6 mlt table 3 on page 22 a9 tpop6 mlt table 3 on page 22 a10 rbias100_1 i table 7 on page 25 a11 rbias10_1 i table 7 on page 25 a12 tpon5 mlt table 3 on page 22 a13 tpop5 mlt table 3 on page 22 a14 - nc - a15 tpon4 mlt table 3 on page 22 a16 tpop4 mlt table 3 on page 22 a17 - nc a18 - nc - a19 - nc - a20 - nc - b1 crsdv7 (rmii) o table 3 on page 22 not used (smii) nc - 1. refer to table 1 on page 11 for signal type definitions. table 1. signal types type name definition
low-power octal phy ? lxt9784 datasheet 13 b2 txen7 (rmii) i table 8 on page 26 not used (smii) nc b3 txd7_0 (rmii) i table 9 on page 27 txd7 (smii) i table 9 on page 27 b4 - nc - b5 - nc - b6 - nc - b7 - nc - b8 - nc - b9 - nc - b10 vcc table 6 on page 24 b11 vcc table 6 on page 24 b12 - nc - b13 - nc b14 - nc b15 - nc b16 - nc b17 - nc b18 int od table 7 on page 25 b19 mdc i table 4 on page 23 b20 tout o table 7 on page 25 c1 rxd6_0 (rmii) o table 8 on page 26 rxd6 (smii) o table 9 on page 27 c2 rxd7_0 (rmii) o table 8 on page 26 rxd7 (smii) o table 9 on page 27 c3 rxd7_1 (rmii) o table 8 on page 26 not used (smii) nc c4 - nc c5 tpin7 mlt table 3 on page 22 c6 tpip7 mlt table 3 on page 22 c7 - nc c8 tpin6 mlt table 3 on page 22 c9 tpip6 mlt table 3 on page 22 c10 gnd c11 gnd c12 tpin5 mlt table 3 on page 22 c13 tpip5 mlt table 3 on page 22 table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
lxt9784 ? low-power octal phy 14 datasheet c14 - nc c15 tpin4 mlt table 3 on page 22 c16 tpip4 mlt table 3 on page 22 c17 - nc c18 led7_b o table 5 on page 23 c19 led7_a o table 5 on page 23 c20 mdio i/o table 4 on page 23 d1 txen6 (rmii) i table 8 on page 26 not used (smii) nc d2 crsdv6 (rmii) o table 8 on page 26 not used (smii) nc d3 rxd6_1 (rmii) o table 8 on page 26 not used (smii) nc d4 - nc d5 gnd d6 vccr a_pwr d7 - nc d8 gnd d9 vccr a_pwr d10 vcc d11 gnd d12 gnd d13 vccr a_pwr d14 - nc d15 gnd d16 vccr a_pwr d17 - nc d18 led6_b o table 5 on page 23 d19 led6_a o table 5 on page 23 d20 led7_c o table 5 on page 23 e1 txd5_1 (rmii) i table 8 on page 26 not used (smii) nc e2 txd6_1 (rmii) i table 8 on page 26 not used (smii) nc e3 txd6_0 (rmii) i table 8 on page 26 txd6 (smii) i table 9 on page 27 e4 vccio table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
low-power octal phy ? lxt9784 datasheet 15 e5 gnd e6 vcc e7 gnd e8 gnd e9 vcc e10 gnd e11 gnd e12 gnd e13 vcc e14 gnd e15 gnd e16 vcc e17 vccio e18 led5_b o table 5 on page 23 e19 led5_a o table 5 on page 23 e20 led6_c o table 5 on page 23 f1 crsdv5 (rmii) o table 8 on page 26 not used (smii) nc f2 txen5 (rmii) i table 8 on page 26 not used (smii) nc f3 txd5_0 (rmii) i table 8 on page 26 txd5 i table 9 on page 27 f4 gnd f5 - nc f6 - nc f14 - nc f15 - nc f16 - nc f17 gnd f18 led4_b o table 5 on page 23 f19 led4_a o table 5 on page 23 f20 led5_c o table 5 on page 23 g1 rxd4_0 (rmii) o table 8 on page 26 rxd4 (smii) o table 9 on page 27 g2 rxd5_0 (rmii) o table 8 on page 26 rxd5 (smii) o table 9 on page 27 table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
lxt9784 ? low-power octal phy 16 datasheet g3 rxd5_1 (rmii) o table 8 on page 26 not used (smii) nc g4 vccio g5 vcc g6 - nc g16 vcc g17 vccio g18 mdi-x i-pu table 7 on page 25 g19 led3_a o table 5 on page 23 g20 led4_c o table 5 on page 23 h1 txen4 (rmii) i table 8 on page 26 nc (smii) pd h2 crsdv4 (rmii) o table 8 on page 26 nc (smii) pd h3 rxd4_1 (rmii) o table 8 on page 26 nc (smii) pd h4 gnd h5 vcc h16 vcc h17 gnd h18 texec i table 7 on page 25 h19 ti i table 7 on page 25 h20 tck i table 7 on page 25 j1 mode_0 i table 7 on page 25 j2 txd4_1 (rmii) i table 7 on page 25 not used (smii) nc j3 txd4_0 (rmii) i table 8 on page 26 txd4 (smii) i table 9 on page 27 j4 vccio table 8 on page 26 j5 vcc j9 gnd j10 gnd j11 gnd j12 gnd j16 vcc j17 vcc j18 - nc table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
low-power octal phy ? lxt9784 datasheet 17 j19 - nc j20 - nc k1 frclnk i-pd table 7 on page 25 k2 mode_1 i table 7 on page 25 k3 mclk i table 7 on page 25 k4 gnd k5 vcc k9 gnd k10 gnd k11 gnd k12 gnd k16 vcc k17 gnd k18 reset i table 7 on page 25 k19 bp4b5b i-pd table 7 on page 25 k20 scrmbp i-pd table 7 on page 25 l1 txd4 (rmii) i table 8 on page 26 sync (smii) i table 9 on page 27 l2 mode_2 ext-pd table 7 on page 25 l3 frc34 i-pd table 7 on page 25 l4 vccio l5 vcc l9 gnd l10 gnd l11 gnd l12 gnd l16 vcc l17 vccio l18 rxer0 (rmii) o table 8 on page 26 not used (smii) nc l19 id_1 i-pd table 7 on page 25 l20 id_0 i-pd table 7 on page 25 m1 txen3 (rmii) i table 8 on page 26 not used (smii) nc m2 txd3_0 (rmii) i table 8 on page 26 txd3 (smii) table 9 on page 27 table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
lxt9784 ? low-power octal phy 18 datasheet m3 txd3_1 (rmii) i table 8 on page 26 not used (smii) nc m4 gnd m5 vcc m9 gnd m10 gnd m11 gnd m12 gnd m16 vcc m17 gnd m18 rxer3 o table 8 on page 26 m19 rxer2 o table 8 on page 26 m20 rxer1 o table 8 on page 26 n1 rxd3_0 (rmii) o table 8 on page 26 rxd3 (smii) o table 9 on page 27 n2 rxd3_1 (rmii) o table 8 on page 26 not used (smii) nc n3 crsdv3 (rmii) o table 8 on page 26 not used (smii) nc n4 vccio n5 vcc n16 vcc n17 vccio n18 rxer6 (rmii) o table 8 on page 26 not used (smii) nc n19 rxer5 (rmii) o table 8 on page 26 not used (smii) nc n20 rxer4 (rmii) o table 8 on page 26 not used (smii) nc p1 crsdv2 (rmii) o table 8 on page 26 not used (smii) nc p2 rxd2_1 (rmii) o table 8 on page 26 not used (smii) nc p3 rxd2_0 o table 8 on page 26 rxd2 o table 8 on page 26 p4 gnd p5 vcc table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
low-power octal phy ? lxt9784 datasheet 19 p15 - nc p16 vcc p17 gnd p18 led3_c o table 5 on page 23 p19 led3_b o table 5 on page 23 p20 rxer7 o table 8 on page 26 r1 txd2_1 (rmii) i table 8 on page 26 not used (smii) nc r2 txd2_0 (rmii) i table 8 on page 26 txd2 (smii) i table 9 on page 27 r3 txen2 (rmii) i table 8 on page 26 not used (smii) nc r4 vccio table 8 on page 26 r5 - nc r6 - nc r7 - nc r15 - nc r16 - nc r17 vccio r18 led2_c o table 5 on page 23 r19 led2_b o table 5 on page 23 r20 led2_a o table 5 on page 23 t1 txen1 (rmii) i table 8 on page 26 not used (smii) nc t2 txd1_0 (rmii) i table 8 on page 26 txd1 (smii) i table 9 on page 27 t3 txd1_1 (rmii) i table 8 on page 26 not used (smii) nc t4 gnd t5 gnd t6 vcc t7 gnd t8 gnd t9 vcc t10 gnd t11 gnd t12 gnd table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
lxt9784 ? low-power octal phy 20 datasheet t13 vcc t14 gnd t15 gnd t16 vcc t17 gnd t18 led1_c o table 5 on page 23 t19 led1_b o table 5 on page 23 t20 led1_a o table 5 on page 23 u1 rxd1_0 (rmii) o table 8 on page 26 rxd1 (smii) o table 9 on page 27 u2 rxd1_1 (rmii) o table 8 on page 26 not used (smii) nc u3 crsdv1 (rmii) o table 8 on page 26 not used (smii) nc u4 - nc u5 gnd u6 vccr a_pwr u7 - nc u8 gnd u9 vccr a_pwr u10 vcc u11 gnd u12 gnd u13 vccr a_pwr u14 - nc u15 gnd u16 vccr a_pwr u17 - nc u18 led0_c o table 5 on page 23 u19 led0_b o table 5 on page 23 u20 led0_a o table 5 on page 23 v1 crsdv0 (rmii) o table 8 on page 26 not used (smii) nc v2 rxd0_1 (rmii) o table 8 on page 26 not used (smii) nc v3 rxd0_0 (rmii) o table 8 on page 26 rxd0 (smii) o table 9 on page 27 table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
low-power octal phy ? lxt9784 datasheet 21 v4 - nc v5 tpip0 mlt table 3 on page 22 v6 tpin0 mlt table 3 on page 22 v7 - nc v8 tpip1 mlt table 3 on page 22 v9 tpin1 mlt table 3 on page 22 v10 gnd v11 gnd v12 tpip2 mlt table 3 on page 22 v13 tpin2 mlt table 3 on page 22 v14 - nc v15 tpip3 mlt table 3 on page 22 v16 tpin3 mlt table 3 on page 22 v17 - nc v18 - nc v19 - nc v20 - nc w1 txd0_1 (rmii) i table 8 on page 26 not used (smii) nc w2 txd0_0 (rmii) i table 8 on page 26 txd0 (smii) i table 9 on page 27 w3 txen0 (rmii) i table 8 on page 26 not used (smii) nc - w4 - nc - w5 - nc - w6 - nc - w7 - nc - w8 - nc - w9 - nc - w10 vcc - w11 vcc - w12 - nc - w13 - nc - w14 - nc - w15 - nc - w16 - nc - w17 - nc - table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
lxt9784 ? low-power octal phy 22 datasheet w18 - nc - w19 - nc - w20 - nc - y1 - nc - y2 - nc - y3 - nc - y4 - nc y5 tpop0 mlt table 3 on page 22 y6 tpon0 mlt table 3 on page 22 y7 - nc y8 tpop1 mlt table 3 on page 22 y9 tpon1 mlt table 3 on page 22 y10 rbias100_0 i table 7 on page 25 y11 rbias10_0 i table 7 on page 25 y12 tpop2 mlt table 3 on page 22 y13 tpon2 mlt table 3 on page 22 y14 - nc y15 tpop3 mlt table 3 on page 22 y16 tpon3 mlt table 3 on page 22 y17 - nc - y18 - nc - y19 - nc - y20 - nc - table 3. network interface signal descriptions ball id signal name type 1 signal description y5, y6 tpop0, tpon0 mlt transmit differential pair, ports 0-7. these pins transmit the serial bit-stream on an unshielded twisted pair (utp) cable. the differential pair is a two-level signal in 10base-t mode (manchester) or a three-level signal in 100base-tx mode (mlt- 3). these signals interface directly with an isolation transformer. y8, y9 tpop1, tpon1 y12, y13 tpop2, tpon2 y15, y16 tpop3, tpon3 a16, a15 tpop4, tpon4 a13, a12 tpop5, tpon5 a9, a8 tpop6, tpon6 a6, a5 tpop7, tpon7 1. refer to table 1 on page 11 for signal type definitions. table 2. numeric pad assignments (continued) ball symbol type 1 reference for full description 1. refer to table 1 on page 11 for signal type definitions.
low-power octal phy ? lxt9784 datasheet 23 v5, v6 tpip0, tpin0 mlt receive differential pair, ports 0-7. these pins receive the serial bit-stream on an unshielded twisted pair (utp) cable. the differential pair is a two-level signal in 10base-t mode (manchester) or a three-level signal in 100base-tx mode (mlt- 3). these signals interface directly with an isolation transformer. v8, v9 tpip1, tpin1 v12, v13 tpip2, tpin2 v15, v16 tpip3, tpin3 c16, c15 tpip4, tpin4 c13, c12 tpip5, tpin5 c9, c8 tpip6, tpin6 c6, c5 tpip7, tpin7 table 4. mdio signal descriptions ball id signal name type 1 signal description c20 mdio i/o management data input/output. the mdio signal is a bi-directional data pin for the management data interface. when this signal is not used, a pull- up resistor is required. b19 mdc i management data clock. the mdc signal functions as a clock reference for the mdio signal. mdc can operate at a maximum frequency of 3 mhz. when this signal is not used, a pull-up resistor is required. 1. refer to table 1 on page 6 for signal type definitions. table 5. led signal descriptions ball id signal name type 1 signal description u20 led0_a o link/activity led, ports 0-7. with a good link the output is low. the output blinks at a rate related to the utilization. t20 led1_a r20 led2_a g19 led3_a f19 led4_a e19 led5_a d19 led6_a c19 led7_a 1. o = output. refer to table 1 for additional signal type definitions. table 3. network interface signal descriptions (continued) ball id signal name type 1 signal description 1. refer to table 1 on page 11 for signal type definitions.
lxt9784 ? low-power octal phy 24 datasheet u19 led0_b o speed led, ports 0-7. indicates speed of operation. the output is low for 100 mbps, and high for 10 mbps. t19 led1_b r19 led2_b p19 led3_b f18 led4_b e18 led5_b d18 led6_b c18 led7_b u18 led0_c o collision led, ports 0-7. when in rmii or smii modes of operation, the output blinks low with collisions stretch rate of 10 ms. t18 led1_c r18 led2_c p18 led3_c g20 led4_c f20 led5_c e20 led6_c d20 led7_c table 6. power supply signal descriptions ball id symbol type signal description d6, d9, d13, d16, u6, u9, u13, u16 vccr analog receiver power supply. +3.3v supply for core analog circuits. e4, e17, g4, g17, j4, l4, l17, n4, n17, r4, r17 vcci/o digital i/o power supply. +3.3v supply for core digital circuits. b10, b11, d10, e6, e9, e13, e16, g5, g16, h5, h16, j5, j16, j17, k5, k16, l5, l16, m5, m16, n5, n16, p5, p16, t6, t9, t13, t16, u10, w10, w11 vcc a/d primary power supply. +3.3v supply for all circuits except receiver and i/o. c10, c11, d8, d5, d11, d12, d15, e5, e7, e8, e10,e11,e12, e14, e15, f4, f17, h4, h17, j9, j10, j11, j12, k4, k9, k10, k11, k12, k17, l9, l10, l11, l12, m4, m9, m10, m11, m12, m17, p4, p17, t4, t5, t7, t8, t10,t11, t12, t14, t15, t17, u5, u8, u11, u12, u15, v10, v11 gnd return ground. power supply return. table 5. led signal descriptions (continued) ball id signal name type 1 signal description 1. o = output. refer to table 1 for additional signal type definitions.
low-power octal phy ? lxt9784 datasheet 25 table 7. miscellaneous signal descriptions ball id signal name type 1 description y11, a11 rbias10_0 rbias10_1 b bias reference resistor 10. a 464 ? 1% resistor should be connected from this pin to ground. this determines the current source in 10m mode. y10, a10 rbias100_0 rbias100_1 b bias reference resistor 100. a 619 ? 1% resistor should be connected from this pin to ground. this determines the current source in 100m mode. k3 mclk i master clock. the lxt9784 master input clock, 35/65 duty cycle, 50ppm. the mclk frequency varies, based on the mode. mode is set by the mode<2:0> pins. in rmii mode, mode<2:0> = 001, mclk = 50 mhz in smii mode, mode<2:0> = 010, mclk = 125 mhz k18 reset i reset. the reset signal is active high and resets the lxt9784. a reset pulse width of at least 500 s should be used. j1, k2, l2 mode_0 mode_1 mode_2 i mode of operation. sets the lxt9784 mode of operation. see table 10. l20, l19 id_0 id_1 i-pd id. sets the two most significant bits of the phy addresses. the id<1:0> pins are used to set the phy addresses for accessing the phy registers through the mii management interface. b18 int od link status interrupt. the link status change interrupt line. k19 bp4b5b i-pd 4b5b encoder bypass. if bp4b5b is high, the 4b5b encoder / 5b4b decoder will be bypassed in 100 mbps mode of operation. k20 scrmbp i-pd scrambler/descrambler bypass. if scrmbp is high, the scrambler/ descrambler of tp-pmd will be bypassed in 100 mbps mode of operation. k1 frclnk i-pd force link. when high, force good link at speed of operation. l3 frc34 i-pd force 34 pattern. when high, force the 34 pattern in 100m only. g18 mdi-x i-pu mdi-x enable. when high, enable the mdi/mdi-x automatic detection and switch-over feature. h19 ti i test input. sets the device into manufacturing test mode (mode<2:0>= ? 111 ? ). should be externally pulled low when not in use. h18 texec i test execute command. sets the device into async test mode (mode<2:0>= ? 111 ? ). should be externally pulled low when not in use. h20 tck i test clock. the test clock signal. should be externally pulled low when not in use. b20 tout o test output. the test output port. 1. refer to table 1 on page 11 for signal type definitions.
lxt9784 ? low-power octal phy 26 datasheet table 8. rmii mode signal descriptions ball id signal name type 1 signal description v1 crsdv0 o carrier sense / receive data valid, ports 0-7. crs and rxdv signals of the mii interface are collapsed into one signal. this signal indicates to the lxt9784 that traffic is present on the link, and that the incoming data on the rxd<1:0> pins is valid. u3 crsdv1 p1 crsdv2 n3 crsdv3 h2 crsdv4 f1 crsdv5 d2 crsdv6 b1 crsdv7 l18 rxer0 o receive error, ports 0-7. the rxer signal indicates to the lxt9784 that an error has occurred during frame reception. m20 rxer1 m19 rxer2 m18 rxer3 n20 rxer4 n19 rxer5 n18 rxer6 p20 rxer7 v2, v3 rxd0_1, rxd0_0 o receive data, ports 0-7. in 100 mbps and 10 mbps mode, data is transferred across these two lines. u2, u1 rxd1_1, rxd1_0 p2, p3 rxd2_1, rxd2_0 n2, n1 rxd3_1, rxd3_0 h3, g1 rxd4_1, rxd4_0 g3, g2 rxd5_1, rxd5_0 d3, c1 rxd6_1, rxd6_0 c3, c2 rxd7_1, rxd7_0 w1, w2 txd0_1, txd0_0 i transmit data, ports 0-7. in 100 mbps and 10 mbps mode, data is transferred across these two lines t3, t2 txd1_1, txd1_0 r1, r2 txd2_1, txd2_0 m3, m2 txd3_1, txd3_0 j2, j3 txd4_1, txd4_0 e1, f3 txd5_1, txd5_0 e2, e3 txd6_1, txd6_0 a2, b3 txd7_1, txd7_0 1. refer to table 1 on page 11 for signal type definitions.
low-power octal phy ? lxt9784 datasheet 27 w3 txen0 i transmit enable, ports 0-7. the transmit enable signal indicates to the lxt9784 that valid data is present on the txd[1:0] pins of the appropriate port. t1 txen1 r3 txen2 m1 txen3 h1 txen4 f2 txen5 d1 txen6 b2 txen7 l1 txd4 i fifth transmit data bit. when the lxt9784 is in a 4b5b by-pass mode, the txd4 pin is used as the fifth transmit data bit of all eight ports. this signal allows for limited symbol interface functionality. table 9. smii mode signal descriptions ball id signal name type 1 signal description v3 rxd0 o receive data and control, ports 0-7. receive data stream, that contains all of the information found on the receive path of the standard mii. u1 rxd1 p3 rxd2 n1 rxd3 g1 rxd4 g2 rxd5 c1 rxd6 c2 rxd7 w2 txd0 i transmit data and control, ports 0-7. transmit data stream, that contains all of the information found on the transmit path of the standard mii. t2 txd1 r2 txd2 m2 txd3 j3 txd4 f3 txd5 e3 txd6 b3 txd7 l1 sync i synchronization. defines the smii segment boundaries. 1. refer to table 1 on page 11 for signal type definitions. table 8. rmii mode signal descriptions (continued) ball id signal name type 1 signal description 1. refer to table 1 on page 11 for signal type definitions.
lxt9784 ? low-power octal phy 28 datasheet table 10. unused pins ball id symbol type description a1,a3,a4,a7,a14,a17,a18,a,19,a20, b4,b5,b6,b7,b8,b9,b12,b13,b14,b15, b16,b17,c4,c7,c14,c17,d4,d7,d14, d17,f5,f6,f14,f15,f16,g6,j18,j19,j20, p15,r5,r6,r7,r15,r16,u4,u7,u14,u17,v4, v7, v14, v17,v18,v19,v20,w4,w5,w6, w7,w8,w9,w12,w13,w14,w15,w16, w17,w18,w19,w20,y1,y2,y3,y4,y7, y14,y17,y18,y19,y20. nc rmii mode no connection- these pins are not used in rmii mode and should not be connected. a1,a2,a3,a4,a7,a14,a17,a18,a,19, a20,b1,b2,b4,b5,b6,b7,b8,b9,b12,b13, b14,b15,b16,b17,c3,c4,c7,c14,c17, d1,d2,d3,d4,d7,d14,d17,e1,e2,f1,f2, f5,f6,f14,f15,f16,g3,g6,j2,j18,j19,j20,l18,m1,m 3,n2,n3,n18,n19,n20,p1,p2, p15,r1,r3,r5,r6,r7,r15,r16,t1,t3,u2,u4,u7,u14, u17,v1,v2,v4,v7, v14, v17,v18,v19,v20,w1,w3,w4,w5,w6,w7, w8, w9,w12,w13,w14,w15,w16, w17,w18,w19,w20,y1,y2,y3,y4,y7, y14,y17,y18,y19,y20. nc smii mode no connection- these pins are not used in smii mode and should not be connected.
low-power octal phy ? lxt9784 datasheet 29 2.0 functional description 2.1 introduction the lxt9784 is a single chip transceiver device containing eight independent 10/100 ethernet transceivers with rmii and/or smii interfaces. the lxt9784 supports per-port speed auto- configuration. each of the eight phys represents a highly-integrated, physical-layer interface solution designed for 10mbps and/or 100 mbps ethernet systems based on the ieee 802.3 standard 10base-t and 100base-tx specifications. 100base-tx is an ieee 802.3 standard physical layer specification for use over two pairs of category 5 unshielded twisted-pair (utp cat 5) or type 1 shielded twisted pair (stp type 1) cable. 100base-tx defines a signaling scheme not only for 100 mbps, but also provides csma/ cd compatibility with the 10mbps ieee 802.3 standard 10base-t signaling standard. each phy of the lxt9784 complies with the ieee 802.3u auto-negotiation section, and with the ieee 802.3x full- duplex flow control section. the interface to each phy complies with the current rmii and smii specifications. the lxt9784 phys incorporate all active circuitry required to interface 10/100 mbps ethernet controllers and csma/cd mac components to 100base-tx and 10base-t networks. each phy supports a direct glue less interface to all standard rmii or smii components. figure 4 shows how the lxt9784 phy fits into a typical 10/100 mbps ethernet switch design. 2.2 lxt9784 configuration the lxt9784 has a common management data interface (mdi) for the eight phys. this is a serial interface and complies with the ieee 802.3standard mii for mdc and mdio signals. in all modes of operation the phys can be configured individually using the mii management interface. figure 4. lxt9784 phy in a 10/100 mbps ethernet solution controller or mac rmii / smii system bus interface rmii or smii magnetics tx d rx d lxt9784 1 of 8
lxt9784 ? low-power octal phy 30 datasheet the phys can individually auto-negotiate with their link partners, and thereby auto-configure their speeds of operation. the mdi/mdix auto-switching configuration is done prior to auto- negotiation. the rmii or smii mode is selected by mode select balls mode<2:0>. three balls select the general operation of the device. table 11 shows the balls settings for the different modes of operation. 2.3 100base-tx mode 2.3.1 100base-tx receiver each receive subsection of the lxt9784 phys accepts 100base-tx mlt-3 data on tpip n and tpin n (where ? n ? is the port number). due to the advanced digital signal processing design techniques employed, the phys accurately receive valid data from cat5 utp and type 1 stp cable over distances well in excess of 100 meters. 2.3.1.1 digital adaptive equalizer the distorted mlt-3 signal at the end of the wire is restored by the equalizer. the equalizer filter coefficients are digitally adapted based on the shape of the received signal, equalizing the signal to exceed ieee specification bit error rate (ber) performance for transmission over 100 meters of cat 5 twisted pair. 2.3.1.2 receive clock and data recovery the clock recovery circuit uses advanced dsp technology to compensate for signal distortion and jitter. the circuitry recovers the 125 mhz clock and data from the equalizer output and presents the data to the nrzi-to-nrz converter. table 11. lxt9784 modes of operation mode pins mii mode mclk frequency 2 1 10 0 0 0 reserved 0 0 1 rmll 50 mhz 0 1 0 smii 125 mhz 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 111 manufacturing test mode 1. mode 2 pin must be set to zero for normal operation.
low-power octal phy ? lxt9784 datasheet 31 2.3.1.3 baseline wander correction the baseline wander effect is the wandering of the dc offset of the receive signal. the wander of the dc offset happens when the 100base-tx data is not dc-balanced. baseline wander can greatly reduce ber performance. the lxt9784 equalizer has an automatic baseline wander correction circuit, thereby preserving outstanding ber performance in case of extreme baseline wander conditions. 2.3.1.4 decoder the lxt9784 phys first convert the data from the clock recovery circuitry to nrz format. the nrz serial data stream is assembled to 5-bit symbols, de-scrambled and aligned to symbol boundaries. the de-scrambling is based on synchronization to the transmitted idle pattern generated by an 11-bit lfsr during idle. the data is then decoded at the 5b/4b decoder. 2.3.1.5 100base-tx receive framing the lxt9784 phys do not differentiate between the fields of the mac frame containing preamble, sfd, data and crc. during 100 mbps reception, the phy detects start-of-stream delimiter (ssd) (/j/k/) and end-of-stream delimiter esd) (/t/r/) pairs. the phy strips those symbols from the data stream before passing the packet to the mac. crsdv n is asserted on a detection of a non-idle symbol. 2.3.1.6 100base-tx rmii data reception when the receive medium is idle, crsdv n is de-asserted and the data on rxd n_ <1:0> is ? 00 ? . when carrier is detected, crsdv n signal asserts asynchronously. after the internal fifo is half full, the phy transfers two bits of recovered data on rxd n_ <1:0> at each clock period, synchronous to mclk. if the phy has additional bits to present on rxd n_ <1:0> (accumulated in the fifo) after crsdv n initial de-assertion, then crsdv n toggles at 25 mhz, starting on a nibble boundary. see figure 5 if false carrier is detected (bad ssd), then rxd n_ <1:0> will be ? 10 ? until the end of the receive event. see figure 6 . 2.3.1.7 100base-tx smii data reception the data is signaled in ten-bit segments, where each segment represents a new byte of data. each segment is delimited by a sync pulse (every 10 clocks). rxd_[7:0] in the serial bit stream are used to convey packet data, receive error status from the previous frame, and phy status, decoded by two smii control bits (crs and rx_dv). see table 12 for bit definitions. figure 7 shows the smii receive data stream. when the receive medium is busy receiving a frame, smii control bit crs is asserted. rx_er (inter-frame status bit rxd0) is asserted if during a frame reception the internal fifo overflows or underflows. if false carrier is detected (bad start-of-stream delimiter), then inter-frame status bit rxd6 is asserted.
lxt9784 ? low-power octal phy 32 datasheet 2.3.1.8 100base-tx receive error detection and reporting in 100base-tx mode, the phys detect errors in the receive data in a number of ways. any of the following conditions is considered an error: if the ssd ("jk") symbol is not fully detected after idle if an invalid symbol is detected at the 4b/5b decoder if idle is detected in the middle of a frame (before "tr" symbol pair are detected) when any of the above error conditions occurs, the phy immediately indicates a receive error for reception. in rmii mode the phy asserts rxer n , and in smii mode the phy asserts the rxd_0 status bit. figure 5. rmii data reception figure 6. false carrier detect table 12. smii rxd_[7:0] contents crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 xo receive error status, from previous frame speed 0 = 10mbps 1=100mbps duplex 0=down 1 = up link 0=down 1 = up jabber 0 =ok 1=error upper nibble 0 = invalid 1 = valid false carrier detect 1 x 1 one data byte (two mii data nibbles) crsdv_n mclk rxd1_n preamble sfd data ? ? rxd0_n 0 0 0 0 0 0 0 0 1 x x x x x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 x x x x x 0 0 0 0 0 ? ? ? ? crsdv_n mclk rxd1_n false carrier detected ? ? rxd0_n 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ?
low-power octal phy ? lxt9784 datasheet 33 2.3.2 100base-tx transmitter the transmit subsection of the lxt9784 phy device accepts di-bit data on txd n_ [1:0] (rmii interface) or serial stream data on txd n (smii interface) while txen n is asserted (high). the data is assembled into nibbles and passed to the 4b/5b encoder as long as txen n is active. the 4b/5b encoder compiles the data into 5-bit-wide parallel symbols. these symbols are scrambled and serialized into a 125 mbps bit stream, converted by the analog transmit driver into an mlt-3 waveform format, and transmitted onto the unshielded twisted pair (utp) or type 1 shielded twisted pair (stp) wire. 2.3.2.1 100base-tx 4b/5b encoder the 4b/5b encoder complies with the ieee 802.3u 100base-tx standard. four bits at a time are accepted and encoded according to the tx 4b/5b look-up table. the lookup table matches a 5-bit code to each 4-bit code. refer to table 12. 2.3.2.2 100base-tx scrambler and mlt-3 encoder data is scrambled in 100base-tx to reduce electromagnetic emissions during long transmissions of high-frequency data codes. the scrambler logic accepts 5 bits from the 4b/5b encoder block, then presents scrambled data to the mlt-3 encoder. the lxt9784 phys implement the 11-bit stream cipher scrambler as adopted by the ansi xt3t9.5 committee for unshielded twisted-pair operation. the cipher equation used is: x[n] = x[n-11] + x[n-9] (mod 2). the encoder receives the scrambled nrz data stream from the scrambler and encodes the stream into mlt-3 for presentation to the driver. mlt3 is similar to nrzi coding, but three levels are output instead of two. there are three output levels +, 0 and -. when an nrz ? 0 ? arrives at the input of the encoder, the last output level is maintained unchanged (either +, 0 or -) when an nrz ? 1 ? arrives at the input of the encoder, the output steps to the next level. the order of steps is ? - ,0,+,0,-,0... ? see figure 8 . figure 7. smii received serial data stream sync mclk receive stream direction rxd_n crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7
lxt9784 ? low-power octal phy 34 datasheet figure 8. nrz to mlt-3 encoding diagram table 13. 4b/5b coding code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 0 0 0 0 0 1 1 1 1 0 data 0 0 0 0 1 1 0 1 0 0 1 data 1 0 0 1 0 2 1 0 1 0 0 data 2 0 0 1 1 3 1 0 1 0 1 data 3 0 1 0 0 4 0 1 0 1 0 data 4 0 1 0 1 5 0 1 0 1 1 data 5 0 1 1 0 6 0 1 1 1 0 data 6 data 0 1 1 1 7 0 1 1 1 1 data 7 1 0 0 0 8 1 0 0 1 0 data 8 1 0 0 1 9 1 0 0 1 1 data 9 1 0 1 0 a 1 0 1 1 0 data a 1 0 1 1 b 1 0 1 1 1 data b 1 1 0 0 c 1 1 0 1 0 data c 1 1 0 1 d 1 1 0 1 1 data d 1 1 1 0 e 1 1 1 0 0 data e 1 1 1 1 f 1 1 1 0 1 data f idle undefined i 1 1 1 1 11 idle. used as inter-stream fill code 0 1 0 1 j 2 1 1 0 0 0 start-of-stream delimiter (ssd), part 1 of 2 control 0 1 0 1 k 2 1 0 0 0 1 start-of-stream delimiter (ssd), part 2 of 2 undefined t 3 0 1 1 0 1 end-of-stream delimiter (esd), part 1 of 2 undefined r 3 0 0 1 1 1 end-of-stream delimiter (esd), part 2 of 2 undefined h 4 0 0 1 0 0 transmit error. used to force signaling errors undefined invalid 0 0 0 0 0 invalid 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs; /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs; /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition. clock nrz nrzi 11001001 1 10 01 0 01 mlt-3 1 1 0 0 1 0 0 1
low-power octal phy ? lxt9784 datasheet 35 2.3.2.3 transmit driver the tpop n and tpon n lines are implemented with a highly slope-controlled driver that meets the tp-pmd specifications. the driver either sinks, floats, or drives the tpop n and tpon n outputs with 20 ma of current, depending on whether the ternary signal is -1, 0, or +1. the magnetics external to the lxt9784 converts this current to voltage levels of 2.0 vptp, as required by the tp- pmd specification. there are four inputs (rbias10_0, rbias10_1, and rbias100_0, rbias100_1) to the lxt9784 that must have external resistor connections to set up voltage biases for the internal analog section of the lxt9784 phys. rbias10_0 and rbias100_0 provide the bias for phys 0 through 3. rbias10_1 and rbias100_1 provide the bias for phys 4 through 7. 2.3.2.4 100base-tx transmit framing the lxt9784 phys do not differentiate between the fields of the mac frame containing preamble, sfd, data and crc. when txen n is asserted, the phy accepts di-bit data on the rmii txd n_ [1:0] lines, or serial stream data on the smii txd n line. the phy encodes the data, and sends it out onto the wire. the phy substitutes the first byte of the preamble with the "jk" symbol pair, encodes all other pieces of data according to the 4b/5b lookup table, and adds the "tr" code after the end of the packet (de-assertion of txen n transmit enable indication). the phy scrambles and serializes the data into a 125 mbps stream, encodes it as mlt-3, and drives it onto the wire. if txer bit in the smii control word is asserted while txen n bit is active, the lxt9784 transmits an invalid "h" symbol. 100base-tx rmii data transmission when txen n is de-asserted, the data on txd n_ [1:0] shall be "00" to indicate idle. when txen n asserts, the phy accepts di-bit data on the txd n_ [1:0] lines. see figure 9 . undefined invalid 0 0 0 0 1 invalid undefined invalid 0 0 0 1 0 invalid invalid undefined invalid 0 0 0 1 1 invalid undefined invalid 0 0 1 0 1 invalid undefined invalid 0 1 0 0 0 invalid undefined invalid 0 1 1 0 0 invalid undefined invalid 0 1 1 0 0 invalid undefined invalid 1 0 0 0 0 invalid undefined invalid 1 1 0 0 1 invalid table 13. 4b/5b coding (continued) code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs; /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs; /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition.
lxt9784 ? low-power octal phy 36 datasheet 100base-tx smii data transmission the data is signaled in ten-bit segments, where each segment represents a new byte of data. each segment is delimited by a sync pulse (every 10 clocks). when tx_en in the serial bit stream is de-asserted, then txd[7:0] are the inter-frame control bits (for a direct mac to mac connection). when the tx_en bit asserts, the phy accepts the data stream on the txd n line. figure 10 shows the format of the smii transmit serial stream. 2.4 10base-t mode 2.4.1 10base-t receiver 2.4.1.1 10base-t manchester decoder the lxt9784 phys perform manchester decoding and timing recovery when in 10base-t mode. the manchester-encoded data stream is decoded from tpip n and tpin n to separate receive clock and receive data signals from the differential signal. this data is assembled to nibbles and transferred to the rmii/smii. 10base-t rmii data reception rmii data is transferred in di-bits at a 50 mhz rate. therefore the data on rxd n_ <1:0> is changed every 10 clock cycles. figure 9. rmii data transmission txen n txd n _0 mclk txd n _1 preamble 0 0 0 0 0 0 0 0 1 x x x x x 0 ? 0 1 1 1 1 1 1 1 1 x x x x x 0 ? sfd data ? ? ? ? figure 10. smii transmit data serial stream sync mclk transmit stream direction txd n tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7
low-power octal phy ? lxt9784 datasheet 37 10base-t smii data reception smii data is signaled in ten-bit segments. each segment is delimited by a sync pulse (every 10 clocks). in 10base-t mode, the data rate is one-tenth the 100 mbps rate, therefore each segment is repeated ten times so that every 10 segments represent a new byte of data. 2.4.1.2 10base-t receive buffer and filter in 10 mbps mode, data is received on tpip n and tpin n , after passing through isolation transformers. the filters implemented inside each lxt9784 phy for 10base-t operation are tuned for supporting a single magnetics that are shared with the 100base-tx side. the receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10base-t standard. the filters are responsible for noise immunity, data acceptance and rejection conditions. the filter rejects the differential pulses listed next. these rejectable single-cycle sine waves are discarded only if they are preceded by 4-bit times (400 ns) of silence. all other activity is determined to be either data, link test pulses, auto-negotiation fast link pulses, or the idle condition of peak magnitude less than 300 mv. differential pulses with a peak magnitude of less than 300 mv. continuous sinusoids with a differential amplitude less than 6.2 v peak to peak and frequency less than 2 mhz. sine waves of a single cycle duration, starting with phase 0 or 180, that have a differential amplitude less than 6.2 v peak to peak and a frequency of at least 2 mhz and not more than 16 mhz. 2.4.1.3 10base-t error detection and reporting in 10base-t mode, the lxt9784 can detect errors in the receive data. as error is defined only in cases that tp-idle is not detected at the end of the frame (200 ns without mid-bit transitions). 2.4.1.4 10base-t link integrity the link integrity in 10 mbps works with link pulses. each lxt9784 phy senses and differentiates those link pulses from fast link pulses and from 100base-tx idles. for link pulse and for 100base-tx idles, the phy uses parallel detection of the respective technology. for fast link pulses, the phy uses auto-negotiation. the 10base-t link pulses or nlps are driven on the tpo n line. the link beat pulse is also used to determine if the receive pair polarity is reversed. if reversed the polarity is corrected internally. 2.4.1.5 10base-t jabber control function each lxt9784 phy contains a jabber control function that when enabled, inhibits transmission after a specified time window. the jabber timer is set to a value between 26.2 and 39 ms. when the phy detects continuous transmission for longer than this time, it prevents further transmissions from going out in the wire until it detects that the mac txen n signal (in rmii mode) or the tx_en signal (in smii mode) has been inactive for at least 314 ms.
lxt9784 ? low-power octal phy 38 datasheet 2.4.1.6 10base-t full duplex the lxt9784 phys support 10 mbps full duplex by disabling the collision and the carrier sense functions. this allows each lxt9784 phy to transmit and receive simultaneously, achieving up to 20 mbps of network bandwidth. the configuration is done through auto-negotiation. 2.4.2 10base-t transmit 2.4.2.1 10base-t manchester encoder when txen n is asserted, the phy accepts di-bit data on the rmii txd n_ [1:0] lines, or serial stream data on the smii txd n line. after the clocked data is serialized into a 10 mbps serial stream, the 20 mhz clock performs the manchester encoding. the manchester code always has a mid-bit transition. if the data to be transmitted is "1", then the transition is from low to high. if the value is "0" then the transition is from high to low. the boundary transition (such as between cell times) occurs only when the data changes from bit to bit: if "10" then the change is from high to low; if "01" then the change is from low to high. 10base-t rmii data transmission the data is transferred in di-bits at a 50 mhz rate. therefore the data on txd n_ [1:0] is valid for 10 clock cycles for each di-bits. 10base-t smii data transmission the data is signaled in ten-bit segments. each segment is delimited by a sync pulse (every 10 clocks). in 10m mode, the data rate is one-tenth the 100m rate, therefore each segment is repeated ten times so that every 10 segments represent a new byte of data. 2.4.2.2 10base-t driver and filter since 10base-t and 100base-tx have different filtration needs, both filters are implemented inside the chip. this allows the two technologies to share the same magnetics. the lxt9784 supports both technologies through one pair of tpop n and tpon n pins and by externally sharing the same magnetics. in 10 mbps mode, the lxt9784 phys begin transmitting the serial manchester bit stream within 3 bit times (300 ns) after the assertion txen n . in 10-mbps mode the line drivers use a pre-distortion algorithm to improve jitter tolerance. the line drivers reduce their drive level during the second half of ? wide ? (100 ns) manchester pulses and maintain a full drive level during all narrow (50 ns) pulses and the first half of the wide pulses. the lxt9784 ? s advanced wave-shaping circuitry prevents overcharging during wide pulses, a major source of jitter. 2.5 mdi/mdi-x function when connecting ethernet devices together, there are two types of cables in use: straight-through and crossed-over cables. in a typical connection, dte to switch, cross-over is implemented in the switch mau. in this case a straight-through cable is required. however, in case that a connection is required between two maus of the same type, then an external cross-over cable is required. in
low-power octal phy ? lxt9784 datasheet 39 cases that the cable type does not match the two ends maus configurations, replacement of the cable is required. with the mdi/mdi-x feature enabled, switching is performed automatically by the lxt9784, to adjust the mau to the cable type. this advanced feature enables auto-correction of a specific wiring problem of incorrect cabling with respect to crossed-over versus straight-through cables. the lxt9784 phy can identify the cable connection type and adjust its mdi port to the cable by switching between the tpo and tpi pairs. the auto switching is done prior to the auto-negotiation algorithm. table 14 shows the standard dte straight-through rj-45 port configuration, with the transmit pair on contacts 1 and 2, and the receive pair on contacts 3 and 6. table 15 shows the mau configuration of a crossed-over rj-45 port. 2.5.1 mdi/mdi-x auto switching activation the external mdi-x input, sampled during reset, enables or disables auto-switching. when this input is externally pulled up, or left unconnected, auto-switching is enabled. when mdi-x is externally pulled down, auto switching is disabled. in the case that auto-switching was disabled during reset, after reset the mdi-x pin is used to configure the connection type (straight-through or crossed-over). a ? 1 ? forces a crossed-over connection, a ? 0 ? forces a straight-through connection. 2.5.2 mdi/mdi-x algorithm in the case that auto-switching was enabled during reset, the phy attempts to detect link activity in a given configuration (mdi or mdi-x) for a duration of 80 - 100 ms. if no link activity is detected during this slot time, the phy waits a random amount of time greater then 80 ms, and switches the mdi pairs to the other configuration. table 14. straight-through pin assignments contact mdi signal 1tdp _n 2tdn _n 3rdp _n 4 not used 5 not used 6rdn _n 7 not used 8 not used table 15. crossed-over pin assignments contact mdi signal 1 rdp _n 2 rdn _n 3tdp _n 4 not used
lxt9784 ? low-power octal phy 40 datasheet 2.6 hardware control interface the lxt9784 can be configured for unmanaged applications, using external pins (hardware control) as described in the following paragraphs. 2.6.1 mdi-x (mdi crossover) during reset, enables the auto-switch feature. if this feature was disabled, then after reset the mdi-x pin controls the manual mdi/mdi-x switching. when mdi-x = 1, the mdi port is forced to mdi-x (cross- over mode). when mdi-x = 0, the mdi port is forced to mdi (straight-through mode). 2.6.2 frclnk (force link) during reset: when frclnk = 1, it forces good link (phy reg17, bit 11), link integrity (phy reg17, bit 1), and disables auto-negotiation (phy reg0, bit 12) when frclnk = 0, normal operation. if frclnk was set, then after reset the frclnk pin will control speed selection (phy reg0, bit 13), where: when frclnk = 1, it forces 100 mbps. when frclnk = 0, it forces 10 mbps. the frclnk pin and bit 11 in phy register 11 ? h are ored together. 2.6.3 frc34 (force 34 transmit pattern) the frc34 pin and bit 12 in phy register 11 ? h are ored together. 2.6.4 bp4b5b (4b/5b bypass) to enter 4b/5b bypass mode, this pin must be set high after the end of reset. during reset, this pin must be pulled down to ensure proper operation of the lxt9784. 5 not used 6tdn _n 7 not used 8 not used table 15. crossed-over pin assignments contact mdi signal
low-power octal phy ? lxt9784 datasheet 41 the bp4b5b pin and bit 14 in phy register 11 ? h are ored together. this pin bypasses the 4b5b encoder/decoder in the transmit and receive sections. in 4b5b bypass mode the data is transmitted in 5-bit symbols. in rmii mode, the fifth bit (msb) of all eight ports is driven through the txd4 pin. the txd4 pin is a static pin and should be pulled up or pulled down. in smii mode, txer represents the fifth bit. 2.6.5 scrmbp (scrambler bypass) in order to enter scrambler by-pass this pin must be set high after the end of reset. during reset this pin must be pulled-down to ensure proper operation of the lxt9784. the scrmbp pin and bit 15 in phy register 11'h are ored together. 2.7 phy addresses the id<1:0> pins are used to set the phy addresses for the mii management interface. the phys are assigned consecutive addresses in increasing order, starting with phy0. the address of phy0 is determined by the setting of id<1:0>. this allows up to four lxt9784s to be connected on a single mii management bus. up to thirty-two ports are available when using all the combinations of id<1:0>. table 16 shows the internal phy addresses for each of the possible combinations of id<1:0>. 2.8 link status interrupt the lxt9784 provides an open-drain interrupt pin (int ), which is driven low by the lxt9784 when one or more of it ? s internal phys has a change in link status. figure 11 is a simplified diagram of the interrupt structure. when int is driven low, all of the phy interrupt registers should be read, to determine which port or ports caused the interrupt (refer to table 51). once a phy interrupt bit has been read, it is self- cleared. the interrupt line becomes inactive only after reading the link status interrupt bits of all the phys that caused the interrupt. in the case of more than one phy having an interrupt pending, int remains asserted until after reading the last phy with a link status interrupt bit set to ? 1 ? . if during the procedure of reading the interrupt registers a new change of link status occurred on a phy which has already been accessed, the interrupt line remains asserted after completing the read procedure. this feature can be used instead of polling the phys for link status change. table 16. phy addresses id_1 id_0 phy0 phy1 phy2 phy3 phy4 phy5 phy6 phy7 0 0 00000 00001 00010 00011 00100 00101 00110 00111 0 1 01000 01001 01010 01011 01100 01101 01110 0 1111 1 0 10000 10001 10010 10011 10100 10101 10110 10111 1 1 11000 11001 11010 11011 11100 11101 11110 11111
lxt9784 ? low-power octal phy 42 datasheet 2.9 reset when the lxt9784 reset signal is asserted (active high) all internal circuits are reset. the phy can also be reset individually via the phy register reset bit (register 0 ? h bit 15). device clock should be stable and running prior to hw reset. reset must be asserted for a minimum of 500 s for proper operation after de-assertion. 2.10 led operation the lxt9784 has three pins per port dedicated to driving the leds. these drivers can indicate link/activity, speed, and collision. the drivers also indicate that the phy port was disabled by management. the activity led in this mode is triggered by both transmit and receive activities. all three drivers are active low. the algorithm for computing media utilization is an average of the activity on the media over the time of 8 maximum length packets, with minimum ipg spacing. the utilization is averaged over: (8 packets * 1518 bytes * 8 bytes/bit * bit time) + (8 ipg * 96 bits * bit time) the percent utilization is indicated by a specific frequency on the led n _a (as shown in table 17) for a period of 600 ms (led refresh rate), based on the activity of the prior 600 ms period. in case the port is disabled, register 0.10 = 1, drivers led n _a and led n _b blink in unison, at a rate of 1 hz, 500 ms on and 500 ms off. eliminate the indication of phy port disable by setting the phy register 1b ? h, bit 4. there is full controllability on all drivers through phy register 1b ? h, bits [2:0]. the led n _b state is frozen when a link is lost and is changed only after the link is re-established. figure 11. simplified interrupt structure port 0 status changed = 1 port interrupt enable from register 12 ? h . . . int_l port 1 status changed = 1 port interrupt enable from register 12 ? h port 7 status changed = 1 port interrupt enable from register 12 ? h phy register 12 ? h bit 0 read phy register 12 ? h bit 0 read
low-power octal phy ? lxt9784 datasheet 43 during reset, all led drivers are active for approximately 2 seconds, then turned off. 2.11 mii management interface operation the lxt9784 provides phy status and accepts phy management information via the mii management interface. this is accomplished via read and write operations to various registers according to the ieee802.3u standard. a read or write of a particular register is called a management frame, which is sent serially over the mdio pin synchronous to mdc at a maximum rate of 3 mhz. read and write cycles are from the perspective of the controller. therefore, the controller would always drive the start, opcode, phy address and register address on to the mdio pin. for a write, the controller would also drive the transition bits and data. for a read, the lxt9784 drives the transition bits and data onto the mdio pin. the controller should drive address and data on the falling edge of mdc and the lxt9784 latches that data on the rising edge of mdc. the phy addresses in the lxt9784 can be configured from 0-31. the management frame structure is shown in table 19 . this structure allows a controller or other management hardware, to query a phy for status of the link, auto-negotiation registers, or configure the phy to one of many modes. table 20 defines the protocol terms. when mdio and mdc are not in use, they should be connected to pull-up devices. table 17. led functionality led driver function description led n _a link solid /activity blink with a good link the output is low, the output toggles at a rate related to the utilization. refer to table 18 for the actual numbers. led n _b speed the output is low for 100 mbps, high for 10 mbps led n _c collision the output blinks low with collisions stretch rate of 10 ms. 1. n indicates port number. table 18. activity led blink rates percent utilization blink rate 1 frequency 0-5% slow 3 hz 5-30% medium 5 hz +30% fast 7 hz 1. note: duty cycle = 50% table 19. mii management frame format function preamble start frame opcode phy adr reg adr turnaround data idle read 1...1 10 10 aaaaa rrrrr z0 d[15:0] z write 1...1 01 01 aaaaa rrrrr 10 d[15:0] z
lxt9784 ? low-power octal phy 44 datasheet 2.12 test port operation the lxt9784 can be set to one of two manufacturing testing modes, depending on ti, texec, and tck input pins combination, as shown in table 20. the mode[2:0] pins are used to enable the manufacturing testing modes, and should be set to "111". the test mode can be used only for manufacturing testing. 2.12.1 nand-tree test this command connects all the outputs of the input-buffers in the device periphery into a nand- tree scheme. all the i/o and outputs, except for mode[2:0], ti, texec, tck, int, and tout pins, are put into a tri-state mode. table 20. glossary of protocol terms term definition preamble sequence of 32 contiguous logic one bits on the mdio pin at the beginning of each transaction with corresponding cycles on the mdc clock pin for synchronization of the phy. start a start of frame pattern of ? 01 ? opcode an operation code which can assume one of two values: 10 read instruction. 01 write instruction. phy adr 5-bit address of the phy device with msb transmitted first, which provides support for 32 unique phy addresses. reg adr 5-bit address of the specific register within the phy device with msb transmitted first. this provides support for 32 unique registers. turnaround a two-bit turnaround time during which no device actively drives the mdio signal on a read cycle. during a read transaction the phy should not drive mdio in the first bit time and the drive a zero in the second bit time. during a write transaction a "10" pattern is driven to phy. data 16 bits of data driven by the phy on read transaction, and will be driven to phy on write transaction. in either case, the msb is transmitted first. idle the idle condition on mdio is a high impedance state. the mdio driver is disabled and the phy should pull-up the mdio line to logic one. table 21. test mode configuration mode select pins 1 test enable pins mode comments 210tcktitexec 0 0 1 x x x rmii normal system mode 01 0xxx smii 1 1 1 0 0 1 nand tree (+ hi z) manufacturing test mode 1 1 1 0 1 0 xnor tree (+ hi z) 1. note: all other combinations are ? reserved ? and should not be used.
low-power octal phy ? lxt9784 datasheet 45 there are two nand-tree chains, with two separate inputs, assigned to uca1 (chain 1) and coled (chain 2), and two separate outputs, assigned to int (chain 1) and tout (chain 2) respectively. to enable nand-tree manufacturing test mode, set mode[2:0] = "111", tck = "0", ti = "0", texec = "1" and power-up or reset the chip. toggling the chain input pin will be reflected at the chain output after a delay of about 20ns. 2.12.2 xnor-tree test this command connects all the outputs of the input-buffers in the device periphery into a xnor- tree scheme. all the i/o and outputs, except for mode[2:0], ti, texec, tck, int, and tout pins, are put into a tri-state mode. there are two xnor-tree chains, with two separate inputs, assigned to uca1 (chain 1) and coled (chain 2), and two separate outputs, assigned to int (chain 1) and tout (chain 2), respectively. in order to set up the device into xnor tree manufacturing test mode set mode[2:0] = "111", tck = "0", ti = "1", texec = "0" and power-up or reset the chip. toggling the chain input pin will be reflected at the chain output after a delay of about 20 ns. 2.12.3 nand/xnor tree chain order a combination of ? 111 ? on the mode_[2:0] pins indicates that the lxt9784 is configured to an asynchronous test mode (nand-tree or xnor-tree). test pins combinations for the asynchronous test modes are: mode_[2:0] = ? 111 ? , tck = ? 0 ? , ti= ? 0 ? , texec = ? 1 ? for nand - tree mode_[2:0] = ? 111 ? , tck = ? 0 ? , ti= ? 1 ? , texec = ? 0 ? for xnor - tree the nand-tree / xnor-tree commands connect all outputs of the input-buffers in the device periphery into a nand-tree / xnor-tree scheme. all the input/output pins and output pins except for: mode_[2.0], ti, texec, tck, int#, and tout pins are put into a tri-state mode. there are two nand-tree / xnor-tree chains, with two separate outputs, assigned to int# (chain 1) and tout (chain 2). the following table lists the chains order / direction (pin no. 1 in the chain, is the farthest from the nand-tree / xnor-tree outputs).] table 22. test scan chain chain order ball id chain #1 ball id chain #2 1 w1 txd0_1 w18 nc 2 w2 txd0_1 w19 nc 3w3txen0w20nc 4 v1 crsdv0 v18 nc 5 v2 rxd0_1 v19 nc
lxt9784 ? low-power octal phy 46 datasheet 6 v3 rxd0_0 v20 nc 7 u1 rxd1_0 u18 led0-c# 8 u2 rxd1_1 u19 led0_b# 9 u3 crsdv1 u20 led0_a# 10 t1 txen1 t18 led1_c# 11 t2 txd1_0 t19 led1_b# 12 t3 txd1_1 t20 led1_a# 13 r1 txd2_1 r18 led2_c# 14 r2 txd2_0 r19 led2_b# 15 r3 txen2 r20 led2_a# 16 p1 crsdv2 p18 led3_c# 17 p2 rxd2_1 p19 led3_b# 18 p3 rxd2_0 p20 rxer7 19 n1 rxd3_0 n18 rxer6 20 n2 rxd3_1 n19 rxer5 21 n3 crsdv3 n20 rxer4 22 m1 txen3 m18 rxer3 23 m2 txd3_0 m19 rxer2 24 m3 txd3_1 m20 rxer1 25 l1 txd4 l18 rxer0 26 l3 frc34 l19 id_1 27 k3 mclk l20 id_0 28 k1 frclnk k18 reset 29 j2 txd4_1 k19 bp4b5b 30 j3 txd4_0 k20 scrmbp 31 h1 txen4 j18 nc 32 h2 crsdv4 j19 nc 33 h3 rxd4_1 j20 nc 34 g1 rxd4_0 g18 mdix 35 g2 rxd5_0 g19 led3_a# 36 g3 rxd5_1 g20 led4_c# 37 f1 crsdv5 f18 led4_b# 38 f2 txen5 f19 led4_a# 39 f3 txd5_0 f20 led5_c# 40 e1 txd5_1 e18 led5_b# 41 e2 txd6_1 e19 led5_a# 42 e3 txd6_0 e20 led6_c# 43 d1 txen6 d18 led6_b# table 22. test scan chain (continued) chain order ball id chain #1 ball id chain #2
low-power octal phy ? lxt9784 datasheet 47 44 d2 crsdv6 d19 led6_a# 45 d3 rxd6_1 d20 led7_c# 46 c1 rxd6_0 c18 led7_b# 47 c2 rxd7_0 c19 led7_a# 48 c3 rxd7_1 c20 mdio 49 b1 crsdv7 b19 mdc 50 b2 txen7 - - 51 b3 txd7_0 - - 52 a2 txd7_1 - - nand-tree / xnor-tree output b18 int# b20 tout table 22. test scan chain (continued) chain order ball id chain #1 ball id chain #2
lxt9784 ? low-power octal phy 48 datasheet 3.0 application information 3.1 magnetics table 23 lists of magnetics modules available from various vendors. all modules listed support both 10m and 100m operation. 3.2 analog references (rbias) the four rbias inputs (rbias10_0, rbias10_1, and rbias100_0, rbias100_1) must have external resistor connections. the inputs are sensitive to the resistor value and some experimentation is required to select the correct values for any given layout. resistors of 1% tolerance are to be used. see figure 12 for a circuit example. 3.3 rmii applications the rmii ports provide eight low pin-count interfaces between the eight phys and an asic switch, as an alternative to the smii interface. the rmii interface is composed of seven signals per port, and a global reference clock. table 23. magnetics module vendor vendor model/type bel fuse 0558-5999-n7 (quad) pulse engineering h1141t (single) h1140t (quad) figure 12. typical rbias circuit 464 1% lxt9784 rbias100_1 rbias10_1 rbias100_0 rbias10_0 619 1% 464 1% 619 1%
low-power octal phy ? lxt9784 datasheet 49 3.3.1 rmii clock in rmii mode of operation, the master input clock (mclk) frequency should be 50 mhz 50 ppm, with a duty-cycle between 35% and 65% inclusive. 3.4 smii applications the smii ports provide eight low pin-count interfaces between the lxt9784 ? s eight phys and an asic switch, as an alternative to the rmii interface. the smii interface is composed of two signals per port, a global synchronization signal, and a global reference clock. figure 13. typical rmii application lxt9784 p0_mdi p1_mdi p2_mdi p3_mdi p4_mdi p5_mdi p6_mdi p7_mdi mdi ports rbias100_0 rbias10_0 analog pins led0_[a:c] led1_[a:c] led2_[a:c] led3_[a:c] led4_[a:c] led5_[a:c] led6_[a:c] led7_[a:c] per port leds mode[2:0] reset mclk configuration mdio mdc mii management interface id[1:0] phy id rmii0_[6:0] rmii1_[6:0] rmii2_[6:0] rmii3_[6:0] rmii4_[6:0] rmii5_[6:0] rmii6_[6:0] rmii7_[6:0] rmii interfaces tpip int interrupt rbias100_1 rbias10_1 scrmbp bp4b5b frclnk mdix frc34 sync tck ti texec tout test port tpin tpop tpon rxd[1:0] txd[1:0] crsdv txen rxer
lxt9784 ? low-power octal phy 50 datasheet data and control bits are transmitted and received serially synchronous to mclk, in ten bit segments delimited by a pulse on sync, on rxd n and txd n respectively. 3.4.1 smii clock in smii mode of operation, the master input clock (mclk) frequency should be 125 mhz, 50ppm, with a duty-cycle between 35% and 65% inclusive. figure 14. typical smii application lxt9784 p0_mdi p1_mdi p2_mdi p3_mdi p4_mdi p5_mdi p6_mdi p7_mdi mdi ports rbias100_0 rbias10_0 analog pins led0_[a:c] led1_[a:c] led2_[a:c] led3_[a:c] led4_[a:c] led5_[a:c] led6_[a:c] led7_[a:c] per port leds mode[2:0] reset mclk configuration mdio mdc mii management interface id[1:0] phy id smii0_[1:0] smii1_[1:0] smii2_[1:0] smii3_[1:0] smii4_[1:0] smii5_[1:0] smii6_[1:0] smii7_[1:0] smii interfaces rxd txd tpip int interrupt rbias100_1 rbias10_1 scrmbp bp4b5b frclnk mdix frc34 sync tck ti texec tout test port tpin tpop tpon
low-power octal phy ? lxt9784 datasheet 51 4.0 test specifications note: table 24 through table 41 and figure 15 through figure 27 represent the performance specifications of the lxt9784 and are guaranteed by test, except where noted, by design. the minimum and maximum values listed in table 26 through table 41 are guaranteed over the recommended operating conditions specified in table 25 . . table 24. absolute maximum ratings parameter minimum maximum units temperature under bias ambient - commercial 0 + 100 o c ambient - extended -40 + 100 o c case - commercial 0 + 120 o c case - extended -40 + 120 o c supply voltage with respect to v ss -0.5 + 3.45 v outputs voltages -0.5 + 3.45 v input voltages -1.0 + 3.45 v caution: exceeding these values may cause permanent damage. caution: functional operation under these conditions is not implied. caution: exposure to maximum rating conditions for extended periods may affect device reliability. table 25. operating conditions parameter symbol min typ 1 max 2 units condition recommended operating temperatures - commercial t opa 0 70 c ambient t opc 0 105 c case recommended operating temperatures - extended t opa - 40 85 c ambient t opc - 40 120 c case recommended supply voltage - commercial v cc 2.85 3.0 / 3.3 3.45 v recommended supply voltage - extended vcc 3.15 3.45 v current consumption i cc - 680 /750 775 ma 100 mbps, rmii mode - 635 / 680 - 10 mbps, rmii mode - 715 / 800 850 100mbs, smii mode - 710 / 760 - 10mbs, smii mode power dissipation p - - 334 mw per port 100mbps rmii mode - - 367 per port 100mbps smii mode 1.0 w auto-negotiation 1. tested at a supply voltage of 3.0v/3.3v. 2. tested at a supply voltage of 3.45v.
lxt9784 ? low-power octal phy 52 datasheet 4.1 dc characteristics table 26. clock dc characteristics parameter symbol min typ max units condition input low voltage (ttl) v il 0.8 v input high voltage (ttl) v ih 2.0 v input leakage currents i ilih 10 a 0< vin< vcc input capacitance c in 8 pf see note 1. 1. characterized, not tested. valid for digital pins only. table 27. rmii/smii and general interface 1 dc characteristics parameter symbol min typ max units condition input low voltage (ttl) v il 0.8 v input high voltage (ttl) v ih 2.0 v output low voltage v ol 0.4 v i out = 4 ma output high voltage v oh 2.4 v i out = -4 ma input leakage current i ilih 10 a 0< vin< vcc input capacitance c in 8 pf note 2. 1. ? general interface ? refers to the following: mii management, configuration and phy id. 2. characterized, not tested. valid for digital pins only. table 28. led dc characteristics parameter symbol min typ max units condition output low voltage v olled 0.7 v i out = 10 ma output high voltage v ohled vcc - 0.7 v i out = -10 ma table 29. 10base-t receiver voltage/current dc characteristics parameter symbol min typ max units condition input differential resistance r id10 10 k ? dc. note 1. input differential accept peak voltage v ida10 585 3100 mv 5 mhz f 10 mhz input differential reject peak voltage v idr10 300 mv 5 mhz f 10 mhz input common mode voltage v icm10 vcc/2 v 1. this value is measured across the receive differential pins, tpip and tpin.
low-power octal phy ? lxt9784 datasheet 53 4.2 ac characteristics figure 15 defines the conditions under which timing measurements are done. the design must guarantee proper operation for voltage swings and slew rates that exceed the specified test conditions. table 30. 10base-t transmitter voltage/current dc characteristics parameter symbol min typ max units condition output differential peak voltage v od10 2.2 2.8 v r l = 100 ? note 1. line driver supply peak current per port i cct10 57 ma r bias10 = 464 ? notes 2 and 3. 1. r l is the resistive load across the transmit differential pins, tpop and tpon. 2. current is measured on all vcc pins @ vcc = 3.3 v. 3. transmitter current is measured with a 1:1 transformer. transmitter peak current is governed by the following equation: maximum differential output peak voltage divided by the load resistance value. table 31. 100base-tx receiver voltage/current dc characteristics parameter symbol min typ max units condition input differential resistance r id100 10 k ? dc. note 1. input differential accept peak voltage v ida100 500 1200 mv input differential reject peak voltage v idr100 100 mv input common mode voltage v icm100 vcc/2 v 1. this value is measured across the receive differential pins, tpip and tpin. table 32. 100base-tx transmitter voltage/current dc characteristics parameter symbol min typ max units condition output differential peak voltage v od100 0.95 1.00 1.05 v r l = 100 ? note 1. line driver supply peak current per port i cct100 20 ma r bias100 = 619 ? notes 2 and 3. 1. r l is the resistive load across the transmit differential pins, tpop and tpon. 2. current is measured on all vcc pins @ vcc = 3.3 v. 3. transmitter current is measured with a 1:1 transformer. transmitter peak current is governed by the following equation: maximum differential output peak voltage divided by the load resistance value.
lxt9784 ? low-power octal phy 54 datasheet 4.2.1 common characteristics figure 15. ac testing level conditions figure 16. mdc clock ac timing table 33. mii management clock specifications parameter symbol min typ max units condition mdc frequency f 03.0mhz mdc clock period t1 300 ns mdc duty cycle t2 35 65 % figure 17. mii management timing parameters: mdc/mdio input levels 1.4v 1.4v t2 t2 t1 mdc t3 mdio (input) mdio (output) t4 t5 data invalid data valid data invalid data invalid data valid data invalid
low-power octal phy ? lxt9784 datasheet 55 table 34. mii management interface timing parameters parameter symbol min typ max units condition mdio setup time to mdc rising edge t3 10 ns mdio hold time from mdc rising edge t4 10 ns mdio valid from mdc rising edge t5 0 200 ns figure 18. normal link pulse timings table 35. 10base-t normal link pulse (nlp) timing parameters parameter symbol min typ max units condition nlp width t6 100 ns 10 mbps nlp period t7 8 16 24 ms 10 mbps figure 19. fast link pulse timings table 36. auto-negotiation fast link pulse (flp) timing parameters parameter symbol min typ max units condition flp width (clock/data) t8 100 ns clock pulse to clock pulse period t9 111 125 139 s clock pulse to data pulse period t10 55.5 62.5 69.5 s normal link pulse t7 t6 fast link pulse t10 t8 t9 clock pulse data pulse clock pulse flp bursts t12 t13
lxt9784 ? low-power octal phy 56 datasheet 4.3 rmii interface number of pulses in one burst t11 17 33 # burst width t12 2 ms flp burst period t13 8 16 24 ms table 37. 100base-tx transmitter ac specifications parameter symbol min typ max units condition tpop/tpon differential output peak jitter t jit 1400 ps hls data figure 20. rmii ac testing level conditions figure 21. rmii rise and fall timings table 36. auto-negotiation fast link pulse (flp) timing parameters parameter symbol min typ max units condition mclk rmii i/o 1.4v 1.4v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v t57 t57
low-power octal phy ? lxt9784 datasheet 57 4.4 smii interface figure 22. rmii timing parameters table 38. rmii interface timing parameters parameter symbol min typ max units condition txd[1:0],txen data setup to mclk rising edge t54 (t rmsu )4 ns txd[1:0],txen data hold to mclk rising edge t55 (t rmhd )2 ns rxd[1:0], rxer,crsdv min valid time t56 (t rmvlm )3 ns rxd[1:0], rxer,crsdv max valid time t56a (t rmvlx )14ns txd[1:0],txen,rxd[1:0], rxer,crsdv rise and fall time t57 (t rmfr )1 5 ns figure 23. smii mode - ac testing level conditions mclk t54 txd[1:0],txen t55 data invalid data valid data invalid t56a previous data valid rxd[1:0],rxer, crsdv input output data invalid t56 data valid mclk smii i/o 1.4v 1.4v 2.0v 0.8v 2.0v 0.8v
lxt9784 ? low-power octal phy 58 datasheet 4.5 reset timing parameters figure 24. smii timing parameters table 39. smii interface timing parameters parameter symbol min typ max units condition txd setup to mclk rising edge t64 (t smsu )1.5 ns txd hold from mclk rising edge t65 (t smhd )1 ns rxd min. valid time t66 (t smvlm )2 ns rxd max. valid time t66a (t smvlx )5ns figure 25. reset timing parameters table 40. reset timing parameters parameter symbol min typ max units condition reset pulse width t58 (t rst_wid ) 500 s power up to falling edge of reset t59 (t pop_rst ) 1000 s mclk t64 t65 data invalid data valid data invalid txd t66a rxd previous data valid output data invalid data valid input t66 power up (vcc) reset t59 t58
low-power octal phy ? lxt9784 datasheet 59 4.6 clock specifications 4.6.1 mclk specifications mclk is the lxt9784 master clock. it is externally sourced by an oscillator. table 41 defines the lxt9784 requirements from this signal. figure 26. master clock specifications figure 27. master clock slope specifications table 41. mclk specifications parameter symbol min typ max units condition mclk duty cycle t60 (t mclk_dc )35 65 % mclk period t61 (t mclk_pr )20 ns rmii mode - 50 mhz mclk period t61 (t mclk_pr )8 ns smii mode - 125 mhz mclk slope t62 (t mclk_sl )3 v/ns mclk jitter t63 (t mclk_jit ) 100 ps peak 1. the mclk frequency shall be 50 ppm. 2. trace characteristic impedance (z 0 ), 60w 10%. t60 t60 t61 1.4v t62 t62 90% 10%
lxt9784 ? low-power octal phy 60 datasheet 5.0 register definitions the phy registers can be accessed through the mii management interface. table 42 defines the bit type designations used in the following tables. table 42. bit type designations designator definition sc self cleared ro read only p external pin affects content ll latch low lh latch high. table 43. control register (register 0) bit definitions bit(s) name description type 1 0.15 reset sets the status and control register of the phy to their default states and is self- clearing. the phy returns a value of ? 1 ? when this register is read until the reset process has completed and accepts a read or write transaction. 1 = phy reset. default 0 = normal operation. rw sc 0.14 loopback enable loopback of transmit data to the receive data path. the phy receive circuitry is isolated from the network. note that this may cause the de-scrambler to lose synchronization and produce 560 ns of ? dead time ? . 1 = loopback enabled. default 0 = loopback disabled (normal operation). rw 0.13 speed selection controls speed when auto-negotiation is disabled. default 1 = 100 mbps 0 = 10 mbps rw p 0.12 auto-negotiation enable bits 0.13 & 0.8 (speed selection and duplex mode, respectively) are ignored when auto-negotiation is enabled. bits 4.12:5 (technology ability field) depends on the phy ability (register 0) to define the preferred link configuration. default 1 = auto-negotiation enable. 0 = auto-negotiation disable. rw p 0.11 power down 1 = analog section only power-down enabled. default 0 = power-down disabled (normal operation). rw 0.10 isolate allows the phy to isolate the media independent interface. the phy doesn't respond on the both transmit and receive activities. 1 = logical isolate of internal mii interface. default 0 = normal operation. rw 1. refer to table 42 for type definitions.
low-power octal phy ? lxt9784 datasheet 61 0.9 restart auto- negotiation restarts the auto-negotiation process and is self cleared after 300 ns 1 = restart auto-negotiation process. default 0 = normal operation. rw sc 0.8 duplex mode controls the duplex mode when auto-negotiation is disabled. if the phy reports that it only able to operate in one duplex mode (via bits 1.15:11), the value of this bit shall correspond to the mode which the phy can operate. when the phy is placed in loopback mode, the behavior of the phy shall not be affected by the status of this bit, bit 0.8. 1 = full duplex. default 0 = half duplex. rw 0.7 collision test force collision in response to the assertion of txen. 1 = force col. default 0 = disable collision signal test. rw 0.6:0 reserved constant ? 0 ? . ro table 44. status register (register 1) bit definitions bit(s) name description type 1 1.15 100base-t4 constant 0 = phy not able to perform 100base-t4. ro 1.14 reserved constant ? 0 ? . ro 1.13 100base-tx half duplex 1 = phy able to perform half duplex 100base-tx 0 = phy not able to operate in 100base-tx ro 1.12 reserved constant ? 0 ? . ro 1.11 10 mbps half duplex 1 = phy able to operate at 10 mbps in half duplex mode 0 = phy not able to operate in 10base-t ro 1.10:7 reserved constant ? 0 ? . ro 1.6 mf preamble suppression constant 0 = phy will not accept management frames with preamble suppressed. ro 1.5 auto-negotiation complete 1 = auto-negotiation process completed default 0 = auto-negotiation process has not completed. ro 1.4 remote fault constant 0 = no remote fault condition detected ro 1.3 reserved constant 0 ro 1.2 link status 1 = valid link has been established. default 0 = invalid link detected. ro ll sc 1.1 jabber detect this bit has meaning only in 10 mbps mode. 1 = jabber condition detected. default 0 = no jabber condition detected. ro lh sc 1.0 extended capability constant 1 = extended register capabilities enabled ro 1. refer to table 42 for type definitions. table 43. control register (register 0) bit definitions (continued) bit(s) name description type 1 1. refer to table 42 for type definitions.
lxt9784 ? low-power octal phy 62 datasheet table 45. phy identifier register (register 2) bit definitions bit(s) name description type 1 2.15:0 phy id (word msb) value: 02a8 ? h ro 1. ro = read only. table 46. phy identifier register (register 3) bit definitions bit(s) name description type 1 3.15:0 phy id (word lsb) value: 0250 ? h ro 1. ro = read only. table 47. auto-negotiation advertisement register (register 4) bit definitions bit(s) name description type 1 4.15 next page constant 0 = transmitting primary capability data page. ro 4.14 reserved constant ? 0 ? .ro 4.13 remote fault 1 = indicates link partner ? s remote fault. default 0 = no remote fault. rw 4.12:5 technology ability field an 8-bit field containing information indicating supported technologies specific to the selector field value. rw 4.12 reserved ignore. r/w 4.11 reserved ignore r/w 4.10 pause 1 = pause operation enabled for full-duplex links. 0 = pause operation disabled. r/w 4.9 100base-t4 1 = 100base-t4 capability is available. 0 = 100base-t4 capability is not available. (the lxt9784 does not support 100base-t4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100base-t4 operation. an external 100base-t4 transceiver could be switched in if this capability is desired.) r/w 4.8 100base-tx full-duplex 1 = port is 100base-tx full duplex capable. 0 = port is not 100base-tx full duplex capable. r/w 4.7 100base-tx 1 = port is 100base-tx capable. 0 = port is not 100base-tx capable. r/w 4.6 10base-t full-duplex 1 = port is 10base-t full duplex capable. 0 = port is not 10base-t full duplex capable. r/w 4.5 10base-t 1 = port is 10base-t capable. 0 = port is not 10base-t capable. r/w 4.4:0 selector field a 5-bit field identifying the type of message to be sent via auto- negotiation. default 00001 ? b (ieee standard 802.3) ro 1. refer to table 42 on page 60 for type definitions.
low-power octal phy ? lxt9784 datasheet 63 note: registers 8-15 are ieee reserved table 48. auto-negotiation link partner ability register (base page) (register 5) bit definitions bit(s) name description type 1 5.15 next page reflects the phy ? s link partner ? s auto-negotiation ability ro 5.14 acknowledge indicates that the phy has successfully received its link partner ? s auto- negotiation advertising ability. ro 5.13 remote fault reflects the phy ? s link partner ? s auto-negotiation ability. ro 5.12:5 technology ability field reflects the phy ? s link partner ? s auto-negotiation ability. ro 5.12 reserved ignore. ro 5.11 reserved ignore ro 5.10 pause 1 = link partner is pause capable. 0 = link partner is not pause capable. ro 5.9 100base-t4 1 = link partner is 100base-t4 capable. 0 = link partner is not 100base-t4 capable. ro 5.8 100base-tx full duplex 1 = link partner is 100base-tx full duplex capable. 0 = link partner is not 100base-tx full duplex capable. ro 5.7 100base-tx 1 = link partner is 100base-tx capable. 0 = link partner is not 100base-tx capable. ro 5.6 10base-t full duplex 1 = link partner is 10base-t full duplex capable. 0 = link partner is not 10base-t full duplex capable. ro 5.5 10base-t 1 = link partner is 10base-t capable. 0 = link partner is not 10base-t capable. ro 5.4:0 selector field reflects the phy ? s link partner ? s auto-negotiation ability. ro 1. ro = read only. table 49. auto-negotiation expansion register (register 6) bit definitions bit(s) name description type 1 bit(s) name description r/w 6:15:5 reserved constant ? 0 ? .ro 6.4 parallel detection fault 1 = fault detected via parallel detection (multiple link fault occurred). default 0 = no fault detected via the parallel detection. ro lh sc 6.3 link partner next page able 1 = link partner is next page able. default 0 = link partner is not next page able. ro 6.2 next page able constant 0 = local device is not next page able. ro 6.1 page received 1 = new page received. default 0 = new page not received. ro lh sc 6.0 link partner auto- negotiation able 1 = link partner is auto-negotiation able default 0 = link partner is not auto-negotiation able ro 1. refer to table 42 on page 60 for type definitions.
lxt9784 ? low-power octal phy 64 datasheet table 50. register 16 (10 hex) status and control bit(s) name description type 1 bit(s) name description r/w 16.15:14 reserved constant ? 0 ? .ro 16.13 reserved constant ? 0 ? .rw 16.12 reserved constant ? 0 ? .ro 16.11 receive de-serializer in- sync indication indicates status of the 100base-tx receive de-serializer in-sync indication. ro 16.10 100base-tx power- down indicates the power state of 100base-tx. 1 = power-down. 0 = normal operation. ro 16.9 10base-t power-down indicates the power state of 10base-t. 1= power-down. 0= normal operation. ro 16.8 polarity indicates 10base-t polarity. 1 = reverse polarity. 0 = normal polarity. ro 16.7 reserved must be set to zero during write. ro 16.6:2 phy address value determined by id[1:0] and phy port number (which of 8) ro 16.1 speed indicates the auto-negotiation result. 1 = 100 mbps. 0 = 10 mbps. ro 16.0 full duplex indicates the auto-negotiation result. 1 = full duplex. 0 = half duplex. ro 1. refer to table 42 on page 60 for type definitions. table 51. register 17 (11 hex) special control bit(s) name description type 1 17.15 scrambler by-pass scrambler by-pass control. 1 = by-pass scrambler. default 0 = normal operation. rw p 17.14 by-pass 4b/5b 1= 4 bit to 5 bit encoder by-pass. default 0 = normal operation. rw p 17.13 force transmit h-pattern 1 = force transmit h-pattern. default 0 = normal operation. rw 17.12 force 34 transmit pattern 1 = force 34 transmit pattern. default 0 = normal operation. rw p 17.11 good link 1 = 100base-tx good link indication forcing to asd output. default 0 = normal operation. rw p 17.10 reserved must be set to zero during write rw 1. refer to table 42 on page 60 for type definitions.
low-power octal phy ? lxt9784 datasheet 65 17.9 carrier sense disable controls the rx100 crs disable function 1 = crs disable. default 0 = crs enable. rw 17.8 reserved must be set to zero during write rw 17.7 auto-negotiation loopback 1 = auto-negotiation loopback. default 0 = auto-negotiation normal mode. rw 17.6 mdi tri-state 1 = mdi tri-state (transmit driver tri-states) default 0 = normal operation rw 17.5 force polarity 1 = reversed polarity default 0 = normal polarity operation. rw 17.4 auto polarity disable 1 = auto polarity disabled. default 0 = auto polarity enabled. rw 17.3 sqe disable 1 = 10base-t squelch test disabled. default 0 = normal squelch operation rw 17.2 extended squelch extended squelch control. 1 = 10base-t extended squelch control enabled. 0 = 10base-t extended squelch control disabled. rw 17.1 link integrity disable 1 = link disabled. default 0 = normal link integrity operation. rw p 17.0 jabber function disable 1 = jabber disabled. default 0 = normal jabber operation. rw table 52. register 18 (12 hex) phy interrupt register bit(s) name description type 1 18.15:2 reserved constant ? 0 ? . ro 18.1 interrupt enable enables the assertion of a specific phy interrupt line. however, bit 0 is not masked, and the interrupt bit will remain visible. 1 = enable the assertion of the interrupt line. default 0 = disable the interrupt line. rw 18.0 link status interrupt reflects the phy link integrity changing. the bit is self-cleared after any read cycle. 1 = a change on phy link status was detected. ro sc 1. refer to table 42 on page 60 for type definitions. table 53. reg 19 (13 hex) 100 base-tx rcv false carrier counter bit(s) name description type 1 19[15:0] false carrier sense a 16 bit counter that increments for each false carrier event (bad ssd). the counter stops when full (and does not roll over.) self clears on read. ro sc 1. refer to table 42 on page 60 for type definitions. table 51. register 17 (11 hex) special control (continued) bit(s) name description type 1 1. refer to table 42 on page 60 for type definitions.
lxt9784 ? low-power octal phy 66 datasheet table 54. reg 20 (14 hex) 100basetx receive disconnect counter bit(s) name description type 1 20[15:0] disconnect event a 16 bit counter that increments for each disconnect event. the counter stops when full (and does not roll over). self clears on read. two or more consecutive false carrier events causes this counter to increment. ro sc 1. ro = read only; sc = self cleared. table 55. reg 21 (15 hex) 100basetx receive error frame counter bit(s) name description type 1 21[15:0] receive error frame a 16 bit counter that increments once per frame for any receive error condition, such as a symbol error or premature end of frame, in that frame. the counter stops when full (and does not roll over). self clears on read. ro sc 1. ro = read only; sc = self cleared. table 56. reg 22 (16 hex) receive symbol error counter bit(s) name description type 1 22[15:0] symbol error counter a 16-bit counter that increments for each symbol error. the counter stops when full (and does not roll over). self clears on read. ro sc 1. ro = read only; sc = self cleared. table 57. reg 23 (17 hex) 100basetx receive premature end of frame error counter bit(s) name description type 1 23[15:0] premature end of frame a 16-bit counter that increments for each premature end of frame event. the counter stops when full (and does not roll over). self clears on read. a frame without a ? tr ? at the end is considered a premature end of frame event. ro sc 1. ro = read only; sc = self cleared. table 58. reg 24 (18 hex) 10baset receive end of frame error counter bit(s) name description type 1 24[15:0] end of frame counter a 16-bit counter which increments for each end of frame error event. the counter stops when full (and does not roll over). self clears on read. ro sc 1. ro = read only; sc = self cleared. table 59. reg 25 (19 hex) 10baset transmit jabber detect counter bit(s) name description type 1 25[15:0] jabber detect counter a 16-bit counter which increments for each jabber detection event. the counter stops when full (and does not roll over). self clears on read. ro sc 1. ro = read only; sc = self cleared.
low-power octal phy ? lxt9784 datasheet 67 table 60. reg 26 (1a hex) reserved bit(s) name description type 1 26[15:0] reserved data read from this should be ignored. ro 1. ro = read only. table 61. register 27 (1b hex) phy special control bit(s) name description type 1 27.15:5 reserved constant ? 0 ? . ro 27.4 led blink 1 = led blink disabled. default 0 = led blink enabled (normal operation). rw 27.3 100rx jabber enable enables carrier sense disconnection while phy in jabber at 100mbps. 1 = carrier sense disconnection enabled. default 0 = carrier sense disconnection disabled. ro 27.2:0 led switch control [2:0] leda ledb ledc 000 link/activity speed collision (rmii, smii modes) 001 collision speed speed 010 link speed speed 011 collision speed activity 100 off speed off 101 on speed off 110 off speed on 111 on speed on rw 1. ro = read only; rw = read/write.
lxt9784 ? low-power octal phy 68 datasheet 6.0 mechanical specifications figure 28. package specifications parameter min max n ball count 324 a overall height 1.94 2.32 a 1 stand off 0.50 0.70 a 2 encapsulation height 1.12 1.22 d package body length 26.80 27.20 d 1 encapsulant length 23.75 24.25 s 1 outer ball center to edge of body 1.44 ref b ball diameter 0.60 0.90 c (2l/4l) substrate thickness .32/.52 .40/.60 e ball pitch 1.27mm 1. all dimensions in millimeters

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