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RSC-300/364 speech recognition microcontroller data sheet ? 2001 sensory inc. p/n 80-0165-o 1 general description the RSC-300/364, from the interactive speech tm family of products, is designed specifically for speech applications in consumer electronic products. the RSC-300/364 combines an 8-bit processor with neural-net algorithms to provide high-quality speaker-independent speech recognition, speaker- dependent speech recognition, and speaker verification. the chip also supports speech synthesis, voice record/playback, 4-voice music synthesis, and system co ntrol. this cmos device includes on-chip ram, rom (rsc-364 only), 16 general-purpose i/o lines, a/d and d/a converters, a microphone pre-amplifier, and a 4-mips dedicated processor. the RSC-300 is designed for rom-less applications that need more rom space and consequently use off-chip memory. in addition to providing the horsepower needed to perform speech recognition and speech synthesis, the processor has sufficient cycles available for general-purpose product control. the RSC-300/364 development kit allows developers to create custom applications. the development kit includes an assembler, linker, simulator, hardware development platform, and library of sensory technology object code. the highly integrated nature of this chip reduces external parts count. a complete system may be built with only a few passive components in addition to a battery, speaker, and microphone. low power requirements and low-voltage operation make the RSC-300/364 an ideal solution for battery-powered and hand-held devices. the RSC-300/364 uses a pre-trained neural network to perform speaker-independent speech recognition, while high-quality speech synthesis is achieved using a time-domain compression scheme that improves on conventi onal adpcm. four-voice music synthesis allows multiple, simultaneous instruments for harmonizing. automatic gain control can compensate for people not optimally positioned with respect to the microphone or for people who speak too softly or loudly. features high-performance processor 4-mips performance at 14.32 mhz 16 general purpose i/o lines interrupts, timers and counters fully static operation; clock rate: dc to 14.32 mhz highly-integrated single-chip solution internal 64 kb of rom (364 only), 2.5 kb of ram 12 bit a/d (analog to digital) converter microphone pre-amplifier internal 32khz secondary timer 24 x 24 multiplier can store 6 speaker dependent words on- chip low power requirements requires single 2.85v to 5.25v power supply ~10ma operating current at 3v low power 32khz oscillator power-down current less than 5 a high-quality recognition and synthesis recognition accuracy: better than 97% (speaker independent) and 99% (speaker dependent). synthesis data rates from 5,000-15,000 bits per second 4-voice music synt hesis capabilities agc control compensates for variations in input signal easily expanded to larger-scale systems separate 16-bit address and 8-bit data buses compatible with common memory components separate code and data address spaces and memory strobes
RSC-300/364 data sheet 2 p/n 80-0165-o ? 2002 sensory inc. table of contents general de scription............................................................................................................ ..................................... 1 features ....................................................................................................................... ........................................... 1 table of contents .............................................................................................................. ...................................... 2 introduction................................................................................................................... ........................................... 3 RSC-300/364 hardware specifications ............................................................................................ ........................ 5 using the rs c-300/364 .......................................................................................................... ................................ 6 memory organization ............................................................................................................ .................................. 7 memory map..................................................................................................................... ....................................... 8 general pu rpose i/o ............................................................................................................ ................................... 9 interrupts ..................................................................................................................... ............................................ 9 reset and cloc ks ............................................................................................................... ................................... 10 timers and counters............................................................................................................ ................................. 11 power down and wake -up operation ............................................................................................... ................... 11 analog outputs................................................................................................................. ..................................... 12 hardware de bug features ........................................................................................................ ............................ 12 design consi deratio ns .......................................................................................................... ................................ 13 omni-directional microphone.................................................................................................... ............................ 14 power consumption and powe r supply cons iderations .............................................................................. ........ 16 die bond pad and qfp pin descriptions.......................................................................................... .................... 17 die pad ring ................................................................................................................... ...................................... 18 RSC-300/364 die bondi ng pad locations .......................................................................................... .................. 19 absolute maxi mum rati ngs....................................................................................................... ............................ 20 d.c. characteristics ........................................................................................................... ................................... 20 vdd vs. idd.................................................................................................................... ......................................... 20 a.c. characteristics (ext ernal memory accesses) ................................................................................ ............... 21 timing di agrams ................................................................................................................ ................................... 21 RSC-300/364 in struction set.................................................................................................... ............................. 22 RSC-300/364 specia l function register (sfr) su mmary ............................................................................ ....... 24 quality and re liability........................................................................................................ .................................... 38 packaging...................................................................................................................... ........................................ 40 ordering in format ion ........................................................................................................... .................................. 41 the interactive speec h? product line ........................................................................................... ..................... 42
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 3 introduction the RSC-300/364 is the newest member in a family of high-performance 8-bit micropr ocessors featuring a high level of integration, targeted to hi gh-accuracy, low-cost speech recogniti on applications. the RSC-300/364 is designed to bring accuracy, fast response time and versatility to low-cost, power-sensitive consumer applications. a design goal of the RSC-300/364 was to reduce total sy stem cost while increasing system performance. by including microphone signal amplification, data conv ersion, recognition and synthesis functionality, and rom storage (rsc-364 only) with a cpu core on a single chip , dramatic cost and power reductions are achieved. thus, the RSC-300/364 is able to provide 4 mips of int eger performance at 14.32 mhz. this allows customer applications to achieve maximum performance at minimum cost. the cpu core embedded in the RSC-300/364 is an 8-bit, variable-length-instruction, microprocessor. the instruction set is most similar to the 8051 family of microcontrollers. the rsc-3 00/364 processor avoids the limitations of dedicated regist ers by having completely symmetrical sour ce and destinations for all instructions. of the 2.5 kbytes of internal sram, 2 kbytes are organi zed as a data space, and 0. 5 kbytes is for register space. all arithmetic operation instructions may be app lied to any register. any pair of adjacent registers (at an even address) may be used as the 16-bit pointer to eit her the source or destination for a data movement instruction. instruction classes allow th e pointer to access internal or exte rnal code space, internal register space, or external data space. architecturally, the RSC-300/364?s separate data and address buses allow use of standard eproms, roms, and srams with little or no additional decoding. provision for separate read and write signals for each external memory space further simplifies interfacing. creating applications using the RSC-300/364 requires the development of electronic circuitry, software code, and speech/music data files (?linguistics? ). this document provides detailed information on those aspects of the RSC-300/364 architecture that are im portant to product designers and programmers. it describes the physical interface to the chip, printed circuit board layout and other design considerations, the RSC-300/364?s instruction set, and memory organization. refer to the RSC-300/364 development kit manual for information on using sensory?s technology code for speech recognition, speake r verification, speech synthesis, and voice record and playback. description of vocabulary development (?lingu istics?) information is beyond the scope of this document and is covered in a design note. custom mask capabilities of the rsc-364 the RSC-300 provides significant and flexible expansion capabilities thr ough the use of external ram or rom products using the custom-mask version of the chip, the rsc-364, may save considerable per-unit cost by avoiding the need for other active devices. the rsc- 300 requires an external code space rom memory to contain the program instructions, sy nthesis data, and speaker independent recognition weights. the custom- masked rsc-364 with no additional external memory devices must rely on the fixed internal memory for all of its rom and ram requirements. the internal rom in the rsc-364 is application specific, with the amount available for user applications decreasing as the number of synthesis words or other technology usage increases. these finite resources restri ct the capabilities of products based on the rsc-364. the prod uct specification for the rsc-364 must be carefully crafted in consultation with sensory to maximize the use of on-chip memory. each application will have its own spec ific limitations, but the table below summarizes some useful guidelines for planning purposes. not all of the maximums can be achieved in a single custom-masked rsc-364 design. for example, a recognition vocabulary of 40 words may lim it the speech synthesis to substantially less than 25 seconds. note: the rsc-364 (custom ma sk) column assumes no external memory .
RSC-300/364 data sheet 4 p/n 80-0165-o ? 2002 sensory inc. description RSC-300 rsc-364 (custom mask ) 1 capabilities: speaker independent (si) recognition 9 9 speaker dependent (sd) recognition 9 limited speech synthesis and special sound effects 9 9 speaker verification 9 9 four-voice music generation 9 limited support voice record and playback 9 not supported 6 si recognition capacity : maximum number of words per recognition set 1 15 15 total recognition vocabulary size in words, all sets unlimited 40 words 3 sd recognition capacity : maximum number of words per recognition set 1 64 2 6 3 /64 4 total recognition vocabulary size in words, all sets unlimited 6 3 /512 4 speaker verification capacity : number of speakers identified per set 1 64 2 1 3 /64 4 synthesized speech capacity: maximum total length of all messages unlimited 25 seconds 3 music synthesis capacity number of simultaneous independent musical voices 4 4 number of musical octaves available 2-4 5 2 number of musical tunes available unlimited 6 requirement for custom rom masks: custom-masked parts (rsc -364) are not stocked by sensory no internal rom custom masked rom required 1. software for the rsc-364 (custom masked) applications ma y be completely developed and verified using the RSC-300/364 development kit and an external 64k rom memory before committing to an rsc-364 custom rom mask. 2. practical limitations to maintain accuracy above 95%. 3. assumes the use of on-chip rom/ram only 4. assumes external serial eeprom memory. 5. depends on choice of musical instrument. 6. requires external storage for recordings.
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 5 RSC-300/364 hardware specifications architectural overview of the RSC-300/364 the RSC-300/364 is a hi ghly integrated device that combines: ? an 8-bit risc microprocessor. ? on-chip rom (64 kbytes, rsc-364 only), register ram (448 bytes), data ram (2 kbytes) and the ability to address off-chip ram or rom. ? analog-to-digital converter, digital-to- analog converter, and a pulse width modulator. ? a microphone pre-amplifier the RSC-300/364 has an external memory interface for accessing external rams, roms or other parallel memory devices. the rsc- 364 also has an internal rom that can be enabled or disabled (partially or fully) by pin inputs (signals -xmh, -xml; s ee figure 4 ). ). when the internal rom of the rsc-364 is disabled, its performance is identical to the RSC-300. with the rsc-364, the entire program must reside in the internal masked rom. external memory can only be used to store data. the 8-bit processor can directly access 448 on-chip general-purpose registers (ram), and 32 additional special functions registers (sfrs). the instruction set accessing these registers is completely symmetrical, allowing mov s, arithmetic, and logical operations with any register as the destination. tw o bi-directional ports provide 16 general-purpose i/o pins to communicate with external devices (see page 9) . the RSC-300/364 has a high frequency (14.32 mhz) oscillator as well as a low frequency (32,768 hz) oscillator. the proces sor clock can be selected from ei ther source, with a selectable divider value. sensory?s technology code requires the use of the 14.32 mhz clock. there are two programmable 8-bit counters / timers, one derived from each oscillator. a variety of wait state configurations allow fast code execution and easy interfacing to slow peripheral memories. an inexpensive electret microphone connects directly to the microphone input of the RSC-300/364. the internal preamplifier converts the tiny microphone signal to a leve l suitable for analog-to-digi tal conversion. (adc), the RSC-300/364 uses a sample and hold (sh) circuit a nd adc converter to convert the amplified analog speech signal into digital data. the chip may also be used wi th line-level inputs. the output audio signal of the rsc- 300/364 is derived either from a dac (digital-to-anal og converter) or a pwm (pulse width modulator). in addition to its on-chip rom (rsc-364 only) and ram, the RSC-300/364 has 8 data lines (d[7:0]) and 16 address lines (a[15:0]), al ong with associated control signals (-rd c, -rdd, -wrc, -wrd, -xml, -xmh) for interfacing to external memory. the memory control si gnals on the RSC-300/364 and the processor instruction set provide independent code and data spaces, allowing configuration of systems up to 192 kbytes with no additional hardware decoding. the RSC-300/364 features 16 general-purpose i/o pins (px.y) for product and memory bank control. pre-amp external memory interface cpu timing and control 32k x 8 32k x 8 high low internal rom (rsc-364) a[15:0] d[7:0] -rdc -wrd -rdd -wrc 448 bytes 8 levels -xmh -xml -reset -te1/ pwm stack space register space break point register aife1 analog control adc timer1 timer2 osc1 osc2 port 0 interrupt logic dacout xi1, xo1 xi2, xo2 p0.0-p0.7 p1.0-p1.7 dac pulse width modulator port 1 aofe3 ain1 aofe2 aofe1 ain? aife2 pwm bufout/ speech processing unit 2k technology sram figure 1 ? RSC-300/364 block diagram
RSC-300/364 data sheet 6 p/n 80-0165-o ? 2002 sensory inc. using the RSC-300/364 creating applications using the RSC-300/364 requires the development of electronic circuitry, software code, and speech/music data files. software code for the RSC-300/364 can be developed by sensory or by external programmers using the RSC-300/364 development ki t. for more information about development tools and services, please contact sensory, or visit www.sensoryinc.com . a typical product will require about $0.30 - $1.00 (in high volume) of additional components, in addition to the RSC-300/364. the following sample circuit provides an example of how the RSC-300/364 might be used in a low volume consumer electronic product. the external rom contai ns the application program, recognition weights, and speech data. a high volume application would likely use an rsc-364 (custom-masked rom), and would not require the separate rom. figure 2 ? reference circuit note: applications using the pwm output may no t meet fcc or ce (such as en55022 class a or b) standards for radiated emissions. for applications that must meet these standards, sensory recommends turning off the pwm in the application software, and using an e xternal audio power amplifier connected to the dac output. please refer to s ensory's application note 80-0105 "dac output" for sample c ircuits and design guidelines.
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 7 memory organization internal rom memory (rsc-364 only) internal rom is organized as two banks of 32 kbytes ea ch, both mapped into code space. either of the two internal banks may be independently disabled using exter nal inputs; input pin -xml disables the lower 32k [0000h-7fffh] bank, while input pin -xmh disables the upper 32k [8000h-ffffh] bank. when a bank is disabled, read accesses to it are directed to off-chip code space. in most applications the -xml and -xmh signals will both be grounded (for use with external ro m program memory) or both will be left floating (to use internal rom memory for program memory). write accesses to the code space are directed to external memory off-chip. except for specific addresses in the last page of memory (described on page 8), read and write accesses to data space are always directed to external memory. external memory the RSC-300/364 allows for extended message lengths and expanded program functionality by using external memory. there are 30 pins that provide an interface between the RSC-300/364 and external rom or ram. the 16 address line outputs, a[15:0], are shared for accesses to external code space or data space. the 8 data lines, d[7:0], are bi-directional, and are normally inputs ex cept when there is a write to external memory. refer to memory map (on page 8) for details on accessing external code and data spaces through movc and movx instructions. the RSC-300/364 uses the -rdc, -wrc, -rdd and -wrd si gnals to strobe data to or from memory or i/o devices. the -rdc and -wrc strobes are provided fo r accessing code space, while the -rdd and -wrd strobes are used to access data space. these four memory strobes are all active low (see page 25 for timing information). using these strobes, the RSC-300/364 can directly access 64k of external code space (either internal or external) and 64k of external data space. ex ternal memory and i/o devices can reside in code space (RSC-300 only) or data space, as determin ed by the user applicat ion. executable code must reside in code space; tables and other data may reside in code spac e or data space. using i/o bits, additional external decoding can be used to bank select between multiple rams or roms. this method allows for external data space storage requirements larger than the combined 128k addressed directly by t he RSC-300/364. figure 3 below illustrates a typical large data space rom-only memo ry configuration. the lowe st 64k bank is addressed as code space, and the other 7 banks are addressed as data space. the rom is sele cted by both -rdd and - rdc. additional logic may be required to use both rom and ram/flash in external data space. sensory's RSC-300/364 technology code requires code execution at 14.3 mhz with one wait state. external rom code memory speeds should be 120 ns or faster. external data space access speed may be independently controlled by the insertion of additional wait states for movx instructions, simplifying access to slow read/write devices. addr (0 - 15) addr 16 data /ce /oe addr 17 addr 18 p0.4 p0.3 p0.2 /rdd /rdc data addr(0 - 15) a18 a17 a16 4 mbit rom RSC-300/364 figure 3 -- large rom decoding
RSC-300/364 data sheet 8 p/n 80-0165-o ? 2002 sensory inc. memory map the RSC-300/364 has three address spaces: code space, data space, and register space. code space is typically rom. data space may be rom, ram, flash, or other parallel read/write memories. register space is limited to on-chip sram. the instruction set provides separate instructions for accessing each space. executable code must reside in code space; tables and other data may reside in code space or data space. register space is intended primarily for variables. the internal rom (rsc-364 only) and off-chip code space memory (RSC-300 only) may be accessed using movc instructions. the off-chip data space is accessed using movx instructions, while the on-chip register space is accessed using mov instructions. writes to code space are always directed off-chip. the internal rom (rsc-364 only) is organized as two code space banks of 32 kbytes each. the banks can be independently disabled using external inputs: the low bank (address range 0000h-7fffh) can be disabled by asserting pin input -xml while the high bank (address range 8000h-ffffh) can be disabled by asserting pin input -xmh. this feature may be used to expand ex ternal addressable code space beyond 64 kbytes. the sram register space supports 8-bit addresses, so only 256 bytes may be directly addressed. general-purpose registers are located between addresses 000h and 0bfh. a 32-byte bank of sfrs (special function registers) resides at addresses 0e0h-0ffh. the 32-byt e bank at addresses 0c0h- 0dfh may be mapped to any of the six lower 32-byte banks in page 0 (addresses 000h through 0bfh), or to eight additional 32-byte banks in page 1 (addresses 100h-1ffh. a special function register controls this mapping, providing a total of 448 bytes of sram register sp ace. the RSC-300/364 also contains 2 kbytes of internal da ta space ram that is reserved for technology use. off-chip memory (and memory-mapped i/o) is accessed using a 16-bit address bus and an 8-bi t data bus. separate read / write strobes are generated for access to external code and data spaces. this allows the RSC-300/364 to directly access 64 kbytes of external code memo ry and 64 kbytes of external data memory. bank switching is commonly implemented using i/o pins to select additional off-chip memory. certain addresses in the range of 0ff00h-0ffffh of data space are mapped internally, so addresses in this last page of data space are not generally accessible. the RSC-300/364 allows software to adjust the speed of off- chip memory access. this allows using fast memory for performance needs or (if feasible) slower memory for cost savings. the off-chip memory access time can be stretched using wait states defined by the bank register, and the software can dynamically change the wait state value depending on the particular memory or i/o peripheral. wait states for external data space may be select ed independently of code space wait states. there is modest stack space on chip. the stack is re quired for interrupts and allows a limited number of nested calls. programmers are encouraged to write inline code in stead of making deeply-nested subroutine calls. the RSC-300/364 offers limited support for a software st ack to allow more deeply nested calls or to store parameters, although this is not usua lly required. macros using this software stack are accessible to developers. 32k x 8 32k x 8 high [8000h-ffffh] low [0000h-7fffh] rsc-364 int rom -xmh -xml movc (read access) mapped ram bank register space 0c0h 0e0h 100h mov 000h special function registers 1ffh off-chip address space 64k x 8 code space movc (write access) 64k x 8 data space movx -rdc -wrc -rdd -wrd stack space (reserved) mapped to ram bank figure 4 -- memory map
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 9 general purpose i/o the RSC-300/364 has 16 general -purpose i/o pins (p0.0-p0.7, p1.0-p1. 7). each pin can be programmed as an input with weak pull-up (~200k ? equivalent device); input with strong pull-up (~10k ? equivalent device); input without pull-up, or as an output. this is accomplished by having 32 bits of configuration registers for the i/o pins (port control register a and port control register b for ports 0 and 1). (see page 24) after reset, all of the i/o pins are set to be inputs with weak pull-ups. designers may make use of this start-up feature to assure enabling or disabling of particular functions controlled by i/o pins. for electrical specifications regarding the general purpose i/o pins, please refer to d.c. characteristics. all i/o pins are diode clamped to v dd and ground, and are capable of sinking up to 200 ma if v dd is exceeded. in addition to providing general purpose i/o, port 0 bit p0.0 can serve as an interrupt input (using imr and irq registers). any i/o pin may be used as a ?wakeu p? event when the chip is in ?sleep? mode. typically some of the i/o pins may be used for extended a ddress bits in larger system s having more than 64k of memory. this may be done by connecting port pins directly to address bit 16 and higher pins of large memory devices. interrupts the RSC-300/364 allows for six interr upt sources, as selected by software. each has its own mask bit and request bit in the imr and irq registers respectively. the global interrupt enable flag, which enables or disables all interrupts, is located in the flags registers. bi t assignments for the imr and ir q registers are listed on page 34. the following events can generate interrupts: positive edge on port 0, bit 0 overflow of timer 1 overflow of timer 2 two sensory proprietary functions completion of pwm sample period note: if an interrupt occurs while the gie bit is being cl eared, the gie bit may be restored to an enabled state upon return from the interrupt service routine. use the clix macro (supplied wi th the sensory speech 6 technology library software) in place of the cli instruct ion to assure that interrupts are globally disabled before proceeding. if an irq bit is set high and the corresponding imr bit is set high and the global interrupt enable bit is set high, an interrupt will occur. interrupts cannot be nested. the flags register is copied to a holding register and then the global interrupt enable is cleared, preventing subsequent in terrupts until the iret instruction is executed. the iret instruction will restore the flags re gister from the holding register. if the corresponding mask register bit is clear, the irq bit will not cause an interrupt. however, it can be polled by reading the irq register. irq bits can be cleared by writing a 0 to the corresponding bit at address 0feh (the irq register). irq bits can not be set by writing to 0feh. writing a one is a no-op. the irq bits must be cleared within the interrupt handler by an explicit write to the irq register rather than by an implicit interrupt acknowledge. im portant: clear interrupts this way: mov irq, #bitmask ; right not this way: and irq, #bitmask ; wrong
RSC-300/364 data sheet 10 p/n 80-0165-o ? 2002 sensory inc. the ?and? instruction is not atomic, it is a read-modify-write. if an interrupt occurs during an ?and irq? operation the interrupt will be cleared before it is seen, possibl y disabling the interrupt un til the system is reset. because you cannot set bits in the irq register, a ?mov ir q? is a safe, effective, and atomic way to clear bits in the irq register. use it the way you wo uld use an ?and? in other registers. note: if port 0.0 (the external irq) is set as an output , the external irq flag will be set if the output is driven from 0 to 1 under program control. for each interrupt, execution begins at a different code space address: interrupt #0 address 4 interrupt #1 address 8 interrupt #2 address 0ch interrupt #3 address 10h interrupt #4 address 14h interrupt #5 address 18h normally the instruction at the interrupt address is a jump to an interrupt service routine (isr). this jump is called a vector . the vectors located at each of t hese addresses are typically in rom. reset and clocks reset the reset pin, -reset, is an active low schmitt trigger input. the reset pin is provided with hysteresis in order to facilitate power-on reset generation via an rc network. reset is held internally for 10 msec after the -reset input signal is de-asserted. this a llows the oscillator to stabilize before enabling other processor subsystems. the -reset signal must be asserted for a minimum of 2 clock periods. oscillators two independent oscillators in the RSC-300/364 provi de a high-frequency clock and a 32 khz time-keeping clock. the oscillator charac teristics are as follows: oscillator #1 pins xi1 and xo1 14.32 mhz oscillator #2 pins xi2 and xo2 32,768 hz oscillator #1 works with an external crystal, a ceramic resonator, or lc. use of oscillator #2 requires a crystal for precise timekeeping. each oscillator has an enable control. when disabled, the inverter is high-impedance, and a weak pull-up device (~100 k ? ) holds the inverter output high. both oscillators are controlled by the clock control register (cpu register 0e8h). by default, oscillator #1 is enabled by reset, while oscillator #2 is disabled by reset. the effect of reset therefore requires that oscillator #1 be functi onal in all designs. the clock control register also determines internal division of the cpu clock source (see below). each oscillator has an associated timer that is fully programmable. the RSC-300/364 timers are described in the following section. processor clock the RSC-300/364 uses a fully static core; the processor can be stopped (by removing the clock source) and restarted without causing a reset or losing contents of in ternal registers. static operation is guaranteed from dc to 14.32 mhz. the processor clock is selected from eit her the oscillator #1 output (gated by wake-up 10 ms delay) or the oscillator #2 output, based on bit 2 of the clock cont rol register. this bit is cleared by reset, which selects oscillator #1. it is the responsi bility of the firmware not to select oscillator #2 until both oscillators have been enabled and stabilized.
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 11 after source selection, the processor clock can be divided-down in order to limit power consumption. bits 3 and 4 of the clock control register det ermine the divisor for t he processor clock. between zero and seven wait states must also be selected for the processor clock. wait states are inserted on reads or writes to all addresses except register space ram and, under certain c onfigurations, internal rom (rsc-364 only). sensory technology code must run with a processor clo ck of 14.32 mhz, a clock di visor of one, and one wait state. this creates internal ram cycl es of 70 nsec duration and internal rom (rsc-364 only) or external cycles of 140 nsec duration. careful design of external dec oding logic and close analysis of gate delays may allow operation with code space memories having 120 nsec access times. additional wait states may be selected for external data space access. timers and counters the two independent oscillators of the RSC-300/364 provide counts to two internal timers. each of the two timers consists of an 8-bit reload value register and an 8-bit up-counter. the reload register is readable and writeable by the processor. the counter is readable with precaution taken against a counter change in the middle of a read. if the processor writes to the counter, t he data is ignored. instead, the counter is preset to the reload register value. that is, any write to a counter will cause it to be reloaded. this is the usual way of initializing the counter. when the timer overflows from ff to 00, a pulse is generated that sets irq #0 (timer #1) or irq #1 (timer #2). if the corresponding imr bit is se t and the global interrupt bit is set, an interrupt will be generated. instead of overflowing to 00, the counter is automatically reloaded on each overflow. for example, if the reload value is 0fah, the counter will count as follows: 0fah, 0fbh, 0fch, 0fdh, 0feh, 0ffh, 0fah, 0fbh etc. the overflow pulse is generated during the period after the counter value was 0ffh. timer #2 may be used as a wakeup when the processor has powered-down. refer to the following registers for more information about using timers and counters: t1r: timer 1 reload register (page 28) t1v: timer 1 counter register (page 28 ) t2r: timer 2 reload register (page 29) t2v: timer 2 counter register (page 29) power down and wake-up operation the RSC-300/364 can be powered down through software by setting the pd bit (bit7) of the clock control register (see page 33) . setting this bit halts the processor until a ?wakeup? event clears the bit. the instruction that causes the power down event may also set or clear ot her bits in the clock control register to enable or disable any of the clocks, and to select a clock to be used as the processor clock upon wakeup. a wakeup event can be generated from either of two sources: bit transition(s) of port 0 or port 1 pins, or an overflow pulse from timer 2. for low power consumption, oscillator #1 (bit 0) and t he fc clock (bit 5) should al ways be disabled during power down. oscillator #2 (bit 1) must be enabled if the wak eup condition is a timer 2 event. if the wakeup event is an io pin event, all clocks should be disabled for lowest power consumption. if oscillator #1 is disabled during power down, and the selected processor clock so urce is oscillator #1, then a wakeup event will require that oscillator #1 be started and stabilized before its output can be used as the processor clock. the oscillator is started when the wakeup event clears bit 0 of the clock control register, but the processor clock is delayed by 10 milliseconds to assure stability.
RSC-300/364 data sheet 12 p/n 80-0165-o ? 2002 sensory inc. if the RSC-300/364 is powered down with oscillator #2 sele cted as the processor cloc k source, a timer2 wakeup event does not require a delay because it is assumed that oscillator #2 is running and stable. due to long startup time for oscillator #2, the RSC-300/364 should not be powered down with oscillator #2 disabled and selected as the processor clock. a wakeup event does not cause a reset. the processor, wh ich was ?stopped-in-its-tracks? when the pd bit was set, is restarted without loss of context. analog outputs the RSC-300/364 offers two separate options for analog output. the dac (digital to analog converter) output provides a general-purpose 10-bit analog output that may be used for speech output (with the inclusion of an audio amplifier), or that may be used for other pur poses requiring an analog waveform. many speech applications may require only driving a small speaker, ho wever, and cost can be saved in these applications by using the pulse width modulator (pwm) outputs of the RSC-300/364 instead of the dac output. special note: applications using the pwm output may not meet fcc or ce (such as en55022 class a or b) standards for radiated emissions. for applications that must meet these standards, sensory recommends turning off the pwm in the application software, and using an external aud io power amplifier connected to the dac output. please refer to sensory's application note 80-0105 "dac output" for sample circuits and design guidelines. dac output the digital-to-analog converter (dac) provides its ou tput through dacout, with an output impedance of 22k ? . v dacout can swing from 0v to v dd . an external audio amplifier and optional volume control must be used to drive a speaker. filtering above 5 khz is recommend ed to provide the correct frequency response. pwm output the two pwm outputs are designed for driving a 16-ohm speaker at audio frequencies. these signals produce good quality audio with no additional components. these outputs are actually digital outputs that produce a series of high frequency pulses at varying rates tha t, when filtered by the mechani cal dynamics of a speaker, create the effect of a continuously varying analog signal. although it is called a pulse width modulator, the RSC-300/364 ac tually incorporates a pulse count modulator: a programmable number of pulses is produced during each sample period. the two pwm outputs connect directly to the two speaker terminals. during operation, the fi rst of the two signals will be at ground and the second will have a pulse train. the pulses will cause the speake r cone to push out (or pull in, depending on the wiring connections). if there are many pulses in a sample peri od, the speaker will push out a large amount; if there are few pulses, the speaker will push out ju st a little. switching the pulse trai n to the first output and holding the second output at ground effectively reverses the polarity of the signals, so now the speaker will pull in. by controlling the number of pulses in each sample peri od and the output on which t hey appear, the speaker can be made to move in and out as required to reproduce an audio waveform. the pwm0 pin is shared with the bufout signal, and t he pwm1 pin is shared with the -te signal. at power- on, these pins are configured for non -pwm operation. the bufout and -te signals are both test signals that are typically not used during normal operation. when the pulse width modulator is enabled via software, the pins are switched over to the pwm function. see page 36 for information about programming the pwm. typically the pwm is controlled by s ensory library code, so there is littl e need for application programs to alter it. hardware debug features special debugging hardware has been incorporated into the RSC-300/364 to assist developers in producing code quickly. the specialized circuitr y provides the following features: a 16-bit break register that holds one rom breakpoint address a trap bit in the flags register (address 0 ffh) that enables or disables the breakpoint.
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 13 a vector at 0fff8h to which the processor is dire cted when the program counter equals the breakpoint address and the trap bit is enabled. the break occurs before execution of the instruction at the breakpoint address. a special page of code space (0ff00h-0ffffh) for holding the resident debugger software. when this page is entered via a break , timers and interrupts are suspended. when execution resumes outside this page, timers and interrupts are restored. entering this page by means other than a break has no special effect, and timers and interrupts continue to operate as normal. a vector at 0fffch to which the processor is direct ed if the -te pin is held low at power-on. this provides a means for starting up in the debugger. the debug circuitry, in conjunction with debug monitor softw are resident in the last page of code rom, allows examining the contents of register, code, and data space addresses. register space contents may be modified, as may data or external code space addresses if implemented in a rsc-writeable device. additionally, the RSC-300/364 supports a 4-byte, bi-d irectional communication interface using external hardware registers. this interface provides one means for another computer to interact with the resident debug monitor. design considerations speech recognition accuracy can be degraded by a numbe r of factors. a common problem that causes accuracy degradation is noise: both electrical noise within the system and audio noise picked up by the microphone. a major innovation in the RSC-300/364 is th e incorporation of an audio preamp circuit right on the chip. the signal from a typical electret microphone is of the order of a few millivolts, and an overall preamp gain of 200 or more is needed to make this signal use able by the rsc. the rsc-3 00/364 requires only a few external passive components to provide this amplificat ion. good grounding practice and elimination of crosstalk into the analog circuitry will further help ensure good re cognition accuracy. product design that encourages the user to speak loudly and close to the microphone helps attain a good signal-to-noise ratio. analog design the schematic in figure 5 illustrates a reference input audio preamp design for use with the RSC-300/364. the microphone resistor (rx) shown as 1.5k has a large influence on the system gain, so the value will depend on the sensitivity of the microphone. the value of 1.5k is typical. recommended value for rx and cx: rx cx 1k 0.01uf 1.5k 0.0068uf 2.2k 0.0047uf 2.7k 0.0033uf 3.9k 0.0027uf 4.7k 0.0022uf some applications may use the rsc- 300/364 with input signals from a device other than an electret microphone. for assistance with such designs, contact sensory. pcb design a double-sided printed circuit board (pcb) with ground plane is figure 5 -- preamplifier schematic
RSC-300/364 data sheet 14 p/n 80-0165-o ? 2002 sensory inc. recommended. the ground plane should cover the analog circuitry area and only be tied to ground near the rsc device. in order to reduce crosst alk, the analog and digital circuits sh ould be physically separated as far as is practical. take special care to keep high-speed clocked lines (e.g., address and data) away from the microphone components and traces. a 0.1 f bypass capacitor should be installed immediately next to each digital ic and near the v dd pins of the rsc chip. the bypass capacitors should be stacked or mono lithic ceramic type, rated at 50 volts. if a three- terminal voltage regulator (such as a 7805) is used, tantalum bypass capacitors should be connected close to the regulator between the input/output pins and ground. in a practical application using replaceable aa or aaa batte ries, incorporating a protec tion diode in series with the power supply will avoid damage to the circuit if batteries are inse rted with the wrong polarity. if the rsc is used in a system with other digital clocks (switching power supplies, lc d driver, etc.) take special care to prevent these signal from getting into the audio circuitry of the rsc. locating and mounting the RSC-300/364 the RSC-300/364 is supplied as a bare, tested die or in a 64 lead, 10 x 10 x 1.0 mm tqfp package. the die form may be wire bonded directly to the main pcb or, in some cases, may be bonded to a separate chip-on- board (cob) circuit board. in production this cob asse mbly may be functionally tested, then attached to the main board as a working module. there are several methods of attaching the cob to the main board, and a careful choice should be made by the designer. the RSC-300/364 is a 72-pad device requiring good attaching methodology for correct operation. since cost is always a consideration, cob boards may often be designed as single-sided pcbs. the simplest way of attaching a single-sided cob to a main board is to lay it, chip side up, on the main board and make solder bridges from the main board up along the thickness of the cob to the electrical contacts on the top of the cob board. in production this is not a reliable technique. a second technique is to use wires or pins to connec t thru-holes between the main board and the cob. this reliable technique may be more time consuming. a third technique is to put a hole in the main board at the center of the cob location and to mount the cob to the main board upside down, that is, with the chip facing down into the hole. then the cob and main boards may be soldered together. in this case, the orientation of the signal leads of the RSC-300/364 is different from that of the other arrangements. omni-directional microphone selecting a suitable microphone for most applications, an inexpensive omni-directional electret capacitor microphone with a minimum sensitivity of -60 db is adequate. in some applications, a directi onal microphone might be more suitable if the signal comes from a different direction than the audio noise. since directional microphones have a frequency response that depends on their distance from the sound source, such microphones should be used with caution. for best performance, speech recognition products should be used in a quiet environment with the speaker?s mouth in close proximity to the microphone. if the product is in tended for use in a noisy environment, care should be taken to design around the noise. improving the signal-t o-noise ratio will help make the product a success. design of microphone housing proper design and consistent manufacturing of the micr ophone housing is important, because improper acoustic positioning of the microphone will reduce recognition accuracy. this section describes several important considerations that must be carefully followed in designing the microphone mounting and housing. many mechanical arrangements are possible for the microphone element, and some will work better than others. we recommend the following guidelines for the microphone housing:
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 15 first: in the product, the microphone element should be po sitioned as close to the mounting surface as possible and should be fully seated in the plastic housing. there must be no airspace between the microphone element and the housing. having such airs pace can lead to acoustic resonance, which can reduce recognition accuracy. good: mic. element flush with surface bad: air cavity between mic. element and surface. figure 6 -- microphone mounting (1) second : the area in front of the microphone element mu st be kept clear of obstructions to avoid interference with recognition. the diameter of the hole in the housing in front of the microphone should be at least 5 mm. any necessary plastic surface in fr ont of the microphone should be as thin as possible, being no more than 0.7 mm if possible. nothing here! surface mic. element diaphragm mic. element aperture figure 7 -- microphone mounting (2) third : the microphone should be acoustically isolated from the housing if possible. this can be accomplished by surrounding the microphone element wi th a spongy material such as rubber or foam. mounting with a non-hardening adhesive such as rtv is another possibility. the purpose is to prevent auditory noises produced by handling or jarring the pr oduct from being ?picked up? by the microphone. such extraneous noises can reduce recognition accuracy.
RSC-300/364 data sheet 16 p/n 80-0165-o ? 2002 sensory inc. good: absorbent material surrounding element. bad: element fastened directly to housin product housing (usually plastic) absorbent material (usually rubber or foam) figure 8 -- microphone mounting (3 ) if the microphone is moved from 6 inches to 12 inches fr om the speaker?s mouth, the signal power decreases by a factor of four. the difference between a loud and a soft voice can also be more than a factor of four. thus, the recognizer must function over a wide dynamic range of input signal strength and it will have reduced recognition ability if the input signal either saturates the a/d conver ter or is too weak. the rsc- 300/364 provides automatic gain control (agc) to partially compensate for a too-la rge or too-small speech signal. this agc operation is performed inside the microphone preamplifier. if the ag c control range is exceeded, software can provide auditory feedback to the speaker about the voice volume. the product can achieve this by saying ?please talk louder? or ?please don?t talk so loud?. power consumption and powe r supply considerations in operation, the speech recognition circuit may draw a current of around 10 ma. if the system is powered on continuously to listen for a given word, it will drain a butt on battery in a few hours, or a large alkaline battery in several days. thus, if the application requires that t he recognizer be on all of the time, the system should operate from mains power. conversely, if the product is designed to operat e from batteries, it must usually remain in the low-power ?sleep? mode most of the time , until it is occasionally awakened for a few seconds to recognize a word. the RSC-300/364 can be awakened from a button press or other i/o event, or from the countdown of the osc2 timer. it cannot be awakened by a speech signal applied to the microphone input. in order to conserve battery power, the product should be designed to be activated by the user each time it is required to recognize a word. a well-designed program will allow a few seconds after activation before attempting recognition in order to allow reference voltages to stabilize. a speech prompt is a good means of providing this delay. current drain is higher during sp eech or music synthesis becaus e power must be delivered to the speaker. mains-powered supply ripple should not exceed 5 milliv olts measured between the vdd and gnd terminals. when using mains power, regulated dc supplies will typi cally be required. three-terminal voltage regulators (such as the 7805) are used commonly for this purpose and will provide a minimum of 47 db of ripple rejection. the power dissipated by these regulators is a function of the voltage differential between the input and output terminals. for instance, powering a 7805 regulator at 9v and delivering 10 mamp through it will dissipate 40 mwatts of power.
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 17 die bond pad and qfp pin descriptions 19 20 36 37 54 55 72 1 RSC-300a rsc-364 (top view of the die) 19 20 36 37 54 55 72 1 RSC-300b (top view of the die) RSC-300/364 (64-lead tqfp) 45 44 43 42 41 40 39 38 37 47 48 1 2 3 4 5 6 7 8 9 10 11 27 17 18 19 20 21 22 23 24 25 26 d1 d2 d3 d4 d5 d6 d7 pwm1 pwm0 gnd aofe2 a1 a0 xo1 xi1 reset_ p1.7 p1.5 p1.4 p1.3 p1.1 aife1 vref xml_ xmh_ pdn wrd_ rdd_ wrdc_ rdc_ gnd vdd a15 a14 a13 a12 a11 a10 a9 a8 gnd vdd a7 60 59 58 57 56 55 54 53 63 64 61 p0.0 p1.2 p1.6 46 62 12 a6 28 d0 13 a5 a4 a3 a2 31 29 30 p1.0 p0.7 p0.5 p0.6 32 36 35 34 33 p0.1 p0.2 p0.3 p0.4 14 15 16 ain0 aofe3/ain1 dacout aife2/aofe1 52 51 50 49 name die pad qfp pin description i/o a[15:0] 20-27, 30-37 1-8, 11-18 external memory address bus o ain0 5 52 analog in, low gain. (range agnd to avdd/2.) i ain1 4 51 analog in, hi gain (8x input amplitude of ain0, same range) i aofe1 72 49 output of 1 st stage of preamplifier o aofe2 6 53 output of 2 nd stage of preamplifier o aofe3 3 51 output of 3 rd stage of preamplifier o aife1 71 48 output of 1 st stage of preamplifier i aife2 1 49 output of 2 nd stage of preamplifier i nc 10,11,43,44 not connected - pwm0 8 55 pulse width modulator output0 o dacout 2 50 analog output (unbuffered). o d[7:0] 12-19 57-64 external data bus i/o vss 7,28,62 9, 39,54 vss - pdn 67 44 power down. active high when powered down. o p1[7:0], p0[7:0] 43-52,53-60 22-29, 30-37 general purp ose port i/o. pin p0.0 can act as an external interrupt input. all i/o pins can act as ?wake up? inputs. i/o /rdc 63 40 external code read strobe o /rdd 65 42 external data read strobe o /reset 42 21 reset i /te1 or pwm1 9 56 test mode or pulse width modulator output1 (multiplexed) i or o vref 70 47 reference voltage = vdd/2 or vdd/4. depends on software - v dd 29,61 10,38 supply voltage - /wrc 64 41 external code write strobe o /wrd 66 43 external data write strobe o /xmh 68 45 external hi-memory enable (low active) i /xml 69 46 external low-memory enable (low active) i xo1 40 19 oscillator 1 output (high frequency) o xi1 41 20 oscillator 1 input i xo2 38 na oscillator 2 output (32768 hz) o xi2 39 na oscillator 2 input i note : substrate should be connected to vss
RSC-300/364 data sheet 18 p/n 80-0165-o ? 2002 sensory inc. die pad ring versions ?rsc-364 ? and ?RSC-300a? p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 nc nc rstb xi1 xo1 xi2 xo2 a0 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 p05 55 north 36 a1 p04 56 35 a2 p03 57 34 a3 p02 58 33 a4 p01 59 32 a5 p00 60 31 a6 vdd 61 30 a7 gnd 62 29 vdd rdcb 63 west east 28 gnd wrcb 64 27 a8 rddb 65 26 a9 wrdb 66 25 a10 pdn 67 24 a11 xmhb 68 23 a12 xmib 69 22 a13 vref 70 21 a14 aife1 71 south 20 a15 aofe1 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 aife2 daco aofe3 ain1 ain0 aofe2 gnd p0/t2/ f p1/t1 nc nc d7 d6 d5 d4 d3 d2 d1 d0 version ?RSC-300b? p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 vdd gnd rstb xi1 xo1 xi2 xo2 a0 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 p05 55 north 36 a1 p04 56 35 a2 p03 57 34 a3 p02 58 33 a4 p01 59 32 a5 p00 60 31 a6 vdd 61 30 a7 gnd 62 29 vdd rdcb 63 west east 28 gnd wrcb 64 27 a8 rddb 65 26 a9 wrdb 66 25 a10 pdn 67 24 a11 vref 68 23 a12 aife1 69 22 a13 aofe1 70 21 a14 south 20 a15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 aife2 dacout aofe3 ain1 ain0 aofe2 gnd p0/t2/bf p1/t1 avdd vdd d7 d6 d5 d4 d3 d2 d1 d0
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 19 RSC-300/364 die bonding pad locations versions ?rsc-364? and ?RSC-300a? note: all locations are the center of the pad. verify that you are bonding parts marked 65-0087 before using this table! pad # south x (um) y (um) pad # east x (um) y (um) pad # north x (um) y (um) pad # west x (um) y (um) 1 aife2 339.05 96.15 20 a15 3268.4 370.7 37 a0 2663.35 3211.6 55 p05 101.1 2513.5 2 daout 462.9 96.15 21 a14 3268.4 494.55 38 xo2 2533.5 3211.6 56 p04 101.1 2389.65 3 aofe3 586.75 96.15 22 a13 3268.4 618.4 39 xi2 2365.45 3211.6 57 p03 101.1 2265.8 4 ain1 710.6 96.15 23 a12 3268.4 742.25 40 xo1 2235.65 3211.6 58 p02 101.1 2141.95 5 ain0 834.45 96.15 24 a11 3268.4 866.1 41 xi1 2105.8 3211.6 59 p01 101.1 2018.1 6 aofe2 958.3 96.15 25 a10 3268.4 989.95 42 rstb 1975.9 3211.6 60 p00 101.1 1894.25 7 gnd 1090 96.15 26 a9 3268.4 1113.8 43 nc 1830.65 3211.6 61 vdd 101.1 1764.85 8 p0/bf 1312.8 96.15 27 a8 3268.4 1237.65 44 nc 1700.8 3211.6 62 gnd 101.1 1635 9 p1/t1 1665 96.15 28 gnd 3268.4 1381.95 45 p17 1556.35 3211.6 63 rdcb 101.1 1504.85 10 nc 1870 96.15 29 vdd 3268.4 1511.8 46 p16 1432.5 3211.6 64 wrcb 101.1 1381 11 nc 1999.5 96.15 30 a7 3268.4 1652.1 47 p15 1308.65 3211.6 65 rddb 101.1 1257.15 12 d7 2131.95 96.15 31 a6 3268.4 1775.95 48 p14 1184.8 3211.6 66 wrdb 101.1 1133.3 13 d6 2255.8 96.15 32 a5 3268.4 1899.8 49 p13 1060.95 3211.6 67 pdn 101.1 1009.45 14 d5 2379.65 96.15 33 a4 3268.4 2023.65 50 p12 937.1 3211.6 68 xmhb 101.1 885.6 15 d4 2503.5 96.15 34 a3 3268.4 2147.5 51 p11 813.25 3211.6 69 xmlb 101.1 761.75 16 d3 2627.35 96.15 35 a2 3268.4 2271.35 52 p10 689.4 3211.6 70 vref 101.1 637.9 17 d2 2751.2 96.15 36 a1 3268.4 2395.2 53 p07 565.55 3211.6 71 aife1 101.1 470.05 18 d1 2875.05 96.15 54 p06 441.7 3211.6 72 aofe1 101.1 346.2 19 d0 2998.9 96.15 notes: 1- die size: 3.3695 x 3.3127 mm 2- 3- chip orgin is at 0.0, 0.0 mm ( lower left hand corner ). pad size is 100um x 100um version ?RSC-300b? note: all locations are the center of the pad. note: verify th at you are bonding parts marked 65-0 098 before using this table!" pad # south x (um) y (um) pad # east x (um) y (um) pad # north x (um) y (um) pad # west x (um) y (um) 1 aife2 339.05 96.175 20 a 15 3150.925 345.7 37 a0 2449.8 2711.625 55 p05 101.125 2433.05 2 daout 454.05 96.175 21 a14 3150.925 475.7 38 xo2 2334.8 2711.625 56 p04 101.125 2296.05 3 aofe3 569.05 96.175 22 a13 3150.925 605.7 39 xi2 2166.7 2711.625 57 p03 101.125 2159.05 4 ain1 684.05 96.175 23 a 12 3150.925 735.7 40 xo1 2051.7 2711.625 58 p02 101.125 2022.05 5 ain0 799.05 96.175 24 a 11 3150.925 865.7 41 xi1 1936.7 2711.625 59 p01 101.125 1885.05 6 aofe2 914.05 96.175 25 a10 3150.925 995.7 42 rstb 1821.7 2711.625 60 p00 101.125 1748.05 7 gnd 1029.8 96.175 26 a9 3150.925 1125.7 43 nc 1706.7 2711.625 61 vdd 101.125 1611.05 8 p0/bf 1244.1 96.175 27 a8 3150.925 1255. 7 44 nc 1591.7 2711.625 62 gnd 101.125 1474.05 9 p1/t1 1596.7 96.175 28 gnd 3150.925 1385.7 45 p17 1476.7 2711.625 63 rdcb 101.125 1337.05 10 nc 1793.2 96.175 29 vdd 3150.925 1515.7 46 p16 1361.7 2711.625 64 wrcb 101.125 1200.05 11 nc 1908.2 96.175 30 a7 3150.925 1645.7 47 p15 1246.7 2711.625 65 rddb 101.125 1063.05 12 d7 2023.2 96.175 31 a6 3150.925 1775.7 48 p14 1131.7 2711.625 66 wrdb 101.125 926.05 13 d6 2138.2 96.175 32 a5 3150.925 1905.7 49 p13 1016.7 2711.625 67 pdn 101.125 789.05 14 d5 2253.2 96.175 33 a4 3150.925 2035.7 50 p12 901.7 2711.625 68 vref 101.125 652.05 15 d4 2368.2 96.175 34 a3 3150.925 2165.7 51 p11 786.7 2711.625 69 aife1 101.125 483.2 16 d3 2483.2 96.175 35 a2 3150.925 2295.7 52 p10 671.7 2711.625 70 aofe1 101.125 346.2 17 d2 2598.2 96.175 36 a1 3150.925 2425.7 53 p07 556.7 2711.625 18 d1 2713.2 96.175 54 p06 441.7 2711.625 19 d0 2828.2 96.175 notes: 1- die size: 3.2520 x 2.8127 mm ( not including scribe ) 2- chip origin is at 0.0, 0.0 mm ( lower left hand corner ). 3- pad size is 100um x 100um
RSC-300/364 data sheet 20 p/n 80-0165-o ? 2002 sensory inc. absolute maximum ratings any pin to gnd: -0.1v to +6.5v operating temperature(t o ): 0c to +70c soldering temperature: 260c for 10 sec power dissipation: 1 w operating conditions: -20c to +70c; v dd =2.85 - 5.25v v ss =0v warning : stressing the RSC-300/364 beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. d.c. characteristics (t o = 0c to +70c, v dd = 2.85v ? 5.25v ) symbol parameter min typ max units test conditions v il input low voltage -0.1 0.75 v v ih (vcc<3.6) input high voltage 0.8*vdd vdd+0.3 v v ih (vcc>3.6) input high voltage 3.0 vdd+0.3 v v ol output low voltage 0.3 0.1*vdd v i ol = 2 ma v oh output high voltage (i/o pi ns) 0.8*vdd 0.9*vdd v i ol = - 2 ma i il logical 0 input current <1 10 ua v ss data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 21 a.c. characteristics (e xternal memory accesses) (t o = -20c to +70c, v dd = 3.3v; load capacitance for outputs = 80 pf; osc=14.32 mhz) cpu=osc/1, 1 ws cpu=osc/2, 0ws symbol parameter min max min max units 1/tcl1 processor clock frequency 14.32 7.16 mhz trlrh -rdc (-rdd) pulse width 140 140 ns trlav -rdc (-rdd) low to address valid 5 5 ns talrax address hold after -rdc (-rdd) 0 0 ns travdv address valid to valid data in 135 135 ns trhdx data hold after -rdc (-rdd) 0 0 ns twlwh -wrc (-wrd) pulse width 140 140 ns tavwl address valid to -wrc (-wrd) 35 70 ns talwax address hold after -wrc (-wrd) 35 70 ns twdvav write data valid to address valid 5 5 ns twhqx data hold after -wrc (-wrd) 35 70 ns timing diagrams note that the -rdc signal does not necessarily pulse for every read from code space, but may stay low for multiple cycles. address -rdd (-rdc) data -wrc (-wrd) trlrh trlav travdv trhdx twlwh address tavwl talrax talwax twdvav twhqx data external read timing external write timing
RSC-300/364 data sheet 22 p/n 80-0165-o ? 2002 sensory inc. RSC-300/364 instruction set the instruction set for the RSC-300/364 has 54 instructions comprising 10 move, 7 rotate, 11 branch, 11 register arithmetic, 9 immediate arit hmetic, and 6 miscellaneous instructio ns. all instructions are 3 bytes or fewer, and no instruction requires more than 10 clock cy cles to execute. the column ?cycles? indicates the number of clock cycles required for ea ch instruction when operating with ze ro wait states. wait states may be added to lengthen all accesses to external addresses or to the internal rom (rsc-364 only), but not internal sram. the column ?+cycles/waitstate? shows the number of additional cycles added for each additional wait state. the wait states used for movx instructions may be set independently of those used for movc or code fetches. this table assumes movx and fetch wait states are the same. opcodes are in hex. move group instructions register-indirect instructions accessing code ( movc ) or data ( movx space locations use an 8-bit operand (?@source? or ?@dest?) to designate an sram register pointer to the 16-bit target address. the ?source? or ?dest? pointer register must be at an even address. t he low byte of the target address is contained at the pointer address, and the high byte of the target address is contained at the pointer address+1. register- indirect instructions accessing register ( mov,push,pop ) space locations use an 8-bit operand (?@source? or ?@dest?) to designate an sram register pointer to the 8-bit target address. the carry, sign, and zero flags are not affected by mov instructions. instruction opcode operand 1 operand 2 description bytes cycles +cycles waitstate mov 10 dest source register to register 3 5 3 mov 11 @dest source register to register-indirect 3 5 3 mov 12 dest @source register-indirect to register 3 6 3 mov 13 dest #immed immediate data to register 3 4 3 movc 14 dest @source code space to register 3 7 4 movc 15 @dest source register to code space 3 8 4 movx 16 dest @source data s pace to register 3 7 4 movx 17 @dest source register to data space 3 8 4 pop 18 dest @++source register to register data stack pop (source pre- incremented) 3 10 3 push 19 @dest-- source register to register data stack push (dest post- decremented) 3 9 3 rotate group instructions rotate group instructions apply only directly to regist er space sram locations. the carry flag is affected by these instructions, but the sign and zero flags are unaffected. instruction opcode operand 1 operand 2 description bytes cycles +cycles waitstate rl 30 dest - rotate left, c set from b7 2 5 2 rr 31 dest - rotate right, c set from b0 2 5 2 rlc 32 dest - rotate left through carry 2 5 2 rrc 33 dest - rotate right through carry 2 5 2 shl 34 dest - shift left, c set from b7, b0=0 2 5 2 shr 35 dest - shift right, c set from b0, b7=0 2 5 2 sar 36 dest - shift right arithmetic, c set from b0, b7 duplicated 2 5 2 branch group instructions the branch instructions use direct address values rather than offsets to define the ta rget address of the branch. this implies that binary code containing branches is not relocatable. however, object code produced by sensory?s assembler contains address references that are resolved at link time, so .obj modules are relocatable. the indirect jump instruction uses an 8-bi t operand (?@dest?) to designat e an sram register pointer to the 16-bit target address. the ?dest? pointer register must be at an even address. the low byte of the target
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 23 address is contained at the pointer address, and the high by te of the target address is contained at the pointer address+1. instruction opcode operand 1 operand 2 description bytes cycles +cycles waitstate jc 20 dest low dest high jump on carry = 1 3 3 3 jnc 21 dest low dest high jump on carry = 0 3 3 3 jz 22 dest low dest high jump on zflag = 1 3 3 3 jnz 23 dest low dest high jump on zflag = 0 3 3 3 js 24 dest low dest high jump on sflag = 1 3 3 3 jns 25 dest low dest high jump on sflag = 0 3 3 3 jmp 26 dest low dest high jump unconditional 3 3 3 call 27 dest low dest high direct subroutine call 3 3 3 ret 28 - - return from call 1 2 1 iret 29 - - return from interrupt 1 2 1 jmpr 2a @dest - jump indirect 2 4 2 miscellaneous group instructions instruction opcode operand 1 operand 2 description bytes cycles +cycles waitstate nop 00 - - no operation 1 2 1 clc 01 - - clear carry 1 2 1 stc 02 - - set carry 1 2 1 cmc 03 - - complement carry 1 2 1 cli 04 - - disable interrupts 1 2 1 sti 05 - - enable interrupts 1 2 1 arithmetic/logical group instructions arithmetic and logical group instructions apply only to register space sram locations. the results of the instruction are always written directly to the sram ?dest? register. all but th e increment and decrement instructions have both register source and immediate source forms. in each of the following instructions the sign and zero fl ags are updated based on the result of the operation. the carry flag is updated by the arit hmetic operations (add, adc, sub, subc, cp, inc, dec) but it is not affected by the logical operations (and, tm, or, xor). note: the carry is set high by sub, cp, subc, dec when a borrow is generated. instruction opcode operand 1 operand 2 description bytes cycles +cycles waitstate and 40 dest source logical and 3 6 3 tm 41 dest source like and, destination unchanged 3 6 3 or 42 dest source logical or 3 6 3 xor 43 dest source exclusive or 3 6 3 sub 44 dest source subtract 3 6 3 cp 45 dest source like sub, destination unchanged 3 6 3 subc 46 dest source subtract w/carry 3 6 3 add 47 dest source add 3 6 3 adc 48 dest source add w/carry 3 6 3 inc 49 dest - increment 2 5 2 dec 4a dest - decrement 2 5 2 and 50 dest #immed logical and 3 5 3 tm 51 dest #immed like and, destination unchanged 3 5 3 or 52 dest #immed logical or 3 5 3 xor 53 dest #immed exclusive or 3 5 3 sub 54 dest #immed subtract 3 5 3 cp 55 dest #immed like sub, destination unchanged 3 5 3 subc 56 dest #immed subtract w/carry 3 5 3 add 57 dest #immed add 3 5 3 adc 58 dest #immed add w/carry 3 5 3
RSC-300/364 data sheet 24 p/n 80-0165-o ? 2002 sensory inc. RSC-300/364 special function register (sfr) summary this section describes the registers located in addres ses 0e0h through 0ffh of the register space. these special function registers (sfrs) are generally used for configuration control and syst em level functions. in many cases an applications programmer might need to acce ss these registers only to initialize the ports. since the sfrs are extensively used by sensory?s library f unctions, thorough understanding is essential before changing the contents of these regist ers. some registers in this address range are for the exclusive use of sensory technology functions and are not further described. the symbol shown is the name recognized by the assembler for the associated register. symbol address register name type p0out 0e0h port 0 output register r/w p1out 0e1h port 1 output register r/w p0in 0e2h port 0 input register read p1in 0e3h port 1 input register read p0ctla 0e4h port 0 control register a r/w p1ctla 0e5h port 1 control register a r/w p0ctlb 0e6h port 0 control register b r/w p1ctlb 0e7h port 1 control register b r/w ckctl 0e8h clock control register r/w wake0 0e9h wakeup configuration, port 0 r/w wake1 0eah wakeup configuration, port 1 r/w t1r 0ebh timer 1 reload r/w t1v 0ech timer 1 counter r/w t2r 0edh timer 2 reload r/w t2v 0eeh timer 2 counter r/w anctl 0efh analog c ontrol register r/w stkptrs 0f6h stack read and write pointers r/w osc1ext 0f7h oscillator 1 extended functions r/w brklo 0f8h break address low byte r/w brkhi 0f9h break address high byte r/w dac 0fah dac hold register r/w bank 0fch ram bank select register r/w imr 0fdh interrupt mask register r/w irq 0feh interrupt request register r/w flags 0ffh flags register r/w port 0 output register (address 0e0h) msb p0out lsb d7 d6 d5 d4 d3 d2 d1 d0 this register is used to write values to port 0. val ues written to this register affect bits that have been configured as outputs. bits that have been configured as inputs are not affected. bit description: p0out: output bits d0 through d7 initialization: all bits cleared to 0 upon reset read access: read output bits from port 0 write access: write output bits to port 0 also refer to: p0ctla, p0ctlb
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 25 port 1 output register (address 0e1h) msb p1out lsb d7 d6 d5 d4 d3 d2 d1 d0 this register is used to write values to port 1. val ues written to this register affect bits that have been configured as outputs. bits that have been configured as inputs are not affected. bit description: p1out: output bits d0 through d7 initialization: all bits cleared to 0 upon reset read access: read output bits from port 1 write access: write output bits to port 1 also refer to: p1ctla, p1ctlb port 0 input register (address 0e2h) msb p0in lsb d7 d6 d5 d4 d3 d2 d1 d0 this register is used to read values from port 0. bit description: p0in: input bits d0 through d7 initialization: read access: input bits from port 0 write access: also refer to: p0ctla, p0ctlb port 1 input register (address 0e3h) msb p1in lsb d7 d6 d5 d4 d3 d2 d1 d0 this register is used to read values from port 1. bit description: p1in: input bits d0 through d7 initialization: read access: input bits from port 1 write access: also refer to: p1ctla, p1ctlb port 0 control register a (address 0e4h) msb p0ctla lsb d7 d6 d5 d4 d3 d2 d1 d0 this register is used with p0ctlb to contro l the function of the general-purpose port 0. bit description: p0ctla: initialization: all bits cleared to 0 upon reset read access: write access: also refer to: p0ctlb
RSC-300/364 data sheet 26 p/n 80-0165-o ? 2002 sensory inc. port 0 control register b (address 0e6h) msb p0ctlb lsb d7 d6 d5 d4 d3 d2 d1 d0 this register is used with p0ctla to contro l the function of the general-purpose port 0. bit description: p0ctlb: initialization: all bits cleared to 0 upon reset read access: write access: also refer to: p0ctla the control registers a and b together control the function of the general-purpose port 0: b a function 0 0 input - weak pull-up 0 1 input - strong pull-up 1 0 input - no pull-up 1 1 output for example, if register p0ctlb bit 4 is set high, and r egister p0ctla bit 4 is low, then pin p0.4 is an input without a pull-up device. port 1 control register a (address 0e5h) msb p1ctla lsb d7 d6 d5 d4 d3 d2 d1 d0 this register is used with p1ctlb to contro l the function of the general-purpose port 1. bit description: p1ctla: initialization: all bits cleared to 0 upon reset read access: write access: also refer to: p1ctlb port 1 control register b (address 0e7h) msb p1ctlb lsb d7 d6 d5 d4 d3 d2 d1 d0 this register is used with p1ctla to contro l the function of the general-purpose port 1. bit description: p1ctlb: initialization: all bits cleared to 0 upon reset read access: write access: also refer to: p1ctla the control registers a and b together control the function of the general-purpose port 1:
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 27 b a function 0 0 input - weak pull-up 0 1 input - strong pull-up 1 0 input - no pull-up 1 1 output for example, if register p1ctlb bit 3 is cleared, and register p1ctla bit 3 is set high, then pin p1.3 is an input with a strong pull-up. clock control register (address 0e8h) msb ckctl lsb pd t2 fc cd 1 cd 0 pc s do 2 eo 1 this register is used to enable the tw o oscillators, to select the processor cloc k source and the internal clock divider, and to enable some sleep/wakeup functions. sens ory?s library code may initialize specific settings for this register, so it should be changed only with care. bit description: ckctl.0: eo1 0: enable oscillator #1 inverter 1: disable oscillator #1 cleared by reset or (wakeup & (pcs=0) ) ckctl.1: do2 0: disable oscillator #2 inverter 1: enable oscillator #2 inverter cleared by reset. ckctl.2: pcs 0: processor clock source = oscillator 1 1: processor clock source = oscillator 2 cleared by reset. ckctl.4-ckctl.3: cd1-cd0 select processor clock divisor. the processor clock rate is the fr action of the source clock shown. cd0 division 0 0 1/2 0 1 1/1 1 0 1/8 1 1 1/256 cleared by reset. ckctl.5: fc 0: disable reserved function clock 1: enable reserved function clock cleared by reset. ckctl 6: t2 0: timer #2 overflow does not cause wakeup 1: timer #2 overflow causes wakeup cleared by reset. ckctl.7: pd 0: processor is in operational state 1: processor is in powerdown state (?sleep?) cleared by reset and wakeup. port 0 wakeup configuration register (address 0e9h) msb wake0 lsb d7 d6 d5 d4 d3 d2 d1 d0
RSC-300/364 data sheet 28 p/n 80-0165-o ? 2002 sensory inc. the wake0 register controls the enabling of i/o events on port0 that can cause a processor ?wakeup?. these wakeup events are recognized independently of whether the processor is running or stopped. the processor may also be waked up by countdown of timer2. bit description: wake0.7-wake0.0 wake enable 0: wakeup is not enabled on corresponding p0 port bit 1: wakeup is enabled on corresponding p0 port bit each bit, if set, enables the corresponding general purpose i/o pin of ports p0.0-p0.7 to generate a wake-up event. if enabled, the polarity of the wake-up trigger is determined by the corresp onding bit in the output register: if the input matches the output register, a wake -up even is generated. it is assumed that the general- purpose pin is configured to be an input. each bit, if clear, prevents the corr esponding general-purpose i/o pin of ports p0.0-p0.7 from generating a wake-up event. initialization: all bits cleared to 0 upon reset also refer to: wake1, p0in, p0ctla, p0ctlb port 1 wakeup configuration register (address 0eah) msb wake1 lsb d7 d6 d5 d4 d3 d2 d1 d0 the wake1 register controls the enabling of i/o events on port1 that can cause a processor ?wakeup?. these wakeup events are recognized independently of whether the processor is running or stopped. bit description: wake1.7-wake1.0 wake enable 0: wakeup is not enabled on corresponding p1 port bit 1: wakeup is enabled on corresponding p1 port bit each bit, if set, enables the corresponding general-purpose i/o pin of ports p1.0-p1.7 to generate a wake-up event. if enabled, the polarity of the wake-up trigger is determined by the corresp onding bit in the output register: if the input matches the output register, a wake -up even is generated. it is assumed that the general- purpose pin is configured to be an input. each bit, if clear, prevents the corresponding general purpose i/o pin of ports p1.0-p1.7 from generating a wake-up event. initialization: all bits cleared to 0 upon reset also refer to: wake0, p1in, p1ctla, p1ctlb timer 1 reload register (address 0ebh) msb t1r lsb d7 d6 d5 d4 d3 d2 d1 d0 this register contains an 8-bit reload value for timer 1. the reload register is readable and writeable by the processor. when the timer overflows from ff to 00, a pulse is generated that sets irq #0 (timer #1). bit description: t1r: initialization: all bits cleared to 0 upon reset read access: timer #1 counter reload (2's complement of period) write access: timer #1 counter reload (2's complement of period)
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 29 also refer to: t1v timer 1 counter register (address 0ech) msb t1v lsb d7 d6 d5 d4 d3 d2 d1 d0 timer 1 counter is a read-only register. if the processor writes to the counter, the data is ignored, and the counter is preset to the reload register value from t1r. instead of overflowing to 00, the counter is automatically reloaded on each overflow. for example, if the reload value is 0fah, the counter will count as follows: 0fah, 0fbh, 0fch, 0fdh, 0feh, 0ffh, 0fah, 0fbh etc. the overflow pulse is generated during the period after the counter value was 0ffh. the input clock for timer 1 is always generated from os cillator #1, gated by the wake-up delay, gated by bit 7 of the clock control register, ckctl.7 fl ag = 0, then divided by 16. for normal operation with a 14.3 mhz crystal, timer 1 counts at a rate of 0.895 mhz. thus the longest du ration that can be directly timed is 255/(0.895 mhz) = 285 microseconds. if the t1p bit of the oscillator 1 ext ension register is set (osc1ext.6=1), an additional division by 2 is performed. bit description: t1v: initialization: all bits cleared to 0 upon reset read access: timer #1 current counter value write access: force asynchronous load of counter from reload register also refer to: t1r, osc1ext timer 2 reload register (address 0edh) msb t2r lsb d7 d6 d5 d4 d3 d2 d1 d0 this register contains an 8-bit reload value for timer 2. the reload register is readable and writeable by the processor. when the timer overflows from ff to 00, a pulse is generated that sets irq #1 (timer #2). bit description: t2r: initialization: all bits cleared to 0 upon reset read access: timer #2 counter reload (2's complement of period) write access: timer #2 counter reload (2's complement of period) also refer to: t2v, ckctl timer 2 counter register (address 0eeh) msb t2v lsb d7 d6 d5 d4 d3 d2 d1 d0 timer 2 counter is a read-only register. if the processo r writes to the counter, the data is ignored, and the counter is preset to the reload register value from t2r. instead of overflowing to 00, the counter is automatically reloaded on each overflow. for example, if the reload value is 0fah, the counter will count as follows: 0fah, 0fbh, 0fch, 0fdh, 0feh, 0ffh, 0fah, 0fbh etc.
RSC-300/364 data sheet 30 p/n 80-0165-o ? 2002 sensory inc. the overflow pulse is generated during the period after the counter value was 0ffh. the input clock for timer #2 is generated from oscillator #2 divided by 128. with typi cal operation with a 32,768 hz crystal for oscillator #2, the count rate for timer 2 is 256 hz. when t2r is set to zero, t2r overflows once per second the processor can be configured to ?wakeup? from the powerdown state on an overflow of the timer2 counter. if oscillator 1 is turned off during this time, the only current consumption is due to the slow 32 khz oscillator2 and counter circuits. bit description: t2v: initialization: all bits cleared to 0 upon reset read access: timer #2 current counter value write access: force asynchronous load of counter from reload register also refer to: t2r, ckctl analog control register (address 0efh) msb anctl lsb md ls1 ls0 dm be de m the analog control register configures the a/d and d/a. since the rsc analog signals are normally dedicated to functions associated with sensory?s library code, there is seldom need for applications programs to access this register. bit description: anctl.7: mode bit (md) if the mode bit is 0, the other bits are as follows: anctl.0: m 1: adc mode, comparator powered-up. 0: dac mode, comparator powered-down. cleared by reset. anctl.1: de 1: enable analog output dacout 0: disable analog output dacout cleared by reset. anctl.2: be 1: enable buffered output bufout. 0: disable buffered output bufout. cleared by reset. anctl.3: dm 0: d/a is full-scale. 1: d/a is half-scale. cleared by reset. anctl.4: ls0 provides lsb for full-scale d/a mode. cleared by reset. anctl.5: ls1 provides lsb for half-scale d/a mode, and second to lsb for full-scale d/a mode. cleared by reset.
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 31 anctl.6: reserved analog control register (address 0efh) (continued) if the mode bit is 1, the other bits are as follows: anctl.0-anctl.1: control the inverter strength of the 32,768 hz oscillator bit 1 bit strength 0 0 5 a 0 1 10 a 1 0 20 a 1 1 40 a anctl.2-anctl.3: control the output resistor of the 32,768 hz oscillator bit 3 bit 2 resistance 0 0 50 k ? 0 1 100 k ? 1 0 200 k ? 1 1 400 k ? anctl.4-anctl.6: reserved when reading from the analog control register, the side containing the 32,768 hz osc illator control parameters is not read, while the other side is read. read access: write access: initialization: on reset, both sides of the analog control register are set to zero. also refer to: stack pointers register (address 0f6h) msb stkptrs lsb wr 2 wr 1 wr 0 rd2 rd1 rd0 the RSC-300/364 has an 8-level hardware stack. this register contains the read and write pointers for the stack. access to these re gisters is normally requir ed only by a debugger program. bit description: stkptrs.7 reserved stkptrs6-4 stack write pointer. contains the 3-bit stack address where the next stack wr ite will occur. stkptrs.3 reserved stkptrs.2-0 stack read pointer. contains the 3-bit stack address where the next stack read will occur. oscillator1 extension register (address 0f7h) msb osc1ext lsb irw t1p mx wx 4 wx 3 wx 2 wx 1 wx 0 this register controls a variety of extended use options for prescalers and extra wait states derived from oscillator bit description: osc1ext[4:0] wx4-wx0 control the numb er of wait states inserted for movx instructions when osc1ext.5=1. this allows simplified operation with slow external read/write memories. if no wait states are used, movx access duration is one clock. controlled program delays in the microsecond range can be obtained by setting the desired number of wait states and executing a dummy movx .
RSC-300/364 data sheet 32 p/n 80-0165-o ? 2002 sensory inc. 0 0 0 0 0 use zero additional wa it states (70 nsec at 14.3 mhz) 1 1 1 1 1 use 31 additional wait states (2.24 sec at 14.3 mhz). osc1ext.5 mx 0: movx instructions use wait states in bank[7:5] 1: movx instructions use wait states in osc1ext[4:0] cleared by reset. osc1ext.6 t1p 0: timer1 prescaler uses osc1 1: timer1 prescaler uses osc1/2 cleared by reset. osc1ext.7: irz 0: internal rom (rsc-364 only) acce sses use wait states in reg bank[7:5] 1: internal rom (rsc-364 only ) accesses use zero wait states cleared by reset. also refer to: ckctl, bank break address low register (address 0f8h) msb brklo lsb a7 a6 a5 a4 a3 a2 a1 a0 this register contains the low 8-bits of the 16-bit break address. the high 8-bits of the break address are held in the break address high register. these registers may be read or written only when the trap bit is set (see page 34) . when the trap bit is set, each pending pc address is compared with the br eakpoint address. when a match occurs, then the pc does not fetch the instruction at the breakpoint address, but rather performs a trap. when a trap is performed the flags register is saved, timers are stopped, interrupts are disabled, and execution branches to location 0fff8h. bit description: brklo.7-0 break address low bits [7:0] set to 0ffh by reset. also refer to: brkhi, flags break address high register (address 0f9h) msb brkhi lsb a15 a14 a13 a12 a11 a10 a9 a8 this register contains the high 8-bits of the 16-bit break address. the low 8-bits of the break address are held in the break address low register. these registers ma y be read or written only when the trap bit is set (see page 34) . when the trap bit is set, each pending pc address is compared with the br eakpoint address. when a match occurs, then the pc does not fetch the instruction at the breakpoint address, but rather performs a trap. when a trap is performed the flags register is saved, timers are stopped, interrupts are disabled, and execution branches to location 0fff8h. bit description: brkhi.7-0 break address high bits [15:8] set to 0ffh by reset. also refer to: brkhi, flags dac hold register (address 0fah) msb dac lsb d7 d6 d5 d4 d3 d2 d1 d0 holds the eight most significant bits of the value to be converted to an analog signal. since the analog signal is typically controlled by sensory library code, there is seldom need for applications programs to access this
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 33 register. this register is not affected during a/d conversi ons. it contains a signed, 8-bit number and is cleared to 0 by reset. bit description: dac: initialization: all bits cleared to 0 upon reset read access: dac hold value write access: dac hold value also refer to: ram bank select register (address 0fch) msb bank lsb w2 w1 w0 b4 b3 b2 b1 b0 the RSC-300/364 architecture supports 1024 bytes of register space (ram). only 448 of the maximum 1024 bytes are implemented in the RSC-300/ 364. since the register space inst ructions support 8-bit addresses, some registers must be addressed through a banking sc heme. the bank register generates address bits 9-5 for accesses associated with register space locations 0c 0-0dfh, the ?map bank?. a 10-bit address is always output to the internal sram register space (maximum of 1024 bytes). bit9 is always 0 in the RSC-300/364, and bit8 is zero unless the lower bits are in the map bank range. bit description: bank.0-bank.4: these bits select a specific 32-byte bl ock of registers to be addressed as ?banked ram? at locations 0c0h to 0dfh. any 32-byte block in the internal register space may be mapped to banked ram except for the sfr block and the map bank itself (the block must be aligned on a 32-byte boundary). the special function registers (0e0h-0ffh) may only be directly addressed. the first 192 locations (000h-0bfh) may be directly addressed or they may be mapped to the map bank, while the remaining 256 locations (100h-1ffh) may only be accessed via the map bank through bank selection. sensory?s technology code makes extensive use of register space. bits bank.0-bank.4 select the appro priate bank in ram as follows. bank[4:0] value address mapped to 0c0h-0dfh bank[4:0] value ram bank mapped to 0c0h-0dfh 00h 000h-01fh 08h 100h-11fh 01h 020h-03fh 09h 120h-13fh 02h 040h-05fh 0ah 140h-15fh 03h 060h-07fh 0bh 160h-17fh 04h 080h-09fh 0ch 180h-19fh 05h 0a0h-0bfh 0dh 1a0h-1bfh 06h not allowed 0eh 1c0h-1dfh 07h not allowed 0fh 1e0h-1ffh 010h or greater the system will wrap around (sram bit9 is ignored in RSC-300/364) bank5-bank7: wait states. these bits define the default number of wait states for external/internal memory access (set to 7 on reset). note that both the internal and ex ternal code and data spaces, but not the sram, are controlled by these bits. sensory technol ogy code requires specific wait states, so changes to this register must be restored before invoking any technology code. the osc1ext register allows additional flexibility in wait state generation. bank: initialization: bits 5-7 set to 1, all other bits cleared to 0 upon reset read access: write access: wait state conf iguration, bank selection
RSC-300/364 data sheet 34 p/n 80-0165-o ? 2002 sensory inc. also refer to: osc1ext interrupt mask register (address 0fdh) msb imr lsb ei5 e14 ei3 ei2 ei1 ei0 bit description: imr0-imr4: ei5: 1= enable interrupt request #5 (reserved) ei4: 1= enable interrupt request #4 (pwm complete) ei3: 1= enable interrupt reque st #3 (positive edge of p00) ei2: 1= enable interrupt request #2 (reserved) ei1: 1= enable interrupt reque st #1 (overflow of timer 2) ei0: 1= enable interrupt reque st #0 (overflow of timer 1) imr6-imr7: unused initialization: all bits cleared to 0 upon reset read access: write access: interrupt source selection also refer to: irq, flags interrupt request register (address 0feh) msb irq lsb ir5 ir4 ir3 ir2 ir1 ir0 bit description: irq0-irq4: ir5: 1= interrupt request #5 (reserved) ir4: 1= interrupt request #4 (pwm complete) ir3: 1= interrupt request #3 (positive edge of p00) ir2: 1= interrupt request #2 (reserved) ir1: 1= interrupt request #1 (overflow of timer 2) ir0: 1= interrupt request #0 (overflow of timer 1) irq6-irq7: unused initialization: all bits cleared to 0 upon reset read access: write access: the bits in this register cannot be set by writing a one to any bit, but they can be cleared by writing zeroes. to assure that pending interrupts are not lost, a bit should be cleared by using a mov instruction, not an and instruction. for example, the inte rrupt service routine for timer1 should clear the interrupt by the instruction: mov irq, #~1 do not use ?and? instructions in the irq register. also refer to: imr, flags flags register (address 0ffh) msb flags lsb c z s t k gie the flags register contains three bits related to the result of the last arithmetic/logic al/rotate/misc instruction, one bit that controls breakpoint enabling, one bit for warni ng of stack full condition, two reserved bits, and one bit that controls the generation of interrupt s. the flags register is not affected by branch instructions, except that an iret instruction restores the value preceding the interrupt. the flags register is not affected by mov instructions unless it is the destination register. other instructions affect the flags register in different ways. refer to
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 35 RSC-300/364 instruction set. note : if an interrupt occurs while the gie bit is being clea red, the gie bit may be restored to an enabled state upon return from the interrupt service routine. use the clix macro (supplied wi th the sensory speech 6 technology library software) in place of the cli instruct ion to assure that interrupts are globally disabled before proceeding. bit description: flags.0: gie (global interrupt enable) 0: all interrupts disabled 1: interrupts enabled cleared by reset flags.1: reserved. do not change values in these bits. flags.2: reserved. do not change values in these bits. flags.3: k (stack) 0: stack not full 1: stack filled, possibly overflowed cleared by reset. the stack bit is set when there is no more room in the stack. this can occur under normal program operation, but it may indicate program malfunction. once set, the bit can only be cleared by reset. this bit may be a useful indicator during development. flags.4: t (trap) 0: breakpoint function disabled 1: breakpoint function enabled cleared by reset. when the trap bit is set, the processor w ill jump to the debug monitor when the program counter equals the value in the break point register. normally only used by a debugger. flags.5: s (sign) 0: result of last arithmetic/l ogical operation was non-negative. 1: result of last arithmetic /logical operation was negative cleared by reset flags.6: z (zero) 0: result of last arithmetic /logical operation was non-zero. 1: result of last arithmet ic/logical operation was zero. cleared by reset flags.7: c (carry) 0: no carry from last ar ithmetic/rotate/misc operation. 1: last arithmetic/rotate/mi sc operation produced a carry. cleared by reset
RSC-300/364 data sheet 36 p/n 80-0165-o ? 2002 sensory inc. special data space addresses summary as described previously, the RSC-300/364 uses movx instructions to access all data space locations. typically data space locations are external, but a few specific lo cations are mapped internally in the last page (0ff00h- 0ffffh) of data space. for this reason, it is generally best to plan to use no external addresses in the last page of data space. (the important exception to this is the debugger interface, mapped externally at 0fffch- 0ffffh.) the internally-mapped addresses include the stack registers and the pulse widt h modulator registers. the RSC-300/364 also has 2 kbytes of internal data space sram. this sram is reserved for technology functions and does not conflict with external sram. stack registers (8 each of 16 bits) occasionally it is useful to manipulat e the stack directly (for example, to leave a deeply nested series of calls without unwinding when a fatal error is detected.). si nce the RSC-300/364 stack spac e is limited, the need for such manipulations is unlikely, but the information here allows doing so if desired. the stack pointer registers are described on page 31. address location name type notes 0ffc0h stack 0 low byte r/w 0ffc1h stack 0 high byte r/w 0ffc2h stack 1 low byte r/w 0ffc3h stack 1 high byte r/w 0ffc4h stack 2 low byte r/w 0ffc5h stack 2 high byte r/w 0ffc6h stack 3 low byte r/w 0ffc7h stack 3 high byte r/w 0ffc8h stack 4 low byte r/w 0ffc9h stack 4 high byte r/w 0ffcah stack 5 low byte r/w 0ffcbh stack 5 high byte r/w 0ffcch stack 6 low byte r/w 0ffcdh stack 6 high byte r/w offceh stack 7 high r/w pulse width modulator (pwm) registers the pulse width modulator registers enable and control t he operation of the pwm. when producing speech or music, these registers are controll ed by sensory?s technology code and should not be touched by applications. address location name type page 0ffe0h pwmctrl w/o 45 0ffe1h pwma w/o 45 0ffe2h pwmdata r/w 46 pwm control register (data space address 0ffe0h) msb pwmctrl lsb d7 d6 d5 pwmen fadje n s2 s1 s0 this register is used to enable the pwm, the pwm freque ncy adjust, and to select the sample period. the pwm sample rate is derived from osc#1, divided by vari ous factors controlled by t he pwm registers. sensory?s library code may initialize specific settings for this register, so it should be changed only with care. bit description: pwm_ctrl[2:0]: sample period the pwm rate is proportional to 1/(8-s). the fastest rate occurs with s=7. the slowest rate occurs with s=0.
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 37 cleared by reset pwmctrl.3: fadjen when the fadjen bit is set, the pwm rate is fu rther reduced by the value in the pwm_a register as described below. 0: disable pwm frequency adjust. pwm sample rate = osc1/(256*(8-s)) 1: enable pwm frequency adjust. pwm sample rate = osc1/((512-a)*(8-s)) cleared by reset. pwmctrl.4: pwmen 0: disable pulse width modulator outputs 1: enable pulse width modulator outputs cleared by reset. pwm adjust register (data space address 0ffe1h) msb pwma lsb d7 d6 d5 d4 d3 d2 d1 d0 the pwm adjust register contains an 8-bit unsigned value that may further reduce the sample rate of the pwm. if the fadjen bit is set, then (256-a) wait stat es are inserted at the end of each sample period. ? if a=0, 256 wait states are inserted. ? if a=0ffh, one wait state is inserted. during the wait period, the active output goes to zero. thus, in addition to lowering the sample rate, smaller values of a also reduce the filtered analog output level. bit description: pwm_a: frequency adjust bits d0 through d7 initialization: all bits cleared to 0 upon reset read access: write access: also refer to: pwmctrl, flags, imr, irq pwmdata register (data space address 0ffe2h) msb pwmdata lsb d7 d6 d5 d4 d3 d2 d1 d0 the pwmdata register contains an 8-bit unsigned value that determines the output pulse pattern (duty cycle) of the active pwm output. when d7=0, the pwm0 output is active and the pwm1 output is zero. the largest output signal for pwm0 is obtained with d=00h. when d7=1, the pwm1 output is active and the pwm0 output is zero. the largest output signal for pwm1 is obtained with d=0ffh. the pwm repeats each data pulse pattern once each sample period. at the end of a sample period, the pwm sets pwmirq. the interrupt service routine may provide a new data value. if the irq is not serviced, the pwm continues to output the data originally stored in pwmdata. output data always lags input by one pwm sample period. bit description: pwmdata: pulse width modulator data bits d0 through d7 initialization: all bits cleared to 0 upon reset read access: write access: also refer to: pwmctrl, pwm_a
RSC-300/364 data sheet 38 p/n 80-0165-o ? 2002 sensory inc. quality and reliability sensory strives to improve customer satisfaction through the on-time delivery of quality products that exceed customer expectations and requirements. to meet these needs, sensory is committed to the goal of continuous quality improvement. each organization within the co mpany is empowered to develop and implement programs that improve the quality of products delivered by sensory. sensory?s quality program extends not only to internal employees, but to its subcont ractors and consultants. s ensory works closely with subcontractors to integrate their quality programs within sensory?s own program. reliability and overview sensory?s reliability program characterizes sensory pr oducts and identifies areas for future improvement. sensory?s overall program is divided into three main categories: 1. qualification - this program ensures that new product de signs, processes, and packages meet their established specifications (e.g., absolute maximum ratings and worst case criteria for use). a variety of tests and statistical analyses are used to create a high conf idence level for determining device performance. 2. monitoring - after qualification of a device, a monitoring pr ogram is used to check that ongoing products continue to meet the established operat ing conditions. a randomly selected sample of devices are used to monitor the predicted relia bility of the products. 3. evaluation and improvement - this program continuously evaluates the results of the qualification and monitoring programs to identify areas for improvement. failure analysis is used to understand the test results and insure quality products are being shipped to customers. sensory?s reliability testing is designed to deliver co mmercial grade parts. since sensory uses top quality manufacturers and designs to stringent requirements, the RSC-300/364 may meet higher reliability standards (e.g., industrial, automotive). reliability tests sensory?s reliability testing focuses on the RSC-300/ 364 in a 64-pin tqfp package. reliability testing is accomplished by subjecting devices to a variety of st ress conditions that accelerate failure mechanisms. the tests used by sensory have been defined by several indust rial standards. jedec 22 is the source for most of the testing methods used by sens ory in its reliability program. this document outlines sensory?s reliability testing for the RSC-300/364. this testing outlines the set of tests performed on the RSC-300/364 in order insure that our pr oducts meet their listed specifications. customers interested in higher levels of reliability should cont act sensory. sensory uses a combination of independent testing houses and vendors to augm ent sensory?s internal staff. reliability test descriptions the following tests were used to de termine the reliability of the rsc-30 0/364. the table below summarizes each of the tests performed. test standard conditions physical dimensions jedec-std-22b-b100 mark permanency jedec-std-22b-b107 solderability jedec-std-22b-b102 autoclave jedec-std-22b-a102-a 96 hours, 30 psi preconditioning jedec-std-22-a113 level 3 bias life jedec-std-22b-a108 +125c, 1008 hours hast jedec-std-22-a110-a 100 hrs, 120c, 85%rh, 33.3 psi lead integrity jedec-std-22b-b105-a resistance to soldering heat jedec-std-22b-b106 thermal shock jedec-std-22b-a106 -65/+150c, 500 cycles temperature cycling mil-std-883-1010.7 -65/+150c, 2000 cycles esd mil-std-883-3015.7 hbm, 2000v latch up eij/jesd-std-78 class 1
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 39 package/process 1. autoclave - reference method jedec-std-22, method a102-a this unbiased test evaluates the moisture resistan ce of nonhermetic solid-state devices. devices are subjected to severe conditions of pressure, humid ity and temperature to accelerate the penetration of moisture through the external protective material or along the interface between the external protective material and the metallic conductors that pass thr ough it. this test is performed under the following conditions: ta=~121c, 100% rh, p=30 psi, 96 hours. 2. preconditioning - reference method jesd-std-22, method a113, level 3. this test method simulates a typical industry multiple solder reflow operation. plastic surface mounted devices are subjected to this test before being submitted to reliability testing. level 3 refers to the exposed shelf life of the device, which is 168 hours after removal from a vapor barrier bag. this method is also used as an indicator for the package?s resistance to ty pical moisture conditions found in board assembly. package/chip 1. bias life - reference method jedec-std-22, method a108 this test is performed to determine the effects of bi as conditions and temperature on solid state devices over an extended period of time. this test acce lerates failure mechanisms that are activated by temperature while under bias, and is used to predict long term failure rates based on accepted methods of calculation using acceleration by temperature. it is intended primarily for device qualification and reliability monitoring. this test is performed at a temperature of 125 c for 1008 hours. 2. highly accelerated temperature and humidity stress test (hast) reference method jesd-std-22, method a110-a. this test is performed to determine the reliability of non- hermetic packaged solid-state devices in humid environm ents. it accelerates the penetration of moisture through the device by subjecting the device to severe temperature, humidity, and bias. this test usually activates the same failure modes as jedec-std-22 , method a101 (85/85). the testing conditions are 120c, 85% rh, and 33.3 psia for a duration of 100 hours. 3. electrostatic discharge (esd) - reference method mil-std-883, method 3015.7 this test is performed to determi ne the susceptibility of the device to a defined electrosta tic human body model discharge. 4. latch up - reference method eij/jesd-std-method 78 this test is performed to determine ic latch up characteristics in order to ensure reliabilit y and minimizing failures due to electrical overstress. package design 1. lead integrity - reference method jedec-std-22, method b105-a this overall test includes various tests for determini ng the integrity of device leads, welds, and seals. devices are subject to various stresses and are then examined for failure criteria. 2. resistance to soldering heat - reference method jedec-std-22, method b106 this test provides a method for determining whether device leads can withstand the effects of temperature during soldering. 3. thermal shock - reference method jedec-std-22, method a106 this test determines the ability of solid state devic es to withstand exposure to extreme changes in temperature. temperature is cycled to expose damag e caused by differing expansion coefficients of the die and package. this test occurs with the chip immersed in liquid. the test consists of 500 cycles between low temperature (-65 c) and high temperature (+150 c) with an immersion time at each temperature of at least five minutes and transitions of ten seconds or less. 4. temperature cycling - reference method mil-std-883-1010.7 this test determines the resistance of a device to extremes of high (+150 c) and low (-65 c) temperatures, and alternate exposures to these extremes. this te st accelerates the effect s of temperature changes caused by differing expansion coefficients of the di e and package. this test consists of 2000 cycles between low temperature and high temperature with a transi tion time not to exceed five minutes. dwell at each extreme is ten minutes.
RSC-300/364 data sheet 40 p/n 80-0165-o ? 2002 sensory inc. packaging the RSC-300/364 is available as tested, singulated die, tested wafers, or in a 64 lead, 10 x 10 x 1.0 mm tqfp package. tqfp mechanical dimensions unit/symbol mm (base) inch (ref) a 1.200 (max) 0.047 (max) a1 0.100+ 0.05 0.004+ 0.002 a2 1.00+ 0.05 0.039+ 0.002 b 0.170~0.270 0.007~0.011 e1 12.000+ 0.100 0.472+ 0.004 e 10.000+ 0.100 0.394+ 0.004 e 0.500 (typ) 0.020 (typ) t 0.127 (typ) 0.005 (typ) y 0.076 (max) 0.003 (max) 0~7 0~7 l 0.006+ 0.150 0.024+ 0.006 l1 1.000 (ref) 0.039 (ref)
data sheet RSC-300/364 ? 2002 sensory inc. p/n 80-0165-o 41 tqfp tray mechanical dimensions ordering information part shipping p/n marketing p/n description RSC-300a die 65-0087 c300xs1p tested, singulated RSC-300 die in waffle pack RSC-300b die 65-0098 c30bxs1p tested, si ngulated RSC-300b die in waffle pack RSC-300 qfp 65-0111 c300xv1t RSC-300 64 pin 10 x 10 x 1.0 mm tqfp rsc-364 die (rom specific) c364xs1p test ed, singulated rsc-364 die in waffle pack rsc-364 qfp (rom specific) c364xv1t rsc-364 64 pin 10 x 10 x 1.0 mm tqfp note: 1. heat resistance up to 24 hours 150 c 2. surface electric resistivity less than 10 12 ? /sq 3. warpage is within 0.76mm 4. tolerance: x=+ 0.5mm, x.x=+ 0.25mm, x.xx=+ 0.13mm
1991 russell ave., santa clara, ca 95054 tel: (408) 327-9000 fax: (408) 727-4748 ? 2002 sensory, inc. all right reserved. sensory is registered by the u.s. patent and trademark office. all other trademarks or registered trademarks are the property of their respective owners. www.sensoryinc.com the interactive speech? product line the interactive speech line of ics and software was developed to ?bring life to products? thr ough advanced speech recognition a nd audio technology. the interactive speech product line was designed for consumer telephony pr oducts and cost-sensitiv e consumer electr onic applications such as home electronics, personal security, and personal communication. the product line includes award-winning r sc series general-purpose microcontrollers and tools, sc series of speech microcontrollers, plus a line of easy-to-implement chips that c an be pin- configured or controlled by an external host microcontroller. sensory?s software te chnologies run on a variety of microcontroll ers and dsps. rsc microcontrollers and tools the rsc product line contains low-cost 8-bit speech- optimized microcontrollers des igned for use in consumer electronics. all members of the rsc family are fully int egrated and include a/d, pre-amplifier, d/a, rom, and ram circuitry. the rsc family can perform a full range of speech/audio functions includi ng speech recogni tion, speaker verification, speech and music synthesis, and voice record/playback. the family is supported by a complete suite of evaluation tools and development kits. sc microcontrollers and tools the sc-6x product line feature the highest qua lity speech synthesis ics at the lowest data rate in the industry. the line inclu des a 12.32 mips processor for high-quality low data-rate speech compression and midi music synthesis, with plenty of power left over for o ther processor and control functions. members of the sc-6x line can store as much as 37 mi nutes of speech on chip and include as muc h as 64 i/o pins for external interfacing. integrating this broad range of features onto a single chip enables developers to create products with high quality, long duration speech at very competitive price points. application specific standard products (assps) voice direct? 364 provides inexpensive speaker-depe ndent speech recognition and speech sy nthesis. this easy-to-use, pin- configurable chip requires no custom programming and can recogn ize up to 60 trained words in slave mode, and 15 words in stand- alone mode. ideal for speaker-dependent command and control of hous ehold consumer products, voic e direct? 364 is part of a complete product line that includes the ic, m odule, and voice direct 364 speech recognition kit. voice extreme? simplifies the creation of fully custom speech- enabled products by offering developers the capability of programming the chip in a high-level c-like language. pr ogram code, speech data, and even record and playback information can be stored on a single off-chip flash memo ry. based on sensory's rsc-364 speech processor, voice extreme includes a highly efficient on-chip code interpreter, and is supported by a comprehensive suite of low-cost development tools. software and technology voice activation? micro footprint software provi des advanced speech technology on a va riety of microcontroller and dsp platforms. a flexible design with a broad range of technologies allows manufacture rs to easily integrate speech functionality into consumer electronic products. fluent speech? small footprint software recognizes up to 50,000 words; offers animated speech with the ability to automate enunciation and articulation; performs text-to-speech synthesis in either male or female voices ; provides noise and echo cancel lation, performs word spotting for natural language usage; offers tel ephone barge-in; and provides c ontinuous digit recognition. important notices reasonable efforts have been made to verify the accuracy of info rmation contained herein, however no guarantee can be made of accuracy or applicability. sensory reserv es the right to change any specification or description contained herein. sensory rese rves the right to make changes to or to discontinue any product or service identified in this publication at any time without notice in order to improve design and supply the best possible product. sensory does not assume responsibilit y for use of any circuitry other than circuitry entirely embodied in a sensory product. info rmation contained herein is provided gratui tously and without liability to any user . reasonable efforts have been made to verify the accuracy of this in formation but no guarantee whatsoev er is given as to the acc uracy or as to its applicability to particular uses. applications de scribed in this data sheet are for illustrative purposes only, an d sensory makes no warranties or representations that the rsc/sc series of pr oducts will be suitable for such applications. in every instance, it must be the responsibility of the user to determine the suitability of the products for each application. sensory products are not auth orized for use as critical components in life support devices or systems. sensory conveys no license or title, either expressed or implied, un der any patent, copyright, or mask work right to the rsc series of products, and sensory makes balanc e between recognition and synthesi s no warranties or representations that the rsc series of products are free from patent, copyright, or mask work right infringement, unless otherwise specified. nothing contained herei n shall be construed as a recommendation to use any product in violation of existin g patents or other rights of third parties. the sale of any sens ory product is subject to all s ensory terms and conditions of sal es and sales policies.

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