general information the gd14526 re-timer is designed for 1.2 gbit/s - 1.5 gbit/s point-to-point serial transmission systems such as hdtv sig- nals according to smpte292. alterna- tively the gd14526 can be configured to operate in the 300 mbit/s - 375 mbit/s range. the device provides a fully integrated so- lution for clock recovery and data (cdr) re-timing and includes an output driver for 50/75 s cables. the cdr can be bypassed for data rates outside the vco range. the clock and data recovery circuit consists of: u a bang-bang phase detector (pd) with data re-timing u a phase-frequency comparator (pfc) u a lock detect circuit (ldc) with lock alarm output u a tristatable charge pump u a wide tuning range vco. the vco centre frequency is determined by the refck multiplied by 20. the loop filter time constant is determined by an external rc filter. when in lock, the digital lock detect circuit (ldc) uses the incoming data to control the pll. when not in lock, i.e. the vco frequency is more than 500 ppm away from the refck frequency, the ldc switches to the local clock (refck) until the vco frequency once more en- ters the 500 ppm range. then it switches back to the pd, comparing the vco clock to the incoming data stream. the ldc continuously monitors the vco frequency against the refck input, clearing lock if the vco leaves the lock range. the high-speed data input is differential and compatible with pecl levels. it is connected via loop-through transmission lines to minimise stub related reflections. the open collector cable driver has dif- ferential outputs and the current in the output stage can be adjusted to a maxi- mum of 36 ma. the gd14526 is packaged in a 40 pin leaded multi layer ceramic (mlc) pack- age with cavity down for easy cooling. preliminary features l two operating ranges: ? 1.2 -1.5 gbit/s ? 300 - 375 mbit/s l jitter in accordance with smpte292. l high-speed data input and output use loop-through bondings to reduce reflections. l complete clock/20, data recovery, and lock acquisition on one ic. l digitally controlled capture and lock. ? full capture range with true phase/frequency detect between vco-clk and refck. ? bang-bang phase detector between vco-clk and data. ? lock in range 500 ppm or 2000 ppm referred to refck. ? lock alarm output. l re-timed differential 50/75 s cable driver output with external termination resistors. l supply operation : 5 v and 3.3 v. l power dissipation: 1100 mw typ. l power down mode for bypass operation. l 40 pin multi layer ceramic (mlc) leaded package with transmission lines. applications l hdtv studio equipment. l gigabit ethernet hdtv 1.5 gbit/s re-timer gd14526 data sheet rev. 02 vco sop son cip sip sin den vctl sel1 refck /20 clock divide lock detect 4:2 mux pfc charge pump div. /4 bang bang phase detector do di u u v u dd r d sel0 outchp vcco vccd vcca v3v3a v3v3 vee vcc_cdr lock ckout
function details the clock and data recovery (cdr) part of the gd14526 consists of: u an input amplifier u a voltage controlled oscillator (vco) u a phase detector (pd) u a loop filter circuit u a charge pump u a phase-frequency comparator (pfc) the charge pump performs the transfor- mation between the digital error signal of the phase detector and the voltage con- trolling the oscillator. the true phase-frequency comparator is used when acquiring lock and a lock detection circuit determines whether or not the pll is locked onto incoming data. a selectable divide-by-4 (den input) fol- lowing the on-chip oscillator provides two tuning ranges for the vco: 1200 - 1500 mhz (den = ?0?) 300 - 375 mhz (den = ?1?). the phase detector the phase detector (pd) used in the cdr is designed to give minimum static phase error of the pll. it is of the true digital type (bang-bang), producing a bi- nary output. it samples data prior to, in the vicinity of and after any potential bit transition. when a transition has oc- curred the value of the sample in the vi- cinity of the transition tells whether the vco clock leads or lags the incoming data and the pd produces a binary out- put accordingly. hence the pll is con- trolled by the bit transition point. the output of the pd is binary with three values indicating whether the vco must go up or down in frequency, if a bit transition has occurred, or stay, if not (consecutive ?1"s or ?0"s). this informa- tion is fed into the charge pump, which transfers it into three output levels: u sinking current u sourcing current u tristating the output. the output of the charge pump is inte- grated and filtered outside the chip by two resistors and a capacitor. the initial values have been determined to 27 s and 1 f f, with a resistor of 330 s con- nected in series with the charge pump output to decrease loop-gain. these val- ues can be altered to achieve the optimal characteristics for the application. the phase frequency comparator the phase-frequency comparator (pfc) ensures predictable lock up condi- tions for the gd14526. it is used during acquisition, and serves as means to pull the vco into the range of the data rate where the phase detector is capable of acquiring lock. the detector is of the set-reset type, comparing the edges of the vco frequency divided by 20 and the local reference clock (refck). the output of the pfc tells whether the vco must be adjusted up or down, proportional to the phase error between the clocks. this information is fed into the charge pump, which provides sinking or sourcing current for the loop filter capaci- tor. figure 1. lock detect scheme. the refck input is a single ended ttl input with a 1.4 v threshold. the lock detect circuit the lock detect circuit (ldc) is the guaranty of a fast and reliable lock up. it monitors the difference between the di- vided vco clock and the reference clock (refck) when the pll is locked onto the incoming data by the pd. if the differ- ence between the divided vco clock and the clock reference is greater than 500 ppm, the ldc considers the pll to be out of lock and switches to the pfc to pull the vco frequency into the data rate range. when ldc has monitored the vco fre- quency to be within the data rate range over a period corresponding to 500 ppm, it switches back to the pd and starts acquiring lock onto data. this way the recovered output clock is always kept within the 500 ppm, regardless of the serial data line is active or not. power down mode gd14526 has been designed with a power down mode to allow data to by- pass the re-timer. this can be useful in applications with multiple data rates. please note that even in power down mode the appropriate supply voltages should always be applied to the v 3v3 ,v cc and v ee pins: cdr (v cc_cdr = +5v): re-timed repeater with cdr, vco and lock detect active. bypass (v cc_cdr = 0v): asynchron repeater with only serial input and output active. v cc_cdr requires approximately 1 ma and can be switched by 5v cmos logic. data sheet rev. 02 gd14526 page 2
applications figure 2. standard input configuration figure 3. pecl input configuration figure 4. loop filter note: decoupling should be made from vcc to vee plane. use 33 nf chip capacitors close to package pins. figure 5. differential, pecl driver figure 6. dual 75 w cable driver data sheet rev. 02 gd14526 page 3 sip sip to cable sin 75 100n 100n 200n 37 10k 10k sin 3v vee vee sip sip in in sin 50 50 10k 10k sin 3v vee 3v sop son cip vcc vcc vcc vee vee 4k 0.5ma 50 50 50 100 2k sop son cip vcc vcc vcc vee vee 1k 1.0ma 75 75 2k vcca vctl 330 27 1f m ouchp
pin list mnemonic: pin no.: pin type: description: sip sin 14, 15 12, 13 analog in serial data input (differential). compatible with pecl levels. loop-back termination: each input is connected to two pins, one for input and the other for the termination resistor. see figures on page 3. sop son 9, 10 6,7 open collector differential serial data output. high speed open collector outputs to be used with 75 s cable or 50 s termination for optical trans- mitter. see figures on page 3. cip 16 analog in dc-current control input for sop, son: 1 ma current into cip generates 25 ma bias for the differential output stage. maximum setting is for 36 ma output stage bias. if cip is pulled low, the out- put stage will turn off. ckout 28 ttl out regenerated output clock, vco frequency divided by 20. refck 23 ttl in reference clock input with frequency equal to data rate divided by 20. sel0 24 ttl in lock detect range select ?0? 2000 ppm ?1" 500 ppm sel1 17 ttl in pll override ?0? pfc always used ?1? lock detect circuit selects pfc or pd lock 22 ttl out cdr lock alarm output. when low, the divided vco frequency deviates more than 500/2000 ppm from refck. vctl 18 analog in vco control voltage input. ouchp 21 analog out charge pump output providing sink or source current for the inte- grating capacitor in the external loop filter. see figure 4 on page 3. den 25 ttl in control of vco divide by 4 ?0? disable divide by 4 ?1? enable divide by 4 vcc_cdr 26 pwr ctl power down of re-timer. ?0? power down (asyncr. repeater) ?1? enable re-timer v3v3 3, 30, 32, 39 pwr +3.3 v power for data path. v3v3a 20 pwr +3.3 v power for pfc and cdr. vcca 19 pwr +5 v power for vco. vccd 5, 8 pwr +5 v power for cable driver. vcco 4, 29, 38 pwr +5 v power for ttl i/o. vee 1, 2, 11, 27, 31, 33, 34, 35, 36, 37, 40 pwr 0 v power. data sheet rev. 02 gd14526 page 4
package pinout figure 7. package 40 pin mlc - top view data sheet rev. 02 gd14526 page 5 5 4 3 2 1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 vccd vcco v3v3 vee vee vee v3v3 vcco vee vee vee vee vee v3v3 vee v3v3 vcco ckout vee vcc_cdr den sel0 refck lock ouchp v3v3 vcca vctl sel1 cip sip sip sin sin vee sop sop vccd son son
maximum ratings these are the limits beyond which the component may be damaged. symbol: characteristic: conditions: min.: typ.: max.: unit: v 3v3 ,v cc positive supply v ee -0.5 7 v v i max, cip input voltage for cip v ee -0.5 v cc +0.5 v i i max, cip input current for cip -1.0 3.0 ma v o max output voltage v ee -0.5 v cc +0.5 v i o max output current 40 ma v i max input voltage v ee -0.5 v cc +0.5 v i i max input current -1.0 1.0 ma t o operating temperature junction -40 +125 o c t s storage temperature -65 +175 o c note 1: temperature range specify only reliability regarding damage. performance is only tested and quaranteed for the t case as given below. dc characteristics t case =0 o cto70 o c, 2 j-c =9 e c/w. appropriate heat sinking is required. all voltages in the table are referred to v ee . symbol: characteristic: conditions: min.: typ.: max.: unit: v cc v cca v cco 5 v supply voltage 4.75 5.00 5.25 v i cc total supply current v cc ,v cca ,v cco 165 ma v 3v3 3.3 v supply voltage 3.1 3.3 3.5 v i 3v3 total supply current v 3v3 85 ma pd power dissipation 1100 mw v c sip/sin sip/sin data common mode voltage v cc -2.0 v cc -0.5 v v i sip/sin sip/sin data minimum input voltage sip/sin data maximum input voltage note 1 200 400 1000 mv p-p mv p-p v iih ttl ttl input hi voltage 2.0 4.0 v v iil ttl ttl input lo voltage 0.8 v i ih ttl ttl input hi current v ih max 500 a i il ttl ttl input lo current v il min -500 a v oh ttl ttl output hi voltage note 2 2.4 v v ol ttl ttl output lo voltage note 2 0.5 v i oh sop/son open collector output hi sink current note 3 -20 -25 -36 ma i ol sop/son open collector output lo sink current note 3 -0.5 ma v vctl vco control voltage i vctl <30a 0.5 v cc -1.5 v i oh chp ouchp source current (dc steady) note 4 500 1000 a i ol chp ouchp sink current (dc steady) note 4 -500 -1000 a note 1: data eye diagram in accordance with smpte292, terminated via loop-through to 75 w . note 2: r load = 500 w to 1.4 v. note 3: r load =50 w to v cc . current into cip =1 ma. output logic level ?1" corresponds to lo sink current into output. note 4: output terminated to 2.5 v during test. data sheet rev. 02 gd14526 page 6
ac characteristics t case =0 o cto70 o c v cc = 5.0 v, v 3v3 = 3.3 v symbol: characteristic: conditions: min.: typ.: max.: unit: j tol jitter tolerance 10h z package outline figure 8. package 40 pin mlc - all dimensions are in inch. ordering information to order, please specify as shown below: product name: package type: case temperature range: option: GD14526-40BA 40 pin mlc 0..70 o c gd14526, data sheet rev. 02 - date: 10 february 1999 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark telephone : +45 4492 6100 telefax : +45 4492 5900 e-mail : sales@giga.dk web site : http://www.giga.dk please check our internet web site for latest version of this data sheet. distributor: copyright ? 1999 giga a/s all rights reserved note 1: leads are hot dip soldered before cutting bottom view top view side view note 2: coplanarity of leads > 0.008" pin 1
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