www.siliconstandard.com 1 of 9 SS6734G 1/15/2005 rev.2.10 300ma low dropout linear regulator features low dropout voltage of 470mv at an output current of 300ma (3.0v output versio n). guaranteed 300ma output current. low ground current of 55ma . output voltage accuracy of 2% at 1.8v/ 2.0v /2.5v /2.7v/ 3.0v/ 3.3v/ 3.5v/ 3.7v/ 3.8v/ 5.0v/5.2v only needs 1mf output capacitor for stability. current and thermal limiting. applications cd-rom drivers. lan cards. microprocessors. dram modules. wir eless communication systems. battery powered systems. description the SS6734G is a 3-pin low-dropout linear regulator with superior characteristics, which include zero base current loss, very low drop- out voltage, and output voltage accuracy of 2%. typical ground current remains approximately 55ma, for loads ranging from zero to maximum. dropout voltage at an output current of 300ma is exceptionally low. built-in output current limiting and thermal limiting provide maximum protection against fault conditions. the SS6734G is available in sot-23-3, sot-89, and to-92 packages. typical application circuit + + ss6734 g 1 mf c out v out vout gnd vin 1 m f c in v in low dropout linear regulator (c in and c out are electrolytic capacitor) pb-free lead finish (second-level interconnect).
www.siliconstandard.com 2 of 9 SS6734G 1/15/2005 rev.2.10 ordering information pin configuration sot-89 (gxt) top view 1: vout 2. gnd 3. vin sot-89 (gxa) top view 1: gnd 2. vin 3. vout t o-92 (gzt) top view 1: gnd 2. vin 3. vout to-92 (gzl) top view 1: vin 2. gnd 3. vout 1 2 3 1 2 3 1 2 3 1 2 3 packing: tr: tape and reel package type: u: sot-23-3 xa: sot-89 xt: sot-89 zt: t o-92 zl: t o-92 g: commercial, pb-free lead finish output v output voltage: 18: 1.8v 20 : 2.0v 25 : 2.5v 27 : 2.7v 30 : 3.0v 33 : 3.3v 35 : 3.5v 37 : 3.7v 38 : 3.8v 50 : 5.0v 52 : 5.2v ss6734-xx gxx xx example: ss6734-18gxatr 1.8v version, in sot-89 package, with pb-free lead finish, shipped on tape and reel. sot-23 (gu) 1: gnd 2: vout 3: vin 3 1 2 sot-23 marking part no. gu part no. gu ss6734-18gu cd18p ss6734-35gu cd35p ss6734-20gu cd20p ss6734-37gu cd37p ss6734-25gu cd25p ss6734-38gu cd38p ss6734-27gu cd27p ss6734-50gu cd50p ss6734-30gu cd30p ss6734-52gu cd52p ss6734-33gu cd33p
www.siliconstandard.com 3 of 9 SS6734G 1/15/2005 rev.2.10 sot-89 marking part no. gxa part no. gxt ss6734-18 gxa ca18p ss6734-18 gxt cb18p ss6734-20 gxa ca20p ss6734-20 gxt cb20p ss6734-25 gxa ca25p ss6734-25 gxt cb25p ss6734-27 gxa ca27p ss6734-27 gxt cb27p ss6734-30 gxa ca30p ss6734-30 gxt cb30p ss6734-33 gxa ca33p ss6734-33 gxt cb33p ss6734-35 gxa ca35p ss6734-35 gxt cb35p ss6734-37 gxa ca37p ss6734-37 gxt cb37p ss6734-38 gxa ca38p ss6734-38 gxt cb38p ss6734-50 gxa ca50p ss6734-50 gxt cb50p ss6734-52 gxa ca52p ss6734-52 gxt cb52p absolute maximum ratings input supply voltage -0.3 ~12v operating temperature range -40c~ 85c storage temperature range -65c~150c maximum junction temperature 125c lead temperature (soldering) 10 sec. 260c thermal resistance junction to ambient sot-89 package 160c/w (assumes no ambient airflow, no heatsink) to-92 package 150c/w sot-23 package 180
www.siliconstandard.com 4 of 9 SS6734G 1/15/2005 rev.2.10 electrical characteristics (t a =25c, c in =1mf, c out =1mf, unless otherwise sp e cified.) (note1 ) parameter test conditions min. typ. max. unit no load output voltage ss6 7 3 4- 5 2 ss6 7 3 4- 5 0 ss6 7 3 4- 3 8 ss6 7 3 4- 3 7 ss6 7 3 4- 3 5 ss6 7 3 4- 3 3 ss6 7 3 4- 3 0 ss6 7 3 4- 2 7 ss6 7 3 4- 2 5 ss6 7 3 4- 2 0 ss6 7 3 4- 1 8 v in =5.5~12v v in =5.5~12v v in =4.1~12v v in =4.0~12v v in =4.0~12v v in =4.0~12v v in =4.0~12v v in =4.0~12v v in =4.0~12v v in =4.0~12v v in =4.0~12v 5.100 4.900 3.725 3.625 3.430 3.235 2.940 2.646 2.450 1.960 1.764 5.200 5.000 3.800 3.700 3.500 3.300 3.000 2.700 2.500 2.000 1.800 5.300 5.100 3.875 3.775 3.570 3.365 3.060 2.754 2.550 2.040 1.836 v output voltage te m p erature coe f ficie n t (note 2) 50 ppm/ c line regulation i l = 1ma, 1.4v d v out d 3.2v 3.3v d v out d 5.2v v in =4v~12v v in =5.5v~12v 3 3 10 10 mv load regulation (note 3) i l =0.1~300ma 1.4v d v out d 3.9v 4.0v d v out d 5.2v v in =5v v in =7v 7 15 20 40 mv current limit (note 4) v in =7v, v out =0v 300 ma dropout voltage (note 5) i l =300ma 4.0v d v out d 5.2v 3.0v d v out d 3.9v 2.5v d v out d 2.9v 2.0v d v out d 2.4v 1.4v d v out d 1.9v 400 470 570 800 1260 mv ground current i o =0.1ma~i max 1.4v d v out d 3.9v 4.0v d v out d 5.2v v in =5~12v v in =7~12v 55 55 80 80 ma note 1: specifications are guaranteed by statistical qu ality control (s q c ), no t by 1 00 % pr o d u ction test ing , o ver the op e rat i ng temp e r at u r e r a ng e fr o m -4 0 c to 8 5 c. note 2: guaranteed by design. note 3: regulation is measured at constant junction te mperature, using pulse testing with a low on time. note 4: current limit is measured by pulsing a short time. note 5: dropout voltage is defined as the input to output differential at which the output voltage drops 100mv.
www.siliconstandard.com 5 of 9 SS6734G 1/15/2005 rev.2.10 typical performance characteristics 5.00 5.05 5.10 5.15 5.20 5.25 5.30 5.35 5.40 fig. 1 v out vs. temperature v out (v) temperature ( c) -50 -30 -10 10 30 50 70 90 ss6 734-52 fig. 2 v out vs. temperature v out (v) -50 -30 -10 10 30 50 70 90 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 temperature ( c) ss 6 734-33 fig. 3 ground current vs. temperature -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 38 40 42 44 46 48 50 i load = 0ma i load =100ma i load =300ma ground current ( m a) temperature ( c) ss 6 734-52 fig. 4 ground current vs. temperature ground current ( m a) temperature ( c) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 38 40 42 44 46 48 i load = 0ma i load =100ma i load =300ma ss 6 734-33 fig. 5 ground current vs. v in ground current ( m a) v in (v) 0 1 2 3 4 5 6 7 8 9 10 11 12 0 10 20 30 40 50 60 ss 6 734-52 fig. 6 ground current vs. v in ground current ( m a) v in (v) 0 1 2 3 4 5 6 7 8 9 10 11 12 0 10 20 30 40 50 60 ss 6 734-33
www.siliconstandard.com 6 of 9 SS6734G 1/15/2005 rev.2.10 typical performance characteristics (continued) fig. 7 v drop vs. i load v drop (mv) i load (ma) 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400 450 500 t=-40 c t= 20 c t= 50 c t= 80 c ss 6 734-52 fig. 8 v drop vs. i load v drop (mv) i load (ma) 0 50 100 150 200 250 300 350 400 0 100 200 300 400 500 600 t= 20 c t=-40 c t= 50 c t= 80 c ss 6 734-33 fig. 9 current limit vs. temperature -40 -20 0 20 40 60 80 400 410 420 430 440 450 460 470 480 490 500 v in = 7v v in = 8v v in = 6v v in = 5v crrent limit (ma) temperature ( q c) ss 6 734
www.siliconstandard.com 7 of 9 SS6734G 1/15/2005 rev.2.10 block diagram 1.235v reference gnd vout vin error a mp + - thermal shutdown - + current limiting pin descriptions vout pin - output pin. gn d pin - powe r gn d. vin pin - powe r suppl y input.
www.siliconstandard.com 8 of 9 SS6734G 1/15/2005 rev.2.10 physical dimensions (unit: mm) sot-23 (gu) symbol min max a 0.95 1.45 a1 0.05 0.15 a2 0.90 1.30 b 0.30 0.50 c 0.08 0.22 d 2.80 3.00 e 2.60 3.00 e1 1.50 1.70 e 0.95 bsc e1 1.90 bsc l 0.30 0.60 l1 0.60 ref e d e1 e1 e a1 a a 2 b 0.25 l1 l ? 8 ? sot-89 (gxx) symbol min max a 1.40 1.60 b 0.44 0.56 b1 0.36 0.48 c 0.35 0.44 d 4.40 4.60 d1 1.50 1.83 e 2.29 2.60 e 1.50 bsc e1 3.00 bsc h 3.94 4.25 b1 e h e1 d d1 a c l e b l 0.89 1.20 pb-free lead finish (second-level interconnect).
information furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 9 of 9 SS6734G 1/15/2005 rev.2.10 to-92 (gzx) symbol min max a 4.32 5.33 b 0.36 0.47 d 4.45 5.20 e 3.18 4.19 e 2.42 2.66 e1 1.15 1.39 j 3.43 - l 12.70 - s 2.03 2.66 a e1 e l d s e j b
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