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preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. november 2006 rev 3 1/70 1 vl6524 VS6524 vga single-chip camera module features 640h x 480v active pixels 3.6 m pixel size, 1/6 inch optical format rgb bayer color filter array integrated 10-bit adc integrated digital image processing functions, including defect correction, lens shading correction, demosaicing, sharpening, gamma correction and color space conversion embedded camera controller for automatic exposure control, automatic white balance control, black level compensation, 50/60 hz flicker cancellation and flashgun support up to 30 fps progressive scan, flexible subsampling and cropping modes itu-r bt.656-4 yuv (ycbcr) 4:2:2 with embedded syncs, rgb 565, rgb 444 or bayer 10-bit output formats viewlive feature allows different sizes, formats and reconstruction settings to be applied to alternate frames 8-bit parallel video interface, horizontal and vertical syncs, 24 mhz clock two-wire serial control interface (i 2 c) on-chip pll, 6.5 to 26 mhz clock input analog power supply, from 2.4v to 3.0v separate i/o power supply, 1.8v or 2.8v levels 3.3v tolerant i/o for power supply > 2.7v integrated power management with power switch, automatic power-on reset and power- safe pins low power consumption, ultra low standby current dual-element plastic lens, f# 2.8, ~59 dfov (VS6524) description the vl6524/VS6524 is a general purpose vga resolution cmos color digital camera featuring low size and low power consumption. this complete camera module is ready to connect to camera enabled baseband processors, back-end ic devices or pda engines. applications mobile phone videophone video surveillance medical machine vision toys pda biometry bar code reader lighting control smop lga www.st.com
contents vl6524/VS6524 2/70 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 electrical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 video pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 microprocessor functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 system clock division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 pixel clock (pclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 pclk gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 output frame size control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.1 cropping module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.2 subsampling module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2.1 horizontal mirror and vertical flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 viewlive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 video pipe setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 output data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 yuv 4:2:2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 rgb and bayer data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2.1 manipulation of rgb data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
vl6524/VS6524 contents 3/70 7.2.2 dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 data synchronization methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 embedded codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.1 prevention of false synchronization codes . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.2 mode 1(itu656 compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.2 vsync and hsync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2.1 horizontal synchronization signal (hsync) . . . . . . . . . . . . . . . . . . . . . 29 8.2.2 vertical synchronization (vsync) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.1 initial power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2 minimum startup command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 host communication - i2c control interface . . . . . . . . . . . . . . . . . . . . . 32 v2w protocol layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 detailed overview of the message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 start (s) and stop (p) conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 index space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 types of messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 random location, single data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 current location, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 random location, single data read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 multiple location write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 multiple location read stating from the current location . . . . . . . . . . . . . . . . . . . . . 40 11 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 low level control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 device parameters [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 mode status [read only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 runmodecontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 clock manager input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
contents vl6524/VS6524 4/70 power management control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 pipe setup bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 pipe setup bank0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 pipe setup bank1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 view live control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 white balance control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 exposure control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 exposure status (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 exposure algorithm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 flashgun control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 flicker frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 defect correction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 sharpening control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 fade to black damper control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 dither control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 output formatter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12 optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1 average sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2 spectral response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.4.1 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.4.2 chip enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.4.3 i2c slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.4.4 parallel data interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.5 esd handling characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.1 smop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.2 lga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
vl6524/VS6524 contents 5/70 15 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
list of tables vl6524/VS6524 6/70 list of tables table 1. vl6524/VS6524 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. subsampled image sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 3. itu656 embedded synchronization code definition (even frames). . . . . . . . . . . . . . . . . . . 27 table 4. itu656 embedded synchronization code definition (odd frames). . . . . . . . . . . . . . . . . . . . 28 table 5. mode 2 - embedded synchronization code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 7. low-level control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 8. device parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 9. mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 10. mode status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 11. runmodecontrol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12. clock manager input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 13. power management control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 14. frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 15. pipe setup bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 16. pipe setup bank0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 17. pipe setup bank1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 18. view live control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 19. white balance control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 20. exposure control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 21. exposure status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 22. exposure algorithm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 23. flashgun control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 24. flicker frequency control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 25. defect correction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. sharpening control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 27. fade to black damper control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 28. dither control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 29. output formatter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 30. optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 31. VS6524 average sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 32. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 33. supply specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 34. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 35. typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 36. external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 37. serial interface voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 38. timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 39. parallel data interface timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 40. esd handling characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 41. lga package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 42. vl6524 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 43. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 44. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
vl6524/VS6524 list of figures 7/70 list of figures figure 1. vl6524/VS6524 simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. state machine at power -up and user mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. frame output format against framerate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. vga 30fps output frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. crop controls ( table 16: pipe setup bank0 control ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. crop 30fps output frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. viewlive frame output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. standard y cb cr data order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. y cb cr data swapping options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. rgb and bayer data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. itu656 frame structure with even codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. mode 2 frame structure (vga example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. hsync timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16. vsync timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 17. write message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 18. read message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19. detailed overview of message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 20. device addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 21. sda data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 22. start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 23. data acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 24. internal register index space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 25. random location, single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 26. current location, single read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 27. random location, single data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 28. multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 29. multiple location read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 30. multiple location read starting from a random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 31. VS6524 spectral response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 32. voltage level specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 33. timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 34. sda/scl rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 35. parallel data output video timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 36. VS6524q06j outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 37. VS6524q06j socket assembly outline drawing for information only . . . . . . . . . . . . . . . . . 65 figure 38. vl6524qomh outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
overview vl6524/VS6524 8/70 1 overview 1.1 description the vl6524/VS6524 is a vga resolution cmos imaging device designed for low power systems. video data is output from the VS6524 over an 8-bit parallel bus in rgb, ycbcr or bayer formats and is controlled via an i2c interface. the vl6524/VS6524 requires an analogue power supply of between 2.4 v to 3.0 v and a digital supply of either 1.8 v or 2.8 v (dependant on interface levels required). an input clock is required in the range 6.5 mhz to 26 mhz. the device contains an embedded video processor and delivers fully color processed images at up to 30 frames per second. the video processor integrates a wide range of image enhancement functions, designed to ensure high image quality, these include: automatic exposure control automatic white balance lens shading compensation defect correction algorithms demosaic (bayer to rgb conversion) matrix compensation sharpening gamma correction flicker cancellation
vl6524/VS6524 electrical interface 9/70 2 electrical interface the device has 20 electrical connections as listed in ta b l e 1 . the physical orientation of the pins on the device is shown in figure 36 . table 1. vl6524/VS6524 signal description pad socket pad name i/o description 1 gnd pwr analogue ground 2 d02 out data output d2 3 d03 out data output d3 4 hsync out horizontal synchronization output 5 vsync out vertical synchronization output 6 d07 out data output d7 7 d06 out data output d6 8 d05 out data output d5 9 d04 out data output d4 10 clk in clock input - 6.5mhz to 26 mhz 11 gnd pwr digital ground 12 fso out flash output 13 ce in chip enable signal active high 14 scl in i2c clock input 15 sda i/o i2c data line 16 avdd pwr analogue supply 2.4 v to 3.0 v 17 d01 out data output d1 18 d00 out data output d0 19 pclk out pixel qualification clock 20 vdd pwr digital supply 1.8 v or 2.8 v
system architecture vl6524/VS6524 10/70 3 system architecture the vl6524/VS6524 consists of the following main blocks: vga-sized pixel array video timing generator video pipe statistics gathering unit clock generator microprocessor a simplified block diagram is shown in figure 1 . figure 1. vl6524/VS6524 simplified block diagram 3.1 operation a video timing generator controls a vga-sized pixel array to produce raw images at up to 30 frames per second. the analogue pixel information is digitized and passed into the video pipe. the video pipe contains a number of different functions (explained in detail later). at the end of the video pipe data is output to the host system over an 8-bit parallel interface along with qualification signals. microprocessor sda scl ce avdd hsync pclk d[0:7] clk vsync clock generator i2c statistics gathering video timing generator reset vreg vdd i2c interface fso gnd gnd vga pixel array video pipe
vl6524/VS6524 system architecture 11/70 the whole system is controlled by an embedded microprocessor that is running firmware stored in an internal rom. the external host communicates with this microprocessor over an i2c interface. the microprocessor does not handle the video data itself but is able to control all the functions within the video pipe. real-time information about the video data is gathered by a statistics engine and is available to the microprocessor. the processor uses this information to perform real-time image control tasks such as automatic exposure control. 3.1.1 video pipe the main functions contained within the vl6524/VS6524 video processing pipe are as follows. gain and offset: this function is used to apply gain and offset to data coming from the sensor array. the required gain and offset values result from the automatic exposure and white balance functions from the microprocessor. anti-vignette: this function is used to compensate for the radial roll-off in intensity caused by the lens. by default the anti-vignette setting matches the lens used in this module and does not need to be adjusted. crop: this function allows the user to select an arbitrary window of interest (woi) from the vga-sized pixel array. it is fully accessible to the user. defect correction: this function runs a defect correction filter over the data in order to remove defects from the final output. this function has been optimized to attain the minimum level of defects from the system and does not need to be adjusted. demosaic: this module performs an interpolation on the bayer data from the sensor array to produce an rgb image. it also applies an anti-alias filter. subsampler: this module allows the image to be sub-sampled in the x and y directions by 2, 3, 4, 5 or 6. matrix: this function performs a color-space conversion from the sensor rgb data to standard rgb color space. sharpening: this module increases the high frequency content of the image in order to compensate for the low-pass filtering effects of the previous modules. gamma: this module applies a programmable gain curve to the output data. it is user adjustable. yuv conversion: this module performs color space conversion from rgb to yuv. it is used to control the contrast and color saturation of the output image as well as the fade to black feature. dither: this module is used to reduce the contouring effect seen in rgb images with truncated data. output formatter: this module controls the embedded codes which are inserted into the data stream to allow the host system to synchronize with the output data. it also controls the optional hsync and vsync output signals.
system architecture vl6524/VS6524 12/70 3.2 microprocessor functions the microprocessor inside the vl6524/VS6524 performs the following tasks: host communication: handles the i2c communication with the host processor. video pipe configuration : configures the video pipe modules to produce the output required by the host. automatic exposure control : in normal operation the vl6524/VS6524 determines the appropriate exposure settings for a particular scene and outputs correctly exposed images. flicker cancellation: the 50/60hz flicker frequency present in the lighting (due to fluorescent lighting) can be cancelled by the system. automatic white balance: the microprocessor adjusts the gains applied to the individual color channels in order to achieve a correctly color balanced image. dark calibration: the microprocessor uses information from special dark lines within the pixel array to apply an offset to the video data and ensure a consistent ?black? level. active noise management: the microprocessor is able to modify certain video pipe functions according to the current exposure settings determined by the automatic exposure controller. the main purpose of this is to improve the noise level in the system under low lighting conditions. functions which ?strength? is reduced under low lighting conditions (e.g. sharpening) are controlled by ?dampers?. functions which ?strength? is increased under low lighting conditions are controlled by ?promoters?. the fade to black operation is also controlled by the microprocessor
vl6524/VS6524 operational modes 13/70 4 operational modes vl6524/VS6524 has a number of operational modes. the standby mode is entered and exited by driving the hardware ce signal. transitions between all other modes are initiated by i2c transactions from the host system or automatically after time-outs. figure 2. state machine at power -up and user mode transitions power down/up: the power down state is entered from all other modes when ce is pulled low or the supplies are removed. during the power-down state (ce = logic 0) the internal digital supply of the vl6524/VS6524 is shut down by an internal switch mechanism. this method allows a very low power-down current value. the device input / outputs are fail-safe, and consequently can be considered high impedance. supplies off standby power-down ce pin low ce pin pause mode supplies turned-off supplies turned on & ce pin low supplies turned off 1 stop mode flashgun mode run mode note: 1 it is possible to enter any of the user modes direct from standby via an i2c command high state machine at power-up i 2 c controlled user mode transitions
operational modes vl6524/VS6524 14/70 during the power-up sequence (ce = logic 1) the digital supplies must be on and stable. the internal digital supply of the vl6524/VS6524 is enabled by an internal switch mechanism. all internal registers are reset to default values by an internal power on reset cell. figure 3. power up sequence standby mode: the vl6524/VS6524 enters standby mode when the ce pin on the device is pulled high. power consumption is very low, most clocks inside the device are switched off. in this state i2c communication is possible when clk is present and when the microprocessor is enabled by writing the value 0x06 to the microenable register 0xc003 ( ta b l e 7 ). all registers are reset to their default values. the device i/o pins have a very high- impedance. note: on exit from standby mode, the vl6524/VS6524 is in a transient mode called uninitialised, this mode is not a user mode. stop mode: this is a low power mode. the analogue section of the vl6524/VS6524 is switched off and all registers are accessed over the i2c interface. a run command received in this state automatically sets a transition through the pause state to the run mode. pause mode: in this mode all vl6524/VS6524 clocks are running and all registers are accessible but no data is output from the device. the device is ready to start streaming but is halted. this mode is used to set up the required output format before outputting any data. note: the powermanagement register btimetopowerdown can be adjusted in pause mode but has no effect until the next run to pause transition ( ta b l e 1 3 ). run mode: this is the fully operational mode. ce clk avdd (2.8v) vdd (1.8v/2.8v) sda scl t1 t2 t3 t4 t1 >= 0ns t2 >= 0ns t3 >= 0ns t4 >= 25ms constraints: t5 low level command:enable clocks setup commands t5 >= 2ms standby power down
vl6524/VS6524 operational modes 15/70 viewlive: this feature allows different sizes, formats and reconstruction settings to be applied to alternate frames of data, while in run mode. flashgun mode: in flashgun mode, the array is configured for use with an external flashgun. a flash is triggered and a single frame of data is output and the device automatically switches to pause mode. mode transitions transitions between operating modes are normally controlled by the host by writing to the mode control register. some transitions can occur automatically after a time out. if there is no activity in the pause state then an automatic transition to the stop state occurs. this functionality is controlled by the power management control register. writing 0xff disables the automatic transition to stop mode.
clock control vl6524/VS6524 16/70 5 clock control 5.1 input clock the vl6524/VS6524 contains an internal pll allowing it to produce accurate frame rates from a wide range of input clock frequencies. the allowable input range is from 6.5 mhz to 26 mhz. the input clock frequency must be programmed in the uwextclockfreqnum (msb) , uwextclockfreqnum (lsb) and bextclockfreqden registers ( ta b l e 1 2 ). to program an input frequency of 6.5 mhz, the numerator can be set to 13 and the denominator to 2. the default input frequency is 12 mhz. 5.2 system clock division it is possible to set an overall system clock division of 2 in the benableglobalsystemclockdivision register ( ta bl e 1 2 ). this results in a pclk of 12mhz and a maximum frame rate of 15fps vga. 5.3 pixel clock (pclk) all data output from the vl6524/VS6524 is qualified by the pclk output. the pclk frequency is 24 mhz (equivalent to a 12 mhz pixel rate as each pixel is represented by 2 bytes of data). for frame rates less than 30 fps the pclk frequency is not reduced, instead additional interframe lines are added into the output data stream. figure 4. frame output format against framerate interframe blanking interframe blanking 1/30 sec 1/30 sec 1/30 sec interframe blanking 1/15 sec 1/15 sec frame output 15fps frame output 30fps interline blanking interline blanking active video active video interline blanking active video interline blanking active video interline blanking active video
vl6524/VS6524 clock control 17/70 similarly when using sub-sampled output modes the pclk frequency is not reduced but instead pairs of pclks are 'dropped', see section 6.1.2: subsampling module for details. the pclk edge used to qualify the output data is fully programmable. it is also possible to program the state of the pclk line (high or low) for the times when it is inactive. 5.4 pclk gating by default the pclk output from the vl6524/VS6524 is not continuous. the pclk qualifies all video data (and embedded codes if selected) on each video line and each interframe line but does not qualify the interline blanking data. in non-subsampled modes the pclk is continuous during the video data output. the operation of the pclk can be controlled using the bpclksetup register ( ta b l e 2 9 ).
output frame size control vl6524/VS6524 18/70 6 output frame size control 6.1 frame format an output frame consists of a number of active lines and a number of interframe lines. each line consists of embedded line codes (if selected), active pixel data and interline blank data. note that by default the interline blanking data is not qualified by the pclk and therefore is not captured by the host system. the default 30fps vga output frame is shown in figure 5 . figure 5. vga 30fps output frame if embedded codes are enabled then 8 additional clocks are required in every line to qualify the codes and 8 fewer interline clock are output leaving the total constant at 1460 clocks per line. by default the pclk output does not qualify the line blanking data and so each line contains only 1280 clocks (or 1288 if embedded codes are enabled). the values which are output during line and frame blanking are an alternating pattern of 0x10 and 0x80 by default. these values can be changed by writing to the blankdata_msb and blankdata_lsb registers in the output formatter control bank. 6.1.1 cropping module the vl6524/VS6524 contains a cropping module which can be used to define a window of interest within the full vga array size. the user can set a start location and the required output size. figure 6 shows the example with pipe setup bank0. 16 interframe blanking lines(0x10/0x80) 480 lines active video line blanking (0x10/0x80) 1460 pclks 37 interframe blanking lines (0x10/0x80) 1280 pclks (640 by 480 pixels) 553 lines
vl6524/VS6524 output frame size control 19/70 figure 6. crop controls ( table 16: pipe setup bank0 control ) complete lines which fall outside the window of interest are replaced in the output data frame with lines of blanking data thus the overall frame length is not reduced. the portion of the output line which contains video data is reduced in length to contain only those pixels defined by the window of interest. however the overall line length remains unchanged as the number of interline clocks increases by the same amount. figure 7. crop 30fps output frame uwcrophstartmsb0 uwcrophstartlsb0 , uwcropvstartmsb0 uwcropvstartlsb0 uwcrophsizemsb0 uwcrophsizelsb0 uwcropvsizemsb0 uwcropvsizelsb0 cropped roi sensor array horizontal size = 640 sensor array vertical size = 480 ffov vga array interframe blanking lines cropvsize lines line blanking 1460 pclks interframe blanking lines 2x crophsize pclks (crophsize by 553 lines cropvsize pixels)
output frame size control vl6524/VS6524 20/70 6.1.2 subsampling module the vl6524/VS6524 has a built in sub-sampler which can divide the image by 1, 2, 3, 4, 5, or 6. using the sub-sampler gives output images with reduced resolution but the same field of view as the full vga image or the region of interest defined in the cropping module. ta b l e 2 lists the available image sizes. subsampled images are produced by ?dropping? pclks so that only certain pixels are qualified in the output data stream. the figure below indicates a portion of the pclk waveform for vga and qvga images. the effect of this is that the time taken to readout one line of the image remains constant in all subsampled modes - it is just the number of clocks that changes. figure 8. pclk waveform in subsampled modes it is possible to use the crop module and the sub-sampler together to achieve almost any required image size. when using the crop and subsampling functions together then the number of lines in a frame must be an integer multiple of the subsample ratio. 6.2 frame rate control the vl6524/VS6524 features an extremely flexible frame rate controller. using registers uwdesiredframe rate_num (msb) , uwdesiredframe rate_num (lsb) and bdesiredframerate_ den any desired frame rate between 1 and 30 fps can be selected (see table 14: frame rate control for register description). to program a required frame rate of 7.5 fps the numerator can be set to 15 and the denominator to 2. the default frame rate is 30 fps. slower frame rates are achieved by adding interframe lines. this results in a longer frame period and therefore a longer period over which integration is possible. due to the longer table 2. subsampled image sizes subsample ratio image format image dimensions 1 (default) vga 640 by 480 2qvga320 by 240 3 - 213 by 160 4 qqvga 160 by 120 5 sqcif 128 by 96 6 - 106 by 80 d0 d3 d4 d[0:7] vga qvga pclk d1 d2 d5 pixel n pixel n+2 pixel n+1
vl6524/VS6524 output frame size control 21/70 integration time available slower frame rates have improved performance in low light conditions. 6.2.1 horizontal mirror and vertical flip the image data output from the vl6524/VS6524 can be mirrored horizontally or flipped vertically (or both). these functions are available in the pipe setup bank0 control register bank. 6.3 viewlive operation viewlive is an option which allows different size, format and image settings to be applied to alternate frames of the output data. the controls for viewlive function are found in the view live control register bank where the fenable register allows the host to enable or disable the function and the initalpipesetupbank register selects which pipe setup bank is output first (see ta bl e 1 8 : view live control for register description). video pipe setup the key controls for vl6524/VS6524 video pipe setup are grouped into register banks called pipe setup bank0 control and pipe setup bank1 control . pipe setup bank0 control setup is used when viewlive is disabled. when viewlive is enabled the output data switches between pipe setup bank0 control and pipe setup bank1 control on each alternate frame. figure 9. viewlive frame output format interframe blanking interline blanking interline blanking interframe blanking frame output active video pipe setup bank0 active video pipe setup bank1
output frame size control vl6524/VS6524 22/70 6.4 context switching it is possible to control which pipe setup bank is used and to switch between banks without the need to pause streaming, the change will occur at the next frame boundry after the change to the register has been made. for example this function allows the vl6524/VS6524 to stream an output targetting a display (e.g. rgb 444) and switch to capture an image (e.g. yuv 4:2:2) with no need to pause streaming or enter any other operating mode. the register bnonviewlive_ activepipesetupbank allows selection of the pipe setup bank (see table 15: pipe setup bank selection ).
vl6524/VS6524 output data formats 23/70 7 output data formats the vl6524/VS6524 supports the following data formats: yuv4:2:2 rgb565 rgb444 (encapsulated as 565) rgb444 (zero padded) bayer 10-bit in all output formats there are 2 output bytes per pixel. the required data format is selected using the bdataformat0 register described in ta b l e 1 6 . the various options available for each format are controlled using the brgbsetup and byuvsetup registers ( ta b l e 2 9 ). 7.1 yuv 4:2:2 data format yuv 422 data format requires 4 bytes of data to represent 2 adjacent pixels. itu601-656 defines the order of the y, cb and cr components as shown in figure 10 . figure 10. standard y cb cr data order the vl6524/VS6524 byuvsetup register can be programmed to change the order of the components as follows: figure 11. y cb cr data swapping options cb cr yy cb cr y y cb cr yy 4-byte data packet y first cb first 1 0 1 1 0 1 0 0 cb cr yy in 4-byte data packet components order 1st 2nd 3rd 4th cb y cr y cb cr yy cb y cr y default
output data formats vl6524/VS6524 24/70 7.2 rgb and bayer data formats the vl6524/VS6524 can output rgb data in the following formats: rgb565 rgb444 (encapsulated as rgb565) rgb444 (zero padded) bayer 10-bit note: pixels in bayer 10-bit data output are defect corrected, correctly exposed and white balanced. any or all of these functions can be disabled. in each of these modes 2 bytes of data are required for each output pixel. the encapsulation of the data is shown in figure 12 . figure 12. rgb and bayer data formats (2) rgb 444 packed as rgb565 0 1 2 3 4 5 6 7 bit r 3 r 4 r 2 r 1 g 5 r 0 g 4 g 3 second byte 0 1 2 3 4 5 6 7 bit g 1 g 2 g 0 b 4 b 2 b 3 b 1 b 0 (1) rgb565 data packing first byte 0 1 2 3 4 5 6 7 bit r 2 r 3 r 1 r 0 g 3 1 g 2 g 1 second byte 0 1 2 3 4 5 6 7 bit 1 g 0 0 b 3 b 1 b 2 b 0 1 first byte (3) rgb 444 zero padded 0 1 2 3 4 5 6 7 bit 0 0 0 0 r 2 r 3 r 1 r 0 second byte 0 1 2 3 4 5 6 7 bit g 2 g 3 g 1 g 0 b 2 b 3 b 1 b 0 first byte (4) bayer 10-bit 0 1 2 3 4 5 6 7 bit 0 1 1 0 0 1 b 9 b 8 second byte 0 1 2 3 4 5 6 7 bit b 6 b 7 b 5 b 4 b 2 b 3 b 1 b 0 first byte
vl6524/VS6524 output data formats 25/70 7.2.1 manipulation of rgb data it is possible to modify the encapsulation of the rgb data in a number of ways: swap the location of the red and blue data reverse the bit order of the individual color channel data reverse the order of the data bytes themselves 7.2.2 dithering an optional dithering function can be enabled for each rgb output mode to reduce the appearance of contours produced by rgb data truncation. this is enabled through the dithercontrol register ( table 28: dither control ).
data synchronization methods vl6524/VS6524 26/70 8 data synchronization methods external capture systems can synchronize with the data output from vl6524/VS6524 in one of two ways: 1. synchronization codes are embedded in the output data 2. via the use of two additional synchronization signals: vsync and hsync both methods of synchronization can be programmed to meet the needs of the host system. 8.1 embedded codes the embedded code sequence can be inserted into the output data stream to enable the external host system to synchronize with the output frames. the code consists of a 4-byte sequence starting with 0xff, 0x00, 0x00. the final byte in the sequence depends on the mode selected. two types of embedded codes are supported by the vl6524/VS6524: mode 1 (itu656) and mode 2. the bsynccodesetup register is used to select whether codes are inserted or not and to select the type of code to insert ( table 29: output formatter control ). when embedded codes are selected each line of data output contains 8 additional clocks: 4 before the active video data and 4 after it. 8.1.1 prevention of fals e synchronization codes the vl6524/VS6524 is able to prevent the output of 0xff and/or 0x00 data from being misinterpreted by a host system as the start of synchronization data. this function is controlled the bcodecheckenable register ( table 29: output formatter control ). 8.1.2 mode 1(itu656 compatible) the structure of an image frame with itu656 codes is shown in figure 13 .
vl6524/VS6524 data synchronization methods 27/70 figure 13. itu656 frame structure with even codes the synchronization codes for odd and even frames are listed in ta b l e 3 and ta bl e 4 . by default all frames output from the vl6524/VS6524 are even. it is possible to set all frames to be odd or to alternate between odd and even using the synccodesetup register in the output formatter control register bank. table 3. itu656 embedded synchronization code definition (even frames) name description 4-byte sequence sav line start - active ff 00 00 80 eav line end - active ff 00 00 9d sav (blanking) line start - blanking ff 00 00 ab eav (blanking) line end - blanking ff 00 00 b6 eav sav frame of image data line 1 line 480 frame blanking period line blanking period 9d 80 eav b6 sav ab
data synchronization methods vl6524/VS6524 28/70 8.1.3 mode 2 the structure of a mode 2 image frame is shown figure 14 . figure 14. mode 2 frame structure (vga example) for mode 2, the synchronization codes are as listed in ta b l e 5 . table 4. itu656 embedded synchronization code definition (odd frames) name description 4-byte sequence sav line start - active ff 00 00 c7 eav line end - active ff 00 00 da sav (blanking) line start - blanking ff 00 00 ec eav (blanking) line end - blanking ff 00 00 f1 table 5. mode 2 - embedded synchronization code definition name description 4-byte sequence ls line start ff 00 00 00 le line end ff 00 00 01 le ls frame of image data line 1 line 480 frame blanking period line blanking period fe fs
vl6524/VS6524 data synchronization methods 29/70 8.2 vsync and hsync the vl6524/VS6524 can provide two programmable hardware synchronization signals: vsync and hsync. the position of these signals within the output frame can be programmed by the user or an automatic setting can be used where the signals track the active video portion of the output frame regardless of its size. 8.2.1 horizontal synchr onization signal (hsync) the hsync signal is controlled by the bhsyncsetup register ( ta b l e 2 9 ) . the following options are available: enable/disable select polarity all lines or active lines only manual or automatic in automatic mode the hsync signal envelops all the active video data on every line in the output frame regardless of the programmed image size. line codes (if selected) fall outside the hsync envelope as shown in figure 15 . figure 15. hsync timing example if manual mode is selected then the pixel positions for hsync rising edge and falling edge are programmable. the pixel position for the rising edge of hsync is programmed in the bhsyncrisingh , bhsyncrisingl registers. the pixel position for the falling edge of hsync is programmed in the bhsyncfallingh and bhsyncfallingl registers ( ta b l e 2 9 ). fs frame start ff 00 00 02 fe frame end ff 00 00 03 table 5. mode 2 - embedded synchronization code definition name description 4-byte sequence ff sav code eav code active video data hsync=1 eav code blanking data hsync=0 00 00 xy 80 10 80 10 80 10 80 10 00 00 xy ff d0 d1 d2 d3 d0 d1 d2 d3 d2 d3 ff 00 00 xy
data synchronization methods vl6524/VS6524 30/70 8.2.2 vertical synchronization (vsync) the vsync signal is controlled by the bvsyncsetup register. the following options are available: enable/disable select polarity manual or automatic in automatic mode the vsync signal envelops all the active video lines in the output frame regardless of the programmed image size as shown in figure 16 . figure 16. vsync timing example if manual mode is selected then the line number for vsync rising edge and falling edge is programmable. the rising edge of vsync is programmed in the bvsyncrisinglineh , bvsyncrisinglinel registers, the pixel position for vsync rising edge is programmed in the bvsyncrisingpixelh and bvsyncrisingpixell registers. similarly the line count for the falling edge position is specified in the bvsyncfallinglineh and bvsyncfallinglinel registers, and the pixel count is specified in the bvsyncfallingpixelh and bvsyncfallingpixell registers described in table 29: output formatter control . blanking blanking v=1 v=0 v=1 v=0 vsync active video active video
vl6524/VS6524 getting started 31/70 9 getting started 9.1 initial power up before any communication is possible with the vl6524/VS6524 the following steps must take place: 1. apply vdd (1.8v or 2.8v) 2. apply avdd (2.8v) 3. apply an external clock (6.5 mhz to 26 mhz) 4. assert ce line high these steps can all take place simultaneously. after these steps are complete a delay of 200 s is required before any i2c communication can take place, see figure 3: power up sequence . 9.2 minimum startup command sequence 1. enable the microprocessor - before any commands can be sent to the vl6524/VS6524, the internal microprocessor must be enabled by writing the value 0x06 to the microenable register 0xc003 ( table 7: low-level control registers ). 2. enable the digital i/o - after power up the digital i/o of the vl6524/VS6524 is in a high- impedance state (?tri-state?). the i/o are enabled by writing the value 0x01 to the enable i/o register 0xc034 ( table 7: low-level control registers ). 3. the user can then program the system clock frequency and setup the required output format before placing the vl6524/VS6524 in run mode by writing 0x02 to the busercommand register 0x0180 ( table 9: mode control ). the above three commands represent the absolute minimum required to get video data output. the default configuration results in an output of vga, 30 fps, yuv data format with itu embedded codes requiring a external clock frequency of 12mhz. in practice the user is likely to require to write some additional setup information prior to receive the required data output.
host communication - i2c control interface vl6524/VS6524 32/70 10 host communication - i2c control interface the interface used on the vl6524/VS6524 is a subset of the i2c standard. higher level protocol adaptations have been made to allow for greater addressing flexibility. this extended interface is known as the v2w interface. v2w protocol layer protocol a message contains two or more bytes of data preceded by a start (s) condition and followed by either a stop (p) or a repeated start (sr) condition followed by another message. stop and start conditions can only be generated by a v2w master. after every byte transferred the receiving device must output an acknowledge bit which tells the transmitter if the data byte has been successfully received or not. the first byte of the message is called the device address byte and contains the 7-bit address of the v2w slave to be addressed plus a read/write bit which defines the direction of the data flow between the master and the slave. the meaning of the data bytes that follow device address changes depending whether the master is writing to or reading from the slave. figure 17. write message for the master writing to the slave the device address byte is followed by 2 bytes which specify the 16-bit internal location (index) for the data write. the next byte of data contains the value to be written to that register index. if multiple data bytes are written then the internal register index is automatically incremented after each byte of data transferred. the master can send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start (sr). figure 18. read message ?0? (write) s dev addr r/w a 2 index bytes data p a/a data a n data byte a data from master to slave from slave to master ?1? (read) s dev addr r/w a data p a data a 1 or more data byte from master to slave from slave to master
vl6524/VS6524 host communication - i2c control interface 33/70 for the master reading from the slave the device address is followed by the contents of last register index that the previous read or write message accessed. if multiple data bytes are read then the internal register index is automatically incremented after each byte of data read. a read message is terminated by the bus master generating a negative acknowledge after reading a final byte of data. a message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation. detailed overview of the message format figure 19. detailed overview of message format the v2w generic message format consists of the following sequence 1. master generates a start condition to signal the start of new message. 2. master outputs, ms bit first, a 7-bit device address of the slave the master is trying to communicate with followed by a r/w bit. sda scl s or sr 12 789 sr or p msb lsb start or repeated start condition ack signal from slave stop or repeated start condition device address 12 789 msb lsb s (sr) 7-bit device address r/w a a (a ) 8-bit data p (sr) data byte from transmitter r/w =0 - master r/w =1 - slave ack signal from receiver r/w bit 0 - write 1 - read sr p 1 2 3 4 5 6
host communication - i2c control interface vl6524/VS6524 34/70 figure 20. device addresses a) r/w = 0 then the master (transmitter) is writing to the slave (receiver). b) r/w = 1 the master (receiver) is reading from the slave (transmitter). 3. the addressed slave acknowledges the device address. 4. data transmitted on the bus a) when a write is performed then master outputs 8-bits of data on sda (ms bit first). b) when a read is performed then slave outputs 8-bits of data on sda (ms bit first). 5. data receive acknowledge a) when a write is performed slave acknowledges data. b) when a read is performed master acknowledges data. repeat 4 and 5 until all the required data has been written or read. minimum number of data bytes for a read =1 (shortest message length is 2-bytes). the master outputs a negative acknowledge for the data when reading the last byte of data. this causes the slave to stop the output of data and allows the master to generate a stop condition. 6. master generates a stop condition or a repeated start. data valid the data on sda is stable during the high period of scl. the state of sda is changed during the low phase of scl. the only exceptions to this are the start (s) and stop (p) conditions as defined below. (see figure 33: timing specification and ta b l e 3 8 : t i m i n g specification ). figure 21. sda data valid 0 0 1 0 0 0 0 r/w sensor address 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 sensor write address 20 h sensor read address 21 h data line stable data valid data line stable data valid data change sda scl
vl6524/VS6524 host communication - i2c control interface 35/70 start (s) and stop (p) conditions a start (s) condition defines the start of a v2w message. it consists of a high to low transition on sda while scl is high. a stop (p) condition defines the end of a v2w message. it consists of a low to high transition on sda while scl is high. after stop condition the bus is considered free for use by other devices. if a repeated start (sr) is used instead of a stop then the bus stays busy. a start (s) and a repeated start (sr) are considered to be functionally equivalent. figure 22. start and stop conditions acknowledge after every byte transferred the receiver must output an acknowledge bit. to acknowledge the data byte receiver pulls sda during the 9th scl clock cycle generated by the master. if sda is not pulled low then the transmitter stops the output of data and releases control of the bus back to the master so that it can either generate a stop or a repeated start condition. figure 23. data acknowledge start condition stop condition s p sda scl s 12 89 start condition negative acknowledge (a ) acknowledge (a) clock pulse for acknowledge sda data output by transmitter sda data output by receiver scl clock from master
host communication - i2c control interface vl6524/VS6524 36/70 index space communication using the serial bus centres around a number of registers internal to the either the sensor or the co-processor. these registers store sensor status, set-up, exposure and system information. most of the registers are read/write allowing the receiving equipment to change their contents. others (such as the chip id) are read only. the internal register locations are organized in a 64k by 8-bit wide space. this space includes ?real? registers, sram, rom and/or micro controller values. figure 24. internal register index space 0 1 2 3 4 65532 65533 65534 65535 16-bit index / 8-bit data format 64k by 8-bit wide index space (valid addresses 0-65535) 130 129 128 127 126 125 8 bits
vl6524/VS6524 host communication - i2c control interface 37/70 types of messages this section gives guidelines on the basic operations to read data from and write data to vl6524/VS6524. the serial interface supports variable length messages. a message contains no data bytes or one data byte or many data bytes. this data can be written to or read from common or different locations within the sensor. the range of instructions available are detailed below. single location, single byte data read or write. write no data byte. only sets the index for a subsequent read message. multiple location, multiple data read or write for fast information transfers. any messages formats other than those specified in the following section should be considered illegal. random location, single data write for the master writing to the slave the r/w bit is set to zero. the register index value written is preserved and is used by a subsequent read. the write message is terminated with a stop condition from the master. figure 25. random location, single write s dev addr r/w a data p a/a data a data a index[7:0] data[7:0] index[15:8] previous index value, k index m 16-bit index, 8-bit data, random location, single data write index[15:0] value, m data[7:0] from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = negative acknowledge ?0? (write)
host communication - i2c control interface vl6524/VS6524 38/70 current location, single data read for the master reading from the slave the r/w bit is set to one. the register index of the data returned is that accessed by the previous read or write message. the first data byte returned by a read message is the contents of the internal index value and not the index value. this was the case in older v2w implementations. note that the read message is terminated with a negative acknowledge (a ) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. this is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition. figure 26. current location, single read data data[7:0] data[7:0] s dev addr r/w a ?1? (read) p a 16-bit index, 8-bit data current location, single data read from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = negative acknowledge previous index value, k
vl6524/VS6524 host communication - i2c control interface 39/70 random location, single data read when a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. the read message then completes the message sequence. to avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages. as mentioned in the previous example, the read message is terminated with a negative acknowledge (a ) from the master. figure 27. random location, single data read multiple location write for messages with more than 1 data byte the internal register index is automatically incremented for each byte of data output, making it possible to write data bytes to consecutive adjacent internal registers without having to send explicit indexes prior to sending each data byte. figure 28. multiple location write ?0? (write) s dev addr r/w a data a data a index[7:0] index[15:0] value, m index[15:8] data data[7:0] data[7:0] sr dev addr r/w a ?1? (read) p a previous index value, k index m no data write data read 16-bit index, 8-bit data random index, single data read a = acknowledge a = negative acknowledge s = start condition sr = repeated start p = stop condition from slave to master from master to slave ?0? (write) s dev addr r/w a data p a/a data a data a index[7:0] data[7:0] index[15:0] value, m data[7:0] index[15:8] data a data[7:0] data[7:0] n bytes of data previous index value, k index m index (m + n - 1) 16-bit index, 8-bit data multiple location write a = acknowledge a = negative acknowledge s = start condition sr = repeated start p = stop condition from slave to master from master to slave
host communication - i2c control interface vl6524/VS6524 40/70 multiple location read stati ng from the current location in the same manner to multiple location writes, multiple locations can be read with a single read message. figure 29. multiple location read data data[7:0] data[7:0] s dev addr r/w a ?1? (read) data p a a data[7:0] data[7:0] n bytes of data index k+1 index (k + n - 1) data data[7:0] data[7:0] a previous index value, k 16-bit index, 8-bit data multiple location read a = acknowledge a = negative acknowledge s = start condition sr = repeated start p = stop condition from slave to master from master to slave
vl6524/VS6524 host communication - i2c control interface 41/70 figure 30. multiple location read starting from a random location ?0? (write) s dev addr r/w a write data (n bytes + acknowledge) ?0? (write) s dev addr r/w a data a data a index[7:0] index[15:0] value, m index[15:8] data p a/a data a data data[7:0] data[7:0] sr dev addr r/w a ?1? (read) sr dev addr r/w a data a data a ?1? (read) read data (r bytes + acknowledge 16-bit index, 8-bit data random index, multiple data read i 2 c combined format specification data p a a data[7:0] data[7:0] n bytes of data from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = negative acknowledge previous index value, k index (m + n - 1) index m no data write data read
register map vl6524/VS6524 42/70 11 register map the vl6524/VS6524 i2c write address is 0x20. all i2c locations contain an 8-bit byte. however, certain parameters require 16 bits to represent them and are therefore stored in more than 1 location. note: for all 16 bit parameters the msb register must be written before the lsb register. the data stored in each location can be interpreted in different ways as shown below. register contents represent different data types as described in ta b l e 6 . float number format float 900 is used in st co-processors to represent floating point numbers in 2 bytes of data. it conforms to the following structure: bit[15] = sign bit (1 represents negative) bit[14:9] = 6 bits of exponent, biased at decimal 31 bit[8:0] = 9 bits of mantissa to convert a floating point number to float 900, use the following procedure: represent the number as a binary floating point number. normalize the mantissa and calculate the exponent to give a binary scientific representation of 1.xxxxxxxxx * 2^y. the x symbols should represent 9 binary digits of the mantissa, round or pad with zeros to achieve 9 digits in total. remove the leading 1 from the mantissa as it is redundant. to calculate the y value bias the exponent by adding to 31 decimal then converting to binary. the data can then be placed in the structure above. table 6. data type data type description i integer parameter. m multiple field registers - 16 bit parameter b bit field register - individual bits must be set/cleared c coded register - function depends on value written f float value
vl6524/VS6524 register map 43/70 example convert -0.41 to float 900 convert the fraction into binary by successive multiplication by 2 and removal of integer component 0.41 * 2 = 0.82 0 0.82 * 2 = 1.64 1 0.64 * 2 = 1.28 1 0.28 * 2 = 0.56 0 0.56 * 2 = 1.12 1 0.12 * 2 = 0.24 0 0.24 * 2 = 0.48 0 0.48 * 2 = 0.96 0 0.96 * 2 = 1.92 1 0.92 * 2 = 1.84 1 0.84 * 2 = 1.68 1 0.68 * 2 = 1.36 1 0.36 * 2 = 0.72 0 this gives us -0.0110100011110. we then normalize by moving the decimal point to give - 1.10100011110 * 2^-2. the mantissa is rounded and the leading zero removed to give 101001000. we add the exponent to the bias of 31 that gives us 29 or 11101. a leading zero is added to give 6 bits 011101. the sign bit is set at 1 as the number is negative. this gives us 1011 1011 0100 1000 as our float 900 representation or bb48 in hex. to convert the encoded representation back to a decimal floating point, we can use the following formula. real is = (-1)^sign * ((512+mantissae)>> 9) * 2^(exp-31) thus to convert bb48 back to decimal, the following procedure is followed: note that >>9 right shift is equal to division by 2^9. sign = 1 exponent = 11101 (29 decimal) mantissa = 101001000 (328 decimal) this gives us: real = (-1)^1 * ((512+328)/2^9) * 2^(29-31) real = -1 * (840/512) * 2^(-2) real = -1 * 1.640625 * 0.25 real = -0.41015625 when compared to the original -0.41, we see that some rounding errors have been introduced.
register map vl6524/VS6524 44/70 low level control registers note: the default values for the above registers are true when the device is powered on, ext. clk input is present and the ce pin is high. all other registers can be read when the clock enable register is set to 0x06. device parameters [read only] mode control table 7. low-level control registers name index r/w data type format default description microenable 0xc003 r/w c 0x38 0x06 - clocks enabled enable i/o 0xc034 r/w b 0x00 set bit[0] to enable io table 8. device parameters name index r/w data type format default description uwdeviceid (msb) 0x0001 r i 0x02 0x020c = 524 uwdeviceid (lsb) 0x0002 r i 0x0c bfirmwarevsnmajor 0x0004 r i 0x01 firmware version 0x0101 = 1.1 bfirmwarevsnminor 0x0006 r i 0x01 bpatchvsnmajor 0x0008 r i 0x00 patch version 0x0000 bpatchvsnminor 0x000a r i 0x00 table 9. mode control name index r/w data type format default description busercommand 0x0180 rw c 0 0x00 - uninitialised 0x01 - boot 0x02 - run 0x03 - pause 0x04 - stop 0x05 - flashgun
vl6524/VS6524 register map 45/70 mode status [read only] runmodecontrol clock manager input control power management control table 10. mode status name index r/w data type format default description bstate 0x0202 r c 0x10 0x10 - raw 0x21 - waiting for boot 0x22 - paused 0x26 - waiting for run 0x31 - running 0x32 - waiting for pause 0x40 - flashgun 0x50 - stopped table 11. runmodecontrol name index r/w data type format default description fmeteringon 0x0280 r/w b 0x01 0x00 = false 0x01 = true table 12. clock manager input control name index r/w data type format default description uwextclockfreqnum (msb) 0x060b r/w i 0x00 specifies the external clock frequency numerator default = 12 mhz uwextclockfreqnum (lsb) 0x060c r/w i 0x0c bextclockfreqden 0x060e r/w i 0x01 specifies the external clock frequency denominator benableglobalsystem clockdivision 0x0610 r/w b 0x00 0x00 = false 0x01 = true -system clock division by 2 table 13. power management control name index r/w data type format default description btimetopowerdown 0x0580 r/w i 0x0f time (ms) from pausing streaming to entering stop. in the range 5 to 154 ms 0xff - disable
register map vl6524/VS6524 46/70 frame rate control pipe setup bank selection pipe setup bank0 control table 14. frame rate control name index r/w data type format default description uwdesiredframe rate_num (msb) 0x0d81 r/w i 0x00 numerator for the frame rate default = 30 fps uwdesiredframe rate_num (lsb) 0x0d82 r/w i 0x1e bdesiredframerate_ den 0x0d84 r/w i 0x01 denominator for the frame rate table 15. pipe setup bank selection name index r/w data type format default description bnonviewlive_ activepipesetupbank 0x0302 r/w i 0x00 0x00 -pipe setup bank0 used 0x01 -pipe setup bank1 used table 16. pipe setup bank0 control name index r/w data type format default description bimagesize0 0x0380 r/w c 0x01 required output dimension 0x01 - imagesize_vga 0x02 - imagesize_qvga 0x03 - imagesize_qqvga 0x04 - imagesize_manual bsubsample0 0x0382 r/w i 0x01 0x01 = minimum sub-sample corresponding to no sub-sampling. max = 0x06 fenablecrop0 0x0384 r/w b 0x00 0x00 = false - 0x01 = true uwcrophstartmsb0 0x0387 r/w m i 0x00 horizontal start point for manual crop uwcrophstartlsb0 0x0388 r/w m i 0x00 uwcrophsizemsb0 0x038b r/w m i 0x00 horizontal size for manual crop uwcrophsizelsb0 0x038c r/w m i 0x00 uwcropvstartmsb0 0x038f r/w m i 0x00 vertical start point for manual crop uwcropvstartlsb0 0x0390 r/w m i 0x00 uwcropvsizemsb0 0x0393 r/w m i 0x00 vertical size for manual crop uwcropvsizelsb0 0x0394 r/w m i 0x00
vl6524/VS6524 register map 47/70 bdataformat0 0x0396 r/w c 0x01 0x00 = ycbcr_jfif 0x01 = ycbcr_rec601 0x02 = ycbcr_custom 0x03 = rgb_565 0x04 = rgb_565_custom 0x05 = rgb_444 0x06 = rgb_444_custom 0x07 = reserved 0x08 = bayer output vp bbayeroutput alignment0 0x398 r/w c 0x04 0x04 = bayer output right shifted 0x05 = bayer output left shifted bcontrast0 0x039a i 0x79 contrast control (%) bcolorsaturation0 0x039c i 0x7d color saturation control (%) bgamma0 0x039e i 0x0f gamma settings 0x00 = gamma_linear 0x10 = gamma smpte 240m 0x1f = gamma_max fhorizontaimirror0 0x03a0 b 0x00 horizontal mirror control, 0x00 = false - 0x01 = true fverticalflip0 0x03a2 b 0x00 vertical mirror control, 0x00 = false - 0x01= true table 16. pipe setup bank0 control name index r/w data type format default description
register map vl6524/VS6524 48/70 pipe setup bank1 control table 17. pipe setup bank1 control name index r/w data type format default description bimagesize1 0x0400 r/w c 0x01 required output dimension 0x01 = imagesize_vga 0x02 = imagesize_qvga 0x03 = imagesize_qqvga 0x04 = imagesize_manual bsubsample1 0x0402 r/w c 0x01 0x01 = minimum sub-sample corresponding to no sub-sampling. max = 0x06 fenablecrop1 0x0404 r/w b 0x00 0x00 = false - 0x01 = true uwcrophstartmsb1 0x0407 r/w m i 0x00 horizontal start point for manual crop uwcrophstartlsb1 0x0408 r/w m i 0x00 uwcrophsizemsb1 0x040b r/w m i 0x00 horizontal size for manual crop uwcrophsizelsb1 0x040c r/w m i 0x00 uwcropvstartmsb1 0x040f r/w m i 0x00 vertical start point for manual crop uwcropvstartlsb1 0x0410 r/w m i 0x00 uwcropvsizemsb1 0x0413 r/w m i 0x00 vertical size for manual crop uwcropvsizelsb1 0x0414 r/w m i 0x00 bdataformat1 0x0416 r/w c 0x01 0x00 = ycbcr_jfif 0x01 = ycbcr_rec601 0x02 = ycbcr_custom 0x03 = rgb_565 0x04 = rgb_565_custom 0x05 = rgb_444 0x06 = rgb_444_custom 0x07 = bayervpbypass 0x08 = bayerthroughvp bbayeroutput alignment1 0x0418 r/w c 0x04 0x04 = bayer output right shifted 0x05 = bayer output left shifted bcontrast1 0x041a r/w i 0x79 contrast control (%) bcolorsaturation1 0x041c r/w i 0x7d color saturation control (%) bgamma1 0x041e r/w i 0x0f gamma settings 0x00 = gamma_linear 0x10 = gamma smpte 240m 0x1f = gamma_max fhorizontalmirror1 0x0420 r/w b 0x00 horizontal mirror control 0x00 = false, 0x01 = true fverticalflip1 0x0422 r/w b 0x00 vertical mirror control 0x00 = false , 0x01 = true
vl6524/VS6524 register map 49/70 view live control white balance control table 18. view live control name index r/w data type format default description fenable 0x0480 r/w b 0x00 enable viewlive mode 0x00 = false - 0x01 = true initalpipesetupbank 0x0482 r/w c 0x00 when viewlive mode is enabled, this register selects which pipesetupbank the first frame output uses, 0x00 = pipesetupbank0 0x01 = pipesetupbank1 table 19. white balance control name index r/w data type format default description whitebalancemode 0x1380 r/w c 0x01 white balance mode selection: 0x00 = off - no white balance, all gains are unity in this mode 0x01 = automatic 0x03 = manual_rgb - gains are applied manually using registers below 0x04 = daylight_preset 0x05 = tungsten_preset 0x06 = fluorescent_preset 0x07 = horizon_preset 0x08 = manual_colour_temp 0x09 = flashgun_preset bmanualredgain 0x1382 r/w i 0x00 user setting for red channel gain bmanualgreengain 0x1384 r/w i 0x00 user setting for green channel gain bmanualbluegain 0x1386 r/w i 0x00 user setting for blue channel gain fpredgainforflashgun msb 0x138b r/w m f 0x3e red channel gain for flashgun code float - default 0x3e66 = 1.199219 fpredgainforflashgun lsb 0x138c r/w m f 0x66 fpgreengainfor flashgun msb 0x138f r/w m f 0x3e green channel gain for flashgun code float - default 0x3e00 = 1.000000 fpgreengainfor flashgun lsb 0x1390 r/w m f 0x00 fpbluegainfor flashgun msb 0x1393 r/w m f 0x3e blue channel gain for flashgun code float . default 0x3e33 = 1.099609 fpbluegainfor flashgun lsb 0x1394 r/w m f 0x33
register map vl6524/VS6524 50/70 exposure control table 20. exposure control name index r/w data type format default description bexposuremode 0x1080 r/w c 0x00 0x00 = automatic_mode 0x01 = compiled_manual_ mode - the desired exposure time is set manually in the manual exposure registers and the exposure parameters are calculated by the algorithm. 0x02 = direct_manual_ mode - the exposure parameters are input directly. 0x03 = flashgun_mode - the exposure parameters are set manually. bexposuremetering 0x1082 r/w c 0x00 weights associated with the zones to calculate the mean statistics. exposure weight is centered or backlit or flat. 0x00 = exposuremetering_flat - uniform gain associated with all pixels 0x01 = exposuremetering_backlit: more gain associated with centre and bottom pixels 0x02 = exposuremetering_centred - more gain associated with centre pixels bmanualexposure time_num 0x1084 r/w i 0x01 exposure time for compiled manual mode in seconds. numerator / denominator gives required exposure time bmanualexposure time_den 0x1086 r/w i 0x1e iexposure compensation 0x1090 r/w i 0x00 exposure compensation - a user choice for setting the runtime target. a unit of exposure compensation corresponds to 1/6 ev. this is a signed register. ffreezeauto exposure 0x10b4 r/w b 0x00 freeze auto exposure 0x00 = false 0x01 = true fpusermaximum integrationtime (msb) 0x10b7 r/w m f 0x64 user maximum integration time in microseconds. this control takes in the maximum integration time that host would like to support. this in turn gives an idea of the degree of ?wobbly pencil effect? acceptable by host. default 0x647f = 654336 fpusermaximum integrationtime (lsb) 0x10b8 r/w m f 0x7f
vl6524/VS6524 register map 51/70 exposure status (read only) exposure algorithm control flashgun control table 21. exposure status name index r/w data type format default description fpcompiledtime (msb) 0x121d r m f present exposure time as calculated by the compiler taking into account the framerate used. fpcompiledtime (lsb) 0x121e r m f table 22. exposure algorithm control name index r/w data type format default description bleakshift 0x113c r/w i 0x02 control exposure leaky integrator. set to 0 for reactive systems. set to 4 for more stable systems. table 23. flashgun control name index r/w data type format default description bflashgunmode 0x1780 r/w c 0x00 manual flashgun control (1) 0x00 = flash off 0x01 = torch (fso pin high) 0x02 = flash pulse 1. the mode control register has priority over this function uwflashgunoffline msb 0x1783 r/w m i 0x02 this is used to set the duration of the flash. the value equals the line in the frame during which the flashgun pulse is switched off. uwflashgunoffline lsb 0x1784 r/w m i 0x1c
register map vl6524/VS6524 52/70 flicker frequency control defect correction control sharpening control fade to black damper control table 24. flicker frequency control name index r/w data type format default description bantiflickermode 0x10c0 r/w c 0x01 modes for anti-flicker compilation. 0x00 = inhibit 0x01 = manual enable blightingfreqhz 0x0c80 r/w i 0x64 flicker free time period calculations this should be 2* ac mains frequency 0x64 = 100 = 50hz ac freq 0x78 =120 = 60hz ac freq fflickercomplatible framelength 0x0c82 r/w b 0x00 set to make the frame length compatible with the flicker free time period, 0x00 = false 0x01 = true table 25. defect correction control name index r/w data type format default description fdisablescythefilter 0x1a80 r/w b 0x00 0x00 = false 0x01 = true fdisablejackfilter 0x1b00 r/w b 0x00 0x00 = false 0x01 = true table 26. sharpening control name index r/w data type format default description buserpeakgain 0x1d80 r/w i 0x0f adjust gradient of sharpening system buserpeaklo threshold 0x1d90 r/w i 0x1e the coring threshold is used to stop the sharpening gain being applied to very small changes in the image (i.e. noise). table 27. fade to black damper control name index r/w data type format default description fdisable 0x2000 r/w b 0x00 set to disable fade to black operation. 0x00 = false 0x01 = true
vl6524/VS6524 register map 53/70 fpblackvalue (msb) 0x2003 r/w m f 0x00 minimum possible damper output for the colour matrix 0.0 fades to absolute black, 1.0 effectively disables fade to black. default 0x0000 = 0 fpblackvalue (lsb) 0x2004 r/w m f 0x00 fpdamperlow threshold (msb) 0x2007 r/w m f 0x63 low threshold to calculate the damper slope default 0x67d1 =500224 fpdamperlow threshold (lsb) 0x2008 r/w m f 0xd1 fpdamperhigh threshold (msb) 0x200b r/w m f 0x65 high threshold to calculate the damper slope default 0x656f = 900096 fpdamperhigh threshold (lsb) 0x200c r/w m f 0x6f fpminimumoutput (msb) 0x200f r f status value showing damper strength used fpminimumoutput (lsb) 0x2010 r f table 27. fade to black damper control name index r/w data type format default description
register map vl6524/VS6524 54/70 dither control output formatter control table 28. dither control name index r/w data type format default description dithercontrol 0x2080 r/w c 0x00 0x00 = dither rgb modes only 0x01 = dither function off 0x02 = dither function on table 29. output formatter control name index r/w data type format default description bcodecheckenable 0x2100 r/w c 0x07 0x00 - allow all output values 1 = suppress 0xff 2 = suppress 0x00 3 = suppress 0x00 and 0xff from output bsynccodesetup 0x2104 r/w b 0x01 [0] enable sync codes [1] sync code type (0 = itu, 1 = mode2) [2] odd/even field (0 =even, 1 =odd) [3] toggle (1 = toggle) [4] load (set high then low over a frame boundary to consume a change applied in [2] or [3]) bhsyncsetup 0x2106 r/w b 0x0b [0] enable [1] polarity [2] active lines only [3] automatic/manual bvsyncsetup 0x2108 r/w b 0x07 [0] enable [1] polarity [2] automatic/manual bpclksetup 0x210a r/w b 0x05 [0] edge (1=positive, 0 =negative) [1] non-active level (1=high. 0 = low) [2] enable [7] free-running fppclken 0x210c r/w b 0x01 0 = false - 1 = true bblankdata_msb 0x2110 r/w i 0x10 blanking msb bblankdata_lsb 0x2112 r/w i 0x80 blanking lsb brgbsetup 0x2114 r/w b 0x00 [0] rgb 444 - zero packing [1] swap r and b components [2] reverse bits byuvsetup 0x2116 r/w b 0x00 [0] cb_first [1] y first
vl6524/VS6524 register map 55/70 bvsyncrisinglineh 0x2118 r/w m i 0x00 line on which vsync should rise (manual vsync must be selected) bvsyncrisinglinel 0x211a r/w m i 0x00 bvsyncrisingpixelh 0x211c r/w m i 0x01 pixel on which vsync should rise (manual vsync must be selected) bvsyncrisingpixell 0x211e r/w m i 0x01 bvsyncfallinglineh 0x2120 r/w m i 0x01 line on which vsync should fall (manual vsync must be selected) bvsyncfallinglinel 0x2122 r/w m i 0xf2 bvsyncfallingpixelh 0x2124 r/w m i 0x00 pixel on which vsync should fall (manual vsync must be selected) bvsyncfallingpixell 0x2126 r/w m i 0x01 bhsyncrisingh 0x2128 r/w m i 0x00 pixel on which hsync should rise (manual hsync must be selected) bhsyncrisingl 0x212a r/w m i 0x03 bhsyncfallingh 0x212c r/w m i 0x00 pixel on which hsync should fall (manual hsync must be selected) bhsyncfallingl 0x212e r/w m i 0x07 table 29. output formatter control name index r/w data type format default description
optical specifications vl6524/VS6524 56/70 12 optical specifications 12.1 average sensitivity the average sensitivity is a measure of the image sensor response to a given light stimulus. the optical stimulus is a white light source with a color temperature of 3200k, producing uniform illumination at the surface of the sensor package. an ir blocking filter is added to the light source. the analog gain of the sensor is set to x1. the exposure time, ? t, is set as 50% of maximum. the illuminance, i, is adjusted so the average sensor output code, xlight, is roughly mid-range equivalent to a saturation level of 50%. once xlight has been recorded the experiment is repeated with no illumination to give a value xdark. the sensitivity is then calculated as .the result is expressed in volts per lux- second. the sensitivity of the VS6524 is given in ta bl e 3 1 . table 30. optical specifications (1) 1. all measurements made at 23c 2c parameter min. typ. max. unit optical format 1/6 inch effective focal length 2.5 mm aperture (f number) 2.8 horizontal field of view 46 49 51 deg. vertical field of view 35 37 39 deg. diagonal field of view (2) 2. value determined through calculation 57 59 61 deg. depth of field (3) 3. by design the device has an acceptable quality between hyperfocal distance /2 and infinity. 20 infinity cm tv distortion -1.5 1.5 % table 31. VS6524 average sensitivity optical parameter value unit average sensitivity 0.71 v/lux.s xlight xdark ? ? tl ? ---------------------------------------
vl6524/VS6524 optical specifications 57/70 12.2 spectral response the spectral response for the VS6524 sensor is shown in figure 31 . figure 31. VS6524 spectral response 0 5 10 15 20 25 30 35 400 450 500 550 600 650 700 wavelength /nm qe /% blue green red 0 5 10 15 20 25 30 35 400 450 500 550 600 650 700 wavelength /nm qe /% blue green red quantum efficiency - sensitivity = 0.71v/lux.sec.
electrical characteristics vl6524/VS6524 58/70 13 electrical characteristics 13.1 absolute maximum ratings caution: stress above those listed under ?absolute maximum ratings? can cause permanent damage to the device. this is a stress rating only and functional operations of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 13.2 operating conditions table 32. absolute maximum ratings symbol parameter min. max. unit t sto storage temperature -40 85 c v dd digital power supplies -0.5 3.3 v avdd analog power supplies -0.5 3.3 v table 33. supply specifications symbol parameter min. max. unit t af operating temperature, functional (camera is electrically functional) -30 70 c t an operating temperature, nominal (camera produces acceptable images) -25 55 c t ao operating temperature, optimal (camera produces optimal optical performance) 530c v dd digital power supplies operating range (@ module pin (1) ) 1. module can contain routing resistance up to 5 ? . 1.7 2.0 v 2.4 3.0 v avdd analog power supplies operating range (@ module pin (1) ) 2.4 3.0 v
vl6524/VS6524 electrical characteristics 59/70 13.3 dc electrical characteristics note: over operating conditions unless otherwise specified. table 34. dc electrical characteristics symbol description test conditions min. typ. max. unit v il input low voltage v dd 1.7 ~ 2.0 v -0.3 0.25 v dd v v dd 2.4 ~ 3.0 v -0.3 0.3 v dd v ih input high voltage v dd < 2.7 v 0.7 v dd v dd + 0.3 v v dd > 2.7 v 0.7 v dd 3.46 v v ol output low voltage i ol < 2 ma i ol < 4 ma 0.2 v dd 0.4 v dd v v oh output high voltage i ol < 4 ma 0.8 v dd v i il input leakage current input pins i/o pins 0 < v in < v dd -10 -1 +10 +1 a a input leakage current sda and scl pins v ih > v dd + 0.3v -2 +500 a c in input capacitance, scl t a = 25 c, freq = 1 mhz 6 pf c out output capacitance t a = 25 c, freq = 1 mhz 6 pf c i/o i/o capacitance, sda t a = 25 c, freq = 1 mhz 8 pf table 35. typical current consumption symbol description test conditions i avdd i vdd units v dd = 1.8v v dd = 2.8v i pd supply current in power down mode ce=0, clk = 12 mhz 0.01 0.6 0.8 a i stanby supply current in standby mode ce=1, clk = 12 mhz 0.001 0.4 1.2 ma istop supply current in stop mode ce=1, clk = 12 mhz 0.002 0.4 7.45 ma i pause supply current in pause mode ce=1, clk = 12 mhz 0.050 14.99 24.4 ma i run supply current in active streaming run mode ce=1, clk = 12 mhz streaming vga @30 fps 8.3 32.6 41.0 ma
electrical characteristics vl6524/VS6524 60/70 13.4 ac electrical characteristics 13.4.1 external clock the vl6524/VS6524 requires an external clock. this clock is a cmos digital input. the clock input is fail-safe in power down mode. 13.4.2 chip enable ce is a cmos digital input. the module is powered down when a logic 0 is applied to ce. see chapter 4 for power down and for power-up sequence. 13.4.3 i2c slave interface vl6524/VS6524 contains an i2c-type interface using two signals: a bidirectional serial data line (sda) and an input-only serial clock line (scl). see chapter 10 for detailed description of protocol. table 36. external clock clk range unit min. typ. max. dc coupled square wave vdd v clock frequency (normal operation) 6.50 6.50, 8.40, 9.60, 9.72, 12.00, 13.00, 16.80, 19.20, 19.44 26 mhz table 37. serial interface voltage levels (1) 1. maximum v ih = v ddmax + 0.5 v symbol parameter standard mode fast mode unit min. max. min. max. v hys hysteresis of schmitt trigger inputs v dd > 2 v n/a n/a 0.05 v dd -v v dd < 2v n/a n/a 0.1 v dd -v low level output voltage (open drain) at 3ma sink current v ol1 v dd > 2 v 0 0.4 0 0.4 v v ol3 v dd < 2v n/a n/a 0 0.2 v dd v v oh high level output voltage n/a n/a 0.8 v dd v t of output fall time from v ihmin to v ilmax with a bus capacitance from 10 pf to 400 pf - 250 20+0.1c b (2) 2. c b = capacitance of one bus line in pf 250 ns t sp pulse width of spikes which must be suppressed by the input filter n/a n/a 0 50 ns
vl6524/VS6524 electrical characteristics 61/70 figure 32. voltage level specification table 38. timing specification (1) 1. all values are referred to a v ihmin = 0.9 v dd and v ilmax = 0.1 v dd symbol parameter standard mode fast mode unit min. max. min. max. f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time for a repeated start 4.0 - 0.6 - s t low low period of scl 4.7 - 1.3 - s t high high period of scl 4.0 - 0.6 - s t su;sta set-up time for a repeated start 4.7 - 0.6 - s t hd;dat data hold time (1) 300 - 300 - ns t su;dat data set-up time (1) 250 - 100 - ns t r rise time of scl, sda - 1000 20+0.1c b (2) 2. c b = capacitance of one bus line in pf 300 ns t f fall time of scl, sda - 300 20+0.1c b (2) 300 ns t su;sto set-up time for a stop 4.0 - 0.6 - s t buf bus free time between a stop and a start 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf v nl noise margin at the low level for each connected device (including hysteresis) 0.1 v dd - 0.1 v dd - v v nh noise margin at the high level for each connected device (including hysteresis) 0.2 v dd - 0.2 v dd - v v oh = 0.8 * v dd v ol = 0.2 * v dd input voltage levels output voltage levels v ih v il
electrical characteristics vl6524/VS6524 62/70 figure 33. timing specification figure 34. sda/scl rise and fall times all values are referred to a v ihmin = 0.9 v dd and v ilmax = 0.1 v dd sda scl start stop start t buf t low t high t hd;sta t hd;dat t su;dat t su;sta t su;sto t hd;sta t f t r t sp s ps 0.9 * v dd 0.1 * v dd 0.9 * v dd 0.1 * v dd t f t r
vl6524/VS6524 electrical characteristics 63/70 13.4.4 parallel data interface timing vl6524/VS6524 contains a parallel data output port (d[7:0]) and associated qualification signals (hsync, vsync, pclk and fso). this port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or bit-serial output configurations. the port is disabled (high impedance) upon reset. figure 35. parallel data output video timing 13.5 esd handling characteristics table 39. parallel data interface timings symbol description conditions min. typ. max. unit f pclk pclk frequency 26 mhz t pclkl pclk low width 10 ns t pclkh pclk high width 10 ns t dv pclk to output valid -5 5 ns t pclkl t pclkh 1/f pclk pclk d[0:7] hsync polarity = 0 t dv valid vsync table 40. esd handling characteristics test criteria unit esd machine model 150 v esd human body 1.5 kv
package outline vl6524/VS6524 64/70 14 package outline 14.1 smop figure 36. VS6524q06j outline drawing side view bottom view packing dimension socket:alps p/n:scka2a0100 socket cover:alps p/n:jscka0002a note:# image direction register use default settings. basic tolerance 0.10mm optical lens specification: focusing range cm to infinity focal length 2.53mm f number f2.8 fov(d) 60.8 tv distortion < 1% 20 pin no. 1 gnd do2 do3 hsync vsync do7 do6 do1 do0 pclk vdd(1.8v) gnd fso ce scl sda avdd(2.8v) do5 do4 clk 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 name pin no. name 4-?0.60 5.000.05 1.050.05 1.800.05 5.000.05 pin1 mark pin1 mark 20 1 0.700.05 0.500.05 1.450.05 2.60 0.650.05 0.3250.05 0.400.05 0.50 4.350.15 3.300.15 3.35 ?5.00 ?5.90 6.00 6.00 1.200.05 0.500.05 8-r0.50 1 1 1 1 1 1 2 2 2 3 4 2 2 2 2 a d protrude 0.05max tool no. cavity no. recess 0.1max protrude 0.05max protrude 0.05max top view t
vl6524/VS6524 package outline 65/70 figure 37. VS6524q06j socket assembly outline drawing for information only top view bottom view socket:alps p/n:scka2a0100 socket cover:alps p/n:jscka0002a note:# image direction register use default settings. basic tolerance 0.10mm a-a section camera protection pcb socket cover socket cmos sensor holder lens 3.85 3.45 5.200.30 4.350.15 3.35 7.40 6.20 7.40 6.20 a a 1.75 3 4 4 a d ir
package outline vl6524/VS6524 66/70 14.2 lga in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. table 41. lga package mechanical data data book (mm) symbol min. typ. max. a 1.80 1.90 2.00 a4 0.35 0.4 0.45 a5 0.7 0.8 0.9 b1 2.0 b2 3.5 b3 0.55 b 0.25 0.30 0.35 d 9.90 10.00 10.10 d1 9.60 9.70 9.80 d2 5 d4 5.4 e0.8 e 9.90 10.00 10.10 e1 9.60 9.70 9.80 e2 5 e4 4.5 g 1.0 1.1 1.2 g1 1 g2 0.3 0.4 0.5 g3 0.8 0.9 1.0 g4 0.8 h 0.8 0.9 1.0 h1 0.8 h2 0.3 0.4 0.5 i 3.95 4.05 4.15 j4.1 k0.3
vl6524/VS6524 package outline 67/70 phi 456 z1.65 l 0.7 0.8 0.9 bbb 0.01 ccc 0.1 ddd 0.08 eee 0.08 nd 9 ne 9 n36 table 41. lga package mechanical data (continued) data book (mm) symbol min. typ. max.
package outline vl6524/VS6524 68/70 figure 38. vl6524qomh outline drawing
vl6524/VS6524 ordering information 69/70 15 ordering information 16 revision history table 42. vl6524 pin assignment pin signal pin signal pin signal pin signal 1 avdd 10 gnd 19 dio7 28 gnd 2 gnd 11 nc 20 dio6 29 pclk 3 sda 12 nc 21 dio5 30 vdd 4 scl 13 nc 22 dio4 31 nc 5ce14nc23vdd32nc 6 vdd 15 avdd 24 dio3 33 nc 7 clk 16 hsync 25 dio2 34 nc 8 gnd 17 vsync 26 dio1 35 nc 9fso18gnd27dio036gnd table 43. order codes part number package VS6524q06j smop 6x6x4.35 mm vl6524qomh lga 10x10x1.90 mm img-524-e01 baseboard with socket plug-in for x24 camera integration kit img-524-p02 lga package plug-in for x24 camera integration kit table 44. document revision history date revision changes 21-mar-2006 1 initial release. 29-jun-2006 2 updates in table 30: optical specifications and addition of section 12.1: average sensitivity and section 12.2: spectral response . updates in table 34: dc electrical characteristics updates in table 40: esd handling characteristics updates in figure 35: parallel data output video timing 06-nov-2006 3 addition of vl6524 reference and package outline drawing.
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