preliminary 8-mbit (1m x 8) static ram cy7c1059dv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-00061 rev. *b revised july 21, 2006 features ?high speed ?t aa = 10 ns ? low active power ?i cc = 110 ma ? low cmos standby power ?i sb2 = 20 ma ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features ? available in lead-free 36-ball fbga and 44-pin tsop ii zs44 packages functional description [1] the cy7c1059dv33 is a high-performance cmos static ram organized as 1m words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tri-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 19 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1059dv33 is available in 36-ball fbga and 44-pin tsop ii package with center power and ground (revolutionary) pinout. note: 1. for guidelines on sram system design, plea se refer to the ?system design guidelines ? cypress application not e, available on t he internet at www.cypress.com. 14 15 logic block diagram a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 1m x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a ce a a 16 a 17 a 9 a 18 a 10 a 19 [+] feedback [+] feedback
preliminary cy7c1059dv33 document #: 001-00061 rev. *b page 2 of 9 pin configuration a 15 v cc a 13 a 12 a 5 nc we a 7 i/o 4 i/o 5 a 4 i/o 6 i/o 7 v ss a 11 a 10 a 1 v ss i/o 0 a 2 a 8 a 6 a 3 a 0 v cc i/o 1 i/o 2 i/o 3 a 17 a 18 a 16 ce oe a 9 a 14 3 2 6 5 4 1 d e b a c f g h 36-ball fbga a 19 a 6 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view tsop ii 12 13 41 44 43 42 16 15 29 30 v cc a 7 a 8 a 9 nc nc nc nc a 18 v ss nc a 15 a 0 i/o 0 a 4 ce a 17 a 12 a 1 18 17 20 19 i/o 1 27 28 25 26 22 21 23 24 nc v ss we i/o 2 i/o 3 a 5 nc a 16 v cc oe i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 13 a 11 a 10 a 19 nc nc a 2 a 3 (top view) selection guide ?10 unit maximum access time 10 ns maximum operating current 110 ma maximum cmos standby current 20 ma [+] feedback [+] feedback
preliminary cy7c1059dv33 document #: 001-00061 rev. *b page 3 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [2] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [2] ....................................?0.3v to v cc + 0.3v dc input voltage [2] ................................ ?0.3v to v cc + 0.3v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .... ........... .............. ......>2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c3.3v 0.3v electrical characteristics over the operating range parameter description test conditions ?10 unit min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 100 mhz 110 ma 83 mhz 100 66 mhz 90 40 mhz 80 i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 40 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 20 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 16 pf c out i/o capacitance 16 pf thermal resistance [3] parameter description test conditions fbga tsop ii unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board tbd tbd c/w jc thermal resistance (junction to case) tbd tbd c/w notes: 2. v il (min.) = ?2.0v and v ih (max.) = v cc + 2v for pulse durations of less than 20 ns. 3. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
preliminary cy7c1059dv33 document #: 001-00061 rev. *b page 4 of 9 ac test loads and waveforms [4] ac switching characteristics [5] over the operating range parameter description ?10 unit min. max. read cycle t power [6] v cc (typical) to the first access 100 s t rc read cycle time 10 ns t aa address to data valid 10 ns t oha data hold from address change 3 ns t ace ce low to data valid 10 ns t doe oe low to data valid 5 ns t lzoe oe low to low-z 0 ns t hzoe oe high to high-z [7, 8] 5ns t lzce ce low to low-z [8] 3ns t hzce ce high to high-z [7, 8] 5ns t pu ce low to power-up 0 ns t pd ce high to power-down 10 ns write cycle [9, 10] t wc write cycle time 10 ns t sce ce low to write end 7 ns t aw address set-up to write end 7 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 7 ns t sd data set-up to write end 5 ns t hd data hold from write end 0 ns t lzwe we high to low-z [8] 3ns t hzwe we low to high-z [7, 8] 5ns notes: 4. ac characteristics (except high-z) are tested using the load conditions shown in figure (a). high-z characteristics are teste d for all speeds using the test load shown in figure (c). 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 6. t power gives the minimum amount of time that the power supply should be at stable, typical v cc values until the first memory access can be performed. 7. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ac test loads. transition is measured when the outputs enter a high impedance state. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. the internal write time of the memo ry is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the si gnal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.0v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5v (b) (a) 3.3v output 5 pf (c) r 317 ? r2 351 ? high-z characteristics: [+] feedback [+] feedback
preliminary cy7c1059dv33 document #: 001-00061 rev. *b page 5 of 9 data retention characteristics over the operating range data retention waveform parameter description conditions [11] min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 20 ma t cdr [3] chip deselect to data retention time 0 ns t r [12] operation recovery time t rc ns switching waveforms read cycle no. 1 [13, 14] read cycle no. 2 (oe controlled) [14, 15] notes: 11. no inputs may exceed v cc + 0.3v 12. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s. 13. device is continuously selected. oe , ce = v il . 14. we is high for read cycle. 15. address valid prior to or coincident with ce transition low. 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current [+] feedback [+] feedback
preliminary cy7c1059dv33 document #: 001-00061 rev. *b page 6 of 9 write cycle no. 1(we controlled, oe high during write) [16, 17] write cycle no. 2 (we controlled, oe low) [17] notes: 16. data i/o is high-impedance if oe = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 18. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 18 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 18 [+] feedback [+] feedback
preliminary cy7c1059dv33 document #: 001-00061 rev. *b page 7 of 9 truth table ce oe we i/o 0 ?i/o 7 mode power h x x high-z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1059dv33-10baxi 51-85105 36- ball fbga (pb-free) industrial CY7C1059DV33-10ZSXI 51-85087 44-pin tsop ii (pb-free) please contact your local cypress sales repr esentative for availability of these parts. package diagrams 36-ball fbga (7.00 mm x 8.5 mm x 1.2 mm) (51-85105) 51-85105-*d [+] feedback [+] feedback
preliminary cy7c1059dv33 document #: 001-00061 rev. *b page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams (continued) 44-pin tsop ii (51-85087) 51-85087-*a [+] feedback [+] feedback
preliminary cy7c1059dv33 document #: 001-00061 rev. *b page 9 of 9 document history page document title: cy7c1059dv33 8-mbit (1m x 8) static ram document number: 001-00061 rev. ecn no. issue date orig. of change description of change ** 342195 see ecn pci new data sheet *a 380574 see ecn syt redefined i cc values for com?l and ind?l temperature ranges i cc (com?l): changed from 110, 90 and 80 ma to 110, 100 and 95 ma for 8, 10 and 12 ns speed bins respectively i cc (ind?l): changed from 110, 90 and 80 ma to 120, 110 and 105 ma for 8, 10 and 12 ns speed bins respectively changed the capacitance values from 8 pf to 10 pf on page # 3 *b 485796 see ecn nxr changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? removed -8 and -12 speed bins from product offering, removed commercial operating range option, modified maximum ratings for dc inpu t voltage from -0.5v to -0.3v and v cc + 0.5v to v cc + 0.3v updated footnote #7 on high-z parameter measurement added footnote #11 changed the description of i ix from input load current to input leakage current. updated the ordering information table and replaced package name column with package diagram. [+] feedback [+] feedback
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