the sae 81c54 p is a static 4096-bit ram (512 words by 8 bits) in advanced cmos technology. the address and data bus in the multiplex operation allows directly interfaces to 8-bit microprocessors/microcontroller families, e.g. sab 8086, sab 8088, sab 8051. due to its low power dissipation of less than 1 m a in standby mode this component requires only minimum supply current. type ordering code package sae 81c54 p q67100-h8486 p-dip-16-1 cmos ram preliminary dataacmos ic sae 81c54 p-dip-16-1 features l 512 x 8 bit-organization l multiplexed address and data bus l tristate address and data lines l on-chip address register l very low current consumption: 1 m a at 5.5 v during standby l dual chip selection l wide supply voltage range from 2.5 v to 5.5 v l fully compatible 5 v 10 % l data retention up to 1.0 v l temperature range C 40 to 110 c semiconductor group 1 09.94
sae 81c54 semiconductor group 2 pin configurations (top view) pin definitions and functions pin no. symbol function 1-7, 10 ad0-7 address/data lines 8 v ss ground 9 cs chip select 11 a8 address line 12 cs chip select 13 14 15 ale wr rd address signal latch enable write enable read enable 16 v dd supply voltage
sae 81c54 semiconductor group 3 logic symbol truth table for control and data bus pin status cs cs rd wr ad0-7 during data phase function h x l l x l h h x x l h x x h l floating floating data from memory data to memory none none read write
sae 81c54 semiconductor group 4 block diagram
sae 81c54 semiconductor group 5 absolute maximum ratings parameter symbol limit values unit ambient temperature t a - 40 to 110 c storage temperature range t stg - 55 to 125 c thermal resistance system - air r th sa 70 k/w dc characteristics t a = C 40 to 110 c; v dd = 2.5 to 5.5 v; v ss = 0 v parameter symbol limit values unit test condition min. typ. max. standby supply current operating supply current i dd i dd 500 1 m a m a t a = 25 c 100-khz ale operating supply voltage standby supply voltage v dd v dd 2.5 1.0 5.5 5.5 v v data retention input current output leakage current i il i ql 1 1 m a m a v i = 0 C 5.5 v v q = 0 C 5.5 v floating l-input voltage ( v dd < 4.5 v) l-input voltage ( v dd > 4.5 v) v i v il C 0.8 C 0.8 0.6 0.8 v v h-input voltage h-input voltage v ih v ih 0.6 x v dd v dd + 0.8 v dd + 0.8 v v v dd = 5 v
sae 81c54 semiconductor group 6 l-output voltage ( v dd < 4.5 v) l-output voltage ( v dd > 4.5 v) v ql v ql 0.4 0.4 v v i ql = 1 ma i ql = 2 ma h-output voltage ( v dd < 4.5 v) h-output voltage ( v dd > 4.5 v) v qh v qh 0.75 x v dd 0.75 x v dd v v i qh = 1 ma i qh = 2 ma ac characteristics t a = C 40 to 110 c; v dd = 4.5 to 5.5 v; v ss = 0 v parameter symbol limit values unit min. max. ale pulse width t ll 40 ns address setup before ale address hold after ale t al t la 25 25 ns ns wr pulse width rd pulse width t cc t cw 60 130 ns ns data setup before wr data hold after wr data hold after rd t dw t wd t dr 70 20 30 ns ns ns access time rd to data output address floating to rd t rd t afc 0 130 ns ns cs before ale cs after wr or rd t cs t sc 30 10 ns ns ale to rd or wr rd or wr to ale = high t lc t cl 35 25 ns ns dc characteristics (contd) t a = C 40 to 110 c; v dd = 2.5 to 5.5 v; v ss = 0 v parameter symbol limit values unit test condition min. typ. max.
sae 81c54 semiconductor group 7 ac characteristics t a = C 40 to 110 c; v dd = 2.5 to 5.5 v; v ss = 0 v parameter symbol limit values unit min. max. ale pulse width t ll 60 ns address setup before ale address hold after ale t al t la 40 60 ns ns wr pulse width rd pulse width t cc t cw 200 350 ns ns data setup before wr data hold after wr data hold after rd t dw t wd t dr 200 60 95 ns ns ns access time rd to data output address floating to rd t rd t afc 0 350 ns ns cs before ale cs after wr or rd t cs t sc 80 30 ns ns ale to rd or wr rd or wr to ale = high t lc t cl 60 30 ns ns
sae 81c54 semiconductor group 8 diagrams
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