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user? manual printed in japan ? pd178054 subseries 8-bit single-chip microcontrollers pd178053 pd178054 pd178f054 document no. u15104ej2v0ud00 (2nd edition) date published january 2002 n cp(k) 2001
2 user? manual u15104ej2v0ud [memo]
3 user? manual u15104ej2v0ud notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip and iebus are trademarks of nec corporation. windows and windowsnt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. ethernet is a trademark of xerox corporation. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron.
4 user? manual u15104ej2v0ud license not needed: pd178f054gc-8bt the customer must judge the need for license: pd178053gc- -8bt, 178054gc- -8bt the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of october, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec s data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer s equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec s data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec s willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?
5 user s manual u15104ej2v0ud regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? ? ? ? ? ? nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
6 user? manual u15104ej2v0ud major revisions in this edition page description throughout change of pd178053, 178054, and 178f054 status from under development to development completed pp.8, 9 modification of related documents p.25 modification of 1.5 development of 8-bit dts series p.55 modification of bit units for manipulation for osts in table 3-4 special function registers p.84 deletion of pins p10 to p15 from table 4-3 port mode register and output latch settings when using alternate functions p.124 modification of description in (3) oscillation stabilization time select register (osts) in 8.3 registers controlling watchdog timer p.240 addition of chapter 19 electrical specifications p.250 addition of chapter 20 package drawing p.251 addition of chapter 21 recommended soldering conditions p.253 modification of figure a-1 configuration of development tools pp.255, 256 addition of a.1 software package and a.3 control software p.255 addition of note 2 to a.2 language processing software p.257 addition of description for ie-78k0-ns-a to a.5 debugging tools (hardware) p.260 deletion of mx78k0 from a.7 embedded software the mark shows major revised points.
7 user s manual u15104ej2v0ud preface readers this manual has been prepared for user engineers who wish to understand the functions of the purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the s manual pin functions cpu functions internal block functions instruction set interrupt explanation of each instruction other on-chip peripheral functions electrical specifications how to read this manual before reading this manual, you should have general knowledge of electric and logic circuits and microcomputers. when you want to understand the functions in general: to know the 78k/0 series user s manual instructions (u12326e) how to interpret the register format: to know the electrical specifications of the chapter 19 electrical specifications . conventions data representation weight: higher digits on the left and lower digits on the right active low representations: note: footnote for item marked with note in the text. caution: information requiring particular attention remark: supplementary information numeral representations: binary ... s manual instruction
8 user? manual u15104ej2v0ud related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd178054 subseries user? manual this manual 78k/0 series instruction user? manual u12326e 78k/0 series application note basics (i) u12704e documents related to development tools (software) (user? manuals) document name document no. ra78k0 assembler package operation u14445e assembly language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e sm78k0s, sm78k0 system simulator ver.2.10 or later operation u14611e windows based sm78k series system simulator ver.2.10 or later external part user open u15006e interface specifications id78k0-ns integrated debugger ver.2.00 or later operation u14379e windows based id78k0 integrated debugger windows based reference u11539e guide u11649e rx78k0 real-time os fundamental u11537e installation u11536e project manager ver. 3.12 or later (windows-based) u14610e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
9 user s manual u15104ej2v0ud documents related to development tools (hardware) (user s manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-178054-ns-em1 emulation board to be prepared documents related to flash rom writing document name document no. pg-fp3 flash memory programmer user s manual u13502e other related documents document name document no. semiconductor selection guide -products & packages- x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
10 user? manual u15104ej2v0ud table of contents chapter 1 outline ....................................................................................................................... 21 1.1 features .............................................................................................................................. 2 1 1.2 applications ....................................................................................................................... 22 1.3 ordering information ........................................................................................................ 22 1.4 pin configuration (top view) .......................................................................................... 23 1.5 development of 8-bit dts series ................................................................................... 25 1.6 block diagram ................................................................................................................... 26 1.7 functional outline ............................................................................................................ 27 chapter 2 pin function ............................................................................................................. 28 2.1 pin function list ............................................................................................................... 28 2.2 description of pin functions .......................................................................................... 30 2.2.1 p00 to p06 (port 0) .............................................................................................................. 30 2.2.2 p10 to p15 (port 1) .............................................................................................................. 30 2.2.3 p30 to p37 (port 3) .............................................................................................................. 30 2.2.4 p40 to p47 (port 4) .............................................................................................................. 31 2.2.5 p50 to p57 (port 5) .............................................................................................................. 31 2.2.6 p60 to p67 (port 6) .............................................................................................................. 31 2.2.7 p70 to p77 (port 7) .............................................................................................................. 31 2.2.8 p120 to p125 (port 12) ........................................................................................................ 32 2.2.9 p130 to p132 (port 13) ........................................................................................................ 32 2.2.10 eo0, eo1 .............................................................................................................................. 3 2 2.2.11 vcol, vcoh ........................................................................................................................ 32 2.2.12 amifc ............................................................................................................................... .... 33 2.2.13 fmifc ............................................................................................................................... .... 33 2.2.14 reset ............................................................................................................................... ... 33 2.2.15 x1, x2 ............................................................................................................................... .... 33 2.2.16 regosc ............................................................................................................................... 33 2.2.17 regcpu ............................................................................................................................... 33 2.2.18 v dd ............................................................................................................................... .......... 33 2.2.19 gnd ............................................................................................................................... ....... 33 2.2.20 v dd port .............................................................................................................................. 3 3 2.2.21 gndport ............................................................................................................................ 33 2.2.22 v dd pll ............................................................................................................................ ...... 33 2.2.23 gndpll ............................................................................................................................... .33 2.2.24 v pp ( pd178f054 only) ....................................................................................................... 33 2.2.25 ic (mask rom version only) ................................................................................................ 34 2.3 pin i/o circuits and recommended connections of unused pins ........................... 35 chapter 3 cpu architecture ................................................................................................. 38 3.1 memory space ................................................................................................................... 38 3.1.1 internal program memory space .......................................................................................... 42 3.1.2 internal data memory space ................................................................................................ 43 3.1.3 special function register (sfr) area ................................................................................. 43 3.1.4 data memory addressing ..................................................................................................... 44
11 user? manual u15104ej2v0ud 3.2 processor registers ......................................................................................................... 47 3.2.1 control registers ................................................................................................................... 47 3.2.2 general-purpose registers ................................................................................................... 50 3.2.3 special function registers (sfr) ....................................................................................... 52 3.3 instruction address addressing .................................................................................... 56 3.3.1 relative addressing .............................................................................................................. 56 3.3.2 immediate addressing .......................................................................................................... 57 3.3.3 table indirect addressing ..................................................................................................... 58 3.3.4 register addressing ............................................................................................................. 59 3.4 operand address addressing ........................................................................................ 60 3.4.1 implied addressing ............................................................................................................... 60 3.4.2 register addressing ............................................................................................................. 61 3.4.3 direct addressing .................................................................................................................. 62 3.4.4 short direct addressing ........................................................................................................ 63 3.4.5 special function register (sfr) addressing ...................................................................... 64 3.4.6 register indirect addressing ................................................................................................ 65 3.4.7 based addressing ................................................................................................................. 66 3.4.8 based indexed addressing ................................................................................................... 67 3.4.9 stack addressing .................................................................................................................. 67 chapter 4 port functions ...................................................................................................... 68 4.1 port functions ................................................................................................................... 68 4.2 port configuration ............................................................................................................ 70 4.2.1 port 0 ............................................................................................................................... ...... 70 4.2.2 port 1 ............................................................................................................................... ...... 71 4.2.3 port 3 ............................................................................................................................... ...... 72 4.2.4 port 4 ............................................................................................................................... ...... 74 4.2.5 port 5 ............................................................................................................................... ...... 75 4.2.6 port 6 ............................................................................................................................... ...... 76 4.2.7 port 7 ............................................................................................................................... ...... 77 4.2.8 port 12 ............................................................................................................................... .... 80 4.2.9 port 13 ............................................................................................................................... .... 82 4.3 registers controlling port functions ............................................................................ 83 4.4 port function operations ................................................................................................ 87 4.4.1 writing to i/o ports ............................................................................................................... 87 4.4.2 reading from i/o ports ......................................................................................................... 87 4.4.3 operations on i/o ports ........................................................................................................ 87 chapter 5 clock generator ................................................................................................. 88 5.1 functions of clock generator ......................................................................................... 88 5.2 configuration of clock generator .................................................................................. 89 5.3 register controlling clock generator ........................................................................... 90 5.4 system clock oscillator .................................................................................................. 91 5.4.1 system clock oscillator ......................................................................................................... 91 5.4.2 divider ............................................................................................................................... .... 93 5.5 clock generator operations ........................................................................................... 94 5.6 changing system clock and cpu clock settings ....................................................... 95 5.6.1 time required for switching between system clock and cpu clock .................................. 95
12 user? manual u15104ej2v0ud chapter 6 8-bit timer/event counters 50 to 53 ............................................................. 96 6.1 functions of 8-bit timer/event counters 50 to 53 ...................................................... 96 6.2 configuration of 8-bit timer/event counters 50 to 53 ................................................ 99 6.3 registers controlling 8-bit timer/event counters 50 to 53 ....................................... 101 6.4 operations of 8-bit timer/event counters 50 to 53 ..................................................... 105 6.4.1 operation as interval timer (8-bit) ........................................................................................ 105 6.4.2 operation as external event counter (timers 50 to 52) ....................................................... 109 6.4.3 square wave output operation (8-bit resolution) (timers 50 to 52) .................................... 110 6.4.4 8-bit pwm output operation (timers 50 to 52) ..................................................................... 111 6.4.5 interval timer operation (16-bit) ........................................................................................... 114 6.5 notes on 8-bit timer/event counters 50 to 53 ............................................................. 115 chapter 7 basic timer ............................................................................................................... 117 7.1 function of basic timer .................................................................................................. 117 7.2 configuration of basic timer .......................................................................................... 117 7.3 operation of basic timer ................................................................................................. 118 chapter 8 watchdog timer .................................................................................................... 119 8.1 functions of watchdog timer ........................................................................................ 119 8.2 configuration of watchdog timer .................................................................................. 121 8.3 registers controlling watchdog timer ......................................................................... 121 8.4 operations of watchdog timer ....................................................................................... 125 8.4.1 watchdog timer operation .................................................................................................... 125 8.4.2 interval timer operation ........................................................................................................ 126 chapter 9 buzzer output controller ............................................................................. 127 9.1 functions of buzzer output controllers ....................................................................... 127 9.2 configuration of buzzer output controllers ................................................................. 128 9.3 registers controlling buzzer output controllers ........................................................ 128 9.3.1 beep0 ............................................................................................................................... .... 128 9.3.2 buz ............................................................................................................................... ........ 129 9.4 operation of buzzer output controllers ....................................................................... 129 chapter 10 a/d converter ...................................................................................................... 130 10.1 functions of a/d converter ............................................................................................. 130 10.2 configuration of a/d converter ...................................................................................... 130 10.3 registers controlling a/d converter ............................................................................. 133 10.4 operations of a/d converter ........................................................................................... 136 10.4.1 basic operations of a/d converter ....................................................................................... 136 10.4.2 input voltage and conversion results ................................................................................... 138 10.4.3 a/d converter operating mode ............................................................................................. 139 10.5 notes on a/d converter ................................................................................................... 145 chapter 11 serial interfaces sio30 to sio32 ................................................................. 147 11.1 functions of serial interfaces sio30 to sio32 ............................................................. 147 11.2 configuration of serial interfaces sio30 to sio32 ...................................................... 149 11.3 registers controlling serial interfaces sio30 to sio32 ............................................. 150 11.4 operations of serial interfaces sio30 to sio32 ........................................................... 152 11.4.1 operation stop mode ............................................................................................................ 152 11.4.2 3-wire serial i/o mode .......................................................................................................... 153
13 user? manual u15104ej2v0ud chapter 12 interrupt functions ......................................................................................... 156 12.1 interrupt function types ................................................................................................. 156 12.2 interrupt sources and configuration ............................................................................. 156 12.3 registers controlling interrupt functions .................................................................... 160 12.4 interrupt servicing operations ....................................................................................... 166 12.4.1 non-maskable interrupt request acknowledgement operation ........................................... 166 12.4.2 maskable interrupt request acknowledgement operation ................................................... 169 12.4.3 software interrupt request acknowledgement operation .................................................... 172 12.4.4 multiple interrupt servicing ................................................................................................... 173 12.4.5 pending interrupt requests ................................................................................................... 176 chapter 13 pll frequency synthesizer ........................................................................... 177 13.1 function of pll frequency synthesizer ....................................................................... 177 13.2 configuration of pll frequency synthesizer .............................................................. 179 13.3 registers controlling pll frequency synthesizer ..................................................... 181 13.4 operation of pll frequency synthesizer ..................................................................... 185 13.4.1 operation of each block of pll frequency synthesizer ...................................................... 185 13.4.2 operation to set n value of pll frequency synthesizer ..................................................... 189 13.5 pll disable status ........................................................................................................... 194 13.6 notes on pll frequency synthesizer ........................................................................... 194 chapter 14 frequency counter ........................................................................................... 195 14.1 function of frequency counter ...................................................................................... 195 14.2 configuration of frequency counter ............................................................................. 195 14.3 registers controlling frequency counter .................................................................... 197 14.4 operation of frequency counter .................................................................................... 199 14.5 notes on frequency counter .......................................................................................... 201 chapter 15 standby function .............................................................................................. 203 15.1 standby function and configuration ............................................................................. 203 15.1.1 standby function ................................................................................................................... 203 15.1.2 register controlling standby function .................................................................................. 204 15.2 operations of standby function .................................................................................... 205 15.2.1 halt mode ........................................................................................................................... 205 15.2.2 stop mode .......................................................................................................................... 208 chapter 16 reset function .................................................................................................... 211 16.1 reset function .................................................................................................................. 211 16.2 power failure detection function .................................................................................. 218 16.3 4.5 v voltage detection function ................................................................................... 219 chapter 17 pd178f054 ............................................................................................................... 220 17.1 memory size switching register (ims) .......................................................................... 221 17.2 internal expansion ram size switching register (ixs) .............................................. 222 17.3 flash memory programming ........................................................................................... 223 17.3.1 selecting communication mode ........................................................................................... 223 17.3.2 flash memory programming function .................................................................................. 224 17.3.3 connecting flashpro iii ........................................................................................................ 224 17.3.4 setting example for flashpro iii (pg-fp3) .......................................................................... 225
14 user? manual u15104ej2v0ud chapter 18 instruction set ................................................................................................... 226 18.1 conventions ....................................................................................................................... 227 18.1.1 operand symbols and description ....................................................................................... 227 18.1.2 description of ?peration?column ........................................................................................ 228 18.1.3 description of ?lag operation?column ................................................................................ 228 18.2 operation list .................................................................................................................... 229 18.3 instructions listed by addressing type ....................................................................... 237 chapter 19 electrical specifications .............................................................................. 240 chapter 20 package drawing ............................................................................................... 250 chapter 21 recommended soldering conditions ........................................................ 251 appendix a development tools ............................................................................................ 252 a.1 software package ............................................................................................................. 255 a.2 language processing software ...................................................................................... 255 a.3 control software ............................................................................................................... 256 a.4 flash memory writing tools ........................................................................................... 256 a.5 debugging tools (hardware) .......................................................................................... 257 a.6 debugging tools (software) ........................................................................................... 259 a.7 embedded software ......................................................................................................... 260 a.8 system upgrade from former in-circuit emulator for 78k/0 series to ie-78001-r-a .......................................................................................... 261 appendix b register index ...................................................................................................... 264 b.1 register index ................................................................................................................... 264 b.2 register index (symbol) .................................................................................................. 267 appendix c revision history .................................................................................................. 270
15 user? manual u15104ej2v0ud list of figures (1/4) figure no. title page 2-1 pin i/o circuits ............................................................................................................................... ..... 36 3-1 memory map of pd178053 .............................................................................................................. 39 3-2 memory map of pd178054 .............................................................................................................. 40 3-3 memory map of pd178f054 ............................................................................................................ 41 3-4 data memory addressing of pd178053 .......................................................................................... 44 3-5 data memory addressing of pd178054 .......................................................................................... 45 3-6 data memory addressing of pd178f054 ........................................................................................ 46 3-7 configuration of program counter ..................................................................................................... 47 3-8 configuration of program status word .............................................................................................. 47 3-9 configuration of stack pointer ........................................................................................................... 49 3-10 data to be saved to stack memory ................................................................................................... 49 3-11 data to be restored from stack memory .......................................................................................... 49 3-12 configuration of general-purpose register ...................................................................................... 51 4-1 port types ............................................................................................................................... ............ 68 4-2 block diagram of p00 to p04 ............................................................................................................. 70 4-3 block diagram of p05 and p06 .......................................................................................................... 71 4-4 block diagram of p10 to p15 ............................................................................................................. 71 4-5 block diagram of p30 to p32 and p35 .............................................................................................. 72 4-6 block diagram of p33 and p34 .......................................................................................................... 73 4-7 block diagram of p36 and p37 .......................................................................................................... 73 4-8 block diagram of p40 to p47 ............................................................................................................. 74 4-9 block diagram of key input detector ................................................................................................ 75 4-10 block diagram of p50 to p57 ............................................................................................................. 75 4-11 block diagram of p60 to p67 ............................................................................................................. 76 4-12 block diagram of p70, p74, and p77 ................................................................................................ 77 4-13 block diagram of p71 and p75 .......................................................................................................... 78 4-14 block diagram of p72 and p76 .......................................................................................................... 78 4-15 block diagram of p73 ......................................................................................................................... 79 4-16 block diagram of p120 and p123 ...................................................................................................... 80 4-17 block diagram of p121 and p124 ...................................................................................................... 81 4-18 block diagram of p122 and p125 ...................................................................................................... 81 4-19 block diagram of p130 to p132 ......................................................................................................... 82 4-20 format of port mode registers .......................................................................................................... 85 4-21 format of pull-up resistor option register 4 (pu4) ......................................................................... 86 5-1 format of dts system clock select register (dtsck) .................................................................. 88 5-2 block diagram of clock generator .................................................................................................... 89 5-3 format of processor clock control register (pcc) ......................................................................... 90 5-4 external circuit of system clock oscillator ....................................................................................... 91 5-5 examples of incorrect resonator connection ................................................................................... 92
16 user? manual u15104ej2v0ud list of figures (2/4) figure no. title page 6-1 block diagram of 8-bit timer/event counter 50 ............................................................................... 97 6-2 block diagram of 8-bit timer/event counter 51 ............................................................................... 97 6-3 block diagram of 8-bit timer/event counter 52 ............................................................................... 98 6-4 block diagram of 8-bit timer 53 ........................................................................................................ 98 6-5 format of timer clock select registers 50 to 52 (tcl50 to tcl52) .............................................. 101 6-6 format of timer clock select register 53 (tcl53) .......................................................................... 102 6-7 format of 8-bit timer mode control registers 50 to 52 (tmc50 to tmc52) ................................. 103 6-8 format of 8-bit timer mode control register 53 (tmc53) .............................................................. 104 6-9 timing of interval timer operation .................................................................................................... 106 6-10 operation timing of external event counter (with rising edge specified) ..................................... 109 6-11 timing of square output operation ................................................................................................... 110 6-12 operation timing of pwm output ...................................................................................................... 112 6-13 timing of operation when cr5n is changed ................................................................................... 113 6-14 operation timing of 16-bit resolution cascade mode (timers 50 and 51) .................................... 115 6-15 start timing of 8-bit timer counter ................................................................................................... 115 6-16 timing after changing compare register value during timer count operation ........................... 116 7-1 block diagram of basic timer ............................................................................................................ 117 7-2 operation timing of basic timer ....................................................................................................... 118 7-3 operating timing to poll btmif0 flag .............................................................................................. 118 8-1 block diagram of watchdog timer .................................................................................................... 119 8-2 format of watchdog timer clock select register (wdcs) ............................................................. 122 8-3 format of watchdog timer mode register (wdtm) ........................................................................ 123 8-4 format of oscillation stabilization time select register (osts) .................................................... 124 9-1 block diagram of beep0 .................................................................................................................... 127 9-2 block diagram of buz ........................................................................................................................ 127 9-3 format of beep clock select register 0 (beepcl0) ...................................................................... 128 9-4 format of clock output select register (cks) ................................................................................. 129 10-1 block diagram of a/d converter ........................................................................................................ 131 10-2 format of a/d converter mode register 3 (adm3) .......................................................................... 133 10-3 format of analog input channel specification register 3 (ads3) .................................................. 134 10-4 format of power-fail comparison mode register 3 (pfm3) ........................................................... 135 10-5 a/d converter basic operation .......................................................................................................... 137 10-6 relationship between analog input voltage and a/d conversion result ....................................... 138 10-7 a/d conversion operation .................................................................................................................. 140 10-8 power-fail comparison threshold value register 3 (pft3) ........................................................... 141 10-9 a/d conversion operation in power-fail comparison mode ........................................................... 142 10-10 example of reducing current consumption in standby mode ........................................................ 145 10-11 a/d conversion end interrupt request generation timing .............................................................. 146
17 user? manual u15104ej2v0ud list of figures (3/4) figure no. title page 11-1 block diagram of serial interface sio30 ........................................................................................... 147 11-2 block diagram of serial interface sio31 ........................................................................................... 148 11-3 block diagram of serial interface sio32 ........................................................................................... 148 11-4 format of serial operating mode registers 30 to 32 (csim30 to csim32) ................................... 150 11-5 format of serial port select register 32 (sio32sel) ...................................................................... 151 11-6 timing in 3-wire serial i/o mode ....................................................................................................... 154 12-1 basic configuration of interrupt function .......................................................................................... 158 12-2 format of interrupt request flag registers (if0l, if0h) ................................................................. 161 12-3 format of interrupt mask flag registers (mk0l, mk0h) ................................................................. 162 12-4 format of priority specification flag registers (pr0l, pr0h) ........................................................ 163 12-5 format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) ................................................................... 164 12-6 configuration of program status word (psw) .................................................................................. 165 12-7 flowchart from generation of non-maskable interrupt request to acknowledgement .................. 167 12-8 non-maskable interrupt request acknowledgement timing ............................................................ 167 12-9 non-maskable interrupt request acknowledgement operation ....................................................... 168 12-10 interrupt request acknowledgement processing algorithm ............................................................. 170 12-11 interrupt request acknowledgement timing (minimum time) ......................................................... 171 12-12 interrupt request acknowledgement timing (maximum time) ........................................................ 171 12-13 multiple interrupt servicing example ................................................................................................. 174 12-14 pending interrupt request ................................................................................................................. 176 13-1 block diagram of pll frequency synthesizer .................................................................................. 179 13-2 format of pll mode select register (pllmd) ................................................................................. 181 13-3 format of pll reference mode register (pllrf) ........................................................................... 182 13-4 format of pll unlock f/f judge register (pllul) ......................................................................... 183 13-5 format of pll data transfer register (pllns) ............................................................................... 184 13-6 configuration of input select block and programmable divider ...................................................... 185 13-7 configuration of reference frequency generator ............................................................................ 186 13-8 configuration of phase comparator, charge pump, and unlock f/f .............................................. 186 13-9 relationship between f r , f n , up, and dw .......................................................................................... 187 13-10 configuration of error out output ...................................................................................................... 188 14-1 block diagram of frequency counter ................................................................................................ 196 14-2 format of if counter mode select register (ifcmd) ...................................................................... 197 14-3 format of if counter control register (ifccr) ............................................................................... 198 14-4 format of if counter gate judge register (ifcjg) ......................................................................... 198 14-5 block diagram of input pin and mode selection ............................................................................... 199 14-6 gate timing of frequency counter .................................................................................................... 200 14-7 frequency counter input pin circuit .................................................................................................. 201 14-8 gate status when halt instruction is executed ............................................................................. 201
18 user? manual u15104ej2v0ud list of figures (4/4) figure no. title page 15-1 format of oscillation stabilization time select register (osts) .................................................... 204 15-2 halt mode release upon interrupt generation ............................................................................... 206 15-3 halt mode release by reset input ............................................................................................... 207 15-4 stop mode release by interrupt request generation ................................................................... 209 15-5 release by stop mode reset input .............................................................................................. 210 16-1 reset function block diagram ........................................................................................................... 212 16-2 timing of reset by reset input ....................................................................................................... 213 16-3 timing of reset due to watchdog timer overflow ........................................................................... 214 16-4 timing of reset by power-on clear ................................................................................................... 215 16-5 format of poc status register (pocs) ........................................................................................... 218 16-6 format of poc status register (pocs) ........................................................................................... 219 17-1 format of memory size switching register (ims) ............................................................................ 221 17-2 format of internal expansion ram size switching register (ixs) .................................................. 222 17-3 format of communication mode selection ....................................................................................... 223 17-4 connection of flashpro iii in 3-wire serial i/o mode ....................................................................... 224 a-1 configuration of development tools .................................................................................................. 253 a-2 ev-9200gc-80 package drawing (for reference only) ................................................................... 262 a-3 ev-9200gc-80 recommended board mounting pattern (for reference only) .............................. 263
19 user? manual u15104ej2v0ud list of tables (1/2) table no. title page 2-1 pin i/o circuit type and recommended connections of unused pins ........................................... 35 3-1 internal memory capacities ................................................................................................................ 42 3-2 vector table ............................................................................................................................... ......... 42 3-3 absolute address of general-purpose registers ............................................................................. 50 3-4 special function registers ................................................................................................................. 53 4-1 port functions ............................................................................................................................... ...... 69 4-2 port configuration ............................................................................................................................... 70 4-3 port mode register and output latch settings when using alternate functions .......................... 84 5-1 configuration of clock generator ...................................................................................................... 89 5-2 maximum time required for cpu clock switching .......................................................................... 95 6-1 configuration of 8-bit timer/event counters 50 to 53 ...................................................................... 99 8-1 watchdog timer inadvertent program loop detection times ......................................................... 120 8-2 interval time ............................................................................................................................... ........ 120 8-3 configuration of watchdog timer ...................................................................................................... 121 8-4 watchdog timer inadvertent program loop detection time ........................................................... 125 8-5 interval timer interval time ............................................................................................................... 126 9-1 configuration of buzzer output controllers ....................................................................................... 128 10-1 configuration of a/d converter .......................................................................................................... 130 11-1 configuration of serial interfaces sio30 to sio32 ........................................................................... 149 12-1 interrupt sources ............................................................................................................................... . 157 12-2 various flags corresponding to interrupt request sources ............................................................ 160 12-3 times from maskable interrupt request generation to interrupt servicing .................................... 169 12-4 interrupt request enabled for multiple interrupt servicing during interrupt servicing ................... 173 13-1 division mode, input pin, and division value .................................................................................... 178 13-2 configuration of pll frequency synthesizer .................................................................................... 179 13-3 error out output signal ...................................................................................................................... 188 13-4 operation of each block and register status in pll disabled status ............................................ 194 14-1 configuration of frequency counter .................................................................................................. 195 15-1 halt mode operating status ............................................................................................................ 205 15-2 operation after halt mode release ................................................................................................ 207 15-3 stop mode operating status ............................................................................................................ 208 15-4 operation after stop mode release ............................................................................................... 210
20 user? manual u15104ej2v0ud list of tables (2/2) table no. title page 16-1 hardware status after reset ............................................................................................................. 216 17-1 differences between pd178f054 and mask rom versions ......................................................... 220 17-2 set value of memory size switching register .................................................................................. 221 17-3 set value of internal expansion ram size switching register ....................................................... 222 17-4 communication modes ....................................................................................................................... 223 17-5 major functions of flash memory programming .............................................................................. 224 17-6 setting example for flashpro iii (pg-fp3) ........................................................................................ 225 18-1 operand symbols and descriptions .................................................................................................. 227 21-1 surface mounting type soldering conditions ................................................................................... 251 a-1 system upgrade method from former in-circuit emulator for 78k/0 series to ie-78001-r-a ............................................................................................................ 261
21 user? manual u15104ej2v0ud chapter 1 outline 1.1 features internal rom and ram item program memory data memory part number internal high-speed ram pd178053 rom 24 kb 1024 bytes pd178054 32 kb pd178f054 flash memory 32 kb instruction set suitable for system control bit processing across entire address space multiplication/division instructions general-purpose i/o ports: 62 pins hardware for pll frequency synthesizer dual modulus prescaler (160 mhz max.) programmable divider phase comparator charge pump frequency counter 8-bit resolution a/d converter: 6 channels serial interface: 3 channels 3-wire serial i/o mode: 2 channels 3-wire serial i/o mode (on-chip time-division transfer function): 1 channel timer: 6 channels basic timer (timer carry ff): 1 channel 8-bit timer/event counter: 4 channels watchdog timer: 1 channel buzzer output vectored interrupt item non-maskable maskable interrupt note software interrupt part number interrupt note external internal pd178053, 178054, 178f054 1 source 5 sources 11 sources 1 source note either a non-maskable interrupt or maskable interrupt (internal) can be selected as the interrupt source of the watchdog timer (intwdt). test input: 1 pin instruction cycle: 0.45/0.89/1.78/3.56/7.11 s (with 4.5 mhz crystal resonator) supply voltage: v dd = 4.5 to 5.5 v (with cpu, pll operating) v dd = 3.5 to 5.5 v (with cpu operating) power-on clear circuit
22 chapter 1 outline user? manual u15104ej2v0ud 1.2 applications car stereos 1.3 ordering information part number package pd178053gc- -8bt 80-pin plastic qfp (14 remark
23 chapter 1 outline user s manual u15104ej2v0ud 1.4 pin configuration (top view) 80-pin plastic qfp (14 14) cautions 1. directly connect the ic (internally connected) pin and v pp pin to gnd. 2. keep the v dd port and v dd pll pins as same potential as that at the v dd pin. 3. keep the gndport and gndpll pins as same potential as that at gnd. 4. connect each of the regosc and regcpu pins to gnd via a 0.1 f capacitor. remark ( ):
24 chapter 1 outline user? manual u15104ej2v0ud pin name amifc: am intermediate frequency counter input ani0 to ani5: a/d converter input beep0, buz: buzzer output eo0, eo1: error out output fmifc: fm intermediate frequency counter input gnd: ground gndpll: pll ground gndport: port ground ic: internally connected intp0 to intp4: interrupt input p00 to p06: port 0 p10 to p15: port 1 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p77: port 7 p120 to p125: port 12 p130 to p132: port 13 regcpu: regulator for cpu power supply regosc: regulator for oscillator reset: reset input sck30, sck31,: serial (sio3) clock input/output sck32, sck321 si30, si31, si32,: serial (sio3) data input si321 so30, so31,: serial (sio3) data output so32, so321 ti50 to ti52: 8-bit timer clock input to50 to to52: 8-bit timer output vcol, vcoh: local oscillation input v dd : power supply v dd pll: pll power supply v dd port: port power supply v pp note : programming power supply x1, x2: crystal resonator note pd178f054 only
25 chapter 1 outline user? manual u15104ej2v0ud products in mass production products under development pd178f098 on-chip uart limits functions of pd178018a subseries 100 pins 100 pins pd178p018a 80 pins 80 pins 100 pins 80 pins pd178098 subseries pd178078 subseries pd178018a subseries pd178003 subseries pd178f054 enhanced timer, 3-wire serial i/o 80 pins 80 pins pd178054 subseries pd178f124 on-chip iebus controller 80 pins 80 pins pd178024 subseries on-chip iebus tm controller, uart enhanced timer, 3-wire serial i/o on-chip uart pd178f048 on-chip osd controller 8-bit pwm 4 channels 14-bit pwm 1 channel 80 pins 80 pins pd178048 subseries on-chip osd controller 8-bit pwm 4 channels 14-bit pwm 1 channel mask rom version flash memory version or prom version on-chip uart 1.5 development of 8-bit dts series
26 chapter 1 outline user s manual u15104ej2v0ud 1.6 block diagram remarks 1. the internal rom capacity differs depending on the product. 2. ( ): pd178f054 8-bit timer/ event counter50 8-bit timer/ event counter51 serial interface30 interrupt control system control serial interface32 voltage regulator watchdog timer basic timer port 0 port 1 port 3 port 4 port 5 port 6 port 7 port 12 port 13 7 6 8 8 8 8 8 6 5 3 6 pll a/d converter frequency counter pll voltage regulator buzzer output 78k/0 cpu core ram 1024 bytes rom flash memory ti50/p33 to50/p130 p00 to p06 p10 to p15 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 p120 to p125 p130 to p132 ani0/p10 to ani5/p15 amifc fmifc eo0 eo1 vcol vcoh v dd pll gndpl ic (v pp ) l si30/p70 so30/p71 sck30/p72 serial interface31 si31/p74 so31/p75 sck31/p76 si32/p120 so32/p121 sck32/p122 si321/p123 so321/p124 sck321/p125 intp0/p00 to intp4/p04 beep0/p36 buz/p37 reset x1 x2 v dd port gndport v dd reset cpu peripheral v osc v cpu regosc regcpu gnd ti51/p34 to51/p131 8-bit timer/ event counter52 8-bit timer53 ti52/p77 to52/p132
27 chapter 1 outline user s manual u15104ej2v0ud 1.7 functional outline item pd178053 pd178054 pd178f054 internal rom 24 kb 32 kb 32 kb (mask rom) (mask rom) (flash memory) high-speed ram 1024 bytes general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.45 s/0.89 s/1.78 s/3.56 s/7.11 s (with crystal resonator of f x = 4.5 mhz) instruction set 16-bit operation multiplication/division (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjustment, etc. i/o ports total: 62 pins cmos i/o: 53 pins cmos input: 6 pins n-ch open-drain output: 3 pins a/d converter 8-bit resolution 6 channels serial interface 3-wire serial i/o mode: 2 channels 3-wire serial i/o mode (on-chip time-division transfer): 1 channel timer basic timer (timer carry ff (10 hz)) : 1 channel 8-bit timer/event counter: 4 channels watchdog timer: 1 channel buzzer output beep pin: 1 khz, 1.5 khz, 3 khz, 4 khz buz pin: 549 hz, 1.10 khz, 2.20 khz, 4.39 khz vectored maskable internal : 11 interrupt external: 5 sources non-maskable internal: 1 software 1 pll division mode 2 types frequency direct division mode (vcol pin) synthesizer pulse swallow mode (vcol and vcoh pins) reference frequency seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 khz) charge pump error out output: 2 pins phase comparator unlock detectable with program frequency counter frequency measurement amifc pin: for 450 khz counting fmifc pin: for 450 khz/10.7 mhz counting reset reset by reset pin internal reset by watchdog timer reset by power-on clear circuit detection of less than 4.5 v note (reset does not occur, however) detection of less than 3.5 v note (during cpu operation) detection of less than 2.2 v note (in stop mode) supply voltage v dd = 4.5 to 5.5 v (during cpu, pll operation) v dd = 3.5 to 5.5 v (during cpu operation) package 80-pin plastic qfp (14 14) note for details, refer to chapter 16 reset function .
28 user? manual u15104ej2v0ud chapter 2 pin function 2.1 pin function list (1) port pins pin name i/o function after reset alternate function p00 to p04 i/o port 0 input intp0 to intp4 7-bit i/o port p05, p06 input/output can be specified in 1-bit units. p10 to p15 input port 1 input ani0 to ani5 6-bit input port p30 to p32 i/o port 3 input p33 8-bit i/o port. ti50 p34 input/output can be specified in 1-bit units. ti51 p35 p36 beep0 p37 buz p40 to 47 i/o port 4 input 8-bit i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by software. interrupt function by key input is provided. p50 to p57 i/o port 5 input 8-bit i/o port input/output can be specified in 1-bit units. p60 to p67 i/o port 6. input 8-bit i/o port. input/output can be specified in 1-bit units. p70 i/o port 7 input si30 p71 8-bit i/o port so30 p72 input/output can be specified in 1-bit units. sck30 p73 p74 si31 p75 so31 p76 sck31 p77 ti52 p120 i/o port 12 input si32 p121 6-bit i/o port so32 p122 input/output can be specified in 1-bit units. sck32 p123 si321 p124 so321 p125 sck321 p130 output port 13 low-level to50 p131 3-bit output port output to51 p132 n-ch open-drain output port (12 v tolerance) to52
29 chapter 2 pin function user? manual u15104ej2v0ud (2) pins other than port pins pin name i/o function after reset alternate function intp0 to intp4 input external maskable interrupt input whose valid edge input p00 to p04 (rising edge, falling edge, or both rising and falling edges) can be specified si30 input serial data input to serial interface. input p70 s131 p74 s132 p120 si321 p123 so30 output serial data output from serial interface. input p71 so31 p75 so32 p121 so321 p124 sck30 i/o serial clock input/output to/from serial interface. input p72 sck31 p76 sck32 p122 sck321 p125 ti50 input external count clock input to 8-bit timer 50 input p33 ti51 external count clock input to 8-bit timer 51 p34 ti52 external count clock input to 8-bit timer 52 p77 to50 output 8-bit timer 50 output low-level p130 to51 8-bit timer 51 output output p131 to52 8-bit timer 52 output p132 beep0 output buzzer output input p36 buz p37 ani0 to ani5 input analog input to a/d converter input p10 to p15 eo0, eo1 output error out output from charge pump of pll frequency synthesizer vcol input inputs local oscillation frequency of pll (in hf and mf modes) vcoh inputs local oscillation frequency of pll (in vhf mode) amifc input input to am intermediate frequency counter input fmifc input to fm or am intermediate frequency counter reset input system reset input x1 input connection of crystal resonator for system clock oscillation. x2 regosc regulator for oscillator. connect this pin to gnd via 0.1 f capacitor. regcpu regulator for cpu power supply. connect this pin to gnd via 0.1 f capacitor. v dd positive power supply gnd ground v dd port port power supply gndport port ground v dd pll note 1 pll positive power supply gndpll note 1 pll ground ic internally connected. directly connect this pin to gnd. v pp note 2 pin to apply high voltage at program writing/verifying. directly connect this pin to gnd in normal operating mode. notes 1. connect a capacitor of about 1000 pf between the v dd pll and gndpll pins. 2. pd178f054 only.
30 chapter 2 pin function user? manual u15104ej2v0ud 2.2 description of pin functions 2.2.1 p00 to p06 (port 0) p00 to p06 constitute a 7-bit i/o port. in addition to i/o port pins, p00 to p06 also function as external interrupt inputs. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 7-bit i/o port for which input or output can be specified in 1-bit units using port mode register 0 (pm0). (2) control mode these pins function as external interrupt input pins (intp0 to intp4). these external interrupt input pins can specify valid edges (rising edge, falling edge, and both rising and falling edges). 2.2.2 p10 to p15 (port 1) p10 to p15 constitute a 6-bit input port. in addition to input port pins, p10 to p15 function as a/d converter analog inputs. the following operating modes can be specified in 1 bit units. (1) port mode these pins function as a 6-bit input port. (2) control mode these pins function as a/d converter analog input pins (ani0 to ani5). 2.2.3 p30 to p37 (port 3) p30 to p37 constitute an 8-bit i/o port . in addition to i/o port pins, p30 to p37 function as timer inputs and buzzer outputs. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit i/o port for which input or output can be specified in 1-bit units using port mode register 3 (pm3). (2) control mode these pins function as timer inputs (ti50, t51) and buzzer outputs (beep0, buz). (a) ti50, ti51 pins for external clock input to the 8-bit timer/event counter. (b) beep0, buz buzzer output pins.
31 chapter 2 pin function user? manual u15104ej2v0ud 2.2.4 p40 to p47 (port 4) p40 to p47 constitute an 8-bit i/o port. these pins can be specified as input or output in 1-bit units using port mode register 4 (pm4). on-chip pull-up resistors can be specified by pull-up resistor option register 4 (pu4). an interrupt function via key input is also provided. 2.2.5 p50 to p57 (port 5) p50 to p57 constitute an 8-bit i/o port. these pins can be specified as input or output in 1-bit units using port mode register 5 (pm5). 2.2.6 p60 to p67 (port 6) p60 to p67 constitute an 8-bit port. these pins can be specified as input or output in 1-bit units using port mode register 6 (pm6). 2.2.7 p70 to p77 (port 7) p70 to p77 pins constitute an 8-bit i/o port. in addition to port pins, p70 to p77 also function as serial interface data i/o, clock i/o, and a timer input. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit i/o port for which input or output can be specified in 1-bit units using port mode register 7 (pm7). (2) control mode these pins function as serial interface data i/o, clock i/o, and timer input pins. (a) si30, so30, si31, so31 serial data i/o pins of the serial interface. (b) sck30, sck31 serial clock i/o pins of the serial interface. (c) ti52 external clock input pin to 8-bit timer/event counter.
32 chapter 2 pin function user? manual u15104ej2v0ud 2.2.8 p120 to p125 (port 12) p120 to p125 constitute a 6-bit i/o port. in addition to i/o port pins, p120 to p125 also function as serial interface data i/o and clock i/o. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit i/o port for which input or output can be specified in 1-bit units using port mode register 7 (pm7). (2) control mode these pins function as serial interface data i/o and clock i/o pins. (a) si32, so32, si321, so321 serial data i/o pins of the serial interface. (b) sck32, sck321 serial clock i/o pins of the serial interface. 2.2.9 p130 to p132 (port 13) p130 to p132 constitute a 3-bit n-ch open-drain output port with a 12 v tolerance. in addition to output port pins, p130 to p132 also function as timer outputs. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 3-bit output port. (2) control mode these pins function as output pins for the 8-bit timer/event counter. to50, to51, to52 these pins are output pins for the 8-bit timer/event counter. 2.2.10 eo0, eo1 these are the output pins of the charge pump of the pll frequency synthesizer. they output the result of phase comparison between the frequency divided by the programmable divider of the local oscillation input (vcol and vcoh pins) and the reference frequency. 2.2.11 vcol, vcoh these pins input the local oscillation frequency (vco) of the pll. because signals are input to these pins via an ac amplifier, cut the dc component of the input signals using a capacitor. vcol hf, mf input this pin becomes active when the hf or mf mode is selected by software; otherwise, the pin is in the status set by bit 2 (vcoldmd) of the pll mode select register (pllmd). if vcoldmd is reset to 0 (to connect a pull-down resistor), however, the vcol pin does not become active even if the hf or mf mode is selected. in this case, set vcoldmd to 1 (high-impedance state).
33 chapter 2 pin function user? manual u15104ej2v0ud vcoh vhf input this pin becomes active when the fm mode is selected by software; otherwise the pin is in the status set by bit 3 (vcohdmd) of the pll mode select register (pllmd). if vcohdmd is reset to 0 (to connect a pull-down resistor), however, the vcol pin does not become active even if the fm mode is selected. in this case, set vcohdmd to 1 (high-impedance state). 2.2.12 amifc input pin of the am intermediate frequency counter. 2.2.13 fmifc input pin of the fm intermediate frequency counter or am intermediate frequency counter. 2.2.14 reset low-level active system reset input pin. 2.2.15 x1, x2 crystal resonator connection pins for system clock oscillation. 2.2.16 regosc regulator pin for oscillator. connect to gnd via a 0.1 f capacitor. 2.2.17 regcpu regulator pin for cpu power supply. connect to gnd via a 0.1 f capacitor. 2.2.18 v dd positive power supply pin. 2.2.19 gnd ground potential pin. 2.2.20 v dd port positive power supply pin for port. 2.2.21 gndport ground potential pin for port. 2.2.22 v dd pll positive power supply pin for pll. 2.2.23 gndpll ground potential pin for pll. 2.2.24 v pp ( pd178f054 only) this pin applies a high voltage when the flash memory programming mode is set or when a program is written or verified. in the normal operation mode, directly connect this pin to gnd.
34 chapter 2 pin function user? manual u15104ej2v0ud 2.2.25 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd178054 subseries at delivery. connect it directly to the gnd pin with the shortest possible wire in the normal operating mode. when a potential difference is produced between the ic pin and gnd pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the user's program may not run normally. connect ic pin to gnd pin directly. gnd ic as short as possible
35 chapter 2 pin function user s manual u15104ej2v0ud 2.3 pin i/o circuits and recommended connections of unused pins table 2-1 shows the types of the i/o circuits of the respective pins and the recommended connections of the pins when they are not used. for the configuration of the i/o circuit of each pin, refer to figure 2-1. table 2-1. pin i/o circuit type and recommended connections of unused pins pin name i/o circuit type i/o recommended connection of unused pin p00/intp0 to p04/intp4 8 i/o input: connect to v dd , v dd port, gnd, or gndport via a resistor. p05, p06 output: leave open. p10/ani0 to p15/ani5 25 input connect to v dd , v dd port, gnd, or gndport. p30 to p32 5 i/o input: connect to v dd , v dd port, gnd, or gndport via a resistor. p33/ti50 5-k output: leave open. p34/ti51 p35 5 p36/beep0 p37/buz p40 to p47 5-a p50 to p57 5 p60 to p67 p70/si30 5-k p71/so30 5 p72/sck30 5-k p73 5 p74/si31 5-k p75/so31 5 p76/sck31 5-k p77/ti52 p120/si32 p121/so32 5 p122/sck32 5-k p123/si321 p124/so321 5 p125/sck321 5-k p130/to50 19 output leave open. p131/to51 p132/to52 eo0, eo1 dts-eo1 vcol, vcoh dts-amp input disable pll in software and select pull-down. amifc, fmifc set these pins in general-purpose input port mode by software and connect each of them to v dd , v dd port, gnd, or gndport via a resistor. regosc, regcpu connect these pins to gnd via 0.1 f capacitor. reset 2 input v dd pll connect to v dd . gndpll directly connect to gnd or gndport. ic (mask rom version) v pp ( pd178f054)
36 chapter 2 pin function user s manual u15104ej2v0ud figure 2-1. pin i/o circuits (1/2) remark v dd and gnd are the positive power supply and ground pins for all port pins. read v dd and gnd as v dd port and gndport. type 2 type 5 type 5-a type 5-k type 8 type 19 in schmitt-triggered input with hysteresis characteristics v dd p-ch p-ch n-ch in/out pull-up enable data output disable input enable v dd p-ch n-ch in/out data output disable v dd p-ch n-ch in/out data output disable input enable v dd p-ch n-ch in/out data output disable input enable v dd out n-ch
37 chapter 2 pin function user s manual u15104ej2v0ud figure 2-1. pin i/o circuits (2/2) note this switch is selectable by software only for the vcol and vcoh pins. remark v dd and gnd are the positive power supply and ground pins for all port pins. read v dd and gnd as v dd port and gndport. type 25 input enable comparator + n-ch p-ch v ref (threshold voltage) in type dts-eo1 v dd pll gndpll dw up p-ch out v dd pll gndpll n-ch note type 25 in
38 user? manual u15104ej2v0ud chapter 3 cpu architecture 3.1 memory space the initial value of the memory size switching register (ims) is cfh. the following values must be set to the registers of each model. part number ims pd178053 c6h pd178054 c8h pd178f054 value equivalent to mask rom version
39 chapter 3 cpu architecture user? manual u15104ej2v0ud (1) pd178053 set the value of the memory size switching register (ims) to c6h. the initial value is cfh. figure 3-1. memory map of pd178053 ffffh 0000h ff00h feffh fee0h fedfh fb00h faffh 6000h 5fffh 0000h 5fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh special function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 24576 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area
40 chapter 3 cpu architecture user s manual u15104ej2v0ud (2) pd178054 set the value of the memory size switching register (ims) to c8h. the initial value is cfh. figure 3-2. memory map of pd178054 ffffh 0000h ff00h feffh fee0h fedfh fb00h faffh 8000h 7fffh 0000h 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh special function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 32768 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area
41 chapter 3 cpu architecture user s manual u15104ej2v0ud (3) pd178f054 set the value of the memory size switching register (ims) to the value corresponding to that of the mask rom versions. the initial value is cfh. figure 3-3. memory map of pd178f054 ffffh 0000h ff00h feffh fee0h fedfh fb00h faffh 8000h 7fffh 0000h 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh special function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 32768 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area
42 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.1.1 internal program memory space programs and table data are stored in internal program memory space, and are usually addressed by the program counter (pc). the pd178054 subseries has internal rom (or flash memory) as shown in the following table. table 3-1. internal memory capacities part number structure capacity pd178053 mask rom 24576 8 bits (0000f to 5fffh) pd178054 32768 8 bits (0000h to 7fffh) pd178f054 flash memory the following areas are assigned to the internal program memory space. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. table 3-2. vector table vector table address interrupt request 0004h intwdt 0006h intp0 0008h intp1 000ah intp2 000ch intp3 000eh intp4 0010h intky 0012h intcsi31 0014h intbtm0 0016h intad3 0018h intcsi32 001ah intcsi30 001ch inttm50 001eh inttm51 0020h inttm52 0022h inttm53 003eh brk
43 chapter 3 cpu architecture user s manual u15104ej2v0ud (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 3.1.2 internal data memory space the pd178054 subseries products incorporate the following rams. (1) internal high-speed ram the pd178053, 178054, and 178f054 have a ram structure of 1024 8 bits. in this area, four banks of general-purpose registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area fee0h to feffh. the internal high-speed ram can also be used as a stack memory area. 3.1.3 special function register (sfr) area an on-chip peripheral hardware special function register (sfr) is allocated in the area ff00h to ffffh. refer to table 3-4 special function registers . caution do not access addresses where the sfr is not assigned.
44 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.1.4 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. the address of an instruction to be executed next is addressed by the program counter (pc) (for details, refer to 3.3 instruction address addressing ). several addressing modes are provided for addressing the memory relevant to the execution of instructions for the pd178054 subseries, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general- purpose registers are available for use. data memory addressing is illustrated in figures 3-4 to 3-6. for the details of each addressing mode, refer to 3.4 operand address addressing . figure 3-4. data memory addressing of pd178053 ffffh ff20h ff1fh ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh 6000h 5fffh 0000h special function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 24576 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
45 chapter 3 cpu architecture user s manual u15104ej2v0ud figure 3-5. data memory addressing of pd178054 ffffh ff20h ff1fh ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh 8000h 7fffh 0000h special function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved internal rom 32768 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
46 chapter 3 cpu architecture user s manual u15104ej2v0ud figure 3-6. data memory addressing of pd178f054 ffffh ff20h ff1fh ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh 8000h 7fffh 0000h special function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 32768 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
47 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.2 processor registers the pd178054 subseries units incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-7. configuration of program counter pc15 pc pc14 pc13 pc12 pc11 pc9 pc8 15 0 pc10 pc7 pc6 pc5 pc4 pc3 pc1 pc0 pc2 70 ie z rbs1 ac rbs0 0 isp cy psw (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically restored upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-8. configuration of program status word
48 chapter 3 cpu architecture user s manual u15104ej2v0ud (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when ie = 0, all the interrupts are disabled (di) except the non-maskable interrupt. when ie = 1, the interrupts are enabled (ei). at this time, the acknowledging of interrupts is controlled by the in-service priority flag (isp), the interrupt mask flag corresponding to each interrupt, and the interrupt priority specification flag. the ie is reset to 0 upon di instruction execution or interrupt acknowledgement and is set to 1 upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set to 1. it is reset to 0 in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. it is reset to 0 in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when isp = 0, acknowledging the vectored interrupt requests to which a low priority is assigned by the priority specification flag registers (pr0l, pr0h) (refer to 12.3 (3) priority specification flag registers (pr0l, pr0h ) is disabled. whether an interrupt request is actually accepted depends on the status of the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
49 chapter 3 cpu architecture user s manual u15104ej2v0ud (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area (fb00h to feffh for pd178053, 178054, and 178f054) can be set as the stack area. figure 3-9. configuration of stack pointer the sp is decremented ahead of a write (save) to the stack memory and is incremented after a read (restored) from the stack memory. each stack operation saves/restores data as shown in figures 3-10 and 3-11. caution since reset input makes sp contents undefined, be sure to initialize the sp before instruction execution. figure 3-10. data to be saved to stack memory figure 3-11. data to be restored from stack memory sp15 sp sp14 sp13 sp12 sp11 sp9 sp8 15 0 sp10 sp7 sp6 sp5 sp4 sp3 sp1 sp0 sp2 interrupt and brk instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instruction push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti and retb instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3
50 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.2.2 general-purpose registers the general-purpose registers are mapped at particular address fee0h to feffh in the data memory. they consist of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register and two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be written with function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupt for each bank. table 3-3. absolute address of general-purpose registers bank register absolute function name absolute name address bank0 h r7 f e f f h lr6fefeh dr5fefdh er4fefch br3fefbh cr2fefah ar1fef9h xr0fef8h bank1 h r7 f e f 7 h lr6fef6h dr5fef5h er4fef4h br3fef3h cr2fef2h ar1fef1h xr0fef0h bank register absolute function name absolute name address bank2 h r7 f e e f h l r6 feeeh dr5feedh er4feech b r3 feebh c r2 feeah ar1fee9h xr0fee8h bank3 h r7 f e e 7 h lr6fee6h dr5fee5h er4fee4h br3fee3h cr2fee2h ar1fee1h xr0fee0h
51 chapter 3 cpu architecture user s manual u15104ej2v0ud figure 3-12. configuration of general-purpose register (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fee0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h
52 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.2.3 special function registers (sfr) unlike a general-purpose register, each special function register has special functions. sfrs are allocated in the ff00h to ffffh area. sfrs are can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions. the manipulatable bit units: 1, 8, and 16, depends on the special function register type. the manipulatable bit units can be specified as follows. 1-bit manipulation use the symbol reserved in the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation use the symbol reserved in the assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation use the symbol reserved in the assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, use an even address. table 3-4 gives a list of special function registers. the meanings of items in the table are as follows. symbol this is a symbol to indicate an address of the special function register. these symbols are reserved for the df178054 and ra78k0, and defined by header file sfrbit.h for the cc78k0. they can be written as instruction operands when the ra78k0, id78k0, or id78k0-ns is used. r/w indicates whether the corresponding special function register can be read or written. r/w: read/write enable r: read only r&reset: read only (reset to 0 when read) w: write only bit units for manipulation indicates the manipulatable bit units: 1, 8, and 16. indicates the bit units that cannot be manipulated. after reset indicates each register status upon reset. the values of special function registers whose addresses are not shown in the table are undefined at reset.
53 chapter 3 cpu architecture user s manual u15104ej2v0ud table 3-4. special function registers (1/3) address special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits ff00h port 0 p0 r/w 00h ff01h port 1 p1 r ff03h port 3 p3 r/w ff04h port 4 p4 ff05h port 5 p5 ff06h port 6 p6 ff07h port 7 p7 ff0ch port 12 p12 ff0dh port 13 p13 ff10h a/d conversion result register 3 note 1 adcr3 ff11h r undefined ff12h a/d converter mode register 3 adm3 r/w 00h ff13h analog input channel specification register 3 ads3 ff15h power-fail comparison threshold value register 3 pft3 ff16h power-fail comparison mode register 3 pfm3 ff1bh poc status register pocs r&reset retained note 2 ff20h port mode register 0 pm0 r/w ffh ff23h port mode register 3 pm3 ff24h port mode register 4 pm4 ff25h port mode register 5 pm5 ff26h port mode register 6 pm6 ff27h port mode register 7 pm7 ff2ch port mode register 12 pm12 ff34h pull-up resistor option register 4 pu4 00h ff40h clock output select register cks ff41h beep clock select register 0 beepcl0 ff42h watchdog timer clock select register wdcs ff48h external interrupt rising edge enable register egp ff49h external interrupt falling edge enable register egn ff69h serial port select register 32 sio32sel ff6ah serial i/o shift register 32 sio32 undefined ff6bh serial operating mode register 32 csim32 00h ff6ch serial i/o shift register 31 sio31 undefined ff6dh serial operating mode register 31 csim31 00h notes 1. this register can be accessed only in 8-bit units. when adcr3 is read, the value of ff11h is read. 2. the value of this register is 03h only at reset by power-on clear. this register is not reset by the reset pin or watchdog timer. caution do not access addresses to which no sfr is assigned.
54 chapter 3 cpu architecture user? manual u15104ej2v0ud table 3-4. special function registers (2/3) address special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits ff6eh serial i/o shift register 30 sio30 r/w undefined ff6fh serial operating mode register 30 csim30 00h ff70h 8-bit compare register 52 cr52 w undefined ff71h 8-bit compare register 53 cr53 ff72h 8-bit timer counter 52 tm523 tm52 r 00h ff73h 8-bit timer counter 53 tm53 ff74h timer clock select register 52 tcl52 r/w ff75h 8-bit timer mode control register 52 tmc52 ff77h timer clock select register 53 tlc53 ff78h 8-bit timer mode control register 53 tmc53 ff80h 8-bit compare register 50 cr50 undefined ff81h 8-bit compare register 51 cr51 ff82h 8-bit timer counter 50 tm501 tm50 r 00h ff83h 8-bit timer counter 51 tm51 ff84h timer clock select register 50 tcl50 r/w ff85h 8-bit timer mode control register 50 tmc50 ff87h timer clock select register 51 tcl51 ff88h 8-bit timer mode control register 51 tmc51 ffa0h pll mode select register pllmd ffa1h pll reference mode register pllrf 0fh ffa2h pll unlock f/f judge register pllul r&reset retained note 1 ffa3h pll data transfer register pllns w 00h ffa6h pll data registers pll data register l pllr pllrl r/w undefined ffa7h pll data register h pllrh ffa8h pll data register 0 pllr0 ffa9h if counter mode select register ifcmd 00h ffaah dts system clock select register dtsck 00h note 2 ffabh if counter gate judge register ifcjg r 00h ffach if counter control register ifccr w ffaeh if counter register ifcr ifcrl r ffafh ifcrh notes 1. undefined by power-on clear reset only. 2. though the initial value of the dts system clock select register (dtsck) is 00h, be sure to set this register to 01h before using it. caution do not access addresses to which no sfr is assigned.
55 chapter 3 cpu architecture user? manual u15104ej2v0ud table 3-4. special function registers (3/3) address special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits ffd0h external access area note 1 r/w undefined | ffdfh ffe0h interrupt request flag register 0l if0 if0l 00h ffe1h interrupt request flag register 0h if0h ffe4h interrupt mask flag register 0l mk0 mk0l ffh ffe5h interrupt mask flag register 0h mk0h ffe8h priority specification flag register 0l pr0 pr0l ffe9h priority specification flag register 0h pr0h fff0h memory size switching register ims cfh note 2 fff4h internal expansion ram size switching register ixs 0ch note 3 fff9h watchdog timer mode register wdtm 00h fffah oscillation stabilization time switching register osts 04h fffbh processor clock control register pcc notes 1. the external access area cannot be accessed by means of sfr addressing. use direct addressing to access this area. 2. the initial value of the memory size switching register (ims) is cfh. set the values of these registers of each model as follows: part number ims pd178053 c6h pd178054 c8h pd178f054 value equivalent to mask rom version 3. do not assign a value other than the initial value to the internal expansion ram size switching register (ixs). caution do not access addresses to which no sfr is assigned.
56 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents, and the contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing. (for details of instructions, refer to 78k/0 user? manual instruction (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two's complement data ( 128 to +127) and bit 7 becomes a sign bit. that is, using relative addressing, the program branches in the range 128 to +127 relative to the first address of the next instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ...
57 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. the call !addr16 and br !add16 instructions can be used to branch to any location in the memory. the callf !addr11 instruction is used to branch to the area between 0800h through 0fffh. [illustration] in the case of call !addr16 and br !addr16 instructions in the case of callf !addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10 _ 8 11 10 00001 643 callf fa 7 _ 0
58 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this addressing is used when the callt [addr5] instruction is executed. this instruction references an address stored in the memory table between 40h through 7fh, and can be used to branch to any location in the memory. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4 0 operation code
59 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
60 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the registers that functions as an accumulator (a and ax) among the general-purpose registers are automatically addressed (implied). of the pd178054 subseries instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of register a and register x is stored in ax. in this example, the a and ax registers are specified by implied addressing.
61 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.4.2 register addressing [function] this addressing mode is used to access a general-purpose register as an operand. the register to be accessed is specified by the register bank select flags (rbs0 and rbs1) and the register specification codes (rn and rpn) in the operation code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] symbol description r x, a, c, b, e, d, l, h rp ax, bc, de, hl 'r' and 'rp' can be written with function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) as well as absolute names (r0 to r7 and rp0 to rp3). [example] mov a, c; when selecting c register as r operation code 01100010 register specification code incw de; when selecting de register pair as rp operation code 10000100 register specification code
62 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.4.3 direct addressing [function] the memory with immediate data in an instruction word is directly addressed. [operand format] symbol description addr16 label or 16-bit immediate data [example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh [illustration] 70 op code addr16 (low order) addr16 (high order) memory ? ? ? ? ?
63 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the fixed 256-byte space fe20h to ff1fh. an internal ram and a special-function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is one part of all the sfr areas. in this area, ports which are frequently accessed in a program and a compare register and a capture register of the timer/event counter are mapped and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to [illustration] below. [operand format] symbol description saddr label of fe20h to ff1fh immediate data saddrp label of fe20h to ff1fh immediate data (even address only) [example] mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h operation code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) [illustration] when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset
64 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.4.5 special function register (sfr) addressing [function] the memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] symbol description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
65 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.4.6 register indirect addressing [function] this addressing is used to address the memory to be manipulated by using the contents of the register pair specified by the register pair code in an instruction word as the operand address. the register pair specified is in the register bank specified by the register bank select flags (rbs0 and rbs1). this addressing can be used for the entire memory space. [operand format] symbol description [de], [hl] [example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 15 0 8 d 7 e 0 7 7 0 a de memory
66 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.4.7 based addressing [function] this addressing mode is used to address a memory location specified by the result of adding the 8-bit immediate data to the contents of the hl register pair which is used as a base register. the hl register pair accessed is the register in the register bank specified by the register bank select flags (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] symbol description [hl + byte] [example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000
67 chapter 3 cpu architecture user s manual u15104ej2v0ud 3.4.8 based indexed addressing [function] this addressing mode is used to address a memory location specified by the result of adding the contents of the b or c register specified in the instruction word to the contents of the hl register pair which is used as a base register. the hl, b, and c registers accessed are the registers in the register bank specified by the register bank select flags (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] symbol description [hl + b], [hl + c] [example] in the case of mov a, [hl + b] operation code 10101011 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/restored upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. [example] in the case of push de operation code 10110101
68 user? manual u15104ej2v0ud chapter 4 port functions 4.1 port functions the pd178054 subseries units incorporate input, output, and i/o ports consisting of 6, 3, and 53 pins, respectively. figure 4-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on-chip hardware input/output pins. figure 4-1. port types ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 5 port 0 ? ? ? ? ? ? ? port 1 ? ? ? ? ? ? ? ? ? port 3 ? ? ? ? ? ? ? ? ? port 4 ? ? ? ? ? ? ? ? ? port 6 ? ? ? ? ? ? ? ? ? port 7 ? ? ? port 13 ? ? ? ? ? ? ? port 12 p00 p06 p10 p15 p30 p37 p50 p57 p60 p67 p70 p77 p120 p125 p130 p132 p40 p47
69 chapter 4 port functions user s manual u15104ej2v0ud table 4-1. port functions pin name i/o function alternate function p00 to p04 i/o port 0 intp0 to intp4 7-bit i/o port p05, p06 input/output can be specified in 1-bit units. p10 to p15 input port 1 ani0 to ani5 6-bit input port p30 to p32 i/o port 3 p33 8-bit i/o port ti50 p34 input/output can be specified in 1-bit units. ti51 p35 p36 beep0 p37 buz p40 to 47 i/o port 4 8-bit i/o port input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by software. interrupt function by key input is provided. p50 to p57 i/o port 5 8-bit i/o port input/output can be specified in 1-bit units. p60 to p67 i/o port 6 8-bit i/o port input/output can be specified in 1-bit units. p70 i/o port 7 si30 p71 8-bit i/o port so30 p72 input/output can be specified in 1-bit units. sck30 p73 p74 si31 p75 so31 p76 sck31 p77 ti52 p120 i/o port 12 si32 p121 6-bit i/o port so32 p122 input/output can be specified in 1-bit units. sck32 p123 si321 p124 so321 p125 sck321 p130 output port 13 to50 p131 3-bit output port to51 p132 n-ch open-drain output port (12 v tolerance) to52
70 chapter 4 port functions user s manual u15104ej2v0ud 4.2 port configuration the ports consist of the following hardware. table 4-2. port configuration item configuration control register port mode register (pmm: m = 0, 3 to 7, 12) port total: 62 port pins (6 inputs, 3 outputs, 53 i/os) 4.2.1 port 0 port 0 is a 7-bit i/o port with an output latch. input or output mode can be specified for port 0 in 1-bit units using port mode register 0 (pm0). alternate functions include external interrupt request input. reset input sets port 0 to the input mode. figures 4-2 and 4-3 show the block diagrams of port 0. caution because port 0 also serves as an external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1. figure 4-2. block diagram of p00 to p04 pm: port mode register rd: port 0 read signal wr: port 0 write signal p00/intp0 p01/intp1 p02/intp2 p03/intp3 p04/intp4 rd wr port wr pm alternate function output latch (p00 to p04) pm00 to pm04 internal bus selector
71 chapter 4 port functions user s manual u15104ej2v0ud 4.2.2 port 1 port 1 is a 6-bit input port. alternate functions include a/d converter analog input. figure 4-4 shows the block diagram of port 1. figure 4-4. block diagram of p10 to p15 rd : port 1 read signal figure 4-3. block diagram of p05 and p06 pm: port mode register rd: port 0 read signal wr: port 0 write signal wr pm wr port rd p05, p06 selector output latch (p05, p06) pm05, pm06 internal bus v ref rd a/d converter p10/ani0 to p15/ani5 + _ internal bus
72 chapter 4 port functions user s manual u15104ej2v0ud 4.2.3 port 3 port 3 is an 8-bit i/o port with an output latch. input or output mode can be specified for port 3 in 1-bit units using port mode register 3 (pm3). alternate functions include timer input and buzzer output. reset input sets port 3 to the input mode. figures 4-5 to 4-7 show the block diagrams of port 3. figure 4-5. block diagram of p30 to p32 and p35 pm: port mode register rd: port 3 read signal wr: port 3 write signal rd p30 to p32, p35 wr port wr mm output latch (p30 to p32, p35) pm30 to pm32, pm35 selector internal bus
73 chapter 4 port functions user s manual u15104ej2v0ud figure 4-6. block diagram of p33 and p34 pm: port mode register rd: port 3 read signal wr: port 3 write signal figure 4-7. block diagram of p36 and p37 pm: port mode register rd: port 3 read signal wr: port 3 write signal p33/ti50 p34/ti51 rd wr port wr pm alternate function output latch (p33, p34) pm33, pm34 internal bus selector wr pm wr port rd selector output latch (p36, p37) pm36, pm37 internal bus alternate function p36/beep0 p37/buz
74 chapter 4 port functions user s manual u15104ej2v0ud 4.2.4 port 4 port 4 is an 8-bit i/o port with an output latch. input or output mode can be specified for port 4 in 1-bit units using port mode register 4 (pm4). connection of pull-up resistors can be specified in 1-bit units using pull-up resistor option register 4 (pu4). the interrupt request flag (kyif) can be set to 1 by detecting key inputs. when using this function, be sure to set the mem register to 01h. reset input sets port 4 to input mode. figures 4-8 and 4-9 show a block diagram of port 4 and block diagram of the key input detector, respectively. figure 4-8. block diagram of p40 to p47 pu: pull-up resistor option register pm: port mode register rd: port 4 read signal wr: port 4 write signal rd p40 to p47 p-ch wr pu wr port wr pm pu40 to pu47 output latch (p40 to p47) pm40 to pm47 selector v dd internal bus
75 chapter 4 port functions user s manual u15104ej2v0ud figure 4-9. block diagram of key input detector wr pm wr port rd selector output latch (p50 to p57) pm50 to pm57 internal bus p50 to p57 p40 p41 p42 p43 p44 p45 p46 p47 intkr key input detector 1 when mem = 01h cautions 1. this register is valid only when the mem register is set to 01h. 2. key return can be detected only when all the pins of p40 to p47 are high level. when any one is low level, even if falling edge is generated at the other pins, the key return signal cannot be detected. 4.2.5 port 5 port 5 is an 8-bit i/o port with an output latch. input or output mode can be specified for port 5 in 1-bit units using port mode register 5 (pm5). reset input sets port 5 to the input mode. figure 4-10 shows the block diagram of port 5. figure 4-10. block diagram of p50 to p57 pm: port mode register rd: port 5 read signal wr: port 5 write signal
76 chapter 4 port functions user s manual u15104ej2v0ud 4.2.6 port 6 port 6 is an 8-bit i/o port with an output latch. input or output mode can be specified for port 6 in 1-bit units using port mode register 6 (pm6). reset input sets port 6 to the input mode. figure 4-11 shows the block diagram of port 6. figure 4-11. block diagram of p60 to p67 pm: port mode register rd: port 6 read signal wr: port 6 write signal wr pm wr port rd selector output latch (p60 to p67) pm60 to pm67 internal bus p60 to p67
77 chapter 4 port functions user s manual u15104ej2v0ud 4.2.7 port 7 port 7 is an 8-bit i/o port with an output latch. input or output mode can be specified for port 7 in 1-bit units using port mode register 7 (pm7). alternate functions include serial interface data i/o, clock i/o, and timer input. reset input sets port 7 to the input mode. figures 4-12 to 4-15 show the block diagrams of port 7. figure 4-12. block diagram of p70, p74, and p77 pm: port mode register rd: port 7 read signal wr: port 7 write signal p70/si30 p74/si31 p77/ti52 rd wr port wr pm alternate function output latch (p70, p74, p77) pm70, pm74, pm77 selector internal bus
78 chapter 4 port functions user s manual u15104ej2v0ud figure 4-13. block diagram of p71 and p75 figure 4-14. block diagram of p72 and p76 pm: port mode register rd: port 7 read signal wr: port 7 write signal rd p71/so30 p75/so31 wr port wr pm output latch (p71, p75) pm71, pm75 selector alternate function internal bus pm: port mode register rd: port 7 read signal wr: port 7 write signal p72/sck30 p76/sck31 rd wr port wr pm alternate function output latch (p72, p76) pm72, pm76 alternate function internal bus selector
79 chapter 4 port functions user s manual u15104ej2v0ud figure 4-15. block diagram of p73 pm: port mode register rd: port 7 read signal wr: port 7 write signal rd p73 wr port wr mm output latch (p73) pm73 selector internal bus
80 chapter 4 port functions user s manual u15104ej2v0ud 4.2.8 port 12 port 12 is a 6-bit i/o port with an output latch. input or output mode can be specified for port 12 in 1-bit units using port mode register 12 (pm12). alternate functions include serial interface data i/o and clock i/o. reset input sets port 12 to the input mode. figures 4-16 to 4-18 show the block diagrams of port 12. figure 4-16. block diagram of p120 and p123 pm: port mode register rd: port 12 read signal wr: port 12 write signal p120/si32 p123/si321 rd wr port wr pm alternate function output latch (p120, p123) pm120, pm123 selector internal bus
81 chapter 4 port functions user s manual u15104ej2v0ud figure 4-17. block diagram of p121 and p124 pm: port mode register rd: port 12 read signal wr: port 12 write signal figure 4-18. block diagram of p122 and p125 pm: port mode register rd: port 12 read signal wr: port 12 write signal wr pm wr port rd selector output latch (p121, p124) pm121, pm124 internal bus alternate function p121/so32 p124/so321 p122/sck32 p125/sck321 rd wr port wr pm alternate function output latch (p122, p125) pm122, pm125 alternate function selector internal bus
82 chapter 4 port functions user s manual u15104ej2v0ud 4.2.9 port 13 port 13 is a 3-bit n-ch open-drain output port with an output latch. the pins of this port are also used as timer output pins. reset input sets port 13 in the general-purpose output port mode. the port 13 block diagram is shown in figure 4-19. figure 4-19. block diagram of p130 to p132 rd: port 13 read signal wr: port 13 write signal rd p130/to50 p131/to51 p132/to52 wr port output latch (p130 to p132) internal bus alternate function
83 chapter 4 port functions user s manual u15104ej2v0ud 4.3 registers controlling port functions the following two types of registers control the ports. port mode registers (pm0, pm3 to pm7, pm12) pull-up resistor option register (pu4) (1) port mode registers (pm0, pm3 to pm7, pm12) these registers are used to set the port input/output mode in 1-bit units. pm0, pm3 to pm7, and pm12 are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when using a port pin as an alternate-function pin, set the values of the port mode registers and the output latches as shown in table 4-3. cautions 1. p10 to p17 are input-only pins, and p130 to p132 are output-only pins. 2. as port 0 has an alternate function as an external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.
84 chapter 4 port functions user? manual u15104ej2v0ud table 4-3. port mode register and output latch settings when using alternate functions pin name alternate functions pm p name i/o p00 to p04 intp0 to intp4 input 1 p33 ti50 input 1 p34 ti51 input 1 p36 beep0 output 0 0 p37 buz output 0 0 p70 si30 input 1 p71 so30 output 0 0 p72 sck30 input 1 output 0 0 p74 si31 input 1 p75 so31 output 0 0 p76 sck31 input 1 output 0 0 p77 ti52 input 1 p120 si32 input 1 p121 so32 output 0 0 p122 sck32 input 1 output 0 0 p123 si321 input 1 p124 so321 output 0 0 p125 sck321 input 1 output 0 0 p130 to p132 to50 to to52 output 0 caution when using the above alternate function pins as an output port, be sure to set the output latch (p ) to 0. remark : don? care pm : port mode register p : output latch of port
85 chapter 4 port functions user s manual u15104ej2v0ud figure 4-20. format of port mode registers pm0 pm7 1 pm06 pm03 pm02 pm01 pm00 76543210 symbol pm3 pm5 ff20h ff27h ff23h ff25h ffh ffh ffh ffh r/w r/w r/w r/w address after reset r/w pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 pm6 ff26h ffh r/w pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 pm05 pm04 pm12 pmmn pmn pin input/output mode selection (m = 0, 3 to 7, 12 : n = 0 to 7) 0 1 output mode (output buffer on) input mode (output buffer off) ff2ch ffh r/w pm122 pm121 pm120 pm125 pm124 pm123 11 pm4 ff24h ffh r/w pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40
86 chapter 4 port functions user s manual u15104ej2v0ud (2) pull-up resistor option register 4 (pu4) this register is used to specify the use of the internal pull-up resistors of port 4. a pull-up resistor can only be used internally for the bit specified by pu4. pu4 can be set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pu4 to 00h. figure 4-21. format of pull-up resistor option register 4 (pu4) pu4n selection of internal pull-up resistor for p4n (n = 0 to 7) 0 internal pull-up resistor not used 1 internal pull-up resistor used symbol pu4 7 pu47 6 pu46 5 pu45 4 pu44 3 pu43 2 pu42 1 pu41 0 pu40 address ff34h after reset 00h r/w r/w
87 chapter 4 port functions user s manual u15104ej2v0ud 4.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 writing to i/o ports (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, for a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 4.4.2 reading from i/o ports (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 4.4.3 operations on i/o ports (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, for a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
88 user? manual u15104ej2v0ud chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. this system clock oscillator is connected to 4.5 mhz crystal resonator. at this time, set bit 0 (dtsck0) of the dts system clock select register (dtsck) to 1. set the dtsck0 flag after power application and reset by the reset pin, and before using the basic timer, buzzer output control circuit, pll frequency synthesizer, and frequency counter. oscillation can be stopped by executing the stop instruction. figure 5-1. format of dts system clock select register (dtsck) dtsck0 selects system clock 1 4.5 mhz 0 setting prohibited 7 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> dtsck0 symbol dtsck address ffaah after reset 00h r/w r/w
89 chapter 5 clock generator user s manual u15104ej2v0ud 5.2 configuration of clock generator the clock generator consists of the following hardware. table 5-1. configuration of clock generator item configuration control register processor clock control register (pcc) oscillator system clock oscillator figure 5-2. block diagram of clock generator system clock oscillator x2 x1 stop 00 00 pcc2 pcc1 internal bus standby controller 2 f x 2 2 f x 2 3 f x 2 4 f x prescaler clock to peripheral hardware prescaler f x cpu clock (f cpu ) wait controller processor clock control register (pcc) pcc0 3 selector 0
90 chapter 5 clock generator user s manual u15104ej2v0ud 5.3 register controlling clock generator the clock generator is controlled by the processor clock control register (pcc). pcc sets the cpu clock. pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pcc to 04h. figure 5-3. format of processor clock control register (pcc) note bits 3 to 7 are read only. remarks 1. f x : system clock oscillation frequency 2. ( ): minimum instruction execution time: 2/f cpu at f x = 4.5 mhz operation 000 0 pcc2 pcc1 pcc0 pcc fffbh 04h r/w note 76 54 symbol address after reset r/w 0 76 3 2 0 1 0 0 pcc2 cpu ciock (f cpu ) selection pcc1 pcc0 0 0 0 1 0 0 1 1 0 1 100 setting prohibited other than above r/w f x /2 f x /2 2 f x /2 3 f x /2 4 f x (0.89 s) (1.78 s) (3.56 s) (7.11 s) (0.45 s)
91 chapter 5 clock generator user s manual u15104ej2v0ud 5.4 system clock oscillator 5.4.1 system clock oscillator the system clock oscillator oscillates with a crystal resonator (4.5 mhz typ.) connected to the x1 and x2 pins. figure 5-4 shows an external circuit of the system clock oscillator. figure 5-4. external circuit of system clock oscillator crystal oscillation caution when using a system clock oscillator, wire as follows in the area enclosed by the broken lines in figure 5-4 to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as gnd. do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. crystal resonator ic x1 x2
92 chapter 5 clock generator user s manual u15104ej2v0ud figure 5-5 shows examples of incorrectly connected resonators. figure 5-5. examples of incorrect resonator connection (1/2) (a) wiring of connection (b) signal lines cross circuits is too long each other (c) high fluctuating current is near a (d) current flows through the ground line signal lines of the oscillator (potential at points a, b, and c fluctuate) x2 ic x1 x2 ic x1 portn (n = 0, 1, 3 to 7, 12, 13) x2 ic x1 x2 ic x1 portn (n = 0, 1, 3 to 7, 12, 13) v dd abc high current high current
93 chapter 5 clock generator user s manual u15104ej2v0ud figure 5-5. examples of incorrect resonator connection (2/2) (e) signals are fetched 5.4.2 divider the divider divides the system clock oscillator output (f x ) and generates various clocks. x2 ic x1
94 chapter 5 clock generator user s manual u15104ej2v0ud 5.5 clock generator operations the clock generator generates the following types of clocks and controls the cpu operating mode, such as the standby mode. system clock f x cpu clock f cpu clock to peripheral hardware the following clock generator functions and operations are determined by the processor clock control register (pcc). (a) upon generation of the reset signal, the lowest speed mode of the system clock (7.11 s when operated at 4.5 mhz) is selected (pcc = 04h). system clock oscillation stops while a low level is applied to the reset pin. (b) one of the five cpu clock types (0.45, 0.89, 1.78, 3.56, 7.11 s at 4.5 mhz) can be selected by setting pcc. (c) two standby modes, stop and halt, are available. (d) the system clock is divided and supplied to the peripheral hardware. the peripheral hardware also stops if the system clock is stopped.
95 chapter 5 clock generator user s manual u15104ej2v0ud table 5-2. maximum time required for cpu clock switching pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 000001010011100 0 0 0 16 instructions 16 instructions 16 instructions 16 instructions 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction set values after switching set values before switching remark one instruction is the minimum instruction execution time with the preswitched cpu clock. pcc2 pcc1 pcc0 5.6 changing system clock and cpu clock settings 5.6.1 time required for switching between system clock and cpu clock the system clock and cpu clock can be switched using bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc). the actual switching operation is not performed directly after writing to pcc, but operation continues on the preswitched clock for several instructions (refer to table 5-2 ).
96 user? manual u15104ej2v0ud chapter 6 8-bit timer/event counters 50 to 53 6.1 functions of 8-bit timer/event counters 50 to 53 8-bit timer/event counters 50 to 53 have the following two modes. mode in which an 8-bit timer/event counter is used alone (single mode) mode in which the two timer/event counters are cascaded (cascade mode with a resolution of 16 bits) these two modes are explained below. (1) mode in which an 8-bit timer/event counter is used alone (single mode) the timer/event counter operates as an 8-bit timer/event counter. in this mode, the following functions can be used. interval timer external event counter square wave output pwm output caution timer 53 can be used only as an interval timer since it does not include timer input and output pins. (2) mode in which the two timer/event counters are cascaded (cascade mode with a resolution of 16 bits) by connecting timer 50 or timer 52 as a lower timer and timer 51 or timer 53 as a higher timer in cascade, they operate as a 16-bit timer/event counter. in this mode, the following functions can be used: interval timer with 16-bit resolution external event counter with 16-bit resolution square wave output with 16-bit resolution figures 6-1 to 6-4 show the block diagrams of 8-bit timer/event counters 50 to 53.
97 chapter 6 8-bit timer/event counters 50 to 53 user? manual u15104ej2v0ud figure 6-1. block diagram of 8-bit timer/event counter 50 figure 6-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit compare register 50 (cr50) 8-bit timer counter 50 (tm50) ti50/p33 f x /2 5 f x /2 7 f x /2 9 f x /2 11 f x /2 3 match ovf clear 3 selector tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 level inversion timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/p130 f x /2 output latch (p130) selector selector mask circuit internal bus 8-bit compare register 51 (cr51) 8-bit timer counter 51 (tm51) ti51/p34 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 match ovf clear 3 tcl512 tcl511 tcl510 internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 level inversion s r q r inv selector selector selector selector inttm51 to51/p131 s f x /2 11 output latch (p131) mask circuit timer clock select register 51 (tcl51) timer mode control register 51 (tmc51)
98 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud figure 6-3. block diagram of 8-bit timer/event counter 52 figure 6-4. block diagram of 8-bit timer 53 internal bus 8-bit compare register 52 (cr52) 8-bit timer counter 52 (tm52) ti52/p77 f x /2 5 f x /2 7 f x /2 9 f x /2 11 f x /2 3 match ovf clear 3 selector tcl522 tcl521 tcl520 timer clock select register 52 (tcl52) internal bus tce52 tmc526 tmc524 lvs52 lvr52 tmc521 toe52 level inversion timer mode control register 52 (tmc52) s r s q r inv selector inttm52 to52/p132 f x /2 output latch (p132) selector selector mask circuit internal bus 8-bit compare register 53 (cr53) 8-bit timer counter 53 (tm53) f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 selector match mask circuit clear 3 selector tcl532 tcl531 tcl530 timer clock select register 53 (tcl53) internal bus lvs51 lvr51 timer mode control register 53 (tmc53) inttm53 f x /2 11
99 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud 6.2 configuration of 8-bit timer/event counters 50 to 53 8-bit timer/event counters 50 to 53 consist of the following hardware. table 6-1. configuration of 8-bit timer/event counters 50 to 53 item configuration timer registers 8-bit timer counters 50, 51, 52, and 53 (tm50 to tm53) registers 8-bit compare registers 50, 51, 52, and 53 (cr50 to cr53) timer outputs 3 lines (to50 to to52) control registers timer clock select registers 50, 51, 52, and 53 (tcl50 to tcl53) 8-bit timer mode control registers 50, 51, 52, and 53 (tmc50 to tmc53) (1) 8-bit timer counters 50, 51, 52, and 53 (tm50 to tm53) tm5n is an 8-bit read-only register that counts the count pulses. the counter is incremented at the rising edge of the count clock. tm50 and tm51 or tm52 and tm53 can be cascaded and used as a 16-bit timer. when tm50 and tm51 are cascaded and used as a 16-bit timer, its value can be read using a 16-bit memory manipulation instruction. however, because tm50 and tm51 are connected with the internal 8-bit bus, they are read one at a time. therefore, read the value of tm50 and tm51 when used as a 16-bit timer two times for comparison, taking changes in the values during counting into consideration. when tm52 and tm53 are cascaded and used as a 16-bit timer, its value can be read using a 16-bit memory manipulation instruction. however, because tm52 and tm53 are connected with the internal 8-bit bus, they are read one at a time. therefore, read the value of tm52 and tm53 when used as a 16-bit timer two times for comparison, taking changes in the values during counting into consideration. if the count value is read while the timer is operating, stop input of the count clock, and read the count value at that point. the count value is cleared to 00h in the following cases. <1> reset input <2> clearing tce5n <3> match between tm5n and cr5n in mode in which the timer is cleared and started on match between tm5n and cr5n caution when tm50 and tm51 or tm52 and tm53 are cascaded, the value of the timer is cleared to 00h even if the least significant bit (tce50 or tce52) of timer mode control register 50 (tmc50) or 52 (tmc52) is cleared. remark n = 0 to 3
100 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud (2) 8-bit compare registers 50, 51, 52, and 53 (cr50 to cr53) the value set to cr5n is always compared with the value of 8-bit timer counter 5n (tm5n). when the value of a compare register matches the count value of the corresponding counter, an interrupt request (inttm5n) is generated (in a mode other than pwm mode). if tm50 and tm51 are cascaded and used as a 16-bit timer, cr50 and cr51 operate together as a 16-bit compare register. the 16-bit counter value and 16-bit compare register value are compared, and when the two values match, an interrupt request (inttm50) is generated. at this time, the interrupt request inttm51 is also generated. therefore, mask inttm51 when using tm50 and tm51 in the cascade mode. if tm52 and tm53 are cascaded and used as a 16-bit timer, cr52 and cr53 operate together as a 16-bit compare register. the 16-bit counter value and 16-bit compare register value are compared, and when the two values match, an interrupt request (inttm52) is generated. at this time, the interrupt request inttm53 is also generated. therefore, mask inttm53 when using tm52 and tm53 in the cascade mode. caution when tm50 and tm51 or tm52 and tm53 are cascaded, be sure to change the cr5n setting value after stopping the timer operation of cascaded tm5n. remark n = 0 to 3
101 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud 6.3 registers controlling 8-bit timer/event counters 50 to 53 the following two types of registers control the 8-bit timer/event counters 50 to 53. timer clock select registers 50 to 53 (tcl50 to tcl53) 8-bit timer mode control registers 50 to 53 (tmc50 to tmc53) (1) timer clock select registers 50 to 52 (tcl50 to tcl52) these registers select the count clock of 8-bit timer counter 5n (tm5n) and the valid edge of the ti5n input. tcl5n is set with an 8-bit memory manipulation instruction. reset input clears tcl50 to tcl52 to 00h. remark n = 0 to 2 figure 6-5. format of timer clock select registers 50 to 52 (tcl50 to tcl52) tcl5n2 tcl5n1 tcl5n0 count clock selection 0 0 0 falling edge of ti5n 0 0 1 rising edge of ti5n 010f x /2 (2.25 mhz) 011f x /2 3 (563 khz) 100f x /2 5 (141 khz) 101f x /2 7 (35.2 khz) 110f x /2 9 (8.79 khz) 111f x /2 11 (2.20 khz) cautions 1. before changing the data of tcl5n, be sure to stop the timer operation. 2. be sure to set bits 3 to 7 to 0. remarks 1. in the cascade mode, the setting of bits tcl50 or tcl52 of the lower timer (tm50 or tm52) is valid, and the setting of bits tcl51 or tcl53 of the higher timer (tm51 or tm53) is invalid. 2. n = 0 to 2 3. f x : system clock oscillation frequency 4. ( ): f x = 4.5 mhz 76543 000 tcl502 tcl501 tcl500 00 210 76543210 76543210 symbol tcl50 address ff84h after reset 00h r/w r/w 000 tcl512 tcl511 tcl510 00 tcl51 ff87h 00h r/w 000 tcl522 tcl521 tcl520 00 tcl52 ff74h 00h r/w
102 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud (2) timer clock select register 53 (tcl53) this register selects the count clock of 8-bit timer counter 53 (tm53). tcl53 is set with an 8-bit memory manipulation instruction. reset input clears tcl53 to 00h. figure 6-6. format of timer clock select register 53 (tcl53) tcl532 tcl531 tcl530 count clock selection 0 0 0 setting prohibited 0 0 1 setting prohibited 010f x /2 (2.25 mhz) 011f x /2 3 (563 khz) 100f x /2 5 (141 khz) 101f x /2 7 (35.2 khz) 110f x /2 9 (8.79 khz) 111f x /2 11 (2.20 khz) cautions 1. before changing the data of tcl53, be sure to stop the timer operation. 2. be sure to reset bits 3 to 7 to 0. remarks 1. in the cascade mode, the setting of bit tcl53 of the higher timer (tm53) is invalid. 2. f x : system clock oscillation frequency 3. ( ): f x = 4.5 mhz (3) 8-bit timer mode control registers 50 to 52 (tmc50 to tmc52) the tmc5n register is used for the following. <1> controlling count operation of 8-bit timer counter 5n (tm5n) <2> selecting operation mode of 8-bit timer counter 5n (tm5n) <3> selecting single mode or cascade mode <4> setting status of timer output f/f (flip-flop) <5> controlling timer f/f or selecting active level in pwm (free-running) mode <6> controlling timer output tmc5n can be set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc5n to 00h. remark n = 0 to 2 76543 000 tcl532 tcl531 tcl530 00 210 symbol tcl53 address ff77h after reset 00h r/w r/w
103 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud figure 6-7. format of 8-bit timer mode control registers 50 to 52 (tmc50 to tmc52) tce5n control of count operation of tm5n 0 clears counter to 0 and disables count operation (disables prescaler) 1 starts count operation tmc5n6 selection of operating mode of tm5n 0 mode of clearing and starting tm5n on match between tm5n and cr5n 1 pwm (free-running) mode tmc5n4 selection of single mode or cascade mode 0 single mode 1 note cascade mode (connected to lower timer) lvs5n lvr5n setting status of timer output f/f 0 0 not affected 0 1 resets timer output f/f to 0 1 0 sets timer output f/f to 1 1 1 setting prohibited tmc5n1 other than pwm mode (tmc5n6 = 0) pwm mode (tmc5n6 = 1) control of timer f/f selection of active level 0 disables inversion operation high active 1 enables inversion operation low active toe5n control of timer output 0 disables output (port mode) 1 enables output note since the higher timer settings become valid, the lower timer tmc504/tmc524 settings become invalid. caution be sure to reset bit 4 (tmc5n4) to 0. remarks 1. the pwm output becomes inactive when tce5n = 0 in the pwm mode. 2. lvs5n and lvr5n are 0 when read after data has been set. 3. n = 0 to 2 <7> tce50 6 tmc506 5 0 4 tmc504 <3> lvs50 <2> lvr50 1 tmc501 <0> toe50 symbol tmc50 address ff85h after reset 00h r/w r/w <7> tce51 6 tmc516 5 0 4 tmc514 <3> lvs51 <2> lvr51 1 tmc511 <0> toe51 tmc51 ff88h 00h r/w <7> tce52 6 tmc526 5 0 4 tmc524 <3> lvs52 <2> lvr52 1 tmc521 <0> toe52 tmc52 ff75h 00h r/w
104 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud (4) 8-bit timer mode control register 53 (tmc53) the tmc53 register is used for the following. <1> controlling count operation of 8-bit timer counter 53 (tm53) <2> selecting single mode or cascade mode tmc53 can be set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc53 to 00h. figure 6-8. format of 8-bit timer mode control register 53 (tmc53) tce53 control of count operation of tm53 0 clears counter to 0 and disables count operation (disables prescaler) 1 starts count operation tmc534 selection of single mode or cascade mode 0 single mode 1 cascade mode (connected to lower timer (tm52)) <7>6543 tce53 00 000 tmc534 0 210 symbol tmc53 address ff78h after reset 00h r/w r/w
105 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud 6.4 operations of 8-bit timer/event counters 50 to 53 6.4.1 operation as interval timer (8-bit) the 8-bit timer/event counter operates as an interval timer that repeatedly generates an interrupt request at the interval specified by the count value set in advance in 8-bit compare register 5n (crn). when the count value of 8-bit timer counter 5n (tm5n) matches the value set in cr5n, the value of tm5n is cleared to 0. tm5n continues counting and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected by using bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). for the operation if the value of the compare register is changed while the timer count operation, refer to (2) in 6.5 notes on 8-bit timer/event counters 50 to 53 . [setting] <1> set each register. tcl5n: select a count clock. cr5n: compare value tmc5n: select a mode in which tm5n is cleared and started on match between tm5n and cr5n (tmc5n = 0000 0b: = don t care). <2> the count operation is started when tec5n is set to 1. <3> inttm5n is generated if the values of tm5n and cr5n match (tm5n is cleared to 00h). <4> after that, inttm5n is repeatedly generated at fixed intervals. to stop the count operation, clear tce5n to 0. remark n = 0 to 3
106 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud figure 6-9. timing of interval timer operation (1/3) (a) basic operation remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. n = 0 to 3 t count clock tm5n count value cr5n tce5n inttm5n to5n count starts cleared cleared 00h 01h n 00h 01h n 00h 01h n n n n n interrupt request acknowledged interrupt request acknowledged interval time interval time interval time
107 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud figure 6-9. timing of interval timer operation (2/3) (b) when cr5n = 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n to5n interval time 00h 00h 00h 00h 00h t count clock tm5n cr5n tce5n inttm5n to5n 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt acknowl- edged interrupt acknowledged n = 0 to 3
108 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud figure 6-9. timing of interval timer operation (3/3) (d) operation when cr5n is changed (m < n) (e) operation when cr5n is changed (m > n) count clock tm5n cr5n tce5n inttm5n to5n n 00h m n ffh 00h m 00h nm cr5n is changed. tm5n overflows because m < n h count clock tm5n cr5n tce5n inttm5n to5n n 1n n 00h 01h n m 1 m 00h 01h m cr5n is changed. h n = 0 to 3
109 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud 6.4.2 operation as external event counter (timers 50 to 52) the external event counter counts the number of clock pulses input from an external source to the ti5n pin using 8-bit timer counter 5n (tm5n). each time the valid edge specified by timer clock select register 5n (tcl5n) has been input to ti5n, the value of tm5n is incremented. as the valid edge, either the rising or falling edge can be selected. when the count value of tm5n matches the value of 8-bit compare register 5n (cr5n), tm5n is cleared to 0, and an interrupt request signal (inttm5n) is generated. after that, each time the value of tm5n matches the value of cr5n, inttm5n is generated. [setting] <1> set each register. tcl5n: select the valid edge of ti5n input. cr5n: compare value tmc5n: select a mode in which tm5n is cleared and started on match between tm5n and cr5n. <2> the count operation is started when tec5n is set to 1. <3> inttm5n is generated if the values of tm5n and cr5n match (tm5n is cleared to 00h). <4> after that, inttm5n is generated each time the value of tm5n matches the value of cr5n. to stop the count operation, clear tce5n to 0. remark n = 0 to 2 figure 6-10. operation timing of external event counter (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00 01 02 03 04 05 n 1 n 00 01 02 03 n n = 0 to 2
110 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud 6.4.3 square wave output operation (8-bit resolution) (timers 50 to 52) 8-bit timer/event counter tm5n can be used to output a square wave with any frequency at time interval specified by the value set in advance in 8-bit compare register 5n (cr5n). when bit 0 (toe5n) of 8-bit timer mode control register 5n (tmc5n) is set to 1, the output status of to5n is inverted at the interval specified by the count value set in advance to cr5n. in this way, a square wave (duty factor = 50%) of any frequency can be output. [setting] <1> set each register. reset the port latch and port mode register to 0 . tcl5n: select a count clock. cr5n: compare value tmc5n: mode in which tm5n is cleared and started on match between tm5n and cr5n lvs5n lvr5n sets status of timer output f/f 1 0 high-level output 0 1 low-level output enable inverting the timer f/f. enable the timer output toe5n = 1. <2> when tce5n is set to 1, the count operation is started. <3> when the value of tm5n matches the value of cr5n, the timer output f/f is inverted. in addition, inttm5n is generated, and tm5n is cleared to 00h. <4> after that, the timer output f/f is inverted at fixed intervals, and a square wave is output from to5n. remark n = 0 to 2 figure 6-11. timing of square output operation note the initial value of the to5n output can be set using bits 2 and 3 (lvr5n and lvs5n) of 8-bit timer mode control register 5n (tmc5n). remark n = 0 to 2 count clock tm5n count value 00h count starts 01h 02h n 1n n 00h n 1 n 00h 01h 02h cr5n inttm5n to5n note
111 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud 6.4.4 8-bit pwm output operation (timers 50 to 52) the 8-bit timer/event counter can be used for pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. a pulse with a duty factor determined by the value set in 8-bit compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n. the active level is selected by bit 1 (tmc5n) of tmc5n. the count clock can be selected by bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register n (tcl5n). pwm output can be enabled or disabled by bit 0 (toe5n) of tmc5n. caution the value of cr5n can be rewritten only once in one cycle in the pwm mode. remark n = 0 to 2 (1) basic operation of pwm output [setting] <1> set port latches (p130 and p131) to 0. <2> select the active level width using the 8-bit compare register (cr5n). <3> select the count clock by using timer clock select register 5n (tcl5n). <4> select the active level using bit 1 (tmc5n1) of tmc5n. <5> when bit 7 (tce5n) of tmc5n is set to 1, the count operation is started. to stop the count operation, reset tce5n to 0. [operation of pwm output] <1> when the count operation is started, the pwm output (output from to5n) remains inactive until an overflow occurs. <2> when an overflow occurs, the active level set in step <1> above is output. this active level is output until the value of cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> the pwm output remains inactive after cr5n and the count value of tm5n match, until an overflow occurs again. <4> after that, <2> and <3> are repeated until the count operation is stopped. <5> when the count operation is stopped because tce5n is cleared to 0, pwm output becomes inactive. remark n = 0 to 2
112 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud figure 6-12. operation timing of pwm output (a) basic operation (when active level = h) (b) when cr5n = 0 (c) when cr5n = ffh count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n active level inactive level active level count clock tm5n cr5n tce5n inttm5n to5n inactive level inactive level 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h 00h n + 2 l tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h ffh n + 2 inactive level active level inactive level active level inactive level n = 0 to 2
113 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud (2) operation when cr5n is changed figure 6-13. timing of operation when cr5n is changed (a) if value of cr5n is changed from n to m before overflow of tm5n (b) if value of cr5n is changed from n to m after overflow of tm5n (c) if value of cr5n is changed from n to m for duration of 2 clocks immediately after overflow of tm5n caution the value of cr5n can be changed only once in one cycle in the pwm mode. count clock tm5n cr5n tce5n inttm5n to5n cr5n changed (n m) n n + 1n + 2 ffh 00h 01h m m + 1m + 2 ffh 00h 01h 02h m m + 1m + 2 n 02h m h count clock tm5n cr5n tce5n inttm5n to5n n n + 1n + 2 ffh 00h 01h n n + 1n + 2 ffh 00h 01h 02h n 02h n h 03h m m m + 1m + 2 cr5n changed (n m) count clock tm5n cr5n tce5n inttm5n to5n n n + 1n + 2 ffh 00h 01h n n + 1n + 2 ffh 00h 01h 02h n 02h n h m m m + 1m + 2 cr5n changed (n m) n = 0 to 2
114 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud 6.4.5 interval timer operation (16-bit) when using the 8-bit timer/counters as a 16-bit timer, be sure to use a combination of timers 50 and 51 or timers 52 and 53. the following section describes the case when using timers 50 and 51. when using timers 52 and 53, read 50 as 52 and 51 as 53 . the 8-bit timer/event counters are used together in 16-bit timer/counter mode when bit 4 (tmc514) of 8-bit timer mode control register 51 (tm51) is set to 1. in this mode, the 8-bit timer/event counters are used as a 16-bit interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance in the 8-bit compare registers (cr50 and cr51). at this time, cr50 serves as the lower 8 bits of the 16-bit compare register, and cr51 serves as the higher 8 bits. [setting] <1> set each register. tcl50: select the count clock for tm50. the count clock for tm51, which is cascaded, does not have to be set. cr50 and cr51: compare values. (each compare value can be set in a range of 00h to ffh.) tmc50 and tmc51: select a mode in which the interval timer is cleared and started on match between tm50 and cr50 (or between tm51 and cr51). tm50 tmc50 = 0000 0b : don t care tm51 tmc51 = 0001 0b : don t care <2> the count operation is started by setting tce51 of tmc51 to 1 first, and then tce50 of tmc50 to 1. <3> if the value of cascaded timer tm50 matches the value of cr50, inttm50 of tm50 is generated (tm50 and tm51 are cleared to 00h). <4> after that, inttm50 is repeatedly generated at fixed intervals. cautions 1. be sure to set the compare registers (cr50 and cr51) after stopping the timer operation. 2. even if the 8-bit timers/counters are cascaded, inttm51 of tm51 is generated when the count value of tm51 matches cr51. be sure to mask tm51 to disable this interrupt. 3. set tce50 and tce51 in the order of tm51 and tm50. 4. counting can be restarted or stopped by setting or resetting tce50 of tm50 to 1 or 0. figure 6-14 shows a timing example in the 16-bit resolution cascade mode.
115 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud figure 6-14. operation timing of 16-bit resolution cascade mode (timers 50 and 51) 6.5 notes on 8-bit timer/event counters 50 to 53 (1) error on starting timer an error of up to 1 clock occurs after the timer has been started until a match signal is generated. this is because 8-bit timer counter 5n (tm5n) is started asynchronously with the count pulse. figure 6-15. start timing of 8-bit timer counter count clock tm50 tm51 cr50 cr51 tce50 tce51 inttm50 to50 operation enabled. count starts. interval time 00h 01h n n + 1 ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h 00h 01h 02h m 1 m 00h b 00h n m interrupt request generated. level inverted. counter cleared. operation stops count pulse tm5n count value 00h 01h 02h 03h 04h timer starts n = 0 to 3
116 chapter 6 8-bit timer/event counters 50 to 53 user s manual u15104ej2v0ud (2) operation after changing compare register during timer count operation if a new value of 8-bit compare register 5n (cr5n) is less than the value of 8-bit timer counter 5n (tm5n), counting continues, and tm5n overflows and starts counting from 0. if the new value of cr5n (m) is less than the old value (n), therefore, it is necessary to restart the timer after changing cr5n. figure 6-16. timing after changing compare register value during timer count operation caution be sure to clear tce5n to 0 to set the stop status, except when ti5n input is selected. remarks 1. n > x > m 2. n = 0 to 3 (3) reading tm5n (n = 0 to 3) during timer operation when tm5n is read during operation, the count clock is temporarily stopped. therefore, select a count clock with a high/low level longer than two cycles of the cpu clock. for example, when the cpu clock (f cpu ) is f x , the count clock to be selected should be f x /4 or less in order that tm5n can be read. remark n = 0 to 3 count pulse cr5n tm5n count value nm x 1 x ffh 00h 01h 02h
117 user? manual u15104ej2v0ud chapter 7 basic timer the basic timer is used for time management during program execution. 7.1 function of basic timer the basic timer generates an interrupt request signal (intbtm0) at time intervals of 100 ms. 7.2 configuration of basic timer figure 7-1. block diagram of basic timer caution use the basic timer after setting bit 0 (dtsck0) of the dts system clock select register (detsck) to 1 after power application, and after reset by the reset pin (refer to 5.1 functions of clock generator). the first interrupt request signal (intbtm0) after the dtsck0 flag has been set is generated within 100 to 140 ms. the second signal and those that follow are generated at intervals of 100 ms. divider 4.5 mhz intbtm0
118 chapter 7 basic timer user s manual u15104ej2v0ud 7.3 operation of basic timer an example of the operation of the basic timer is shown below. in this example, the basic timer operates as an interval timer that repeatedly generates an interrupt at time intervals of 100 ms. interrupt request signal (intbtm0) is generated every 100 ms. the timer clock frequency is 10 hz. figure 7-2. operation timing of basic timer by polling the interrupt request flag (btmif0) of this basic timer by software, time management can be carried out. note that btmif0 is not a read & reset flag. figure 7-3. operating timing to poll btmif0 flag for the registers controlling the basic timer, refer to chapter 12 interrupt functions . timer clock (10 hz) btmif0 flag 1 when polled by software 0 is written by software always 1 unless 0 is written by software interrupt acknowledged timer clock (10 hz) intbtm0 interval time (100 ms) interval time interval time interrupt acknowledged
119 user? manual u15104ej2v0ud chapter 8 watchdog timer 8.1 functions of watchdog timer the watchdog timer has the following functions. watchdog timer interval timer selecting oscillation stabilization time caution select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (wdtm). (the watchdog timer and interval timer cannot be used simultaneously.) figure 8-1 shows a block diagram. figure 8-1. block diagram of watchdog timer f x /2 8 run clock input controller divider divided clock selector output controller intwdt reset wdt mode signal 3 division mode selector osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 internal bus run wdtm4 wdtm3 oscillation stabilization time select register (osts) watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm)
120 chapter 8 watchdog timer user s manual u15104ej2v0ud (1) watchdog timer mode an inadvertent program loop is detected. upon detection of the inadvertent program loop, a non-maskable interrupt request or reset can be generated. table 8-1. watchdog timer inadvertent program loop detection times inadvertent program loop detection time 2 12 /f x (910 s) 2 13 /f x (1.82 ms) 2 14 /f x (3.64 ms) 2 15 /f x (7.28 ms) 2 16 /f x (14.6 ms) 2 17 /f x (29.1 ms) 2 18 /f x (58.3 ms) 2 20 /f x (233 ms) remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz (2) interval timer mode interrupt requests are generated at the preset time intervals. table 8-2. interval time interval time 2 12 /f x (910 s) 2 13 /f x (1.82 ms) 2 14 /f x (3.64 ms) 2 15 /f x (7.28 ms) 2 16 /f x (14.6 ms) 2 17 /f x (29.1 ms) 2 18 /f x (58.3 ms) 2 20 /f x (233 ms) remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz
121 chapter 8 watchdog timer user s manual u15104ej2v0ud 8.2 configuration of watchdog timer the watchdog timer consists of the following hardware. table 8-3. configuration of watchdog timer item configuration control registers watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) oscillation stabilization time select register (osts) 8.3 registers controlling watchdog timer the following three types of registers are used to control the watchdog timer. watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) oscillation stabilization time select register (osts)
122 chapter 8 watchdog timer user s manual u15104ej2v0ud (1) watchdog timer clock select register (wdcs) this register sets the watchdog timer and overflow time of the interval timer. wdcs is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdcs to 00h. figure 8-2. format of watchdog timer clock select register (wdcs) remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz 0 7 0 6 0 0 4 0 3210 ff42h address wdcs symbol wdcs2 wdcs1 wdcs0 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 wdcs2 wdcs1 wdcs0 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 20 /f x watchdog timer/interval timer overflow time (910 s) (1.82 ms) (3.64 ms) (7.28 ms) (14.6 ms) (29.1 ms) (58.3 ms) (233 ms)
123 chapter 8 watchdog timer user s manual u15104ej2v0ud (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 8-3. format of watchdog timer mode register (wdtm) notes 1. once set to 1, run cannot be cleared to 0 by software. therefore, use reset input to clear run to 0. 2. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 3. wdtm starts interval timer operation at a time run is set to 1. caution when run is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the timer clock select register (wdcs). remark : don t care run <7> 0 6 0 wdtm4 4 wdtm3 3210 fff9h address wdtm symbol 000 5 00h after reset r/w r/w run 0 1 watchdog timer operating mode selection note 1 wdtm3 watchdog timer operating mode selection note 2 wdtm4 interval timer mode note 3 (maskable interrupt occurs upon generation of an overflow.) watchdog timer mode 1 (non-maskable interrupt occurs upon generation of an overflow.) watchdog timer mode 2 (reset operation is activated upon generation of an overflow.) 0 1 0 1 1 count stop counter is cleared and counting starts.
124 chapter 8 watchdog timer user s manual u15104ej2v0ud (3) oscillation stabilization time select register (osts) this register is used to select the time required for oscillation to stabilize after the reset signal has been input or the stop mode has been released. this register is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. therefore, it takes 2 17 /f x to release the stop mode by reset input. figure 8-4. format of oscillation stabilization time select register (osts) osts2 osts1 osts0 selection of oscillation stabilization time 0002 12 /f x (910 s) 0012 14 /f x (3.64 ms) 0102 15 /f x (7.28 ms) 0112 16 /f x (14.6 ms) 1002 17 /f x (29.1 ms) other than above setting prohibited remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz address fffah symbol osts 7 0 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 after reset 04h r/w r/w
125 chapter 8 watchdog timer user s manual u15104ej2v0ud 8.4 operations of watchdog timer 8.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer operates to detect any inadvertent program loop. the watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (wdcs0 to wdcs2) of timer clock select register 2 (wdcs). a watchdog timer count operation is started by setting bit 7 (run) of wdtm to 1. after the watchdog timer count operation starts, set run to 1 within the set inadvertent program loop time interval. the watchdog timer can be cleared and counting started by setting run to 1. if run is not set to 1 and the inadvertent program loop detection time has elapsed, a system reset or a non-maskable interrupt request is generated according to the value of wdtm bit 3 (wdtm3). the watchdog timer continues operating in the halt mode but stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. caution the actual inadvertent program loop detection time may be shorter than the set time by a maximum of 0.5%. table 8-4. watchdog timer inadvertent program loop detection time inadvertent program loop detection time 2 12 /f x (910 s) 2 13 /f x (1.82 ms) 2 14 /f x (3.64 ms) 2 15 /f x (7.28 ms) 2 16 /f x (14.6 ms) 2 17 /f x (29.1 ms) 2 18 /f x (58.3 ms) 2 20 /f x (233 ms) remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz
126 chapter 8 watchdog timer user s manual u15104ej2v0ud 8.4.2 interval timer operation the watchdog timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 0. the count clock (interval time) can be selected by using bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). by setting bit 7 (run) of wdtm to 1, the watchdog timer starts operating as an interval timer. when the watchdog timer operates as an interval timer, the interrupt mask flag (wdtmk) and priority specification flag (wdtpr) are validated and the maskable request interrupt (intwdt) can be generated. among maskable interrupt requests, the intwdt default has the highest priority. the interval timer continues operating in the halt mode but stops in stop mode. thus, set run to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless reset is input. 2. the interval time just after setting by wdtm may be shorter than the set time by a maximum of 0.5%. table 8-5. interval timer interval time interval time 2 12 /f x (910 s) 2 13 /f x (1.82 ms) 2 14 /f x (3.64 ms) 2 15 /f x (7.28 ms) 2 16 /f x (14.6 ms) 2 17 /f x (29.1 ms) 2 18 /f x (58.3 ms) 2 20 /f x (233 ms) remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz
127 user? manual u15104ej2v0ud chapter 9 buzzer output controller 9.1 functions of buzzer output controllers the pd178054 subseries has the following two types of buzzer output controllers. beep0 buz beep0 outputs a square wave of the buzzer frequency selected by beep clock select register 0 (beepcl0) from the beep0/p36 pin. buz outputs a square wave of the buzzer frequency selected by the clock output select register (cks) from the buz/p37 pin. figures 9-1 and 9-2 show the block diagrams of beep0 and buz. figure 9-1. block diagram of beep0 figure 9-2. block diagram of buz remark f x : system clock frequency internal bus beep cl02 beep cl01 beep cl00 beep clock select register 0 (beepcl0) beep0/p36 1 khz 1.5 khz 3 khz 4 khz output latch (p36) pm36 selector internal bus bzoe bcs1 bcs0 clock output select register (cks) buz/p37 f x /2 10 f x /2 11 f x /2 12 f x /2 13 output latch (p37) pm37 selector
128 chapter 9 buzzer output controlller user s manual u15104ej2v0ud 9.2 configuration of buzzer output controllers the buzzer output controllers consist of the following hardware. table 9-1. configuration of buzzer output controllers (1) beep0 item configuration control register beep clock select register 0 (beepcl0) (2) buz item configuration control register clock output select register (cks) 9.3 registers controlling buzzer output controllers 9.3.1 beep0 beep0 is controlled by the following register. beep clock select register 0 (beepcl0) (1) beep clock select register 0 (beepcl0) this register selects the frequency of the buzzer output. beepcl0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-3. format of beep clock select register 0 (beepcl0) beep beep beep selection of frequency of beep0 output cl02 cl01 cl00 0 disables buzzer output (port function) 1 0 0 1 khz 0 0 1 3 khz 1 1 0 4 khz 1 1 1 1.5 khz caution the selected clock may not be correctly output during the period of 1 cycle immediately after the output clock has been changed. 76543 00000 2 beep cl02 1 beep cl01 0 beep cl00 symbol beep cl0 address ff41h after reset 00h r/w r/w
129 chapter 9 buzzer output controller user s manual u15104ej2v0ud 9.3.2 buz buz is controlled by the following register. clock output select register (cks) (1) clock output select register (cks) this register enables/disables buzzer output and sets the clock of the buzzer output. cks is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-4. format of clock output select register (cks) bzoe enables/disables output of buz 0 low-level output 1 enables buzzer output bcs1 bcs0 selects output clock of buz 00f x /2 10 (4.39 khz) 01f x /2 11 (2.20 khz) 10f x /2 12 (1.10 khz) 11f x /2 13 (549 hz) remarks 1. f x : system clock frequency 2. ( ): f x = 4.5 mhz 9.4 operation of buzzer output controllers the buzzer frequency is output by the following procedure. (1) beep0 <1> select a buzzer output frequency using bits 0 to 2 (beepcl00 to beepcl02) of beep clock select register 0 (beepcl0). <2> set the output latch of p36 to 0. <3> set bit 6 (pm36) of the port mode register 3 to 0 (set the output mode). (2) buz <1> select a buzzer output frequency by using bits 5 and 6 (bcs0 and bcs1) of the clock output select register (cks) (disable buzzer output). <2> set bit 7 (bzoe) of cks to 1 and enable buzzer output. <3> set the output latch of p37 to 0. <4> set bit 7 (pm37) of the port mode register 3 to 0 (set output mode). <7>6543 bzoe bcs1 bcs0 0 0 2 0 1 0 0 0 symbol cks address ff40h after reset 00h r/w r/w
130 user? manual u15104ej2v0ud chapter 10 a/d converter 10.1 functions of a/d converter the a/d converter converts analog inputs into digital values and consists of 6 channels (ani0 to ani5) with an 8-bit resolution. the conversion method is based on successive approximation and the conversion result is held in 8-bit a/d conversion result register 3 (adcr3). conversion is started by setting a/d converter mode register 3. select one analog input channel from ani0 to ani5 and carry out a/d conversion. when a/d conversion is complete, the next a/d conversion is started immediately. each time an a/d conversion operation ends, an interrupt request (intad3) is generated. 10.2 configuration of a/d converter the a/d converter consists of the following hardware. table 10-1. configuration of a/d converter item configuration analog inputs 6 channels (ani0 to ani5) control registers a/d converter mode register 3 (adm3) analog input channel specification register 3 (ads3) power-fail comparison mode register 3 (pfm3) registers successive approximation register (sar) a/d conversion result register 3 (adcr3) power-fail comparison threshold value register 3 (pft3)
131 chapter 10 a/d converter user? manual u15104ej2v0ud figure 10-1. block diagram of a/d converter ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 sample & hold circuit voltage comparator voltage comparator successive approximation register (sar) a/d conversion result register 3 (adcr3) controller controller v dd gnd adcs3 intad3 pfen3 adcs3 ads33 ads32 ads31 ads30 0 fr32 fr31 fr30 0 0 0 pfcm3 pfhrm3 power-fail comparison mode register 3 (pfm3) a/d converter mode register 3 (adm3) analog input channel specification register 3 (ads3) 4 internal bus selector tap selector power-fail comparison threshold value register 3 (pft3)
132 chapter 10 a/d converter user s manual u15104ej2v0ud (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is set (termination of a/d conversion), the sar contents are transferred to the a/d conversion result register. (2) a/d conversion result register 3 (adcr3) this register is an 8-bit register to store the a/d conversion result. each time a/d conversion terminates, the conversion result is loaded from the successive approximation register (sar). adcr is read with an 8-bit memory manipulation instruction. reset input makes adcr undefined. caution when data is written to a/d converter mode register 3 (adm3) and analog input channel specification register 3 (ads3), the contents of adcr3 may be undefined. read the result of conversion after conversion has been completed and before writing data to adm3 and ads3; otherwise the correct conversion result may not be read. (3) power-fail comparison threshold value register 3 (pft3) this register sets a threshold value to be compared with the value of a/d conversion result register 3 (adcr3). pft3 is read or written with an 8-bit memory manipulation instruction. (4) sample & hold circuit the sample & hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (5) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (6) resistor string the resistor string is connected between v dd and gnd, and generates a voltage to be compared to the analog input. (7) ani0 to ani5 pins these are the 6-channel analog input pins through which analog signals to undergo a/d conversion are input to the a/d converter. cautions 1. use the ani0 to ani5 input voltages within the specified range. if a voltage higher than v dd or lower than gnd is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes undefined and may adversely affect the converted values of other channels. 2. the analog input pins (ani0 to ani5) are also used as input port pins (p10 to p15). when one of ani0 to ani5 is selected for a/d conversion, do not execute an input instruction to port 1; otherwise the conversion resolution may drop. if a digital pulse is applied to the pin adjacent to the pin executing a/d conversion, the a/d conversion value may not be obtained as expected due to coupling noise. do not apply a pulse to the pin adjacent to the pin executing a/d conversion.
133 chapter 10 a/d converter user s manual u15104ej2v0ud 10.3 registers controlling a/d converter the following three registers control the a/d converter. a/d converter mode register 3 (adm3) analog input channel specification register 3 (ads3) power-fail comparison mode register 3 (pfm3) (1) a/d converter mode register 3 (adm3) this register selects the conversion time of the analog input to be converted and starts or stops the conversion operation. adm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-2. format of a/d converter mode register 3 (adm3) adcs3 control of a/d conversion operation 0 stops conversion operation 1 enables conversion operation fr32 fr31 fr30 selection of conversion time 0 0 0 288/f x (64.0 s) 0 0 1 240/f x (53.3 s) 0 1 0 192/f x (42.7 s) 1 0 0 144/f x (32.0 s) 1 0 1 120/f x (26.7 s) 1 1 0 96/f x (21.3 s) other than above setting prohibited cautions 1. the conversion result is undefined immediately after bit 7 (adcs3) has been set to 1. 2. to change the data of bits 3 to 5 (fr30 to fr32), stop the a/d conversion operation. remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz address ff12h symbol adm3 <7> adcs3 6 0 5 fr32 4 fr31 3 fr30 2 0 1 0 0 0 after reset 00h r/w r/w
134 chapter 10 a/d converter user s manual u15104ej2v0ud (2) analog input channel specification register 3 (ads3) this register specifies the input channel of the analog voltage to be converted. ads3 is set with an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-3. format of analog input channel specification register 3 (ads3) ads33 ads32 ads31 ads30 specification of analog input channel 0000 ani0 0001 ani1 0010 ani2 0011 ani3 0100 ani4 0101 ani5 other than above setting prohibited address ff13h symbol ads3 6 0 7 0 5 0 4 0 3 ads33 2 ads32 1 ads31 0 ads30 after reset 00h r/w r/w
135 chapter 10 a/d converter user s manual u15104ej2v0ud (3) power-fail comparison mode register 3 (pfm3) pfm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-4. format of power-fail comparison mode register 3 (pfm3) pfen3 enable/disable of power-fail comparison 0 disables power-fail comparison 1 enables power-fail comparison pfcm3 selection of power-fail comparison mode 0 generates interrupt request (intad) when adcr3 pft 1 generates interrupt request (intad) when adcr3 < pft note pfhrm3 selection of power-fail halt repeat mode 0 disables power-fail halt repeat mode 1 enables power-fail halt repeat mode note when bit 5 (pfhrm3) is set to 1, power-fail comparison manipulation is enabled in the halt mode in which a/d conversion is repeated until an interrupt request (intad3) is generated (this bit is reset to 0 when intad3 is generated). address ff16h symbol pfm3 <7> pfen3 <6> pfcm3 <5> pfhrm3 4 0 3 0 2 0 1 0 0 0 after reset 00h r/w r/w
136 chapter 10 a/d converter user s manual u15104ej2v0ud 10.4 operations of a/d converter 10.4.1 basic operations of a/d converter (1) select one channel for a/d conversion with a/d converter analog input channel specification register 3 (ads3). (2) sample the voltage input to the selected analog input channel with the sample & hold circuit. (3) sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until termination of a/d conversion. (4) bit 7 of the successive approximation register (sar) is set and the tap selector sets the series resistor string voltage tap to (1/2) v dd . (5) the voltage difference between the series resistor string voltage tap and analog input is compared with a voltage comparator. if the analog input is greater than (1/2) v dd , the msb of sar remains set. if the input is smaller than (1/2) v dd , the msb is reset. (6) next, bit 6 of sar is automatically set and the operation proceeds to the next comparison. in this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. bit 7 = 1: (3/4) v dd bit 7 = 0: (1/4) v dd the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated with the result as follows. analog input voltage voltage tap: bit 6 = 1 analog input voltage < voltage tap: bit 6 = 0 (7) comparison of this sort continues up to bit 0 of sar. (8) upon completion of the comparison of 8 bits, any valid digital resultant value remains in sar and the resultant value is transferred to and latched in a/d conversion result register 3 (adcr3). at the same time, the a/d conversion termination interrupt request (intad3) can also be generated. caution the value immediately after a/d conversion has been started may not satisfy the ratings.
137 chapter 10 a/d converter user s manual u15104ej2v0ud figure 10-5. a/d converter basic operation a/d conversion operations are performed continuously until bit 7 (adcs3) of the adm is reset (0) by software. if a write to adm3 or ads3 is performed during an a/d conversion operation, the conversion operation is initialized, and if the adcs3 bit is set (1), conversion starts again from the beginning. after reset input, the value of adcr3 is undefined. sar adcr3 intad3 a/d converter operation sampling time sampling a /d conversion conversion time undefined 80h c0h or 40h conversion result conversion result
138 chapter 10 a/d converter user s manual u15104ej2v0ud 10.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani5) and the a/d conversion result (the value stored in a/d conversion result register 3 (adcr3) is shown by the following expression. adcr3 = int ( 256 + 0.5) or (adcr3 0.5) v in < (adcr3 + 0.5) remark int( ): function which returns integer parts of value in parentheses. v in : analog input voltage v dd :v dd pin voltage adcr3: a/d conversion result register 3 (adcr3) value figure 10-6 shows the relationship between the analog input voltage and the a/d conversion result. figure 10-6. relationship between analog input voltage and a/d conversion result v in v dd v dd 256 v dd 256 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 255 254 253 3 2 1 0 a/d conversion results (adcr3) input voltage/v dd
139 chapter 10 a/d converter user s manual u15104ej2v0ud 10.4.3 a/d converter operating mode the a/d converter has the following two modes: a/d conversion operation mode: in this mode, the voltage applied to the analog input pin selected from ani0 to ani5 is converted into a digital signal. the result of the a/d conversion is stored in a/d conversion result register 3 (adcr3), and at the same time, an interrupt request signal (intad3) is generated. power-fail comparison mode: the digital value resulting from a/d conversion is compared with the value assigned to power-fail comparison threshold value register 3 (pft3) is compared. if the result of the comparison matches the condition set by bit 6 (pfcm3) of power-fail comparison mode register 3 (pfm3), an interrupt request signal (intad3) is generated. (1) a/d conversion operation mode when bit 7 (adcs3) of a/d converter mode register 3 (adm3) is set to 1, the a/d conversion starts on the voltage applied to the analog input pins specified with bits 0 to 3 (ads30 to ads33) of ads3. upon termination of the a/d conversion, the conversion result is stored in a/d conversion result register 3 (adcr3) and the interrupt request signal (intad3) is generated. after one a/d conversion operation is started and terminated, the next a/d conversion operation starts immediately. the a/d conversion operation continues repeatedly until new data is written to adm3. if data is written to adcs3 again during a/d conversion, the converter suspends its a/d conversion operation and starts a/d conversion on the newly written data. if data with adcs3 set to 0 is written to adm3 during a/d conversion, the a/d conversion operation stops immediately.
140 chapter 10 a/d converter user s manual u15104ej2v0ud figure 10-7. a/d conversion operation remarks 1. n = 0, 1, ... , 5 2. m = 0, 1, ... , 5 note the conversion result is illegal immediately after bit 7 (adcs3) of a/d converter mode register 3 (adm3) has been set to 1 (to enable conversion). caution reset bit 5 (pfhrm3) of power-fail comparison mode register 3 (pfm3) to 0. conversion start adcs3 = 1 a /d conversion adcr3 intad3 (when pfen3 = 0) undefined note anin anim anin anim anim anin anin ads3 rewrite adm3 rewrite adcs3 = 0 conversion suspended conversion results are not stored stop stop
141 chapter 10 a/d converter user s manual u15104ej2v0ud (2) power-fail comparison mode in the power-fail comparison mode, the digital value converted from analog input is compared in units of 8 bits. if the result of the comparison matches the condition set by bit 6 (pfcm3) of power-fail comparison mode register 3 (pfm3), an interrupt request (intad3) is generated. moreover, the power-fail comparison mode can be used in the halt mode. at this time, the halt mode can be released by generating the interrupt request signal (intad3) as a result of comparison (however, the a/ d operation must be executed before the halt instruction is executed). to set the power-fail comparison mode, set bit 7 (peen3) of pfm3 to 1, set bit 6 (pfcm3) to the generation condition of intad, and assign the threshold value to be compared with the value of a/d conversion result register 3 (adcr3) to power-fail comparison threshold value register 3 (pft3). by setting bit 7 (adcs3) of a/d converter mode register 3 (adm3) to 1, the voltage applied to the analog input pin specified by ads3 is converted into a digital signal. when the a/d conversion has been completed, the result of the conversion is stored in adcr3. this conversion result is compared with the value set in pft3 and if the result of the comparison matches the condition set by bit 6 (pfcm3) of pfm3, an interrupt request signal (intad3) is generated. figure 10-8. power-fail comparison threshold value register 3 (pft3) remark bit 7 (pft37) is the msb, and bit 0 (pft30) is the lsb. for the setting value, refer to 10.4.2 input voltage and conversion results . cautions 1. in the power-fail comparison mode, the first result (a/d conversion result and interrupt request (intad)) of the a/d conversion (started by setting bit 7 (adcs3) of a/d converter mode register 3 (adm3) to 1) is not correct. 2. when executing a/d conversion in the halt mode using the power-fail halt repeat mode, clear the interrupt request flag (adif) after the first conversion has been completed immediately after bit 7 (adcs3) of adm3 has been set to 1, and bit 5 (pfhrm3) of power- fail comparison mode register 3 (pfm3) has been set to 1, before executing the halt instruction. 3. to set the power-fail comparison mode in the halt mode, be sure to set bit 5 (pfhrm3) of pfm3 to 1 before executing the halt instruction; otherwise comparison cannot be performed correctly because the conversion result in the halt mode is not stored in a/ d conversion result register 3 (adcr3). if bit 5 (pfhrm3) of pfm3 is set in the normal operating mode (other than halt mode), the a/d conversion is not performed correctly. therefore, be sure to clear this bit to 0 in the normal mode. symbol pft3 7 pft37 6 pft36 5 pft35 4 pft34 3 pft33 2 pft32 1 pft31 0 pft30 r/w r/w after reset 00h address ff15h
142 chapter 10 a/d converter user s manual u15104ej2v0ud figure 10-9. a/d conversion operation in power-fail comparison mode (1/3) (1) in normal mode (other than halt mode) notes 1. the conversion data is undefined immediately after bit 7 (adcs3) of a/d converter mode register 3 (adm3) is set to 1 (to start conversion). 2. the first result of the a/d conversion (a/d conversion result and interrupt request) is not correct. do not use this result because there is a possibility that it will be determined that the comparison condition has matched even if it has not. caution set power-fail comparison threshold value register 3 (pft3) and power-fail comparison mode register 3 (pfm3) before starting conversion. be sure to reset bit 5 (pfhrm3) of pfm3 to 0 (to disable halt repeat mode setting). remark n = 0, 1, ... 5 m = 0, 1, ... 5 conversion starts adcs3 = 1 ads3 rewrite adm3 rewrite adcs3 = 0 a/d conversion adcr3 pft3, pfm3 set conversion stopped stop stop comparison condition does not match note 2 comparison condition matches anin anin anin anin anim anim unde- fined note 1 anin anin anim intad3 (when pfen3 = 1) comparison condition does not match
143 chapter 10 a/d converter user s manual u15104ej2v0ud figure 10-9. a/d conversion operation in power-fail comparison mode (2/3) (2) in halt repeat mode (when generation of interrupt (intad3) is used to release halt mode) notes 1. the conversion data is undefined immediately after bit 7 (adcs3) of a/d converter mode register 3 (adm3) is set to 1 (to start conversion). 2. when executing a/d conversion in the halt mode by using the power-fail comparison mode, clear the interrupt request flag (adif) after the first conversion has been completed immediately after bit 7 (adcs3) of adm3 has been set to 1, and bit 5 (pfhrm3) of power-fail comparison mode register 3 (pfm3) has been set to 1, before executing the halt instruction. 3. the first result of the a/d conversion (a/d conversion result and interrupt request) is not correct. do not use this result because there is a possibility that it will be determined that the comparison condition has matched even if it has not. caution be sure to set bit 5 (pfhrm3) of pfm3 to 1 (to enable the halt repeat mode setting). remark n = 0, 1, ... 5 a/d conversion adcr3 stop stop comparison condition does not match comparison condition does not match note 3 comparison condition matches comparison condition matches (pfhrm3 is reset) anin anin anin anin anin anin unde- fined note 1 anin anin anin anin conversion starts adcs3 = 1 adif clear pfhrm3 = 1 adm3 rewrite adcs3 = 0 halt instruction note 2 halt operation interrupt request releases halt mode intad3 (when pfen3 = 1) pft3, pfm3 set
144 chapter 10 a/d converter user s manual u15104ej2v0ud figure 10-9. a/d conversion operation in power-fail comparison mode (3/3) (3) in halt repeat mode (when generation of interrupt (intad3) is not used to release halt mode) notes 1. the conversion data is undefined immediately after bit 7 (adcs3) of a/d converter mode register 3 (adm3) is set to 1 (to start conversion). 2. when executing a/d conversion in the halt mode by using the power-fail halt repeat mode, clear the interrupt request flag (adif) after the first conversion has been completed immediately after bit 7 (adcs3) of adm3 has been set to 1, and bit 5 (pfhrm3) of power-fail comparison mode register 3 (pfm3) has been set to 1, before executing the halt instruction. 3. the first result of the a/d conversion (a/d conversion result and interrupt request) is not correct. do not use this result because there is a possibility that it will be determined that the comparison condition has matched even if it has not. caution be sure to set bit 5 (pfhrm3) of pfm3 to 1 (to enable the halt repeat mode setting). remark n = 0, 1, ... 5 a/d conversion adcr3 stop comparison condition matches (pfhrm3 is reset) anin anin anin anin anin unde- fined note 1 anin previous conversion result a/d conversion is in progress but conversion operation is stopped previous conversion result ... conversion starts adcs3 = 1 adif clear pfhrm3 = 1 halt instruction note 2 halt operation interrupt request (intad) does not release halt mode intad3 (when pfen3 = 1) comparison condition does not match note 3 ... pft3, pfm3 set
145 chapter 10 a/d converter user s manual u15104ej2v0ud 10.5 notes on a/d converter (1) current consumption in standby mode the a/d converter is stopped in the standby mode. at this time, the current consumption can be reduced by stopping the conversion operation (by resetting bit 7 (adcs3) of a/d converter mode register 3 (adm3) to 0). figure 10-10 shows how to reduce the current consumption in the standby mode. figure 10-10. example of reducing current consumption in standby mode (2) input range of ani0 to ani5 the input voltages of ani0 to ani5 should be within the specified range. in particular, if a voltage above v dd or below gnd is input (even if within the absolute maximum rating range), the conversion value for that channel will be undefined. the conversion values of the other channels may also be affected. (3) conflicting operations <1> conflict between writing a/d conversion result register 3 (adcr3) on completion of conversion and reading adcr3 by an instruction reading adcr3 takes precedence. after adcr3 has been read, a new conversion result is written to adcr3. <2> conflict between writing adcr3 on completion of conversion and writing a/d converter mode register 3 (adm3) or writing analog input channel specification register 3 (ads3) writing adm3 or ads3 takes precedence. adcr3 is not written. nor is the conversion completion interrupt request signal (intad3) generated. v dd gnd p-ch series resistor string adcs3
146 chapter 10 a/d converter user s manual u15104ej2v0ud (4) ani0 to ani5 the analog input pins ani0 to ani5 also function as input port (p10 to p15) pins. when a/d conversion is performed with any of pins ani0 to ani5 selected, be sure not to execute a port1 input instruction while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if analog input channel specification register 3 (ads3) is changed. caution is therefore required since, if an analog input pin is changed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads3 rewrite, and when adif is read immediately after the adm rewrite, adif may be set despite the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is stopped and then resumed, clear adif before it is resumed. figure 10-11. a/d conversion end interrupt request generation timing remarks 1. n = 0, 1, ..., 5 2. m = 0, 1, ..., 5 (6) conversion result immediately after starting a/d conversion the first a/d conversion result value is undefined immediately after the a/d conversion operation has been started. poll the a/d conversion completion interrupt request (intad3) and discard the first conversion result. (7) reading a/d conversion result register 3 (adcr3) if data is written to a/d converter mode register 3 (adm3) and analog input channel specification register 3 (ads3), the contents of adcr3 can be undefined. read the conversion value before writing adm3 and ads3 after the conversion operation has been completed; otherwise the correct conversion result may not be read. a /d conversion adcr3 intad3 anin anin anim anim anin anin anim anim adm3 rewrite (start of anin conversion) ads3 rewrite (start of anim conversion) adif is set but anim conversion has not ended
147 user? manual u15104ej2v0ud chapter 11 serial interfaces sio30 to sio32 11.1 functions of serial interfaces sio30 to sio32 the serial interface sio3n has the following two modes. (1) operation stop mode this mode is used when serial transfer is not performed. for details, refer to 11.4.1 operation stop mode . (2) 3-wire serial i/o mode (msb first) in this mode, 8-bit data is transferred by using three lines: serial clock (sck3n), serial output (so3n), and serial input (si3n) lines. because transmission and reception can be executed simultaneously in this mode, the processing time of data transfer can be shortened. the first bit of the 8-bit data to be transferred is the msb. the 3-wire serial i/o mode is useful for connecting a peripheral i/o or display controller with a clocked serial interface. for details, refer to 11.4.2 3-wire serial i/o mode . figures 11-1 to 11-3 show the block diagrams of the serial interface sio3n. remark n = 0 to 2 figure 11-1. block diagram of serial interface sio30 internal bus 8 interrupt request signal generator selector serial clock counter serial clock controller serial i/o shift register 30 (sio30) si30/p70 so30/p71 p71 output latch pm71 pm72 sck30/p72 intcsi30 f x /2 4 f x /2 5 f x /2 6 p72 output latch
148 chapter 11 serial interfaces sio30 to sio32 user s manual u15104ej2v0ud figure 11-2. block diagram of serial interface sio31 figure 11-3. block diagram of serial interface sio32 internal bus 8 interrupt request signal generator selector serial clock counter serial clock controller serial i/o shift register 31 (sio31) si31/p74 so31/p75 p75 output latch pm75 pm76 sck31/p76 intcsi31 f x /2 4 f x /2 5 f x /2 6 p76 output latch 8 internal bus selector selector selector selector pm121 pm122 pm125 p121 output latch p124 output latch p122 output latch p125 output latch pm124 si32/p120 si321/p123 sck32/p122 sck321/p125 so32/p121 so321/p124 serial i/o shift register 32 (sio32) serial clock counter serial clock controller interrupt request signal generator selector intcsi32 f x /2 4 f x /2 5 f x /2 6
149 chapter 11 serial interfaces sio30 to sio32 user s manual u15104ej2v0ud 11.2 configuration of serial interfaces sio30 to sio32 the serial interface sio3n consists of the following hardware. table 11-1. configuration of serial interfaces sio30 to sio32 item configuration register serial i/o shift registers 30 to 32 (sio30 to sio32) control registers serial operating mode registers 30 to 32 (csim30 to csim32) serial port select register 32 (sio32sel) (1) serial i/o shift registers 30 to 32 (sio30 to sio32) these 8-bit registers convert parallel data into serial data and transmit or receive the serial data (shift operation) in synchronization with a serial clock. sio3n is set with an 8-bit memory manipulation instruction. serial operation is started by writing or reading data to or from sio3n when bit 7 (csie3n) of serial operating mode register 3n (csim3n) is 1. data written to sio3n is output to a serial output line (so3n) for transmission. data is read to sio3n from a serial input line (si3n) for reception. reset input makes the values of these registers undefined. caution do not execute access other than that for the transfer start trigger to sio3n during a transfer operation (the read operation is disabled when mode3n = 0, and the write operation is disabled when mode3n = 1). remark n = 0 to 2
150 chapter 11 serial interfaces sio30 to sio32 user s manual u15104ej2v0ud 11.3 registers controlling serial interfaces sio30 to sio32 the following registers control the serial interface sio3n. serial operating mode registers 30 to 32 (csim30 to csim32) serial port select register 32 (sio32sel) (1) serial operating mode register 30 to 32 (csim30 to csim32) these registers select the serial clock of sio3n and an operating mode, and enable or disable the operation. csim3n is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 11-4. format of serial operating mode registers 30 to 32 (csim30 to csim32) csie3n enable/disable of sio3n operation shift register operation serial counter port 0 disables operation cleared port function note 1 1 enables operation enables counter operation serial function + port function note 2 mode3n transfer operation mode flag operating mode transfer start trigger so3n output 0 transmit or transmit/receive mode sio3n write serial output 1 receive only mode sio3n read fixed to low level note 3 scl3n1 scl3n0 clock selection 0 0 external clock input to sck3n 01f x /2 4 (281 khz) 10f x /2 5 (141 khz) 11f x /2 6 (70.3 khz) notes 1. the si3n, so3n, and sck3n pins can be used as port pins when csie3n = 0 (when sio3n operation is stopped). 2. when csie3n = 1 (when sio3n operation is enabled), the si3n pin can be used as a port pin if only the transmission function is used, and the so3n pin can be used as a port pin in the receive mode. 3. the so3n pin can be used as a port pin. remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz <7>6543 csie30 0000 2 mode30 1 scl301 0 scl300 symbol csim30 r/w r/w after reset 00h address ff6fh <7>6543 csie31 0000 2 mode31 1 scl311 0 scl310 csim31 r/w 00h ff6dh <7>6543 csie32 0000 2 mode32 1 scl321 0 scl320 csim32 r/w 00h ff6bh
151 chapter 11 serial interfaces sio30 to sio32 user s manual u15104ej2v0ud caution set the port mode register (pm ) as follows in the 3-wire serial i/o mode. set the output latch to 0. serial type serial interface serial interface serial interface sio32 operation mode sio30 sio31 s32sel0 = 0 s32sel0 = 1 serial clock output pm72 = 0 pm76 = 0 pm122 = 0 pm125 = 0 (master transmission or (set p72/sck30 pin (set p76/sck31 pin (set p122/sck32 pin (set p125/sck321 reception) to output mode) to output mode) to output mode) pin to output mode) serial clock input pm72 = 1 pm76 = 1 pm122 = 1 pm125 = 1 (slave transmission or reception) (set p72/sck30 pin (set p76/sck31 pin (set p122/sck32 pin (set p125/sck321 to input mode) to input mode) to input mode) pin to input mode) in transmit or transmit/receive pm71 = 0 pm75 = 0 pm121 = 0 pm124 = 0 mode (set p71/so30 pin to (set p75/so31 pin to (set p121/so32 pin (set p124/so321 pin output mode) output mode) to output mode) to output mode) in receive mode pm70 = 1 pm74 = 1 pm120 = 1 pm123 = 1 (set p70/si30 pin to (set p74/si31 pin to (set p120/si32 pin to (set p123/si321 pin input mode) input mode) input mode) to input mode) (2) serial port select register 32 (sio32sel) this register selects the port used for serial interface sio32. sio32sel is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 11-5. format of serial port select register 32 (sio32sel) s32sel0 serial interface sio32 port selection si pin so pin sck pin 0 note 1 p120/si32 p121/so32 p122/sck32 1 note 2 p123/si321 p124/so321 p125/sck321 notes 1. the p123/si321, p124/so321, p125/sck321 pins can be used as port pins. 2. the p120/si32, p121/so32, p122/sck32 pins can be used as port pins. 76543 00000 2 0 1 0 0 s32sel0 symbol sio32sel r/w r/w after reset 00h address ff69h
152 chapter 11 serial interfaces sio30 to sio32 user s manual u15104ej2v0ud 11.4 operations of serial interfaces sio30 to sio32 this section explains the two modes of the serial interfaces sio30 to sio32. 11.4.1 operation stop mode in this mode, serial transfer is not performed. the alternate-function pins used for the serial interface can be used as ordinary i/o port pins. (1) register setting the operation stop mode is set using serial operating mode register 3n (csim3n). csim3n is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. csie3n enable/disable of sio3n operation shift register operation serial counter port 0 disables operation cleared port function note 1 1 enables operation enables count operation serial function + port function note 2 notes 1. the si3n, so3n, and sck3n pins can be used as port pins when csie3n = 0 (when sio3n operation is stopped). 2. when csie3n = 1 (when sio3n operation is enabled), the si3n pin can be used as a port pin if only the transmission function is used, and the so3n pin can be used as a port pin in the receive mode. remark n = 0 to 2 r/w r/w address ff6fh after reset 00h symbol csim30 <7> csie30 6 0 5 0 4 0 3 0 2 mode30 1 scl301 0 scl300 r/w ff6dh 00h csim31 <7> csie31 6 0 5 0 4 0 3 0 2 mode31 1 scl311 0 scl310 r/w ff6bh 00h csim32 <7> csie32 6 0 5 0 4 0 3 0 2 mode32 1 scl321 0 scl320
153 chapter 11 serial interfaces sio30 to sio32 user s manual u15104ej2v0ud 11.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connecting a peripheral i/o or display controller equipped with a clocked serial interface. in this mode, communication is executed by using three lines: serial clock (sck3n), serial output (so3n), and serial input (si3n) lines. (1) register setting the 3-wire serial i/o mode is set using serial operating mode register 3n (csim3n). these registers are set with a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. csie3n enable/disable of sio3n operation shift register operation serial counter port 0 disables operation cleared port function note 1 1 enables operation enables counter operation serial function + port function note 2 mode3n transfer operation mode flag operating mode transfer start trigger so3n output 0 transmit or transmit/receive mode sio3n write serial output 1 receive-only mode sio3n read fixed to low level note 3 scl3n1 scl3n0 clock selection 0 0 external clock input to sck3n 01f x /2 4 (281 khz) 10f x /2 5 (141 khz) 11f x /2 6 (70.3 khz) notes 1. the si3n, so3n, and sck3n pins can be used as port pins when csie3n = 0 (when sio3n operation is stopped). 2. when csie3n = 1 (when sio3n operation is enabled), the si3n pin can be used as a port pin if only the transmission function is used, and the so3n pin can be used as a port pin in the receive mode. 3. the so3n pin can be used as a port pin. remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz symbol csim30 <7> csie30 6 0 5 0 4 0 3 0 2 mode30 1 scl301 0 scl300 r/w r/w after reset 00h address ff6fh r/w ff6dh 00h csim31 <7> csie31 6 0 5 0 4 0 3 0 2 mode31 1 scl311 0 scl310 r/w ff6bh 00h csim32 <7> csie32 6 0 5 0 4 0 3 0 2 mode32 1 scl321 0 scl320
154 chapter 11 serial interfaces sio30 to sio32 user s manual u15104ej2v0ud caution set the port mode register (pm ) as follows in the 3-wire serial i/o mode. set the output latch to 0. serial type serial interface serial interface serial interface sio32 operation mode sio30 sio31 s32sel0 = 0 s32sel0 = 1 serial clock output pm72 = 0 pm76 = 0 pm122 = 0 pm125 = 0 (master transmission or (set p72/sck30 pin (set p76/sck31 pin (set p122/sck32 pin (set p125/sck321 reception) to output mode) to output mode) to output mode) pin to output mode) serial clock input pm72 = 1 pm76 = 1 pm122 = 1 pm125 = 1 (slave transmission or reception) (set p72/sck30 pin (set p76/sck31 pin (set p122/sck32 pin (set p125/sck321 to input mode) to input mode) to input mode) pin to input mode) in transmit or transmit/receive pm71 = 0 pm75 = 0 pm121 = 0 pm124 = 0 mode (set p71/so30 pin to (set p75/so31 pin to (set p121/so32 pin (set p124/so321 pin output mode) output mode) to output mode) to output mode) in receive mode pm70 = 1 pm74 = 1 pm120 = 1 pm123 = 1 (set p70/si30 pin to (set p74/si31 pin to (set p120/si32 pin to (set p123/si321 pin input mode) input mode) input mode) to input mode) (2) communication operation in the 3-wire serial i/o mode, data is transmitted or received in 8-bit units. data is transmitted or received in synchronization with the serial clock. the shift operation of serial i/o shift register 3n (sio3n) is performed at the falling edge of the serial clock (sck3n). the transmit data is retained in so3n latch and is output from the so3n pin. the receive data input to the si3n pin is latched to sio3n at the falling edge of the serial clock. when 8-bit data has been transferred, the operation of sio3n is automatically stopped, and an interrupt request flag (csiif3n) is set. figure 11-6. timing in 3-wire serial i/o mode sck3n si3n so3n csiif3n transfer starts at falling edge of sck3n transfer ends 12345678 di7 di6 di5 do7 do6 do5 di4 di3 di2 do4 do3 do2 di1 di0 do1 do0
155 chapter 11 serial interfaces sio30 to sio32 user s manual u15104ej2v0ud (3) starting transfer serial transfer is started by writing (or reading) the transfer data to serial i/o shift register 3n (sio3n) when the following conditions are satisfied. operation control bit of sio3n (bit 7 (csie3n) of serial operation mode register 3n (csim3n)) = 1 if the internal serial clock is stopped or sck3n is high level after transfer of 8-bit serial data transmit/receive mode transfer is started if sio3n is written when bit 7 (csie3n) of csim3n = 1, and bit 2 (mode3n) = 0 receive mode transfer is started if sio3n is read when bit 7 (csie3n) of csim3n = 1, and bit 2 (mode3n) = 1 caution serial transfer is not started even if 1 is written to csie3n after data is written to sio3n. on completion of transfer of the 8-bit data, serial transfer is automatically stopped, and an interrupt request flag (csiif3n) is set.
156 user? manual u15104ej2v0ud chapter 12 interrupt functions 12.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupts this type of interrupt is acknowledged unconditionally even if interrupts are disabled. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. it generates a standby release signal. one interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag register (pr). multiple interrupt servicing is possible if a high-priority interrupt is generated while a low-priority interrupt is being serviced. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (refer to table 12-1 ). a standby release signal is generated. maskable interrupts are provided for each product as follows. pd178053, 178054, 178f054 internal: 11, external: 5 (3) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even in an interrupt- disabled state. the software interrupt does not undergo interrupt priority control. 12.2 interrupt sources and configuration the pd178053, 178054, and 178f054 have a total of 17 sources (non-maskable interrupt, maskable interrupt, software interrupt) (refer to table 12-1 ). remark either a non-maskable interrupt or a maskable interrupt (internal) can be selected for the watchdog timer interrupt source (intwdt).
157 chapter 12 interrupt functions user? manual u15104ej2v0ud table 12-1. interrupt sources interrupt type default interrupt source internal/ vector basic priority note 1 external table configuration name trigger address type note 2 non-maskable intwdt overflow of watchdog timer internal 0004h (a) (when watchdog timer mode 1 is selected) maskable 0 intwdt overflow of watchdog timer (b) (when interval timer mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intky detection of key input of port 4 internal 0010h (b) 7 intcsi31 end of transfer by serial interface sio31 0012h 8 intbtm0 generation of basic timer match signal 0014h 9 intad3 end of conversion by a/d converter 0016h 10 intcsi32 end of transfer by serial interface sio32 0018h 11 intcsi30 end of transfer by serial interface sio30 001ah 12 inttm50 generation of match signal of 8-bit timer/ 001ch event counter 50 13 inttm51 generation of match signal of 8-bit timer/ 001eh event counter 51 14 inttm52 generation of match signal of 8-bit timer/ 0020h event counter 52 15 inttm53 generation of match signal of 8-bit timer 53 0022h software brk execution of brk instruction 003eh (d) notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or held pending according to their default priorities. the default priority 0 is the highest, and 15 is the lowest. 2. (a) to (d) under the heading basic configuration type correspond to (a) to (d) in figure 12-1.
158 chapter 12 interrupt functions user? manual u15104ej2v0ud figure 12-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (c) external maskable interrupt (b) internal maskable interrupt internal bus priority controller vector table address generator standby release signal interrupt request internal bus ie pr isp mk if interrupt request priority controller vector table address generator standby release signal internal bus ie pr isp mk if priority controller vector table address generator standby release signal interrupt request edge detector external interrupt mode register (egp, egn)
159 chapter 12 interrupt functions user s manual u15104ej2v0ud figure 12-1. basic configuration of interrupt function (2/2) (d) software interrupt remark if: interrupt request flag ie: interrupt enable flag isp: inservice priority flag mk: interrupt mask flag pr: priority specification flag internal bus priority controller vector table address generator interrupt request
160 chapter 12 interrupt functions user s manual u15104ej2v0ud 12.3 registers controlling interrupt functions the following six types of registers are used to control the interrupt functions. interrupt request flag register (if0l, if0h) interrupt mask flag register (mk0l, mk0h) priority specification flag register (pr0l, pr0h) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) program status word (psw) table 12-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. table 12-2. various flags corresponding to interrupt request sources interrupt source interrupt request flag interrupt mask flag priority specification flag register register register intwdt wdtif if0l wdtmk mk0l wdtpr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intky kyif kymk kypr intcsi31 csiif31 csimk31 csipr31 intbtm0 btmif0 if0h btmmk0 mk0h btmpr0 pr0h intad3 adif admk adpr intcsi32 csiif32 csimk32 csipr32 intcsi30 csiif30 csimk30 csipr30 inttm50 tmif50 tmmk50 tmpr50 inttm51 tmif51 tmmk51 tmpr51 inttm52 tmif52 tmmk52 tmpr52 inttm53 tmif53 tmmk53 tmpr53
161 chapter 12 interrupt functions user s manual u15104ej2v0ud (1) interrupt request flag registers (if0l, if0h) the interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l and if0h are set with a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register if0, use a 16-bit memory manipulation instruction for the setting. reset input clears these registers to 00h. figure 12-2. format of interrupt request flag registers (if0l, if0h) if interrupt request flag 0 no interrupt request signal 1 interrupt request signal is generated; interrupt request state cautions 1. wdtif flag is r/w enabled only when a watchdog timer is used as an interval timer. if a watchdog timer is used in watchdog timer mode 1, set wdtif flag to 0. 2. to operate the timers, serial interface, and a/d converter after the standby mode has been released, clear the interrupt request flag, because the interrupt request flag may be set by noise. 3. when an interrupt is acknowledged, the interrupt request flag is automatically cleared before entering the interrupt routine. csiif31 tmif53 kyif tmif52 pif4 tmif51 pif3 tmif50 pif2 csiif30 pif1 csiif32 pif0 adif wdtif btmif0 r/w r/w r/w <0> <1> <2> <3> <4> <5> <6> <7> <0> <1> <2> <3> <4> <5> <6> <7> after reset 00h 00h address ffe0h ffe1h symbol if0l if0h
162 chapter 12 interrupt functions user s manual u15104ej2v0ud (2) interrupt mask flag registers (mk0l, mk0h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing and to set standby clear enable/disable. mk0l and mk0h are set with a 1-bit or 8-bit memory manipulation instruction. if mk0l and mk0h are used as a 16-bit register mk0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 12-3. format of interrupt mask flag registers (mk0l, mk0h) mk interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled cautions 1. if the wdtmk flag is read when the watchdog timer is used in watchdog timer mode 1, mk0 value becomes undefined. 2. because port 0 functions alternately as the external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. csimk31 tmmk53 kymk tmmk52 pmk4 tmmk51 pmk3 tmmk50 pmk2 csimk30 pmk1 csimk32 pmk0 admk wdtmk btmmk0 mk0l mk0h r/w r/w r/w ffe4h ffe5h ffh ffh <0> <1> <2> <3> <4> <5> <6> <7> <0> <1> <2> <3> <4> <5> <6> <7> after reset address symbol
163 chapter 12 interrupt functions user s manual u15104ej2v0ud (3) priority specification flag registers (pr0l, pr0h) the priority specification flags are used to set the corresponding maskable interrupt priority orders. pr0l and pr0h are set with a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are used as a 16-bit register pr0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 12-4. format of priority specification flag registers (pr0l, pr0h) pr priority level selection 0 high priority level 1 low priority level caution when the watchdog timer is used in watchdog timer mode 1, set the wdtpr flag to 1. csipr31 tmpr53 kypr tmpr52 ppr4 tmpr51 ppr3 tmpr50 ppr2 csipr30 ppr1 csipr32 ppr0 adpr wdtpr btmpr0 pr0l pr0h r/w r/w r/w <0> <1> <2> <3> <4> <5> <6> <7> <0> <1> <2> <3> <4> <5> <6> <7> ffe8h ffe9h ffh ffh after reset address symbol
164 chapter 12 interrupt functions user s manual u15104ej2v0ud (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers set the valid edge for intp0 to intp4. egp and egn are set with a 1-bit or 8-bit memory manipulation instructions. reset input clears these registers to 00h. figure 12-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) egpn egnn intpn pin valid edge selection (n = 0 to 4) 0 0 interrupt prohibited 0 1 falling edge 1 0 rising edge 1 1 both falling and rising edges 7 0 7 0 6 0 6 0 5 0 5 0 4 egp4 4 egn4 3 egp3 3 egn3 2 egp2 2 egn2 1 egp1 1 egn1 0 egp0 0 egn0 egp egn r/w r/w r/w after reset 00h 00h address ff48h ff49h symbol
165 chapter 12 interrupt functions user s manual u15104ej2v0ud (5) program status word (psw) the program status word is a register that holds the instruction execution result and the current status for interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control multiple interrupt servicing are mapped. besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, if the brk instruction is executed, the contents of psw are automatically saved into a stack and the ie flag is reset to 0. when a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the isp flag. the acknowledged interrupt is also saved into the stack with the push psw instruction. it is restored from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 12-6. configuration of program status word (psw) 7 ie psw 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy 02h after reset isp 0 used when normal instruction is executed priority of interrupt currently being received high-priority interrupt servicing (low-priority interrupt disable) 1 interrupt request not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) ie interrupt request acknowledge enable/disable 0 disabled 1 enabled
166 chapter 12 interrupt functions user s manual u15104ej2v0ud 12.4 interrupt servicing operations 12.4.1 non-maskable interrupt request acknowledgement operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledgement disabled state. it does not undergo interrupt priority control and has the highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved to the stack, the program status word (psw) and the program counter (pc), in that order, the ie and isp flags are reset to 0, and the vector table contents are loaded into pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction is executed. if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program execution. figure 12-7 shows the flowchart from generation of the non-maskable interrupt request to acknowledging it. figure 12-8 shows the timing of acknowledging the non-maskable interrupt request, and figure 12-9 shows the operation performed if a more than one non-maskable interrupt request occurs.
167 chapter 12 interrupt functions user s manual u15104ej2v0ud figure 12-7. flowchart from generation of non-maskable interrupt request to acknowledgement wdtm: watchdog timer mode register wdt: watchdog timer figure 12-8. non-maskable interrupt request acknowledgement timing wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdtm3 = 0 (with non-maskable interrupt request selected)? interrupt request generation wdt interrupt servicing? interrupt control register unaccessed? interrupt servicing start interrupt request held pending reset processing interval timer start no yes yes no yes no yes no yes no instruction instruction cpu processing wdtif psw and pc save, jump to interrupt servicing interrupt servicing program
168 chapter 12 interrupt functions user s manual u15104ej2v0ud figure 12-9. non-maskable interrupt request acknowledgement operation (a) if a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request execution of one instruction nmi request nmi request is held pending. pending nmi request is serviced. nmi request nmi request held pending. only one nmi request is acknowledged even if two or more nmi requests are generated in duplicate. nmi request held pending. main routine execution of one instruction
169 chapter 12 interrupt functions user s manual u15104ej2v0ud 12.4.2 maskable interrupt request acknowledgement operation a maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (mk) flag of the interrupt request is cleared to 0. a vectored interrupt request is acknowledged in an interrupt enable state (with ie flag set to 1). however, a low-priority interrupt request is not acknowledged during high-priority interrupt servicing (with isp flag reset to 0). wait times from maskable interrupt request generation to interrupt request servicing are as follows. for the interrupt acknowledge timing, refer to figures 12-11 and 12-12 . table 12-3. times from maskable interrupt request generation to interrupt servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time is maximized. remark 1 clock: (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specification flag is acknowledged first. if two or more requests are specified as the same priority by the priority specification flag, the default priorities apply. any pending interrupt requests are acknowledged when they become acknowledgeable. figure 12-10 shows interrupt request acknowledgement algorithms. if a maskable interrupt request is acknowledged, the acknowledged interrupt request is saved to the stack, the program status word (psw) and the program counter (pc), in that order, the ie flag is reset to 0, and the acknowledged interrupt priority specification flag contents are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into the pc and branched. return from the interrupt is possible with the reti instruction. f cpu 1
170 chapter 12 interrupt functions user s manual u15104ej2v0ud figure 12-10. interrupt request acknowledgement processing algorithm if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag controlling acknowledging maskable interrupt request (1 = enable, 0 = disable) isp: flag indicating priority of interrupt currently being serviced (0 = interrupt with high priority serviced, 1 = interrupt request is not acknowledged, or interrupt with low priority serviced) start if = 1? mk = 0? pr = 0? any simultaneously generated pr = 0 interrupt requests? any simultaneously generated high-priority interrupt requests ? ie = 1? isp = 1? vectored interrupt servicing interrupt request pending interrupt request pending interrupt request pending interrupt request pending interrupt request pending interrupt request pending interrupt request pending vectored interrupt servicing any high- priority interrupt request among simultaneously generated pr = 0 interrupts? ie = 1? yes (high priority) yes no yes no no no yes (interrupt request generation) no yes no (low priority) yes yes no yes yes no no
171 chapter 12 interrupt functions user s manual u15104ej2v0ud figure 12-11. interrupt request acknowledgement timing (minimum time) 1 f cpu remark 1 clock: (f cpu : cpu clock) figure 12-12. interrupt request acknowledgement timing (maximum time) 1 f cpu remark 1 clock: (f cpu : cpu clock) instruction instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 8 clocks 7 clocks cpu processing if ( pr = 1) if ( pr = 0) instruction divide instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 33 clocks 32 clocks cpu processing if ( pr = 1) if ( pr = 0) 25 clocks
172 chapter 12 interrupt functions user s manual u15104ej2v0ud 12.4.3 software interrupt request acknowledgement operation a software interrupt request is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, it is saved to the stack, the program status word (psw) and program counter (pc), in that order, the ie flag is reset to 0 and the contents of the vector tables (003eh and 003fh) are loaded into the pc and branched. return from the software interrupt is possible with the retb instruction. caution do not use the reti instruction for returning from a software interrupt.
173 chapter 12 interrupt functions user s manual u15104ej2v0ud 12.4.4 multiple interrupt servicing the acknowledgement of another interrupt request while an interrupt is being serviced is called multiple interrupt servicing. multiple interrupt servicing does not take place unless the interrupts (except the non-maskable interrupt) are abled to be acknowledged (ie = 1). acknowledging another interrupt request is disabled (ie = 0) when one interrupt has been acknowledged. therefore, to enable multiple interrupt servicing, the ei flag must be set to 1 during interrupt servicing, to enable other interrupts. multiple interrupt servicing may not occur even when interrupts are enabled. this is controlled by the priorities of the interrupts. although two types of priorities, default priority and programmable priority, may be assigned to an interrupt, multiple interrupt servicing is controlled by using the programmable priority. if an interrupt with the same priority as or a higher priority than the interrupt currently being serviced occurs, that interrupt can be acknowledged and serviced. if an interrupt with a priority lower than that of the interrupt currently being serviced occurs, that interrupt cannot be acknowledged and serviced. an interrupt that is not acknowledged and serviced because it is disabled or it has a low priority is held pending. this interrupt is acknowledged after servicing of the current interrupt has been completed and one instruction of the main routine has been executed. multiple interrupt servicing is not enabled while a non-maskable interrupt is being serviced. table 12-4 shows the interrupts that can enter multiple interrupt servicing, and figure 12-13 shows an example of multiple interrupt servicing. table 12-4. interrupt request enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request pr = 0 pr = 1 ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt d d d d d maskable interrupt isp = 0 e e d d d isp = 1 e e d e d software interrupt servicing e e d e d remarks 1. e: multiple interrupt servicing enabled 2. d: multiple interrupt servicing disabled 3. isp and ie are the flags contained in psw isp = 0: an interrupt with higher priority is being serviced isp = 1: an interrupt request is not accepted or an interrupt with lower priority is being serviced ie = 0: interrupt request acknowledgement is disabled ie = 1: interrupt request acknowledgement is enabled 4. pr is a flag contained in pr0l and pr0r. pr = 0: higher priority level pr = 1: lower priority level interrupt being serviced multiple interrupt request non-maskable interrupt request
174 chapter 12 interrupt functions user s manual u15104ej2v0ud figure 12-13. multiple interrupt servicing example (1/2) example 1. example where multiple interrupt occurs two times example 2. example where multiple interrupt does not occur because of priority control two interrupt requests, intyy and intzz, are acknowledged while interrupt intxx is serviced, and multiple interrupt occurs. before each interrupt request is acknowledged, the ei instruction is always executed, and the interrupt is enabled. interrupt request intyy that is generated while interrupt intxx is being serviced is not acknowledged because its priority is lower than that of intxx, and therefore, multiple interrupt does not occur. intyy request is held pending, and is acknowledged after one instruction of the main routine has been executed. pr = 0: high-priority level pr = 1: low-priority level ie = 0: acknowledging interrupt request is disabled. main processing ei intxx (pr = 1) intyy (pr = 0) ie = 0 ei reti intxx service intzz (pr = 0) ie = 0 ei reti intyy service ie = 0 reti intzz service main processing intxx service intyy service intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 1) ei ie = 0 ei reti reti
175 chapter 12 interrupt functions user s manual u15104ej2v0ud figure 12-13. multiple interrupt servicing example (2/2) example 3. example where multiple interrupt does not occur because interrupts are not enabled because interrupts are not enabled (ei instruction is not issued) in interrupt servicing intxx, interrupt request intyy is not acknowledged, and multiple interrupt does not occur. the intyy request is held pending, and is acknowledged after one instruction of the main routine has been executed. pr = 0: high priority level ie = 0: acknowledging interrupts is disabled. main processing intxx service intyy service intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 0) ie = 0 reti reti ei
176 chapter 12 interrupt functions user s manual u15104ej2v0ud 12.4.5 pending interrupt requests even if an interrupt request is generated, the following instructions hold it pending. mov psw, #byte mov a, psw mov psw, a mov1 psw.bit, cy mov1/and1/or1/xor1 cy, psw.bit set1/clr1 psw.bit retb reti push psw pop psw bt/bf/btclr psw.bit, $addr16 ei di instructions manipulating if0l, if0h, mk0l, mk0h, pr0l, and pr0h registers caution because the ie flag is cleared to 0 by the software interrupt (caused by execution of the brk instruction), a maskable interrupt request is not acknowledged even if it occurs while the brk instruction is executed. however, a non-maskable interrupt is acknowledged. figure 12-14. pending interrupt request remarks 1. instruction n: instruction that holds interrupt request pending 2. instruction m: instruction that does not hold interrupt request pending 3. operation of if is not affected by value of pr. cpu processing if instruction n instruction m save psw and pc, jump to interrupt servicing interrupt servicing program
177 user? manual u15104ej2v0ud chapter 13 pll frequency synthesizer 13.1 function of pll frequency synthesizer the pll (phase locked loop) frequency synthesizer is used to lock the frequency in the mf (middle frequency), hf (high frequency), and vhf (very high frequency) ranges to a specific frequency by means of phase difference comparison. the pll frequency synthesizer divides the frequency of the signal input from the vcol or vcoh pin by using a programmable divider, and outputs the phase difference between the frequency of this signal and reference frequency from the eo0 and eo1 pin. the following input pin states and frequency division modes are used. (1) direct division (mf) mode the vcol pin is used. the vcoh pin is set in the status specified by bit 3 (vcohdmd) of the pll mode select register (pllmd). (2) pulse swallow (hf) mode the vcol pin is used. the vcoh pin is set in the status specified by bit 3 (vcohdmd) of pllmd. (3) pulse swallow (vhf) mode the vcoh pin is used. the vcol pin is set in the status specified by bit 2 (vcoldmd) of pllmd. (4) vcol and vcoh pin disable the vcol and vcoh pins are set in the status specified by bits 2 (vcoldmd) and 3 (vcohdmd) of pllmd. at this time, the phase comparator, reference frequency generator, and charge pump operate. (5) pll disable the pll disabled status is set by the pll reference mode register (pllrf). the vcoh and vcol pins are set in the status specified by bits 2 (vcoldmd) and 3 (vcohdmd) of pllmd. the eo0 and eo1 pins go into a high-impedance state. at this time, all the internal pll operations are stopped. these division modes are selected by using the pll mode select register (pllmd). the division value (n value) is set to the programmable divider by using the pll data register. frequency division in each of the above modes is carried out according to the value (n value) set to the programmable divider. table 13-1 shows the division modes, input pins used (vcol pin or vcoh pin), and the value that can be set to the programmable divider.
178 chapter 13 pll frequency synthesizer user? manual u15104ej2v0ud table 13-1. division mode, input pin, and division value division mode pin used value that can be set direct division (mf) vcol 32 to 2 12 ? pulse swallow (hf) vcol 1024 to 2 17 ? pulse swallow (vhf) vcoh 1024 to 2 17 ? caution for the frequencies that can be actually input, and input amplitude, refer to chapter 19 electrical specifications.
179 chapter 13 pll frequency synthesizer user? manual u15104ej2v0ud 13.2 configuration of pll frequency synthesizer the pll frequency synthesizer consists of the following hardware. table 13-2. configuration of pll frequency synthesizer item configuration data registers pll data register l (pllrl) pll data register h (pllrh) pll data register 0 (pllr0) control registers pll mode select register (pllmd) pll reference mode register (pllrf) pll unlock f/f judge register (pllul) pll data transfer register (pllns) figure 13-1. block diagram of pll frequency synthesizer note external circuit internal bus internal bus pll mode select register (pllmd) pll data transfer register (pllns) pll ns0 pll md0 pll md1 pll rf2 pll rf1 pll rf0 pll ul0 pll reference mode register (pllrf) pll unlock f/f judge register (pllul) pll rf3 2 input select block programmable divider phase comparator ( -det) unlock ff reference frequency generator 4.5 mhz 4 charge pump eo1 eo0 vcoh vcol mixer 2 f n f r pll data register (pllrl, pllrh, pllr0) voltage control generator lowpass filter note note vcol dmd vcoh dmd
180 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud (1) pll data register l (pllrl), pll data register h (pllrh), and pll data register 0 (pllr0) these registers set the division value of the pll frequency synthesizer. the division value of the pll frequency synthesizer is made up of 17 bits. the higher 16 bits of this value are set by pll data register l (pllrl) and pll data register h (pllrh). the higher 16 bits can also be set by the pll data register (pllr). the least significant bit is set by bit 7 (pllscn) of pll data register 0 (pllr0). reset input makes the contents of these registers undefined. these registers hold the current values in the stop and halt modes. (2) input select block the input select block consists of the vcol and vcoh pins, and input amplifiers of the respective pins. (3) programmable divider the programmable divider consists of two modulus prescalers, a programmable counter (12 bits), a swallow counter (5 bits), and a division mode select switch. (4) reference frequency generator the reference frequency generator consists of a divider that generates the reference frequency f r of the pll frequency synthesizer, and a multiplexer. (5) phase comparator the phase comparator ( -det) compares the phase of the divided frequency output f n of the programmable divider with that of the reference frequency output f r of the reference frequency generator, and outputs an up request signal (up) and down request signal (dw). (6) unlock f/f the unlock f/f detects the unlock status of the pll frequency synthesizer from the up request signal (up) and down request signal (dw) of the phase comparator ( -det). (7) charge pump the charge pump outputs the result of the output of the phase comparator from the error out pins (eo0 and eo1 pins).
181 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud 13.3 registers controlling pll frequency synthesizer the pll frequency synthesizer is controlled by the following four registers. pll mode select register (pllmd) pll reference mode register (pllrf) pll unlock f/f judge register (pllul) pll data transfer register (pllns) (1) pll mode select register (pllmd) this register selects the input pin and division mode of the pll frequency synthesizer. pllmd is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. in the stop mode, only bits 3 and 2 (vcohdmd and vcoldmd) retain the previous value. bits 1 and 0 (pllmd1 and pllmd0) are reset to 0. in the halt mode, it holds the value immediately before the halt mode was set. figure 13-2. format of pll mode select register (pllmd) vcoh selection of disable status of vcoh pin dmd 0 connected to pull-down resistor. 1 high-impedance state vcol selection of disable status of vcol pin dmd 0 connected to pull-down resistor. 1 high-impedance state pllmd1 pllmd0 selection of division mode of pll frequency synthesizer and vco input pin 0 0 disables vcol and vcoh pins note 0 1 direct division (vcol pin and mf mode) 1 0 pulse swallow (vcoh pin and vhf mode) 1 1 pulse swallow (vcol pin and hf mode) note this does not mean that the pll is disabled. the vcoh and vcol pins become the status specified by bit 3 (vcohdmd) and bit 2 (vcoldmd). the eo0 and eo1 pins go low. remark bits 4 to 7 are fixed to 0 by hardware. 7 0 6 0 5 0 4 0 <3> vcohdmd <2> vcoldmd pllmd1 pllmd0 symbol pllmd r/w r/w after reset 00h address ffa0h <1> <0>
182 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud (2) pll reference mode register (pllrf) this register selects the reference frequency f r of the pll frequency synthesizer and sets the disabled status of the pll frequency synthesizer. pllrf is set with 1-bit or 8-bit memory manipulation instruction. the value of this register is set to 0fh after reset and in the stop mode. in the halt mode, it holds the value immediately before the halt mode was set. figure 13-3. format of pll reference mode register (pllrf) pllrf3 pllrf2 pllrf1 pllrf0 setting of reference frequency f r of pll frequency synthesizer 000050 khz 000125 khz 0010 12.5 khz 00119 khz 01001 khz 01013 khz 011010 khz 0111 setting prohibited 1 pll disable note note when pll disable is selected, the status of the vcol, vcoh, eo0, and eo1 pins are as follows: vcoh, vcol pins: status specified by bit 3 (vcohdmd) and bit 2 (vcoldmd) of the pll mode select register (pllmd). eo0, eo1 pins: high-impedance state remark bits 4 to 7 are fixed to 0 by hardware. : don t care 7 0 6 0 5 0 4 0 pllrf3 pllrf2 pllrf1 pllrf0 symbol pllrf r/w r/w address ffa1h after reset 0fh <1> <0> <3> <2>
183 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud (3) pll unlock f/f judge register (pllul) this register detects whether the pll frequency synthesizer is in the unlock status. because this register is an r&reset register, it is reset to 0 after it has been read. reset input sets this register to 0 h note 1 . in the stop and halt modes, this register holds the value immediately before the stop or halt mode was set. figure 13-4. format of pll unlock f/f judge register (pllul) pllul0 detection of status of unlock f/f 0 unlock f/f = 0: pll lock status 1 unlock f/f = 1: pll unlock status notes 1. the value of bit 0 (pllul0) at reset differs depending on the type of reset that has been executed (refer to the table below). 2. bit 0 (pllul0) is r&reset. 76543210 after reset power-on clear 0000000 undefined watchdog timer retained reset input retained stop mode retained halt mode retained remark bits 1 to 7 are fixed to 0 by hardware. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 pllul0 symbol pllul r/w r note 2 after reset 0 h note 1 address ffa2h <0>
184 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud (4) pll data transfer register (pllns) this register transfers the values of the pll data registers (pllrl, pllrh, and pllr0) to the programmable counter and swallow counter. the value of this register is 00h after reset and in the stop mode. in the halt mode, this register holds the previous value immediately before the halt mode is set. figure 13-5. format of pll data transfer register (pllns) pllns0 transfers value of pll data register to programmable counter and swallow counter 0 does not transfer 1 transfers remark bits 1 to 7 are fixed to 0 by hardware. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 pllns0 symbol pllns r/w w after reset 00h address ffa3h <0>
185 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud 13.4 operation of pll frequency synthesizer 13.4.1 operation of each block of pll frequency synthesizer (1) operation of input select block and programmable divider the input select block and programmable divider select the input pin and division mode of the pll frequency synthesizer and divide the frequency in the selected division mode, according to the setting of the pll mode select register (pllmd). the programmable counter (12 bits) and pulse swallow counter (5 bits) are binary counters. the division value (n value) is set to the programmable counter (12 bits) and swallow counter (5 bits) by the pll data registers (pllrl, pllrh, and pllr0). when the n value has been transferred to the programmable counter and swallow counter, frequency division is performed in the selected division mode according to the status of bit 0 (pllns0) of the pll data transfer register. figure 13-6 shows the configuration of the input select block and programmable divider. figure 13-6. configuration of input select block and programmable divider (2) operation of reference frequency generator the reference frequency generator divides the 4.5 mhz output of the crystal oscillator and generates seven types of reference frequency f r for the pll frequency synthesizer. reference frequency f r is selected by the pll reference mode register (pllrf). figure 13-7 shows the configuration of the reference frequency generator. pll ns0 vcoh vhf amp amp hf mf vhf hf mf 12 bits internal bus pll data registers (pllrl, pllrh, pllr0) 5 bits f n two modulus prescalers (1/32, 1/33) programmable counter (12 bits) swallow counter (5 bits) vcol to -det pll data transfer register vcohdmd vcoldmd
186 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud figure 13-7. configuration of reference frequency generator (3) operation of phase comparator ( -det) figure 13-8 shows the configuration of the phase comparator ( -det), charge pump, and unlock f/f. the phase comparator ( -det) compares the phase of the divided frequency f n of the programmable divider with that of the reference frequency f r of the reference frequency generator, and outputs an up request signal, up, or a down request signal, dw. if the divided frequency f n is lower than the reference frequency f r , the up request signal is output. if f n is higher than f r , the down request signal is output. figure 13-9 shows the relation among reference frequency f r , divided frequency f n , up request signal up, and down request signal dw. when the pll is disabled, neither the up nor the down request signal is output. the up and down request signals are input to the charge pump and unlock f/f. figure 13-8. configuration of phase comparator, charge pump, and unlock f/f pllrf3 to pllrf0 4-16 decoder divider 4.5 mhz mux 1 khz 3 khz 9 khz 25 khz 50 khz pll disable signal f r to -det f n eo1 pllul unlock f/f charge pump eo0 pll disable signal f r up reference frequency generator programmable divider dw phase comparator ( -det)
187 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud figure 13-9. relationship between f r , f n , up, and dw (a) if f r advances f n in phase (4) operation of charge pump the charge pump outputs the result of the up request (up) or down request (dw) signal from the phase comparator ( -det) from the error out pins (eo0 and eo1 pins). table 13-3 shows the output signals. the eo0 and eo1 pins are of voltage-driven type pins. figure 13-10 shows the configuration of the error out pins. (d) if f n is lower than f r (c) if f n and f r are in phase (b) if f n advances f r in phase f r f n up dw f r f n up dw f r f n up dw f r f n up dw
188 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud table 13-3. error out output signal relationship between divided frequency error out output signal f n and reference frequency f r when f r > f n low level when f r < f n high level when f r = f n floating (high impedance) figure 13-10. configuration of error out output p-ch eo1 gndpll v dd pll v dd pll n-ch dw up gndpll p-ch eo0 n-ch
189 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud (5) operation of unlock f/f the unlock f/f detects the unlock status of the pll frequency synthesizer. the unlock status of the pll frequency synthesizer is detected from the up request signal up and down request signal dw of the phase comparator ( -det). because either of the up request or down request signal outputs a low level in the unlock status, the unlock status can be detected by using this low-level signal. the status of the unlock f/f is detected by bit 0 (pllul0) of the pll unlock f/f judge register (pllul). the unlock f/f is set at the cycle of reference frequency f r selected at that time. the pll unlock f/f judge register is reset when its contents have been read. to read the pllul, therefore, it must be read at a cycle longer than the cycle (1/f r ) of the reference frequency. 13.4.2 operation to set n value of pll frequency synthesizer the division value (n value) is set to the programmable counter (12 bits) and swallow counter (5 bits) by the pll data registers (pllrl, pllrh, and pllr0). when the n value has been transferred to the programmable counter and swallow counter by bit 0 (pllns0) of the pll data transfer register (pllns), frequency division is carried out in the selected division mode. examples of setting the n value in the respective division modes (mf, hf, and vhf) are shown below. (1) direct division mode (mf) (a) calculating division value n (value set to pll data register) n = f vcol f r where, f vcol : input frequency of v col pin f r : reference frequency (b) example of setting pll data register an example of setting the pll data register to receive broadcasting stations in the following mw band is shown below. receive frequency: 1422 khz (mw band) reference frequency: 9 khz intermediate frequency: 450 khz division value n is calculated as follows: n = f vcol = 1422 + 450 = 208 (decimal) f r 9 = 0d0h (hexadecimal)
190 chapter 13 pll frequency synthesizer user? manual u15104ej2v0ud data is set to the pll data registers (pllr and pllr0) as follows. after setting the above pll data registers (pllr and pllr0), data must be transferred to the programmable counter by setting bit 0 (pllns0) of the pll data transfer register (pllns). (2) pulse swallow mode (hf) (a) calculating division value n (value set to pll data register) n = f vcol f r where, f vcol : input frequency of v col pin f r : reference frequency (b) example of setting pll data register an example of setting the pll data register to receive broadcasting stations in the following sw band is shown below. receive frequency: 25.50 mhz (sw band) reference frequency: 10 khz intermediate frequency: 450 khz division value n is calculated as follows: n = f vcol = 25500 + 450 = 2595 (decimal) f r 10 = 0a23h (hexadecimal) pllr programmable counter value don t care fixed to 0 pllrl pllrh b7 b16 b6 b15 b5 b14 b4 b13 b3 b12 b2 b11 b1 b10 b0 b9 b7 b8 b6 b7 b5 b6 b4 b5 000 0d0 011010000 b3 b4 b2 b3 b1 b2 b0 b1 b7 b0 b6 b5 b4 b3 b2 b1 b0 pllr0 pllscn
191 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud because the least significant bit of the division value n must be set to bit 7 (pllscn) of pll data register 0 (pllr0), data must be set by shifting the result of the above calculation 1 bit to the right. data is set to the pll data registers (pllr and pllr0) as follows. after setting the above pll data registers (pllr and pllr0), data must be transferred to the programmable counter and swallow counter by setting bit 0 (pllns0) of the pll data transfer register (pllns). in this example, a value of half the n value is set to the high-order 16 bits of the pll data register (pllr) by shifting the n value resulting from calculation 1 bit to the right. if the n value is calculated as follows with the least significant bit of the n value in pllscn fixed to 0, the result of the calculation (n pllr ) can be set to the pll data register (pllr) as is. if the calculation result is set in this way, however, the input frequency (f vcol ) is 2 f r (reference frequency) of the set value n pllr . n pllr = f vcol 2f r pllr programmable counter value fixed to 0 pllrl pllrh b7 b16 b6 b15 b5 b14 b4 b13 b3 b12 b2 b11 b1 b10 b0 b9 b7 b8 b6 b7 b5 b6 b4 b5 000 05110 0511h 00101 00010 0001 b3 b4 b2 b3 b1 b2 b0 b1 b7 b0 b6 b5 b4 b3 b2 b1 b0 pllr0 pllscn value shifted 1 bit to right 000001010001 0001 0 0 shifted 1 bit to right a23h result of calculation (n value) 000010100010 0011 swallow counter value
192 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud (3) pulse swallow mode (vhf) (a) calculating division value n (value set to pll data register) n = f vcoh f r where, f vcoh : input frequency of vcoh pin f r : reference frequency (b) example of setting pll data register an example of setting the pll data register to receive broadcasting stations in the following fm band is shown below. receive frequency: 100.0 mhz (fm band) reference frequency: 50 khz intermediate frequency: +10.7 mhz division value n is calculated as follows: n = f vcoh = 100.0 + 10.7 = 2214 (decimal) f r 0.05 = 08a6h (hexadecimal) because the least significant bit of the division value n must be set to the pll data register 0 (pllr0), data must be set by shifting the value calculated by the above expression 1 bit to the right. data is set to the pll data registers (pllr and pllr0) as follows. pllr pllrl pllrh b7 b16 b6 b15 b5 b14 b4 b13 b3 b12 b2 b11 b1 b10 b0 b9 b7 b8 b6 b7 b5 b6 b4 b5 000 04530 0453h 00100 00110 0101 b3 b4 b2 b3 b1 b2 b0 b1 b7 b0 b6 b5 b4 b3 b2 b1 b0 pllr0 pllscn value shifted 1 bit to right 000001000101 0011 0 0 shifted 1 bit to right 8a6h result of calculation (n value) 000010001010 0110 programmable counter value fixed to 0 swallow counter value
193 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud after setting the above pll data registers (pllr and pllr0), data must be transferred to the programmable counter and swallow counter by setting bit 0 (pllns0) of the pll data transfer register (pllns). in this example, a value of half the n value is set to the higher 16 bits of the pll data register (pllr) by shifting the n value resulting from calculation 1 bit to the right. if the n value is calculated as follows with the least significant bit of the n value in pllscn fixed to 0, the result of the calculation (n pllr ) can be set to the pll data register (pllr) as is. if the calculation result is set in this way, however, the input frequency (f vcoh ) is 2 f r (reference frequency) of the set value n pllr . n pllr = f vcoh 2f r
194 chapter 13 pll frequency synthesizer user s manual u15104ej2v0ud 13.5 pll disable status the pll frequency synthesizer can be stopped (pll disabled status) by performing any of the following settings while the pll frequency synthesizer is operating. setting value of bit 3 (pllrf3) of the pll reference mode register (pllrf) to 1 to set pll disabled status setting stop mode with the stop instruction setting reset status with the reset function the following table shows the operation of each block and the status of each register in the pll disabled status. table 13-4. operation of each block and register status in pll disabled status block/register status in pll disabled status vcol and vcoh pins status set in bit 3 (vcohdmd) and bit 2 (vcoldmd) of pllmd programmable divider division stops reference frequency generator output stops phase comparator output stops eo0 and eo1 pin high impedance pll mode select register retains value on execution of write instruction pll data register pll unlock f/f judge register 13.6 notes on pll frequency synthesizer notes on using pll frequency synthesizer because the input pins (vcol and vcoh pins) of the pll frequency synthesizer are provided with an ac amplifier, cut the dc component of the input signal by connecting a capacitor to the input pins in series. the potential of the selected input pin is intermediate (about 1/2v dd ). the input pin not selected becomes the status set in bit 3 (vcohdmd) and bit 2 (vcoldmd) of the pll mode select register (pllmd). for the frequencies that can be actually input and input amplitude, refer to chapter 19 electrical specifications .
195 user? manual u15104ej2v0ud chapter 14 frequency counter 14.1 function of frequency counter the frequency counter counts the intermediate frequency (if) of a tuner. the intermediate frequency input to the fmifc or amifc pin is counted for a specific time (1 ms, 4 ms, 8 ms, or open) by a 16-bit counter. the count value of the frequency counter is stored in the if counter register. for the range of the frequency that can be input to the fmifc and amifc pins, refer to chapter 19 electrical specifications . 14.2 configuration of frequency counter the frequency counter consists of the following hardware. table 14-1. configuration of frequency counter item configuration counter register if counter register (ifcr) control registers if counter mode select register (ifcmd) if counter control register (ifcr) if counter gate judge register (ifcjg)
196 chapter 14 frequency counter user? manual u15104ej2v0ud figure 14-1. block diagram of frequency counter (1) if counter input select block the if counter input select block selects the pin to be used from the fmifc and amifc pins, and a count mode. (2) gate time control block the gate time control block sets a gate time (count time). (3) start/stop control block the start/stop control block starts counting by the if counter register and detects the end of counting. (4) if counter register block the if counter register block is a 16-bit register that counts up the frequency input in the set gate time. the count value is stored to the if counter register (ifcr). when the count value reaches ffffh, the if counter register holds ffffh at the next input, and stops counting. the value of this register is reset to 0000h after reset or in the stop mode. in the halt mode, it holds the current count value. internal bus ifc md0 ifc ck1 ifc ck0 ifc jg0 if counter mode select register (ifcmd) if counter gate judge register (ifcjg) if counter control register (ifccr) ifc md1 ifc res ifc st input select block start/stop control block gate time control block if counter register (ifcr) block 2 2 fmifc amifc
197 chapter 14 frequency counter user s manual u15104ej2v0ud 14.3 registers controlling frequency counter the frequency counter is controlled by the following three registers. if counter mode select register (ifcmd) if counter control register (ifccr) if counter gate judge register (ifcjg) (1) if counter mode select register (ifcmd) this register selects the input pin of the frequency counter, and selects a mode and gate time (count time). this register is set with a 1-bit or 8-bit memory manipulation instruction. the value of this register is reset to 00h after reset or in the stop mode. in the halt mode, this register holds the value immediately before the halt mode is set. figure 14-2. format of if counter mode select register (ifcmd) ifcmd1 ifcmd0 selection of frequency counter pin and mode 0 0 disables fmifc, amifc pins note 0 1 amifc pin, amif count mode 1 0 fmifc pin, fmif count mode 1 1 fmifc pin, amif count mode ifcck1 ifcck0 selection of gate time 0 0 1 ms 0 1 4 ms 1 0 8 ms 1 1 open note the fmifc and amfic pins are in a high-impedance state. remark bits 4 to 7 are fixed to 0 by hardware. 7 0 6 0 5 0 4 0 ifcmd1 ifcmd0 ifcck1 ifcck0 symbol ifcmd r/w r/w after reset 00h address ffa9h <0> <1> <2> <3>
198 chapter 14 frequency counter user s manual u15104ej2v0ud (2) if counter control register (ifccr) this register starts counting by the if counter register and clears the if counter register. ifccr is set with a 1-bit or 8-bit memory manipulation instruction. the value of this register is reset to 00h after reset and in the stop mode. in the halt mode, this register holds the value immediately before the halt mode is set. figure 14-3. format of if counter control register (ifccr) ifcst setting of if counter register start 0 nothing is affected 1 starts counting ifcres setting of data clear of if counter register 0 nothing is affected 1 clears data of if counter register remark bits 2 to 7 are fixed to 0 by hardware. (3) if counter gate judge register (ifcjg) this register detects opening/closing of the gate of the frequency counter. the value of this register is reset to 00h after reset and in the stop mode. in the halt mode, this register holds the value immediately before the halt mode is set. figure 14-4. format of if counter gate judge register (ifcjg) ifcjg0 detection of opening/closing of frequency counter gate 0 gate is closed 1 if gate time is set to other than open status until gate is closed after ifcst has been set to 1 if gate time is set to open status where gate is open as soon as it has been set to be opened remark bits 1 to 7 are fixed to 0 by hardware. caution ifcjg0 remains set even if the if counter register overflows and stops counting, until the set gate time expires. 7 0 6 0 5 0 4 0 3 0 2 0 ifcst ifcres symbol ifccr r/w w after reset 00h address ffach <0> <1> 7 0 6 0 5 0 4 0 3 0 2 0 1 0 ifcjg0 symbol ifcjg r/w r after reset 00h address ffabh <0>
199 chapter 14 frequency counter user? manual u15104ej2v0ud 14.4 operation of frequency counter <1> select an input pin, mode, and gate time using the if counter mode select register (ifcmd). figure 14-5 shows a block diagram of input pin and mode selection. <2> set bit 0 (ifcres) of the if counter control register (ifccr) to 1, and clear the data of the if counter register. <3> set bit 1 (ifcst) of the if counter control register (ifccr) to 1. <4> the gate is opened only for the set gate time since a 1 khz internal signal has risen after ifcst was set. if the gate time is set to be opened, the gate is opened as soon as it has been specified to be opened. bit 0 (ifcjg0) of the if counter gate judge register (ifcjg) is automatically set to 1 as soon as ifcst has been set to 1. when the gate time has elapsed, bit 0 (ifcjg0) of the if counter gate judge register (ifcjg) is automatically cleared to 0. if it is specified that the gate be open, however, ifcjg0 is not automatically cleared. in this case, set a gate time. figure 14-6 shows the gate timing of the frequency counter. <5> while the gate opens the frequency input to the selected fmifc or amifc pin, the if counter register counts the frequency. if the fmifc pin is used in the fmif count mode, however, the input frequency is divided by half before it is counted. the relationship between the count value x (decimal), the input frequencies (f fmifc and f amifc ), and the gate time (t gate ) is shown below. fmif count mode (fmifc pin) f fmifc = x 2 (khz) t gate amif count mode (fmifc or amifc pin) f amifc = x (khz) t gate figure 14-5. block diagram of input pin and mode selection if counter register amp 1/2 amp amp fmifc amifc fmif count mode amif count mode amif count mode
200 chapter 14 frequency counter user s manual u15104ej2v0ud figure 14-6. gate timing of frequency counter (a) if gate time is set to 1, 4, or 8 ms (b) if gate is set to be open caution if counting is started by using ifcst while this gate is open, the gate is closed after an undefined time. to open the gate, therefore, do not set ifcst to 1. remark ifcst: bit 1 of if counter control register (ifccr) ifcjg0: bit 0 of if counter gate judge register (ifcjg) ifcck1, 0: bits 1 and 0 of if counter mode select register (ifcmd) h l internal 1 khz ifcjg0 sets ifcst. ifcjg0 is automatically set at this point. counting starts. gate is opened at this point. clears ifcjg0 counting ends if gate time is 8 ms. gate time: 8 ms gate time: 1 ms gate time: 1 ms counting ends if gate time is 1 ms. counting ends if gate time is 4 ms. 1 ms 4 ms 8 ms open close open close open close gate time count period. if ifcst is set during this period, gate is closed after undefined time. h l internal 1 khz gate gate ifcck1 = ifcck0 = 1. gate is opened at this point. if gate is opened when ifcjg0 is opened, gate is closed after undefined time. ifcck1 = ifcck0 = 1 sets gate time by using ifcck1 and ifcck0 count period open close open close
201 chapter 14 frequency counter user s manual u15104ej2v0ud 14.5 notes on frequency counter (1) notes on using frequency counter because signals are input to the frequency counter from an input pin (fmifc or amifc pin) with an ac amplifier as shown in figure 14-7, cut the dc component of the input signals by using capacitor c. if the fmifc or amifc pin is selected by the if counter mode select register, switch sw1 turns on, and switch sw2 turns off. as a result, the voltage on the pin is about 1/2v dd . unless the voltage has risen to a sufficient intermediate level at this time, counting may not be performed normally because the ac amplifier is not in the normal operating range. therefore, make sure that sufficient wait time elapses after a pin has been selected and before counting is started (ifcst = 1). figure 14-7. frequency counter input pin circuit (2) notes in halt mode the fmifc and amifc pins hold the status immediately before the halt status was set. to release the halt mode by using the interrupt of the frequency counter at this time, the following point must be noted. the gate will not be opened if the halt instruction is executed after counting has been started by ifcst before the gate is actually opened. therefore, wait for at least 1 ms before executing the halt instruction. figure 14-8. gate status when halt instruction is executed open close 1 ms max. timing to open gate sets ifcst interrupt request is not issued if halt instruction is executed during this period because gate is not opened. gate sw1 sw2 to internal counter v dd pll r c external frequency fmifc or amifc pin
202 chapter 14 frequency counter user s manual u15104ej2v0ud (3) error of frequency counter the error of the frequency counter includes an error of gate time and a count error. (1) error of gate time the gate time of the frequency counter is created by dividing 4.5 mhz. therefore, if 4.5 mhz is shifted +x ppm, the gate time is also shifted x ppm. (2) count error the frequency counter counts the frequency at the rising edge of the input signal. if a high level is input to the pin when the gate is opened, therefore, one excess pulse is counted. when the gate is closed, however, counting is not affected by the status of the pin. therefore, the count error is maximum + 1 .
203 user? manual u15104ej2v0ud chapter 15 standby function 15.1 standby function and configuration 15.1.1 standby function the standby function is designed to decrease power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. system clock oscillator continues oscillation. in this mode, current consumption cannot be decreased as in the stop mode. the halt mode is valid to restart immediately upon interrupt request and to carry out intermittent operations such as in watch applications. although the cpu stops operating, the peripheral functions can operate. to lower the current consumption, therefore, stop all unnecessary circuits before executing the halt instruction. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the system clock oscillator stops and the whole system stops. cpu current consumption can be considerably decreased. data memory low-voltage hold (down to v dd = 2.2 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. if the supply voltage drops below 2.2 v, the system is reset by means of power-on clear reset. for reset, refer to chapter 16 reset function . because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is necessary to secure an oscillation stabilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. all the functions stop operating. some registers of the pll frequency synthesizer and frequency counter are reset, but the other functions are stopped with their current status retained. cautions 1. when shifting to the stop mode, be sure to stop the peripheral hardware operation before executing the stop instruction. 2. the following sequence is recommended for power consumption reduction of the a/d converter: first clear bit 7 (adcs3) of adm3 to 0 to stop the a/d conversion operation, then execute the halt or stop instruction.
204 chapter 15 standby function user? manual u15104ej2v0ud 15.1.2 register controlling standby function a wait time after the stop mode is released upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time select register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. figure 15-1. format of oscillation stabilization time select register (osts) remark f x : system clock oscillation frequency ( ): f x = 4.5 mhz caution the wait time when the stop mode is released does not include the time required for the clock oscillation to start after the stop mode has been released (see ??in the figure below), regardless of whether the mode has been released by the reset signal or an interrupt request. address fffah 04h after reset r/w r/w 0 0 0 0 1 selection of oscillation stabilization time when stop mode is released 2 12 /f x osts2 7 0 symbol osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 0 0 1 1 0 other than above osts1 0 1 0 1 0 osts0 setting prohibited 2 14 /f x 2 15 /f x 2 16 /f x 2 17 /f x (910 s) (3.64 ms) (7.28 ms) (14.6 ms) (29.1 ms) stop mode release x1 pin voltage waveform a
205 chapter 15 standby function user s manual u15104ej2v0ud 15.2 operations of standby function 15.2.1 halt mode (1) halt mode set and operating status the halt mode is set by executing the halt instruction. the operating status in the halt mode is described below. table 15-1. halt mode operating status item status clock generator can oscillate system clock. stops clock supply to cpu. cpu stops operating. port holds status before halt mode is set. 8-bit timer/event counter holds operation before halt mode is set and can operate. basic timer watchdog timer buzzer output controller a/d converter retains operation performed when halt mode is set. however, comparison cannot be performed correctly in a/d conversion operation mode. in power-fail comparison mode, operation is as follows depending on setting of bit 5 (pfhrm3) of power-fail comparison mode register 3 (pfm3): pfhrm3 = 0: comparison cannot be performed normally. pfhrm3: power-fail comparison operation can be performed. serial interface retains operation performed when halt mode is set and can operate. (sio30 to sio32) external interrupt hold operation before halt mode is set and can operate. pll frequency synthesizer frequency counter retains operation performed before halt mode is set. however, operation is not performed correctly though it is continued. power-on clear circuit reset when voltage of less than 3.5 v is detected.
206 chapter 15 standby function user s manual u15104ej2v0ud (2) halt mode release the halt mode can be released by the following three types of sources. (a) release upon unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. if disabled, the next address instruction is executed. figure 15-2. halt mode release upon interrupt generation remarks 1. the broken lines indicate the case when the interrupt request that released the standby status is acknowledged. 2. wait time will be as follows: when vectored interrupt servicing is carried out: 8 to 9 clocks when vectored interrupt servicing is not carried out: 2 to 3 clocks (b) release upon non-maskable interrupt request when a non-maskable interrupt is generated, the halt mode is released and vectored interrupt servicing is carried out whether interrupt acknowledgement is enabled or disabled. halt instruction wait standby release signal operation mode clock halt mode wait oscillation operation mode interrupt request
207 chapter 15 standby function user? manual u15104ej2v0ud (c) release by reset input if the reset signal is input, the halt mode is released. as is the case with normal reset operation, the program is executed after branch to the reset vector address. figure 15-3. halt mode release by reset input remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz table 15-2. operation after halt mode release release source mk pr ie isp operation maskable interrupt 0 0 0 next address instruction execution request 001 interrupt servicing execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt servicing execution 1 halt mode hold non-maskable interrupt interrupt servicing execution request reset input reset processing remark : don? care halt instruction reset signal operation mode clock reset period halt mode oscillation oscillation stop oscillation stabilization wait status operation mode oscillation wait (2 17 /f x : 29.1 ms)
208 chapter 15 standby function user s manual u15104ej2v0ud 15.2.2 stop mode (1) stop mode set and operating status the stop mode is set by executing the stop instruction. cautions 1. when the stop mode is set, the x1 pin is pulled down to gnd, and the x2 pin is internally pulled up to v dd to minimize the leakage current at the crystal oscillator block. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately released if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait set using the oscillation stabilization time select register (osts), the operation mode is set. the operating status in the stop mode is described below. table 15-3. stop mode operating status item status clock generator can oscillate system clock. stops clock supply to cpu. cpu stops operating. port holds status before halt mode is set. 8-bit timer/event counter operation stops and cannot operate. basic timer watchdog timer buzzer output controller a/d converter serial interface (sio30 to sio32) external interrupt can operate. pll frequency synthesizer operation stops and cannot operate. frequency counter power-on clear circuit reset generated when detecting 2.2 v or less.
209 chapter 15 standby function user s manual u15104ej2v0ud remark the broken lines indicate the case when the interrupt request that released the standby status is acknowledged. (2) stop mode release the stop mode can be released by the following two types of sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. if interrupt request acknowledgement is enabled after the lapse of oscillation stabilization time, vectored interrupt servicing is carried out. if interrupt request acknowledgement is disabled, the next address instruction is executed. figure 15-4. stop mode release by interrupt request generation stop instruction wait (time set by osts) oscillation stabilization wait status operation mode oscillation operation mode stop mode oscillation stop oscillation standby release signal clock interrupt request
210 chapter 15 standby function user s manual u15104ej2v0ud (b) release by reset input if the reset signal is input, the stop mode is released, and after the lapse of oscillation stabilization time, a reset operation is carried out. figure 15-5. release by stop mode reset input remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 4.5 mhz table 15-4. operation after stop mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt servicing execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt servicing execution 1 stop mode hold reset input reset processing remark : don t care reset signal operating mode clock reset period stop mode oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 29.1 ms) stop instruction oscillation
211 user? manual u15104ej2v0ud chapter 16 reset function 16.1 reset function the following three operations are available to generate the reset signal. (1) external reset input via a reset pin (2) internal reset by inadvertent program loop time detection watchdog timer (3) internal reset by power-on clear (poc) (1) external reset input by reset pin when a low level is input to the reset pin, the device is reset, and each hardware unit enters the status shown in table 16-1. while the reset signal is input and during the oscillation stabilization time immediately after the reset signal has been deasserted, each pin goes into a high-impedance state (however, the p130 to p132 pins become low level, and the vcoh and vcol pins are pulled down). the reset signal is deasserted when a high level is input to the reset pin, and the program execution is started after the oscillation stabilization time (2 17 /f x ) has elapsed. (2) internal reset by inadvertent program loop time detection of watchdog timer reset is effected and each hardware unit enters the status shown in table 16-1 when the watchdog timer overflow. while reset is in effect and during the oscillation stabilization time immediately after the effect of reset has been cleared, each pin goes into a high-impedance state (however, the p130 to p132 pins become low level, and the vcoh and vcol pins are pulled down). reset by the watchdog timer is cleared immediately after reset has been effected, and the program execution is started after the oscillation stabilization time (2 17 /f x ) has elapsed. (3) internal reset by power-on clear (poc) reset is effected by means of power-on clear under the following conditions: if supply voltage is less than 3.5 v note on power application if supply voltage drops to less than 2.2 v note in stop mode if supply voltage drops to less than 3.5 v note (including halt mode) when these reset conditions of power-on clear are satisfied, reset is effected, and each hardware unit enters the status shown in table 16-1. while the reset signal is input and during the oscillation stabilization time immediately after the reset signal has been deasserted, each pin goes into a high-impedance state (the p130 to p132 pins become low level, however). reset by power-on clear is cleared if the supply voltage rises beyond a specific level, and the program execution is started after the oscillation stabilization time (2 17 /f x ) has elapsed. note these voltage values are maximum values. actually, reset is effected at a voltage lower than these.
212 chapter 16 reset function user? manual u15104ej2v0ud cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, system clock oscillation remains stopped. 3. when the stop mode is released by reset input, the stop mode register contents are held during reset input. however, the i/o port pin becomes high-impedance. output dedicated port pin (p130 to p132) becomes low level regardless of the previous status. figure 16-1. reset function block diagram reset count clock reset controller watchdog timer stop over- flow reset signal interrupt function power-on clear circuit at stop
213 chapter 16 reset function user s manual u15104ej2v0ud figure 16-2. timing of reset by reset input (a) in normal operation mode (b) in stop mode reset internal reset signal i/o port pin delay delay high impedance x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) output port pin (p130 to p132) reset internal reset signal i/o port pin delay delay high impedance x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) stop status (oscillation stop) stop instruction execution output port pin (p130 to p132)
214 chapter 16 reset function user s manual u15104ej2v0ud figure 16-3. timing of reset due to watchdog timer overflow x1 normal operation watchdog timer overflow internal reset signal i/o port pin reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) high impedance output port pin (p130 to p132)
215 chapter 16 reset function user s manual u15104ej2v0ud figure 16-4. timing of reset by power-on clear (a) at power application (b) in stop mode (c) in normal operating mode (including halt mode) high impedance i/o port pin reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 v dd internal reset signal power-on clear voltage (3.5 v) output port pin (p130 to p132) 4.5 v 3.5 v 2.2 v l high impedance normal operation i/o port pin reset period (oscillation stop) stop status (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 v dd internal reset signal power-on clear voltage (2.2 v) output port pin (p130 to p132) 4.5 v 3.5 v 2.2 v stop instruction execution i/o port pin x1 v dd power-on clear voltage (3.5 v) output port pin (p130 to p132) 4.5 v 3.5 v 2.2 v reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) internal reset signal high impedance normal operation
216 chapter 16 reset function user s manual u15104ej2v0ud table 16-1. hardware status after reset (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) undefined ram data memory undefined note 2 general-purpose register undefined note 2 port (output latch) ports 0, 1, 3 to 7, 12, 13 (p0, p1, p3 to p7, p12, p13) 00h port mode registers (pm0, pm3 to pm7, pm12) ffh pull-up resistor option register 4 (pu4) 00h processor clock control register (pcc) 04h oscillation stabilization time select register (osts) 04h dts system clock select register (dtsck) 00h note 3 memory size switching register (ims) cfh note 4 internal expansion ram size switching register (ixs) 0ch note 5 8-bit timer/event counter counters 50 to 53 (tm50 to tm53) 00h compare registers 50 to 53 (cr50 to cr53) undefined clock select registers 50 to 53 (tcl50 to tcl53) 00h mode control registers 50 to 53 (tmc50 to tmc53) 00h watchdog timer clock select register (wdcs) 00h mode register (wdtm) 00h buzzer output controller beep clock select register 0 (beepcl0) 00h clock output select register (cks) 00h serial interface shift registers 30 to 32 (sio30 to sio32) undefined operating mode registers 30 to 32 (csim30 to csim32) 00h port select register 32 (sio32sel) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. the status before reset is retained even after reset in the standby mode. 3. though the initial value is 00h, be sure to set it to 01h before use. 4. the initial value is cfh. set the following value to this register depending on the model: pd178053: c6h pd178054: c8h pd178f054: value corresponding to mask rom versions 5. do not assign a value other than 0ch.
217 chapter 16 reset function user s manual u15104ej2v0ud table 16-1. hardware status after reset (2/2) hardware status after reset a/d converter mode register 3 (adm3) 00h a/d conversion result register 3 (adcr3) undefined analog input channel specification register 3 (ads3) 00h power-fail comparison mode register 3 (pfm3) 00h power-fail comparison threshold value register 3 (pft3) 00h interrupt request flag registers (if0l and if0h) 00h mask flag registers (mk0l and mk0h) ffh priority specification flag registers (pr0l and pr0h) ffh external interrupt rising edge enable register (egp) 00h external interrupt falling edge enable register (egn) 00h pll frequency synthesizer pll mode select register (pllmd) 00h pll reference mode register (pllrf) 0fh pll unlock f/f judge register (pllul) retained note 1 pll data registers (pllrh, pllrl, and pllr0) undefined pll data transfer register (pllns) 00h frequency counter if counter mode select register (ifcmd) 00h if counter gate judge register (ifcjg) 00h if counter control register (ifccr) 00h if counter register (ifcr) 0000h power-on clear poc status register (pocs) retained note 2 notes 1. undefined only at power-on clear reset 2. 03h only at power-on clear reset
218 chapter 16 reset function user s manual u15104ej2v0ud 7 0 6 0 5 0 4 0 3 0 2 0 1 vm45 pocm symbol pocs after reset retained note r/w r&reset address ff1bh 0 16.2 power failure detection function if reset is effected by means of power-on clear, bit 0 (pocm) of the poc status register (pocs) is set to 1. if reset is effected by the reset pin or the watchdog timer, however, pocm holds the previous status. a power failure status can be detected by detecting this pocm after reset by power-on clear has been cleared (after program execution has been started from address 0000h). figure 16-5. format of poc status register (pocs) pocm detection of power-on clear occurrence status 0 power-on clear does not occur 1 note reset is effected by power-on clear note the value of this register is set to 03h only when reset is effected through power-on clearing. it is not reset by the reset pin or watchdog timer. remark the values of the special function registers, other than pocs and pllul, at power-on clear are the same as the values following a reset by the reset pin or watchdog timer (see table 16-1 ).
219 chapter 16 reset function user s manual u15104ej2v0ud 7 0 6 0 5 0 4 0 3 0 2 0 1 vm45 0 pocm symbol pocs after reset retained note r/w r&reset address ff1bh 16.3 4.5 v voltage detection function this function is used to detect a voltage drop on the v dd pin below 4.5 v (4.5 v 0.3 v). if the voltage on the v dd pin drops below 4.5 v (4.5 v 0.3 v), bit 1 (vm45) of the poc status register (pocs) is set. note, however, that this 4.5 v voltage detection function does not cause internal reset. figure 16-6. format of poc status register (pocs) vm45 detection of voltage level of v dd pin 0 does not detect if v dd pin is less than 4.5 v (4.3 v 0.3 v) 1 detects if v dd pin is less than 4.5 v (4.3 v 0.3 v) note the value of this register is set to 03h only at power-on clear reset, and is not reset by the reset pin and watchdog timer. remark the values of the special function registers, other than pocs and pllul, at power-on clear are the same as the values following a reset by the reset pin or watchdog timer (see table 16-1 ).
220 user? manual u15104ej2v0ud chapter 17 pd178f054 the pd178f054 is provided with a flash memory to/from which data can be rewritten/erased with the device mounted on the printed circuit board. the differences between the flash memory ( pd178f054) and mask rom versions ( pd178053 and 178054) are shown in table 17-1. table 17-1. differences between pd178f054 and mask rom versions item pd178f054 pd178053, 178054 internal memory rom structure flash memory mask rom rom capacity 32 kb pd178053: 24 kb pd178054: 32 kb internal rom capacity selected by memory equivalent to mask rom version pd178053: c6h size switching register (ims) pd178054: c8h ic pin not provided provided v pp pin provided not provided electrical specifications refer to chapter 19 electrical specifications .
221 chapter 17 pd178f054 user? manual u15104ej2v0ud 17.1 memory size switching register (ims) the internal memory capacity of the pd178f054 can be changed using the memory size switching register (ims). by using this register, the memory of the pd178f054 can be mapped in the same manner as a mask rom version with a different internal memory capacity. ims is set with an 8-bit memory manipulation instruction. reset input sets this register to cfh. be sure to set ims to c6h or c8h. figure 17-1. format of memory size switching register (ims) ram2 ram1 ram0 selection of internal high-speed ram capacity 0 1 0 512 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 selection of internal rom capacity 011024 kb 100032 kb other than above setting prohibited table 17-2 shows the setting of ims to perform the same memory mapping as that of a mask rom version. table 17-2. set value of memory size switching register targeted model set value of ims pd178053 c6h pd178054 c8h 7 ram2 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 symbol ims after reset cfh r/w r/w address fff0h
222 chapter 17 pd178f054 user s manual u15104ej2v0ud 17.2 internal expansion ram size switching register (ixs) the internal expansion ram capacity of the pd178f054 can be changed using the internal expansion ram size switching register (ixs). by using this register, the memory of the pd178f054 can be mapped in the same manner as a mask rom version with a different internal expansion ram capacity. ixs is set with an 8-bit memory manipulation instruction. reset input sets this register to 0ch. caution do not set a value other than the initial value. figure 17-2. format of internal expansion ram size switching register (ixs) ixram4 ixram3 ixram2 ixram1 ixram0 selection of internal expansion ram capacity 011000 bytes other than above setting prohibited table 17-3 shows the setting of ixs to perform the same memory mapping as that of a mask rom version. table 17-3. set value of internal expansion ram size switching register targeted model set value of ixs pd178053, 178054 0ch 7 0 6 0 5 0 4 ixram4 3 i xram3 2 i xram2 1 i xram1 0 i xram0 symbol ixs after reset 0ch r/w r/w address fff4h
223 chapter 17 pd178f054 user s manual u15104ej2v0ud 17.3 flash memory programming the program memory provided in the pd178f054 is flash memory. the flash memory can be written on-board, i.e., with the pd178f054 mounted on the target system. to do so, connect a dedicated flash programmer (flashpro iii (part number: fl-pr3, pg-fp3)) to the host machine and target system. remark fl-pr3 and pg-fp3 are products of naito densei machida mfg. co., ltd. 17.3.1 selecting communication mode the flash memory is written by using flashpro iii and by means of serial communication. select a communication mode from those listed in table 17-4. to select a communication mode, the format shown in figure 17-3 is used. each communication mode is selected depending on the number of v pp pulses shown in table 17-4. table 17-4. communication modes communication mode pins used number of v pp pulses 3-wire serial i/o (sio3) si30/p70 0 so30/p71 sck30/p72 si31/p74 1 so31/p75 sck31/p76 si32/p120 2 so32/p121 sck32/p122 caution be sure to select a communication mode by the number of v pp pulses shown in table 17-4. figure 17-3. format of communication mode selection 12 n 10 v v dd gnd v pp v dd gnd reset
224 chapter 17 pd178f054 user s manual u15104ej2v0ud 17.3.2 flash memory programming function an operation such as writing the flash memory is performed when a command or data is transmitted/received in the selected communication mode. the major flash memory programming functions are listed in table 17-5. table 17-5. major functions of flash memory programming function description batch erase erases all memory contents. batch blank check checks erased status of entire memory. data write writes data to flash memory starting from write start address and based on number of data (bytes) to be written). batch verify compares all contents of memory with input data. 17.3.3 connecting flashpro iii the connection between flashpro iii and the pd178f054 is shown in figure 17-4. figure 17-4. connection of flashpro iii in 3-wire serial i/o mode note n = 1, 2 flashpro iii pd178f054 v pp n note v dd reset sck so si gnd v pp v dd v dd port reset sck30, sck31, sck32 si30, si31, si32 so30, so31, so32 gnd gndport
225 chapter 17 pd178f054 user s manual u15104ej2v0ud 17.3.4 setting example for flashpro iii (pg-fp3) when writing data to flash memory using flashpro iii (pg-fp3), use the following settings. <1> load parameter file. <2> select the serial mode and serial cock using the type command. <3> an example of the settings for pg-fp3 is shown in table 17-6. table 17-6. setting example for flashpro iii (pg-fp3) communication mode setting of flashpro iii number of v pp pulses note 3-wire serial i/o (sio3) comm port sio ch-0 0 cpu clk on target board in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz sio clk 1.0 mhz 3-wire serial i/o (sio31) comm port sio-ch1 1 cpu clk on target board in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz sio clk 1.0 mhz 3-wire serial i/o (sio32) comm port sio-ch2 2 cpu clk on target board in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz sio clk 1.0 mhz note number of v pp pulse supplied by flashpro iii (pg-fp3) when serial mode is initialized. this determines the pin used for the communication. remark comm port: selection of serial port sio clk: selection of serial clock frequency cpu clk: selection of cpu clock source to be input
226 user? manual u15104ej2v0ud chapter 18 instruction set this chapter describes each instruction set of the pd178054 subseries as list table. for details of its operation and operation code, refer to the 78k/0 series user? manual instruction (u12326e) .
227 chapter 18 instruction set user? manual u15104ej2v0ud 18.1 conventions 18.1.1 operand symbols and description operands are written in the ?perand?column of each instruction in accordance with the description of the instruction operand symbols (refer to the assembler specifications for detail). when there are two or more descriptions, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be written as they are. each symbol has the following meaning. #: immediate data specification !: absolute address specification $: relative address specification [ ]: indirect address specification in the case of immediate data, write an appropriate numeric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register symbols, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used. table 18-1. operand symbols and descriptions symbol description r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even address only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special function register symbols, refer to table 3-4 special function registers .
228 chapter 18 instruction set user? manual u15104ej2v0ud 18.1.2 description of ?peration?column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by address or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 18.1.3 description of ?lag operation?column (blank): nt affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored
229 chapter 18 instruction set user? manual u15104ej2v0ud 18.2 operation list instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 8-bit data mov r, #byte 2 4 r byte transfer saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 7 sfr byte a, r note 3 12 a r r, a note 3 12 r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 5 a sfr sfr, a 2 5 sfr a a, !addr16 3 8 9 a (addr16) !addr16, a 3 8 9 (addr16) a psw, #byte 3 7 psw byte a, psw 2 5 a psw psw, a 2 5 psw a a, [de] 1 4 5 a (de) [de], a 1 4 5 (de) a a, [hl] 1 4 5 a (hl) [hl], a 1 4 5 (hl) a a, [hl + byte] 2 8 9 a (hl + byte) [hl + byte], a 2 8 9 (hl + byte) a a, [hl + b] 1 6 7 a (hl + b) [hl + b], a 1 6 7 (hl + b) a a, [hl + c] 1 6 7 a (hl + c) [hl + c], a 1 6 7 (hl + c) a xch a, r note 3 12 a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 6 a ? sfr a, !addr16 3 8 10 a ? (addr16) a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program.
230 chapter 18 instruction set user? manual u15104ej2v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 16-bit data movw rp, #word 3 6 rp word transfer saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 8 ax sfrp sfrp, ax 2 8 sfrp ax ax, rp note 3 1 4 ax rp rp, ax note 3 1 4 rp ax ax, !addr16 3 10 12 ax (addr16) !addr16, ax 3 10 12 (addr16) ax xchw ax, rp note 3 1 4 ax ? rp 8-bit add a, #byte 2 4 a, cy a + byte operation saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 a, cy a + r r, a 2 4 r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 a, cy a + (addr16) a, [hl] 1 4 5 a, cy a + (hl) a, [hl + byte] 2 8 9 a, cy a + (hl + byte) a, [hl + b] 2 8 9 a, cy a + (hl + b) a, [hl + c] 2 8 9 a, cy a + (hl + c) addc a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 a, cy a + r + cy r, a 2 4 r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 a, cy a + (addr16) + cy a, [hl] 1 4 5 a, cy a + (hl) + cy a, [hl + byte] 2 8 9 a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 a, cy a + (hl + b) + cy a, [hl + c] 2 8 9 a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program.
231 chapter 18 instruction set user? manual u15104ej2v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 8-bit sub a, #byte 2 4 a, cy a ?byte operation saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte a, r note 3 2 4 a, cy a ?r r, a 2 4 r, cy r ?a a, saddr 2 4 5 a, cy a ?(saddr) a, !addr16 3 8 9 a, cy a ?(addr16) a, [hl] 1 4 5 a, cy a ?(hl) a, [hl + byte] 2 8 9 a, cy a ?(hl + byte) a, [hl + b] 2 8 9 a, cy a ?(hl + b) a, [hl + c] 2 8 9 a, cy a ?(hl + c) subc a, #byte 2 4 a, cy a ?byte ?cy saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte ?cy a, r note 3 2 4 a, cy a ?r ?cy r, a 2 4 r, cy r ?a ?cy a, saddr 2 4 5 a, cy a ?(saddr) ?cy a, !addr16 3 8 9 a, cy a ?(addr16) ?cy a, [hl] 1 4 5 a, cy a ?(hl) ?cy a, [hl + byte] 2 8 9 a, cy a ?(hl + byte) ?cy a, [hl + b] 2 8 9 a, cy a ?(hl + b) ?cy a, [hl + c] 2 8 9 a, cy a ?(hl + c) ?cy and a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a [hl] a, [hl + byte] 2 8 9 a a [hl + byte] a, [hl + b] 2 8 9 a a [hl + b] a, [hl + c] 2 8 9 a a [hl + c] notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program.
232 chapter 18 instruction set user? manual u15104ej2v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 8-bit or a, #byte 2 4 a a byte operation saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) a, [hl + c] 2 8 9 a a (hl + c) xor a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) a, [hl + c] 2 8 9 a a (hl + c) cmp a, #byte 2 4 a ?byte saddr, #byte 3 6 8 (saddr) ?byte a, r note 3 24 a r r, a 2 4 r ?a a, saddr 2 4 5 a ?(saddr) a, !addr16 3 8 9 a ?(addr16) a, [hl] 1 4 5 a ?(hl) a, [hl + byte] 2 8 9 a ?(hl + byte) a, [hl + b] 2 8 9 a ?(hl + b) a, [hl + c] 2 8 9 a ?(hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program.
233 chapter 18 instruction set user? manual u15104ej2v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 16-bit addw ax, #word 3 6 ax, cy ax + word operation subw ax, #word 3 6 ax, cy ax ?word cmpw ax, #word 3 6 ax ?word multiply/ mulu x 2 16 ax a x divide divuw c 2 25 ax (quotient), c (remainder) ax c increment/ inc r 1 2 r r + 1 decrement saddr 2 4 6 (saddr) (saddr) + 1 dec r 1 2 r r ?1 saddr 2 4 6 (saddr) (saddr) ?1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ?1 rotate ror a, 1 1 2 (cy, a 7 a 0 , a m? a m ) 1 time rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 time rorc a, 1 1 2 (cy a 0 , a 7 cy, a m? a m ) 1 time rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 time ror4 [hl] 2 10 12 a 3-0 (hl) 3-0 , (hl) 7-4 a 3-0 , (hl) 3-0 (hl) 7-4 rol4 [hl] 2 10 12 a 3-0 (hl) 7-4 , (hl) 3-0 a 3-0 , (hl) 7-4 (hl) 3-0 bcd adjba 2 4 decimal adjust accumulator after adjust addition adjbs 2 4 decimal adjust accumulator after subtract bit mov1 cy, saddr.bit 3 6 7 cy (saddr.bit) manipulate cy, sfr.bit 3 7 cy sfr.bit cy, a.bit 2 4 cy a.bit cy, psw.bit 3 7 cy psw.bit cy, [hl].bit 2 6 7 cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 8 sfr.bit cy a.bit, cy 2 4 a.bit cy psw.bit, cy 3 8 psw.bit cy [hl].bit, cy 2 6 8 (hl).bit cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program.
234 chapter 18 instruction set user? manual u15104ej2v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy bit and1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) manipulate cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 cy cy (hl).bit or1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 cy cy (hl).bit xor1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw. bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 cy cy (hl).bit set1 saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 8 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 2 6 psw.bit 1 [hl].bit 2 6 8 (hl).bit 1 clr1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 8 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 2 6 psw.bit 0 [hl].bit 2 6 8 (hl).bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program.
235 chapter 18 instruction set user? manual u15104ej2v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy call/return call !addr16 3 7 (sp ?1) (pc + 3) h , (sp ?2) (pc + 3) l , pc addr16, sp sp ?2 callf !addr11 2 5 (sp ?1) (pc + 2) h , (sp ?2) (pc + 2) l , pc 15-11 00001, pc 10-0 addr11, sp sp ?2 callt [addr5] 1 6 (sp ?1) (pc + 1) h , (sp ?2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ?2 brk 1 6 (sp ?1) psw, (sp ?2) (pc + 1) h , (sp ?3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ?3, ie 0 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 6 pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3, nmis 0 retb 1 6 pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3 stack push psw 1 2 (sp ?1) psw, sp sp ?1 manipulate rp 1 4 (sp ?1) rp h , (sp ?2) rp l , sp sp ?2 pop psw 1 2 psw (sp), sp sp + 1 r r r rp 1 4 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, #word 4 10 sp word sp, ax 2 8 sp ax ax, sp 2 8 ax sp uncondi- br !addr16 3 6 pc addr16 tional $addr16 2 6 pc pc + 2 + jdisp8 branch ax 2 8 pc h a, pc l x conditional bc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 1 branch bnc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program.
236 chapter 18 instruction set user? manual u15104ej2v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy conditional bt saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if(saddr.bit) = 1 branch sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 9 pc pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 11 pc pc + 4 + jdisp8 if psw. bit = 0 [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 0 btclr saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) sfr.bit, $addr16 4 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr16 3 10 12 pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b, $addr16 2 6 b b ?1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ?, then pc pc + 2 + jdisp8 if c 0 saddr. $addr16 3 8 10 (saddr) (saddr) ?1, then pc pc + 3 + jdisp8 if(saddr) 0 cpu sel rbn 2 4 rbs1, 0 n control nop 1 2 no operation ei 2 6 ie 1(enable interrupt) di 2 6 ie 0(disable interrupt) halt 2 6 set halt mode stop 2 6 set stop mode notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program.
237 chapter 18 instruction set user? manual u15104ej2v0ud 18.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 2nd operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] $addr16 1 none [hl + b] 1st operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a
238 chapter 18 instruction set user? manual u15104ej2v0ud (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 1st operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1
239 chapter 18 instruction set user? manual u15104ej2v0ud (4) call/instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand ax !addr16 !addr11 [addr5] $addr16 1st operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
240 user? manual u15104ej2v0ud chapter 19 electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.0 v v dd port ?.3 to v dd + 0.3 note 1 v v dd pll ?.3 to v dd + 0.3 note 1 v v pp pd178f054 only ?.3 to +10.5 v input voltage v i ?.3 to v dd + 0.3 v output voltage v o excluding p130 to p132 ?.3 to v dd + 0.3 v output withstand v bds p130 to p132 n-ch open drain 16 v voltage analog input voltage v an p10 to p15 analog input pin ?.3 to v dd + 0.3 v output current, high i oh per pin ? ma total of p00 to p06, p30 to p37, p54 to p57, ?5 ma p60 to p67, and p120 to p125 total of p40 to p47, p50 to p53, and p70 to p77 ?5 ma output current, low i ol note 2 per pin peak value 16 ma rms value 8 ma total of p00 to p06, p30 to p37, peak value 30 ma p40 to p47, p50 to p57, p60 to p67, rms value 15 ma p70 to p77, p120 to p125, and p130 to p132 operating temperature t a in normal operation mode ?0 to +85 c during flash memory programming 10 to 40 ( pd178f054 only) storage temperature t stg ?5 to +125 c notes 1. keep the voltage at v dd port and v dd pll same as that at the v dd pin. 2. the rms value should be calculated as follows: [rms value] = [peak value] x duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. recommended supply voltage ranges (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit supply voltage v dd1 when cpu and pll are operating 4.5 5.0 5.5 v v dd2 when cpu is operating and pll is stopped 3.5 5.0 5.5 v data retention voltage v ddr when crystal oscillation stops 2.3 5.5 v output withstand v bds p130 to p132 (n-ch open drain) 15 v voltage
241 chapter 19 electrical specifications user? manual u15104ej2v0ud dc characteristics (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 p10 to p15, p30 to p32, p35 to p37, p40 to p47, 0.7 v dd v dd v p50 to p57, p60 to p67, p71, p73, p75, p121, p124 v ih2 p00 to p06, p33, p34, p70, p72, p74, p76, p77, 0.8 v dd v dd v p120, p122, p123, p125, reset input voltage, low v il1 p10 to p15, p30 to p32, p35 to p37, p40 to p47, 0 0.3 v dd v p50 to p57, p60 to p67, p71, p73, p75, p121, p124 v il2 p00 to p06, p33, p34, p70, p72, p74, p76, p77, 0 0.2 v dd v p120, p122, p123, p125, reset output voltage, high v oh1 p00 to p06, p30 to p37, 4.5 v v dd 5.5 v, v dd ?1.0 v p40 to p47, p50 to p57, i oh = ? ma p60 to p67, p70 to p77, 3.5 v v dd < 4.5 v, v dd ?0.5 v p120 to p125 i oh = ?00 a v oh2 eo0, eo1 4.5 v v dd 5.5 v, v dd ?1.0 v i oh = ? ma output voltage, low v ol1 p00 to p06, p30 to p37, 4.5 v v dd 5.5 v, 1.0 v p40 to p47, p50 to p57, i ol = 1 ma p60 to p67, p70 to p77, 3.5 v v dd < 4.5 v, 0.5 v p120 to p125, i ol = 100 a p130 to p132 v ol2 eo0, eo1 v dd = 4.5 to 5.5 v, 1.0 v i ol = 3 ma input leakage i lih1 p00 to p06, p10 to p15, v in = v dd 3 a current, high p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120 to p125, reset remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
242 chapter 19 electrical specifications user? manual u15104ej2v0ud dc characteristics (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit input leakage i lil1 p00 to p06, p10 to p15, v in = 0 v 3 a current, low p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p120 to p125, reset output off i loh1 p130 to p132 v out = 15 v 3 a leakage current i lol1 p130 to p132 v out = 0 v 3 a i loh2 eo0, eo1 v out = v dd ? a i lol2 eo0, eo1 v out = 0 v 3 a supply current note i dd1 when cpu is operating pd178053, 2.5 15 ma and pll is stopped. pd178054 sine wave input to x1 pin pd178f054 5.0 18 ma at f x = 4.5 mhz v in = v dd i dd2 in halt mode with pll pd178053, 0.2 0.8 ma stopped. pd178054 sine wave input to x1 pin pd178f054 0.3 0.8 ma at f x = 4.5 mhz v in = v dd data retention v ddr1 when crystal resonator is oscillating 3.5 5.5 v voltage v ddr2 when crystal oscillation is power-failure detection 2.2 v stopped function v ddr3 data memory retained 2.0 v data retention i ddr1 when crystal oscillation is t a = 25 c, 2.0 4.0 a current stopped v dd = 5 v i ddr2 t a = ?0 to +85 c, 2.0 20 a v dd = 3.5 to 5.5 v note excluding av dd current and v dd pll current. remarks 1. f x : system clock oscillation frequency 2. unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
243 chapter 19 electrical specifications user? manual u15104ej2v0ud reference characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit supply current i dd3 when cpu and pll are operating. 5 ma sine wave input to vcoh pin at f in = 160 mhz v in = 0.15 v p-p ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy f x = 4.5 mhz 0.44 7.11 s (minimum instruction execution time) ti50, ti51 input f ti5 2 mhz frequency ti50, ti51 input t tih5 200 ns high-/low-level widths t til5 interrupt input t inth intp0 to intp4 1 s high-/low-level widths t intl reset pin t rsl 10 s low-level width
244 chapter 19 electrical specifications user? manual u15104ej2v0ud (2) serial interface sio3 (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) (a) 3-wire serial i/o mode (sck3 ... internal clock output) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy1 800 ns sck3 high/low-level width t kh1 ,t kcy1 /2 ?50 ns t kl1 si3 setup time to sck3 t sik1 100 ns si3 hold time from sck3 t ksi1 400 ns output delay time from sck3 to t kso1 c = 100 pf note 300 ns so3 note c is the load capacitance of sck3 and so3 output line. (b) 3-wire serial i/o mode (sck3 ... external clock input) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy2 800 ns sck3 high/low-level width t kh2 , 400 ns t kl2 si3 setup time to sck3 t sik2 100 ns si3 hold time from sck3 t ksi2 400 ns output delay time from sck3 to t kso2 c = 100 pf note 300 ns so3 sck3 at rising or falling edge time t r2 , t f2 1000 ns note c is the load capacitance of so3 output line.
245 chapter 19 electrical specifications user? manual u15104ej2v0ud ac timing test point (excluding x1 input) ti timing interrupt input timing reset input timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points 1/f ti5 t til5 t tih5 ti50, ti51, ti52 t intl t inth intp0 to intp4 t rsl reset
246 chapter 19 electrical specifications user? manual u15104ej2v0ud serial transfer timing 3-wire serial i/o mode: remark m = 1, 2 n = 2 t kcym t klm t khm sck3 si3 so3 t sikm t ksim t ksom input data output data t rn t fn
247 chapter 19 electrical specifications user s manual u15104ej2v0ud a/d converter characteristics (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit resolution 888bit total conversion v dd = 4.5 to 5.5 v 1.0 %fsr error notes 1, 2 1.4 %fsr conversion time t conv 21.3 64.0 s analog input voltage v ian 0v dd v notes 1. excluding quantization error ( 0.2%fsr) 2. this value is indicated as a ratio to the full-scale value (%fsr). pll characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit operating frequency f in1 vcol pin, mf mode, sine wave input, v in = 0.15 v p-p 0.5 3.0 mhz f in2 vcol pin, hf mode, sine wave input, v in = 0.15 v p-p 10 40 mhz f in3 vcoh pin, vhf mode, sine wave input, v in = 0.15 v p-p 60 130 mhz f in4 vcoh pin, vhf mode, sine wave input, v in = 0.3 v p-p 40 160 mhz ifc characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit operating frequency f in5 amifc pin, amif count mode, sine wave input, 0.4 0.5 mhz v in = 0.15 v p-p f in6 fmifc pin, fmif count mode, sine wave input, 10 11 mhz v in = 0.15 v p-p f in7 fmifc pin, amif count mode, sine wave input, 0.4 0.5 mhz v in = 0.15 v p-p
248 chapter 19 electrical specifications user s manual u15104ej2v0ud flash memory programming characteristics (v dd = 3.5 to 5.5 v, t a = 10 to 40 c) ( pd178f054 only) (1) write/delete characteristics parameter symbol conditions min. typ. max. unit write current (v dd pin) note i ddw when v pp = v pp1 , f x = 4.5 mhz 20 ma write current (v pp pin) note i ppw when v pp = v pp1 , f x = 4.5 mhz 20 ma delete current (v dd pin) note i dde when v pp = v pp1 , f x = 4.5 mhz 20 ma delete current (v pp pin) note i ppe when v pp = v pp1 100 ma unit delete time t er 0.5 1 1 s total delete time t era 20 s number of overwrite delete and write are counted as one cycle 20 times v pp power supply voltage v pp0 in normal mode 0 0.2 v dd v v pp1 during flash memory programming 9.7 10.0 10.3 v note port current (including current flowing to internal pull-up resistors) is not included. remark f x : system clock oscillation frequency (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit v pp setup time t psron v pp high voltage 1.0 s v pp setup time from v dd t drpsr v pp high voltage 1.0 s reset setup time from v pp t psrrf v pp high voltage 1.0 s v pp count start time from reset t rfcf 1.0 s count execution time t count 2.0 ms v pp counter high-level width t ch 8.0 s v pp counter low-level width t cl 8.0 s v pp counter noise elimination width t nfw 40 ns
249 chapter 19 electrical specifications user s manual u15104ej2v0ud flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psron t psrrf t drpsr t ch t cl t count
250 user? manual u15104ej2v0ud chapter 20 package drawing 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h
251 user? manual u15104ej2v0ud chapter 21 recommended soldering conditions the pd178053, 178054, and 178f054 should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 21-1. surface mounting type soldering conditions pd178053gc- -8bt: 80-pin plastic qfp (14 14) pd178054gc- -8bt: 80-pin plastic qfp (14 14) pd178f054gc-8bt: 80-pin plastic qfp (14 14) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: twice or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: twice or less wave soldering soldering bath temperature: 260 c or less, time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c or less, time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating).
252 user? manual u15104ej2v0ud appendix a development tools the following development tools are available for the development of systems which employ the pd178054 subseries. figure a-1 shows the configuration example of the tools. support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatibles can be used for pc98-nx series computers. when using pc98-nx series computers, refer to the description for ibm pc/at compatibles. windows unless otherwise specified, ?indows?means the following oss. windows 3.1 windows 95 windows 98 windows 2000 windows nt tm ver. 4.0
253 appendix a development tools user? manual u15104ej2v0ud figure a-1. configuration of development tools (1/2) (1) when using the in-circuit emulator ie-78k0-ns notes 1. the c compiler source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. language processing software assembler package c compiler package device file c compiler source file note 1 debugging software integrated debugger system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory software package project manager (windows only) note 2 software package flash memory write environment control software embedded software real-time os os i/o board performance board power supply unit
254 appendix a development tools user s manual u15104ej2v0ud figure a-1. configuration of development tools (2/2) (2) when using the in-circuit emulator ie-78001-r-a remark items in broken line boxes differ according to the development environment. refer to a.5 debugging tools (hardware) . system simulator integrated debugger device file embedded software real-time os os debugging tool assembler package c compiler package c library source file device file language processing software flash memory write adapter in-circuit emulator emulation probe conversion socket or conversion adapter target system host machine (pc or ews) interface board interface adapter emulation board i/o board probe board emulation probe conversion board on-chip flash memory version flash memory write environment flash programmer
255 appendix a development tools user s manual u15104ej2v0ud a.1 software package sp78k0 this package contains various software tools for 78k/0 series development. software package the following tools are included. ra78k0, cc78k0, id78k0-ns, sm78k0, and various device files part number: s sp78k0 remark in the part number differs depending on the os used. s sp78k0 host machine os supply medium ab17 pc-9800 series, windows (japanese version) cd-rom bb17 ibm pc/at compatibles windows (english version) a.2 language processing software ra78k0 assembler package cc78k0 c compiler package df178054 note 1 device file cc78k0-l note 2 c library source file notes 1. the df178054 can be used in common with the ra78k0, cc78k0, sm78k0, id78k0-ns, and id78k0. 2. cc78k0-l is not included in the software package (sp78k0). this assembler converts programs written in mnemonics into an object codes executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with an optical device file (df178054). this assembler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in assembler package) on windows. part number: s ra78k0 this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler should be used in combination with an optical assembler package and device file. this c compiler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in assembler package) on windows. part number: s cc78k0 this file contains information peculiar to the device. this device file should be used in combination with an optical tool (ra78k0, cc78k0, sm78k0, id78k0-ns, and id78k0). corresponding os and host machine differ depending on the tool used. part number: s df178054 this is a source file of functions configuring the object library included in the c compiler package. this file is required to match the object library included in c compiler package to the user s specifications. it does not depend on the operating environment because it is a source file. part number: s cc78k0-l
256 appendix a development tools user s manual u15104ej2v0ud remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.1), solaris tm (rel. 2.5.1) s df178054 s cc78k0-l host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at compatibles windows (english version) 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.1), 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt a.3 control software project manager this is control software designed to enable efficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. the project manager is included in the assembler package (ra78k0). it can only be used in windows. a.4 flash memory writing tools flashpro iii (part number: fl-pr3, pg-fp3) flash programmer fa-80gc flash memory writing adapter flashpro iii controller remark flashpro iii and fa-80gc are products of naito densei machida mfg. co., ltd. contact: +81-45-475-4191 naito densei machida mfg. co., ltd. flash programmer dedicated to microcontrollers with on-chip flash memory. flash memory writing adapter used connected to the flashpro iii. fa-80gc: 80-pin plastic qfp (gc-8bt type) control program that runs on a pc. this is supplied with flashpro iii.
257 appendix a development tools user? manual u15104ej2v0ud a.5 debugging tools (hardware) (1/2) (1) when using the in-circuit emulator ie-78k0-ns ie-78k0-ns in-circuit emulator ie-78k0-ns-pa performance board ie-78k0-ns-a in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if-a pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-178054-ns-em1 emulation board np-80gc emulation probe ev-9200gc-80 conversion socket (refer to figures a-2, a-3 ) remarks 1. np-80gc is a product of naito densei machida mfg. co., ltd. contact: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. ev-9200gc-80 is sold in five-unit sets. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to integrated debugger (id78k0-ns). this emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. this board is used for extending the ie-78k0-ns functions, and is used connected to the ie-78k0-ns. with the addition of this board, the addition of a coverage function, enhancement of tracer and timer functions, and other such debugging function enhancements are possible. in-circuit emulator that combines ie-78k0-ns and ie-78k0-ns-pa this adapter is used for supplying power from a receptacle of 100 to 240 v ac. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-78k0-ns host machine (c bus compatible). this is pc card and interface cable required when using the notebook-type computer as the ie-78k0-ns host machine (pcmcia socket compatible). this adapter is required when using the ibm pc compatible computers as the ie-78k0- ns host machine (isa bus compatible). this adapter is required when using a pc with a pci bus as the ie-78k0-ns host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator to the target system and is designed for 80-pin plastic qfp (gc-8bt type). this conversion socket connects the np-80gc to the target system board designed to mount an 80-pin plastic qfp (gc-8bt type).
258 appendix a development tools user? manual u15104ej2v0ud a.5 debugging tools (hardware) (2/2) (2) when using the in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator ie-70000-98-if-c interface adapter ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-78000-r-sv3 interface adapter ie-178054-ns-em1 emulation board ie-78k0-r-ex1 emulation probe conversion board ep-78230gc-r emulation probe ev-9200gc-80 conversion socket (refer to figures a-2, a-3 ) remark ev-9200gc-80 is sold in five-unit sets. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to integrated debugger (id78k0). this emulator should be used in combination with emulation probe and interface adapter, which is required to connect this emulator to the host machine. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-78001-r-a host machine (c bus compatible). this adapter is required when using the ibm pc/at compatible computers as the ie- 78001-r-a host machine (isa bus compatible). this adapter is required when using a pc with a pci bus as the ie-78001-r-a host machine. this is adapter and cable required when using an ews computer as the ie-78001-r- a host machine, and is used connected to the board in the ie-78000-r-a. as ethernet tm , 10base-5 is supported. with the other method, a commercially available conversion adapter is necessary. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator and emulation conversion board. this board is required when using the ie-178054-ns-em1 on the ie-78001-r-a. this probe is used to connect the in-circuit emulator to the target system and is designed for 80-pin plastic qfp (gc-8bt type). this conversion socket connects the ep-78230gc-r to the target system board designed to mount an 80-pin plastic qfp (gc-8bt type).
259 appendix a development tools user? manual u15104ej2v0ud a.6 debugging tools (software) sm78k0 this is a system simulator for the 78k/0s series. the sm78k0 is windows-based system simulator software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with the device file (df178054) (sold separately). part number: s sm78k0 id78k0-ns this debugger supports the in-circuit emulators for the 78k/0 series. the integrated debugger id78k0-ns and id78k0 are windows-based software. (supporting in-circuit emulators id78k0: supports in-circuit emulator ie-78001-r-a. ie-78k0-ns and ie-78k0-ns-a) id78k0-ns: supports in-circuit emulators ie-78k0-ns and ie-78k0-ns-a. id78k0 it has improved c-compatible debugging functions and can display the results of integrated debugger tracing with the source program using an integrating window function that associates (supporting in-circuit emulator the source program, disassemble display, and memory display with the trace result. ie-78001-r-a) it should be used in combination with the device file (sold separately). part number: s id78k0-ns, s id78k0 remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns s id78k0 host machine os supply medium ab13 ibm pc/at compatibles windows (japanese version) 3.5-inch 2hd fd bb13 windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version)
260 appendix a development tools user? manual u15104ej2v0ud a.7 embedded software rx78k0 rx78k0 is a real-time os conforming to the itron specifications. real-time os tool (configurator) for generating nucleus of rx78k0 and plural information tables is supplied. used in combination with an optional assembler package (ra78k0) and device file (df178054). the real-time os is a dos-based application. it should be used in the dos prompt when using in windows. part number: s rx78013- ???? caution when purchasing the rx78k0, fill in the purchase application form in advance and sign the user agreement. remark and ???? in the part number differ depending on the host machine and os used. s rx78013- ???? ???? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k mass-production object 0.1 million units 001m 1 million units 010m 10 million units s01 source program source program for mass-produced object host machine os supply medium aa13 pc-9800 series windows (japanese version) 3.5-inch 2hd fd ab13 ibm pc/at compatibles windows (japanese version) bb13 windows (english version)
261 appendix a development tools user s manual u15104ej2v0ud a.8 system upgrade from former in-circuit emulator for 78k/0 series to ie-78001-r-a if you already have a former in-circuit emulator for 78k/0 series microcontrollers (ie-78000-r or ie-78000-r-a), that in-circuit emulator can operate as an equivalent to the ie-78001-r-a by replacing its internal break board with the ie-78001-r-bk. table a-1. system upgrade method from former in-circuit emulator for 78k/0 series to ie-78001-r-a in-circuit emulator owned in-circuit emulator cabinet system upgrade note board to be purchased ie-78000-r required ie-78001-r-bk ie-78000-r-a not required note for upgrading a cabinet, send user s in-circuit emulator to nec.
262 appendix a development tools user s manual u15104ej2v0ud drawing for conversion socket (ev-9200gc-80) package and recommended board mounting pattern figure a-2. ev-9200gc-80 package drawing (for reference only) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g1e item millimeters inches a b c d e f g h i j k l m n o p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059
263 appendix a development tools user s manual u15104ej2v0ud figure a-3. ev-9200gc-80 recommended board mounting pattern (for reference only) a f d e c b g j k l h i 0.026 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p1e item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 +0.001 0.002 +0.003 0.002 +0.001 0.002 +0.003 0.002 +0.003 0.002 +0.003 0.002 +0.001 0.001 +0.001 0.002 +0.001 0.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution
264 user? manual u15104ej2v0ud appendix b register index b.1 register index 8-bit compare register 50 (cr50) ... 100 8-bit compare register 51 (cr51) ... 100 8-bit compare register 52 (cr52) ... 100 8-bit compare register 53 (cr53) ... 100 8-bit timer counter 50 (tm50) ... 99 8-bit timer counter 51 (tm51) ... 99 8-bit timer counter 52 (tm52) ... 99 8-bit timer counter 53 (tm53) ... 99 8-bit timer mode control register 50 (tmc50) ... 102 8-bit timer mode control register 51 (tmc51) ... 102 8-bit timer mode control register 52 (tmc52) ... 102 8-bit timer mode control register 53 (tmc53) ... 104 [a] a/d conversion result register 3 (adcr3) ... 132, 146 a/d converter mode register 3 (adm3) ... 133 analog input channel specification register 3 (ads3) ... 134 [b] beep clock select register 0 (beepcl0) ... 128 [c] clock output select register (cks) ... 129 [d] dts system clock select register (dtsck) ... 88 [e] external interrupt falling edge enable register (egn) ... 164 external interrupt rising edge enable register (egp) ... 164 [i] if counter control register (ifccr) ... 198 if counter gate judge register (ifcjg) ... 198 if counter mode select register (ifcmd) ... 197 if counter register (ifcr) ... 196 internal expansion ram size switching register (ixs) ... 222 interrupt mask flag register 0h (mk0h) ... 162 interrupt mask flag register 0l (mk0l) ... 162 interrupt request flag register 0h (if0h) ... 161 interrupt request flag register 0l (if0l) ... 161
265 appendix b register index user? manual u15104ej2v0ud [m] memory size switching register (ims) ... 221 [o] oscillation stabilization time select register (osts) ... 124, 204 [p] pll data register (pllr) ... 190, 191, 192 pll data register 0 (pllr0) ... 180 pll data register h (pllrh) ... 180 pll data register l (pllrl) ... 180 pll data transfer register (pllns) ... 184 pll mode select register (pllmd) ... 181 pll reference mode register (pllrf) ... 182 pll unlock f/f judge register (pllul) ... 183 poc status register (pocs) ... 218, 219 port 0 (p0) ... 70 port 1 (p1) ... 71 port 3 (p3) ... 72 port 4 (p4) ... 74 port 5 (p5) ... 75 port 6 (p6) ... 76 port 7 (p7) ... 77 port 12 (p12) ... 80 port 13 (p13) ... 82 port mode register 0 (pm0) ... 83 port mode register 3 (pm3) ... 83 port mode register 4 (pm4) ... 83 port mode register 5 (pm5) ... 83 port mode register 6 (pm6) ... 83 port mode register 7 (pm7) ... 83 port mode register 12 (pm12) ... 83 power-fail comparison mode register 3 (pfm3) ... 135 power-fail comparison threshold value register 3 (pft3) ... 132, 141 priority specification flag register 0h (pr0h) ... 163 priority specification flag register 0l (pr0l) ... 163 processor clock control register (pcc) ... 90 pull-up resistor option register 4 (pu4) ... 86 [s] serial i/o shift register 30 (sio30) ... 149 serial i/o shift register 31 (sio31) ... 149 serial i/o shift register 32 (sio32) ... 149 serial operating mode register 30 (csim30) ... 150 serial operating mode register 31 (csim31) ... 150 serial operating mode register 32 (csim32) ... 150 serial port select register 32 (sio32sel) ... 151
266 appendix b register index user? manual u15104ej2v0ud [t] timer clock select register 50 (tcl50) ... 101 timer clock select register 51 (tcl51) ... 101 timer clock select register 52 (tcl52) ... 101 timer clock select register 53 (tcl53) ... 102 [w] watchdog timer clock select register (wdcs) ... 122 watchdog timer mode register (wdtm) ... 123
267 appendix b register index user? manual u15104ej2v0ud b.2 register index (symbol) [a] adcr3: a/d conversion result register 3 ... 132, 146 adm3: a/d converter mode register 3 ... 133 ads3: analog input channel specification register 3 ... 134 [b] beepcl0: beep clock select register 0 ... 128 [c] cks: clock output select register ... 129 cr50: 8-bit compare register 50 ... 100 cr51: 8-bit compare register 51 ... 100 cr52: 8-bit compare register 52 ... 100 cr53: 8-bit compare register 53 ... 100 csim30: serial operating mode register 30 ... 150 csim31: serial operating mode register 31 ... 150 csim32: serial operating mode register 32 ... 150 [d] dtsck: dts system clock select register ... 88 [e] egn: external interrupt falling edge enable register ... 164 egp: external interrupt rising edge enable register ... 164 [i] if0h: interrupt request flag register 0h ... 161 if0l: interrupt request flag register 0l ... 161 ifccr: if counter control register ... 198 ifcjg: if counter gate judge register ... 198 ifcmd: if counter mode select register ... 197 ifcr: if counter register ... 196 ims: memory size switching register ... 221 ixs: internal expansion ram size switching register ... 222 [m] mk0h: interrupt mask flag register 0h ... 162 mk0l: interrupt mask flag register 0l ... 162 [o] osts: oscillation stabilization time select register ... 124, 204 [p] p0: port 0 ... 70 p1: port 1 ... 71 p3: port 3 ... 72
268 appendix b register index user? manual u15104ej2v0ud p4: port 4 ... 74 p5: port 5 ... 75 p6: port 6 ... 76 p7: port 7 ... 77 p12: port 12 ... 80 p13: port 13 ... 82 pcc: processor clock control register ... 90 pfm3: power-fail comparison mode register 3 ... 135 pft3: power-fail comparison threshold value register 3 ... 132, 141 pllmd: pll mode select register ... 181 pllns: pll data transfer register ... 184 pllr: pll data register ... 190, 191, 192 pllr0: pll data register 0 ... 180 pllrf: pll reference mode register ... 182 pllrh: pll data register h ... 180 pllrl: pll data register l ... 180 pllul: pll unlock f/f judge register ... 183 pm0: port mode register 0 ... 83 pm3: port mode register 3 ... 83 pm4: port mode register 4 ... 83 pm5: port mode register 5 ... 83 pm6: port mode register 6 ... 83 pm7: port mode register 7 ... 83 pm12: port mode register 12 ... 83 pocs: poc status register ... 218, 219 pr0h: priority specification flag register 0h ... 163 pr0l: priority specification flag register 0l ... 163 pu4: pull-up resistor option register 4 ... 86 [s] sio30: serial i/o shift register 30 ... 149 sio31: serial i/o shift register 31 ... 149 sio32: serial i/o shift register 32 ... 149 sio32sel: serial port select register 32 ... 151 [t] tcl50: timer clock select register 50 ... 101 tcl51: timer clock select register 51 ... 101 tcl52: timer clock select register 52 ... 101 tcl53: timer clock select register 53 ... 102 tm50: 8-bit timer counter 50 ... 99 tm51: 8-bit timer counter 51 ... 99 tm52: 8-bit timer counter 52 ... 99 tm53: 8-bit timer counter 53 ... 99 tmc50: 8-bit timer mode control register 50 ... 102 tmc51: 8-bit timer mode control register 51 ... 102 tmc52: 8-bit timer mode control register 52 ... 102 tmc53: 8-bit timer mode control register 53 ... 104
269 appendix b register index user? manual u15104ej2v0ud [w] wdcs: watchdog timer clock select register ... 122 wdtm: watchdog timer mode register ... 123
270 user? manual u15104ej2v0ud appendix c revision history a history of the revisions up to this edition is shown below. ?pplied to:?indicates the chapters to which the revision was applied. edition description applied to: 2nd change of pd178053, 178054, and 178f054 status from under development to throughout development completed modification of related documents preface modification of 1.5 development of 8-bit dts series chapter 1 outline modification of bit units for manipulation for osts in table 3-4 special function chapter 3 registers cpu architecture deletion of pins p10 to p15 from table 4-3 port mode register and output latch chapter 4 settings when using alternate functions port functions modification of description in (3) oscillation stabilization time select register chapter 8 (osts) in 8.3 registers controlling watchdog timer watchdog timer addition of electrical specifications chapter 19 electrical specifications addition of package drawing chapter 20 package drawing addition of recommended soldering conditions chapter 21 recommended soldering conditions modification of figure a-1 configuration of development tools appendix a addition of a.1 software package and a.3 control software development tools addition of note 2 to a.2 language processing software addition of description for ie-78k0-ns-a to a.5 debugging tools (hardware) deletion of mx78k0 from a.7 embedded software
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