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1 512k (64k x 8) multiplexed addresses/ outputs low-voltage otp eprom at27lv520 features ? 8-bit multiplexed addresses/outputs fast read access time ? 70 ns dual voltage range operation ? low-voltage power supply range, 3.0v to 3.6v, or ? standard 5v 10% supply range pin compatible with standard at27c520 low-power cmos operation ? 20 a max. standby for ale = v ih and v cc = 3.6v ? 29 mw max. active at 5 mhz for v cc = 3.6v jedec standard packages ? 20-lead tssop ? 20-lead soic high-reliability cmos technology ? 2,000v esd protection ? 200 ma latch-up immunity rapid ? programming algorithm ? 50 s/byte (typical) cmos- and ttl-compatible inputs and outputs ? jedec standard for lvttl integrated product identification code commercial and industrial temperature range description the at27lv520 is a low-power, high-performance, 524,288-bit one-time programma- ble read-only memory (otp eprom) organized 64k by eight bits. it incorporates latches for the eight lower order address bits to multiplex with the eight data bits. this minimizes system chip count, reduces cost, and simplifies the design of multiplexed bus systems. it requires only one power supply in the range of 3.0v to 3.6v for normal read mode operation, making it ideal for fast, portable systems using battery power. any byte can be accessed in less than 70 ns. the at27lv520 is available in 173 mil, 20-lead tssop and 300 mil, 20-lead soic, one-time programmable (otp) plastic packages. rev. 0911d?05/00 pin configurations pin name function a8 - a15 addresses ad0 - ad7 addresses/outputs oe /vpp output enable/program supply ale address latch enable tssop top view 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 a10 a12 a14 ale vcc oe/vpp a15 a13 a11 a9 a8 ad1 ad3 ad5 ad7 gnd ad6 ad4 ad2 ad0 (continued) soic top view 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe/vpp a15 a13 a11 a9 ad0 ad2 ad4 ad6 gnd vcc ale a14 a12 a10 a8 ad1 ad3 ad5 ad7
at27lv520 2 atmel ? s innovative design techniques provide fast speeds that rival 5v parts while keeping the low power consump- tion of a 3.3v supply. at v cc = 3.0v, any byte can be accessed in less than 70 ns. with a typical power dissipa- tion of only 18 mw at 5 mhz and v cc = 3.3v, the at27lv520 consumes less than one fifth the power of a standard 5v eprom. standby mode is achieved by assert- ing ale high. standby mode supply current is typically less than 1 a at 3.3v. the at27lv520 operating with v cc at 3.0v produces ttl level outputs that are compatible with standard ttl logic devices operating at v cc = 5.0v. the device is also capa- ble of standard 5-volt operation making it ideally suited for dual supply range systems or card products that are plug- gable in both 3-volt and 5-volt hosts. atmel ? s at27lv520 has additional features to ensure high quality and efficient production use. the rapid ? program- ming algorithm reduces the time required to program the part and guarantees reliable programming. programing time is typically only 50 s/byte. the integrated product identification code electronically identifies the device and manufacturer. this feature is used by industry standard programming equipment to select the proper programming algorithms and voltages. the at27lv520 programs exactly the same way as a standard 5v at27c520 and uses the same programming equipment. system considerations switching under active conditions may produce transient voltage excursions. unless accommodated by the system design, these transients may exceed data sheet limits, resulting in device non-conformance. at a minimum, a 0.1 f high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. this capacitor should be connected between the v cc and ground termi- nals of the device, as close to the device as possible. addi- tionally, to stabilize the supply voltage level on printed circuit boards with large eprom arrays, a 4.7 f bulk elec- trolytic capacitor should be utilized, again connected between the v cc and ground terminals. this capacitor should be positioned as close as possible to the point where the power supply is connected to the array. block diagram oe, ale, and program logic y decoder x decoder y-gating cell matrix identification output buffers vcc gnd oe/vpp latches ale ad7 - ad0 a15 - a8 8 8
at27lv520 3 note: 1. minimum voltage is -0.6v dc which may undershoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc which may overshoot to +7.0v for pulses of less than 20 ns. notes: 1. x can be v il or v ih. 2. read, output disable, and standby modes require 3.0v v cc 3.6v, or 4.5v v cc 5.5v. 3. refer to programming characteristics. 4. v h = 12.0 0.5v. 5. two identifier bytes may be selected. all a8 - a15 inputs are held low (v il ), except a9 which is set to v h and a8 which is tog- gled low (v il ) to select the manufacturer ? s identification byte and high (v ih ) to select the device code byte. absolute maximum ratings* temperature under bias ................................ -55 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on a9 with respect to ground ......................................-2.0v to +14.0v (1) v pp supply voltage with respect to ground .......................................-2.0v to +14.0v (1) operating modes mode/pin ale oe /v pp a8 - a15 ad0 - ad7 read (2) v il v il ai d out output disable (2) v il /v ih v ih x (1) high z/a0 - a7 standby v ih v ih ai a0 - a7 address latch enable (2) v ih v ih xa0 - a7 rapid program (3) v ih v pp ai d in product identification (4) v il v il a9 = v h (5) a8 = v ih or v il a10 - a15 = v il identification code
at27lv520 4 note: 1. v cc standby current will be slightly higher with ale, ai, and adi at ttl levels. dc and ac operating conditions for read operation at27lv520-70 at27lv520-90 operating temp. (case) com. 0 c - 70 c0 c - 70 c ind. -40 c - +85 c-40 c - +85 c v cc supply 3.0v to 3.6v 3.0v to 3.6v 5v = 10% 5v = 10% dc and operating characteristics for read operation symbol parameter condition min max units v cc = 3.0v to 3.6v i li input load current v in = 0v to v cc 1a i lo output leakage current v out = 0v to v cc 5a i sb (1) v cc standby current ale = v cc 0.3v; ai, adi = gnd/v cc 0.3v 20 a i cc v cc active current f = 5 mhz, i out = 0 ma, ale = v il 8ma v il input low voltage -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 2.0 ma 0.4 v v oh output high voltage i oh = -2.0 ma 2.4 v v cc = 4.5v to 5.5v i li input load current v in = 0v to v cc 1a i lo output leakage current v out = 0v to v cc 5a i sb (1) v cc standby current ale = v cc 0.3v; ai, adi = gnd/v cc 0.3v 100 a i cc v cc active current f = 5 mhz, i out = 0 ma, ale = v il 20 ma v il input low voltage -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 a 2.4
at27lv520 5 note: 3, 4, 5 ? see ac waveforms for read operation ac waveforms for read operation (1) notes: 1. timing measurement reference levels for all speed grades are v ol = 0.8v and v oh = 2.0v. input ac drive levels are v il = 0.45v and v ih = 2.4v. 2. oe /v pp may be delayed up to t ce - t oe after the address is valid without impact on t ce . 3. oe /v pp may be delayed up to t acc - t oe after the address is valid without impact on t acc . 4. this parameter is only sampled and is not 100% tested. 5. output float is defined as the point when data is no longer driven. ac characteristics for read operation v cc = 3.0v to 3.6v and 4.5v to 5.5v symbol parameter condition at27lv520-70 at27lv520-90 units min max min max t acc (3) address to output delay ale = oe /v pp = v il 70 90 ns t ce address latch enable low to output delay address valid 55 70 ns t as address setup time oe /v pp = v ih 12 15 ns t ah address hold time oe /v pp = v ih 12 15 ns t ale address latch enable width oe /v pp = v ih 40 45 ns t oe (3) oe /v pp to output delay ale = v il 30 35 ns t df (4)(5) oe /v pp high to output float ale = v il 25 25 ns t oh output hold from address or oe /v pp , whichever occurred first ale = v il 70ns ale oe/v pp ad7 - ad0 a15 - a8 tale address in tas tah data out toe tacc tdf toh tce
at27lv520 6 input test waveforms and measurement levels t r , t f < 20 ns (10% to 90%) output test load note: c l = 100 pf including jig capacitance. note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. pin capacitance f = 1 mhz, t = 25 c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
at27lv520 7 programming waveforms notes: 1. the input timing reference is 0.8v for v il and 2.0v for v ih . 2. t oe and t dfp are characteristics of the device but must be accommodated by the programmer. dc programming characteristics t a = 25 5 c, v cc = 6.5 0.25v, oe /v pp = 13.0 0.25v symbol parameter test conditions limits units min max i li input load current v in = v il , v ih 10 a v il input low level -0.6 0.8 v v ih input high level 2.0 v cc + 1.0 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 a 2.4 v i cc2 v cc supply current (program and verify) 25 ma i pp2 oe /v pp current ale = v ih 25 ma v cc oe/v pp ale ad7 - ad0 a15 - a8 6.5v 5.0v 13v v ih v il v ih v il v ih v il v ih v il tvcs toes tprt tlp tale addr tlas tlah tas data in tpw toeh tvr tdh tds addr tale tlah tlas data out toe tdfp tah address stable program read (verify)
at27lv520 8 notes: 1. v cc must be applied simultaneously or before oe /v pp and removed simultaneously or after oe /v pp . 2. program pulse width tolerance is 50 = sec = = 5%. 3. this parameter is only sampled and is not 100% tested. output float is defined as the point where data is no longer driven ? see timing diagram. note: 1. the at27lv520 has the same product identification code as the at27c520. both are programming compatible. ac programming characteristics t a = 25 5 c, v cc = 6.5 0.25v, oe /v pp = 13.0 0.25v symbol parameter (1) test conditions limits units min max t ale address latch enable width input rise and fall times: (10% to 90%) 20 ns input pulse levels: 0.45v to 2.4v input timing reference level: 0.8v to 2.0v output timing reference level: 0.8v to 2.0v 500 ns t las latched address setup time 100 ns t lah latched address hold time 100 ns t lp ale low to oe /v pp high voltage delay 2 s t oes oe /v pp setup time 2 s t oeh oe /v pp hold time 2 s t ds data setup time 2 s t dh data hold time 2 s t pw ale program pulse width (2) 47.5 52.5 s t vr oe /v pp recovery time 2 s t vcs v cc setup time 2 s t oe data valid from oe /v pp 150 ns t dfp oe /v pp high to output float delay (3) 0 130 ns t as address setup time 2 s t ah address hold time 0 s t prt oe /v pp pulse rise time during programming 50 ns atmel ? s 27lv520 integrated product identification code codes pins hex data a8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 manufacturer 0000111101e device type 1100111019d
at27lv520 9 rapid ? programming algorithm a 50 s ale pulse width is used to program. the address is set to the first location. v cc is raised to 6.5v and oe /v pp is raised to 13.0v. each address is first programmed with one 50 s ale pulse without verification. then a verifica- tion/reprogramming loop is executed for each address. in the event a byte fails to pass verification, up to 10 succes- sive 50 s pulses are applied with a verification after each pulse. if the byte fails to verify after 10 pulses have been applied, the part is considered failed. after the byte verifies properly, the next address is selected until all have been checked. oe /v pp is then lowered to v ih and v cc to 5.0v. all bytes are read again and compared with the original data to determine if the device passes or fails. start addr = first location addr = first location vcc = 6.5v vpp = 13.0v vcc = 5.0v vpp = 5.0v program one 50 s pulse program one 50 s pulse last addr.? last addr.? no no no x = 0 x = 10? increment x verify byte device failed device passed compare all bytes to original data yes yes yes increment address increment address pass pass fail fail
at27lv520 10 ordering information t acc (ns) i cc (ma) active ordering code package operation range 90 8 at27lv520-90sc at27lv520-90xc 20s 20x commercial (0 c to 70 c) at27lv520-90si at27lv520-90xi 20s 20x industrial (-40 c to +85 c) 70 8 at27lv520-70sc at27lv520-70xc 20s 20x commercial (0 c to 70 c) AT27LV520-70SI at27lv520-70xi 20s 20x industrial (-40 c to +85 c) package type 20s 20-lead, 0.300" wide, plastic gull wing small outline (soic) 20x 20-lead, 0.173" wide, thin shrink small outline (tssop)
at27lv520 11 packaging information 0.299 (7.60) 0.291 (7.39) 0.020 (0.508) 0.013 (0.330) 0.420 (10.7) 0.393 (9.98) pin 1 .050 (1.27) bsc 0.513 (13.0) 0.497 (12.6) 0.012 (0.305) 0.003 (0.076) 0.105 (2.67) 0.092 (2.34) 0 8 ref 0.035 (0.889) 0.015 (0.381) 0.013 (0.330) 0.009 (0.229) 4.48(.176) 4.30(.169) 6.50(.256) 6.25(.246) 0.65(.0256) bsc 0.30(0.012) 0.18(0.007) pin 1 id 6.60(.260) 6.40(.252) 0.15(.006) 0.05(.002) 1.10(0.043) max 0.18(.007) 0.09(.003) 0 8 ref 0.70(.028) 0.50(.020) 20s , 20-lead, 0.300" wide, plastic gull wing small outline dimensions in inches and (millimeters) 20x , 20-lead, 0.173" wide, thin super small outline package (tssop) dimensions in (millimeters) and inches
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