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d a t a sh eet product speci?cation file under discrete semiconductors, sc07 1995 apr 25 discrete semiconductors philips semiconductors BF1100WR dual-gate mos-fet
1995 apr 25 2 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR features specially designed for use at 9 to 12 v supply voltage short channel transistor with high forward transfer admittance to input capacitance ratio low noise gain controlled amplifier up to 1 ghz superior cross-modulation performance during agc. applications vhf and uhf applications such as television tuners and professional communications equipment. description enhancement type field-effect transistor in a plastic microminiature sot343r package. the transistor consists of an amplifier mos-fet with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during agc. caution the device is supplied in an antistatic package. the gate-source input must be protected against static discharge during transport or handling. pinning pin symbol description 1 s, b source 2 d drain 3 g 2 gate 2 4 g 1 gate 1 fig.1 simplified outline (sot343r) and symbol. marking code: mf. handbook, halfpage mam192 s,b d g 1 g 2 top view 2 1 3 4 quick reference data symbol parameter conditions min. typ. max. unit v ds drain-source voltage - - 14 v i d drain current - - 30 ma p tot total power dissipation - - 280 mw t j operating junction temperature - - 150 c ? y fs ? forward transfer admittance 24 28 33 ms c ig1-s input capacitance at gate 1 - 2.2 2.6 pf c rs reverse transfer capacitance f = 1 mhz - 25 35 ff f noise ?gure f = 800 mhz - 2 - db
1995 apr 25 3 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR limiting values in accordance with the absolute maximum rating system (iec 134). note 1. device mounted on a printed-circuit board. symbol parameter conditions min. max. unit v ds drain-source voltage - 14 v i d drain current - 30 ma i g1 gate 1 current - 10 ma i g2 gate 2 current - 10 ma p tot total power dissipation see fig.2; up to t amb = 50 c; note 1 - 280 mw t stg storage temperature - 65 +150 c t j operating junction temperature - +150 c fig.2 power derating curve. handbook, halfpage 0 50 100 200 300 0 mld180 150 200 100 p tot (mw) t ( c) amb o fig.3 forward transfer admittance as a function of junction temperature; typical values. 50 0 50 150 40 0 mld156 100 30 20 10 y fs (ms) t ( c) j o
1995 apr 25 4 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR thermal characteristics notes 1. device mounted on a printed-circuit board. 2. t s is the temperature at the soldering point of the source lead. static characteristics t j = 25 c; unless otherwise speci?ed. notes 1. r g1 connects gate 1 to v gg = 9 v; see fig.26. 2. r g1 connects gate 1 to v gg = 12 v; see fig.26. symbol parameter conditions value unit r th j-a thermal resistance from junction to ambient note 1 350 k/w r th j-s thermal resistance from junction to soldering point t s = 91 c; note 2 210 k/w symbol parameter conditions min. max. unit v (br)g1-ss gate 1-source breakdown voltage v g2-s = v ds = 0; i g1-s = 1 ma 13.2 20 v v (br)g2-ss gate 2-source breakdown voltage v g1-s = v ds = 0; i g2-s = 1 ma 13.2 20 v v (f)s-g1 forward source-gate 1 voltage v g2-s = v ds = 0; i s-g1 = 10 ma 0.5 1.5 v v (f)s-g2 forward source-gate 2 voltage v g1-s = v ds = 0; i s-g2 = 10 ma 0.5 1.5 v v g1-s(th) gate 1-source threshold voltage v g2-s = 4 v; v ds = 9 v; i d = 20 m a 0.3 1 v v g2-s = 4 v; v ds = 12 v; i d = 20 m a 0.3 1 v v g2-s(th) gate 2-source threshold voltage v g1-s = 4 v; v ds = 9 v; i d = 20 m a 0.3 1.2 v v g1-s = 4 v; v ds = 12 v; i d = 20 m a 0.3 1.2 v i dsx drain-source current v g2-s = 4 v; v ds = 9 v; r g1 = 180 k w ; note 1 8 13 ma v g2-s = 4 v; v ds = 12 v; r g1 = 250 k w ; note 2 8 13 ma i g1-ss gate 1 cut-off current v g2-s = v ds = 0; v g1-s = 12 v - 50 na i g2-ss gate 2 cut-off current v g1-s = v ds = 0; v g2-s = 12 v - 50 na
1995 apr 25 5 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR dynamic characteristics common source; t amb = 25 c; v g2-s = 4 v; i d = 10 ma; unless otherwise specified. symbol parameter conditions min. typ. max. unit ? y fs ? forward transfer admittance pulsed; t j = 25 c v ds = 9 v 24 28 33 ms v ds = 12 v 24 28 33 ms c ig1-s input capacitance at gate 1 f = 1 mhz v ds = 9 v - 2.2 2.6 pf v ds = 12 v - 2.2 2.6 pf c ig2-s input capacitance at gate 2 f = 1 mhz v ds = 9 v - 1.6 - pf v ds = 12 v - 1.4 - pf c os drain-source capacitance f = 1 mhz v ds = 9 v - 1.4 1.8 pf v ds = 12 v - 1.1 1.5 pf c rs reverse transfer capacitance f = 1 mhz v ds = 9 v - 25 35 ff v ds = 12 v - 25 35 ff f noise ?gure f = 800 mhz; g s = g sopt ; b s = b sopt v ds = 9 v - 2 2.8 db v ds = 12 v - 2 2.8 db fig.4 gain reduction as a function of the agc voltage; typical values. f = 50 mhz. t j = 25 c. handbook, halfpage 0 10 20 30 40 50 0 1 2 3 4 v (v) agc gain reduction (db) mld157 (1) r g = 250 k w to v gg = 12 v. (2) r g = 180 k w to v gg = 9 v. f w = 50 mhz; f unw = 60 mhz; t amb = 25 c. fig.5 unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see fig.26. handbook, halfpage 80 90 100 110 120 0 (1) (2) 10 20 30 40 50 v unw (db m v) gain reduction (db) mld158
1995 apr 25 6 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR fig.6 output characteristics; typical values. v g2-s = 4 v. t j = 25 c. handbook, halfpage 0 20 16 4 8 12 0 4 16 mld159 8 12 i d (ma) v (v) ds 1.3 v 1.2 v 1.1 v 1.0 v 0.9 v v = 1.4 v g1 s fig.7 transfer characteristics; typical values. v ds = 9 to 12 v. t j = 25 c. handbook, halfpage 0 20 16 4 8 12 0 0.4 2.0 mld160 0.8 1.2 1.6 i d (ma) v (v) g1 s v = 4 v 2.5 v 2 v 1.5 v 1 v g2 s 3 v fig.8 gate 1 current as a function of gate 1 voltage; typical values. v ds = 9 to 12 v. t j = 25 c. handbook, halfpage 0 1 2 3 250 200 150 50 0 100 mld161 i g1 ( m a) v (v) g1 s 3 v 2.5 v 2 v 3.5 v v = 4 v g2 s fig.9 forward transfer admittance as a function of drain current; typical values. v ds = 9 to 12 v. t j = 25 c. handbook, halfpage 0 40 20 30 10 0 10 20 30 mld162 y fs (ms) i (ma) d 3 v 2.5 v 2 v v = 4 v g2 s 3.5 v
1995 apr 25 7 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR fig.10 drain current as a function of gate 1 current; typical values. v ds = 9 to 12 v. v g2-s = 4 v. t j = 25 c. handbook, halfpage 0 20 40 80 60 16 12 4 0 8 mld163 i ( m a) g1 i d (ma) fig.11 drain current as a function of gate 1 supply voltage (= v gg ) and drain supply voltage; typical values; see fig.26. v g2-s = 4 v. r g1 connected to v gg . t j = 25 c. handbook, halfpage 0 20 15 10 5 0 4 8 16 mld164 12 v = v (v) gg ds i d (ma) r = 100 k w g1 147 k w 180 k w 205 k w 249 k w 301 k w 402 k w 511 k w fig.12 drain current as a function of gate 1 voltage (= v gg ); typical values; see fig.26. v ds = 9 v; v g2-s = 4 v. r g1 = 180 k w ( connected to v gg ); t j = 25 c. handbook, halfpage 0 2 4 10 8 6 12 4 0 8 mld165 v (v) gg i d (ma) v ds = 12 v; v g2-s = 4 v. r g1 = 250 k w (connected to v gg ); t j = 25 c. fig.13 drain current as a function of gate 1 voltage (= v gg ); typical values; see fig.26. handbook, halfpage 0 4 8 12 12 4 0 8 mld166 v (v) gg i d (ma)
1995 apr 25 8 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR fig.14 gate 1 current as a function of gate 2 voltage; typical values. v ds = 9 v. r g1 = 180 k w (connected to v gg ); t j = 25 c. handbook, halfpage 0 2 4 6 50 40 30 10 0 20 mld167 i g1 ( m a) v (v) g2 s 8 v 7 v 6 v 5 v 4 v v = 9 v gg fig.15 gate 1 current as a function of gate 2 voltage; typical values. v ds = 12 v. r g1 = 250 k w (connected to v gg ); t j = 25 c. handbook, halfpage 0 2 4 6 50 40 30 10 0 20 mld168 i g1 ( m a) v (v) g2 s 11 v 10 v 9 v 8 v 7 v v = 12 v gg fig.16 drain current as a function of the gate 2 voltage; typical values; see fig.26. v ds = 9 v. r g1 = 180 k w (connected to v gg ); t j = 25 c. handbook, halfpage 0 2 4 6 0 16 mld169 12 8 4 i d (ma) 8 v 7 v 6 v 5 v 4 v v = 9 v gg v (v) g2 s v ds = 12 v. r g1 = 250 k w (connected to v gg ); t j = 25 c. fig.17 drain current as a function of the gate 2 voltage; typical values; see fig.26. handbook, halfpage 0 2 4 6 0 16 mld170 12 8 4 i d (ma) 11 v 10 v 9 v 8 v 7 v v = 12 v gg v (v) g2 s
1995 apr 25 9 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR fig.18 input admittance as a function of frequency; typical values. v ds = 9 v; v g2 = 4 v. i d = 10 ma; t amb = 25 c. handbook, halfpage 10 3 mld181 10 2 10 10 1 10 2 10 1 y is (ms) f (mhz) b is g is v ds = 9 v; v g2 = 4 v. i d = 10 ma; t amb = 25 c. fig.19 reverse transfer admittance and phase as a function of frequency; typical values. 10 3 mld182 10 2 10 10 3 10 2 10 1 y rs 10 3 10 10 1 2 rs ( m s) f (mhz) rs y rs (deg) j j fig.20 forward transfer admittance and phase as a function of frequency; typical values. v ds = 9 v; v g2 = 4 v. i d = 10 ma; t amb = 25 c. 10 3 mld183 10 2 10 1 10 2 10 1 10 10 2 y fs (ms) y fs f (mhz) fs fs (deg) j j fig.21 output admittance as a function of frequency; typical values. v ds = 9 v; v g2 = 4 v. i d = 10 ma; t amb = 25 c. handbook, halfpage 10 3 mld184 10 2 10 10 1 10 1 10 2 y os (ms) f (mhz) b os g os
1995 apr 25 10 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR fig.22 input admittance as a function of frequency; typical values. v ds = 12 v; v g2 = 4 v. i d = 10 ma; t amb = 25 c. handbook, halfpage 10 3 mld185 10 2 10 10 1 10 2 10 1 y is (ms) f (mhz) b is g is v ds = 12 v; v g2 = 4 v. i d = 10 ma; t amb = 25 c. fig.23 reverse transfer admittance and phase as a function of frequency; typical values. 10 3 mld186 10 2 10 10 3 10 2 10 1 y rs 10 3 10 10 1 2 rs ( m s) f (mhz) rs y rs (deg) j j fig.24 forward transfer admittance and phase as a function of frequency; typical values. v ds = 12 v; v g2 = 4 v. i d = 10 ma; t amb = 25 c. 10 3 mld187 10 2 10 1 10 2 10 1 10 10 2 y fs (ms) y fs f (mhz) fs fs (deg) j j fig.25 output admittance as a function of frequency; typical values. v ds = 12 v; v g2 = 4 v. i d = 10 ma; t amb = 25 c. handbook, halfpage 10 3 mld188 10 2 10 10 1 10 1 10 2 y os (ms) f (mhz) b os g os
1995 apr 25 11 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR fig.26 cross-modulation test circuit. handbook, full pagewidth dut v agc c1 4.7 nf r1 10 k w mgc420 c4 4.7 nf l1 450 nh c3 12 pf r l 50 w ? v gg v ds r gen 50 v i r2 50 4.7 nf c2 r g w w for v gg = v ds = 9 v, r g = 180 k w . for v gg = v ds = 12 v, r g = 250 k w .
1995 apr 25 12 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR table 1 scattering parameters: v ds = 9 v; v g2-s = 4 v; i d = 10 ma table 2 noise data: v ds = 9 v; v g2-s = 4 v; i d = 10 ma table 3 scattering parameters: v ds = 12 v; v g2-s = 4 v; i d = 10 ma table 4 noise data: v ds = 12 v; v g2-s = 4 v; i d = 10 ma f (mhz) s 11 s 21 s 12 s 22 magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) 50 0.985 - 3.9 2.618 175.1 0.001 137.9 1.000 - 1.9 100 0.981 - 7.3 2.602 170.5 0.001 80.4 0.999 - 4.0 200 0.975 - 14.4 2.577 160.7 0.002 74.0 0.995 - 7.6 300 0.965 - 21.6 2.555 151.6 0.002 79.3 0.994 - 11.3 400 0.947 - 28.3 2.513 141.8 0.003 80.5 0.992 - 15.0 500 0.927 - 34.9 2.449 133.4 0.003 82.8 0.988 - 18.5 600 0.913 - 41.7 2.339 124.6 0.003 78.9 0.984 - 22.0 700 0.890 - 47.9 2.361 115.4 0.003 80.6 0.982 - 25.3 800 0.869 - 54.0 2.302 106.4 0.003 93.9 0.979 - 28.8 900 0.845 - 59.7 2.228 97.6 0.003 104.8 0.976 - 32.1 1000 0.823 - 65.4 2.167 89.6 0.003 129.3 0.974 - 35.5 f (mhz) f min (db) g opt r n (ratio) (deg) 800 2.00 0.67 43.9 0.89 f (mhz) s 11 s 21 s 12 s 22 magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) 50 0.985 - 3.7 2.576 175.3 0.000 125.0 1.000 - 1.6 100 0.980 - 7.4 2.563 170.9 0.001 111.2 1.000 - 3.3 200 0.973 - 14.6 2.541 161.6 0.002 83.0 0.997 - 6.4 300 0.962 - 21.5 2.519 152.9 0.002 85.2 0.996 - 9.3 400 0.946 - 28.5 2.479 143.5 0.003 79.4 0.995 - 12.4 500 0.929 - 35.0 2.419 135.5 0.003 78.2 0.991 - 15.3 600 0.912 - 41.6 2.373 127.2 0.003 80.0 0.989 - 18.1 700 0.895 - 47.8 2.336 118.7 0.003 83.4 0.987 - 20.9 800 0.868 - 53.8 2.284 110.0 0.003 91.3 0.985 - 23.7 900 0.845 - 59.8 2.213 101.6 0.003 95.9 0.983 - 26.5 1000 0.823 - 65.7 2.160 94.1 0.003 112.2 0.981 - 29.3 f (mhz) f min (db) g opt r n (ratio) (deg) 800 2.00 0.66 43.3 0.97
1995 apr 25 13 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR package outline fig.27 sot343r. dimensions in mm. 0.3 0.1 0.25 0.10 0.2 0.1 max 1.00 max msb367 1.4 1.2 2.2 1.8 b a 1.35 1.15 0.4 0.2 b m 0.2 a m 0.2 2.2 2.0 0.7 0.5 3 4 2 1
1995 apr 25 14 philips semiconductors product speci?cation dual-gate mos-fet BF1100WR definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
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