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vishay TFBS5614 document number 82617 rev. 1.1, 14-oct-03 vishay semiconductors www.vishay.com 1 18163 fast infrared transceiver module (mir, 1.152 mbit/s) for irda ? applications description the TFBS5614 transceiver is an infrared transceiver module compliant to the latest irda physical layer standard for fast infrared data communication, sup- porting irda speeds up to 1.152 mbit/s (mir), hp- sir ? , sharp ask ? and carrier based remote control modes up to 2 mhz. integrated within the transceiver module are a photo pin diode, an infrared emitter (ired), and a low-power control ic to provide a total front-end solution in a single package. this new vishay mir transceiver is built in a new smaller package using the experiences of the lead frame babyface technology. the transceivers are capable of directly interfacing with a wide variety of i/o devices, which perform the modulation/ demodu- lation function. at a minimum, a v cc bypass capacitor and a serial resistor for current control are the only external components required implementing a com- plete solution. TFBS5614 has a tri-state output and is floating in shut-down mode with a weak pull-up. features compliant to the latest irda physical layer specifi- cation (up to 1.152 mbit/s), hp-sir ? , sharp ask ? and tv remote control, bi-directional operation included. for 3.0 v and 5 v applications. operates from 2.7 v to 5.5 v within specification low power consumption (< 0.55 ma supply current in receive mode, no signal) power shutdown mode (< 5 a shutdown current in full temperature range, up to 85 c) surface mount package, low profile (2.7 mm) universal (8.0 2.7 3.3 mm 3 ) backward pin compatible to vishay transceivers as irm1030 and tfbs5615 high efficiency emitter low profile (universal) package capable of surface mount soldering to side and top view orientation directly interfaces with various super i/o and controller devices tri-state-receiver output, floating in shut down with a weak pull-up split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, us - patent no. 6,157,476 logic voltage 1.5 v to 5.5 v (optional at pin 6 on request) independent of ired driver and analog supply voltage only one external component required tv remote control supported applications telecommunication products (cellular phones, pagers) digital still and video cameras printers, fax machines, photocopiers, screen projectors medical and industrial data collection notebook computers, desktop pcs, palmtop computers (win ce, palm pc), pdas internet tv boxes, video conferencing systems external infrared adapters (dongles) kiosks, pos, point and pay devices including irfm - applications
www.vishay.com 2 document number 82617 rev. 1.1, 14-oct-03 vishay TFBS5614 vishay semiconductors parts table functional bloc k diagram pin description part description qty / reel TFBS5614-tr1 oriented in carrier tape for side view surface mounting 1000 pcs TFBS5614-tr3 oriented in carrier tape for side view surface mounting 2500 pcs 18149 ired driver push-pull driver gnd txd rxd vcc2 vcc1 amplifier sd v logic logic & control comparator pin number function description i/o active 1 v cc2 ired anode ired anode to be externally connected to v cc2 . an external resistor is necessary for controlling the ired current. this pin is allowed to be supplied from an uncontrolled power supply separated from the controlled v cc1 - supply 2 txd this schmitt-trigger input is used to transmit serial data when sd is low. an on-chip protection circui t disables the led driver if the txd pin is asserted for longer than 80 s. when used in conjunction with the sd pin, this pin is also used to control receiver output pulse duration. i high 3 rxd received data output, push-pull cmos driver output capable of driving standard cmos or ttl loads. no external pull-up or pull- down resistor is required. floating with a weak pull-up of 500 k ? (typ.) in shutdown mode. o low 4 sd shutdown, also used for setting the output pulse duration. setting this pin active for more than 1.5 ms places the module into shutdown mode. before that (t < 0.7 ms) on the falling edge of this signal, the state of the txd pin is sampled and used to set the receiver output to long pulse duration (2 s) or to short pulse duration (0.4 s) mode i high 5 v cc1 supply voltage 6 nc internally not connected i 7 gnd ground
vishay TFBS5614 document number 82617 rev. 1.1, 14-oct-03 vishay semiconductors www.vishay.com 3 pinout TFBS5614 weight 80 mg definitions: in the vishay transceiver data sheets the following nomenclature is used for defining the irda operating modes: sir: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version irphy 1.0 mir: 576 kbit/s to 1152 kbit/s fir: 4 mbit/s vfir: 16 mbit/s mir and fir were implemented with irphy 1.1, followed by irphy 1.2, adding the sir low power standard. irphy 1.3 extended the low power option to mir and fir and vfir was added with irphy 1.4.a new version of the standard in any case obsoletes the former version. with introducing the updated versions the old versions are obso- lete. therefore the only valid irda standard is the actual version irphy 1.4 (in oct. 2002). absolute maximum ratings reference point ground (pin 7) unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. 18165 parameter test conditions symbol min ty p. max unit supply voltage range, transceiver - 0.3 v < v cc2 < 6 v v cc1 - 0.3 + 6.0 v supply voltage range, transmitter - 0.5 v < v cc1 < 6 v v cc2 - 0.3 + 6.5 v input currents for all pins, except ired anode pin 10 ma output sinking current 25 ma power dissipation see derating curve p d 500 mw junction temperature t j 125 c ambient temperature range (operating) t amb - 25 + 85 c storage temperature range t stg - 25 + 85 c soldering temperature see recommended solder profile 240 c average output current, pin 1 i ired(dc) 125 ma repetitive pulsed output current, pin 1 t < 90 s, t on < 20 % i ired(rp) 600 ma ired anode voltage, pin 1 v ireda - 0.5 + 6.5 v voltage at all inputs and outputs v in < v cc1 is allowed v in - 0.5 + 5.5 v load at mode pin when used as mode indicator 50 pf
www.vishay.com 4 document number 82617 rev. 1.1, 14-oct-03 vishay TFBS5614 vishay semiconductors eye safety information *) due to the internal limitation meas ures the device is a "class 1" device. **) irda specifies the max. intensity with 500 mw/sr. electrical characteristics transceiver t amb = 25 c, v cc1 = v cc2 = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) standard illuminant a **) the typical threshold level is 0.5 x v cc1 . it is recommended to use the specified min/ma x values to avoid increased operating current. parameter test conditions symbol min ty p. max unit virtual source size method: (1-1/e) encircled energy d 1.8 2.0 mm maximum intensity for class 1 iec60825-1 or en60825-1, edition jan. 2001, operating below the absolute maximum ratings i e *) (500) **) mw/sr parameter test conditions symbol min ty p. max unit supply voltage v cc1 2.7 5.5 v dynamic supply current sd = low, e e = 1 klx i cc 550 900 a average dynamic supply current, transmitting i ired = 500 ma, 25 % duty cycle i cc 1100 1500 a standby supply current sd = high, t = 25 c, e e = 0 klx i sd 1 a sd = high, t = 25 c, e e = 1 klx *) i sd 2.5 a sd = high, t = 85 c, not ambient light sensitive i sd 5 a operating temperature range t a - 25 + 85 c output voltage low, rxd c load = 15 pf, i ol = 1 ma v ol 0.4 v output voltage high, rxd i oh = - 500 a v oh 0.8 x v cc1 v i oh = - 250 a, c load = 15 pf v oh 0.9 x v cc1 v rxd to v cc1 impedance r rxd 400 500 600 k ? input voltage low (txd, sd) v il - 0.5 0.5 v input voltage high (txd, sd) cmos level **) v ih v cc1 - 0.5 v cc1 + 0.5 v input leakage current (txd, sd) v in = 0.9 x v cc1 i ich - 2 + 2 a controlled pull down current sd, txd = "0" to "1", 0 < v in < 0.15 v cc1 i irtx + 150 a sd, txd = "0" to "1", v in > 0.7 v cc1 i irtx - 1 0 1 a input capacitance (txd, sd) c i 5 pf
vishay TFBS5614 document number 82617 rev. 1.1, 14-oct-03 vishay semiconductors www.vishay.com 5 optoelectronic characteristics receiver t amb = 25 c, v cc1 = v cc2 = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) some endecs are not able to decode shor t pulses as valid sir pulses. therefore this additional mode was added in tfdu5307. tfdu5307 is set to the "short output pulse" as default after power on, also after recovering from the shutdown mode (sd must ha ve been longer active than 1.5 ms). for mode changing see the chapt er "programming" parameter test conditions symbol min ty p. max unit minimum detection threshold irradiance, sir mode 9.6 kbit/s to 1152 kbit/s = 850 nm - 900 nm e e 40 (4) 90 (9) mw/m 2 ( w/cm 2) maximum detection threshold irradiance = 850 nm - 900 nm e e 5 (500) kw/m 2 (mw/cm 2 ) logic low receiver input irradiance e e 4 (0.4) mw/m 2 ( w/cm 2) rise time of output signal 10 % to 90 %, c l = 15 pf t r(rxd) 20 60 ns fall time of output signal 90 % to 10 %, c l = 15 pf t f(rxd) 20 60 ns rxd pulse width of output signal, default mode after power on input pulse length t pwopt > 0.140 s t pw 300 400 500 ns sir endec compatibility mode *) : rxd pulse width of output signal input pulse length 0.140 s < t pwopt , see chapter "programming" t pw 1.7 2.0 2.2 s stochastic jitter, leading edge input irradiance = 100 mw/m 2 , 1.152 mbit/s, 576 kbit/s 80 ns input irradiance = 100 mw/m 2 , 115.2 kbit/s 350 ns standby /shutdown delay after shutdown active or (sd low to high transition) 0.6 1.5 ms shutdown active time window for programming during this time the pulse duration of the output can be programmed to the application mode. see chapter "programming" 600 s receiver start up time power on delay shutdown recovery delay after shutdown inactive (sd high to low transition) and after power-on 300 s latency t l 200 s
www.vishay.com 6 document number 82617 rev. 1.1, 14-oct-03 vishay TFBS5614 vishay semiconductors transmitter t amb = 25 c, v cc1 = v cc2 = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) note: due to this wavelength restriction compared to the irda s pec of 850 nm to 900 nm the transmitter is able to operate as s ource for the standard remote control applications with codes as e.g. phillips rc5/rc6 ? or recs 80. when operat ed under irda full range con- ditions >110 mw/sr) the rc range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used. parameter test conditions symbol min ty p. max unit ired operating current, recommended serial resistor for mir applications v cc2 = 3.3 v: r s = 2.0 ? v cc2 = 5.0 v: r s = 5.6 ? i d 400 500 ma output leakage ired current txd = 0 v, 0 < v cc1 < 5.5 v i ired - 1 1 a output radiant intensity recommended application circuit, see figure 1 = 0 , 15 txd = high, sd = low i e 150 mw/sr output radiant intensity v cc1 = 5.0 v, = 0 , 15 txd = low or sd = high (receiver is inactive as long as sd = high) i e 0.04 mw/sr output radiant intensity, angle of half intensity 24 peak - emission wavelength *) p 880 900 nm spectral bandwidth ? 45 nm optical rise time, fall time t ropt , t fopt 10 40 ns optical output pulse duration input pulse width 217 ns, 1.152 mbit/s t opt 200 217 240 ns input pulse width t txd < 80 s t opt 20 t txd s input pulse width t txd 80 s t opt 20 85 s optical overshoot 25 %
vishay TFBS5614 document number 82617 rev. 1.1, 14-oct-03 vishay semiconductors www.vishay.com 7 recommended circuit diagram used with a clean low impedance power supply the TFBS5614 only needs an external series current lim- iting resistor. however, depending on the entire sys- tem design and board layout, additional external components may be required (see figure 1). the capacitor c1 is buffering the supply voltage and eliminates the inductance of the power supply line. this one should be a tantalum or other fast capacitor to guarantee the fast rise time of the ired current. the resistor r1 is the current limiting resistor and this is supply voltage dependent, see derating curve in fig- ure 4, to avoid too high internal power dissipation. vishay?s transceivers integrate a sensitive receiver and a built-in power driver. the combination of both needs a careful circuit board layout. the use of thin, long, resistive and inductive wiring should be avoided. the inputs (txd, sd) and the output rxd should be directly (dc) coupled to the i/o circuit. the capacitor c2 combined with the resistor r2 is the low pass filter for smoothing the supply voltage. r2, c1 and c2 are optional and dependent on the quality of the supply voltages v ccx and injected noise. an unstable power supply with dropping volt- age during transmission may reduce the sensitivity (and transmission range) of the transceiver. the placement of these parts is critical. it is strongly recommended to position c2 as close as possible to the transceiver power supply pins. an tantalum capacitor should be used for c1 while a ceramic capacitor is used for c2. in addition, when connecting the described circuit to the power supply, low impedance wiring should be used. when extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at v cc2 . often some power supplies are not apply to follow the fast current rise time. in that case another 4.7 f (type, see table under c1) at v cc2 will be help- ful. under extreme emi conditions as placing an rf- transmitter antenna on top of the transceiver, we rec- ommend to protect all inputs by a low-pass filter, as a minimum a 12 pf capacitor, especially at the rxd port. keep in mind that basic rf - design rules for circuit design should be taken into account. especially longer signal lines should not be used without termi- nation. see e.g. "the art of electronics" paul horow- itz, winfield hill, 1989, cambridge university press, isbn: 0521370957. table 1. recommended application circuit components figure 1. recommended application circuit ired anode v cc ground sd txd rxd v ired v cc gnd sd txd rxd r1 r2 c1 c2 18147 v logic v logic ired cathode component recommended value vishay part number c1 4.7 f, 16 v 293d 475x9 016b c2 0.1 f, c e r a m i c vj 1206 y 104 j xxmt r1 5 v supply voltage: 5.6 ? s. text 0.25 w (recommended using two 2.8 ? , 0.125 w resistors in series). 3.3 v supply voltage: 2.0 ? s. text 0.25 w e.g. 2 x crcw-1206-2r0-f-rt1 for 3.3 v supply voltage r2 47 ? , 0.125 w crcw-1206-47r0-f-rt1
www.vishay.com 8 document number 82617 rev. 1.1, 14-oct-03 vishay TFBS5614 vishay semiconductors i/o and software in the description, already different i/os are men- tioned. different combinations are tested and the function verified with the special drivers available from the i/o suppliers. in special cases refer to the i/ o manual, the vishay application notes, or contact directly vishay sales, marketing or application. programming pulse duration switching after power-on the TFBS5614 is in the default short rxd pulse duration mode. some endecs are not able to decode short pulses as valid sir pulses. therefore an additional mode with extended pulse duration (same as in standard sir transceivers) is added in TFBS5614. TFBS5614 is set to the "short output pulse" as default after power on, and after recovering from the shutdown mode (sd being active longer than 1.5 ms). to switch the transceivers from the short rxd pulse duration mode to the long pulse duration mode and vice versa, follow the procedure described below. setting to the endec compatibility mode with an rxd pulse duration of 2 s 1. set sd input to logic "high". 2. set txd input to logic "high". wait t s 200 ns. 3. set sd to logic "low" (this negative edge latches state of txd, which determines speed setting). 4. after waiting t h 200 ns. after that txd is enabled as normal txd input and the rxd output is set for the longer rxd - pulse duration mode. setting back to the default mode with a 400 ns pulse duration 1. set sd input to logic "high". 2. set txd input to logic "low". wait t s 200 ns. 3. set sd to logic "low" (this negative edge latches state of txd, which determines speed setting). 4. after waiting t h 200 ns txd can be set to logic "low". the hold time of txd is limited by the maxi- mum allowed pulse length. after that txd is now enabled as normal txd input and the rxd output is set for the short rxd - pulse duration mode. the timing of the pulse duration changing procedure is quite uncritical. however, the whole change must not take more than 600 s. see in the spec. "shut- down active time window for programming" simplified method setting the device to the long pulse duration is simply applying a short active (less than 600 s) pulse to sd. in any case a short sd pulse will force the device to leave the default mode and go the compatibility mode. vice versa applying a 1.5 ms (minimum) pulse at sd will cause the device to go back to the default mode by activating a power-on-reset and setting the device to the default short pulse mode. this simplified method takes more time but may be easier to handle. figure 2. timing diagram for changing the output pulse duration sd 50% t s t h high: txd 50% 50% 18150 low: 400 ns 2 s
vishay TFBS5614 document number 82617 rev. 1.1, 14-oct-03 vishay semiconductors www.vishay.com 9 table 2. truth table dry packing the reel is packed in a moisture proof aluminum bag to protect the device from absorbing moisture during transportation and storage. recommended method of storage dry box storage is recommended as soon as the dry bag has been opened to prevent moisture absorption. the following conditions should be observed, if dry boxes are not available: acc. to jedec standard jesd22-a113 inputs outputs remark sd txd optical input irradiance mw/m 2 rxd transmitter operation high < 600 s x x weakly pulled (500 k ? ) to v cc1 0 time window for pulse duration setting high > 1.5 ms x x weakly pulled (500 k ? ) to v cc1 0 shutdown low high x high inactive i e transmitting low high > 80 s x high inactive 0 protection is active low low < 4 high inactive 0 ignoring low signals below the irda defined threshold for noise immunity low low > min. detection threshold irradiance < max. detection threshold irradiance low (active) 0 response to an irda compliant optical input signal low low > max. detection threshold irradiance undefined 0 overload conditions can cause unexpected outputs reel aluminiumbag moisture level sticker 0 barcode label esd sticker 18298 level caution this bag contains moisture ?sensitive devices 1. shelf life in sealed bag 12 months at <40c and < 90% relative humidity (rh) 2. after this bag is opened devices that will be subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temp. 220c) must be: 2a.mounted within 72 hours at factory condition of < 30c/60%rh or 2b.stored at <20% rh. 3. devices require baking before mounting if: humidity indicator card is >20% when read at 23c + 5c or 2a or 2b is not met. 4. if baking is required, devices may be baked for: 192 hours at 40c + 5c/-0c and <5%rh (dry air/nitrogen) or 96 hours at 605 o cand <5%rh for all device containers or 24 hours at 1255c not suitable for reels or tubes bag seal date: ______________________________ (if blank, see bar code label) note: level defined by eia jedec standard jesd22-a113 4 18299
www.vishay.com 10 document number 82617 rev. 1.1, 14-oct-03 vishay TFBS5614 vishay semiconductors recommended solder profile current derating diagram figure 4 shows the maximum operating temperature when the device is operated without external current limiting resistor. a minimum resistor of 2 ohms is rec- ommended from the anode of the ired to v cc . for other conditions see package drawing. figure 3. recommended solder profile figure 4. temperature derating diagram time(s) temperature ( c ) 14874 0 20 40 60 80 100 120 140 160 180 200 220 240 0 50 100 150 200 250 300 350 2 c-4 c/s 10 s max. @230 c 90 s max 120 s - 180 s 2 c-4 c/s 50 55 60 65 70 75 80 85 90 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 operating voltage [v] @ duty cycle 20% ambient temperature ( c) 18097 figure 5. intensity i e vs. current control resistor r2, 5 v applications figure 6. intensity i e vs. current control resistor r1, 3 v applications 0 100 200 300 400 500 0246810121416 current control resistor ( ) 14379 intensity (mw/sr) min. intensity in emission cone 15 max.r dson , max.v f max. intensity in emission cone 15 v cc =4.75v min. r dson , min. v f 5.0v 5.0v 5.25v 0 100 200 300 400 500 600 700 024681012 current control resistor ( ) 15111 intensity (mw/sr) emission cone 15 v cc =3.0v min. r dson , min. v f 3.3v 3.3v 3.6v max. intensity in emission cone 15 max. r dson , max. v f min. intensity in
vishay TFBS5614 document number 82617 rev. 1.1, 14-oct-03 vishay semiconductors www.vishay.com 11 package dimensions in mm 16963
www.vishay.com 12 document number 82617 rev. 1.1, 14-oct-03 vishay TFBS5614 vishay semiconductors reel dimensions 14017 w 1 w 2 reel hub tape width a max. n w 1 min. w 2 max. w 3 min. w 3 max. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4
vishay TFBS5614 document number 82617 rev. 1.1, 14-oct-03 vishay semiconductors www.vishay.com 13 tape dimensions in mm 18297
www.vishay.com 14 document number 82617 rev. 1.1, 14-oct-03 vishay TFBS5614 vishay semiconductors ozone depleting substances policy statement it is the policy of vishay semiconductor gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol (1987) and its london amendments (1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. vishay semiconductor gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. vishay semiconductor gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice. parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use vishay semiconductors products for any unintended or unauthorized application, the buyer shall indemnify vishay semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. vishay semiconductor gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2831, fax number: 49 (0)7131 67 2423

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