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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. document no. u12627ej3v0ds00 (3rd edition) date published september 2000 j cp(k) printed in japan 8-bit single-chip microcontroller data sheet mos integrated circuit m m m m pd789800 the mark shows major revised points. ? 1997, 2000 the m pd789800 is a 78k/0s series product designed for a usb keyboard (for assp). the m pd789800 has on-chip hardware compatible with a usb keyboard, including usb (universal serial bus) functions, a regulator which powers a usb driver/receiver, and a key return signal detection circuit. the m pd78f9801, a product with on-chip flash memory which can operate on the same supply voltage as for masked rom products and various development tools are also available. detailed descriptions of its functions, etc., are given in the following user's manuals. be sure to read them for design purposes. m m m m pd789800 sub-series user's manual : u12978e 78k/0s series user's manual, instruction : u11047e features on-chip usb functions implements a usb (universal serial bus) by connecting to hub and host. transfer speed: 1.5 mbps (when the system clock operates at 6.0 mhz) on-chip regulator controls the usb port voltage by using a bus power supply (v reg = 3.3 0.3 v) dedicated to the usb driver/receiver. on-chip rom and ram internal rom : 8k bytes internal high-speed ram : 256 bytes minimum instruction execution time can be switched between high speed (0.33 m s) and low speed (1.33 m s) (when the system clock operates at 6.0 mhz). i/o port: 31 serial interface: 2 channels usb function : 1 channel three-wire serial i/o mode : 1 channel timer: 3 channels 8-bit timer : 1 channel 8-bit timer/event counter: 1 channel watchdog timer : 1 channel on-chip key return signal detection circuit supply voltage: v dd = 4.0 to 5.5 v operating ambient temperature : t a = -40 c to +85 c (when the usb is not operating) t a = 0 c to +70 c (when the usb is operating)
data sheet u12627ej3v0ds00 2 m m m m pd789800 applications usb keyboards, etc. ordering information part number package m pd789800gb- -3bs-mtx 44-pin plastic qfp (10 10) m pd789800gb- -8es 44-pin plastic lqfp (10 10) remark indicates rom code suffix.
data sheet u12627ej3v0ds00 3 m m m m pd789800 78k/0s series development the 78k/0s series products are shown below. the sub-series names are indicated in frames. 78k/0s series small-scale package, general-purpose applications small-scale package, general-purpose applications and a/d function inverter control lcd drive assp 44-pin 44-pin 42-/44-pin 28-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin 44-pin products in mass production products under development y subseries supports smb. pd789014 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 44-pin 44-pin 20-pin 20-pin m pd789026 m pd789046 pd789074 with subsystem clock pd789014 with enhanced timer function and expanded rom and ram on-chip uart and capable of low-voltage (1.8 v) operation pd789167 with enhanced a/d converter pd789104a with enhanced timer pd789146 with enhanced a/d converter pd789104a with eeprom added pd789124a with enhanced a/d rc oscillation version of pd789104a pd789104a with enhanced a/d converter pd789026 with a/d converter and multiplier a/d converter and internal voltage boosting method lcd (28 4) pd789407a with enhanced a/d converter pd789446 with enhanced a/d converter pd789426 with enhanced a/d converter a/d converter and internal voltage boosting method lcd (5 4) rc oscillation version of pd789306 for pc keyboard. on-chip usb function for key pad. on-chip poc rc oscillation version of pd789860 for keyless entry. on-chip poc and key return circuit on-chip inverter controller and uart m pd789104a m pd789114a m pd789842 m pd789124a m pd789134a m pd789146 m pd789156 m pd789167 m pd789177 m pd789316 m pd789426 m pd789436 m pd789446 m pd789860 m pd789861 m pd789840 m pd789800 m pd789456 m pd789407a m pd789167y m pd789177y m m m m m m m m m m m a/d converter and resistance division method lcd (28 4) m m m m pd789417a m pd789488 m 88-pin segment: 40 pins, common: 16 pins pd789830 m 144-pin segment/common outputs: 96 pins pd789835 m dot lcd drive 52-pin 52-pin for remote controller. on-chip sio and resistance division method lcd pd789327 m pd789467 m for remote controller. on-chip a/d converter and internal voltage boosting method lcd 30-pin pd789074 m pd789026 with enhanced timer function m a/d converter and internal voltage boosting method lcd (15 4) m pd789306 m internal voltage boosting method lcd (24 4) 64-pin 80-pin pd789477 m pd789488 with remote controller receive circuit added and resistance division method lcd m vfd drive 52-pin total of display outputs: 25 pd789871 m tm
data sheet u12627ej3v0ds00 4 m m m m pd789800 the major functional differences among the subseries are listed below. v dd rom capacity 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min value remark m pd789046 16 k 1 ch m pd789026 4 k to 16 k 34 m pd789074 2 k to 8 k 1 ch 1 ch 24 small scale, general- purpose applica- tions m pd789014 2 k to 4 k 2 ch - - -- 1 ch (uart: 1 ch) 22 - m pd789177 - 8 ch m pd789167 16 k to 24 k 3 ch 1 ch 8 ch - 31 - m pd789156 - 4 ch m pd789146 8 k to 16 k 4 ch - on-chip eeprom m pd789134a 4 ch m pd789124a 4 ch - rc oscillation version m pd789114a - 4 ch small- scale, general- purpose applica- tions + a/d function m pd789104a 2 k to 8 k 1 ch 1 ch - 1 ch 4 ch - 1 ch (uart: 1 ch) 20 1.8 v - inverter control m pd789842 8 k to 16 k 3 ch note 1 ch 1 ch 8 ch - 1 ch (uart: 1 ch) 30 4.0 v - vfd drive m pd789871 4 k to 8 k 3 ch - 1 ch 1 ch -- 1 ch 33 2.7 v - m pd789488 32 k 8 ch 2 ch (uart: 1 ch) 45 m pd789417a - 7 ch m pd789407a 12 k to 24 k 3 ch 7 ch - 43 m pd789456 - 6 ch m pd789446 6 ch - 30 m pd789436 - 6 ch m pd789426 12 k to 16 k 6 ch 1 ch (uart: 1 ch) 40 - m pd789316 rc oscillation version lcd drive m pd789306 8 k to 16 k 2 ch 1 ch 1 ch 1 ch - - 2 ch (uart: 1 ch) 23 1.8 v - m pd789835 24 k to 60 k 6 ch - 3 ch 28 1.8 v dot lcd drive m pd789830 24 k 1 ch 1 ch 1 ch 1 ch - - 1 ch (uart: 1 ch) 30 2.7 v - m pd789477 24 k 3 ch 1 ch 8 ch 2 ch (uart: 1 ch) 45 m pd789467 1 ch - 18 m pd789327 4 k to 24 k 1 ch 1 ch 21 1.8 v on-chip lcd m pd789800 - 2 ch (usb: 1 ch) 31 4.0 v m pd789840 8 k 4 ch 1 ch 29 2.8 v - m pd789861 rc oscillation version, on- chip eeprom assp m pd789860 4 k 2 ch - - 1 ch - - - 14 1.8 v on-chip eeprom note 10-bit timer: 1 channel function subseries name
data sheet u12627ej3v0ds00 5 m m m m pd789800 functions item function rom 8k bytes internal memory high-speed ram 256 bytes minimum instruction execution time 0.33 m s/1.33 m s (when the system clock operates at 6.0 mhz) general-purpose register 8 bits 8 registers instruction set ? 16-bit operation ? bit manipulation (set, reset, and test) etc. i/o ports cmos i/o: 31 pins (of these, 18 pins can be switched to n-ch open-drain i/o pins.) serial interface ? usb (universal serial bus) function : 1 channel ? three-wire serial i/o mode : 1 channel timer ? 8-bit timer : 1 channel ? 8-bit timer/event counter : 1 channel ? watchdog timer : 1 channel regulator incorporated (v reg = 3.3 0.3 v) maskable internal: 9, external: 2 vector interrupt source nonmaskable internal: 1 power supply voltage v dd = 4.0 to 5.5 v operating ambient temperature ? t a = -40c to + 85c (when the usb is not operating) ?t a = 0c to + 70c (when the usb is operating) package ? 44-pin plastic qfp (10 10) ? 44-pin plastic lqfp (10 10)
data sheet u12627ej3v0ds00 6 m m m m pd789800 contents 1. pin configuration (top view) ................................................................................................7 2. block diagram ................................................................................................................ ............8 3. pin functions ................................................................................................................ ...............9 3.1 port pins................................................................................................................... .............................. 9 3.2 non-port pins............................................................................................................... ......................... 10 3.3 pin input/output circuits and handling of unused pins .................................................................. 11 4. memory space ................................................................................................................. ...........13 5. peripheral hardware functions ......................................................................................14 5.1 ports ....................................................................................................................... ............................... 14 5.2 clock generator............................................................................................................. ....................... 14 5.3 timer....................................................................................................................... ............................... 15 5.4 serial interface............................................................................................................ .......................... 16 5.5 regulator................................................................................................................... ............................ 18 5.6 key return signal detection circuit ......................................................................................... .......... 19 6. interrupt function........................................................................................................... .......21 7. standby function ............................................................................................................. ........23 8. reset function ............................................................................................................... ...........23 9. instruction set overview ..................................................................................................... 24 9.1 legend...................................................................................................................... ............................. 24 9.2 operations.................................................................................................................. ........................... 26 10. electrical characteristics................................................................................................31 11. package drawings ............................................................................................................ .......39 12. recommended soldering conditions...............................................................................41 appendix a development tools...............................................................................................42 appendix b related documents ..............................................................................................44
data sheet u12627ej3v0ds00 7 m m m m pd789800 1. pin configuration (top view) 44-pin plastic qfp (10 10) m pd789800gb- -3bs-mtx 44-pin plastic lqfp (10 10) m pd789800gb- -8es p04 p03 p02 p01 p00 v dd1 v ss1 p17 p16 p15 p14 nc p13 p12 p11 p10 usbdp usbdm ic regc v dd0 v ss0 x1 x2 reset p40/kr00 p41/kr01 p05 p06 p07 p20/sck10 p21/so10 p22/si10 p23 nc p24 p25 p26/ti01/to01/intp0 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 p47/kr07 p46/kr06 p45/kr05 p44/kr04 p43/kr03 p42/kr02 caution connect the ic (internally connected) pin directly to the v ss0 or v ss1 pin. ic : internally connected sck10 : serial clock input/output intp0 : interrupt from peripherals si10 : serial data input kr00 - kr07 : key return so10 : serial data output nc : no connection ti01 : timer input p00-p07 : port 0 to01 : timer output p10-p17 : port 1 usbdm, usbdp : universal serial bus data p20-p26 : port 2 v dd0 , v dd1 : power supply p40-p47 : port 4 v ss0 , v ss1 : ground reset : reset x1, x2 : crystal regc : voltage regulator for usb function
data sheet u12627ej3v0ds00 8 m m m m pd789800 2. block diagram key return0 8-bit timer00 8-bit timer/ event counter01 watchdog timer regulator usb function0 serial interface10 interrupt control port 0 port 1 port 2 port 4 system control 78k/0s cpu core rom ram p00-p07 p10-p17 p20-p26 p40-p47 reset x1 x2 kr00/p40-kr07/p47 ti01/to01/p26 regc usbdm usbdp intp0/p26 sck10/p20 so10/p21 si10/p22 v dd0 v dd1 v ss0 v ss1 ic v reg
data sheet u12627ej3v0ds00 9 m m m m pd789800 3. pin functions 3.1 port pins pin name i/o function when reset also used as p00-p07 i/o port 0 8-bit input/output port input or output is specifiable bit by bit. when used as an input port, the use of on-chip pull-up resistors can be specified by software. cmos output or n-ch open-drain output is specifiable in 8-bit units. input - p10-p17 i/o port 1 8-bit input/output port input or output is specifiable bit by bit. when used as an input port, the use of on-chip pull-up resistors can be specified by software. cmos output or n-ch open-drain output is specifiable in 8-bit units. input - p20 sck10 p21 so10 p22 si10 p23-p25 - p26 i/o port 2 7-bit input/output port input or output is specifiable bit by bit. when used as an input port, the use of on-chip pull-up resistors can be specified by software. only for p25 and p26, cmos output or n-ch open-drain output is specifiable bit by bit. input intp0/ti01/to01 p40-p47 i/o port 4 8-bit input/output port input or output is specifiable bit by bit. when used as an input port, the use of on-chip pull-up resistors can be specified by software. input kr00 - kr07
data sheet u12627ej3v0ds00 10 m m m m pd789800 3.2 non-port pins pin name i/o function when reset also used as intp0 input external interrupt request input for which effective edges (rising and/or falling edges) can be specified input p26/ti01/to01 kr00 - kr07 input input for detecting key return signals input p40-p47 regc - internally generated power supply for driving usb driver/receiver. connect this pin to v ss through a 220- w resistor and a 0.1- m f capacitor. -- reset input system reset input input - sck10 i/o serial clock input/output for serial interface input p20 si10 input serial data input for serial interface input p22 so10 output serial data output for serial interface input p21 ti01 input external count clock input to 8-bit timer/event counter 01 input p26/intp0/to01 to01 output timer output from 8-bit timer/event counter 01 input p26/intp0/ti01 usbdm i/o serial data input/output (negative side) for usb function. the pull-up resistor (1.5 k w ) for the usbdm pin must be connected to the regc pin. input - usbdp i/o serial data input/output (positive side) for usb function input - x1 input input x2 - connected to crystal for system clock oscillator - - v dd0 - positive supply voltage for ports - - v dd1 - positive supply voltage for circuits other than ports - - v ss0 - ground potential for ports - - v ss1 - ground potential for circuits other than ports - - ic - internally connected. connect this pin directly to v ss0 .- - nc - not internally connected. leave this pin open. - -
data sheet u12627ej3v0ds00 11 m m m m pd789800 3.3 pin input/output circuits and handling of unused pins table 3-1 lists the types of input/output circuits for each pin and explains how unused pins are handled. figure 3-1 shows the configuration of each type of input/output circuit. table 3-1. type of input/output circuit for each pin pin name i/o circuit type i/o recommended connection of unused pins p00-p07 p10-p17 5-r p20/ sck10 p21/so10 p22/si10 p23, p24 8-c p25 p26/intp0/ti01/to01 8-f p40/ kr00 -p47/ kr07 8-c input : connect these pins separately to v dd0 , v dd1 , v ss0 , or v ss1 via respective resistors. output : leave these pins open. usbdm connect this pin to the regc pin. usbdp 24-a i/o connect this pin to v ss0 or v ss1 via resistors. reset 2 input - ic - - connect this pin directly to v ss0 or v ss1 . nc - - leave this pin open. regc - - connect this pin to the usbdm pin.
data sheet u12627ej3v0ds00 12 m m m m pd789800 figure 3-1. pin input/output circuits type 2 type 5-r type 8-f type 24-a type 8-c in schmitt trigger input with hysteresis pull-up enable p-ch cut output data output disable v dd0 v dd0 p-ch n-ch in/out p-ch input enable v ss0 v dd0 p-ch in/out p-ch v dd0 pull-up enable output disable output data n-ch v ss0 pull-up enable p-ch cut output data output disable v dd0 v dd0 p-ch n-ch in/out p-ch v ss0 v ss0 txdxp rxdx txdxn v reg p-ch n-ch in/out
data sheet u12627ej3v0ds00 13 m m m m pd789800 4. memory space figure 4-1 shows the memory map of the m pd789800. figure 4-1. memory map special function register 256 8 bits internal high-speed ram 256 8 bits unusable program area callt table area program area vector table area internal rom 8,192 8 bits data memory space program memory space ffffh ff00h feffh fe00h fdffh 2000h 1fffh 0000h 0000h 001ah 0019h 0040h 003fh 1fffh 007fh 0080h
data sheet u12627ej3v0ds00 14 m m m m pd789800 5. peripheral hardware functions 5.1 ports i/o ports are listed below. cmos input/output ports (ports 0 to 2 and port 4): 31 pins of these, 18 pins (pins of ports 0 and 1, p25, and p26) can be switched to n-ch open-drain input/output pins. table 5-1. port functions name pin name function port 0 p00-p07 input/output port. input or output is specifiable bit by bit. when used as an input port, the use of on-chip pull-up resistors can be specified by software. cmos output or n-ch open-drain output is specifiable in 8-bit units. port 1 p10-p17 input/output port. input or output is specifiable bit by bit. when used as an input port, the use of on-chip pull-up resistors can be specified by software. cmos output or n-ch open-drain output is specifiable in 8-bit units. p20-p24 input/output port. input or output is specifiable bit by bit. when used as an input port, the use of on-chip pull-up resistors can be specified by software. port 2 p25, p26 input/output port. input or output is specifiable bit by bit. when used as an input port, the use of on-chip pull-up resistors can be specified by software. only for p25 and p26, cmos output or n-ch open-drain output is specifiable. port 4 p40-p47 input/output port. input or output is specifiable bit by bit. when used as an input port, the use of on-chip pull-up resistors can be specified by software. 5.2 clock generator the m pd789800 has an on-chip system clock generator. it is possible to change the minimum instruction execution time. 0.33 m s/ 1.33 m s (when the system clock operates at 6.0 mhz) figure 5-1. block diagram of clock generator x1 system clock oscillator f x prescaler f x 2 2 prescaler clock to peripheral hardware cpu clock (f cpu ) standby control circuit wait control circuit selector stop x2
data sheet u12627ej3v0ds00 15 m m m m pd789800 5.3 timer the m pd789800 has three on-chip timers. 8-bit timer 00 : 1 channel 8-bit timer/event counter 01 : 1 channel watchdog timer : 1 channel table 5-2. timer operation 8-bit timer 00 8-bit timer/event counter 01 watc hdog timer interval timer 1 channel 1 channel 1 channel operation mode external event counter - 1 channel - timer output - 1 output - square wave output - 1 output - function interrupt request 1 1 1 figure 5-2. block diagram of 8-bit timer 00 internal bus 8-bit compare register 00 (cr00) match selector inttm00 f x /2 6 f x /2 9 clear 8-bit timer counter 00 (tm00) internal bus
data sheet u12627ej3v0ds00 16 m m m m pd789800 figure 5-3. block diagram of 8-bit timer/event counter 01 internal bus 8-bit compare register 01 (cr01) match selector inttm01 f x /2 4 f x /2 8 clear 8-bit timer counter 01 (tm01) internal bus ti01/p26/ intp0/to01 output control circuit to01/p26/intp0/ ti01 figure 5-4. block diagram of watchdog timer prescaler f x 2 6 f x 2 8 f x 2 10 selector 7-bit counter run control circuit clear f x 2 4 intwdt maskable interrupt request reset intwdt nonmaskable interrupt request 5.4 serial interface two channels of serial interface are on chip. usb function the m pd789800 supports 1.5 mbps transfer speed with the system clock of 6.0 mhz and incorporates an nrzi (non return zero invert) decode/encode function, bit stuffing function, and crc (cyclic redundancy check) function specified by the usb (universal serial bus) communication protocol. figure 5-5 shows a block diagram. serial interface 10 (sio10) sio10 has the following two modes: operation stop mode three-wire serial i/o mode (the first bit can be switched between the msb and lsb.) figure 5-6 shows a block diagram.
data sheet u12627ej3v0ds00 17 m m m m pd789800 figure 5-5. block diagram of usb function internal bus internal bus usbdp usbdm each handshake packet sync packet usb clock overflow intusbtm f x intusbrd start usb receiver enable register (usbmod) counter transmit reservation registers (htxrsv, dtxrsv) transmit/receive pointers (usbpob, usbpow) remote wake-up control register (remwup) eop generation/detection resume & reset detection control sync detection/usb clock generator usb timer (7-bit counter) usb timer start reservation control register (usbtcl) receive result storage register (drxrsl) packet receive status register (rxstat) crc circuit endp detection circuit compare register receive buffer transmit buffer bit stuff/bit strip control circuit receive bank switching id detection buffer nrzi encoder output latch selector data/handshake packet receive mode register (urxmod)
data sheet u12627ej3v0ds00 18 m m m m pd789800 figure 5-6. block diagram of serial interface 10 internal bus serial i/o shift register 10 (sio10) f x /2 2 f x /2 3 si10/p22 so10/p21 serial clock counter sck10/p20 serial clock control circuit interrupt request signal generator intcsi10 selector selector 5.5 regulator the m pd789800 incorporates a regulator which powers the usb driver/receiver. the features are as follows: generates v reg (3.3 0.3 v) from v dd0 and v dd1 (4.0 to 5.5 v) and outputs it to the regc pin. supports power-saving mode, reducing current dissipation during stop mode. figure 5-7. block diagram of the regulator and usb driver/receiver regulator pd789800 m m usb driver/ receiver rxd sep sem txdp txdm txen rxen v dd0 v ss0 v reg v dd0 v ss0 usbdm hub regc v ss 0.1 f 1.5 k w usbdp 220 w cautions 1. to settle the v reg voltage, connect the regc pin to v ss via a 220- w w w w resistor and a 0.1- m m m m f capacitor. 2. connect the pull-up resistor (1.5 k w w w w ), for the usbdm pin, to the regc pin.
data sheet u12627ej3v0ds00 19 m m m m pd789800 5.6 key return signal detection circuit the m pd789800 incorporates the key return signal detection circuit that can detect the key return signals input to the p40/kr00-p47/kr07 pins. specify whether to detect the key return signals at the p40/kr00-p47/kr07 pins by means of key return mode register 00 (krm00). inhibit interrupts before setting krm00 (see caution 3 ). krm00 is set by a 1-bit memory operation instruction or an 8-bit memory operation instruction. bit 0 (krm000) corresponds to the kr00/p40-kr03/p43 pins. its setting is common to these four pins. bits 4 to 7 (krm004-krm007) correspond to the kr04/p44-kr07/p47 pins respectively and are set bit by bit. inputting the reset signal clears krm00 to 00h. figure 5-8 shows the format of key return mode register 00. figure 5-9 shows the block diagram of the falling edge detection circuit. figure 5-8. format of key return mode register 00 symbol76543210address when reset r/w krm00 krm007 krm006 krm005 krm004 0 0 0 krm000 f f f 5 h 0 0 h r/w krm00n selection of key return signal detection for the p4n/kr0n pin (n = 4 to 7) 0 no detection 1 detection (detecting the falling edges of the p4n/kr0n signals) krm000 selection of key return signal detection for the p40/kr00-p43/kr03 pins 0 no detection 1 detection (detecting the falling edges of the p40/kr00-p43/kr03 signals) cautions 1. be sure to set 0 in bits 1 to 3. 2. when krm00 is set to 1, the pull-up resistor is forcibly connected to the corresponding pin. however, when the pin is placed in output mode, the pull-up resistor is disconnected. 3. before setting krm00, inhibit interrupts (set bit 4 of interrupt mask flag register 0 (mk0) (krmk00 = 1). after setting krm00, clear bit 4 of interrupt request flag register 0 (if0) (krif00 = 0), then permit interrupts (clear bit 4 of mk0 (krmk00 = 0)).
data sheet u12627ej3v0ds00 20 m m m m pd789800 figure 5-9. block diagram of falling edge detection circuit falling edge detection circuit krmk00 krif00 set signal standby release signal key return mode register 00 (krm00) note selector p40/kr00 p41/kr01 p42/kr02 p43/kr03 p44/kr04 p45/kr05 p46/kr06 p47/kr07 note register that selects the pin used for falling edge input
data sheet u12627ej3v0ds00 21 m m m m pd789800 6. interrupt function there are two types and 12 sources of interrupt function as shown below. nonmaskable interrupt: 1 source maskable interrupts : 11 sources table 6-1. interrupt source list interrupt source type of interrupt priority note 1 name trigger internal/ external vector table address basic configuration type note 2 nonmaskable - intwdt watchdog timer overflow (when watchdog timer mode 1 is selected) (a) 0 intwdt watchdog timer overflow (when interval timer mode is selected) 0004h 1 intusbtm usb timer overflow 0006h 2 intusbrt eop detection when a usb token packet is received 0008h 3 intusbrd eop detection when a usb data/handshake packet is received 000ah 4 intusbst eop detection when a usb data/handshake packet is sent 000ch 5 intusbre detection of transition from j state to k state or se0 on the usb bus internal 000eh (b) 6 intp0 detection of a pin input edge external 0010h (c) 7 intcsi10 end of three-wire sio bus interface transmission and reception 0012h 8 inttm00 generation of the 8-bit timer counter 00 match signal 0014h 9 inttm01 generation of the 8-bit timer/event counter 01 match signal internal 0016h (b) maskable 10 intkr00 detection of the key return signal external 0018h (c) notes 1. the priority is the order of priority when multiple maskable interrupts are generated simultaneously. 0 is the highest priority and 10 is the lowest priority. 2. types (a) to (c) in the basic configuration correspond to (a) to (c) in figure 6-1, respectively. remark only one of the two watchdog timer interrupt sources, non-maskable or maskable (internal), can be selected.
data sheet u12627ej3v0ds00 22 m m m m pd789800 figure 6-1. basic configuration of interrupt function (a) internal nonmaskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt internal bus mk if interrupt request ie vector table address generator standby release signal (c) external maskable interrupt internal bus intm0, krm00 mk if ie vector table address generator standby release signal edge detection circuit interrupt request intm0 : external interrupt mode register 0 krm00 : key return mode register 00 if : interrupt request flag ie : interrupt enable flag mk : interrupt mask flag
data sheet u12627ej3v0ds00 23 m m m m pd789800 7. standby function the standby function is a function to reduce current consumption and there are two kinds of standby function as shown below. halt mode : stops the operating clock of the cpu. intermittent operation together with normal operation can reduce average current consumption. stop mode : stops oscillation of the system clock. stops the entire operation by the system clock and minimizes power consumption. figure 7-1. standby function stop mode oscillation of system clock stopped system clock operation halt mode clock supply to cpu is stopped, while oscillation continues halt instruction interrupt request stop instruction interrupt request 8. reset function the system is reset in the following two ways. external reset by reset pin internal reset by detection of inadvertent program loop time of watchdog timer
data sheet u12627ej3v0ds00 24 m m m m pd789800 9. instruction set overview the instruction set for the m pd789800 is listed later. 9.1 legend 9.1.1 operand formats and descriptions the description made in the operand field of each instruction conforms to the operand format for the instructions listed below (the details conform with the assembly specification). if more than one operand format is listed for an instruction, one is selected. uppercase letters, #, !, $, and a pair of [ and ] are used to specify keywords, which must be written exactly as they appear. the meanings of these special characters are as follows: ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ and ]: indirect address specification immediate data should be described using appropriate values or labels. the specification of values and labels must be accompanied by #, !, $, or a pair of [ and ]. operand registers, expressed as r or rp in the formats, can be described using both functional names (x, a, c, etc.) and absolute names (r0, r1, r2, and other names listed in table 9-1). table 9-1. operand formats and descriptions format description r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh: immediate data or label fe20h to ff1fh: immediate data or label (even addresses only) addr16 addr5 0000h to ffffh: immediate data or label (only even address for 16-bit data transfer instructions) 0040h to 007fh: immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
data sheet u12627ej3v0ds00 25 m m m m pd789800 9.1.2 descriptions of the operation field a : a register (8-bit accumulator) x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair (16-bit accumulator) bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag ie : interrupt request enable flag nmis : flag to indicate that a nonmaskable interrupt is being handled () : contents of a memory location indicated by a parenthesized address or register name x h , x l : upper and lower 8 bits of a 16-bit register : logical product (and) : logical sum (or) : exclusive or ? : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 9.1.3 description of the flag operation field (blank) : no change 0 : to be cleared to 0 1 : to be set to 1 : to be set or cleared according to the result r : to be restored to the previous value
data sheet u12627ej3v0ds00 26 m m m m pd789800 9.2 operations flag mnemonic operand byte clock operation z ac cy mov r, #byte 3 6 r ? byte saddr, #byte 3 6 (saddr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte a, psw 2 4 a ? psw psw, a 2 4 psw ? a a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl + byte] 2 6 a ? (hl + byte) [hl + byte], a 2 6 (hl + byte) ? a xch a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl + byte] 2 8 a ? (hl + byte) movw rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 3 1 4 ax ? rp rp, ax note 3 14rp ? ax notes 1. except when r = a. 2. except when r = a or x. 3. only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u12627ej3v0ds00 27 m m m m pd789800 flag mnemonic operand byte clock operation z ac cy xchw ax, rp note 1 8 ax ? rp add a, #byte 2 4 a, cy ? a + byte saddr, #byte 3 6 (saddr), cy ? (saddr) + byte a, r 2 4 a, cy ? a + r a, saddr 2 4 a, cy ? a + (saddr) a, !addr16 3 8 a, cy ? a + (addr16) a, [hl] 1 6 a, cy ? a + (hl) a, [hl + byte] 2 6 a, cy ? a + (hl + byte) addc a, #byte 2 4 a, cy ? a + byte + cy saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy a, r 2 4 a, cy ? a + r + cy a, saddr 2 4 a, cy ? a + (saddr) + cy a, !addr16 3 8 a, cy ? a + (addr16) + cy a, [hl] 1 6 a, cy ? a + (hl) + cy a, [hl + byte] 2 6 a, cy ? a + (hl + byte) + cy sub a, #byte 2 4 a, cy ? a - byte saddr, #byte 3 6 (saddr), cy ? (saddr) - byte a, r 2 4 a, cy ? a - r a, saddr 2 4 a, cy ? a - (saddr) a, !addr16 3 8 a, cy ? a - (addr16) a, [hl] 1 6 a, cy ? a - (hl) a, [hl + byte] 2 6 a, cy ? a - (hl + byte) subc a, #byte 2 4 a, cy ? a - byte - cy saddr, #byte 3 6 (saddr), cy ? (saddr) - byte - cy a, r 2 4 a, cy ? a - r - cy a, saddr 2 4 a, cy ? a - (saddr) - cy a, !addr16 3 8 a, cy ? a - (addr16) - cy a, [hl] 1 6 a, cy ? a - (hl) - cy a, [hl + byte] 2 6 a, cy ? a - (hl + byte) - cy and a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) note only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u12627ej3v0ds00 28 m m m m pd789800 flag mnemonic operand byte clock operation z ac cy or a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) xor a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) cmp a, #byte 2 4 a - byte saddr, #byte 3 6 (saddr) - byte a, r 2 4 a - r a, saddr 2 4 a - (saddr) a, !addr16 3 8 a - (addr16) a, [hl] 1 6 a - (hl) a, [hl + byte] 2 6 a - (hl + byte) addw ax, #word 3 6 ax, cy ? ax + word subw ax, #word 3 6 ax, cy ? ax - word cmpw ax, #word 3 6 ax - word inc r 2 4 r ? r + 1 saddr 2 4 (saddr) ? (saddr) + 1 dec r 2 4 r ? r - 1 saddr 2 4 (saddr) ? (saddr) - 1 incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp - 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a m - 1 ? a m ) 1 rol a, 1 1 2 (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a m - 1 ? a m ) 1 rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u12627ej3v0ds00 29 m m m m pd789800 flag mnemonic operand byte clock operation z ac cy set1 saddr. bit 3 6 (saddr. bit) ? 1 sfr. bit 3 6 sfr. bit ? 1 a. bit 2 4 a. bit ? 1 psw. bit 3 6 psw. bit ? 1 [hl]. bit 2 10 (hl). bit ? 1 clr1 saddr. bit 3 6 (saddr. bit) ? 0 sfr. bit 3 6 sfr. bit ? 0 a. bit 2 4 a. bit ? 0 psw. bit 3 6 psw. bit ? 0 [hl]. bit 2 10 (hl). bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy call !addr16 3 6 (sp - 1) ? (pc + 3) h , (sp - 2) ? (pc + 3) l , pc ? addr16, sp ? sp - 2 callt [addr5] 1 8 (sp - 1) ? (pc + 1) h , (sp - 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp - 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3, nmis ? 0 rrr push psw 1 2 (sp - 1) ? psw, sp ? sp - 1 rp 1 4 (sp - 1) ? rp h , (sp - 2) ? rp l , sp ? sp - 2 pop psw 1 4 psw ? (sp), sp ? sp + 1 r r r rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 movw sp, ax 2 8 sp ? ax ax, sp 2 6 ax ? sp br !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 ax 1 6 pc h ? a, pc l ? x remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u12627ej3v0ds00 30 m m m m pd789800 flag mnemonic operand byte clock operation z ac cy bc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 bt saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 1 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 1 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 1 bf saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 0 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 0 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 0 dbnz b, $addr16 2 6 b ? b - 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c - 1, then pc ? pc + 2 + jdisp8 if c 1 0 saddr, $addr16 3 8 (saddr) ? (saddr) - 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1 (enable interrupt) di 3 6 ie ? 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock control register (pcc).
data sheet u12627ej3v0ds00 31 m m m m pd789800 10. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol conditions rated value unit supply voltage v dd -0.3 to +6.5 v input voltage v i -0.3 to v dd + 0.3 v output voltage v o -0.3 to v dd + 0.3 v each pin -10 ma output high current i oh total for all pins -30 ma each pin 30 ma output low current i ol total for all pins 160 ma operating ambient temperature t a -40 to +85 c storage temperature t stg -65 to +150 c caution absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. always use the product within its rated values. remark the characteristics of a dual-function pin do not differ between the port function and the secondary function, unless otherwise stated.
data sheet u12627ej3v0ds00 32 m m m m pd789800 characteristics of the system clock oscillation circuit (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillator frequency (f x ) note 1 6.0 6.0 6.0 mhz crystal oscillation settling time note 2 10 ms x1 input frequency (f x ) note 1 6.0 6.0 6.0 mhz external clock x1 input high/low level width (t xh , t xl ) 71 83 ns notes 1. only the characteristics of the oscillation circuit are indicated. see the description of the ac characteristics for the instruction execution time. 2. time required for oscillation to settle once a reset sequence ends or stop mode is deselected. use a resonator that can settle oscillation before the oscillation settling time expires. caution when using the system clock oscillation circuit, observe the following conditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. keep the wiring as short as possible. do not allow signal wires to cross one another. keep the wiring away from wires that carry a high, non-stable current. keep the grounding point of the capacitors at the same level as v ss0 . do not connect the grounding point to a grounding wire that carries a high current. do not extract a signal from the oscillation circuit. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. x1 x2 open x2 x1 ic c2 c1
data sheet u12627ej3v0ds00 33 m m m m pd789800 dc characteristics (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. typ. max. unit each pin -1 ma output high current i oh total for all pins -15 ma each pin 10 ma output low current i ol total for all pins 80 ma v ih1 p00-p07, p10-p17 0.7v dd v dd v v ih2 reset, p20-p26, p40-p47 0.8v dd v dd v v ih3 x1 v dd C 0.1 v dd v input high voltage v ih4 usbdm, usbdp t a = 0 c to +70 c2.0 3.6v v il1 p00-p07, p10-p17 0 0.3v dd v v il2 reset, p20, p22, p40-p47 0 0.2v dd v v il3 x1 0 0.1 v input low voltage v il4 usbdm, usbdp t a = 0 c to +70 c0 0.8v v oh1 pins other than usbdm and usbdp i o = -1 ma v dd C 1.0 v output high voltage v oh2 usbdm, usbdp t a = 0 c to +70 c, rl = 15 k w (connected to v ss ) note 1 2.8 v v ol1 pins other than usbdm and usbdp i o = 10 ma 1.0 v output low voltage v ol2 usbdm, usbdp t a = 0 c to +70 c, rl = 15 k w (connected to v dd ) note 1 0.3 v i lih1 pins other than x1, x2, usbdm, and usbdp v i = v dd 3 m a i lih2 x1, x2 v i = v dd 20 m a high-level input leakage current i lih3 usbdm, usbdp t a = 0 c to +70 c 0 v v i v reg 10 m a i lil1 pins other than x1, x2, usbdm, and usbdp v i = 0 v -3 m a i lil2 x1, x2 v i = 0 v -20 m a low-level input leakage current i lil3 usbdm, usbdp t a = 0 c to +70 c 0 v v i v reg -10 m a high-level output leakage current i loh v o = 0 v 3 m a low-level output leakage current i lol v o = 0 v -3 m a software pull-up resistor rv i = 0 v 50 100 200 k w regulator output voltage v reg i o = 0 to -3 ma 3.0 3.3 3.6 v i dd1 6.0-mhz crystal oscillation (operating mode) note 3 1.5 3.0 ma i dd2 6.0-mhz crystal oscillation (halt mode) note 3 0.5 1.1 ma when the usb function is disabled 10 30 m a supply current note 2 i dd3 stop mode when the usb function is enabled (t a = 0 c to +70 c) 50 100 m a notes 1. rl is a resistor connected to a bus line. 2. the power supply current does not include the current flowing through the on-chip pull-up resistor. 3. during high-speed mode operation (when the processor clock control register (pcc) is cleared to 00h) remark the characteristics of a dual-function pin do not differ between the port function and the secondary function, unless otherwise stated.
data sheet u12627ej3v0ds00 34 m m m m pd789800 ac characteristics (1) basic operations (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. typ. max. unit when pcc = 00h (f x = 6.0 mhz) 0.333 0.333 0.333 m s cycle time (minimum instruction execution time) t cy when pcc = 02h (f x = 6.0 mhz) 1.333 1.333 1.333 m s ti01 input frequency f ti 04.0mhz ti01 input high/low level width t tih , t til 0.1 m s interrupt input high/low level width t inth , t intl intp0 10 m s reset input low level width t rsl 10 m s (2) serial interface (a) usb function (t a = 0 c to +70 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. typ. max. unit cl = 50 pf note 75 ns usbdm and usbdp rise time t r cl = 350 pf note 300 ns cl = 50 pf note 75 ns usbdm and usbdp fall time t f cl = 350 pf note 300 ns t r and t f matching t rfm t r /t f 80 120 % differential output signal cross-over point v crs 1.3 2.0 v data transfer rate t drate when the microcontroller operates at the system clock (f x ) of 6.0 mhz 1.5 1.5 1.5 mbps t udj1 upon transferring the next bit -95 0 95 ns transmission differential signal jitter t udj2 upon transferring the bit following the next bit -150 0 150 ns transmission eop width t eopt1 1.25 1.33 1.50 m s t eopr1 eop width to be eliminated 300 m s reception eop width t eopr2 eop width to be detected 675 m s t ures1 usb reset width to be eliminated 2.5 m s reception usb reset width t ures2 usb reset width to be detected 5.5 m s note cl is the capacitance of the usbdm and usbdp output lines.
data sheet u12627ej3v0ds00 35 m m m m pd789800 (b) three-wire serial i/o mode (t a = -40 c to +85 c, v dd = 4.0 to 5.5 v) (i) sck10 ...internal clock output (when f x = 6.0 mhz) parameter symbol conditions min. typ. max. unit when tps100 note 1 = 0 667 667 667 ns sck10 cycle time t kcy1 when tps100 note 1 = 1 1,333 1,333 1,333 ns when tps100 note 1 = 0 283 333 ns sck10 high/low level width t kh1 , t kl1 when tps100 note 1 = 1 617 667 ns si10 setup time t sik1 relative to sck10 - 150 ns when tps100 note 1 = 0 333 ns si10 hold time t ksi1 relative to sck10 - when tps100 note 1 = 1 667 ns so10 output dalay t kso1 relative to sck10 , cl = 100 pf note 2 0 200 ns notes 1. bit 4 of serial operation mode register 10 (csim10) 2. cl is the capacitance of the so output line. (ii) sck10 ...external clock output parameter symbol conditions min. typ. max. unit sck10 cycle time t kcy2 667 ns sck10 high/low level width t kh2 , t kl2 283 ns si10 setup time t sik2 100 ns si10 hold time t ksi2 333 ns so10 output delay t kso2 relative to sck10 , cl = 100 pf note 0 250 ns note cl is the capacitance of the so output line.
data sheet u12627ej3v0ds00 36 m m m m pd789800 ac timing measurement points (except the x1 input and usb function) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f x t xl t xh x1 input v ih3 (min.) v il3 (max.) ti timing ti01 t til t tih 1/f ti interrupt input timing intp0 t intl t inth reset input timing reset t rsl
data sheet u12627ej3v0ds00 37 m m m m pd789800 serial transfer timing usb function: usbdm and usbdp rise/fall time usbdm, usbdp t r 0.1v dd 0.9v dd t f transmission different signal jitter next bit bit following the next bit 667 ns 1,333 ns t udj1 t udj2 usbdm, usbdp differential output signal cross-over point, transmission eop width, reception eop width, and reception usb reset width t eopt1 , t eoprm , t uresm usbdm, usbdp v crs m = 1, 2 three-wire serial i/o mode: t kcym t klm t khm sck10 0.8v dd 0.2v dd t sikm t ksim t ksom input data output data si10 so10 m = 1, 2
data sheet u12627ej3v0ds00 38 m m m m pd789800 data hold characteristics of data memory at low voltage in stop mode (t a = -40 c to +85 c) item symbol conditions min. typ. max. unit data hold supply voltage v dddr 4.0 5.5 v release signal set time t srel 0 m s reset by reset 2 15 /f x ms oscillation settling time note 1 t wait reset by interrupt request note 2 ms notes 1. during the oscillation settling time, cpu operations are disabled to prevent them from becoming unstable upon the start of oscillation. 2. 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected according to the setting of bits 0 to 2 (osts0 to osts2) of the oscillation settling time selection register. remark f x : system clock oscillation frequency data hold timing (stop mode release by reset ) v dd data hold mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data hold timing (standby release signal: stop mode release by interrupt signal) v dd data hold mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
data sheet u12627ej3v0ds00 39 m m m m pd789800 11. package drawings 44-pin plastic qfp (10x10) item millimeters a b d g 13.2 0.2 10.0 0.2 0.8 (t.p.) 1.0 j 13.2 0.2 k s44gb-80-3bs-2 c 10.0 0.2 i 0.16 1.6 0.2 l 0.8 0.2 f 1.0 n p q s 0.10 2.7 0.1 0.125 0.075 3.0 max. m 0.17 + 0.06 - 0.05 h 0.37 + 0.08 - 0.07 r3 + 7 - 3 note each lead centerline is located within 0.16 mm of its true position (t.p.) at maximum material condition. 33 34 22 44 1 12 11 23 s s n j detail of lead end c d a b r k m l p i s q g f m h
data sheet u12627ej3v0ds00 40 m m m m pd789800 33 34 22 44 1 12 11 23 44 pin plastic lqfp (10 x 10) item millimeters n q 0.1 0.05 0.10 u 0.6 0.15 s44gb-80-8es-1 j i h n a 12.0 0.2 b 10.0 0.2 c 10.0 0.2 d 12.0 0.2 f g h 1.0 0.37 1.0 i j k 0.8 (t.p.) 1.0 0.2 0.2 l 0.5 m 0.17 s 1.6 max. r3 + 0.08 - 0.07 + 0.03 - 0.06 + 4 - 3 detail of lead end f g k m m p 1.4 0.05 note each lead centerline is located within 0.16 mm of its true position (t.p.) at maximum material condition. s s a b cd u r s p q l t
data sheet u12627ej3v0ds00 41 m m m m pd789800 12. recommended soldering conditions the m pd789800 should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact our sales representatives. table 12-1. surface mounting type soldering conditions m m m m pd789800gb- -3bs-mtx: 44-pin plastic qfp (10 10) soldering method soldering conditions symbol infrared reflow package peak temperature: 235c duration: 30 sec. max. (at 210c or above) maximum allowable number of reflow processes: 3 ir35-00-3 vps package peak temperature: 215c duration: 40 sec. max. (at 200c or above) maximum allowable number of reflow processes: 3 vp15-00-3 wave soldering solder bath temperature: 260c max. duration: 10 sec. max. number of times: once preliminary heat temperature: 120c max. (package surface temperature) ws60-00-1 partial heating method terminal temperature: 300c max. duration: 3 sec. max. (per device side) - caution use of more than one soldering method should be avoided (except for partial heating method). m m m m pd789800gb- -8es: 44-pin plastic lqfp (10 10) soldering method soldering conditions symbol infrared reflow package peak temperature: 235c duration: 30 sec. max. (at 210c or above) maximum allowable number of reflow processes: 2 ir35-00-2 vps package peak temperature: 215c duration: 40 sec. max. (at 200c or above) maximum allowable number of reflow processes: 2 vp15-00-2 wave soldering solder bath temperature: 260c max. duration: 10 sec. max. number of times: once preliminary heat temperature: 120c max. (package surface temperature) ws60-00-1 partial heating method terminal temperature: 300c max. duration: 3 sec. max. (per device side) - caution use of more than one soldering method should be avoided (except for partial heating method).
data sheet u12627ej3v0ds00 42 m m m m pd789800 appendix a development tools the following development tools are available for developing systems using the m pd789800. language processing software ra78k0s notes 1, 2, 3 assembler package common to the 78k/0s series cc78k0s notes 1, 2, 3 c compiler package common to the 78k/0s series df789801 notes 1, 2, 3 device file for the m pd789800 sub-series cc78k0s-l notes 1, 2, 3 c compiler library source file common to the 78k/0s series flash memory write tools flashpro ill dedicated flash writer fa-44gb note 4 flash memory write adapter (gb-3bs type) fa-44gb-8es note 4 flash memory write adapter (gb-8es type) debugging tools (1/2) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of application system using 78k/0s series. supports integrated debugger (id78k0s-ns). used in combination with ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-70000-mc-ps-b ac adapter this is the adapter for supplying power from outlet of 100 to 240 vac. ie-70000-98-if-c interface adapter this adapter is needed when pc-9800 series (excluding notebook models) is used as a host machine of ie-78k0s-ns. (compatible with c bus) ie-70000-cd-if-a pc card interface this pc card and interface cable are needed when a notebook-type personal computer is used as a host machine of ie-78k0s-ns. (compatible with a pcmcia socket) ie-70000-pc-if-c interface adapter this adapter is needed when ibm pc/at tm and compatibles are used as a host machine of ie-78k0s-ns. (compatible with isa bus) ie-70000-pci-if interface adapter this adapter is needed when a personal computer with a built-in pci bus is used as a host machine of ie-78k0s-ns. ie-789801-ns-em1 emulation board emulation board for emulating the peripheral hardware inherent to the device. used in combination with in-circuit emulator. notes 1. based on the pc-9800 series (japanese windows tm ) 2. based on the ibm pc/at and compatibles (japanese/english windows) 3. based on the hp9000 series 700 tm (hp-ux tm ), sparcstation tm (sunos tm , solaris tm ), and news tm (news-os tm ) 4. product manufactured by naito densei machida mfg. co., ltd. (044-822-3813) remark the ra78k0s and cc78k0s can be used in combination with the df789801.
data sheet u12627ej3v0ds00 43 m m m m pd789800 debugging tools (2/2) np-44gb notes 1, 2 emulation prove this probe is used to connect the in-circuit emulator to the target system and is designed for 44-pin plastic qfp. it should be used in combination with ev-9200g-44. ev-9200g-44 conversion socket this conversion socket connects the np-44gb to the target system board designed to mount a 44-pin plastic qfp (gb-3bs, gb-8es type). np-44gb-tq notes 1, 2 emulation prove this probe is used to connect the in-circuit emulator to the target system and is designed for 44-pin plastic qfp. it should be used in combination with tgb-044sap. tgb-044sap note 3 conversion socket this conversion socket connects the np-44gb-tq to the target system board designed to mount a 44-pin plastic qfp (gb-3bs, gb-8es type). sm78k0s notes 4, 5 system simulator common to the 78k/0s series id78k0s-ns notes 4, 5 integrated debugger common to the 78k/0s series df789801 notes 4, 5 device file for the m pd789800 sub-series real-time os mx78k0s notes 4, 5 os for the 78k/0s series notes 1. product manufactured by naito densei machida mfg. co., ltd. (044-822-3813) 2. either probe and socket combination can be selected for use. 3. product manufactured by tokyo eletec corporation for further information, consult: tokyo electronic div. (tel (03) 3820-7112), or osaka electronic div. (tel (06) 6244-6672) daimaru kogyo corporation. 4. based on the pc-9800 series (japanese windows) 5. based on the ibm pc/at and compatibles (japanese/english windows) remark the sm78k0s can be used in combination with the df789801.
data sheet u12627ej3v0ds00 44 m m m m pd789800 appendix b related documents documents related to devices document no. document name japanese english m pd789800 data sheet u12627j this manual m pd78f9801 data sheet u12626j u12626e m pd789800 sub-series user's manual u12978j u12978e 78k/0s series user's manual, instruction u11047j u11047e documents related to development tools (user's manual) document no. document name japanese english operation u11622j u11622e assembly language u11599j u11599e ra78k0s assembler package structured assembly language u11623j u11623e operation u11816j u11816e cc78k0s c compiler language u11817j u11817e sm78k0s system simulator for ibm pc/at (windows) reference u11489j u11489e sm78k series system simulator external parts user open interface specifications u10092j u10092e id78k0s-ns integrated debugger windows-based reference u12901j u12901e ie-78k0s-ns in-circuit emulator u13549j u13549e ie-789801-ns-em1 emulation board u13390j u13390e documents related to software to be incorporated into the product (user's manual) document no. document name japanese english os for 78k/0s series mx78k0s basic u12938j u12938e other documents document no. document name japanese english semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e semiconductor device quality control/reliability handbook c12769j - guide for products related to micro-computer: other companies u11416j - caution the above documents may be revised without notice. use the latest versions when you design application systems.
data sheet u12627ej3v0ds00 45 m m m m pd789800 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. eeprom is a trademark of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
data sheet u12627ej3v0ds00 46 m m m m pd789800 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
data sheet u12627ej3v0ds00 47 m m m m pd789800 [memo]
m m m m pd789800 some related documents may be preliminary versions. note, however, that whether a related document is preliminary is not indicated in this document. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of september, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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