30 n-channel logic level enhancement mode field effect transistor features 30v , 70a , r ds(on) =7.5m @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-220 & to-263 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 20 v -pulsed i d 70 a i dm 210 a drain-source diode forward current i s 70 a maximum power dissipation p d w operating and storage temperature range t j ,t stg -55 to 175 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 1.9 62.5 /w c /w c ? r ds(on) =10.5m @v gs =5v. ? @tc=25 c derate above 25 c w/ c drain current-continuous s g d ceb series to-263(dd-pak) cep series to-220 g s s d d g 4-112 4 dec. 2002 CEP71A3/ceb71a3 4 65 0.53
electrical characteristics (t c =25 c unless otherwise noted) parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss v gs =0v,i d = 250 a 30 v zero gate voltage drain current i dss v ds =30v,v gs =0v 1 a gate-body leakage i gss v gs = 20v, v ds =0v 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d =250 a 13 v drain-source on-state resistance r ds(on) v gs =10v,i d =50a 7.5 m ? v gs =5v,i d = 40a 10.5 m ? on-state drain current i d(on) v gs =10v,v ds =5v 120 50 a s forward transconductance fs g v ds =10v,i d = 35a dynamic characteristics b input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =15v, v gs =0v f =1.0mh z 2152 p f p f p f 234 switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f fall time v dd = 15v, i d =60a, v gen =10v r g =1.8 ? 27 54 ns ns ns ns 28 58 17 total gate charge gate-source charge gate-drain charge q g q gs q gd nc nc nc 6.5 9.2 965 55 67 9 18 v ds =15v , i d = 30a , v gs =10v 56 105 42 CEP71A3/ceb71a3 4 4-113
parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs = 0v, is =35a 0.93 1.3 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. [ [ 4-114 figure 1. output characteristics figure 2. transfer characteristics figure 3. capacitance v ds , drain-to source voltage (v) v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) i d , drain current(a) c, capacitance (pf) i d , drain current (a) 4 CEP71A3/ceb71a3 60 50 40 30 20 10 0 0 1 2 3 4 5 v g s =3 v v gs =10,8,6,4v 0 12 34 25 c tj=125 c -55 c 20 30 40 50 60 10 figure 4. on-resistance variation with temperature t j , junction temperature( c) on-resistance(ohms) r ds(on) , r ds(on) , normalized -100 -50 0 50 100 200 2.2 1.9 1.6 1.3 1.0 0.7 0.4 v gs =10v i d =50a 150 3000 2500 2000 1500 1000 500 0 5 10 15 20 25 30 ciss coss crss 0
with temperature figure 6. breakdown voltage variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) v gs , gate to source voltage (v) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) figure 7. transconductance variation with drain current i ds , drain-source current (a) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) i d , drain current (a) 4-115 4 figure 5. gate threshold variation CEP71A3/ceb71a3 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 3 a -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 3 a 50 10 1.0 0.1 0.4 0.6 0.8 1.0 1.2 1.4 10 0 2 4 6 8 015 30 45 60 v ds =15v i d =30a 50 40 30 20 10 0 0 10 20 30 40 v ds =10v 10 10 -1 10 10 2 1 0 10 -1 10 1 10 2 10 0 t c =25 c single pulse tj=175 c rds( o n) li m i t dc 100ms 10 ms 1m s 100 3 s
figure 11. switching test circuit figure 12. switching waveforms t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width 4-116 4 inverted transient thermal impedance square wave pulse duration (msec) figure 13. normalized thermal transient impedance curve r(t),normalized effective v dd r d v v r s v g gs in gen out l CEP71A3/ceb71a3 p dm t 1 t 2 1. r / jc (t)=r (t) * r / jc 2. r / jc =see datasheet 3. t jm- t c =p*r / jc (t) 4. duty cycle, d=t1/t2 0.1 0.05 0.02 0.01 single pulse 10 10 10 4 3 2 10 1 10 0 10 -1 10 -2 10 -2 10 -1 10 0 0.2 d=0.5
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