View HYS64V128220GU-75-A_2583953.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

infineon technologies 1 11.01 hys 64/72v128220gu sdram-modules 3.3 v 128m x 64/72-bit, 1024 mbyte sdram modules 168-pin unbuffered dimm modules description the hys 64v128220gu and hys 72128220gu are industry standard 168-pin 8-byte dual in-line memory modules (dimms) which are organized as 128m 64 and 128m 72 in two banks high speed memory arrays designed with 512m synchronous drams (sdrams) for non-parity and ecc applications. the dimms use ?-7? speed sorted 512 mbit synchronous drams (sdrams) to meet the pc133-222 requirements, ?-7.5? for pc133-333 and ?-8? components for pc100-222 applications. decoupling capacitors are mounted on the pc board. the pc board design is according to intel?s module specification. the dimms have a serial presence detect, implemented with a serial e 2 prom using the 2-pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 168-pin dimms provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25? (31.75 mm) height. 168-pin unbuffered 8 byte dual-in-line sdram modules for pc main memory applications using 256mbit technology. pc100-222, pc133-333 & pc133-222 versions two bank 128m 64 and 128m 72 organization optimized for byte-write non-parity and ecc applications jedec standard synchronous drams (sdram) programmed latencies: single + 3.3 v ( 0.3 v) power supply programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh decoupling capacitors mounted on substrate all inputs and outputs are lvttl compatible serial presence detect with e 2 prom uses infineon 512 mbit sdram components in 64m 8 organization and tsopii-54 packages fully pc board layout compatible to intel?s rev. 1.0 module specification gold contact pad, card size: 133.35 mm 31.75 mm 4.00 mm (jedec mo-161-ba) product speed cl t rcd t rp -7 pc133 2 2 2 -7.5 pc133 3 3 3 -8 pc100 2 2 2 sdram performance: -7 -7.5 -8 unit pc133 pc133 pc100 f ck clock frequency (max.) 133 133 100 mhz t ac clock access time 5.4 5.4 6 ns target datasheet 11.01
hys 64/72v128220gu sdram-modules infineon technologies 2 11.01 note: all part numbers end with a place code, designating the die revision. consult factory for current revision. example: hys 64v128220gu-8-a, indicating rev.a dies are used for sdram components. ames in paranthese are for the x72 ecc versions; example: pin 106 = (cb5) ordering information type code package descriptions module height hys 64128220gu-7-a pc133-222-520 l-dim-168-30 pc133 128m 64 2 bank sdram module 1.25 ? hys 72v128220gu-7-a pc133-222-520 l-dim-168-30 pc133 128m 72 2 bank sdram module 1.25 ? hys 64v128220gu-7.5-a pc133-333-520 l-dim-168-30 pc133 128m 64 2 bank sdram module 1.25 ? hys 72v128220gu-7.5-a pc133-333-520 l-dim-168-30 pc133 128m 72 2 bank sdram module 1.25 ? hys 64v128220gu-8-a pc100-222-620 l-dim-168-30 pc100 128m 64 2 bank sdram module 1.25 ? hys 72v128220gu-8-a pc100-222-620 l-dim-168-30 pc100 128m 72 2 bank sdram module 1.25 ? pin definitions and functions a0 - a12 address inputs clk0 - clk3 clock input ba0, ba1 bank selects dqmb0 - dqmb7 data mask dq0 - dq63 data input/output cs0 - cs3 chip select cb0 - cb7 check bits (x72 organization only) v dd power (+ 3.3 v) ras row address strobe v ss ground cas column address strobe scl clock for presence detect we read/write input sda serial data out for presence detect cke0, cke1 clock enable n.c./du no connection address format part number rows columns bank select refresh period interval 128m 64 128m 72 hys64v128220gu hys72v128220gu 13 11 2 8k 64 ms 7.8 s
hys 64/72v128220gu sdram-modules infineon technologies 3 11.01 pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 du 86 dq32 128 cke0 3dq1 45cs2 87 dq33 129 cs3 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 v dd 48 du 90 v dd 132 n.c. 7dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n.c. 92 dq37 134 n.c. 9 dq6 51 n.c. 93 dq38 135 n.c. 10 dq7 52 n.c. (cb2) 94 dq39 136 cb6 11 dq8 53 n.c. (cb3) 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 n.c. 103 dq46 145 n.c. 20 dq15 62 du 104 dq47 146 du 21 n.c. (cb0) 63 cke1 105 n.c. (cb4) 147 n.c. 22 n.c. (cb1) 64 v ss 106 n.c. (cb5) 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n.c. 66 dq22 108 n.c. 150 dq54 25 n.c. 67 dq23 109 n.c. 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we 69 dq24 111 cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0 72 dq27 114 cs1 156 dq59 31 du 73 v dd 115 ras 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 clk2 121 a9 163 clk3 38 a10 80 n.c. 122 ba0 164 n.c. 39 ba1 81 wp 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 clk1 167 sa2 42 clk0 84 v dd 126 a12 168 v dd note: pin names in parenthses are for the x72 ecc versions
hys 64/72v128220gu sdram-modules infineon technologies 4 11.01 block diagram: 64m x 64/72 two bank sdram dimm modules bl012 dq0-dq7 dqm cs d0 dq0-dq7 dqm d8 cs cs0 cs1 dq(7:0) dqmb0 dq0-dq7 dq(39:32) dqmb4 dqm cs d4 cs dq0-dq7 dqm d12 dq0-dq7 dq(15:8) dqmb1 dqm cs d1 cs dq0-dq7 dqm d9 dq0-dq7 dq(47:40) dqmb5 dqm cs cs d5 dqm dq0-dq7 d13 dq0-dq7 cb(7:0) dqm cs cs d16 dqm dq0-dq7 d17 dq0-dq7 dq0-dq7 dq(31:24) dqmb3 dq(23:16) dqmb2 dqm dqm cs3 cs2 cs cs cs cs cs cs d3 dq0-dq7 dqm d2 dqm dq0-dq7 dqmb7 dq(63:56) d11 dqmb6 dq(55:48) d10 cs d7 d6 dq0-dq7 dqm dq0-dq7 dqm cs dq0-dq7 dqm d15 dqm dq0-dq7 d14 a0-a12, ba0, ba1 d0-d15, (d16, d17) dd v ss v c d0-d15, (d16, d17) d0-d15, (d16, d17) ras, cas, we d0-d15, (d16, d17) d0-d7, (d16) cke0 d9-d15, (d17) cke1 dd v 10 k ? clock wiring 32 m x 64 32 m x 72 clk0 4 sdram + 3.3 pf 5 sdram 5 sdram 4 sdram + 3.3 pf clk1 4 sdram + 3.3 pf 4 sdram + 3.3 pf clk2 4 sdram + 3.3 pf clk3 4 sdram + 3.3 pf 47 k scl scl 2 sa0 sa1 sa2 e prom (256 word x 8 bit) sa1 sa0 sa2 sda wp ? note: d16 & d17 is only used in the x72 ecc version and all resistor values are 10 except otherwise noted. ?
hys 64/72v128220gu sdram-modules infineon technologies 5 11.01 absolute maximum ratings parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ? 1.0 4.6 v power supply voltage on v dd v dd ? 1.0 4.6 v storage temperature range t stg -55 +150 o c power dissipation per sdram component p d ? 1w data out current (short circuit) i os ? 50 ma permanent device damage may occur if ? absolute maximum ratings ? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability dc characteristics t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v parameter symbol limit values unit min. max. input high voltage v ih 2.0 v dd +0.3 v input low voltage v il ? 0.5 0.8 v output high voltage ( i out = ? 4.0 ma) v oh 2.4 ? v output low voltage ( i out =4.0 ma) v ol ? 0.4 v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) ? 40 40 a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) ? 40 40 a capacitance t a =0 to 70 c; v dd =3.3v 0.3 v, f =1mhz parameter symbol limit values unit max. 64m 64 max. 64m 72 input capacitance ( a0 to a11, ba0, ba1, ras , cas , we ) c i1 105 144 pf input capacitance (cs0 - cs3 ) c i2 32 40 pf input capacitance (clk0 - clk3) c icl 40 43 pf input capacitance (cke0, cke1) c i3 65 72 pf input capacitance (dqmb0 - dqmb7) c i4 20 25 pf input/output capacitance (dq0 - dq63, cb0 - cb7) c io 17 17 pf input capacitance (scl, sa0-2) c sc 88pf input/output capacitance c sd 88pf
hys 64/72v128220gu sdram-modules infineon technologies 6 11.01 operating currents per sdram component t a = 0 to 70 o c; v ss = 0 v; v dd , v ddq = 3.3 v 0.3 v parameter & test condition symb. -7 -7.5 -8 note max. operating current one bank active, burst length = 1 t rc = t rc(min) , io = 0 ma idd1 tbd. tbd. tbd. ma 3, 4 precharge standby current in power down mode cs =vih (min.), cke<=vil(max) idd2p 4 4 4 ma 3 precharge standby current in non-power down mode cs = vih (min.), cke>=vih(min) idd2n 36 36 30 ma 3 no operating current active state ( max. 4 banks) cs = vih(min), cke>=vih(min.) idd3n 35 35 30 ma 3 cs = vih(min), cke<=vil(max.) idd3p 11 11 11 ma 3 burst operating current read command cycling idd4 255 255 150 ma 3, 4 auto refresh current auto refresh command cycling t rfc = t rfc(min) idd5 440 440 360 ma 5 t rfc = 7.8 s tbd. tbd. tbd. ma self refresh current (standard components) self refresh mode cke=0.2v. tck=infinity idd6 4 4 4 ma self refresh current (low power components) self refresh mode cke=0.2v. tck=infinity idd6 tbd. tbd. tbd. ma notes: 3. these parameters depend on the cycle rate. all values are measured at 133 mhz for ? -7 ? and ? -7.5 ? and at 100 mhz for ? -8 ? components with the outputs open. input signals are changed once during tck. 4. these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the vddq current is excluded. 5. t rfc = t rfc(min) ? burst refresh ? , t rfc = 7.8 s ? distributed refresh ? .
hys 64/72v128220gu sdram-modules infineon technologies 7 11.01 ac characteristics 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7 pc133-222 -7.5 pc133-333 -8 pc100-222 min. max min. max. min. max. clock clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 7.5 ? ? 7.5 10 ? ? 10 10 ? ? ns ns ? system frequency cas latency = 3 cas latency = 2 f ck ? ? 133 133 ? ? 133 100 ? ? 100 100 mhz mhz ? clock access time cas latency = 3 cas latency = 2 t ac ? ? 5.4 5.4 ? ? 5.4 6 ? ? 6 6 ns ns 3), 4) clock high pulse width t ch 2.5 ? 2.5 ? 3 ? ns 4) clock low pulse width t cl 2.5 ? 2.5 ? 3 ? ns 4) setup and hold times input setup time t cs 1.5 ? 1.5 ? 2 ? ns 5) input hold time t ch 0.8 ? 0.8 ? 1 ? ns 5) power down mode entry time t sb ? 1 ? 1 ? 1clk 6) power down mode exit setup time t pde 1 ? 1 ? 1 ? clk 7) mode register setup time t rsc 2 ? 2 ? 2 ? clk transition time (rise and fall) t t 1 ? 1 ? 1 ? ns ? common parameters ras to cas delay t rcd 15 ? 20 ? 20 ? ns ? precharge time t rp 15 ? 20 ? 20 ? ns ? active command period t ras 42 ? 45 100k 50 100k ns ? cycle time t rc 60 ? 67.5 ? 70 ? ns ? bank to bank delay time t rrd 14 ? 15 ? 16 ? ns ? cas to cas delay time (same bank) t ccd 1 ? 1 ? 1 ? clk ?
hys 64/72v128220gu sdram-modules infineon technologies 8 11.01 notes 1. all ac characteristics are shown on sdram component level. an initial pause of 100 s is required after power-up, then a precharge all banks command must be given followed by eight auto-refresh (cbr) cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit show. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1 v/ns edge rate between 0.8 v and 2.0 v. 3. if clock rising time is longer than 1 ns, a time ( t t /2 ? 0.5) ns must be added to this parameter. 4. rated at 1.4 v 5. if t t is longer than 1 ns, a time ( t t ? 1) ns has to be added to this parameter. 6. anytime the refresh period has been exceeded, a minimum of two auto-refresh (cbr) commands must be given to ? wake-up ? the device. 7. timing is asynchronous. if setup time is not met by rising edge of the clock then the cke signal is assumed latched on the next cycle. refresh cycle refresh period (8192 cycles) t ref 64 ?? 64 ? 64 ms 6) self refresh exit time t srex ? 11 ? 1 ? clk 8) read cycle data out hold time t oh 3 ? 3 ? 3 ? ns 2) data out to low impedance t lz 0 ? 0 ? 0 ? ns ? data out to high impedance t hz 373738ns 9) dqm data out disable latency t dqz ? 2 ? 2 ? 2clk ? write cycle data input to precharge (write recovery) t wr 2 ? 2 ? 2 ? clk ? dqm write mask latency t dqw 0 ? 0 ? 0 ? clk ? ac characteristics (cont ? d) 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7 pc133-222 -7.5 pc133-333 -8 pc100-222 min. max min. max. min. max.
hys 64/72v128220gu sdram-modules infineon technologies 9 11.01 8. self-refresh exit is a synchronous operation and begins on the second positive clock edge after cke returns high. self-refresh exit is not complete until a time period equal to t rc is satisfied after the self refresh exit command is registered. 9. this is referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. serial presence detect a serial presence detect storage device - e 2 prom - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol (i 2 c synchronous 2-wire bus). 50 pf i/o measurement conditions for t ac and t oh clock 2.4 v 0.4 v input is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd
hys 64/72v128220gu sdram-modules infineon technologies 10 11.01 spd-table for 128m x 64 (1024 mbyte non-ecc) modules hys64v128220gu byte # description spd entry value hex 128m x 64 -7 -7.5 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses 13 0d 4 number of column addresses 11 0b 5 number of dimm banks 2 02 6 module data width 64 40 7 module data width (cont ? d) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl = 3 7.5 / 10 ns 75 75 a0 10 access time from clock at cl = 3 5.4 / 6 ns 54 54 60 11 dimm config non-ecc 00 12 refresh rate/type self-refresh, 7.8 s 82 13 sdram width, primary x8 08 14 error checking sdram data width na 00 15 minimum clock delay for back-to- back random column address t ccd =1clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cl = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes unbuffered 00 22 sdram device attributes: general v dd tol +/ ? 10% 0e 23 sdram cycle time at cl = 2 7.5 / 10.0 ns 75 a0 a0 24 access time from clock for cl = 2 5.4 / 6.0 ns 54 60 60 25 minimum clock cycle time at cl = 1 not supported 00 00 00 26 maximum data access time from clock at cl = 1 not supported 00 00 00 27 minimum row precharge time 15 / 20 ns 0f 14 14 28 minimum row active to row active delay t rrd 14 / 15 / 16 ns 0e 0f 10 29 minimum ras to cas delay t rcd 15 / 20 ns 0f 14 14 30 minimum ras pulse width t ras 42 / 45 / 50 ns 2a 2d 32 31 module bank density (per bank) 256 mbyte 80 32 sdram input setup time 1.5 / 2.0 ns 15 15 20 33 sdram input hold time 0.8 / 1.0 ns 08 08 10
hys 64/72v128220gu sdram-modules infineon technologies 11 11.01 34 sdram data input hold time 1.5 / 2.0 ns 15 15 20 35 sdram data input setup time 0.8 / 1.0 ns 08 08 10 36-61 superset information ? ff ff ff 62 spd revision revision 1.2 12 12 12 63 checksum for bytes 0 - 62 ? 35 7a dd 64 manufacturers jedec id code ? c1 65-71 manufacturer infineo(n) 72 module assembly locaction 73-90 module part number 91-92 module revision code 93-94 module manufacturing code 95-98 module serial number 99- 125 superset information 126 frequency specification 64 64 64 127 100 mhz support details ? ff ff ff 128+ unused storage locations ? ff ff ff spd-table for 128m x 64 (1024 mbyte non-ecc) modules hys64v128220gu byte # description spd entry value hex 128m x 64 -7 -7.5 -8
hys 64/72v128220gu sdram-modules infineon technologies 12 11.01 spd-table for 128m x 72 (1024 mbyte ecc) modules hys72v128220gu byte# description spd entry value hex 128m x 72 -7 -7.5 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses 13 0d 4 number of column addresses 11 0b 5 number of dimm banks 2 02 6 module data width 72 48 7 module data width (cont ? d) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl = 3 7.5 / 10 ns 75 75 a0 10 access time from clock at cl = 3 5.4 / 6 ns 54 54 60 11 dimm config ecc 02 12 refresh rate/type self-refresh, 7.8 s 82 13 sdram width, primary x8 08 14 error checking sdram data width x8 08 15 minimum clock delay for back-to- back random column address t ccd =1clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cl = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes unbuffered 00 22 sdram device attributes: general v dd tol +/ ? 10% 0e 23 sdram cycle time at cl = 2 7.5 / 10.0 ns 75 a0 a0 24 access time from clock for cl = 2 5.4 / 6.0 ns 54 60 60 25 minimum clock cycle time at cl = 1 not supported 00 00 00 26 maximum data access time from clock at cl = 1 not supported 00 00 00 27 minimum row precharge time 15 / 20 ns 0f 14 14 28 minimum row active to row active delay t rrd 14 / 15 / 16 ns 0e 0f 10 29 minimum ras to cas delay t rcd 15 / 20 ns 0f 14 14 30 minimum ras pulse width t ras 42 / 45 / 50 ns 2a 2d 32 31 module bank density (per bank) 256 mbyte 80 32 sdram input setup time 1.5 / 2.0 ns 15 15 20 33 sdram input hold time 0.8 / 1.0 ns 08 08 10
hys 64/72v128220gu sdram-modules infineon technologies 13 11.01 34 sdram data input hold time 1.5 / 2.0 ns 15 15 20 35 sdram data input setup time 0.8 / 1.0 ns 08 08 10 36-61 superset information ? ff ff ff 62 spd revision revision 1.2 12 12 12 63 checksum for bytes 0 - 62 ? 47 8c ef 64 manufacturers jedec id code ? c1 65-71 manufacturer infineo(n) 72 module assembly locaction 73-90 module part number 91-92 module revision code 93-94 module manufacturing code 95-98 module serial number 99-125 superset information 126 frequency specification 64 64 64 127 100 mhz support details ? ff ff ff 128+ unused storage locations ? ff ff ff spd-table for 128m x 72 (1024 mbyte ecc) modules hys72v128220gu byte# description spd entry value hex 128m x 72 -7 -7.5 -8
hys 64/72v128220gu sdram-modules infineon technologies 14 11.01 package outlines l-dim-168-30 (jedec mo-161-ba) sdram dimm module package hys 64/72v128220gu note: all tolerances according to jedec standard l-dim-168-30 133.35 10 11 3 6.35 6.35 41 40 42.18 84 127.35 3 1.27 85 94 95 124 125 168 2 17.78 4 3min. 4 max. 31.75 detail of contacts 2.55 1 1.27 1 1.27 91 x 1.27 = 115.57 3.125 0.25 3 *) on ecc modules only *) *) + 0.15 - + 0.13 - + 0.1 -
hys 64/72v128220gu sdram-modules infineon technologies 15 11.01 change list: 4.11.2001 first revision

▲Up To Search▲

Price & Availability of HYS64V128220GU-75-A

	To Download HYS64V128220GU-75-A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .