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lm2641 dual adjustable step-down switching power supply controller general description the lm2641 is a dual step-down power supply controller intended for application in notebook personal computers and other battery-powered equipment. fixed-frequency synchronous drive of logic-level n-channel power mosfets is combined with an optional pulse-skipping mode to achieve ultra efficient power conver- sion over a 1000:1 load current range. the pulse-skipping mode can be disabled in favor of fixed-frequency operation regardless of the load current level. high dc gain and current-mode feedback control assure excellent line and load regulation and a wide loop bandwidth for fast response to dynamic loads. an internal oscillator fixes the switching frequency at 300 khz. optionally, switching can be synchronized to an external clock running as fast as 400 khz. an optional soft-start feature limits current surges from the input power supply at start up and provides a simple means of start-up sequencing. logic-level inputs allow the controllers to be turned on and off separately. key specifications n 96% efficient n 5.5 to 30v input range n dual outputs adjustable from 2.2 to 8v n 0.5% typical load regulation error n 0.002%/v typical line regulation error features n 300 khz fixed-frequency switching n switching synchronization with an external signal up to 400 khz n optional pulse-skipping mode n adjustable secondary feedback n input undervoltage lockout n output undervoltage shutdown protection n output overvoltage shutdown protection n programmable soft-start (each controller) n 5v, 50 ma linear regulator output n precision 2.5v reference output n 28-pin tssop applications n notebook and subnotebook computers n wireless data terminals n battery-powered instruments connection diagram and ordering information 28-lead tssop (mtc) 10094901 top view order number LM2641MTC-ADJ see ns package number mtc28 may 2001 lm2641 dual adjustable step-down switching power supply controller ? 2001 national semiconductor corporation ds100949 www.national.com
pin description (refer to typical application circuits) pin # name function 1 csh2 the sense point for the positive side of the voltage across the current sense resistor (r13) placed in series with output # 2. 2 fb2 the regulated output voltage appearing at output # 2 is sensed using this pin by connecting it to the center of the output resistive divider (r15 and r16). 3 comp2 an r-c network made up of r11, c10, and c12 is connected to this pin which provides loop compensation for regulated output # 2. 4 ss2 this provides programmable soft-start for the # 2 output along with capacitor c15. 5 on/off2 this pin turns off only output # 2. 6sd the part can be put into asleepo mode using this pin, where both outputs are off and the internal chip functions are shut down. 7 sync the internal oscillator may be synchronized to an external clock via this pin. 8 gnd connect this pin to circuit signal ground. 9 ref internal 2.5v reference voltage. this voltage is turned off by the sd pin, but remains on if either or both on/off pins are pulled low, which turns off the regulated output(s). 10 2ndfb/fpwm a 12v supply can be generated using an auxiliary winding on the 5v output inductor. feedback to control this 12v output is brought in through this pin. if the 12v supply is not required, this pin can also force the chip to operate at fixed frequency at light loads by pulling the pin low (this is the aforced-pwmo mode of operation). this will prevent the converter from operating in pulse-skipping mode. 11 on/off1 this pin turns off only output # 1. 12 ss1 this provides programmable soft-start for the # 1 output along with capacitor c3. 13 comp1 an r-c network made up of r6, c5, and c7 is connected to this pin which provides loop compensation for regulated output # 1. 14 fb1 the regulated output voltage appearing at output # 1 is sensed using this pin by connecting it to the center of the output resistive divider (r1 and r2). 15 csh1 the sense point for the positive side of the voltage across the current sense resistor (r4) placed in series with output # 1. 16 hdrv1 the drive for the gate of the high-side switching fet used for output # 1. 17 sw1 this is the switching output drive point of the two power fets which produce output # 1. 18 cboot1 the bootstrap capacitor (c8) for output # 1 is returned to this point. 19 ldrv1 the drive for the gate of the low-side switching fet (synchronous rectifier) used for output # 1. 20 pgnd connect this pin to circuit power ground. 21 csl1 the sense point for the negative side of the voltage across the current sense resistor (r4) placed in series with output # 1. 22 lin this pin provides a low-current (50 ma max) 5v output. this output is always on, and can not be turned off by either the sd or on/off pins. 23 in this is the connection for the main input power. 24 ldrv2 the drive for the gate of the low-side switching fet (synchronous rectifier) used for output # 2. 25 cboot2 the bootstrap capacitor (c9) for output # 2 is returned to this point. 26 sw2 this is the switching output drive point of the two power fets which produce output # 2. 27 hdrv2 the drive for the gate of the high-side switching fet used for output # 2. 28 csl2 the sense point for the negative side of the voltage across the current sense resistor (r13) placed in series with output # 2. lm2641 www.national.com 2
typical application circuits 10094903 figure 1. application with 5v/3a and 3.3v/4a outputs lm2641 www.national.com 3
typical application circuits (continued) 10094904 figure 2. application with 5v/3a, 3.3v/4a, and 12v/0.3a outputs lm2641 www.national.com 4
absolute maximum ratings (notes 2, 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. in, sw1, and sw2 ?0.3 to 31v fb1 and fb2 ?0.3 to 3v sd, on/off1, on/off2, 2ndfb/fpwm, sync, ref, ss1, ss2, comp1, comp2 and csl1 ?0.3 to (v lin +0.3)v lin ?0.3 to 6v csh1, csh2, and csl2 (note 12) ?0.3 to 9v voltage from cboot1 to sw1 and from cboot2 to sw2 ?0.3 to 5v voltage from hdrv1 to sw1 and from hdrv2 to sw2 ?0.3v voltage from cboot1 to hdrv1 and from cboot2 hdrv2 ?0.3v junction temp. +150c power dissipation (note 3) 883 mw ambient storage temp. (t j ) ?65 to +150c soldering dwell time, temp. (note 4) wave 4 sec, 260c infrared 10 sec, 240c vapor phase 75 sec, 219c esd rating (note 5) 2 kv operating ratings (notes 1, 2) v in 5.5 to 30v junction temp. (t j ) 0 to +125c electrical characteristics typicals and limits appearing in regular type apply for t j = 25c. limits appearing in boldface type apply over the entire junc- tion temperature range for operation, 0 to +125c. unless otherwise specified under the parameter or conditions columns, v in = 10v, and v sd =v on/off1 =v on/off2 = 5v. (notes 2, 6, 7) symbol parameter conditions typical limit units system v in input supply voltage range 5.5 v(min) 30 v(max) v out1 output voltage adjustment range 2.2 v(min) 6.0 v(max) v out2 output voltage adjustment range 2.2 v(min) 8.0 v(max) d v out /v out load regulation 0 mv (csh1-csl1) 80 mv, 0mv (csh2-csl2) 80 mv 0.5 % d v out / d v in line regulation 5.5v v in 30v 0.002 %/v i in input supply current on (note 8) 0.6 ma v fb1 =v fb2 = 1.4v, 1 ma(max) v csh1 = 5.2v, v csl1 = 5v, v csh2 = 3.5v, v csl2 = 3.3v standing by (note 9) 80 a v on/off1 =v on/off2 =0v 150 a(max) shut down (note 10) 25 a v sd =0v 60 a(max) i ss1 ,i ss2 soft-start source current v ss1 =v ss2 = 1v 4.75 a 2.0 a(min) 7.0 a(max) soft-start sink current 10 a v pcl positive current limit voltage (voltage from csh1 to csl1 and from csh2 to csl2) 100 mv 80 mv(min) 140 mv(max) v ncl negative current limit voltage (voltage from csh1 to csl1 and from csh2 to csl2) v 2ndfb/fpwm = 0.8v ?100 mv ?80 mv(min) ?140 mv(max) lm2641 www.national.com 5
electrical characteristics (continued) typicals and limits appearing in regular type apply for t j = 25c. limits appearing in boldface type apply over the entire junc- tion temperature range for operation, 0 to +125c. unless otherwise specified under the parameter or conditions columns, v in = 10v, and v sd =v on/off1 =v on/off2 = 5v. (notes 2, 6, 7) symbol parameter conditions typical limit units v out undervoltage shutdown latch threshold 70 % 60 %(min) 80 %(max) v out overvoltage shutdown latch threshold 150 % 135 %(min) 165 %(max) secondary feedback threshold voltage (2ndfb/fpwm) 2.5 v 2.4 v(min) 2.6 v(max) (2ndfb/fpwm) pin pull-up current v sfb = 2.4v v on/off1 =0v v on/off2 =5v 40 80 a(max) (2ndfb/fpwm) pin input leakage current 0.1 a gate drive v boot bootstrap voltage (voltage from cboot1 to sw1 and from cboot2 to sw2) cboot1 and cboot2 source 1a each 4.5 v 4.3 v(min) hdrv1 and hdrv2 sink and source current 0.35 a ldrv1 and ldrv2 sink and source current 0.35 a hdrv1 and hdrv2 high-side on-resistance v cboot1 =v cboot2 = 5v, v sw1 = v sw2 =0v 6 w hdrv1 and hdrv2 low-side on-resistance v cboot1 =v cboot2 = 5v, v sw1 = v sw2 =0v 4 w ldrv1 and ldrv2 high-side on-resistance v lin =5v 8 w ldrv1 and ldrv2 low-side on-resistance v lin =5v 4 w oscillator f osc oscillator frequency 300 khz 255 khz(min) 345 khz(max) minimum off-time v fb1 =1v, measured at hdrv1 250 ns 350 ns(max) maximum frequency of synchronization 400 khz(min) minimum width of synchronization pulses sync pulses are low-going 200 ns(min) error amplifier i fb1 ,i fb2 feedback input bias current v fb1 =v fb2 = 1.4v 100 na 250 na(max) i comp1 ,i comp2 comp output source current v fb1 =v fb2 = 1v, v comp1 = v comp2 =1v 90 a 40 a(min) i comp1 ,i comp2 comp output sink current v fb1 =v fb2 = 1.4v, v comp1 = v comp2 = 0.2v 60 a 40 a(min) voltage references and linear voltage regulator lm2641 www.national.com 6
electrical characteristics (continued) typicals and limits appearing in regular type apply for t j = 25c. limits appearing in boldface type apply over the entire junc- tion temperature range for operation, 0 to +125c. unless otherwise specified under the parameter or conditions columns, v in = 10v, and v sd =v on/off1 =v on/off2 = 5v. (notes 2, 6, 7) symbol parameter conditions typical limit units v bg bandgap voltage 1.238 v v ref reference voltage 0.01 ma i ref 5 ma source, v lin 6v 2.5 v 2.45 v(min) 2.55 v(max) v lin output voltage of the linear voltage regulator 6v v in 30v, 0ma i lin 25 ma 5v 4.6 v(min) 5.4 v(max) v uvlo undervoltage lockout threshold (note 11) 4.0 v 3.6 v(min) 4.4 v(max) lin-to-v out switch-over threshold v out taken at csl1 4.8 v logic inputs v ih minimum high level input voltage (sd, on/off1, on/off2, and sync) 2.4 v(min) v ih minimum high level input voltage (2ndfb/fpwm) 2.6 v(min) v il maximum low level input voltage (sd, on/off1, on/off2, sync, and 2ndfb/fpwm) 0.8 v(max) maximum input leakage current (sd, on/off1, on/off2, and sync) logic input voltage 0 or 5v 0.1 a note 1: unless otherwise specified, all voltages are with respect to the voltage at the gnd and pgnd pins. note 2: absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions under which operation of the device is guaranteed. operating ratings do not imply guaranteed performance limits. for guaranteed performance limits and associated test conditions, se e the electrical characteristics tables. note 3: the absolute maximum power dissipation depends on the ambient temperature. the 883 mw rating results from substituting 150c, 70c, and 90.6c/w for t jmax ,t a , and q ja respectively into the formula p max =(t jmax -t a )/ q ja , where p max is the absolute maximum power dissipation, t jmax is the absolute maximum junction temperature, t a is the ambient temperature, and q ja is the junction-to-ambient thermal resistance of the package. a q ja of 90.6c/w represents the worst-case condition of no heat sinking of the 28-pin tssop. heat sinking allows the safe dissipation of more power. the absolute maximum power dissip ation must be derated by 11.04 mw per c above 70c ambient. the lm2641 actively limits its junction temperature to about 150c. note 4: for detailed information on soldering plastic small-outline packages, refer to the packaging databook available from national semiconductor corp oration. note 5: for testing purposes, esd was applied using the human-body model, a 100 pf capacitor discharged through a 1.5 k w resistor. note 6: a typical is the center of characterization data taken with t a =t j = 25c. typicals are not guaranteed. note 7: all limits are guaranteed. all electrical characteristics having room-temperature limits are tested during production with t a = 25c. all hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. note 8: both controllers are on but not switching. currents entering the ic at in, csl1, csh1, csl2, and csh2 are measured. those entering at csl1 and csh1 are multiplied by 0.50 to emulate the effect of a switching conversion from 10v down to 5v. those entering at csl2 and csh2 are multiplied by 0.33 to emula te the effect of a switching conversion from 10v down to 3.3v. after multiplication, all five currents are added. because the voltage at the csl1 input is g reater than the lin-to-v out switchover threshold, most of the input supply current enters the ic via the csl1 input. note 9: both switching controllers are off. the 5v, 50 ma linear regulator (output at lin) and the precision 2.5v reference (output at ref) remain on. note 10: both switching controllers and the 2.5v precision reference are off. the 5v, 50 ma linear regulator remains on. note 11: the controllers remain off until the voltage of the 5v, 50 ma linear regulator (output at lin) reaches this threshold. note 12: in applications where the output voltage can exceed the absolute maximum rating, a 100 w resistor must be placed in series with the csh and csl inputs. lm2641 www.national.com 7
block diagram 10094902 figure 3. lm2641 block diagram lm2641 www.national.com 8
typical performance charateristics efficiency vs load current efficiency vs load current efficiency vs load current 10094914 10094915 10094916 efficiency vs load current efficiency vs load current efficiency vs load current 10094917 10094918 10094919 efficiency vs load current efficiency vs load current efficiency vs load current 10094920 10094921 10094922 ref output voltage ref output voltage normalized switching output voltage vs junction temperature 10094923 10094924 10094925 lm2641 www.national.com 9
typical performance charateristics (continued) normalized error amplifier voltage vs junction temperature error amplifier gm vs junction temperature normalized oscillator frequency vs junction temperature 10094926 10094927 10094928 shutdown quiescent current and standby quiescent current vs supply voltage 10094929 lm2641 www.national.com 10
theory of operation basic operation of the current-mode controller the output voltage is held at a constant value by the main control loop, which is made up of the error amplifier , the current sense amplifier , and the pwm comparator (refer to the block diagram, figure 3 ). the lm2641 controller has two primary modes of operation: forced pulse-width modulation (fpwm) where the control- ler always operates at a fixed frequency, and pulse-skipping mode where the controller frequency decreases at reduced output loads to improve light-load efficiency. fpwm mode of operation pulling the fpwm pin low initiates a mode of operation called forced pulse-width modulation (fpwm). this means that the lm2641 will always operate at a fixed frequency, regardless of output load. the cycle of operation is: the high-side fet switch turns on at the beginning of every clock cycle, causing current to flow through the inductor. the inductor current ramps up, causing a voltage drop across the sense resistor, and this voltage is amplified by the current sense amplifier. the voltage signal from the current sense amplifier is applied to the input of the pwm comparator, where it is compared to the control level set by the error amplifier. once the current sense signal reaches this control voltage, the pwm com- parator resets the driver logic which turns off the high-side fet switch. the low-side fet switch turns on after a delay time which is the lesser of either: (a) the time it takes the sw pin voltage to reach zero (this voltage is sensed by the shoot-through protection circuitry). (b) 100 ns, which is the pre-set value for maximum delay. when operating at very light loads (in fpwm mode), the inductor current must flow in a negative direction through the low-side fet switch in order to maintain the fixed-frequency mode of operation. for this reason, the built-in zero cross detector is disabled when ever fpwm mode is activated (that is, when ever the fpwm pin is pulled to a low state). it should be noted that if the fpwm pin is high (operation described in next section), the zero cross detector will turn off the low-side fet switch anytime the inductor current drops to zero (which prevents negative inductor current). pulse-skipping mode of operation pulling the fpwm pin high allows the lm2641 to operate in pulse-skipping mode at light loads, where the switching fre- quency decreases as the output load is reduced. the con- troller will operate in fixed-frequency mode, as described in the previous section, if the output load current is sufficiently high. pulse-skipping results in higher efficiency at light loads, as decreasing the switching frequency reduces switching losses. the load current value where the transition from fixed-frequency to pulse-skipping operation occurs is the point where the inductor current goes low enough to cause the voltage measured across the current sense resistor (r4 or r13) to drop below 25 mv. in pulse-skipping mode, the high-side fet switch will turn on at the beginning of the first clock cycle which occurs after the voltage at the feedback pin falls below the reference voltage. the high-side fet switch remains on until the voltage across the current sense resistor rises to 25 mv (and then it turns off). ramp compensation all current-mode controllers require the use of ramp com- pensation to prevent subharmonic oscillations, and this com- pensation is built into the lm2641. the internal compensa- tion assumes an r sense value of 25 m w , inductor value of 6.8h, and a maximum output voltage of 6v. to prevent oscillations, the slope m of the compensation ramp must be equal to the maximum downward slope of the voltage waveform at the output of the current sense ampli- fier. the relationship of the slope m to the external compo- nents is given by: m comp =m cs amp (max) = n x r sense xv out (max) / l where: m comp is the slope of the compensation ramp. m cs amp (max) is the maximum downward slope of the voltage at the output of the current sense amplifier. n is the gain of the current sense amplifier. r sense is the value of the current sense resistor. v out (max) is the maximum output voltage. l is the inductance of the output inductor. it is important to note that since the value r sense appears in the numerator and l is in the denominator, these two values may be increased or decreased at the same ratio without changing the slope. at higher values of load current, a lower value r sense will be selected. the inductance value for the output inductor should be decreased by the same percentage to maintain correct ramp compensation. application information improved transient response if the output voltage falls below 97% of the nominal value, the low-voltage regulation (lreg) comparator will activate logic which turns on the high-side fet switch continuously until the output returns to nominal. the low-side fet switch is held off during this time. this action will improve transient response since it bypasses the error amplifier and pwm comparator, forcing the high-side switch on until the output returns to nominal. this feature is disabled during start-up. boost high-side gate drive a aflyingo bootstrap capacitor is used to generate the gate drive voltage used for the high-side fet switch. this boot- strap capacitor is charged up to about 5v using an internal supply rail and diode when ever the low-side fet switch is on. when the high-side fet switch turns on, the source is pulled up near the input voltage. the voltage across the bootstrap capacitor boosts up the gate drive voltage, ensur- ing that the gate is driven at least 4.3v higher than the source. reference the internal bandgap reference is used to generate a 2.5v reference voltage which is connected to the ref pin. the guaranteed tolerance of the ref voltage is 2% over the full operating temperature range, as long as the current drawn is 5 ma. a bypass capacitor on the ref pin is not required, but may be used to reduce noise. lm2641 www.national.com 11
application information (continued) 5v lin output the lm2641 contains a built-in 5v/50 ma ldo regulator whose output is connected to the lin pin. since this is an ldo regulator, it does require an external capacitor to main- tain stability. the minimum amount of capacitance required for stability is 4.7 f, with esr in the range of about 100 m w to 3 w . a good quality solid tantalum capacitor is recom- mended (ceramics can not be used because the esr is too low). if cold temperature operation is required, a capacitor must be selected which has an esr that is in the stable range over the entire operating temperature range of the application. since the current limit for this ldo regulator is set at about 85 ma, it can be used at load currents up to about 50 ma (assuming total ic power dissipation does not exceed the maximum value). guaranteed specifications are provided for worst-case val- ues of v lin over the full operating temperature range for load currents up to 25ma (see electrical characteristics). to es- timate how the v lin output voltage changes when going from i lin = 25ma to i lin = 50ma, a change in v lin of about ?30mv should be expected due to loading (typical value only, not guaranteed). this decrease in v lin is linear with increasing load current. it must be understood that the maximum allowable current of 50ma must include the current drawn by the gate drive circuitry. this means that the maximum current available for use at the lin pin is 50 ma minus whatever is being used internally for gate drive. the amount of current used for gate drive by each switching output can be calculated using the formula: i gd =2xqxf osc where: i gd is the gate drive current supplied by v lin . q is the gate charge required by the selected fet (see fet data sheet: gate charge characteristics). f osc is the switching frequency. example: as shown in the typical application, if the fet nds8410 is used with the lm2641, the turn-on gate voltage (v gs )is5v?v diode = 4.3v. referring to the nds8410 data sheet, the curve gate charge characteristics shows that the gate charge for this value of v gs is about 24 nc. assuming 300 khz switching frequency, the gate drive cur- rent used by each switching output is: i gd =2xqxf osc =2x(24x10 ?9 )x(3x10 5 ) = 14.4 ma if both outputs are switching, the total gate drive current drawn would be twice (28.8 ma). note that in cases where the voltage at switching output # 1 is 4.8v or higher, the internal gate drive current is obtained from that output (which means the full 50 ma is available for external use at the lin pin). sync pin the basic operating frequency of 300khz can be increased to up to 400khz by using the sync pin and an external cmos or ttl clock. the synchronizing pulses must have a minimum pulse width of 200 ns. if the sync function is not used, the sync pin must be connected to the lin pin or to ground to prevent false triggering. current limit circuitry the lm2641 is protected from damage due to excessive output current by an internal current limit comparator, which monitors output current on a cycle-by-cycle basis. the cur- rent limiter activates when ever the absolute magnitude of the voltage developed across the output sense resistor ex- ceeds 100 mv (positive or negative value). if the sensed voltage exceeds 100 mv, the high-side fet switch is turned off. if the sensed voltage goes below -100 mv, the low-side fet switch is turned off. it should be noted that drawing sufficient output current to activate the current limit circuits can cause the output voltage to drop, which could result in a under-voltage latch-off condition (see next section). under-voltage/over-voltage protection the lm2641 contains protection circuitry which activates if the output voltage is too low (uv) or too high (ov). in the event of either a uv or ov fault, the lm2641 is latched off and the high-side fet is turned off, while the low-side fet is turned on. if the output voltage drops below 70% of nominal value, the under-voltage comparator will latch off the lm2641. to restore operation, power to the device must be shut off and then restored. it should be noted that the uv latch provides protection in cases where excessive output current forces the output voltage down. the uv latch circuitry is disabled during start-up. if the output voltage exceeds 150% of nominal, the over-voltage comparator latches off the lm2641. as stated before, power must be cycled off and then on to restore operation. it must be noted that the ov latch can not protect the load from damage in the event of a high-side fet switch failure (where the fet shorts out and connects the input voltage to the load). protection for the load in the event of such a failure can be implemented using a fuse in the power lead. since the low-side fet switch turns on whenever the ov latch acti- vates, this would blow a series fuse if the fet and fuse are correctly sized. soft-start an internal 5 a current source connected to the soft-start pins allows the user to program the turn-on time of the lm2641. if a capacitor is connected to the ss pin, the voltage at that pin will ramp up linearly at turn on. this voltage is used to control the pulse widths of the fet switches. the pulse widths start at a very narrow value and linearly increase up to the point where the ss pin voltage is about 1.3v. at that time, the pulse-to-pulse current limiter controls the pulse widths until the output reaches its nominal value (and the pwm current-mode control loop takes over). the lm2641 contains a digital counter (referenced to the oscillator frequency) that times the soft-start interval. the maximum allotted ss time period is 4096 counts of the oscillator clock, which means the time period varies with oscillator frequency: max. allowable ss interval = 4096 / f osc lm2641 www.national.com 12
application information (continued) if the output voltage does not move to within ?1% of nominal in the period of 4096 counts, the device will latch off. to restore operation, the power must be cycled off to on. minimum pulse width as the input voltage is increased, the pulse widths of the switching fet's decreases. if the pulse widths become nar- rower than 350ns, pulse jitter may occur as the pulses alternate with slightly different pulse widths. this is does not affect regulator stability or output voltage accuracy. start-up issues the lm2641 contains an output undervoltage protection circuit which is made up of a digital counter and a compara- tor which monitors v out . during turn-on, the counter begins counting clock cycles when the input voltage reaches ap- proximately 3v. if the counter reaches 4096 cycles before the output voltage rises to within 1% of nominal value, the ic will be latched off in an undervoltage fault condition. the function of this protection is to shut the regulator off if the output is overloaded (such as a short to ground). however, the uv latch can cause start-up problems if the circuit is not properly designed. the following two sections explain how to avoid these types of problems: input voltage rise time if the input voltage rises too slowly, the lm2641 will latch off in an undervoltage condition. to avoid this problem, the input voltage must rise quickly enough to allow the output to get into regulation before the 4096 count time interval elapses. for a switching frequency of 300 khz, 4096 cycles will be completed in 13.6 milliseconds. in reality, the total rise time of v in should not approach the 4096 clock cycle limit if reliable start-up is to be assured. it should be noted that the total rise time of v in is also affected by current loading when the power converter begins switch- ing (which draws power from the input capacitors) causing their voltage to sag (details of input capacitor requirements are outlined in the next section). it is also important to note that this type of start-up problem is more likely to occur at higher values of output voltage, since the input voltage must rise to a higher voltage to allow the output voltage to regulate (which means the input dv/dt rate has to be faster). the recommended output voltage limit of 6v should not be exceeded. input capacitance the amount and type of input capacitance present is directly related to how well the regulator can start up. the reason is that the input capacitors serve as the source of energy for the power converter when the regulator begins switching. typically, the input voltage (which is the voltage across the input capacitors) will sag as the power converter starts draw- ing current which will cause a dip in v in as it is ramping up. if the input capacitors are too small or have excessive esr, the input volatge may not be able to come up fast enough to allow the output volatge to get into regulation before the digital clock counts off 4096 cycles and the part will latch off as an undervoltage fault. to prevent this type of start-up problem: 1. the input capacitors must provide sufficient bulk capaci- tance and have low impedance. solid tantalum capaci- tors designed for high-frequency switching applications are recommended as they generally provide the best cost/performance characteristics and maintain a very low esr even at cold temperatures. ceramic capacitors also have very low esr over the full temperature range, but x5r/x7r dielectric types should be used to assure sufficient capacitance will be provided (z5u or y5f types are not suitable). some of the newer electrolytic types such as poscap, oscon, and polymer electrolytic may also be usable as input capacitors. however, care must be taken if the application will be used at low temperatures as the esr of these capacitors may increase significantly at tem- peratures below 0c. most aluminum electrolytes are not usable with this ic at temperatures below this limit. check the esr specifications of the selected capacitor carefully if low temperature operation will be required. 2. the input capacitors must be physically located not more than one centimeter away from the switching fet's, as trace inductance in the switching current path can cause problems. loop compensation the lm2641 must be properly compensated to assure stable operation and good transient response. as with any control loop, best performance is achieved when the com- pensation is optimized so that maximum bandwidth is ob- tained while still maintaining sufficient phase margin for good stability. best performance for the lm2641 is typically obtained when the loop bandwidth (defined as the frequency where the loop gain equals unity) is in the range of f osc /10 to f osc /5. in the discussion of loop stability, it should be noted that there is a high-frequency pole f p (hf), whose frequency can be approximated by: f p (hf) ~ f osc /2xq s (assumes q s < 0.5) where: as can be seen in the approximation for q s , the highest frequency for f p (hf) occurs at the maximum value of v in . the lowest frequency for f p (hf) is about f osc /10 (when v in = 4.5v and v out = 1.8v). as noted above, the location of the pole f p (hf) is typically in the range of about f osc /10 to f osc /4. this pole will often be near the unity-gain crossover frequency, and it can signifi- cantly reduce phase margin if left uncompensated. fortu- nately, the esr of the output capacitor(s) forms a zero which is usually very near the frequency of f p (hf), and provides cancellation of the negative phase shift it would otherwise cause. for this reason, the output capacitor must be care- fully selected. most of the loop compensation for the lm2641 is set by an r-c network from the output of the error amplifier to ground (see figure 4 ). since this is a transconductance amplifier, it has a very high output impedance (160 k w ). lm2641 www.national.com 13
application information (continued) the components shown will add poles and zeros to the loop gain as given by the following equations: c10 adds a pole whose frequency is given by: f p (c10) = 1 / [2 p x c10 (r11 + 160k) ] c12 adds a pole whose frequency is given by: f p (c12) = 1 / [2 p x c12 (r11 || 160k) ] r11 adds a zero whose frequency is given by: f z (r11) = 1 / [2 p x r11 (c10 + c12) ] the output capacitor adds both a pole and a zero to the loop: f p (c out )=1/[2 p xr l xc out ] f z (esr) = 1 / [2 p xesrxc out ] where r l is the load resistance, and esr is the equivalent series resistance of the output capacitor(s). the function of the compensation components will be ex- plained in a qualitative discussion of a typical loop gain plot for an lm2641 application, as illustrated in figure 5 . c10 and r11 form a pole and a zero. changing the value of c10 moves the frequency of both the pole and the zero. changing r11 moves the zero without significantly affecting the pole. the c10 pole is typically referred to as the dominant pole, and its primary function is to roll off loop gain and reduce the bandwidth. the r11 zero is required to add some positive phase shift to offset some of the negative phase shift from the two low-frequency poles. without this zero, these two poles would cause ?180 of phase shift at the unity-gain crossover, which is clearly unstable. best results are typically obtained if r11 is selected such that the frequency of f z (r11) is in the range of f c /4 to f c where f c is the unity-gain crossover fre- quency. the output capacitor (along with the load resistance r l ) forms a pole shown as f p (c out ). although the frequency of this pole varies with r l , the loop gain also varies proportion- ally which means the unity-gain crossover frequency stays essentially constant regardless of r l value. c12 can be used to create an additional pole most often used for bypassing high-frequency switching noise on the comp pin. in many applications, this capacitor is unneces- sary. if c12 is used, best results are obtained if the frequency of the pole is set in the range f osc /2 to 2f osc . this will provide bypassing for the high-frequency noise caused by switching transitions, but add only a small amount of negative phase shift at the unity-gain crossover frequency. the esr of c out (as well as the capacitance of c out ) form the zero f z (esr), which typically falls somewhere between 10khz and 50khz. this zero is very important, as it cancels phase shift caused by the high-frequency pole f p (hf). it is important to select c out with the correct value of capaci- tance and esr to place this zero near f c (typical range f c /2 to f c ). as an example, we will present an analysis of the loop gain plot for a 3.3v design. values used for calculations are: v in = 12v v out = 3.3v @ 4a c out = c14 + c16 = 200 f esr=60m w (each) = 30m w total f osc = 300khz f p (hf) ~ 40khz r13 = 20m w l2 = 6.8 h r l = 0.825 w dc gain = 55db the values of compensation components will be: c10 = 2200 pf, r11 = 8.2k, and c12 will not be used. using this data, the poles and zeros are calculated: f p (c10) = 1 / [2 p x c10 (r11 + 160k) ] = 430hz f z (r11) = 1 / [2 p x r11 (c10 + c12) ] = 8.8khz f p (c out )=1/[2 p xr l xc out ] = 960hz f z (esr) = 1 / [2 p xesrxc out ] = 27khz f p (hf) ~ 40khz using these values, the calculated gain plot is shown in figure 6 . 10094905 figure 4. typical compensation network 10094906 figure 5. typical loop gain plot lm2641 www.national.com 14
application information (continued) looking at the plot, it can be seen that the unity-gain cross- over frequency f c is expected to be about 25khz. using this value, the phase margin at the point is calculated to be about 84. to verify the accuracy of these calculations, the circuit was bench tested using a network analyzer. the measured gain and phase are shown plotted in figure 7 . the measured gain plot agrees very closely to the predicted values. the phase margin at 0db is slightly less than pre- dicted (71 vs. 84), which is to be expected due to the negative phase shift contributions of high frequency poles not included in this simplified analysis. it should be noted that 70 phase margin with 25khz band- width is excellent, and represents the optimal compensation for this set of values for v in ,v out , inductor and r l . optimizing stability the best tool for measuring both bandwidth and phase margin is a network analyzer. if this is not available, a simple method which gives a good measure of loop stability is to apply a minimum to maximum step of output load current and observe the resulting output voltage transient. a design which has good phase margin ( > 50) will typically show no ringing after the output voltage transient returns to its nomi- nal value. it should be noted that the stability (phase margin) does not have to be optimal for the regulator to be stable. the design analyzed in the previous section was re-compensated by changing r11 and c10 to intentionally reduce the phase margin to about 35 and re-tested for step response. the output waveform displayed slight ringing after the initial re- turn to nominal, but was completely stable otherwise. in most cases, the compensation components shown in the typical application circuits will give good performance. to assist in optimizing phase margin, the following guidelines show the effects of changing various components. c out : increasing the capacitance of c out moves the fre- quency of the pole f p (c out ) to a lower value and reduces loop bandwidth. increasing c out can be beneficial (increas- ing the phase margin) if the loop bandwidth is too wide ( > f osc /5) which places the high-frequency poles too close to the unity-gain crossover frequency. esr of c out : the esr forms a zero f z (esr), which is needed to cancel negative phase shift near the unity-gain frequency. high-esr capacitors can not be used, since the zero will be too low in frequency which will make the loop bandwidth too wide. r11/c10: these form a pole and a zero. changing the value of c10 changes the frequency of both the pole and zero. note that since this causes the frequency of both the pole and zero to move up or down together, adjusting the value of c10 does not significantly affect loop bandwidth. changing the value of r11 moves the frequency location of the zero f z (r11), but does not significantly shift the c10 pole (since the value of r11 is much less than the 160k w output impedance of the gm amplifier). since only the zero is moved, this affects both bandwidth and phase margin. this means adjusting r11 is an easy way to maximize the posi- tive phase shift provided by the zero. best results are typi- cally obtained if f z (r11) is in the frequency range of f c /4 to f c (where f c is the unity-gain crossover frequency). design procedure this section presents guidelines for selecting external com- ponents. inductor selection in selecting an inductor, the parameters which are most important are inductance, current rating, and dc resistance. inductance it is important to understand that all inductors are not created equal, as the method of specifying inductance varies widely. it must also be noted that the inductance of every inductor decreases with current. the core material, size, and con- struction type all contribute the the inductor's dependence on current loading. some inductors exhibit inductance curves which are relatively flat, while others may vary more than 2:1 from minimum to maximum current. in the latter 10094907 figure 6. calculated gain plot for 3.3v/4a application 10094908 figure 7. measured gain/phase plot for 3.3v/4a application lm2641 www.national.com 15
design procedure (continued) case, the manufacturer's specified inductance value is usu- ally the maximum value, which means the actual inductance in your application will be much less. an inductor with a flatter inductance curve is preferable, since the loop characteristics of any switching converter are affected somewhat by inductance value. an inductor which has a more constant inductance value will give more consis- tent loop bandwidth when the load current is varied. the data sheet for the inductor must be reviewed carefully to verify that the selected component will have the desired inductance at the frequency and current for the application. current rating this specification may be the most confusing of all when picking an inductor, as manufacturers use different methods for specifying an inductor's current rating. the current rating specified for an inductor is typically given in rms current, although in some cases a peak current rating will also be given (usually as a multiple of the rms rating) which gives the user some indication of how well the inductance operates in the saturation region. other things being equal, a higher peak current rating is preferred, as this allows the inductor to tolerate high values of ripple current without significant loss of inductance. in the some cases where the inductance vs. current curve is relatively flat, the given current rating is the point where the inductance drops 10% below the nominal value. if the induc- tance varies a lot with current, the current rating listed by the manufacturer may be the acenter pointo of the curve. this means if that value of current is used in your application, the amount of inductance will be less than the specified value. dc resistance the dc resistance of the wire used in an inductor dissipates power which reduces overall efficiency. thicker wire de- creases resistance, but increases size, weight, and cost. a good tradeoff is achieved when the inductor's copper wire losses are about 2% of the maximum output power. selecting an inductor determining the amount of inductance required for an appli- cation can be done using the formula: where: v in is the maximum input voltage. v out is the output voltage. f is the switching frequency, f osc i ripple is the inductor ripple current. in general, a good value for this is about 30% of the dc output current. it can be seen from the above equation, that increasing the switching frequency reduces the amount of required induc- tance proportionally. of course, higher frequency operation is typically less efficient because switching losses become more predominant as a percentage of total power losses. it should also be noted that reducing the inductance will increase inductor ripple current (other terms held constant). this is a good point to remember when selecting an inductor: increased ripple current increases the fet conduction losses, inductor core losses, and requires a larger output capacitor to maintain a given amount of output ripple volt- age. this means that a cheaper inductor (with less induc- tance at the operating current of the application) will cost money in other places. input capacitors the switching action of the high-side fet requires that high peak currents be available to the switch or large voltage transients will appear on the v in line. to supply these peak currents, a low esr capacitor must be connected between the drain of the high-side fet and ground. the capacitor must be located as close as possible to the fet (maximum distance = 0.5 cm). a solid tantalum or low esr aluminum electrolytic can be used for this capacitor. if a tantalum is used, it must be able to withstand the turn-on surge current when the input power is applied. to assure this, the capacitor must be surge tested by the manufacturer and guaranteed to work in such appli- cations. caution: if a typical off-the-shelf tantalum is used that has not been surge tested, it can be blown during power-up and will then be a dead short. this can cause the capacitor to catch fire if the input source continues to supply current. voltage rating for an aluminum electrolytic, the voltage rating must be at least 25% higher than the maximum input voltage for the application. tantalum capacitors require more derating, so it is recom- mended that the selected capacitor be rated to work at a voltage that is about twice the maximum input voltage. current rating capacitors are specified with an rms current rating. to determine the requirement for an application, the following formula can be used: it is also recommended that a 0.1f ceramic capacitor be placed from v in to ground for high frequency bypassing, located as close as possible to the v in pin. output capacitors the output capacitor(s) are critical in loop stability (covered in a previous section) and also output voltage ripple. the types best suited for use as output capacitors are alu- minum electrolytics and solid tantalum. aluminum electrolytics the primary advantage of aluminum electrolytics is that they typically give the maximum capacitance-to-size ratio, and they are reasonably priced. however, it must be noted that aluminum electrolytics used in high-performance switching regulator designs must be high frequency, low esr types such as sanyo oscon or panasonic hfq which are spe- cifically designed for switching applications. capacitors such as these with good high frequency ( 3 100khz) specifications are not cheap. aluminum electrolytic capacitors should generally not be used in switching regulator applications where the ambient temperature goes below 0c. a typical low-voltage aluminum electrolytic has an esr vs. temperature curve that is fairly flat from 25c to 125c. however, a temperature change from 25c to 0c will approximately double the esr, and it will double again going from 0c down to ?20c. tantalum lm2641 www.national.com 16
design procedure (continued) solid tantalum capacitors are best in applications which must operate over a wide temperature range. a good quality tantalum will typically exhibit less than 2:1 change in esr over the temperature range of +125c to ?40c. recom- mended types are sprague 593d, sprague 594d, and avx tps series. selecting an output capacitor the required value of output capacitance is directly related to the specification for the maximum amount of output volt- age ripple allowed in the application. since esr effects the ripple voltage, it is important to have a guideline for esr. the maximum allowed esr can be calculated as follows. v ripple =i ripple * esr(max) using v = ldi/dt v out =l * i ripple /{(1?d)t s }=l * i ripple * f s /(1?d) i ripple =v out * (1?d)/)l * f s ) esr(max) = v ripple /i ripple a reasonable value for c out can be obtained by choosing capacitors with net esr less than 1 2 of esr(max). hence, esr(max) = v ripple * l * f s /{v out (1?d)} the value of c out necessary to meet the voltage ripple specification can be found using the approximation: where: i ripple is the inductor ripple current. v ripple is the output ripple voltage. esr is the equivalent series resistance of the output capaci- tor. f is the switching frequency, f s . t s = 1/f s . d = duty cycle. the esr term predominates in determining output ripple voltage. good quality tantalum capacitors have guaranteed maximum specifications for esr, but the typical values for esr are usually considerably lower than the maximum limit. power mosfets two n-channel logic-level mosfets are required for each output. the voltage rating should be at least 1.2 times the maximum input voltage. maximizing efficiency for a design requires selecting the right fet. the on-resistance of the fet determines the on-state (conduction) losses, while gate charge defines the losses during switch transitions. these two parameters require a trade-off, since reducing on-resistance typically requires increasing gate capacitance (which increases the charge required to switch the fet). improved fets are currently being released which are designed specifically for optimized on-resistance and gate charge characteristics. the v in and v out for a specific application determines the on time of each switch. in some cases where one fet is on most of the time, efficiency may be improved slightly by selecting a low on-resistance fet for one of the fet switches and a different type with lower gate charge require- ment for the other fet switch. however, for most applica- tions this would give no measurable improvement. current sense resistor a sense resistor is placed between the inductor and the output capacitor to measure the inductor current. the value of this resistor is set by the current limit voltage of the lm2641 (see electrical characteristics) and the maximum (peak) inductor current. the value of the sense resistor can be calculated from: where: v cl (min) is the minimum specified current limit voltage (see electrical characteristics). i max is the maximum output current for the application. i ripple is the inductor ripple current for the application. tol is the tolerance (in %) of the sense resistor. the physical placement of the sense resistors should be as close as possible to the lm2641 to minimize the lead length of the connections to the csh and csl pins. keeping short leads on these connections reduces the amount of switching noise conducted into the current sense circuitry of the lm2641. external diodes fet diodes both of the low-side mosfet switches have an external schottky diode connected from drain to source. these di- odes are electrically in parallel with the intrinsic body diode present inside the fet. these diodes conduct during the dead time when both fets are off and the inductor current must be supplied by the catch diode (which is either the body diode or the schottky diode). converter efficiency is improved by using external schottky diodes. since they have much faster turn-off recovery than the fet body diodes, switching losses are reduced. the voltage rating of the schottky must be at least 25% higher than the maximum input voltage. the average current rating of the diode needs to be only about 30% of the output current, because the duty cycle is low. the physical placement of the schottky diode must be as close as possible to the fet, since any parasitic (lead) inductance in series with the schottky will slow its turn-on and cause current to flow through the fet body diode. bootstrap diodes as shown in the block diagram for the lm2641, the cboot pin has an internal diode which is connected to the 5v internal rail (which is also connected to the lin pin). this diode charges up the bootstrap capacitor to about 5v when the low-side fet switch turns on and pulls its drain down to ground. the internal diode works well until the pulse widths get extremely narrow, and then the charge applied to the bootstrap capacitor can become insufficient to fully turn on the gate of the fet. for this reason, an external diode should be used which connects directly between the bootstrap capacitor and the external capacitor connected to the lin pin (c17). a fast-recovery silicon diode should be used which has an average current rating 3 50 ma, with voltage rating > 30v. lm2641 www.national.com 17
design procedure (continued) output diodes it is recommended that diodes be placed between the regu- lated outputs and ground to prevent the outputs from swing- ing below ground. the diode used may be a schottky or silicon type, and should have a current rating of 1a or more. if the outputs are allowed to swing below ground more than a vbe, the substrate of the lm2641 will become forward biased which will cause the part to operate incorrectly. an- other potential problem which could be caused by negative output transients is damage to the output capacitors, since tantalum capacitors can be damaged if a reverse voltage is forced across them the operating conditions where this can occur are not typi- cal: it can happen if one or both of the outputs are very lightly loaded, and an undervoltage (or overvoltage) condition is detected. when this happens, the lm2641 turns off the switching oscillator and turns on both of the low-side fet's which abruptly grounds one end of the inductor. when this happens, the other end of the inductor (which is connected to the regulated output) will experience a transient ringing voltage as the energy stored in the inductor is discharged. the amplitude and duration of the ringing is a function of the r-l-c tank circuit made up the output capacitance, inductor, and resistance of the inductor windings. because of this, the choice of inductor influences how large in amplitude the ringing will be. in tests performed on the typical application circuit, the sumida inductor showed less ringing than the pulse inductor, but both showed a voltage transient that would go slightly below ground. for this rea- son, the output diodes are recommended. lm2641 www.national.com 18
physical dimensions inches (millimeters) unless otherwise noted 28-lead tssop (mtc) order number LM2641MTC-ADJ ns package number mtc28 life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. national semiconductor corporation americas tel: 1-800-272-9959 fax: 1-800-737-7018 email: support@nsc.com national semiconductor europe fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer response group tel: 65-2544466 fax: 65-2504466 email: ap.support@nsc.com national semiconductor japan ltd. tel: 81-3-5639-7560 fax: 81-3-5639-7507 www.national.com lm2641 dual adjustable step-down switching power supply controller national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the righ t at any time without notice to change said circuitry and specifications.

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