mcf5213 coldfire ? integrated microcontroller reference manual additional devices supported: mcf5211 mcf5212 mcf5213rm rev 1.1 07/2005 ( datasheet : )
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mcf5213 reference manual, rev. 1.1 freescale semiconductor i preliminary paragraph number title page number about this book xxiii audience xxiii organization xxiii conventions xxv register figure conventions xxvi acronyms and abbreviations xxvi terminology conventions xxviii revision history xxx chapter 1 overview 1.1 mcf5213 family confi gurations ................................................................................... 1-2 1.2 block diag ram .............................................................................................................. .. 1-3 1.3 part numbers and packaging .......................................................................................... 1-4 1.4 mcf5213 family feat ures ............................................................................................. 1-4 1.4.1 v2 core overvi ew ...................................................................................................... 1-9 1.4.2 integrated debug module ........................................................................................... 1-9 1.4.3 jtag ..................................................................................................................... .... 1-10 1.4.4 on-chip memori es .................................................. .................................................. 1-10 1.4.4.1 sram ................................................................................................................... 1-10 1.4.4.2 flash .................................................................................................................. .... 1-11 1.4.5 flexcan .................................................................................................................. .1-11 1.4.6 uarts .................................................................................................................... .. 1-11 1.4.7 i 2 c bus ...................................................................................................................... 1-1 1 1.4.8 qspi ..................................................................................................................... ..... 1-11 1.4.9 dma timers (dtim0 -dtim3) ............................................................................... 1-12 1.4.10 general purpose timer (gpta/gptb) .................................................................... 1-12 1.4.11 pulse width modulation timers (pwm) .................................................................. 1-12 1.4.12 periodic interrupt timers (pit0 and pit1) .............................................................. 1-12 1.4.13 software watchdog timer ........................................................................................ 1-13 1.4.14 clock module and phase lo cked loop (pll) ......................................................... 1-13 1.4.15 interrupt controller (intc) ...................................................................................... 1-13 1.4.16 dma controlle r ........................................................................................................ 1- 13 1.4.17 reset ................................................................................................................... ....... 1-13 1.4.18 gpio .................................................................................................................... ..... 1-14 contents
mcf5213 reference manual, rev. 1.1 ii freescale semiconductor preliminary contents paragraph number title page number chapter 2 signal descriptions 2.1 overview ................................................................................................................... ...... 2-1 2.2 reset signa ls .............................................................................................................. ..... 2-5 2.3 pll and clock si gnals ................................................................................................... 2-6 2.4 mode select ion ............................................................................................................. .. 2-6 2.5 external interrupt signals ............................................................................................... 2- 6 2.6 queued serial peripheral interface (qspi) ..................................................................... 2-7 2.7 i 2 c i/o signals ................................................................................................................ 2 -7 2.8 uart module sign als ................................................................................................... 2-8 2.9 dma timer signa ls ........................................................................................................ 2- 8 2.10 adc signals ............................................................................................................... .... 2-8 2.11 general purpose time r signals ...................................................................................... 2-9 2.12 pulse width modulator signals ...................................................................................... 2-9 2.13 debug support signals ................................................................................................... 2- 9 2.14 ezport signal descri ptions .. ......................................................................................... 2-10 2.15 power and ground pi ns .............................................. .................................................. 2-11 chapter 3 coldfire core 3.1 processor pipe lines ........................................................................................................ .3-1 3.2 processor register description ....................................................................................... 3-4 3.2.1 user programming model .......................................................................................... 3-4 3.2.2 data registers (d 0?d7) .............................................................................................. 3-5 3.2.3 address registers (a0?a6) ........................................................................................ 3-5 3.2.4 stack pointers (a7) ..................................................................................................... 3 -5 3.2.5 program counter (pc) ................................................................................................ 3-6 3.2.6 condition code register (ccr) ................................................................................. 3-6 3.2.7 mac register desc ription ......................................................................................... 3-7 3.2.8 supervisor register description ................................................................................. 3-8 3.2.8.1 status register (sr) ................................................................................................ 3-8 3.2.8.2 supervisor/user stack pointe rs (a7 and other_a7) .......................................... 3-9 3.2.8.3 vector base regist er (vbr) ................................................................................ 3-10 3.2.8.4 cache control regist er (cacr) .......................................................................... 3-10 3.2.8.5 access control register s (acr0, acr1) ............................................................ 3-10 3.2.8.6 memory base address register (ram bar, flashbar)-check for cf2 ((condi- tionalized 1 in rambar1 for st/df bcs ki rin does not list the number of the reg- ister. -vg 5/2005)) 3-10 3.3 memory map/register definition ................................................................................ 3-10
mcf5213 reference manual, rev. 1.1 freescale semiconductor iii preliminary contents paragraph number title page number 3.4 additions to the instructi on set architecture ............................................................... 3-11 3.5 exception processing overview ................................................................................... 3-12 3.6 exception stack fram e definition ................................................................................ 3-14 3.7 processor excepti ons .................................................. .................................................. 3-1 5 3.7.1 access error exce ption ............................................................................................ 3-15 3.7.2 address error exce ption ........................................................................................... 3-16 3.7.3 illegal instruction exception ..................................................................................... 3-16 3.7.4 divide-by-ze ro ......................................................................................................... 3- 16 3.7.5 privilege viol ation .................................................................................................... 3- 16 3.7.6 trace except ion ........................................................................................................ 3- 16 3.7.7 unimplemented line-a opcode ............................................................................... 3-17 3.7.8 unimplemented line-f opcode ............................................................................... 3-17 3.7.9 debug interrupt ......................................................................................................... 3 -17 3.7.10 rte and format error exception ............................................................................. 3-17 3.7.11 trap instruction exception ..................................................................................... 3-17 3.7.12 interrupt exception ................................................................................................... 3- 18 3.7.13 fault-on-fault halt ................................................................................................... 3- 18 3.7.14 reset exception ........................................................................................................ 3 -18 3.7.15 reset vect or ............................................................................................................ .. 3-21 3.8 instruction executi on timing ....................................................................................... 3-24 3.8.1 timing assumptions ................................................................................................. 3-24 3.8.2 move instruction exec ution times ........................................................................ 3-25 3.9 standard one operand instruct ion execution ti mes ................................................... 3-26 3.10 standard two operand instru ction execution times ................................................... 3-27 3.11 miscellaneous instruction execution time s ................................................................. 3-28 3.12 mac instruction execution times ch eck cf2 mac (emac #?s) ............................ 3-29 3.13 check cf3/cf2 mac/emacbranch in struction executi on times ........................... 3-30 chapter 4 hardware multiply/accumulate (mac) unit 4.1 overview ................................................................................................................... ...... 4-1 4.1.1 mac programming model ......................................................................................... 4-2 4.1.2 general operat ion ....................................................................................................... 4 -3 4.1.3 mac instruction set summary .................................................................................. 4-4 4.1.4 data represen tation ......... ........................................................................................... 4- 5 4.2 mac instruction execu tion timings ............................................................................. 4-5
mcf5213 reference manual, rev. 1.1 iv freescale semiconductor preliminary contents paragraph number title page number chapter 5 static ram (sram) 5.1 introducti on ............................................................................................................... ...... 5-1 5.1.1 features ................................................................................................................. ...... 5-1 5.1.2 operati on ................................................................................................................ .... 5-1 5.2 register desc ription ....................................................................................................... 5-1 5.2.1 sram base address regi ster (rambar) ............................................................... 5-2 5.2.2 sram initiali zation .................................................................................................... 5- 3 5.2.3 sram initializati on code .......................................................................................... 5-4 5.2.4 power manageme nt .................................................................................................... 5-4 chapter 6 clock module 6.1 features ................................................................................................................... ........ 6-1 6.2 modes of oper ation ........................................................................................................ 6 -1 6.2.1 normal pll m ode .................................................. .................................................... 6-1 6.2.2 1:1 pll m ode ............................................................................................................. 6-1 6.2.3 external clock mode .............................................. .................................................... 6-1 6.3 low-power mode op eration .......................................................................................... 6-2 6.4 block diag ram .............................................................................................................. .. 6-2 6.5 signal descri ptions ........................................................................................................ .6-4 6.5.1 extal .................................................................................................................... ... 6-4 6.5.2 xtal ..................................................................................................................... ..... 6-5 6.5.3 clkout ................................................................................................................... .6-5 6.5.4 clkmod[1:0] ........................................................................................................... 6-5 6.5.5 rsto .......................................................................................................................... 6-5 6.6 memory map and re gisters ............................................................................................ 6-5 6.6.1 module memory map ................................................................................................. 6-5 6.6.2 register descri ptions .................................................................................................. 6- 6 6.6.2.1 synthesizer control regi ster (syncr) ................................................................. 6-6 6.6.2.2 synthesizer status regi ster (synsr) .................................................................... 6-8 6.6.2.3 low power control regi ster (lpcr) ................................................................... 6-10 6.6.3 ppm register desc riptions ....................................................................................... 6-10 6.6.3.1 peripheral power management register high (ppmrh) .................................... 6-11 6.6.3.2 peripheral power management register low (ppmrl) ..................................... 6-12 6.7 functional descri ption .................................................................................................. 6-1 3 6.7.1 system clock m odes .............................................. .................................................. 6-13 6.7.2 clock operation du ring reset .................................................................................. 6-14 6.7.3 system clock ge neration ......................................................................................... 6-14
mcf5213 reference manual, rev. 1.1 freescale semiconductor v preliminary contents paragraph number title page number 6.7.4 pll operation .......................................................................................................... 6- 15 6.7.4.1 phase and frequency de tector (pfd ) ................................................................... 6-15 6.7.4.2 charge pump/loop filter ..................................................................................... 6-16 6.7.4.3 voltage control out put (vco) ............................................................................ 6-16 6.7.4.4 multiplication factor divider (mfd ) ................................................................... 6-16 6.7.4.5 pll lock detect ion ............................................................................................. 6-16 6.7.4.6 pll loss of lock conditions ............................................................................... 6-17 6.7.4.7 pll loss of lock reset ....................................................................................... 6-17 6.7.4.8 loss of clock de tection ....................................................................................... 6-18 6.7.4.9 loss of clock reset .............................................................................................. 6-18 6.7.4.10 alternate clock se lection ..................................................................................... 6-18 6.7.4.11 loss of clock in stop mode ................................................................................. 6-18 chapter 7 power management 7.1 introducti on ............................................................................................................... ...... 7-1 7.1.1 features ................................................................................................................. ...... 7-1 7.2 memory map/register definition .................................................................................. 7-1 7.2.1 wake-up control re gister .......................................................................................... 7-2 7.2.2 peripheral power management set re gisters (ppmsr0 & ppmsr1) ...................... 7-3 7.2.3 peripheral power management clear registers (ppmcr0 & ppmcr1) .................. 7-4 7.2.4 peripheral power ma nagement registers (ppmhr0 & ppmlr0) 7-4 7.2.5 low-power control regi ster (lpcr) ........................................................................ 7-6 7.2.6 miscellaneous control re gister (misccr) ............................................................... 7-7 7.3 functional descri ption .................................................................................................... 7 -8 7.3.1 peripheral shut down ................................................................................................. 7-8 7.3.2 limp mode ................................................................................................................ .7-8 7.3.3 low-power mode s ...................................................................................................... 7-8 7.3.3.1 run mode ............................................................................................................... 7-9 7.3.3.2 wait mode .............................................................................................................. 7-9 7.3.3.3 doze mode .............................................................................................................. 7-9 7.3.3.4 stop mode .............................................................................................................. .7-9 7.3.4 peripheral behavior in low-power modes .............................................................. 7-10 7.3.4.1 coldfire core ....................................................................................................... 7-1 0 7.3.4.2 static random-access me mory (sram) ............................................................ 7-10 7.3.4.3 clock module ....................................................................................................... 7-10 7.3.4.4 chip configurati on module .................................................................................. 7-10 7.3.4.5 reset controll er .................................................................................................... 7-1 0 7.3.4.6 system control m odule (scm) ............................................................................ 7-11
mcf5213 reference manual, rev. 1.1 vi freescale semiconductor preliminary contents paragraph number title page number 7.3.4.7 gpio ports ............................................................................................................ 7 -11 7.3.4.8 interrupt controllers (intc0) .............................................................................. 7-11 7.3.4.9 edge port .............................................................................................................. 7-11 7.3.4.10 dma controller .................................................................................................... 7-12 7.3.4.11 on-chip watchdog timer ..................................................................................... 7-12 7.3.4.12 programmable interrupt timers (p it0, pit1, pit2 and pit3) ............................ 7-12 7.3.4.13 dma timers (dtim 0?dtim3) ........................................................................... 7-12 7.3.4.14 queued serial peripheral interface (qspi) ........................................................... 7-13 7.3.4.15 uart modules (uart0, uart1, and uart2) ............................................... 7-13 7.3.4.16 i2c module ........................................................................................................... 7 -13 7.3.4.17 jtag .................................................................................................................. ... 7-13 7.3.4.18 bdm ................................................................................................................... .. 7-13 7.3.5 summary of peripheral state during low-power modes ........................................ 7-14 chapter 8 chip configuration module (ccm) 8.1 introducti on ............................................................................................................... ...... 8-1 8.1.1 block diag ram ............................................................................................................ 8-1 8.1.2 features ................................................................................................................. ...... 8-1 8.2 external signal desc riptions .......................................................................................... 8-2 8.2.1 rcon ......................................................................................................................... 8-2 8.2.2 clkmod[1:0] ........................................................................................................... 8-2 8.3 memory map/register definition .................................................................................. 8-2 8.3.1 programming m odel ................................................................................................... 8-2 8.3.2 memory map .............................................................................................................. 8 -3 8.3.3 register descri ptions .................................................................................................. 8- 3 8.3.3.1 chip configuration re gister (ccr ) ....................................................................... 8-3 8.3.3.2 reset configuration regi ster (rcon) ................................................................... 8-4 8.3.3.3 chip identification re gister (cir) ......................................................................... 8-5 8.4 functional descri ption .................................................................................................... 8 -5 8.4.1 reset configur ation .................................................................................................... 8- 6 8.4.2 output pad strength c onfiguration ............................................................................ 8-7 8.4.3 clock mode sel ection ................................................................................................. 8-7 8.5 reset ...................................................................................................................... .......... 8-7 chapter 9 reset controller module 9.1 features ................................................................................................................... ........ 9-1
mcf5213 reference manual, rev. 1.1 freescale semiconductor vii preliminary contents paragraph number title page number 9.2 block diag ram .............................................................................................................. .. 9-1 9.3 signals .................................................................................................................... ......... 9-2 9.3.1 rsti ............................................................................................................................ 9- 2 9.3.2 rsto .......................................................................................................................... 9-2 9.4 memory map and re gisters ............................................................................................ 9-2 9.4.1 reset control regist er (rcr) .................................................................................... 9-2 9.4.2 reset status regist er (rsr) ....................................................................................... 9-3 9.5 functional descri ption .................................................................................................... 9 -4 9.5.1 reset sources ............................................................................................................ .. 9-4 9.5.1.1 power-on rese t ...................................................................................................... 9-5 9.5.1.2 external re set ......................................................................................................... 9-5 9.5.1.3 loss-of-clock re set ............................................................................................... 9-5 9.5.1.4 loss-of-lock re set ............................................. .................................................... 9-6 9.5.1.5 software re set ........................................................................................................ 9 -6 9.5.1.6 lvd reset .............................................................................................................. 9-6 9.5.2 reset control flow ..................................................................................................... 9- 6 9.5.2.1 synchronous reset requests .................................................................................. 9-8 9.5.2.2 internal reset re quest ........................................ .................................................... 9-8 9.5.2.3 power-on reset/low-voltage detect reset .......................................................... 9-8 9.5.3 concurrent re sets ....................................................................................................... 9 -8 9.5.3.1 reset flow ............................................................................................................. .9-8 9.5.3.2 reset status flags ................................................................................................... 9- 9 chapter 10 system control module (scm) 10.1 overview .................................................................................................................. ..... 10-1 10.2 features .................................................................................................................. ....... 10-1 10.3 memory map and regist er definition .......................................................................... 10-2 10.4 register descri ptions .................................................................................................... 1 0-2 10.4.1 internal peripheral system base address register (ipsbar) ................................. 10-2 10.4.2 memory base address regi ster (rambar) .......................................................... 10-3 10.4.3 core reset status regi ster (crsr) .......................................................................... 10-5 10.4.4 core watchdog control regi ster (cwcr) .............................................................. 10-6 10.4.5 core watchdog service regi ster (cwsr) ............................................................... 10-8 10.5 internal bus arbi tration ................................................................................................ 10 -8 10.5.1 overview ................................................................................................................ ... 10-8 10.5.2 arbitration algor ithms ............................................................................................. 10-9 10.5.2.1 round-robin mode .............................................................................................. 10-9 10.5.2.2 fixed mode ........................................................................................................... 1 0-9 10.5.3 bus master park regi ster (mpark) ...................................................................... 10-10
mcf5213 reference manual, rev. 1.1 viii freescale semiconductor preliminary contents paragraph number title page number 10.6 system access control unit (sacu) ......................................................................... 10-11 10.6.1 overview ................................................................................................................ . 10-12 10.6.2 features ................................................................................................................ ... 10-12 10.6.3 memory map/register definition .......................................................................... 10-14 10.6.3.1 master privilege regi ster (mpr) ....................................................................... 10-14 10.6.3.2 peripheral access control regi sters (pacr0?pacr8) .................................... 10-15 10.6.3.3 grouped peripheral access control re gisters (gpacr0 & gpacr1) ............ 10-16 chapter 11 general purpose i/o module 11.1 introducti on .............................................................................................................. ..... 11-1 11.2 overview .................................................................................................................. ..... 11-2 11.3 features .................................................................................................................. ....... 11-2 11.4 signal descri ptions ....................................................................................................... 11-2 11.5 memory map/register definition ................................................................................ 11-3 11.5.1 ports memory map ................................................................................................... 11-3 11.6 register descri ptions .................................................................................................... 1 1-4 11.6.1 port output data regi sters (portn) ....................................................................... 11-4 11.6.2 port data direction re gisters (ddrn) ..................................................................... 11-6 11.6.3 port pin data/set data regi sters (portnp/setn ) ................................................. 11-8 11.6.4 port clear output data registers (clrn) .............................................................. 11-10 11.6.5 pin assignment re gisters ....................................................................................... 11-11 11.6.5.1 dual function pin assignm ent registers ........................................................... 11-11 11.6.5.2 quad function pin assignm ent registers .......................................................... 11-12 11.6.5.3 port nq pin assignmen t register ...................................................................... 11-13 11.6.6 pad control regi sters ............................................. ................................................ 11-13 11.6.6.1 pin slew rate re gister ....................................................................................... 11-13 11.6.6.2 pin drive strength register ................................................................................ 11-13 11.7 ports interrupts .......................................................................................................... .. 11-14 chapter 12 interrupt controller module 12.1 68k/coldfire interrupt arch itecture overvi ew ........................................................... 12-1 12.1.1 interrupt controller theo ry of operation ................................................................. 12-2 12.1.1.1 interrupt recogni tion ............................................................................................ 12-3 12.1.1.2 interrupt prioriti zation ........................................ .................................................. 12-3 12.1.1.3 interrupt vector de termination ............................................................................ 12-3 12.2 memory map ................................................................................................................ 12-4
mcf5213 reference manual, rev. 1.1 freescale semiconductor ix preliminary contents paragraph number title page number 12.3 register descri ptions .................................................................................................... 1 2-5 12.3.1 interrupt pending register s (iprhn, iprln) ........................................................... 12-5 12.3.2 interrupt mask register (imrhn, imrln) .............................................................. 12-6 12.3.3 interrupt force registers (intfrchn, intfrcln) ............................................... 12-8 12.3.4 interrupt request level re gister (irlrn) ............................................................. 12-10 12.3.5 interrupt acknowledge le vel and priority regist er (iacklprn) ........................ 12-10 12.3.6 interrupt control register (icrnx, (x = 1, 2,..., 63)) .............................................. 12-11 12.3.6.1 interrupt sour ces ................................................. ................................................ 12-1 1 12.3.7 software and level n iack register s (swiackr, l1iack?l7iack) ............. 12-14 12.4 low-power wakeup operation .................................................................................. 12-15 chapter 13 edge port module (eport) 13.1 introducti on .............................................................................................................. ..... 13-1 13.2 low-power mode op eration ........................................................................................ 13-1 13.3 interrupt/general-purpose i/o pin descripti ons ........................................................... 13-2 13.4 memory map and re gisters .......................................................................................... 13-3 13.4.1 memory map ............................................................................................................ 13 -3 13.4.2 register s ............................................................................................................... ..... 13-3 13.4.2.1 eport pin assignment regi ster (eppar) ......................................................... 13-3 13.4.2.2 eport data direction re gister (epddr) .......................................................... 13-4 13.4.2.3 edge port interrupt enable register (epi er) ...................................................... 13-5 13.4.2.4 edge port data regi ster (epdr) .......................................................................... 13-5 13.4.2.5 edge port pin data re gister (eppdr) ................................................................. 13-6 13.4.2.6 edge port flag regi ster (epfr) ........................................................................... 13-6 chapter 14 dma controller module 14.1 overview .................................................................................................................. ..... 14-1 14.1.1 dma module featur es ........................................... .................................................. 14-2 14.2 dma transfer over view ............................................ .................................................. 14-3 14.3 dma controller module pr ogramming model ............................................................ 14-3 14.3.1 source address register s (sar0?sar3) ................................................................ 14-4 14.3.2 destination address regist ers (dar0?dar3) ....................................................... 14-5 14.3.3 byte count registers (bcr0?bcr3) ...................................................................... 14-5 14.3.4 dma control registers (dcr0?dcr3) .................................................................. 14-5 14.3.5 dma status registers (dsr0?dsr3) ..................................................................... 14-8 14.4 dma controller module func tional description ........................................................ 14-8
mcf5213 reference manual, rev. 1.1 x freescale semiconductor preliminary contents paragraph number title page number 14.4.1 transfer requests (cycle-steal and continuous modes) ......................................... 14-9 14.4.2 data transfer modes ................................................................................................ 14-9 14.4.2.1 dual-address tran sfers ........................................................................................ 14-9 14.4.3 channel initialization and startup .......................................................................... 14-10 14.4.3.1 channel prioritiz ation ......................................................................................... 14-10 14.4.3.2 programming the dma cont roller module ....................................................... 14-10 14.4.4 data transfer .......................................................................................................... 1 4-11 14.4.4.1 auto-alignment .................................................................................................. 14-11 14.4.4.2 bandwidth cont rol .............................................. ................................................ 14-11 14.4.5 termination ............................................................................................................. 14-11 chapter 15 coldfire flash module (cfm) 15.1 features .................................................................................................................. ....... 15-1 15.2 block diag ram ............................................................................................................. . 15-2 15.3 memory map ................................................................................................................ 15-4 15.3.1 cfm configurati on field ......................................................................................... 15-5 15.3.2 flash base address regist er (flashbar) ............................................................ 15-5 15.3.3 cfm registers .......................................................................................................... 1 5-7 15.3.4 register descri ptions ................................................................................................ 15- 8 15.3.4.1 cfm configuration regi ster (cfmcr) ............................................................... 15-8 15.3.4.2 cfm clock divider regist er (cfmclkd) ......................................................... 15-9 15.3.4.3 cfm security register (cfmsec) .................................................................... 15-10 15.3.4.4 cfm protection register (cfmprot) .............................................................. 15-11 15.3.4.5 cfm supervisor access re gister (cfmsacc) ................................................ 15-12 15.3.4.6 cfm data access regist er (cfmdacc) ......................................................... 15-13 15.3.4.7 cfm user status regist er (cfmustat) ......................................................... 15-14 15.3.4.8 cfm command register (cfmcmd) ............................................................... 15-15 15.4 cfm operation ........................................................................................................... 15 -16 15.4.1 read operati ons ...................................................................................................... 15- 16 15.4.2 write operati ons ..................................................................................................... 15- 16 15.4.3 program and erase op erations ............................................................................... 15-17 15.4.3.1 setting the cfmclkd register ........................................................................ 15-17 15.4.3.2 program, erase, and ve rify sequences ............................................................... 15-18 15.4.3.3 flash valid commands ....................................................................................... 15-19 15.4.3.4 flash user mode illegal operations ................................................................... 15-21 15.4.4 stop mode ............................................................................................................... 15-21 15.5 flash security op eration ............................................................................................ 15-22 15.5.1 back door ac cess ................................................................................................... 15-23 15.5.2 erase verify ch eck ................................................. ................................................ 15-23
mcf5213 reference manual, rev. 1.1 freescale semiconductor xi preliminary contents paragraph number title page number 15.6 reset ..................................................................................................................... ....... 15-23 15.7 interrupts ................................................................................................................ ..... 15-23 chapter 16 ezport 16.1 features .................................................................................................................. ....... 16-1 16.2 modes of oper ation ...................................................................................................... 16 -1 16.3 external signal desc ription .......................................................................................... 16-2 16.3.1 overview ................................................................................................................ ... 16-2 16.3.2 detailed signal desc riptions .................................................................................... 16-2 16.3.2.1 ezpck ? ezport clock ...................................................................................... 16-2 16.3.2.2 ezpcs ? ezport chip select .............................................................................. 16-3 16.3.2.3 ezpd ? ezport serial data in ............................................................................ 16-3 16.3.2.4 ezpq ? ezport serial data out .......................................................................... 16-3 16.4 command definition .................................................................................................... 16-3 16.4.1 command descrip tions ........................................... .................................................. 16-4 16.4.1.1 write enable ......................................................................................................... 1 6-4 16.4.1.2 write disabl e ........................................................................................................ 1 6-4 16.4.1.3 read status regi ster ............................................................................................. 16-4 16.4.1.4 write configuration register ............................................................................... 16-5 16.4.1.5 read data ............................................................................................................. . 16-6 16.4.1.6 read data at high speed ...................................................................................... 16-6 16.4.1.7 page program ........................................................................................................ 16 -6 16.4.1.8 sector er ase .......................................................................................................... 16-6 16.4.1.9 bulk erase ............................................................................................................ . 16-7 16.4.1.10 reset chip ........................................................................................................... .. 16-7 16.5 functional descri ption .................................................................................................. 16 -7 16.6 initialization/applicati on informati on .......................................................................... 16-7 chapter 17 programmable interrupt ti mer modules (pit0?pit1) 17.1 introducti on .............................................................................................................. ..... 17-1 17.1.1 overview ................................................................................................................ ... 17-1 17.1.2 block diagra m .......................................................................................................... 1 7-1 17.1.3 low-power mode op eration .................................................................................... 17-1 17.2 memory map/register definition ................................................................................ 17-2 17.2.1 pit control and status register (pcsr n ) ................................................................ 17-3 17.2.2 pit modulus register (pmr n ) ................................................................................. 17-5
mcf5213 reference manual, rev. 1.1 xii freescale semiconductor preliminary contents paragraph number title page number 17.2.3 pit count register (pcntr n ) ................................................................................. 17-5 17.3 functional descri ption .................................................................................................. 17 -5 17.3.1 set-and-forget time r operation ............................................................................... 17-6 17.3.2 free-running timer op eration ................................................................................ 17-6 17.3.3 timeout specifica tions ............................................................................................. 17-6 17.3.4 interrupt oper ation ................................................................................................... 17 -7 chapter 18 general purpose timer module (gpt) 18.1 introducti on .............................................................................................................. ..... 18-1 18.2 features .................................................................................................................. ....... 18-1 18.3 block diag ram ............................................................................................................. . 18-2 18.4 low-power mode op eration ........................................................................................ 18-3 18.5 signal descri ption ........................................................................................................ . 18-3 18.5.1 gpt[2:0] ................................................................................................................ ... 18-3 18.5.2 gpt3 .................................................................................................................... ..... 18-3 18.5.3 syncn ................................................................................................................... ... 18-4 18.6 memory map and re gisters .......................................................................................... 18-4 18.6.1 gpt input capture/output compare select register (gptios) ............................. 18-5 18.6.2 gpt compare force regist er (gpcforc) ............................................................. 18-6 18.6.3 gpt output compare 3 mask register (gptoc3m) .............................................. 18-6 18.6.4 gpt output compare 3 data register (gpt oc3d) ................................................ 18-7 18.6.5 gpt counter register (gptcnt) ........................................................................... 18-7 18.6.6 gpt system control regist er 1 (gptscr1) ........................................................... 18-8 18.6.7 gpt toggle-on-overflow re gister (gpttov) ...................................................... 18-9 18.6.8 gpt control register 1 (gptctl1) ........................................................................ 18-9 18.6.9 gpt control register 2 (gptctl2) ...................................................................... 18-10 18.6.10 gpt interrupt enable re gister (gptie) ................................................................ 18-10 18.6.11 gpt system control regist er 2 (gptscr2) ......................................................... 18-11 18.6.12 gpt flag register 1 (gptflg1) ........................................................................... 18-12 18.6.13 gpt flag register 2 (gptflg2) ........................................................................... 18-12 18.6.14 gpt channel register s (gptcn) ........................................................................... 18-13 18.6.15 pulse accumulator control re gister (gptpactl) .............................................. 18-14 18.6.16 pulse accumulator flag regi ster (gptpafl g) .................................................... 18-15 18.6.17 pulse accumulator counter re gister (gptpacnt) ............................................. 18-16 18.6.18 gpt port data regist er (gptport ) ..................................................................... 18-16 18.6.19 gpt port data direction re gister (gptdd r) ....................................................... 18-17 18.7 functional descri ption ................................................................................................ 18-1 7 18.7.1 prescaler ............................................................................................................... ... 18-17 18.7.2 input captur e .......................................................................................................... 1 8-17
mcf5213 reference manual, rev. 1.1 freescale semiconductor xiii preliminary contents paragraph number title page number 18.7.3 output compar e ...................................................................................................... 18-1 8 18.7.4 pulse accumula tor .................................................................................................. 18-18 18.7.5 event counter m ode ............................................................................................... 18-18 18.7.6 gated time accumulation mode ........................................................................... 18-19 18.7.7 general-purpose i/ o ports ...................................................................................... 18-20 18.8 reset ..................................................................................................................... ....... 18-22 18.9 interrupts ................................................................................................................ ..... 18-22 18.9.1 gpt channel interr upts (cnf) ............................................................................... 18-22 18.9.2 pulse accumulator over flow (paovf) ................................................................. 18-22 18.9.3 pulse accumulator i nput (paif) ............................................................................ 18-23 18.9.4 timer overflow (tof) ........................................................................................... 18-23 chapter 19 dma timers (dtim0?dtim3) 19.1 introducti on .............................................................................................................. ..... 19-1 19.1.1 overview ................................................................................................................ ... 19-1 19.1.2 features ................................................................................................................ ..... 19-2 19.2 memory map/register definition ................................................................................ 19-2 19.2.1 prescaler ............................................................................................................... ..... 19-2 19.2.2 capture mode ........................................................................................................... 1 9-3 19.2.3 reference comp are ................................................................................................... 19-3 19.2.4 output m ode ............................................................................................................. 19-3 19.2.5 memory map ............................................................................................................ 19 -3 19.2.6 dma timer mode registers (dtmr n ) ................................................................... 19-4 19.2.7 dma timer extended mode registers (dtxmr n ) ................................................ 19-5 19.2.8 dma timer event registers (dter n ) .................................................................... 19-6 19.2.9 dma timer reference registers (dtrr n ) ............................................................. 19-7 19.2.10 dma timer capture registers (dtcr n ) ................................................................ 19-8 19.2.11 dma timer counters (dtcn n ) .............................................................................. 19-8 19.3 initialization/applicati on informati on .......................................................................... 19-9 19.3.1 code example ........................................................................................................... 1 9-9 19.3.2 calculating time-out values ................................................................................. 19-10 chapter 20 queued serial peripheral interface (qspi) 20.1 introducti on .............................................................................................................. ..... 20-1 20.1.1 block diagra m .......................................................................................................... 2 0-1 20.1.2 overview ................................................................................................................ ... 20-2
mcf5213 reference manual, rev. 1.1 xiv freescale semiconductor preliminary contents paragraph number title page number 20.1.3 features ................................................................................................................ ..... 20-2 20.1.4 external signals de scription .................................................................................... 20-2 20.1.5 modes of operat ion .................................................................................................. 20-3 20.2 memory map/register definition ................................................................................ 20-3 20.2.1 qspi mode regist er (qmr) .................................................................................... 20-3 20.2.2 qspi delay register (qdlyr) ............................................................................... 20-5 20.2.3 qspi wrap regist er (qwr) ..................................................................................... 20-6 20.2.4 qspi interrupt regi ster (qir) .................................................................................. 20-6 20.2.5 qspi address regist er (qar) ................................................................................. 20-8 20.2.6 qspi data regist er (qdr) ....................................................................................... 20-8 20.2.7 command ram registers (qcr0?qcr15) ............................................................ 20-8 20.3 functional descri ption ................................................................................................ 20-1 0 20.3.1 qspi ram .............................................................................................................. 20 -11 20.3.1.1 receive ram ..................................................................................................... 20-12 20.3.1.2 transmit ram .................................................................................................... 20-12 20.3.1.3 command ram .................................................................................................. 20-13 20.3.2 baud rate select ion ................................................................................................ 20-13 20.3.3 transfer delays ....................................................................................................... 20 -14 20.3.4 transfer length ....................................................................................................... 20 -15 20.3.5 data transfer .......................................................................................................... 2 0-15 20.3.6 initialization/applicati on information .................................................................... 20-16 chapter 21 uart modules 21.1 introducti on .............................................................................................................. ..... 21-1 21.1.1 overview ................................................................................................................ ... 21-1 21.1.2 features ................................................................................................................ ..... 21-2 21.2 external signal desc ription .......................................................................................... 21-3 21.3 memory map/register definition ................................................................................ 21-4 21.3.1 uart mode registers 1 (umr1 n ) ......................................................................... 21-5 21.3.2 uart mode register 2 (umr2 n ) ........................................................................... 21-6 21.3.3 uart status registers (usr n ) ............................................................................... 21-8 21.3.4 uart clock select registers (ucsr n ) .................................................................. 21-9 21.3.5 uart command registers (ucr n ) ...................................................................... 21-10 21.3.6 uart receive buffers (urb n ) ............................................................................. 21-12 21.3.7 uart transmit buffers (utb n ) ........................................................................... 21-13 21.3.8 uart input port change registers (uipcr n ) ...................................................... 21-13 21.3.9 uart auxiliary cont rol register (uacr n ) ......................................................... 21-14 21.3.10 uart interrupt status /mask registers (uisr n /uimr n ) ..................................... 21-14 21.3.11 uart baud rate generator registers (ubg1 n /ubg2 n ) ..................................... 21-16
mcf5213 reference manual, rev. 1.1 freescale semiconductor xv preliminary contents paragraph number title page number 21.3.12 uart input port register (uip n ) .......................................................................... 21-17 21.3.13 uart output port command registers (uop1 n /uop0 n ) ................................... 21-17 21.4 functional descri ption ................................................................................................ 21-1 8 21.4.1 transmitter/receiver clock source ........................................................................ 21-18 21.4.1.1 programmable di vider ........................................................................................ 21-18 21.4.1.2 calculating baud rates ....................................................................................... 21-19 21.4.1.2.1 internal bus cloc k baud rates ....................................................................... 21-19 21.4.1.2.2 external cl ock ................................................................................................ 21-19 21.4.2 transmitter and receiver operating mode s ........................................................... 21-19 21.4.2.1 transmitter .......................................................................................................... 2 1-20 21.4.2.2 receiver .............................................................................................................. 21-21 21.4.2.3 fifo .................................................................................................................. .. 21-22 21.4.3 looping modes ....................................................................................................... 21-2 3 21.4.3.1 automatic echo m ode ........................................................................................ 21-24 21.4.3.2 local loop-back mode ...................................................................................... 21-24 21.4.3.3 remote loop-back mode ................................................................................... 21-24 21.4.4 multidrop mode ...................................................................................................... 21-2 5 21.4.5 bus operati on ......................................................................................................... 21 -27 21.4.5.1 read cycles ........................................................................................................ 21- 27 21.4.5.2 write cycles ....................................................................................................... 21- 27 21.4.6 programmi ng .......................................................................................................... 21- 27 21.4.6.1 interrupt and dma request initializati on .......................................................... 21-27 21.4.6.1.1 setting up the uart to gene rate core interrupts ......................................... 21-27 21.4.6.1.2 setting up the uart to request dma service ............................................. 21-28 21.4.6.2 uart module initializa tion sequence .............................................................. 21-29 chapter 22 i 2 c interface 22.1 introducti on .............................................................................................................. ..... 22-1 22.2 overview .................................................................................................................. ..... 22-1 22.3 features .................................................................................................................. ....... 22-1 22.4 i 2 c system configur ation ............................................................................................. 22-3 22.4.1 start signal ........................................................................................................... 2 2-3 22.4.2 slave address tran smission ..................................................................................... 22-4 22.4.3 data transfer ........................................................................................................... . 22-4 22.4.4 acknowledge ............................................................................................................ 2 2-4 22.4.5 stop signal ............................................................................................................. 22-5 22.4.6 repeated start ...................................................................................................... 22-5 22.4.7 clock synchronization a nd arbitration .................................................................... 22-6 22.4.8 handshaking and clock stretching ........................................................................... 22-7
mcf5213 reference manual, rev. 1.1 xvi freescale semiconductor preliminary contents paragraph number title page number 22.5 memory map/register definition ................................................................................ 22-8 22.5.1 i 2 c address register (i2adr) ................................................................................. 22-8 22.5.2 i 2 c frequency divider regi ster (i2fdr) ................................................................. 22-9 22.5.3 i 2 c control register (i2cr) ................................................................................... 22-10 22.5.4 i 2 c status register (i2sr) ...................................................................................... 22-11 22.5.5 i 2 c data i/o register (i2dr) ................................................................................. 22-12 22.6 i 2 c programming exam ples ....................................................................................... 22-12 22.6.1 initialization se quence ............................................................................................ 22-12 22.6.2 generation of st art ............................................................................................. 22-13 22.6.3 post-transfer softwa re response ........................................................................... 22-13 22.6.4 generation of st op ................................................................................................ 22-14 22.6.5 generation of repeat ed start ............................................................................. 22-15 22.6.6 slave mode ............................................................................................................. 2 2-15 22.6.7 arbitration lo st ....................................................................................................... 2 2-15 chapter 23 analog-to-digital converter (adc) 23.1 introducti on .............................................................................................................. ..... 23-1 23.2 features .................................................................................................................. ....... 23-1 23.3 block diag ram ............................................................................................................. . 23-1 23.4 functional descri ption .................................................................................................. 23 -2 23.4.1 input mux func tion ................................................................................................ 23-5 23.4.2 adc sample conve rsion .......................................................................................... 23-6 23.4.2.1 single-ended samp les .......................................................................................... 23-7 23.4.2.2 differential sa mples ............................................................................................. 23-8 23.4.3 adc data proce ssing ............................................................................................... 23-9 23.4.4 sequential vs. parall el sampling ............................................................................ 23-10 23.4.5 scan sequenci ng ..................................................................................................... 23-1 1 23.4.6 power manageme nt ................................................................................................ 23-12 23.4.6.1 power management modes ................................................................................ 23-12 23.4.6.2 power management details ................................................................................ 23-13 23.4.6.3 adc stop mode of operation ......................................................................... 23-14 23.4.7 adc clock ............................................................................................................. 23 -14 23.4.7.1 general ............................................................................................................... . 23-14 23.4.7.2 description of cloc k operation .......................................................................... 23-15 23.4.7.3 adc clock resynchronization at start of scan ................................................. 23-15 23.4.8 voltage reference pins vrefh& vrefl ........................................................... 23-17 23.4.9 supply pins vdda and vssa ............................................................................... 23-18 23.5 register defini tions .................................................................................................... 23 -18 23.5.1 control 1 register (ctrl1) ................................................................................... 23-21
mcf5213 reference manual, rev. 1.1 freescale semiconductor xvii preliminary contents paragraph number title page number 23.5.1.1 reserved?bit 15 ................................................................................................ 23-21 23.5.1.2 stop 0 (stop0)?bit 14 .................................................................................. 23-22 23.5.1.3 start conversion (sta rt0)?bit 13 ................................................................. 23-22 23.5.1.4 synchronization 0 enable (sync0)?bit 12 ..................................................... 23-22 23.5.1.5 end of scan interrupt enab le 0 (eosie0)?bit 11 ........................................... 23-22 23.5.1.6 zero crossing interrupt en able (zcie)?bit 10 ................................................ 23-22 23.5.1.7 low limit interrupt enable (llmtie)?bit 9 .................................................. 23-23 23.5.1.8 high limit interrupt enable (hlmtie)?bit 8 ................................................. 23-23 23.5.1.9 channel configure (c hncfg)?bits 7?4 ....................................................... 23-23 23.5.1.10 scan mode control (smo de)?bits 2-0 ........................................................... 23-24 23.5.2 control 2 register (ctrl2) unde r sequential scan modes ................................. 23-25 23.5.2.1 reserved?bits 15?5 .......................................................................................... 23-26 23.5.2.2 clock divisor select (div)?bits 4?0 ............................................................... 23-26 23.5.3 control 2 register (ctrl2) unde r parallel scan modes ...................................... 23-26 23.5.3.1 reserved?bit 15 ................................................................................................ 23-27 23.5.3.2 stop (stop1)?bi t 14 ........................................................................................ 23-27 23.5.3.3 start conversion (sta rt1)?bit 13 ................................................................. 23-27 23.5.3.4 sync1 enable (sync 1)?bit 12 ..................................................................... 23-27 23.5.3.5 reserved?bits 10?6 .......................................................................................... 23-27 23.5.3.6 end of scan interrupt enab le 1 (eosie1)?bit 11 ........................................... 23-28 23.5.3.7 simultaneous mode (s imult)?bit 5 .............................................................. 23-28 23.5.3.8 clock divisor select (div)?bits 4?0 ............................................................... 23-28 23.5.4 zero crossing control regi ster (zxctrl) ........................................................... 23-29 23.5.4.1 zero crossing enable n (zcen)?bits 15?0 ...................................................... 23-29 23.5.5 channel list 1 and 2 registers (clst1 and clst2) ............................................ 23-29 23.5.5.1 reserved?bits 15, 11, 7 and 3 .......................................................................... 23-30 23.5.5.2 sample n (sample4)?bits 2, 1, and 0 ........................................................ 23-30 23.5.6 sample disable regist er (sdis) ............................................................................. 23-31 23.5.6.1 reserved?bits 15?8 .......................................................................................... 23-31 23.5.6.2 disable sample (dsn )?bits 7?0 ....................................................................... 23-31 23.5.7 status register (stat) ........................................................................................... 23-31 23.5.7.1 conversion in progress 0 (cip0)?bit 15 .......................................................... 23-32 23.5.7.2 conversion in progress 1 (cip1)?bit 14 .......................................................... 23-32 23.5.7.3 reserved?bit 13 ................................................................................................ 23-32 23.5.7.4 end of scan interrupt 1 (eosi1)?bit 12 .......................................................... 23-32 23.5.7.5 end of scan interrupt 0 (eosi0)?bit 11 .......................................................... 23-33 23.5.7.6 zero crossing interrupt (zci)?bit 10 ............................................................... 23-33 23.5.7.7 low limit interrupt ( llmti)?bit 9 ................................................................ 23-33 23.5.7.8 high limit interrupt (h lmti)?bit 8 ............................................................... 23-33 23.5.7.9 ready sample 7?0 (rdy n)?bits 7?0 ............................................................... 23-34 23.5.8 limit status register (limstat) ......................................................................... 23-34
mcf5213 reference manual, rev. 1.1 xviii freescale semiconductor preliminary contents paragraph number title page number 23.5.9 zero crossing status regi ster (zxstat) .............................................................. 23-35 23.5.9.1 reserved?bits 15?8 .......................................................................................... 23-35 23.5.9.2 zero crossing status (z cs[7:0])?bits 7?0 ....................................................... 23-35 23.5.10 result 0-7 register s (rslt0?7) ............................................................................. 23-36 23.5.10.1 sign extend (sex t)?bit 15 ............................................................................. 23-36 23.5.10.2 digital result of the c onversion (rslt)?bits 14?3 ....................................... 23-36 23.5.10.3 test data (test_da ta)?bits 14?3 ..................................................................... 23-37 23.5.10.4 reserved?bit s 2?0 ............................................................................................ 23-37 23.5.11 low and high limit registers (l olim0-7 and hili m0-7) ................................. 23-37 23.5.12 offset registers (offst0?7) ................................................................................. 23-38 23.5.13 power control regist er (pwr) .............................................................................. 23-39 23.5.13.1 auto standby (asb )?bit 15 ............................................................................. 23-40 23.5.13.2 reserved?bit s 14?13 ........................................................................................ 23-40 23.5.13.3 voltage reference power st atus 2 (psts2)?bit 12 ......................................... 23-40 23.5.13.4 converter b power status 1 (psts1)?bi t 11 ................................................... 23-40 23.5.13.5 converter a power status 0 (psts0)?bi t 10 ................................................... 23-40 23.5.13.6 power-up delay (pud elay)?bits 9?4 .......................................................... 23-40 23.5.13.7 auto power-down (apd)?bit 3 ...................................................................... 23-41 23.5.13.8 power-down control for voltage re ference circuit 2 (pd2)?bit 2 ............... 23-41 23.5.13.9 manual power-down for conve rter b (pd1)?bit 1 ......................................... 23-41 23.5.13.10 manual power-down for conve rter a (pd0)?bit 0 ......................................... 23-42 23.5.14 voltage reference regi ster (vref) ...................................................................... 23-42 23.5.14.1 select vrefh source (s el_vrefh)?bit 15 ................................................. 23-42 23.5.14.2 select vrefl source (s el_vrefl)?bit 14 ................................................. 23-42 23.5.14.3 reserved?bit s 13?0 .......................................................................................... 23-43 chapter 24 pulse width modula tion (pwm) module 24.1 introducti on .............................................................................................................. ..... 24-1 24.1.1 overview ................................................................................................................ ... 24-1 24.2 memory map/register definition ................................................................................ 24-2 24.2.1 pwm enable register (pwme) ............................................................................... 24-3 24.2.2 pwm polarity register (pwmpol) ........................................................................ 24-4 24.2.3 pwm clock select regist er (pwmclk) ................................................................ 24-4 24.2.4 pwm prescale clock select register (pwmprclk) ............................................. 24-5 24.2.5 pwm center align enable re gister (pwmcae) ................................................... 24-6 24.2.6 pwm control register (pwmctl) ......................................................................... 24-7 24.2.7 pwm scale a register (pwmscla) ...................................................................... 24-8 24.2.8 pwm scale b register (pwmsclb) ...................................................................... 24-8 24.2.9 pwm channel counter registers (pwmcnt n ) ..................................................... 24-9
mcf5213 reference manual, rev. 1.1 freescale semiconductor xix preliminary contents paragraph number title page number 24.2.10 pwm channel period registers (pwmper n ) ...................................................... 24-10 24.2.11 pwm channel duty regist ers (pwmdtyn) ........................................................ 24-11 24.2.12 pwm shutdown register (pwmsdn) .................................................................. 24-11 24.3 functional descri ption ................................................................................................ 24-1 2 24.3.1 pwm clock sel ect .................................................. ................................................ 24-12 24.3.1.1 prescaled clock (a or b) .................................................................................... 24-13 24.3.1.2 scaled clock (sa or sb) .................................................................................... 24-14 24.3.1.3 clock select ........................................................................................................ 24 -14 24.3.2 pwm channel time rs ............................................................................................ 24-14 24.3.2.1 pwm enable ....................................................................................................... 24-15 24.3.2.2 pwm polarity ..................................................................................................... 24-15 24.3.2.3 pwm period and du ty ........................................................................................ 24-15 24.3.2.4 pwm timer count ers ......................................................................................... 24-16 24.3.2.5 left-aligned out puts .......................................................................................... 24-17 24.3.2.5.1 left-aligned output example ........................................................................ 24-17 24.3.2.6 center-aligned ou tputs ...................................................................................... 24-18 24.3.2.6.1 center-aligned out put example .................................................................... 24-19 24.3.2.7 pwm 16-bit functions ....................................................................................... 24-19 24.3.2.8 pwm boundary ca ses ........................................ ................................................ 24-21 chapter 25 flexcan 25.1 introducti on .............................................................................................................. ..... 25-1 25.1.1 block diagra m .......................................................................................................... 2 5-1 25.1.1.1 the can system .................................................................................................. 25-2 25.1.2 features ................................................................................................................ ..... 25-3 25.1.3 modes of operat ion .................................................................................................. 25-3 25.1.3.1 normal mode ........................................................................................................ 25- 3 25.1.3.2 freeze mode ......................................................................................................... 25 -3 25.1.3.3 module disabled mode ........................................................................................ 25-4 25.1.3.4 loop-back mode .................................................................................................. 25-4 25.1.3.5 listen-only m ode ............................................... .................................................. 25-5 25.2 external signal desc ription .......................................................................................... 25-5 25.3 memory map/register definition ................................................................................ 25-5 25.3.1 flexcan configurati on register (canmcr n ) ...................................................... 25-6 25.3.2 flexcan control register (canctrl n ) ............................................................... 25-8 25.3.3 flexcan free running timer register (timer n ) ............................................... 25-10 25.3.4 rx mask registers (rxgmask n , rx14mask n , rx15mask n ) ...................... 25-11 25.3.5 flexcan error counter register (errcnt n ) ...................................................... 25-12 25.3.6 flexcan error and status register (errstat n ) ................................................ 25-14
mcf5213 reference manual, rev. 1.1 xx freescale semiconductor preliminary contents paragraph number title page number 25.3.7 interrupt mask register (imask n ) ....................................................................... 25-16 25.3.8 interrupt flag register (iflag n ) .......................................................................... 25-16 25.3.9 message buffer st ructure ....................................................................................... 25-17 25.4 functional overvi ew ................................................................................................... 25-2 0 25.4.1 transmit process ..................................................................................................... 25- 21 25.4.2 arbitration proc ess ................................................. ................................................ 25-2 1 25.4.3 receive pro cess ...................................................................................................... 25- 22 25.4.3.1 self-received fr ames ......................................................................................... 25-23 25.4.4 matching proce ss .................................................................................................... 25-2 3 25.4.5 message buffer handling ....................................................................................... 25-23 25.4.5.1 serial message buff ers (smbs) ......................................................................... 25-23 25.4.5.2 message buffer deactivation ............................................................................. 25-24 25.4.5.3 locking and releasing me ssage buffers ........................................................... 25-24 25.4.6 can protocol relate d frames ............................................................................... 25-25 25.4.6.1 remote frames ................................................................................................... 25-25 25.4.6.2 overload fram es ................................................................................................. 25-26 25.4.7 time stamp ............................................................................................................. 2 5-26 25.4.8 bit timing .............................................................................................................. . 25-26 25.5 flexcan initializati on sequence ............................................................................... 25-28 25.5.1 interrupts .............................................................................................................. ... 25-29 chapter 26 debug module 26.1 introducti on .............................................................................................................. ..... 26-1 26.1.1 overview ................................................................................................................ ... 26-1 26.1.1.1 the new debug module hardwa re (rev. b+) ..................................................... 26-2 26.1.1.2 enhancements over revision a ............................................................................ 26-2 26.2 external signal desc ription .......................................................................................... 26-2 26.3 real-time trace support .............................................................................................. 26-3 26.3.1 begin execution of taken br anch (pst = 0x5) ....................................................... 26-5 26.4 memory map/register definition ................................................................................ 26-6 26.4.1 revision b+ shared de bug resources ..................................................................... 26-7 26.4.2 configuration/status re gister (csr) ........................................................................ 26-7 26.4.3 bdm address attribut e (baar) ............................................................................. 26-9 26.4.4 address attribute trigger register (aat r) .......................................................... 26-10 26.4.5 trigger definition regi ster (tdr) ......................................................................... 26-11 26.4.6 program counter breakpoint/mask registers (pbr, pbmr) ................................ 26-13 26.4.7 address breakpoint register s (ablr, abhr) ..................................................... 26-14 26.4.8 data breakpoint/mask regi sters (dbr, db mr) ................................................... 26-15 26.5 background debug mode (bdm) .............................................................................. 26-16
mcf5213 reference manual, rev. 1.1 freescale semiconductor xxi preliminary contents paragraph number title page number 26.5.1 cpu halt ................................................................................................................ . 26-16 26.5.2 bdm serial interface .............................................................................................. 26-17 26.5.2.1 receive packet format ....................................................................................... 26-18 26.5.2.2 transmit packet format ...................................................................................... 26-19 26.5.3 bdm command se t ................................................................................................ 26-19 26.5.3.1 coldfire bdm comma nd format ...................................................................... 26-21 26.5.3.1.1 extension words as required ......................................................................... 26-21 26.5.3.2 command sequence diagrams ........................................................................... 26-22 26.5.3.3 command set descri ptions ................................................................................ 26-23 26.5.3.3.1 read a/d register (rareg/rdreg) .................................................................... 26-23 26.5.3.3.2 write a/d register (wareg/wdreg) ................................................................ 26-24 26.5.3.3.3 read memory locat ion (read) ....................................................................... 26-24 26.5.3.3.4 write memory loca tion (write) ..................................................................... 26-26 26.5.3.3.5 dump memory block (dump) ........................................................................ 26-27 26.5.3.3.6 fill memory bloc k (fill) ................................................................................. 26-29 26.5.3.3.7 resume executio n (go) .................................................................................. 26-30 26.5.3.3.8 no operation (nop) ......................................................................................... 26-31 26.5.3.3.9 synchronize pc to the ps t/ddata lines (sync_pc) ................................... 26-31 26.5.3.3.10 read control regist er (rcreg) ......................................................................... 26-32 bdm accesses of the stack pointe r registers (a7: ssp, usp) 33 bdm accesses of the mac registers 33 26.5.3.3.11 write control regist er (wcreg) ...................................................................... 26-34 26.5.3.3.12 read debug module regist er (rdmreg) ......................................................... 26-35 26.5.3.3.13 write debug module regi ster (wdmreg) ....................................................... 26-36 26.6 real-time debug s upport .......................................................................................... 26-37 26.6.1 theory of oper ation ................................................................................................ 26-37 26.6.1.1 emulator mode ................................................................................................... 26-38 26.6.2 concurrent bdm and proc essor operation ............................................................ 26-39 26.7 processor status, ddata definition ......................................................................... 26-39 26.7.1 user instructi on set ................................................ ................................................ 26-4 0 26.7.2 supervisor instru ction set ....................................................................................... 26-44 26.8 freescale-recommende d bdm pinout ...................................................................... 26-44 chapter 27 ieee 1149.1 test access port (jtag) 27.1 introducti on .............................................................................................................. ..... 27-1 27.1.1 block diagra m .......................................................................................................... 2 7-1 27.1.2 features ................................................................................................................ ..... 27-2 27.1.3 modes of operat ion .................................................................................................. 27-2 27.2 external signal desc ription .......................................................................................... 27-2
mcf5213 reference manual, rev. 1.1 xxii freescale semiconductor preliminary contents paragraph number title page number 27.2.1 jtag enable (jta g_en) ........................................................................................ 27-2 27.2.2 test clock input (tclk) ......................................................................................... 27-3 27.2.3 test mode select/b reakpoint (tms/bkpt ) ............................................................. 27-3 27.2.4 test data input/development se rial input (tdi/dsi) ............................................. 27-3 27.2.5 test reset/developmen t serial clock (trst /dsclk) .......................................... 27-4 27.2.6 test data output/development se rial output (tdo/dso) ..................................... 27-4 27.3 memory map/register definition ................................................................................ 27-4 27.3.1 instruction shift regi ster (ir) .................................................................................. 27-4 27.3.2 idcode regist er ..................................................................................................... 27-4 27.3.3 bypass regi ster ......................................................................................................... 27-5 27.3.4 test_ctrl regist er .............................................................................................. 27-5 27.3.5 boundary scan regi ster ............................................................................................ 27-5 27.4 functional descri ption .................................................................................................. 27 -6 27.4.1 jtag module ........................................................................................................... 27 -6 27.4.2 tap controll er ......................................................................................................... 2 7-6 27.4.3 jtag instructi ons ..................................................................................................... 27 -7 27.4.3.1 idcode instruct ion ............................................................................................. 27-7 27.4.3.2 sample/preload inst ruction ......................................................................... 27-8 27.4.3.3 extest instruct ion ............................................................................................. 27-8 27.4.3.4 enable_test_ctrl in struction .................................................................... 27-8 27.4.3.5 highz instruct ion ................................................................................................ 27-8 27.4.3.6 clamp instruct ion .............................................................................................. 27-8 27.4.3.7 bypass instruc tion ........................................... .................................................. 27-8 27.5 initialization/applicati on informati on .......................................................................... 27-9 27.5.1 restricti ons ............................................................................................................ ... 27-9 27.5.2 nonscan chain op eration ......................................................................................... 27-9 appendix a register memory map
mcf5213 reference manual, rev. 1.1 freescale semiconductor xxiii preliminary review copy only about this book the primary objective of this reference manual is to define the functionality of the mcf5213 processor for use by software and hardware developers. in addition, this manual s upports the mcf5211 and mcf5212. this book is written from the perspective of the mcf5213, and unle ss otherwise noted, the information also applies to the mcf5211 and mcf5212. the mcf5211 and mcf5212 have the same functionality as the mcf 5213, and any differences in data regarding bus timing, signal behavior, and ac, dc, and thermal characteristics are in the data sheet. the information in this book is subjec t to change without notic e, as described in the disclaimers on the title page. as with any technical documentation, it is the reader?s responsibil ity to be sure he is using the most recent version of the documentation. to locate any published errata or updates for th is document, refer to the world-wide web at http://www.freesca le.com/coldfire . audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with the mcf5213. it is assumed that the re ader understands operating systems, microprocessor system design, basic principles of software and hard ware, and basic details of the coldfire ? architecture. organization following is a summary and br ief description of the major sections of this manual: ? chapter 1, ?overview,? includes general descriptions of th e modules and features on the device, focusing in particul ar on new features. ? chapter 2, ?signal descriptions,? describes the device signals. it includes a listing of signals that characterizes each signal as an in put or output, defines its state at reset, and identifies whether a pull-up resistor should be used. ? chapter 3, ?coldfire core,? provides an overview of the micr oprocessor core. it describes the organization of the vers ion 2 (v2) coldfire processor core and includes an overview of the programming model as they ar e implemented on the device. ? chapter 4, ?hardware multiply/accumulate (mac) unit,? describes the multiply/accumulate (mac) unit, which executes inte ger multiply, multiply-accumulat e, and miscellaneous register instructions. the mac is integrated in to the operand execution pipeline (oep). ? chapter 5, ?static ram (sram),? covers general operations, conf iguration, and in itialization of the on-chip static ram (sram) implementation. it also provides information and examples of how to minimize power consum ption when using the sram. ? chapter 6, ?clock module,? describes the device?s different clocking methods. it also describes clock module operation in low power modes.
about this book mcf5213 reference manual, rev. 1.1 xxiv freescale semiconductor preliminary review copy only ? chapter 7, ?power management,? describes the low power operati on of the device and peripheral behavior in low power modes. ? chapter 8, ?chip configuration module (ccm),? details the various opera ting configurations of the device. it provides a description of signa ls used by the ccm and a programming model. ? chapter 9, ?reset controller module,? describes the operation of the reset controller module, detailing the different type s of reset that can occur. ? chapter 10, ?system control module (scm),? describes the functionality of the scm, which provides the programming model for peripheral acce ss control, the software core watchdog timer (cwt), and the generic access error information. ? chapter 11, ?general purpose i/o module ,? describes the operation a nd programming model of the general purpose i/o (gpi o) ports on the device. ? chapter 12, ?interrupt controller module,? describes operation of the interrupt controller portion of the scm. it includes descripti ons of the registers in the interr upt controller memory map and the interrupt priority scheme. ? chapter 13, ?edge port module (eport),? describes eport module functionality, including operation in low power mode. ? chapter 14, ?dma controller module,? describes the direct memory access (dma) controller module. it provides an overview of the module and describes in detail its signals and registers. the latter sections of this chapter describe operati ons, features, and supported data transfer modes in detail. ? chapter 15, ?coldfire flash module (cfm) ,? describes implementation of the superflash? technology licensed from sst used on this de vice. the coldfire flash module (cfm) is constructed with four banks of 32k x 16-bit flash to generate a 256- kbyte, 32-bit wide electrically erasable and programmable read- only memory array. the cfm is ideal for program and data storage for single-chip appli cations and allows for field reprogramming without external high-voltage sources. ? chapter 16, ?ezport ,? describes the interface that allows the flash memory contents on a 32 bit general purpose microcontroller to be read, erased and programme d from off-chip in a format compatible to many standalone flash memory chips. ? chapter 17, ?programmable interr upt timer modules (pit0?pit1),? describes the functionality of the pit timers, including operation in low power mode. ? chapter 18, ?general purpose timer module (gpt) ,? describes the functionality of the 4-channel general purpose timer module (gpt), including th e configuration of cha nnel 3 as a 16-bit pulse accumulator that can operate as a simple ev ent counter or as a gated time accumulator. ? chapter 19, ?dma timers (dtim0?dtim3) ,? describes the configur ation and operation of the four direct memory access (d ma) timer modules (dtim0, dt im1, dtim2, and dtim3). these 32-bit timers provide input capture and referenc e compare capabilities with optional signaling of events using interrupts or dma triggers. a dditionally, programming examples are included. ? chapter 20, ?queued serial peripheral interface (qspi),? provides a featur e-set overview and a description of operation, including de tails of the qspi?s internal storage organization. the chapter concludes with the programmi ng model and a timing diagram. ? chapter 21, ?uart modules,? describes the use of the universal asynchronous receiver/transmitters (uarts) implemented on the device and includes programming examples. ? chapter 22, ?i 2 c interface,? describes the i 2 c module, including i 2 c protocol, clock synchronization, and i 2 c programming model registers.
about this book mcf5213 reference manual, rev. 1.1 freescale semiconductor xxv preliminary review copy only ? chapter 23, ?analog-to-dig ital converter (adc) ,? describes the two separate and complete adcs, each with their own sample and hold circuits and a common voltage reference and common digital control module. ? chapter 24, ?pulse width modulation (pwm) module ,? describes the configuration and operation of the pulse width modulation (p wm) module. it includes a bloc k diagram, programming model, and functional description. ? chapter 25, ?flexcan ,? describes the implementation of the controller area network (can) protocol. it describes flexcan module operation and provides a programming model. ? chapter 26, ?debug module,? describes the hardware debug support in the device. ? chapter 27, ?ieee 1149.1 test access port (jtag),? describes configurati on and operation of the joint test action group (jtag) implementation. it describes those items required by the ieee 1149.1 standard and provides additional information sp ecific to the device. fo r internal details and sample applications, see the ieee 1149.1 document. ? appendix a, ?register memory map ,? summarizes the address, name, and byte assignment for registers within the cpu space, lists an overview of the memory map for the on-chip modules, and provides a detailed memory map including all of the registers for on-chip modules. additional literature is published as new processors become available. for a current list of coldfire documentation, refer to http://www.freescale.com/coldfire . conventions this document uses the foll owing notational conventions: cleared/set when a bit takes the valu e zero, it is said to be clea red; when it ta kes a value of one, it is said to be set. mnemonics in text, instruction mn emonics are shown in uppercase. mnemonics in code and tables, instruction mnemonics are shown in lowercase. italics italics indicate variable command parameters. book titles in text are set in italics. 0x0 prefix to denote hexadecimal number 0b0 prefix to denote binary number reg[field] abbreviations for regist ers are shown in uppercase. sp ecific bits, fields, or ranges appear in brackets. for example, rambar [ba] identifies the base address field in the ram base address register. nibble a 4-bit data unit byte an 8-bit data unit word a 16-bit data unit 1 longword a 32-bit data unit x in some contexts, such as signal encodings, x indicates a don?t care. n used to express an undefined numerical value ~ not logical operator 1. the only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. to simplify the discussion these un its are referred to as words regardless of length.
about this book mcf5213 reference manual, rev. 1.1 xxvi freescale semiconductor preliminary review copy only & and logical operator | or logical operator overbar an overbar indicates that a signal is active-low. register figure conventions this document uses the following convent ions for the register reset values: ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by th e polarity of the indicated signal. the following register fields are used: acronyms and abbreviations table i lists acronyms and abbreviati ons used in this document. r0 indicates a reserved bit field in a me mory-mapped register. these bits are always read as zeros. w r1 indicates a reserved bit field in a me mory-mapped register. these bits are always read as ones. w r fieldname indicates a read/write bit. w r fieldname indicates a read-only bit field in a memory-mapped register. w r indicates a write-only bit field in a memory-mapped register. w fieldname r fieldname write 1 to clear: indicates that writ ing a 1 to this bit field clears it. ww1c r0 indicates a self-clearing bit. w fieldname table i. acronyms and abbreviated terms term meaning adc analog-to-digital conversion alu arithmetic logic unit bdm background debug mode
about this book mcf5213 reference manual, rev. 1.1 freescale semiconductor xxvii preliminary review copy only bist built-in self test bsdl boundary-scan description language codec code/decode dac digital-to-analog conversion dma direct memory access dsp digital signal processing ea effective address fifo first-in, first-out gpio general-purpose i/o i 2 c inter-integrated circuit ieee institute for electrical and electronics engineers ifp instruction fetch pipeline ipl interrupt priority level jedec joint electron device engineering council jtag joint test action group lifo last-in, first-out lru least recently used lsb least-significant byte lsb least-significant bit mac multiply accumulate unit, also media access controller mbar memory base address register msb most-significant byte msb most-significant bit mux multiplex nop no operation oep operand execution pipeline pc program counter pclk processor clock plic physical layer interface controller pll phase-locked loop por power-on reset pqfp plastic quad flat pack pwm pulse width modulation table i. acronyms and abbreviated terms (continued) term meaning
about this book mcf5213 reference manual, rev. 1.1 xxviii freescale semiconductor preliminary review copy only terminology conventions table ii shows terminology conventions used throughout this document. qspi queued serial peripheral interface risc reduced instruction set computing rx receive sim system integration module sof start of frame tap test access port ttl transistor transistor logic tx transmit uart universal asynchronous/synch ronous receiver transmitter table ii. notational conventions instruction operand syntax opcode wildcard cc logical condition (example: ne for not equal) register specifications an any address register n (example: a3 is address register 3) ay,ax source and destination address registers, respectively dn any data register n (example: d5 is data register 5) dy,dx source and destination data registers, respectively rc any control register (example vbr is the vector base register) rm mac registers (acc, mac, mask) rn any address or data register rw destination register w (us ed for mac instructions only) ry,rx any source and destination registers, respectively xi index register i (can be an address or data register: ai, di) miscellaneous operands # immediate data following the 16-bit operation word of the instruction effective address y,x source and destination effective addresses, respectively table i. acronyms and abbreviated terms (continued) term meaning
about this book mcf5213 reference manual, rev. 1.1 freescale semiconductor xxix preliminary review copy only assembly language program label list of registers for mo vem instruction (example: d3?d0) shift operation: shift left (<<), shift right (>>) operand data size: byte (b), word (w), longword (l) bc both instruction and data caches dc data cache ic instruction cache # identifies the 4-bit vect or number for trap instructions <> identifies an indirect data address referencing memory identifies an absolute address referencing memory d n signal displacement value, n bits wide (example: d16 is a 16-bit displacement) sf scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for mac operations) operations + arithmetic addition or postincrement indicator ? arithmetic subtraction or predecrement indicator x arithmetic multiplication / arithmetic division ~ invert; operand is logically complemented &logical and | logical or ^ logical exclusive or << shift left (example: d0 << 3 is shift d0 left 3 bits) >> shift right (example: d0 >> 3 is shift d0 right 3 bits) source operand is moved to destination operand two operands are exchanged sign-extended all bits of the upper portion are made equal to the high-order bit of the lower portion if then else test the condition. if true, the operations after ?t hen? are performed. if the condition is false and the optional ?else? clause is present, the operations af ter ?else? are performed. if the condition is false and else is omitted, the instruction performs no operation. refer to the bcc instruction description as an example. subfields and qualifiers {} optional operation () identifies an indirect address table ii. notational conventions (continued) instruction operand syntax
about this book mcf5213 reference manual, rev. 1.1 xxx freescale semiconductor preliminary review copy only revision history table iii provides a revision history for this document. d n displacement value, n-bits wide (example: d 16 is a 16-bit displacement) address calculated effective address (pointer) bit bit selection (example: bit 3 of d0) lsb least significant bit (example: lsb of d0) lsb least significant byte lsw least significant word msb most significant bit msb most significant byte msw most significant word table iii. mcf5213 reference manual revision history revision number date of release substantive changes 1 05/2005 initial public release. 1.1 07/2005 interim release with corrections. table ii. notational conventions (continued) instruction operand syntax
mcf5213 reference manual, rev. 1.1 freescale semiconductor 1-1 preliminary chapter 1 overview this chapter provides an overview of the majo r features and functional components of the mcf5213 family of microcontroller s. the mcf5213 family is a high ly integrated implementation of the coldfire ? family of reduced instruction set compu ting (risc) microcontrollers that also includes the mcf5211 and mcf5212 . the differences between th ese parts are summarized in table 1-1 . this document is written from the perspective of the mcf5213. the mcf5213 represents a family of highly-inte grated 32-bit microcontrollers based on the v2 coldfire microarchitecture. featur ing up to 32 kbytes of internal sram and 256 kbytes of flash memory, four 32-bit timers with dma request capability, a 4-channel dma controller, a can module, an i 2 c? module, 3 uarts and a queued spi , the mcf5213 family has been designed for general purpose industrial control applications. this 32-bit device is based on the version 2 coldfire reduced instru ction set computer (risc) core with a multiply-accumulate unit (mac) and di vider providing 76 drystone 2.1 mips at a frequency up to 80 mhz from internal fl ash. on-chip modules include the following: ? v2 coldfire core with multiply-accumulate unit (mac) ? 32 kbytes of internal sram ? 256 kbytes of on-chip flash memory ? three universal asynchronous receiver/transmitters (uarts) ? controller area network 2.0b (flexcan) module ? inter-integrated circuit (i 2 c) bus controller ? 12-bit analog-to-digital converter (adc) ? queued serial peripheral interface (qspi) module ? four-channel, 32-bit direct memory access (dma) controller ? four-channel, 32-bit input capture/output compare timers with optional dma support ? two 16-bit periodic interrupt timers (pits) ? programmable software watchdog timer ? interrupt controller capable of handling up to 63 interrupt sources ? clock module with 8 mhz on-chip relaxation oxcillator and integrated phase locked loop (pll)
overview mcf5213 reference manual, rev. 1.1 1-2 freescale semiconductor preliminary these devices are ideal for cost-sensitive applica tions requiring significant control processing for connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets such as security, imaging, networking, gaming, and medical. this leading package of integration and high performance allows fast time to market through easy co de reuse and extensive third party tool support. to locate any published errata or updates for this document, refe r to the coldfire products website at http://www.freescale.com/coldfire . 1.1 mcf5213 family configurations table 1-1. mcf5213 family configurations module 5211 5212 5213 coldfire version 2 core with mac (multiply-accumulate unit) xxx system clock 66 mhz 66, 80 mhz performance (dhrystone 2.1 mips) 63 up to 76 flash / static ram (sram) 128/16 kbytes 256/32 kbytes interrupt controller (intc) x x x fast analog-to-digital converter (adc) x x x flexcan 2.0b module - - x four-channel direct-memory access (dma) x x x watchdog timer module (wdt) x x x programmable interval timer module (pit) 2 2 2 four-channel general purpose timer 3 3 3 32-bit dma timers 4 4 4 qspi x x x uart(s) 3 3 3 i 2 cxxx pwm 8 8 8 general purpose i/o module (gpio) x x x chip configuration and reset controller module xxx background debug mode (bdm) x x x jtag - ieee 1149.1 test access port 1 xxx package 64-pin lqfp 81-ball mapbga 64-pin lqfp 81-ball mapbga 100-lead lqfp
overview mcf5213 reference manual, rev. 1.1 freescale semiconductor 1-3 preliminary 1.2 block diagram the superset device in the mcf5213 family come s in a 100-lead leaded quad flat package (lqfp). figure 1-1 shows a top-level block diagram of the mcf5213. figure 1-1. mcf5213 block diagram 1 the full debug/trace interface is available only on the 100-pin packages. a reduced debug interface is bonded on smaller packages. arbiter interrupt controller uart 0 qspi uart 1 uart 2 i 2 c dtim 0 dtim 1 dtim 2 dtim 3 v2 coldfire cpu ifp oep mac 4 ch dma mux jtag tap to/from padi 32 kbytes sram (4kx16)x4 256 kbytes flash (32kx16)x4 ports (gpio) cim rsti rsto u n txd u n rxd u n rts dtin n /dtout n canrx jtag_en adc an[7:0] v rh v rl pll oco clkgen edge port flexcan extal xtal clkout pit0 pit1 gpt pwm to/from interrupt controller cantx u n cts pmm v stby padi ? pin muxing ezport ezpcs clkmod0 clkmod1 qspi_sck, qspi_pcs n pwm n qspi_din, qspi_dout gpt ezpck ezpd ezpq swt
overview mcf5213 reference manual, rev. 1.1 1-4 freescale semiconductor preliminary 1.3 part numbers and packaging table 1-2 summarizes the features of the mcf52 13 product family. several speed/package options are available to match cost- or performance-sensitive applications. 1.4 mcf5213 family features the mcf5213 family includes the following features: ? version 2 coldfire variable -length risc processor core ? static operation ? 32-bit address and data paths on-chip ? up to 80 mhz processor core frequency ? sixteen general-purpose, 32-bit data and address registers ? implements coldfire isa_a+ with extensions to support the user stack pointer register and four new instructions for improved bit processing ? multiply-accumulate (mac) unit with 32-bit accumulator to support 16 16 32 or 32 32 32 operations ? illegal instruction decode that allows for 68k emulation support ? system debug support ? revision b+ debug module on-chip ? real time trace for determin ing dynamic execution path ? background debug mode (bdm) for in-circuit debugging ? real time debug support, with six hardware breakpoints (4 pc, 1 address, and 1data) that can be configured into a 1- or 2-level trigger ? on-chip memories ? 32 kbyte dual-ported sram on cpu internal bus, supporting core and dma access with standby po wer supply support ? 256 kbytes of interleaved flash memory supporting 2-1-1-1 accesses table 1-2. part number summary part number flash / sram key features package speed mcf5211 128 kbytes / 16 kbytes 3 uarts, i 2 c, qspi, a/d 16-/32-bit/pwm timers 64-pin lqfp 81-ball mapbga 66 mhz mcf5212 256 kbytes / 32 kbytes 3 uarts, i 2 c, qspi, a/d 16-/32-bit/pwm timers 64-pin lqfp 81-ball mapbga 66 mhz 66, 80 mhz mcf5213 256 kbytes / 32 kbytes 3 uarts, i 2 c, qspi, a/d 16-/32-bit/pwm timers, can 81-ball mapbga 100-lead lqfp 80 mhz 80 mhz
overview mcf5213 reference manual, rev. 1.1 freescale semiconductor 1-5 preliminary ? power management ? fully static operation with proces sor sleep and whole chip stop modes ? very rapid response to interrupts from th e low-power sleep mode (wake-up feature) ? clock enable/disable for each peripheral when not used ? flexcan 2.0b module ? based on and includes all existing features of the freescale toucan module ? full implementation of the can protocol specification version 2.0b ? standard data and remote frames (up to 109 bits long) ? extended data and remote frames (up to 127 bits long) ? 0-8 bytes data length ? programmable bit rate up to 1 mbit/sec ? flexible message buffers (mbs), totalling up to 16 message buffers of 0?8 byte data length each, configurable as rx or tx, all supporting st andard and extended messages ? unused mb space can be used as general purpose ram space ? listen only mode capability ? content-related addressing ? no read/write semaphores ? three programmable mask registers: gl obal for mbs 0-13, special for mb14, and special for mb15 ? programmable transmit-first scheme: lo west id or lowest buffer number ? time stamp based on 16-bit free-running timer ? global network time, synchronized by a specific message ? maskable interrupts ? three universal asynchronous/synchr onous receiver transmitters (uarts) ? 16-bit divider for clock generation ? interrupt control logic ? maskable interrupts ? dma support ? data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity ? up to 2 stop bits in 1/16 increments ? error-detection capabilities ? modem support includes request-to-send (urts ) and clear-to-send (ucts ) lines for two uarts ? transmit and receive fifo buffers
overview mcf5213 reference manual, rev. 1.1 1-6 freescale semiconductor preliminary ?i 2 c module ? interchip bus interface for eeproms, lcd controllers, a/d converters, and keypads ? fully compatible with industry-standard i 2 c bus ? master or slave modes support multiple masters ? automatic interrupt generation with programmable level ? queued serial peripheral interface (qspi) ? full-duplex, three-wire synchronous transfers ? up to four chip selects available ? master mode operation only ? programmable bit rates up to half the cpu clock frequency ? up to 16 pre-programmed transfers ? fast analog-to-digital converter (adc) ? eight analog input channels ? 12-bit resolution 2.5 counts accuracy ? minimum 2.25 s conversion time ? simultaneous sampling of two channe ls for motor control applications ? single-scan or continuous operation ? optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit ? unused analog channels can be used as digital i/o ? four 32-bit dma timers ? 12.5-ns resolution at 80 mhz ? programmable sources for clock input, including an external clock option ? programmable prescaler ? input capture capability with program mable trigger edge on input pin ? output compare with programmable mode for the output pin ? free run and restart modes ? maskable interrupts on input capture or output compare ? dma trigger capability on input capture or output compare ? four-channel general purpose timer ? 16-bit architecture ? programmable prescaler ? output pulse widths variable from microseconds to seconds ? single 16-bit input pulse accumulator
overview mcf5213 reference manual, rev. 1.1 freescale semiconductor 1-7 preliminary ? toggle-on-overflow feature for puls e-width modulator (pwm) generation ? one dual-mode pulse accumulation channel per timer ? pulse-width modulation timer ? operates as eight channels with 8-bit resolu tion or four channels with 16-bit resolution ? programmable period and duty cycle ? programmable enable/disable for each channel ? software selectable polarity for each channel ? period and duty cycle are double buffered. ch ange takes effect when the end of the current period is reached (pwm counter reache s zero) or when the channel is disabled. ? programmable center or left ali gned outputs on individual channels ? four clock sources (a, b, sa, and sb) provide for a wide range of frequencies ? emergency shutdown ? two periodic interrupt timers (pits) ? 16-bit counter ? selectable as free running or count down ? core software watchdog timer ? 16-bit counter ? low power mode support ? clock generation features ? 1 to 16 mhz crystal, 8 mhz on-chip relaxation oscillator, or external oscillator reference options ? relaxation oscillator nvm-trimmed to 2% accuracy ? 2 to 10 mhz reference frequency for normal pll mode ? system can be clocked from pll or dir ectly from crystal oscillator or relaxation oscillator ? low power modes supported ?2 n (n 0 15) low-power divider for extremely low frequency operation ? interrupt controller ? support for up to 57 interrupt sources organized as follows: ? 50 fully-programmable interrupt sources ? 7 fixed-level interrupt sources ? seven external interrupt signals ? unique vector number for each interrupt source ? ability to mask any individual interrupt sour ce or all interrupt sources (global mask-all)
overview mcf5213 reference manual, rev. 1.1 1-8 freescale semiconductor preliminary ? support for hardware and software interrupt acknowledge (iack) cycles ? combinatorial path to provide wake-up from low power modes ? dma controller ? four fully programmable channels ? dual-address transfer support with 8-, 16-, and 32-bit data capabil ity, along with support for 16-byte (4 x 32-bit) burst transfers ? source/destination address pointers th at can increment or remain constant ? 24-bit byte transfer counter per channel ? auto-alignment transfers suppor ted for efficient block movement ? bursting and cycle steal support ? software-programmable dma requesters in the uarts (6), 32-bit timers (4), and dma channels (4) ?reset ? separate reset in and reset out signals ? seven sources of reset: ? power-on reset (por) ? external ? software ? watchdog ? loss of clock ? loss of lock ? low-voltage detection (lvd) ? status flag indication of source of last reset ? chip integration module (cim) ? system configuration during reset ? selects one of six clock modes ? configures output pad drive strength ? unique part identification nu mber and part revision number ? general purpose i/o interface ? up to 56 bits of general purpose i/o ? bit manipulation supported via set/clear functions ? unused peripheral pins may be used as extra gpio ? jtag support for system level board testing
overview mcf5213 reference manual, rev. 1.1 freescale semiconductor 1-9 preliminary 1.4.1 v2 core overview the version 2 coldfire processor core is comprised of two separa te pipelines that are decoupled by an instruction buffer. the two-stage instru ction fetch pipeline (ifp) is responsible for instruction-address generation and instruction fe tch. the instruction buffe r is a first-in-first-out (fifo) buffer that holds prefet ched instructions awaiting ex ecution in the operand execution pipeline (oep). the oep includes two pipeline stages. the first stage decodes instructions and selects operands (dsoc); the s econd stage (agex) performs instruction execution and calculates operand effective addresses, if needed. the v2 core implements the coldfire instructio n set architecture revision a+ with added support for a separate user stack pointer register and f our new instructions to assist in bit processing. additionally, the mcf5213 core includes the multiply-accumulate unit (mac) for improved signal processing capabilities. the mac implements a three-st age execution pipeline, optimized for 16 x 16 bit operations, with support for one 32-bit accumula tor. supported operands include 16- and 32-bit signed and unsigned integers, as we ll as signed fractional operands and a complete set of instructions to process these data types. the mac provid es support for execution of dsp operations within the context of a single processor at a minimal hardware cost. 1.4.2 integrated debug module the coldfire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. th rough a standard debug interface, users can access debug information; on 100 -lead packages, real-time tracing capability is provided. this allows the pr ocessor and system to be debugged at full speed without the need for costly in-circuit emulators. the on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, and four pc plus one pc mask registers. these registers can be accessed thro ugh the dedicated debu g serial communication channel or from the processor?s supervisor m ode programming model. the breakpoint registers can be configured to generate triggers by comb ining the address, data, and pc conditions in a variety of single- or dual-level definitions. the trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. the mcf5213 implem ents revision b+ of the coldfire debug architecture. the mcf5213?s interrupt servic ing options during emulator m ode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging. to support program trace, the v2 debug module provides processo r status (pst[3:0]) and debug data (ddata[3:0]) ports. these buses and the pstclk output provide execution status, captured operand data, and branch target addresses defining processor activity at the cpu?s clock rate. the full debug/trace interface is av ailable only on the 100-pin pack ages. however, every product
overview mcf5213 reference manual, rev. 1.1 1-10 freescale semiconductor preliminary features the dedicated debug serial communicat ion channel (dsi, dso, dsclk) and the allpst signal. the mcf5213 includes a new debug signal, allpst . this signal is the logical ?and? of the processor status (pst[3:0]) signals and is useful for detecting when the processor is in a halted state (pst[3:0] = 1111). 1.4.3 jtag the mcf5213 supports circuit boa rd test strategies based on the test technology committee of ieee and the joint test action group (jtag). the test logic includes a test access port (tap) consisting of a 16-state controller, an instruction register, and thr ee test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32- bit id register). the boundary scan register links the device?s pins into one shift register. test logic, implemented usi ng static logic design, is independent of the device system logic. the mcf5213 implementation can do the following: ? perform boundary-scan operations to te st circuit board electrical continuity ? sample mcf5213 system pins during operation and transparently shift out the result in the boundary scan register ? bypass the mcf5213 for a given circuit board test by effectively reducing the boundary-scan register to a single bit ? disable the output drive to pins during circuit-board testing ? drive output pins to stable levels 1.4.4 on-chip memories 1.4.4.1 sram the dual-ported sram module provides a genera l-purpose 32-kbyte memory block that the coldfire core can access in a single cycle. the location of the memory block can be set to any 32-kbyte boundary within the 4-g byte address space. this memory is ideal for storing critical code or data structures and for use as the syst em stack. because the sram module is physically connected to the processor's high- speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. the sram module is also accessible by the dma. the dual-ported nature of the sram makes it ideal for implementing applicati ons with double-buffer schemes, where the processor and a dma device operate in alternate regions of the sram to maximize system performance.
overview mcf5213 reference manual, rev. 1.1 freescale semiconductor 1-11 preliminary 1.4.4.2 flash the coldfire flash module (cfm) is a non-vola tile memory (nvm) modul e that connects to the processor?s high-speed local bus. the cfm is cons tructed with four banks of 32k x 16-bit flash arrays to generate 256 kbytes of 32-bit flash memory. these arrays serve as electrically erasable and programmable, non-volatile program and da ta memory. the flash memory is ideal for program and data storage for si ngle-chip applications, allowing for field reprogramming without requiring an external high voltage source. the cfm interfaces to the coldfire core through an optimized read-only memory controller which supports interleaved accesses from the 2-cycle flash arrays. a backdoor mapping of the flash memo ry is used for all program, erase, and verify operations, as well as providing a read datapa th for the dma. flash memory may also be programmed via the ezport, which is a serial flash programming in terface that allows the flash to be read, erased and programmed by an external controller in a fo rmat compatible with most spi bus flash memory chips. 1.4.5 flexcan the flexcan module on the mcf5213 (refer to table 1-1 ) is a communication controller implementing the 2.0b can protoc ol. the can protocol is comm only used as an industrial control serial data bus, meeting the specific re quirements of real-time processing, reliable operation in a harsh emi environment, cost -effectiveness, and required bandwidth. the instantiation of flexcan on the mc f5213 contains 16 message buffers. 1.4.6 uarts the mcf5213 contains three full- duplex uarts that function independently. the three uarts can be clocked by the system bus clock, elimina ting the need for an externally supplied clock. they can use dma requests on tran smit-ready and receive-ready, as well as interrupt requests for servicing. flow control via u n cts and u n rts pins is provided on all three uarts. on smaller packages, the third uart is multiplexed with other digital i/o functions. 1.4.7 i 2 c bus the i 2 c bus is a two-wire, bidi rectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between de vices. this bus is suit able for applications requiring occasional communications over a short distance between many devices. 1.4.8 qspi the queued serial peripheral inte rface module provides a high-speed synchronous serial peripheral interface with queued transfer capability. it allo ws up to 16 transfers to be queued at once, eliminating cpu intervention between transfers.
overview mcf5213 reference manual, rev. 1.1 1-12 freescale semiconductor preliminary 1.4.9 dma timers (dtim0-dtim3) there are four independent, dma-transfer -generating 32-bit tim ers (dtim[3:0]) on the mcf5213. each timer modul e incorporates a 32-b it timer with a separate register set for configuration and control. the timers can be conf igured to operate from th e system clock or from an external clock source using one of the dtin n signals. if the system clock is selected, it can be divided by 16 or 1. the input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual tim er counter register (tcr n ). each of these timers can be configured for input capture or reference compare mode. by conf iguring the internal registers, each timer may be configured to assert an external signal, generate an interrupt on a particular event, or cause a dma transfer. 1.4.10 general purpose timer (gpta/gptb) the general purpose timer (gptb) is a 4-channe l timer module. the timer consists of a 16-bit programmable counter driven by a 7-stage programmable prescaler. e ach of the four channels can be configured for input capture or output compar e. additionally, one of the channels, channel 3, can be configured as a pulse accumulator. a timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter . the input capture and out put compare functions allow simultaneous input waveform measurements and output waveform generation. the input capture function can capture the time of a selected transition edge. the output compare function can generate output waveforms and timer software delays. the 16-b it pulse accumulator can operate as a simple event counter or a gated time accumulator. 1.4.11 pulse width modulation timers (pwm) the mcf5213 has an 8-channel, 8-bit pwm timer. each channel has a programmable period and duty cycle as well as a dedicated counter. each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. the pwm outputs have programmable polarity, and can be programmed as left a ligned outputs or center aligned outputs. for higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. the module can thus be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels. 1.4.12 periodic interrupt timers (pit0 and pit1) the two periodic interrupt timers (pit0 and pit1 ) are 16-bit timers that provide interrupts at regular intervals with minimal processor interv ention. each timer can either count down from the value written in its pit modulus register, or it can be a free-running down-counter.
overview mcf5213 reference manual, rev. 1.1 freescale semiconductor 1-13 preliminary 1.4.13 core software watchdog timer the watchdog timer is a 32-bit timer that facil itates recovery from runaway code. the watchdog counter is a free-running down-cou nter that generates a reset on underflow when enabled. to prevent a reset, software must periodically restart the countdown. 1.4.14 clock module and phase locked loop (pll) the clock module contains a crystal oscillato r (osc), phase-locked loop (pll), reduced frequency divider (rfd), status/con trol registers, and control lo gic. to improve noise immunity, the pll and osc have their own power supply inputs, vddpll a nd vsspll. all other circuits are powered by the normal supply pins, vdd and vss. 1.4.15 interrupt controller (intc) the mcf5213 includes an interrupt controller that can support up to 57 interrupt sources. the interrupt controller is organized as 7 levels with 9 interrupt sources per level. each interrupt source has a unique interrupt vector, and 50 of the 57 sources provide a programmable level [1-7] and priority within the level. 1.4.16 dma controller the direct memory access (dma) controller module provides an efficient way to move blocks of data with minimal processor interactio n. the dma module provides four channels (dma0-dma3) that allow byte, wo rd, longword or 16-byte burst lin e transfers. these transfers are triggered by software explicitly setting a dcr n [start] bit. other sources include the dma timer and uarts. the dma controller supports dual address transfers to on-chip devices. 1.4.17 reset the reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the la st reset. there are seven sources of reset: ? external reset input ? power-on reset (por) ? phase locked-loop (pll) loss of lock ? pll loss of clock ? software ? low-voltage detector (lvd)
overview mcf5213 reference manual, rev. 1.1 1-14 freescale semiconductor preliminary control of the lvd and its associ ated reset and interrupt are hand led by the reset controller. other registers provide status flags indicating the last source of reset and a control bit for software assertion of the rsto pin. 1.4.18 gpio nearly all pins on the mcf5213 have general pur pose i/o capability and are grouped into 8-bit ports. some ports do not use all eight bits. each port has registers that configure, monitor, and control the port pins.
mcf5213 reference manual, rev. 1.1 freescale semiconductor 2-1 preliminary chapter 2 signal descriptions this chapter describes signals implemented on this de vice and includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used. note the terms ?assertion? and ?negation? are used to avoid confusion when dealing with a mixture of active-low and active- high signals. the term ?asserted? indicates that a signal is active, independent of the voltage level. the term ?negated? indicates that a signal is inactive. active-low signals, such as sras and ta , are indicated with an overbar. 2.1 overview figure 2-1 shows the block diagram of the device with the signal interface.
signal descriptions mcf5213 reference manual, rev. 1.1 2-2 freescale semiconductor preliminary figure 2-1. block diagram with signal interfaces tdo/dso tdi/dsi tms/ bkpt tclk/pstclk uart1 serial i/o extal dtin[3:0] dtout[3:0] jtag port coldfire v2 core mac utxd0 urxd0 urts0 ucts0 utxd1 urxd1 urts1 ucts1 trst /dsclk test 4 4 te s t controller 4 pst[3:0] 4 i 2 c module scl sda uart2 serial i/o dma timer modules clock module (pll) ddata[3:0] debug module div mode selection reset controller power rcon clkmod0 clkmod1 rsti rsto edgeport interrupt controller 0 interrupt controller 1 irq [7:1] uart0 serial i/o dma controller general purpose timer qspi flexcan adc pit timers (pit0? jtag_en clkout xtal utxd2 urxd2 (dtim0? dtim3) vrh vrl an[7:0] sync[a:b] gpt[3:0] 4 qspi_din qspi_dout qspi_clk qspi_cs[3:0] cantx canrx management por ts module pit1) internal bus arbiter system control module (scm) vddf vstby flash module 32k sram ezport ezpck ezpcs ezpd ezq 2 8 edgeport urts2 ucts2 pwm pwm[7:0] allpst
signal descriptions mcf5213 reference manual, rev. 1.1 freescale semiconductor 2-3 preliminary table 2-1 shows the pin functions by primary and alternate purpose, and illustrates which pack ages contain each pin. table 2-1. pin functions by primary and alternate purpose and package pin group primary function secondary function tertiary function quaternary function drive strength / control slew rate / control pull-up / pull-down pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp notes adc an7 ? ? gpio 2ma fast ? 51 h9 33 an6 ? ? gpio 2ma fast ? 52 g9 34 an5 ? ? gpio 2ma fast ? 53 g8 35 an4 ? ? gpio 2ma fast ? 54 f9 39 an3 ? ? gpio 2ma fast ? 46 g7 28 an2 ? ? gpio 2ma fast ? 45 g6 27 an1 ? ? gpio 2ma fast ? 44 h6 26 an0 ? ? gpio 2ma fast ? 43 j6 25 synca ? ? ? n/a n/a ? ? ? ? no primary syncb ? ? ? n/a n/a ? ? ? ? no primary vdda ? ? ? n/a n/a ? 50 h8 32 vssa ? ? ? n/a n/a ? 47 h7 39 vrh ? ? ? n/a n/a ? 49 j8 31 vrl ? ? ? n/a n/a ? 48 j7 30 clock generation extal ? ? ? n/a n/a ? 73 b9 47 xtal ? ? ? n/a n/a ? 72 c9 46 vddpll ? ? ? n/a n/a ? 74 b8 48 vsspll ? ? ? n/a n/a ? 71 c8 45 debug data allpst ? ? ? 10ma fast ? 86 a6 55 ddata[3:0] ? ? gpio 10ma fast ? 84,83,78,77 ? ? pst[3:0] ? ? gpio 10ma fast ? 70,69,66,65 ? ?
mcf5213 reference manual, rev. 1.1 2-4 freescale semiconductor preliminary signal descriptions i 2 c scl cantx 1 utxd2 gpio pdsr[0] psrr[0] ? 10 e1 8 sda canrx 1 urxd2 gpio pdsr[0] psrr[0] ? 11 e2 9 interrupts irq7 ? ? gpio 2 ma fast ? 95 c4 58 irq6 ? ? gpio 2 ma fast ? 94 b4 ? irq5 ? ? gpio 2 ma fast ? 91 a4 ? irq4 ? ? gpio 2 ma fast ? 90 c5 57 irq3 ? ? gpio 2 ma fast ? 89 a5 ? irq2 ? ? gpio 2 ma fast ? 88 b5 ? irq1 synca pwm1 gpio 10 ma fast ? 87 c6 56 jtag/bdm jtag_en ? ? ? n/a n/a pull-down 26 j2 17 tclk/ pstclk clkout ? ? 10 ma fast ? 64 c7 44 tdi/dsi ? ? ? n/a n/a ? 79 b7 50 tdo/dso ? ? ? 10 ma fast ? 80 b7 50 tms /bkpt ? ? ? n/a n/a ? 76 a8 49 trst /dsclk ? ? ? n/a n/a ? 85 b6 54 mode selection 2 clkmod0 ? ? ? n/a n/a pull-down 2 40 g5 24 clkmod1 ? ? ? n/a n/a pull-down 2 39 h5 ? rcon/ ezpcs ? ? ? n/a n/a pull-up 21 g3 16 pwm pwm7 ? ? gpio pdsr[31] psrr[31] ? 63 d7 ? pwm5 ? ? gpio pdsr[30] psrr[30] ? 60 e8 ? pwm3 ? ? gpio pdsr[29] psrr[29] ? 33 j4 ? pwm1 ? ? gpio pdsr[28] psrr[28] ? 38 j5 ? table 2-1. pin functions by primary and alternate purpose and package pin group primary function secondary function tertiary function quaternary function drive strength / control slew rate / control pull-up / pull-down pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp notes
signal descriptions mcf5213 reference manual, rev. 1.1 freescale semiconductor 2-5 preliminary qspi qspi_din/ ezpd canrx 1 rxd1 gpio pdsr[2] psrr[2] ? 16 f3 12 qspi_dout /ezpq cantx 1 txd1 gpio pdsr[1] psrr[1] ? 17 g1 13 qspi_sck/ ezpck scl rts1 gpio pdsr[3] psrr[3] ? 18 g2 14 qspi_cs3 synca syncb gpio pdsr[7] psrr[7] ? 12 f1 ? qspi_cs2 ? ? gpio pdsr[6] psrr[6] ? 13 f2 ? qspi_cs1 ? ? gpio pdsr[5] psrr[5] ? 19 h2 ? qspi_cs0 sda cts1 gpio pdsr[4] psrr[4] ? 20 h1 15 reset 3 rsti ? ? ? n/a n/a pull-up 3 96 a3 59 rsto ? ? ? 10 ma fast ? 97 b3 60 test test ? ? ? n/a n/a pull-down 5 c2 3 timers, 16-bit gpt3 ? pwm7 gpio pdsr[23] psrr[23] pull-up 4 62 d8 43 gpt2 ? pwm5 gpio pdsr[22] psrr[22] pull-up 4 61 d9 42 gpt1 ? pwm3 gpio pdsr[21] psrr[21] pull-up 4 59 e9 41 gpt0 ? pwm1 gpio pdsr[20] psrr[20] pull-up 4 58 f7 40 timers, 32-bit dtin3 dtout3 pwm6 gpio pdsr[19] psrr[19] ? 32 h3 19 dtin2 dtout2 pwm4 gpio pdsr[18] psrr[18] ? 31 j3 18 dtin1 dtout1 pwm2 gpio pdsr[17] psrr[17] ? 37 g4 23 dtin0 dtout0 pwm0 gpio pdsr[16] psrr[16] ? 36 h4 22 uart 0 ucts0 canrx ? gpio pdsr[11] psrr[11] ? 6 c1 4 urts0 cantx ? gpio pdsr[10] psrr[10] ? 9 d3 7 urxd0 ? ? gpio pdsr[9] psrr[9] ? 7 d1 5 utxd0 ? ? gpio pdsr[8] psrr[8] ? 8 d2 6 table 2-1. pin functions by primary and alternate purpose and package pin group primary function secondary function tertiary function quaternary function drive strength / control slew rate / control pull-up / pull-down pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp notes
mcf5213 reference manual, rev. 1.1 2-6 freescale semiconductor preliminary signal descriptions 2.2 reset signals table 2-2 describes signals that are used to either reset the chip or as a reset indication. uart 1 ucts1 synca urxd2 gpio pdsr[15] psrr[15] ? 98 c3 61 urts1 syncb utxd2 gpio pdsr[14] psrr[14] ? 4 b1 2 urxd1 ? ? gpio pdsr[13] psrr[13] ? 100 b2 63 utxd1 ? ? gpio pdsr[12] psrr[12] ? 99 a2 62 uart 2 ucts2 ? ? gpio pdsr[27] psrr[27] ? 27 ? ? urts2 ? ? gpio pdsr[26] psrr[26] ? 30 ? ? urxd2 ? ? gpio pdsr[25] psrr[25] ? 28 ? ? utxd2 ? ? gpio pdsr[24] psrr[24] ? 29 ? ? flexcan canrx n/a n/a ? ? ? ? see note 1,5 cantx n/a n/a ? ? ? ? see note 1,5 vstby vstby ? ? ? n/a n/a ? 55 f8 37 vdd vdd ? ? ? n/a n/a ? 8 6 5 vss vss ? ? ? n/a n/a ? 8 6 5 1 the multiplexed cantx and canrx signals are not available on the mcf5211 or mcf5212 2 clkmod0 and clkmod1 have internal pull-down resistors, howeve r the use of external resistors is very strongly recommended 3 rsti has an internal pull-up resistor, however the use of an external resistor is very strongly recommended 4 for gpio function. primary function has pull-up control within the gpt module 5 cantx and canrx are secondary functions only. table 2-1. pin functions by primary and alternate purpose and package pin group primary function secondary function tertiary function quaternary function drive strength / control slew rate / control pull-up / pull-down pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp notes
signal descriptions mcf5213 reference manual, rev. 1.1 freescale semiconductor 2-7 preliminary table 2-2. reset signals signal name abbreviation function i/o reset in rsti primary reset input to th e device. asserting rsti immediately resets the cpu and peripherals. i reset out rsto driven low for 512 cpu clocks afte r the reset source has deasserted and pll locked. o
signal descriptions mcf5213 reference manual, rev. 1.1 2-8 freescale semiconductor preliminary 2.3 pll and clock signals table 2-3 describes signals that are used to s upport the on-chip clock generation circuitry. 2.4 mode selection table 2-4 describes signals used in mode selection, table 2-5 describes particular clocking modes. table 2-3. pll and clock signals signal name abbreviation function i/o external clock in extal crystal oscillator or external clock input except when the on-chip relaxation oscillator is used. i crystal xtal crystal oscillator output except when clkmod1=1, then sampled as part of the clockmode selection mechanism. o clock out clkout this output signal reflects the internal system clock. o table 2-4. mode selection signals signal name abbreviation function i/o clock mode selection clkmod[1:0] selects the clock boot mode. i reset configuration rcon the serial flash programming mode is entered by asserting the rcon pin (with the test pin negated) as the chip comes out of reset. during this mode, the ezport has access to the flash memory which can be programmed from an external device. test test reserved for factory testing only and in normal modes of operation should be connected to vss to prevent unintentional activation of test functions. i table 2-5. clocking modes clkmod[1:0] xtal configure the clock mode 00 0 pll disabled, clock driven by external oscillator 00 1 pll disabled, clock driven by on-chip oscillator 01 n/a pll disabled, clock driven by crystal 10 0 pll in normal mode, clock driven by external oscillator 10 1 pll in normal mode, clock driven by on-chip oscillator 11 n/a pll in normal mode, clock driven by crystal
signal descriptions mcf5213 reference manual, rev. 1.1 freescale semiconductor 2-9 preliminary 2.5 external interrupt signals table 2-6 describes the external interrupt signals. 2.6 queued serial peripheral interface (qspi) table 2-7 describes qspi signals. 2.7 i 2 c i/o signals table 2-8 describes the i 2 c serial interface module signals. table 2-6. external interrupt signals signal name abbreviation function i/o external interrupts irq [7:1] external interrupt sources. i table 2-7. queued serial peripheral interface (qspi) signals signal name abbreviation function i/o qspi synchronous serial output qspi_dout provides the serial data from t he qspi and can be programmed to be driven on the rising or falling edge of qspi_clk. o qspi synchronous serial data input qspi_din provides the serial data to the qspi and can be programmed to be sampled on the rising or falling edge of qspi_clk. i qspi serial clock qspi_clk provides the serial cl ock from the qspi. the polarity and phase of qspi_clk are programmable. o synchronous peripheral chip selects qspi_cs[3:0] qspi peripheral chip selects that can be programmed to be active high or low. o table 2-8. i 2 c i/o signals signal name abbreviation function i/o serial clock scl open-drain clock signal for the for the i 2 c interface. either it is driven by the i 2 c module when the bus is in master mode or it becomes the clock input when the i 2 c is in slave mode. i/o serial data sda open-drain signal that serves as the data input/output for the i 2 c interface. i/o
signal descriptions mcf5213 reference manual, rev. 1.1 2-10 freescale semiconductor preliminary 2.8 uart module signals table 2-9 describes the uart module signals. 2.9 dma timer signals table 2-10 describes the signals of the four dma timer modules. 2.10 adc signals table 2-11 describes the signals of the analog-to-digital converter. table 2-9. uart module signals signal name abbreviation function i/o transmit serial data output utxd n transmitter serial data outputs for the uart modules. the output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. data is shifted out, lsb first, on this pin at the falling edge of the serial clock source. o receive serial data input urxd n receiver serial data inputs for the uart modules. data is received on this pin lsb first. when the uart clock is stopped for power-down mode, any transition on this pin restarts it. i clear-to-send ucts n indicate to the uart modules that they can begin data transmission. i request-to-send urts n automatic request-to-send outputs from the uart modules. this signal can also be configured to be asserted and negated as a function of the rxfifo level. o table 2-10. dma timer signals signal name abbreviation function i/o dma timer input dtin event input to the dma timer modules. i dma timer output dtout programmable output from the dma timer modules. o table 2-11. adc signals signal name abbreviation function i/o analog inputs an[7:0] inputs to the a-to-d converter. i analog reference v rh reference voltage high and low inputs. i v rl i analog supply v dda isolate the adc circuitry from power supply noise ? v ssa ?
signal descriptions mcf5213 reference manual, rev. 1.1 freescale semiconductor 2-11 preliminary 2.11 general purpose timer signals table 2-12 describes the general purpose timer signals. 2.12 pulse width modulator signals table 2-13 describes the pwm signals. 2.13 debug support signals the signals in table 2-14 are used as the interface to the on-chip jtag controller and also to interface to the bdm logic. table 2-12. gpt signals signal name abbreviation function i/o general purpose timer input/output gpt[3:0] inputs to or outputs from the general purpose timer module i/o table 2-13. pwm signals signal name abbreviation function i/o pwm output channels pwm[7:0] pulse width modulated output for pwm channels o table 2-14. debug support signals signal name abbreviation function i/o jtag enable jtag_en select between debug module and jtag signals at reset i test reset trst this active-low signal is used to initialize the jtag logic asynchronously. i test clock tclk used to synch ronize the jtag logic. i test mode select tms used to sequence the jtag state machine. tms is sampled on the rising edge of tclk. i test data input tdi serial input for test inst ructions and data. tdi is sampled on the rising edge of tclk. i test data output tdo serial output for test inst ructions and data. tdo is tri-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tclk. o development serial clock dsclk development serial clock-internally synchronized input. (the logic level on dsclk is validated if it has the same value on two consecutive rising bus clock edges.) clocks the serial communication port to the debug module during packet transfers. maximum frequency is pstclk/5. at the synchroniz ed rising edge of dsclk, the data input on dsi is sampled and dso changes state. i
signal descriptions mcf5213 reference manual, rev. 1.1 2-12 freescale semiconductor preliminary 2.14 ezport signal descriptions table 2-15 contains a list of ezport external signals breakpoint bkpt breakpoint - input used to request a manual breakpoint. assertion of bkpt puts the processor into a halted state after the current instruction completes. halt status is reflected on processor status/debug data signals (pstddata[7:0]) as the value 0xf. if csr[bkd] is set (disabling normal bkpt functionality), asserting bkpt generates a debug interrupt exception in the processor. i development serial input dsi development serial input -internal ly synchronized input that provides data input for the serial communication port to the debug module, once the dsclk has been seen as high (logic 1). i development serial output dso development serial output -provides serial output communication for debug module responses. dso is registered internally. the output is delayed from the validation of dsclk high. o debug data ddata[3:0] display captured processor data and breakpoint status. the clkout signal can be used by the development system to know when to sample ddata[3:0]. o processor status clock pstclk processor status clock - delayed version of the processor clock. its rising edge appears in the center of valid pst and ddata output. pstclk indicates when the development system should sample pst and ddata values. if real-time trace is not used, setting csr[pcd] keeps pstclk, and pst and ddata outputs from toggling without disabling triggers. non-quiescent operation can be reenabled by clearing csr[pcd], although the external development systems must resynchronize with the pst and ddata outputs. pstclk starts clocking only when the first non-zero pst value (0xc, 0xd, or 0xf) occurs during system reset exception processing. o processor status outputs pst[3:0] indicate core status. debug mode timing is synchronous with the processor clock; status is unrelate d to the current bus transfer. the clkout signal can be used by the development system to know when to sample pst[3:0]. o all processor status outputs allpst logical ?and? of pst[3.0] o table 2-15. ezport signal descriptions signal name abbreviation function i/o ezport clock ezpck shift clock for ezport transfers i ezport chip select e zpc s chip select for signalling the start and end of serial transfers i ezport serial data in ezpd ezpd is sampled on the rising edge of ezpck i ezport serial data out ezpq ezpq transitions on the falling edge of ezpck o table 2-14. debug support signals (continued) signal name abbreviation function i/o
signal descriptions mcf5213 reference manual, rev. 1.1 freescale semiconductor 2-13 preliminary 2.15 power and ground pins the pins described in table 2-16 provide system power and ground to the chip. multiple pins are provided for adequate current capability. all power suppl y pins must have ade quate decoupling (bypass capacitance) for high-frequency noise suppression. table 2-16. power and ground pins signal name abbreviation function i/o pll analog supply vddpll, vsspll dedicated power supply signals to isolate the sensitive pll analog circuitry from the normal levels of noise present on the digital power supply. i positive supply vdd these pins supply positive power to the core logic. i ground vss this pin is the negative supply (ground) to the chip.
signal descriptions mcf5213 reference manual, rev. 1.1 2-14 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-1 chapter 3 coldfire core this section describes the orga nization of the version coldfire ? processor core and an overview of the program-visible registers. for deta iled information on instructions, see the isa_a+ definition in the coldfire family programmer?s reference manual . 3.1 processor pipelines figure 3-2 is a block diagram showing the processor pi pelines of a cf coldfire version core. as with all coldfire cores, the cf processor core is comprised of two separate pi pelines that are decoupled by an instruction buffer. instruction instruction fifo decode & select, address instruction operand data[31:0] instruction fetch cycle 2 instruction pipeline execution fetch pipeline iag ic1 ic2 ied ib dsoc agex address [31:0] instruction buffer address generation fetch cycle 1 early decode generation, execute operand fetch
coldfire core mcf5213 reference manual, rev. 1.1 3-2 freescale semiconductor the instruction fetch pipeline (ifp ) is a -stage pipeline for prefet ching instructions. the prefetched instruction stream is then gated into the two-stage operand execution pipeline (oep), which decodes the instruction, fetches the required ope rands and then executes the require d function. since the ifp and oep pipelines are decoupled by an instruction buffer which serves as a fi fo queue, the ifp is able to prefetch instructions in advance of their actual use by th e oep thereby minimizing time stalled waiting for instructions. the cf pipeline stages include the following: ? instruction fetch pipeline (ifp) ? instruction address genera tion (iag)?calculates the next prefetch address ? instruction fetch cycle 1 (ic1)?initiate s prefetch on the processor?s local bus ? instruction fetch cycle 2 (ic2)?complete s prefetch on the processor?s local bus ? instruction early decode (ied)? generates time-critical decode signals needed for the oep ? instruction buffer (ib)?optional buffer stage mi nimizes effects of fetch latency using fifo queue ? operand execution pipeline (oep) ? decode and select/operand fetch cycle (dso c)?decodes instructions and fetches the required components for eff ective address calculation, or the operand fetch cycle ? address generation/execute cycle (agex)?cal culates operand addre ss or executes the instruction for register-to-register and register-to-memory store operations , the instruction passes through both oep stages once. for memory-to-register and read-modi fy-write memory operations, an instruction is effectively staged through the oep twice: the first time to calculate the effectiv e address and initiate the operand fetch on the processor?s local bus, and the se cond time to complete the operand reference and perform the required function defined by the instruction. the resulting pipeline and local bus structure allows the cf32 processor core to deliver sustained high performance across a variety of de manding embedded applications. see table 1-1 for details on the performance of this device. 3.2 processor register description the following sections describe the processor regist ers in the user and supervisor programming models. the appropriate programming model is selected based on the privilege level (user mode or supervisor mode) of the processor as defined by th e s bit of the status register (sr). table 3-3 lists the processor registers. 3.2.1 user programming model table 3-1 illustrates the user programming model. the user programming model is the same as the m68000 family microprocessors, consis ting of the following registers: ? 16 general-purpose 32-bi t registers (d0?d7, a0?a7) ? 32-bit program counter (pc)
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-3 ? 8-bit condition code register (ccr) figure 3-1. coldfire family user programming model 3.2.2 data registers (d0?d7) registers d0?d7 are used as data registers for bit (1-bit), byte (8-bit ), word (16-bit) and longword (32-bit) operations; they can also be used as index registers. note registers d0 and d1 contai n hardware configuration details after reset. see section 3.7.14, ?reset exception? for more details. 3.2.3 address registers (a0?a6) these registers can be used as softwa re stack pointers, index registers, or base addr ess registers; they can also be used for word and longword operations. 3.2.4 stack pointers (a7) this coldfire implementationsupports two unique stack pointer (a7) registers?the supervisor stack pointer (ssp) and the user stack pointer (usp). this support provide s the required isolation between operating modes of the processor. the ssp is described in section 3.2.8.2, ?supervisor/user stack pointers (a7 and other_a7) .? a subroutine call saves the pc on the stack and the return restores it from the stack. both the pc and the sr are saved on the supervisor stack during the pro cessing of exceptions and inte rrupts. the return from exception (rte) instruction restores the sr and pc values from the supervisor stack. 31 0 d0 data registers d1 d2 d3 d4 d5 d6 d7 31 0 a0 address registers a1 a2 a3 a4 a5 a6 a7 stack pointer pc program counter ccr condition code register
coldfire core mcf5213 reference manual, rev. 1.1 3-4 freescale semiconductor 3.2.5 program counter (pc) the pc contains the address of the currently executing instruction. during instruction execution and exception processing, the processor auto matically increments the contents of the pc or places a new value in the pc, as appropriate. for some addressing modes, the pc is used as a base address for pc-relative operand addressing. 3.2.6 condition code register (ccr) the ccr is the lsb of the proc essor status register (sr). the branch prediction bit, bit 7, provides a mechanism to alter the static algorithm used by the branch acceleration logic on the ifp. bits 4?0 act as indicator flags for results generated by processor operations. the extend bit (x) is also used as an input operand during multipreci sion arithmetic computations . 3.2.7 mac register description the registers in the mac portion of the us er programming model, are described in chapter 4, ?enhanced multiply-accumulate unit (emac) ,? and include the following registers: 76543210 field 0 0 0 x n z v c reset 0 1 1 read-only 0 1 0 1 ????? address lsb of status register (sr) figure 3-2. condition code register (ccr) table 3-1. ccr field descriptions bits field description 7 p branch prediction bit. alters th e static prediction algorithm used by the branch acceleration logic in the ifp on forward conditional branches. 0 forward conditional branch instruct ions are predicted as not taken. 1 forward conditional branch instru ctions are predicted as taken. note: all backward bcc instructions are predicte d as taken, regardless of this bit. 6-5 ? reserved, should be cleared. 4 x extend condition code bit. set to the value of the c-bit for arithmetic operations; otherwise not affected or set to a specified result. 3 n negative condition code bit. set if the most significant bit of the result is set; otherwise cleared. 2 z zero condition code bit. set if the result equals zero; otherwise cleared. 1 v overflow condition code bit. set if an arithm etic overflow occurs implying that the result cannot be represented in the operand size; otherwise cleared. 0 c carry condition code bit. set if a carry out of the operand msb occurs for an addition, or if a borrow occurs in a subtraction; otherwise cleared
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-5 ? a 32-bit accumulator (acc) ? a 16-bit mask register (mask) ? a 32-bit status register (macsr) these registers are shown in table 3-2 . 3.2.8 supervisor register description only system control software is intended to use the supervisor programming model to implement restricted operating system functions, i/o control, and memory management. all accesses that af fect the control features of coldfire pro cessors are in the supervisor programmi ng model, which consists of registers available in user mode as well as the following control registers: ? 16-bit status register (sr) ? 32-bit supervisor stack pointer (ssp) ? 32-bit vector base register (vbr) ? 32-bit cache control register (cacr) ? two 32-bit access control registers (acr0, acr1) ? two 32-bit memory base addre ss register (rambar, flashbar) the supervisor programming model consis ts of the registers available to us ers as well as the registers listed in figure 3-3 . table 3-2. mac register set 31:24 23:16 15:8 7:0 mnemonic mac status register macsr mac accumulator 0 acc0 mac accumulator 1 acc1 mac accumulator 2 acc2 mac accumulator 3 acc3 extensions for acc0 and acc1 accext01 extensions for acc2 and acc3 accext23 mac mask register mask
coldfire core mcf5213 reference manual, rev. 1.1 3-6 freescale semiconductor figure 3-3. supervisor programming model the following paragraphs describe the supervisor programming model registers. 3.2.8.1 status register (sr) the sr stores the processor status and includes the ccr, the interrupt priority mask, and other control bits. in supervisor mode, software can access the en tire sr. in user mode, only the lower 8 bits are accessible (ccr). the control bits indicate the follow ing states for the processor: trace mode (t bit), supervisor or user mode (s bit), a nd master or interrupt state (m bit) . all defined bits in the sr have read/write access when in supervisor m ode. sr is set to 0x27 after reset. th e sr register must be explicitly loaded after reset and before any compare, bcc or scc instructions are executed. 31 19 15 0 (ccr) sr status register other_a7 supervisor a7 stack pointer must be zeros vbr vector base register cacr cache control register asid address space id register acr0 access control register 0 (data) acr1 access control register 1 (data) acr2 access control register 2 (instruction) acr3 access control register 3 (instruction) mmubar mmu base address register rambar0 ram base address register 0 rambar1 ram base address register 1 flashbar flash base address register ipsbar module base address register system byte condition code register (ccr) 1514131211109876543210 field t ? s m ? i ??? x n z v c reset000000000 1 1 read-only 0 1 0 1 ????? address cpu @ 0x80e figure 3-4. status register (sr) table 3-3. sr field descriptions bits field description 15 t trace enable. when set, the processor performs a trace exception after every instruction. 14 ? reserved, should be cleared. 13 s supervisor/user state. denotes whether the processor is in supervisor mode (s = 1) or user mode (s = 0). 12 m master/interrupt state. this bit is cleared by an interrup t exception, and can be set by software during execution of the rte or move to sr instructions. 11 ? reserved, should be cleared.
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-7 3.2.8.2 supervisor/user stack pointers (a7 and other_a7) this coldfire architecture supports two independent stack pointer (a7) registers?the supervisor stack pointer (ssp) and the user stac k pointer (usp). the hardware implementation of these two programmable-visible 32-bit registers does not identify one as the ssp and the ot her as the usp. instead, the hardware uses one 32-bit regist er as the active a7 and the other as other_a7. thus, the register contents are a function of the processor operation mode, as shown in the following: if sr[s] = 1 then a7 = supervisor stack pointer other_a7 = user stack pointer else a7 = user stack pointer other_a7 = supervisor stack pointer the bdm programming model supports direct reads and writes to a7 and other_a7. it is the responsibility of the external deve lopment system to determine, base d on the setting of sr[s], the mapping of a7 and other_a7 to the two program-visible definitions (ssp and usp). to support dual stack pointers, the following two supervisor instructions are included in the coldfire instruction set architecture to load/store the usp: move.l ay, usp; move to usp move.l usp, ax; move from usp these instructions ar e described in the coldfire family programmer?s reference manual . 3.2.8.3 vector base register (vbr) the vbr contains the base address of the exception ve ctor table in memory. to access the vector table, the displacement of an exception vector is added to the value in vbr. the lower 20 bits of the vbr are not implemented by coldfire processors ; they are assumed to be zero, forc ing the table to be aligned on a 1 mbyte boundary. 3.2.8.4 cache control register (cacr) the cacr controls operation of th e instruction/data cache memories . it includes bits for enabling, freezing, and invalidating cache cont ents. it also includes bits fo r defining the default cache mode and write-protect fields. the cacr is described in section 5.2.1.1, ?cache control register (cacr) .? 10-8 i interrupt level mask. defines the current interrupt level. interrupt requests are inhibited for all priority levels less t han or equal to the current level, except the edge-se nsitive level 7 request, which cannot be masked. 7-0 ccr refer to ta b l e 3 - 1 . table 3-3. sr field descriptions (continued) bits field description
coldfire core mcf5213 reference manual, rev. 1.1 3-8 freescale semiconductor 3.2.8.5 access control registers (acr0, acr1) the access control registers, ac r0 and acr1, define attribut es for two user-defined memory regions. these attributes includ e the definition of cache mode, write protect, and buffer write enables. the acrs are described in section 5.2.1.2, ?access contro l registers (acr0, acr1) .? 3.2.8.6 memory base address register (rambar, flashbar) memory base address registers are used to specify the base address of the internal sram and flash modules and indicate the ty pes of references mapped to each. each base address register includes a base address, write-protect bi t, address space mask bits, and an en able bit. for the mcf5213, flashbar determines the base address of the on-chip flash, and rambar dete rmines the base address of the on-chip ram. for more information, refer to section 5.2.1, ?sram base a ddress register (rambar) .? 3.3 memory map/register definition table 3-4 lists register names, the cpu space location, a nd whether the register is written from the processor using the movec instruction. table 3-4. coldfire cpu registers name cpu space (rc) written with movec register name memory management control registers cacr 0x002 yes 0x0000_0000 cache control register acr0, acr1 0x004?0x005 yes undefined access control registers 0 and 1 processor general-purpose registers processor miscellaneous registers other_a7 0x800 no undefined other stack pointer vbr 0x801 yes 0x0000_0000 vector base register macsr 0x804 no 0x0000_0000 mac status register mask 0x805 no 0xffff_ffff mac address mask register acc0?acc3 0x806, 0x809, 0x80a, 0x80b no undefined mac accumulators 0-3 accext01 0x807 no undefined mac accumulator 0, 1 extension bytes accext23 0x808 no undefined mac accumulator 2, 3 extension bytes sr 0x80e no 0x27?? status register pc 0x80f yes undefined program counter local memory registers flashbar 0xc04 yes 0x0000_0000 flash base address register rambar 0xc05 yes 0x0000_0000 sram base address register
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-9 3.4 additions to the instruction set architecture the original coldfire instruc tion set architect ure (isa) was derived fro m the m68000-family opcodes based on extensive analysis of em bedded application code. after the initial coldfire compilers were created, developers identified isa additions that would enhanc e both code density and overall performance. additionally, as users implemented coldfire-based designs into a wide range of embedded systems, they identified frequently used instructi on sequences that could be improved by the creation of new instructions. this observation was especially prev alent in development environments that made use of substantial amounts of assembly language code. table 3-5 summarizes the new instructi ons added to the revision a+ is a. for more details see the coldfire family programmer?s reference manual . 3.5 exception processing overview exception processing for coldfire pr ocessors is streamlined for perfor mance. the coldfire processors differ from the m68000 family in that they include: ? a simplified exception vector table ? reduced relocation capabilities us ing the vector base register ? a single exception stack frame format ? use of a single self-aligning stack poi nter (for isa_a im plementations only) all coldfire processors use an instruction restart exception model, but certain microarchitectures (cf2 and cf3) require more softwa re support to recover from certain access errors. see section 3.7.1, ?access error exception ? for details. exception processing include s all actions from the detec tion of the fault condition to the initiation of fetch for the first handler instruction. exception pr ocessing is comprised of four major steps. table 3-5. isa revision a+ new instructions instruction description bitrev the contents of the destination data register ar e bit-reversed; that is, new dn[31] = old dn[0], new dn[30] = old dn[1], ..., new dn[0] = old dn[31]. byterev the contents of the destination data register are byte-reversed; that is, new dn[31:24] = old dn[7:0], ..., new dn[7:0] = old dn[31:24]. ff1 the data register, dn, is scanned, beginning fr om the most-significant bit (dn[31]) and ending with the least-significant bit (dn[0]), searching for the first set bit. the data register is then loaded with the offset count from bi t 31 where the first set bit appears. move from usp usp destination move to usp source usp stldsr pushes the contents of the status register on to the stack and then reloads the status register with the immediate data value.
coldfire core mcf5213 reference manual, rev. 1.1 3-10 freescale semiconductor first, the processor makes an internal copy of the sr and then enters supervis or mode by asserting the s bit and disabling trace mode by negating the t bit. the occurrence of an interrupt exception also forces the m bit to be cleared and the interrupt priority mask to be set to the level of the current interrupt request. second, the processor determines the exce ption vector number. for all faults except interrupts, the processor performs this calculati on based on the exception type. for inte rrupts, the processor performs an interrupt-acknowledge (iack) bus cycl e to obtain the vector number from the interrupt controller. the iack cycle is mapped to a special acknowledge addr ess space with the interrupt level encoded in the address. third, the processor saves the current context by cr eating an exception stack frame on the system stack. processors implementing isa_a suppor t a single stack pointer in the a7 address register; therefore, there is not notion of separate supervisor and user stack pointer. as a result , the exception stack frame is created at a 0-modulo-4 address on top of the current system stack. for processors implementing all other isa revisions and supporting 2 stack point ers, the exception stack frame is created at a 0-m odulo-4 address on top of the system stack defined by the supervisor stack pointer (ssp). additionally, the processor uses a simplified fixed-length stack frame for all exceptions. the exception t ype determines whether the program counter placed in the exception stack frame defines the location of the faulting instructi on (fault) or the address of the next instruction to be executed (next). fourth, the processor calculates the a ddress of the first instruction of the exception handler. by definition, the exception vector table is aligned on a 1 mbyte boundary. this instruction address is generated by fetching an exception vector from the table located at the addr ess defined in the vect or base register. the index into the exception table is cal culated as (4 x vector number). on ce the exception vector has been fetched, the contents of the vector de termine the address of the first inst ruction of the desired handler. after the instruction fetch for the first opc ode of the handler has been initiat ed, exception processing terminates and normal instruction processi ng continues in the handler. all coldfire processors support a 1024-byte vector table aligned on any 1 mbyte address boundary (see table 3-6 ). the table contains 256 exception vectors; the first 64 are defined by freescale and the remaining 192 are user-def ined interrupt vectors. table 3-6. exception vector assignments vector number(s) vector offset (hex) stacked program counter assignment 0 0x000 ? initial stack pointer 1 0x004 ? initial program counter 2 0x008 fault access error 3 0x00c fault address error 4 0x010 fault illegal instruction 5 0x014 fault divide by zero 6?7 0x018?0x01c ? reserved 8 0x020 fault privilege violation 9 0x024 next trace
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-11 all coldfire processors inhibit interrupt sampling dur ing the first instruction of all exception handlers. this allows any handler to effectively disable interr upts, if necessary, by raising the interrupt mask level contained in the status re gister. in addition, the isa_a+ architec ture includes an instruction (stldsr) that stores the current interrupt mask level and loads a value into the sr. this instruction is specifically intended for use as the first instruction of an interr upt service routine which services multiple interrupt requests with different interrupt levels. for more details see the coldfire family programmer?s reference manual . 3.6 exception stack frame definition the exception stack frame is shown in figure 3-5 . the first longword of the ex ception stack frame contains the 16-bit format/vector word (f/v) and the 16-bit status register, a nd the second longword contains the 32-bit program counter address. figure 3-5. exception stack frame form the 16-bit format/vector word contains 3 unique fields: ? a 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by the processor indicating a tw o-longword frame format. see table 3-7 . 10 0x028 fault unimplemented line-a opcode 11 0x02c fault unimplemented line-f opcode 12 0x030 next debug interrupt 13 0x034 ? reserved 14 0x038 fault format error 15?23 0x03c?0x05c ? reserved 24 0x060 next spurious interrupt 25?31 0x064?0x07c ? reserved 32?47 0x080?0x0bc next trap # 0-15 instructions 48?63 0x0c0?0x0fc ? reserved 64?255 0x100?0x3fc next user-defined interrupts ?fault? refers to the pc of the instruction that caused the except ion; ?next? refers to the pc of the next instruction that follows the instruction that caused the fault. table 3-6. exception vector assignments (continued) vector number(s) vector offset (hex) stacked program counter assignment ssp + 0x4 31 17 15 0 27 25 format fs[3:2] vector[7:0] fs[1:0] status register program counter[31:0]
coldfire core mcf5213 reference manual, rev. 1.1 3-12 freescale semiconductor ? there is a 4-bit fault st atus field, fs[3:0], at the top of the system stack. th is field is defined for access and address errors only a nd written as zeros for all ot her types of exceptions. see table 3-8 . ? the 8-bit vector number, vector[7 :0], defines the exception type a nd is calculated by the processor for all internal faults a nd represents the value suppl ied by the interrupt controll er in the case of an interrupt. refer to table 3-6 . 3.7 processor exceptions 3.7.1 access error exception the exact processor response to an access error depends on the type of memory reference being performed. for an instruction fetch, the proce ssor postpones the error reporting until the faulted reference is needed by an instruction for execution. therefore, faults that occur during instruction pr efetches that are then followed by a change of instruction flow do not gene rate an exception. when the processor attempts to execute an instruction with a faulted opword and/or extension word s, the access error is signaled and the instruction aborted. for this type of exception, the programming model has not been altered by the instruction generating the access error. table 3-7. format field encodings original ssp @ time of exception, bits 1:0 ssp @ 1st instruction of handler format field 00 original ssp - 8 4 01 original ssp - 9 5 10 original ssp - 10 6 11 original ssp - 11 7 table 3-8. fault status encodings fs[3:0] definition 00xx reserved 0100 error on instruction fetch 0101 reserved 011x reserved 1000 error on operand write 1001 attempted write to write-protected space 101x reserved 1100 error on operand read 1101 reserved 111x reserved
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-13 if the access error occurs on an operand read, the proc essor immediately aborts the current instruction?s execution and initiates exception proces sing. in this situation, any address register upda tes attributable to the auto-addressing modes, (for example, (an)+,-(an )), have already been performed, so the programming model contains the updated an value. in addition, if an access error occurs during the execution of a movem instruction loading from me mory, any registers already updated before the fault occurs contain the operands from memory. the cf coldfire processor uses an imprecise re porting mechanism for access errors on operand writes. because the actual write cycle may be decoupled from the processo r?s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. accordingly, the pc contai ned in the exception stack frame merely represents the location in the program when the access error was signaled. al l programming model updates associat ed with the write instruction are completed. the nop instruction can collect access errors for writes. this instruction delays its execution until all previous operations, including al l pending write operations, are complete. if any previous write terminates with an access error, it is guaranteed to be reported on the nop instruction. 3.7.2 address error exception any attempted execution transferring c ontrol to an odd instruction address (that is, if bit 0 of the target address is set) results in an address error exception. any attempted use of a word-sized index register (xn.w) or a scale fa ctor of 8 on an indexed effective addressing mode generates an addr ess error as does an attempted ex ecution of a full-format indexed addressing mode. 3.7.3 illegal instruction exception any attempted execution of an illegal 16-bit opcode (e xcept for line-a and line-f opcodes) generates an illegal instruction excepti on (vector 4). additionally, any attempted execution of any non-mac line-a and most line-f opcode generates their unique excepti on types, vector numbers 10 and 11, respectively. coldfire cores do not provide illegal instruction de tection on the extension wo rds on any instruction, including movec. 3.7.4 divide-by-zero attempting to divide by zero causes an exception (vector 5, offset = 0x014). 3.7.5 privilege violation the attempted execution of a supervisor mode inst ruction while in user mode generates a privilege violation exception. see the coldfire programmer?s reference manual for a list of supervisor-mode instructions.
coldfire core mcf5213 reference manual, rev. 1.1 3-14 freescale semiconductor 3.7.6 trace exception to aid in program development, all coldfire proce ssors provide an instruction-by-instruction tracing capability. while in trace mode, indicated by setting of the t bit in the status register (sr[15] = 1), the completion of an instructi on execution (for all but the stop instru ction) signals a tr ace exception. this functionality allows a debugger to monitor program execution. the stop instruction has the following effects: 1. the instruction before the stop executes and then generates a trace exception. in the exception stack frame, the pc points to the stop opcode. 2. when the trace handler is exited, the stop in struction is executed, loading the sr with the immediate operand from the instruction. 3. the processor then generates a trace exception. the pc in the exce ption stack frame points to the instruction after the stop, and the sr reflects the value loaded in the previous step. if the processor is not in trace mode and executes a stop instruction where the immediate operand sets sr[t], hardware loads the sr and generates a trace exception. the pc in the exception stack frame points to the instruction after the stop, and the sr reflects the value loaded in step 2. because coldfire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for tr ace mode after processing ot her exception types. as an example, consider the execution of a trap instruction while in tra ce mode. the processor will initiate the trap exception and then pass control to the corr esponding handler. if the syst em requires that a trace exception be processed, it is the re sponsibility of the trap exception handler to check for this condition (sr[t] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception. 3.7.7 unimplemented line-a opcode a line-a opcode is defined when bits 15-12 of the opwor d are 0b1010. this excepti on is generated by the attempted execution of an undefined line-a opcode. 3.7.8 unimplemented line-f opcode a line-f opcode is defined when bits 15-12 of the opword are 0b1111. this exception is generated by attempted execution of an undefined line-f opcode. 3.7.9 debug interrupt this special type of program interrupt is discussed in detail in .? this exception is generated in response to a hardware breakpoint register trigger. the processor does not gene rate an iack cycle but rather calculates the vector number internally (vector number 12).
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-15 3.7.10 rte and format error exception when an rte instruction is executed, the processor fi rst examines the 4-bit format field to validate the frame type. for a coldfire core, any attempted rte execution where the format is not equal to {4,5,6,7} generates a format error. the exception stack frame fo r the format error is created without disturbing the original rte frame and the stacked pc pointing to the rte instruction. the selection of the format value provides some limited debug support for porting code from m68000 applications. on m68000 family proc essors, the sr was located at the top of the stack. on those processors, bit 30 of the longword addressed by the syst em stack pointer is typical ly zero. thus, if an rte is attempted using this ?old? format, it gene rates a format error on a coldfire processor. if the format field defines a valid type, the proces sor: (1) reloads the sr operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the firs t longword, and then (4) transfers control to the instruction ad dress defined by the second longword operand within the stack frame. 3.7.11 trap instruction exception the trap #n instruction always forces an exception as part of its execution and is useful for implementing system calls. 3.7.12 interrupt exception interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from the interrupt controller using an iack cycle. see ,? for details on the interrupt controller. 3.7.13 fault-on-fault halt if a coldfire processor encounters a ny type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic ?fault-on-fau lt? condition. a re set is required to force the processor to exit this halted state. 3.7.14 reset exception asserting the reset input signal to the processor ca uses a reset exception. the reset exception has the highest priority of any exception; it provides for system initialization and re covery from catastrophic failure. reset also aborts any processing in progress when the re set input is recognized. processing cannot be recovered. the reset exception places the processor in the superv isor mode by setting the s bit and disables tracing by clearing the t bit in the sr. this exception also clears the m bit and sets the processor?s interrupt priority mask in the sr to the highest level (lev el 7). next, the vbr is initialized to zero (0x00000000). the control registers specifying the operation of any memories (e.g., cach e and/or ram modules) connected directly to the processor are disabled.
coldfire core mcf5213 reference manual, rev. 1.1 3-16 freescale semiconductor note other implementation-specifi c registers are also affected. refer to each of the modules in this user?s manual for details on these registers. once the processor is granted the bus , it then performs two longword read bus cycles. the first longword at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program counter. after the initial instruction is fetched from memory, program execution begins at the address in the pc. if an access error or address error occurs befo re the first instruction is executed, the processor enters the fault-on-fault halted state. coldfire processors load hardware configuratio n information into the d0 and d1 general-purpose registers after system reset. the hardware conf iguration information is loaded immediately after the reset-in signal is negated. this allows an emul ator to read out the contents of these registers via bdm to determine the hardware configuration. information loaded into d0 defines the pro cessor hardware configuration as shown in figure 3-11 . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r11 0 01111 version prev w reset11 0 0111100100000 1514131211109876543210 r mac div emac fpu mmu 0 0 0 isa_rev dbg_rev w reset 11 0 0000010001001 figure 3-6. d0 hardware configuration info table 3-9. d0 hardware confi guration info field description bits field description 23?20 version coldfire core version number. this 4-bit field defines the hardware microarchitecture (version) of the coldfire core. if version = 0b0010, then version 2 coldfire if version = 0b0011, then version 3 coldfire if version = 0b0100, then version 4 coldfire if version = 0b0101, then version 5 coldfire all other values are reserved for future use. the upper 12 bits of the d0 reset value direct ly identify the coldfire core version, e.g., ?cf2? for a version 2 core, ?cf3? for a version 3 core, etc. 19?16 prev processor revision number. the default is 0b0000. 15 mac mac present.this bit signals if the optional multiply-accumulate (mac) execution engine is present in the processor core. 0 mac execute engine not present in core. 1 mac execute engine is present in core. (this is the value used for this device.) if an emac is present, this bit is cleared.
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-17 information loaded into d1 defines the local memory hardware configuration as shown in figure 3-11 . 14 div divide present. this bit signals if the hardware divider (div) is present in the processor core. certain early v2 core implementations , e.g., mcf5202, mcf5204, mcf5206, did not include hardware support for integer divide operations. 0 divide execute engine not present in core. 1 divide execute engine is present in core.(this is the value used for this device.) 13 emac emac present. this bit signals if the optional enhanced multiply-accumulate (emac) execution engine is present in the processor core. 0 emac execute engine not present in core. (this is the value used for this device.) 1 emac execute engine is present in core.if an mac is present, this bit is cleared. 12 fpu fpu present. this bit signals if the opti onal floating-point (fpu) execution engine is present in the processor core. 0 fpu execute engine not present in core. (this is the value used for this device.) 1 fpu execute engine is present in core. 11 mmu mmu present. this bit signals if the opti onal virtual memory management unit (mmu) is present in the processor core. 0 mmu execute engine not present in core.(this is the value used for this device.) 1 mmu execute engine is present in core. 10? ? reserved. 7?4 isa_rev isa revision. this 4-bit field defines the inst ruction set architecture (isa) revision level implemented in the coldfire processor core. if isa_rev = 0b0000, then isa_a if isa_rev = 0b1000, then isa_a+. (this is the value used for this device.) if isa_rev = 0b0001, then isa_b if isa_rev = 0b0010, then isa_c all other values are reserved for future use. 3?0 dbg_rev debug module revision number. this 4-bit field defines the revision level of the debug module implemented in the coldfire processor core. if dbg_rev = 0b0000, then debug_a. ( if dbg_rev = 0b1000, then debug_a+ if dbg_rev = 0b0001, then debug_b if dbg_rev = 0b1001, then debug_b+. (this is the value used for this device.) if dbg_rev = 0b0010, then debug_c if dbg_rev = 0b0011, then debug_d if dbg_rev = 0b0100, then debug_e all other values are reserved for future use. table 3-9. d0 hardware confi guration info field description bits field description
coldfire core mcf5213 reference manual, rev. 1.1 3-18 freescale semiconductor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r clsz icas icsz sram0sz ? w reset0001000010010000 reset0001000010100000 1514131211109876543210 r mbsz dcas dcsz[3:0] sram1sz[3:0] ? w reset0001000010000000 reset0001000001100000 reset0001000001110000 figure 3-7. d1 hardware configuration info table 3-10. d1 local memory hardware c onfiguration information field description bits name description 31?30 clsz cache line size. this field is fixed to a hex value of 0x0 indicating a 16-byte cache line size. 29?28 icas instruction cac he associativity. 00 four-way. 01 direct mapped. (this is the value used for this device) 27?24 icsz instruction cache size. 0000 no instruction cache. 0001 512b instruction cache. 0010 1kb instruction cache. 0011 2kb instruction cache. 0100 4kb instruction cache. 0101 8kb instruction cache. 0110 16kb instruction cache. 0111 32kb instruction cache. 1000 64kb instruction cache. 0x9?0xf reserved. all other values do not apply for this device.
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-19 23?20 sram0sz sram bank 0 size. the first ram bank can be used for either sram or flash. the first encoding shown are used to indicate the si ze of a ram bank, and the second set of encodings indicate the size for a flash bank. ram size encodings: if sram0sz = 0b0000, then no sram0. if sram0sz = 0b0001, then sram0 size is 512 bytes if sram0sz = 0b0010, then sram0 size is 1 kbytes if sram0sz = 0b0011, then sram0 size is 2 kbytes if sram0sz = 0b0100, then sram0 size is 4 kbytes if sram0sz = 0b0101, then sram0 size is 8 kbytes if sram0sz = 0b0110, then sram0 size is 16 kbytes if sram0sz = 0b0111, then sram0 size is 32 kbytes if sram0sz = 0b1000, then sram0 size is 64 kbytes if sram0sz = 0b1001, then sram0 size is 128 kbytes all other values are reserved for future use. flash size encodings: 0000-0111, then no flash. if sram0sz = 0b1000, then 64kb flash. if sram0sz = 0b1001, then 128kb flash. if sram0sz = 0b1010, then 256kb flash. if sram0sz = 0b1011, then 512kb flash. all other values are reserved for future use. 19?16 ? reserved 15?14 mbsz mbus size. encoded bus data width. this 2-bit field defines the width of the coldfire master bus datapath. if mbsz = 0b00, then 32- bit system bus datapath if mbsz = 0b01, then 64- bit system bus datapath all other values are reserved for future use. 13?12 dcas d-cache associativity . this 2-bit field defines the d-cache set-associativity. if dcas = 0b00, then d-cache is 4-way set-associative organization. if dcas = 0b01, then d-cache is direct-mapped organization. (this is the value used for this device) all other values are reserved for future use. 11?8 dcsz d-cache size. unified (instruction or data) cache size. if dcsz = 0b0000, then no d-cache. (this is the value used for this device) if dcsz = 0b0001, then d-cache size is 512 bytes if dcsz = 0b0010, then d-cache size is 1 kbytes if dcsz = 0b0011, then d-cache size is 2 kbytes if dcsz = 0b0100, then d-cache size is 4 kbytes if dcsz = 0b0101, then d-cache size is 8 kbytes if dcsz = 0b0110, then d-cache size is 16 kbytes if dcsz = 0b0111, then d-cache size is 32 kbytes if dcsz = 0b1000, then d-cache size is 64 kbytes all other values are reserved for future use. table 3-10. d1 local memory hardware c onfiguration information field description bits name description
coldfire core mcf5213 reference manual, rev. 1.1 3-20 freescale semiconductor information loaded into d1 defines the local memory hardware configuration as shown in figure 3-11 . 3.8 instruction execution timing this section presents cf processor instruction executi on times in terms of proce ssor core clock cycles. the number of operand references for eac h instruction is enclosed in parentheses following the number of processor clock cycles. each timing en try is presented as c(r/w) where: ?c is the number of processor cloc k cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution. ? r/w is the number of operand reads (r) and writ es (w) required by the in struction. an operation performing a read-modify-write function is denoted as (1/1). this section includes the assumptions concerning the timing values and the execution time details. 3.8.1 timing assumptions for the timing data presented in this section, the followi ng assumptions apply: 1. the oep is loaded with the opword and all requ ired extension words at the beginning of each instruction execution. this implie s that the oep does not wait for the ifp to supply opwords and/or extension words. 2. the oep does not experience a ny sequence-related pipeline sta lls.the most common example of this type of stall involves c onsecutive store operations, excludi ng the movem instruction. for all store operations (except movem), certain hardware resources with in the processor are marked as ?busy? for two clock cycles af ter the final decode and select/ operand fetch cycle (dsoc) of the store instruction. if a subsequent store instruction is encountered within this 2-cycle window, it is stalled until the resource again becomes availa ble. thus, the maximum pipeline stall involving consecutive store operations is 2 cycles. the movem instruction uses a different set of resources and this stall does not apply. 7?4 sram1sz sram bank 1 size. the second ram bank can is used only for sram if sram1sz = 0b0000, then no sram1 if sram1sz = 0b0001, then sram1 size is 512 bytes if sram1sz = 0b0010, then sram1 size is 1 kbytes if sram1sz = 0b0011, then sram1 size is 2 kbytes if sram1sz = 0b0100, then sram1 size is 4 kbytes . if sram1sz = 0b0101, then sram1 size is 8 kbytes. if sram1sz = 0b0110, then sram1 size is 16 kbytes if sram1sz = 0b0111, then sram1 size is 32 kbytes if sram1sz = 0b1000, then sram1 size is 64 kbytes. if sram1sz = 0b1001, then sram1 size is 128 kbytes all other values are reserved for future use. 3-0 ? reserved table 3-10. d1 local memory hardware c onfiguration information field description bits name description
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-21 3. the oep completes all memory acc esses without any stall conditions caused by the memory itself. thus, the timing details provided in this section assume that an infi nite zero-wait state memory is attached to the processor core. 4. all operand data accesses are aligned on the same byte boundary as the ope rand size, i.e., 16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands al igned on 0-modulo-4 addresses. the processor core decomposes misa ligned operand references into a seri es of aligned a ccesses as shown in table 3-11 . note each timing entry is presented as c(r/w) where: c is the number of processor clock cycles, including all applicable operand fetches and writes, as well as all inte rnal core cycles re quired too complete the instruction execution. r/w is the number of operand reads (r) and writes (w) required by the instruction. an operation performing a read-modify write function is denoted as (1/1). 3.8.2 move instruction execution times table 3-12 lists execution times fo r move.{b,w} instructions; table 3-13 lists timings for move.l. for all tables in this section, the execut ion time of any instruction using the pc-relative effective addressing modes is the same for the comparable an-relative mode.the nomenclature ?xxx.w l? refers to both forms of absolute addressing, xxx.w and xxx.l. table 3-11. misaligned operand references address[1:0] size bus operations additional c(r/w) x1 word byte, byte 2(1/0) if read 1(0/1) if write x1 long byte, word, byte 3(2/0) if read 2(0/2) if write 10 long word, word 2(1/0) if read 1(0/1) if write table 3-12. move byte and word execution times source destination rx (ax) (ax)+ -(ax) (d16,ax) (d8,ax,xi*sf) xxx.wl dy 1(0/0) 1(0/1) 1(0/1) 1( 0/1) 1(0/1) 2(0/1) 1(0/1) ay 1(0/0) 1(0/1) 1(0/1) 1( 0/1) 1(0/1) 2(0/1) 1(0/1) (ay) (1/0) (1/1) (1/1) (1/1) (1/1) (1/1)) (1/1) (ay)+ (1/0) (1/1) (1/1) (1/1) (1/1) (1/1)) (1/1) -(ay) (1/0) (1/1) (1/1) (1/1) (1/1) (1/1) (1/1)
coldfire core mcf5213 reference manual, rev. 1.1 3-22 freescale semiconductor 3.9 standard one operand in struction execution times (d16,ay) (1/0) (1/1) (1/1) (1/1) (1/1) ? ? (d8,ay,xi*sf) (1/0) (1/1) (1/1) (1/1)) ? ? ? xxx.w (1/0) (1/1) (1/1) (1/1) ? ? ? xxx.l (1/0) (1/1) (1/1) (1/1) ? ? ? (d16,pc) (1/0) (1/1) (1/1) 1/1) (1/1) ? ? (d8,pc,xi*sf) (1/0) (1/1) (1/1) (1/1)) ? ? ? #xxx 1(0/0) (0/1) (0/1) (0/1) ? ? ? table 3-13. move long execution times source destination rx (ax) (ax)+ -(ax) (d16,ax ) (d8,ax,xi*sf) xxx.wl dy 1(0/0) 1(0/1) 1(0/1) 1( 0/1) 1(0/1) 2(0/1) 1(0/1) ay 1(0/0) 1(0/1) 1(0/1) 1( 0/1) 1(0/1) 2(0/1) 1(0/1) (ay) 2(1/0) 2(1/1) 2(1/1) 2( 1/1) 2(1/1) 3(1/1) 2(1/1) (ay)+ 2(1/0) 2(1/1) 2(1/1) 2 (1/1) 2(1/1) 3(1/1) 2(1/1) -(ay) 2(1/0) 2(1/1) 2(1/1) 2( 1/1) 2(1/1) 3(1/1) 2(1/1) (d16,ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) ? ? (d8,ay,xi*sf) 3(1/0) 3 (1/1) 3(1/1) (1/1) ? ? ? xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) ? ? ? xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) ? ? ? (d16,pc) 2(1/0) 2(1/1) 2 (1/1) 2(1/1) 2(1/1) ? ? (d8,pc,xi*sf) 3(1/0) 3 (1/1) 3(1/1) 3(1/1) ? ? ? #xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) ? ? ? table 3-14. one operand instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xn*sf) xxx.wl #xxx bitrevdx1(0/0)???? ? ?? byterevdx1(0/0)???? ? ?? clr.b 1(0/0) 1(0/1) 1(0/1 ) 1(0/1) 1(0/1) 2(0/1) 1(0/1) ? clr.w 1(0/0) 1(0/1) 1(0/1 ) 1(0/1) 1(0/1) 2(0/1) 1(0/1) ? table 3-12. move byte and word execution times (continued) source destination rx (ax) (ax)+ -(ax) (d16,ax) (d8,ax,xi*sf) xxx.wl
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-23 3.10 standard two operand instruction execution times clr.l 1(0/0) 1(0/1) 1(0/1 ) 1(0/1) 1(0/1) 2(0/1) 1(0/1) ? ext.wdx1(0/0)???? ? ?? ext.ldx1(0/0)???? ? ?? extb.ldx1(0/0)???? ? ?? ff1dx1(0/0)???? ? ?? neg.ldx1(0/0)???? ? ?? negx.l dx 1(0/0) ???? ? ?? not.ldx1(0/0)???? ? ?? sccdx1(0/0)???? ? ?? swapdx1(0/0)???? ? ?? tst.b 1(0/0) 3(1/0) 3(1/0) 3( 1/0) 3(1/0) 4(1/ 0) 3(1/0) 1(0/0) tst.w 1(0/0) 3(1/0) 3(1/0) 3(1 /0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) tst.l 1(0/0) 2(1/0) 2(1/0) 2( 1/0) 2(1/0) 3(1/ 0) 2(1/0) 1(0/0) table 3-15. two operand instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d16,pc) (d8,an,xn*sf) (d8,pc,xn*sf) xxx.wl #xxx add.l ,rx 1(0/0) 3(1/0) 3(1/0) 3 (1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) add.l dy, ? 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) ? addi.l #imm,dx 1(0/0) ? ? ? ? ? ? ? addq.l #imm, 1(0/0) 3(1/1) 3(1/ 1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) ? addx.l dy,dx 1(0/0) ? ? ? ? ? ? ? and.l ,rx 1(0/0) 3(1/0) 3(1/0) 3 (1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) and.l dy, ? 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) ? andi.l #imm,dx 1(0/0) ? ? ? ? ? ? ? asl.l ,dx 1(0/0) ? ? ? ? ? ? 1(0/0) asr.l ,dx 1(0/0) ? ? ? ? ? ? 1(0/0) bchg dy, 2(0/0) 4(1/1) 4(1/1 ) 4(1/1) 4(1/1) 5(1/1) 4(1/1) ? bchg #imm, 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) ? ? ? bclr dy, 2(0/0) 4(1/1) 4(1/1 ) 4(1/1) 4(1/1) 5(1/1) 4(1/1) ? bclr #imm, 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) ? ? ? table 3-14. one operand instruction execution times (continued) opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xn*sf) xxx.wl #xxx
coldfire core mcf5213 reference manual, rev. 1.1 3-24 freescale semiconductor bset dy, 2(0/0) 4(1/1) 41/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) ? bset #imm, 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) ? ? ? btst dy, 2(0/0) 3(1/1) 3(1/1 ) 3(1/1) 3(1/1) 4(1/1) 3(1/1) ? btst #imm, 1(0/0) 3(1/1) 3 (1/1) 3(1/1) 3(1/1) ? ? 1(0/0) cmp.l ,rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) cmpi.l #imm,dx 1(0/0) ? ? ? ? ? ? ? divs.w ,dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) divu.w ,dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) divs.l ,dx 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) ? ? ? divu.l ,dx 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) ? ? ? eor.l dy, 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) ? eori.l #imm,dx 1(0/0) ? ? ? ? ? ? ? lea ,ax ? 1(0/0) ? ? 1(0/0) 2(0/0) 1(0/0) ? lsl.l ,dx 1(0/0) ? ? ? ? ? ? 1(0/0) lsr.l ,dx 1(0/0) ? ? ? ? ? ? 1(0/0) moveq #imm,dx ? ? ? ? ? ? ? 1(0/0) muls.w y, dx 4(0/0) 6(1/0) 6(1/ 0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(1/0) mulu.w y, dx 4(0/0) 6(1/0) 6(1/ 0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(1/0) muls.l y, dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) ? ? ? mulu.l y, dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) ? ? ? or.l ,rx 1(0/0) 3(1/0) 3(1/0) 3 (1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) or.l dy, ? 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) ? ori.l #imm,dx 1(0/0) ? ? ? ? ? ? ? rems.l ,dx 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) ? ? ? remu.l ,dx 35(0/0) 38(1/0) 38(1/0) 38(1/0) 38(1/0) ? ? ? sub.l ,rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) sub.l dy, ? 3(1/1) 3(1/1) 3 (1/1) 3(1/1) 4(1/1) 3(1/1) ? subi.l #imm,dx 1(0/0) ? ? ? ? ? ? ? subq.l #imm, 1(0/0) 3(1/1) 3(1 /1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) ? subx.l dy,dx 1(0/0) ? ? ? ? ? ? ? table 3-15. two operand instruction execution times (continued) opcode effective address rn (an) (an)+ -(an) (d16,an) (d16,pc) (d8,an,xn*sf) (d8,pc,xn*sf) xxx.wl #xxx
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-25 3.11 miscellaneous instruction execution times table 3-16. miscellaneous instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an,xn*sf) xxx.wl #xxx link.w ay,#imm 2(0/1) ? ? ? ? ? ? ? move.l ay,usp 3(0/0) ? ? ? ? ? ? ? move.l usp,ax 3(0/0) ? ? ? ? ? ? ? move.w ccr,dx 1(0/0) ???? ? ?? move.w ,ccr 1(0/0) ? ? ? ? ? ? 1(0/0) move.w sr,dx 1(0/0) ? ? ? ? ? ? ? move.w ,sr 7(0/0) ? ? ? ? ? ? 7(0/0) 2 movec ry,rc 9(0/1) ? ? ? ? ? ? ? movem.l ,&list ? 1+n(n/0) ? ? 1+n(n/0) ? ? ? movem.l &list, ? 1+n (0/n) ? ? 1+n(0/n) ? ? ? nop 3(0/0) ? ? ? ? ? ? ? pea ? 2(0/1) ? ? 2(0/1) 4 3(0/1) 5 2(0/1) ? pulse 1(0/0)???? ? ?? stldsr#imm????? ? ?5(0/1) stop#imm????? ? ?3(0/0) 3 trap#imm????? ? ?15(1/2) trapf 1(0/0)???? ? ?? trapf.w 1(0/0) ? ? ? ? ? ? ? trapf.l 1(0/0)???? ? ?? unlk ax 2(1/0) ? ? ? ? ? ? ? wddata ? 3(1/0) 3(1/0) 3(1/0 ) 3(1/0) 4(1/0) 3(1/0) 3(1/0) wdebug ? 5(2/0) ? ? 5(2/0) ? ? ? 1 n is the number of registers moved by the movem opcode. 2 if a move.w #imm,sr instruction is executed and imm[13] = 1, the execution time is 1(0/0). 3 the execution time for stop is the time required until the processor begins sampling continuously for interrupts. 4 pea execution times are t he same for (d16,pc). 5 pea execution times are the same for (d8,pc,xn*sf).
coldfire core mcf5213 reference manual, rev. 1.1 3-26 freescale semiconductor 3.12 mac instruction execution times table 3-17. emac instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d8,an, xn*sf) xxx.wl #xxx muls.w y, dx 4(0/0) (1/0) (1/0) (1/0) (1/0) 1/0) (1/0) 4(/0) mulu.w y, dx 4(0/0) (1/0) (1/0) (1/0) (1/0) 1/0) (1/0) 4(/0) muls.l y, dx 4(0/0) (1/0) (1/0) (1/0) (1/0) ? ? ? mulu.l y, dx 4(0/0) (1/0) (1/0) (1/0) (1/0) ? ? ? mac.w ry, rx, raccx 1(0/0) ? ? ? ? ? ? ? mac.l ry, rx, raccx 1(0/0) ? ? ? ? ? ? ? msac.w ry, rx, raccx 1(0/0) ? ? ? ? ? ? ? msac.l ry, rx, raccx 1(0/0) ? ? ? ? ? ? ? mac.w ry, rx, , rw, raccx ? (1/0) (1/0) (1/0) (1/0) 1 1 effective address of (d16,pc) not supported ??? mac.l ry, rx, , rw, raccx ? (1/0) (1/0) (1/0) (1/0) 1 ??? msac.w ry, rx, , rw ? (1/0) (1/0) (1/0) (1/0) 1 ??? msac.l ry, rx, , rw, raccx ? (1/0) (1/0) (1/0) (1/0) 1 ??? mov.l y, raccx 1(0/0) ? ? ? ? ? ? 1(0/0) mov.l raccy,raccx 1(0/0) ? ? ? ? ? ? ? mov.l y, macsr 5(0/0) ? ? ? ? ? ? 5(0/0) mov.l y, rmask 4(0/0) ? ? ? ? ? ? 4(0/0) mov.l y,raccext01 1(0/0) ? ? ? ? ? ? 1(0/0) mov.l y,raccext23 1(0/0) ? ? ? ? ? ? 1(0/0) mov.l raccx,x 1(0/0) 2 2 storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (macsr[7:4] = 1---, -11-, --11) ??? ? ? ?? mov.l macsr,x 1(0/0) ? ? ? ? ? ? ? mov.l rmask, x 1(0/0) ? ? ? ? ? ? ? mov.l raccext01,x 1(0/0) ? ? ? ? ? ? ?
coldfire core mcf5213 reference manual, rev. 1.1 freescale semiconductor 3-27 3.13 branch instruction execution times table 3-18. general branch instruction execution times opcode effective address rn (an) (an)+ -(an) (d16,an) (d16,pc) (d8,an,xi*sf) (d8,pc,xi*sf) xxx.wl #xxx bsr ? ? ? ? (0/1) ? ? ? jmp ? (0/0) ? ? (0/0) (0/0) (0/0) ? jsr ? (0/1) ? ? (0/1) (0/1) (0/1) ? rte ? ? (2/0) ? ? ? ? ? rts ? ? (1/0) ? ? ? ? ? table 3-19. bra, bcc inst ruction execution times opcode forward taken forward not taken backward taken backward not taken bra (0/0) ? (0/0) ? bcc (0/0) 1(0/0) (0/0) (0/0)
coldfire core mcf5213 reference manual, rev. 1.1 3-28 freescale semiconductor
mcf5213 reference manual, rev. 1.1 freescale semiconductor 4-1 preliminary chapter 4 hardware multiply/accumulate (mac) unit this chapter describes the multiply/accumulate (mac) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. th e mac is integrated into the operand execution pipeline (oep). 4.1 overview the mac unit provides hardware support for a limite d set of digital signal processing (dsp) operations used in embedded code, while suppor ting the integer multiply instructi ons in the coldfire microprocessor family. the mac unit provides signal proce ssing capabilities which are useful in a variety of applications including digital audio and se rvo control. integrated as an executi on unit in the processor?s oep, the mac unit implements a three-stage arith metic pipeline optimized for 16 x 16 multiplies. both 16- and 32-bit input operands are supported by this de sign in addition to a full set of extensions for signed and unsigned integers plus signed, fixed-poi nt fractional input operands. the mac unit provides functiona lity in three related areas: ? signed and unsigned integer multiplies ? multiply-accumulate operati ons supporting signed, unsigned, a nd signed fractional operands ? miscellaneous register operations each of the three areas of support is addressed in detail in the succeeding sections. logic that supports this functionality is contained in a mac module, as shown in figure 4-1 . the mac unit is tightly coupled to the oep and feat ures a three-stage execut ion pipeline. to minimize silicon costs, the coldfire mac is optimized for 16 x 16 multiply instructions. the oep can issue a 16 x 16 multiply with a 32-bit accumu lation and fetch a 32-bit operand in the same cy cle. a 32 x 32 multiply with a 32-bit accumulation takes three cycles before the next instruction can be issued. figure 4-1 shows the basic functionality of the coldfire mac. a full set of instructions is provided for signed and unsigned integers plus signed, fixed-poi nt, fractional input operands.
hardware multiply/accumulate (mac) unit mcf5213 reference manual, rev. 1.1 4-2 freescale semiconductor preliminary figure 4-1. coldfire mac multiplication and accumulation the mac unit is an extension of the basic multiplier found on most microprocessors. it can perform operations native to signal processi ng algorithms in an acceptable number of cycles, given the application constraints. for example, small digi tal filters can tolerate some varian ce in the execution time of the algorithm; larger, more complicated algorithms, such as orthogonal transforms, may have more demanding speed requirements excee ding the scope of any processor architecture and requiring a fully developed dsp implementation. the m68000 architecture was not designed for high-speed signal pr ocessing, and a large dsp engine would be excessive in an embedde d environment. in striking a middl e ground between speed, size, and functionality, the cold fire mac unit is optimized for a small set of operations that involve multiplication and cumulative additions. specifi cally, the multiplier array is opt imized for single-cycle, 16 x 16 multiplies producing a 32-bit result, with a possible accumulation cycle following. this is common in a large portion of signal processing applications. in addition, the cold fire core architecture has been modified to allow for an operand fetch in parallel with a multiply, increasing overall performance for certain dsp operations. 4.1.1 mac programming model figure 4-2 shows the registers in the mac por tion of the user programming model. figure 4-2. mac programming model 31 0 macsr mac status register acc mac accumulator mask mac mask register x +/- operand y operand x shift 0,1,-1 accumulator
hardware multiply/accumulate (mac) unit mcf5213 reference manual, rev. 1.1 freescale semiconductor 4-3 preliminary these registers are described as follows: ? accumulator (acc)?this 32-bit, re ad/write, general-purpose regist er is used to accumulate the results of mac operations. ? mask register (mask)?this 16-bi t general-purpose register provid es an optional address mask for mac instructions that fetch operands from memory. it is useful in the implementation of circular queues in operand memory. ? mac status register (macsr)? this 8-bit register defines c onfiguration of the mac unit and contains indicator flags affected by mac instruct ions. unless noted otherwise, the setting of macsr indicator flags is ba sed on the final result, that is, the result of the final operation involving the product and accumulator. 4.1.2 general operation the mac unit supports the coldfire integer multiply instructions (muls and mulu) and provides additional functionality for multip ly-accumulate operations. the added mac instructions to the coldfire isa provide for the multipli cation of two numbers, followed by the addition or subtraction of this number to or from the value contained in the accumulator. the product may be optionally shifted left or right one bit before the addition or subtr action takes place. hardware suppor t for saturation ar ithmetic may be enabled to minimize softwa re overhead when dealing with potentia l overflow conditions using signed or unsigned operands. these mac operations treat the operands as one of the following formats: ? signed integers ? unsigned integers ? signed, fixed-point , fractional numbers to maintain compactness, the mac module is opt imized for 16-bit multipli cations. two 16-bit operands produce a 32-bit product. longword operations are perfor med by reusing the 16-bit multiplier array at the expense of a small amount of extra control logic. again, the pr oduct of two 32-bit operands is a 32-bit result. for longword integer operations, only the least si gnificant 32 bits of the product are calculated. for fractional operations, the entire 63-bit product is calcu lated and either truncated or rounded to a 32-bit result using the round-to-nearest (even) method. because the multiplier arra y is implemented in a 3-st age pipeline, mac instructi ons can have an effective issue rate of one clock for word operations, three for longword inte ger operations, and four for 32-bit fractional operations. arithmetic ope rations use register-based input operands, and summed values are stored internally in the accumulator. thus, an additio nal move instruction is nece ssary to store data in a general-purpose register. mac instruct ions can choose th e upper or lower word of a register as the input, which helps filtering operations in wh ich one data register is loaded wi th input data and another is loaded with coefficient data. two 16-bit mac operations can be performed without fetching additional operands between instructions by alternating th e word choice during the calculations. the need to move large amounts of data quickly can limit throughput in dsp engines. however, data can be moved efficiently by using the movem instruction, which automati cally generates line-sized burst references and is ideal for filling registers quickly with input data, filter co efficients, and output data. loading an operand from memory into a register during a mac operation makes some dsp operations, especially filtering and co nvolution, more manageable. the macsr has a 4-bit operational mode field and three condition fl ags. the operational mode bits control the overflow/saturation mode, whether opera nds are signed or unsigne d, whether operands are treated as integers or fractions, and how rounding is performed. negative, zero, and overflow flags are also provided.
hardware multiply/accumulate (mac) unit mcf5213 reference manual, rev. 1.1 4-4 freescale semiconductor preliminary the three program-visible mac regi sters, a 32-bit accumulat or (acc), the mac mask register (mask), and macsr, are described in section 4.1.1, ?mac programming model .? 4.1.3 mac instruction set summary the mac unit supports the integer mu ltiply operations defined by the ba seline coldfire architecture, as well as the new multiply-accumulate instructions. table 4-1 summarizes the mac unit instruction set. table 4-1. mac instruction summary instruction mnemonic description multiply signed muls y,dx multiplies two signed operands yielding a signed result multiply unsigned mulu y,dx multiplies two unsigned operands yielding an unsigned result multiply accumulate mac ry,rxsf msac ry,rxsf multiplies two operands, then adds or subtracts the product to/from the accumulator multiply accumulate with load mac ry,rxsf,rw msac ry,rxsf,rw multiplies two operands, then adds or subtracts the product to/from the accumulator while loading a register with the memory operand load accumulator mov.l {ry,#imm},acc loads the accumulator with a 32-bit operand store accumulator mov.l acc,rx writes the contents of the accumulator to a register load macsr mov.l {ry,#imm},macsr writes a value to the macsr store macsr mov.l macsr,rx writes the contents of macsr to a register store macsr to ccr mov.l macsr,ccr writes the cont ents of macsr to the processor?s ccr register load mask mov.l {ry,#imm},mask writes a value to mask store mask mov.l mask,rx writes the contents of mask to a register
hardware multiply/accumulate (mac) unit mcf5213 reference manual, rev. 1.1 freescale semiconductor 4-5 preliminary 4.1.4 data representation the mac unit supports three basic operand types: ? two?s complement signed integer: in this format , an n-bit operand represents a number within the range -2 (n-1) < operand < 2 (n-1) - 1. the binary point is to the ri ght of the least significant bit. ? two?s complement unsigned intege r: in this format, an n-bit op erand represents a number within the range 0 < operand < 2 n - 1. the binary point is to the right of the least significant bit. ? two?s complement, signed fractional: in an n-bit number, the first bit is th e sign bit. the remaining bits signify the first n-1 bits after th e binary point. given an n-bit number, a n-1 a n-2 a n-3 ... a 2 a 1 a 0 , its value is given by the following formula: this format can represent numbers in the range -1 < operand < 1 - 2 (n-1) . for words and longwords, the greatest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x0x8000_0000, resp ectively. the most positive word is 0x7fff or (1 - 2 -15 ); the most positive longword is 0x7fff_ffff or (1 - 2 -31 ). 4.2 mac instruction execution timings for information on mac instruct ion execution timings, refer to section 3.12, ?mac instruction execution times check cf2 mac (emac #?s) .? value 1 a n1 ? ? () ?2 i1n ? + () ai ? i0 = n2 ? + =
hardware multiply/accumulate (mac) unit mcf5213 reference manual, rev. 1.1 4-6 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 5-1 preliminary chapter 5 static ram (sram) 5.1 introduction this chapter is a description of the on-chip stat ic ram (sram) implementa tion that covers general operations, configuration, and initia lization. it also provides informat ion and examples showing how to minimize power consumpti on when using the sram. 5.1.1 features features include the following: ? one 32-kbyte sram ? single-cycle access ? physically located on processor's high-speed local bus ? memory location programmable on any 0-modulo-32 kbyte address ? byte, word, and longword address capabilities 5.1.2 operation the sram module provides a general-purpose memory bl ock that the coldfire pr ocessor can access in a single cycle. the location of the memory block can be specified to any 0-modulo-32k address within the 256-mbyte address space (0x8000_0000 - 0x8fff_ ffff). the memory is ideal for storing critical code or data structures or for use as the system stack. be cause the sram module is physically connected to the processor's high-speed local bus, it can service processor-initiated accesses or memory-referencing commands from the debug module. the sram is dual-ported to provide dma access. the sram is partitioned in to two physical memory arrays to allow simultane ous access to both arrays by the proces sor core and another bus master. see chapter 8, ?system control module (scm) ,? for more information. 5.2 register description the sram programming model includes a description of the sram base addr ess register (rambar), sram initialization, a nd power management.
static ram (sram) mcf5213 reference manual, rev. 1.1 5-2 freescale semiconductor preliminary 5.2.1 sram base address register (rambar) the configuration information in the sram base a ddress register (rambar) controls the operation of the sram module. ? the rambar holds the base ad dress of the sram. the movec instruction provides write-only access to this register. ? the rambar can be read or written from the debug module. ? all undefined bits in the register are reserv ed. these bits are ignor ed during writes to the rambar and return zeroes when read from the debug module. ? the rambar valid bit is cleared by reset, di sabling the sram module. all other bits are unaffected. note do not confuse this rambar with the scm rambar in section 8.4.2, ?memory base addres s register (rambar) .? although simila r, this core rambar enables core access to the sram memory, while the scm rambar enables peripheral (e .g. dma) access to the sram. the rambar contains several control fields. these fields are shown in figure 5-1 . address: cpu + 0x0c05 access: core write-only debug read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 00 0 0 00 w ba 0 0 0 0 priu pril spv wp 0 0 c/i sc sd uc ud v reset00000000000000000000 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-1. sram base address register (rambar) table 5-1. rambar field descriptions field description 31?16 ba base address. defines the 0-modulo-32k base address of the sram module. by programming this field, the sram may be located on any 32-kbyte boundary within the processor?s 256-mbyte address space (0x8000_0000 - 0x8fff_ffff). 15?12 reserved, should be cleared 11?10 priu pril priority bit. priu determines if dma or cpu has priori ty in the upper 16k bank of memory. pril determines if dma or cpu has priority in the lower 16k bank of memo ry. if a bit is set, the cpu has priority. if a bit is cleared, dma has priority. priority is determined according to the following table: note: the recommended setting for the priority bits is 00. priu,pril upper bank priority lower bank priority 00 cpu cpu 01 cpu dma 10 dma cpu 11 dma dma
static ram (sram) mcf5213 reference manual, rev. 1.1 freescale semiconductor 5-3 preliminary 5.2.2 sram initialization after a hardware reset, the cont ents of the sram module are undefi ned. the valid bit of the rambar is cleared, disabling the module. if the sram requi res initialization with instructions or data, the following steps should be performed: 1. load the rambar, mapping the sram module to the de sired location within the address space. 2. read the source data and write it to the sram . there are various instructions to support this function, including memory-to-memory move inst ructions, or the movem opcode. the movem instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this opcode generally provides maximum performance. 3. after the data has been loaded into the sram, it may be appropriate to load a revised value into the rambar with a new set of attributes. these at tributes consist of the write-protect and address space mask fields. 9 spv secondary port valid. allows access by dma 0 dma access to memory is disabled. 1 dma access to memory is enabled. note: the bde bit in the second rambar register must also be set to allow dual port access to the sram. for more information, see section 8.4.2, ?memory base address register (rambar) .? 8 wp write protect. allows only read accesses to the sram. when this bit is set, any attempted write access will generate an access error exception to the coldfire processor core. 0 allows read and write accesses to the sram module 1 allows only read accesses to the sram module 7?6 reserved, should be cleared. 5?1 c/i, sc, sd, uc, ud address space masks (as n ) these five bit fields allow certain types of accesses to be ?masked,? or inhibited from accessing the sram module. the address space mask bits are: c/i = cpu space/interrupt acknowledge cycle mask sc = supervisor code address space mask sd = supervisor data address space mask uc = user code address space mask ud = user data address space mask for each address space bit: 0 an access to the sram module can occur for this address space 1 disable this address space from the sram module. if a reference using this address space is made, it is inhibited from accessing the sram module, and is processed like any other non-sram reference. these bits are useful for po wer management as detailed in section 5.2.4, ?power management.? in most applications the c/i bit is set 0 v valid. when set, this bit enables the sram module; otherwise, the module is disabled. a hardware reset clears this bit. 0 contents of rambar are not valid 1 contents of rambar are valid table 5-1. rambar field descriptions (continued) field description
static ram (sram) mcf5213 reference manual, rev. 1.1 5-4 freescale semiconductor preliminary the coldfire processor or an external debugger us ing the debug module can perf orm these initialization functions. 5.2.3 sram initialization code the following code segment describe s how to initialize the sram. the c ode sets the base address of the sram at 0x2000_0000 and initializes the sram to zeros. rambase equ 0x20000000 ;set this variable to 0x20000000 ramvalid equ 0x00000001 move.l #rambase+ramvalid,d0 ;load rambase + valid bit into d0. movec.l d0, rambar ;load rambar and enable sram the following loop initializes the entire sram to zero: lea.l rambase,a0 ;load pointer to sram move.l #8192,d0 ;load loop counter into d0 (sram size/4) sram_init_loop: clr.l (a0)+ ;clear 4 bytes of sram subq.l #1,d0 ;decrement loop counter bne.b sram_init_loop ;if done, then exit; else continue looping 5.2.4 power management if the sram is used only for data operands, setting the as n bits associated with instruction fetches can decrease power dissipati on. additionally, if the sram contai ns only instructions, masking operand accesses can reduce power dissipation. table 5-2 shows some examples of typical rambar settings. table 5-2. typical rambar setting examples data contained in sram rambar[7:0] instruction only 0x2b data only 0x35 both instructions and data 0x21
mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-1 preliminary chapter 6 clock module the clock module allows the mcf5213 to be configur ed for one of several clocking methods. clocking modes include internal phase-locked loop (pll) clocking with either an external clock reference or an external crystal reference supported by an internal crystal amplifier. th e pll can also be disabled and an external oscillator can be used to clock the device directly. the cl ock module contains the following: ? crystal amplifier and oscillator (osc) ? phase-locked loop (pll) ? reduced frequency divider (rfd) ? status and control registers ? control logic 6.1 features features of the clock module include the following: ? 1- to 16-mhz crystal, 8-mhz on-ch ip relaxation oscillator, or exte rnal oscillator reference options ? 2- to 10-mhz reference crystal oscillator for normal pll mode ? system can be clocked from pll or directly from crystal oscillator or relaxation oscillator ? support for low-power modes ? separate clock out signal ?2 n (0 n 15) low-power divider for extr emely low frequency operation 6.2 modes of operation the clock module can be operated in normal pll mode (default), 1:1 pll mode, or external clock mode (pll disabled). 6.2.1 normal pll mode in normal pll mode, the pll is fully programmable. it can synthesize frequencie s ranging from 4x to 18x the reference frequency and has a post divider capable of reducing this synthesized frequency without disturbing the pll. the pll reference can be eith er a crystal oscillator or an external clock. 6.2.2 1:1 pll mode in 1:1 pll mode, the pll synthesize s a frequency equal to the external clock input reference frequency. the post divider is not active. 6.2.3 external clock mode in external clock mode, the pll is bypassed, and the external clock is applied to extal. the resulting operating frequency is equal to the external clock frequency.
clock module mcf5213 reference manual, rev. 1.1 6-2 freescale semiconductor preliminary 6.3 low-power mode operation this subsection describes the operation of the cloc k module in low-power and halted modes of operation. low-power modes are described in chapter 7, ?power management .? table 6-1 shows the clock module operation in low-power modes. table 6-1. clock module operation in low-power modes in wait and doze modes, the system clocks to the peripherals are enab led, and the clocks to the cpu and sram are stopped. each module can disable its clock locally at the module level. in stop mode, all system clocks ar e disabled. there are several options for enabling or disabling the pll or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time. the pll can be disabled in stop mo de, but requires a wakeup period before it can relock. the oscillator can also be disabled during stop mode, but requires a wakeup period to restart. when the pll is enabled in stop mode (stpmd[1:0]), the external clkout signal can support systems using clkout as the clock source. there is also a fast wakeup opt ion for quickly enabling the system clocks during stop recovery. this eliminates the wakeup recovery time but at the risk of se nding a potentially unstabl e clock to the system. to prevent a non-locked pll freque ncy overshoot when using the fast wakeup option, change the rfd divisor to the current rfd value pl us one before entering stop mode. in external clock mode, there are no wakeup pe riods for oscillator startup or pll lock. 6.4 block diagram figure 6-1 shows a block diagram of the entire clock modu le. the pll block in this diagram is expanded in detail in figure 6-2 . low-power mode clock operation mode exit wait clocks sent to peripheral modules only exit not caused by clock module, but normal clocking resumes upon mode exit doze clocks sent to peripheral modules only exit not caused by clock module, but normal clocking resumes upon mode exit stop all system clocks disabled exit not caused by clock module, but clock sources are re-enabled and normal clocking resumes upon mode exit halted normal exit not caused by clock module
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-3 preliminary . figure 6-1. clock module block diagram clkout xtal external clock osc pllref reference clock pll mfd pllmode locen clkmod[1:0] rstout clkout locks lock locs rfd[2:0] to reset module lolre locre stpmd[1:0] stop mode pllsel disclk pll clock out scaled pll clock out internal clock pllmode clkgen stop mode internal clocks lock fwkup extal
clock module mcf5213 reference manual, rev. 1.1 6-4 freescale semiconductor preliminary figure 6-2. pll block diagram 6.5 signal descriptions the clock module signals are summarized in table 6-2 and a brief description fo llows. for more detailed information, refer to chapter 14, ?signal descriptions .? 6.5.1 extal this input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator. table 6-2. signal properties name function extal oscillator or clock input xtal oscillator output clkout system clock output clkmod[1:0] clock mode select inputs rsto reset signal from reset controller stpmd clkmod[1:0] rstout mfd (4?18) locks lock locs to reset module clkout pllsel disclk mdf[2:0] phase and frequency detect loss of clock detect lock detect charge pump filter vco rfd[2:0] scaled pll clock out pll clock out reference clock locen lolre pllmode locre
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-5 preliminary 6.5.2 xtal this output is an internal oscillat or connection to the exte rnal crystal. if clkm od0 is asserted during reset, xtal is sampled to determine clocking mode. 6.5.3 clkout this output reflects the internal system clock. 6.5.4 clkmod[1:0] these inputs are used to select the clock mode during chip configuration as described in table 6-3 . table 6-3. clocking modes 6.5.5 rsto the rsto pin is asserted by one of the following: ? internal system reset signal ? frcrstout bit in the reset cont rol status register (rcr); see section 29.4.1, ?reset control register (rcr) .? 6.6 memory map and registers the clock module programming model consists of these registers: ? synthesizer control register (syncr)?defines clock operation ? synthesizer status register (synsr)? reflects clock status 6.6.1 module memory map clkmod[1:0] xtal clocking mode 00 0 pll disabled, clock driven by external oscillator. 00 1 pll disabled, clock driven by on-chip oscillator. 01 n/a pll disabled, clock driven by external crystal. 10 0 pll in normal mode, clock driven by external oscillator. 10 1 pll in normal mode, clock driven by on-chip oscillator. 11 n/a pll in normal mode, clock driven by external crystal. table 6-4. clock module memory map ipsbar offset register name access 1 1 s = cpu supervisor mode access only. 0x0012_0000 synthesizer control register (syncr) s 0x0012_0002 synthesizer status register (synsr) s 0x0012_0004 reserved ? 0x0012_0006 lpcr - low power control register s
clock module mcf5213 reference manual, rev. 1.1 6-6 freescale semiconductor preliminary 6.6.2 register descriptions this subsection provides a descript ion of the clock module registers. 6.6.2.1 synthesizer control register (syncr) table 6-5. scm additional registers memory map ipsbar offset register name access 0x0000_000c pprh - peripheral power management register - high s 0x0000_0018 pprl - peripheral power management register - low s 15 14 13 12 11 10 9 8 field lolre mfd2 mfd1 mf d0 locre rfd2 rfd1 rfd0 reset 0001_0000 r/w r/w 76 5 4 32 10 field locen disclk fwkup ? ? clksrc 1 1 the reset value of pllen and clksrc depend on the valu e of clkmod1 during reset (set to 1 if pll is enabled when the device emerges from reset) pllmode pllen 1 reset 0000_0010 r/w r/w address ipsbar + 0x0012_0000 figure 6-3. synthesizer c ontrol register (syncr) table 6-6. syncr field descriptions bit(s) name description 15 lolre loss of lock reset enable. determines how the system handles a loss of lock indication. when operating in normal mode or 1:1 pll mode, the pll must be locked before setting the lolre bit. otherwise reset is immediately asserted. to prevent an immediate reset, the lolre bit must be clear ed before writing the mfd[2:0] bits or entering stop mode with the pll disabled. 1 reset on loss of lock 0 no reset on loss of lock note: in external clock mode, the lolre bit has no effect.
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-7 preliminary 14?12 mfd multiplication factor divider. contain the binary value of the divider in the pll feedback loop. the mfd[2: 0] value is the multiplication fa ctor applied to the reference frequency. when mfd[2:0] are changed or the pll is disabled in stop mode, the pll loses lock. in 1:1 pll mode, mfd[2:0] are i gnored, and the multiplication factor is one. note: in external clock mode, th e mfd[2:0] bits have no effect. 11 locre loss-of-clock reset enable. determines how the system handles a loss-of-clock condition. when the locen bit is clear, locre has no effect. if the locs flag in synsr indicates a loss-of-clock condition, setting the locre bit causes an immediate reset. to prevent an immediate reset, the locre bit must be cleared before entering stop mode with the pll disabled. 1 reset on loss-of-clock 0 no reset on loss-of-clock note: in external clock mode, the locre bit has no effect. 10?8 rfd reduced frequency divider field. the binary value written to rfd[2:0] is the pll frequency divisor. see table in mfd bit description. changing rfd[2:0] does not affect the pll or cause a relock delay. changes in clock frequency are synchronized to the next falling edge of the current system clock. to avoid surpassing the allowable system operating frequency, write to rfd[2:0] only when the lock bit is set. 7 locen enables the loss-of-clock function. locen does not affect the loss of lock function. 1 loss-of-clock function enabled 0 loss-of-clock function disabled note: in external clock mode, the locen bit has no effect . 6 disclk disable clkout determines whether clkout is driven. setting the disclk bit holds clkout low. 1 clkout disabled 0 clkout enabled table 6-6. syncr field descriptions (continued) bit(s) name description (( the following table illustrate s the system frequency mult iplier of the reference frequency 1 in normal pll mode. 1 f sys = f ref x 2(mfd + 2)/2 exp rfd; f ref x 2(mfd + 2) 80 mhz, f sys 80 mhz mfd[2:0] 000 2 (4x) 2 mfd = 000 not valid for f ref < 3 mhz 001 (6x) 010 (8x) (3) 011 (10x) 100 (12x) 101 (14x) 110 (16x) 111 (18x) rfd[2:0] 000 ( 1) 4 6 8 1012141618 001 ( 2) 3 3 default value out of reset 23 4 56789 010 ( 4) 1 3/2 2 5/2 3 7/2 4 9/2 011 ( 8) 1/2 3/4 1 5/4 3/2 7/4 2 9/4 100 ( 16) 1/4 3/8 1/2 5/8 3/4 7/8 1 9/8 101 ( 32) 1/8 3/16 1/4 5/16 3/8 7/16 1/2 9/16 110 ( 64) 1/16 3/32 1/8 5/32 3/16 7/32 1/4 9/32 111 ( 128) 1/32 3/64 1/16 5/64 3/32 7/64 1/8 9/64
clock module mcf5213 reference manual, rev. 1.1 6-8 freescale semiconductor preliminary 6.6.2.2 synthesizer status register (synsr) the synsr is a read-only register th at can be read at a ny time. writing to the synsr has no effect and terminates the cycle normally. figure 6-4. synthesizer st atus register (synsr) 5 fwkup fast wakeup determines when the system clocks are enabled during wakeup from stop mode. 1 system clocks enabled on wakeup regardless of pll lock status 0 system clocks enabled only when pll is locked or operating normally note: when fwkup = 0, if the pll or oscillator is enabled and unintentionally lost in stop mode, the pll wakes up in self-clocked mode or reference clock mode depending on the clock that was lost. in external clock mode, the fwkup bit has no effect on the wakeup sequence. 4?3 ? reserved, should be cleared. 2 clksrc determines whether the pll output clock or the pll reference clock is to drive the system clock. this bit is ignored when the pll is disabled, in which case the pll reference clock will drive the system clock. ha ving this separate bit allows the pll to first be enabled, and then the system clock can be switched to the pll output clock only after the pll has locked. when disabling the pll, the clock can be switched before disabling the pll so that a smooth transfer is ensured. 0) pllreference clock (input clock) drives the system clock. 1) pll output clock drives the system clock (provided the pll is enabled). 1 pllmode determines the operating mode of the pll. this bit should only be changed after reset with the pll disabled. 0) pll operates in 1:1 mode 1) pll operates in normal mode 0 pllen enables and disables the pll. if the pll is enabled out of reset the chip will not leave the reset state until the pl l is locked and the system cl ock will be driven by the pll output clock. use the clksrc control bit to switch the system clock between the pll output clock and pll bypass clock once the pll is enabled. 0) pll is disabled 1) pll is enabled 76 5 4 32 10 field extosc ocosc cryosc locks lock locs ? reset see note 1 see note 2 000 r/w r address ipsbar + 0x0012_0002 note: 1. reset state determined during reset configuration. 2. see the locks and lock bit descriptions. table 6-6. syncr field descriptions (continued) bit(s) name description
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-9 preliminary table 6-7. synsr field descriptions bit(s) name description 7 extosc indicates if an external oscillator is providing the reference clock source 0) reference clock is not external oscillator 1 reference clock is external oscillator 6 ocosc indicates if the on-chip oscillator is providing the reference clock source. 0 reference clock is not on-chip oscillator 1 reference clock is on-chip oscillator 5 cryosc indicates if an external crystal is providing the reference clock source 0 reference clock is not external crystal 1 crystal clock reference 4 locks sticky indication of pll lock status. 1 no unintentional pll loss of lock since last syst em reset or mfd change 0 pll loss of lock since last system rese t or mfd change or currently not locked due to exit from stop with fwkup set the lock detect function sets the locks bit when the pll achieves lock after: a system reset a write to syncr that changes the mf d[2:0] bits when the pll loses lock, locks is cleared. when the pll relocks, locks remains cleared until one of the two listed events occurs. in stop mode, if the pll is intentionally di sabled, then the locks bit reflects the value prior to entering stop mode. however, if fwkup is set, then locks is cleared until the pll regains lock. once lock is regained, the locks bit reflects the value prior to entering stop mode. furthermore, reading the locks bit at the same time that the pll loses lock does not return the current loss of lock condition. in external clock mode, locks remains cleared after reset. in normal pll mode and 1:1 pll mode, locks is set after reset. 3 lock set when the pll is locked. pll lock occurs when the synthesized frequency is within approximately 0.75 percent of the programm ed frequency. the pll loses lock when a frequency deviation of greater than approx imately 1.5 percent occurs. reading the lock flag at the same time that the pll loses lock or acquires lock does not return the current condition of the pll. the power-on reset circuit uses the lock bit as a condition for releasing reset. if operating in external clock mode, lock remains cleared after reset. 1 pll locked 0 pll not locked
clock module mcf5213 reference manual, rev. 1.1 6-10 freescale semiconductor preliminary 6.6.2.3 low power control register (lpcr) figure 6-5. low power control register the low power divider is a 4-bit field that divides dow n the system clock (regardl ess if the reference clock or pll clock is driving the sy stem clock) by a factor of 2 n (where n is a number fr om 0 to 15 represented by the 4 bit field). the clock change takes effect with the next rising edge of the system clock 6.6.3 ppm register descriptions this subsection provides a description of the pe ripheral power management registers in the scm. 2 locs sticky indication of whether a loss-of-clock condition has occurred at any time since exiting reset in normal pll and 1:1 pll modes. locs = 0 when the system clocks are operating normally. locs = 1 when system clocks have failed due to a reference failure or pll failure. after entering stop mode with fwkup set and the pll and oscillator intentionally disabled (stpmd[1:0] = 11), the pll exits stop mode in the scm while the oscillator starts up. during this time, locs is temporar ily set regardless of locen. it is cleared once the oscillator comes up and the pll is attempting to lock. if a read of the locs flag and a loss-of-c lock condition occur simultaneously, the flag does not reflect the current loss-of-clock condition. a loss-of-clock condition can be detected only if locen = 1 or the oscillator has not yet returned from exit from stop mode with fwkup = 1. 1 loss-of-clock detected since exiting reset or oscillator not yet recovered from exit from stop mode with fwkup = 1 0 loss-of-clock not detected since exiting reset note: the locs flag is always 0 in external clock mode. 1?0 ? reserved, should be cleared. 76 5 4 32 10 field ? ? ? ? lpd3 lpd2 lpd1 lpd0 reset 0000_0000 r/w r r/w address ipsbar + 0x0000_0007 table 6-7. synsr field de scriptions (continued) bit(s) name description
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-11 preliminary 6.6.3.1 peripheral power mana gement register high (ppmrh) table 6-8. ppmrh field descriptions figure 6-6. peripheral power management register high 31 30 29 28 27 26 25 24 field ? ? ? ? ? ? ? ? reset 0000_0000 r/w r 23 22 21 20 19 18 17 16 field ? ? ? ? ? ? ? ? reset 0000_0000 r/w r 15 14 13 12 11 10 9 8 field ? ? ? ? cdcfm cdfcan cdpwm cdicoc reset 0000_0000 r/w r/w 7 6 5 4 3 2 1 0 field cdadc ? ? cdpit1 cdpit0 ? cdeport cdports reset 0000_0000 r/w r/w address ipsbar+0000_000c bit(s) name description 31?12 ? reserved, should be cleared. 11 cdcfm disable clock to the cfm (common flash module) 0) cfm module clock is enabled 1) cfm module clock is disabled 10 cdfcan disable clock to the flexcan module. 0) flexcan module clock is enabled 1) flexcan module clock is disabled 9 cdpwm disable clock to the pwm module. 0) pwm module clock is enabled 1) pwm module clock is disabled 8 cdicoc disable clock to the 16 bit timer module (icoc). 0) icoc module clock is enabled 1) icoc module clock is disabled 7 cdadc disable clock to the adc module. 0) adc module clock is enabled 1) adc module clock is disabled 6?5 ? reserved, should be cleared. 4 cdpit1 disable clock to the pit1 module. 0) pit0 module clock is enabled 1) pit1 module clock is disabled 3 cdpit0 disable clock to the pit0 module. 0) pit0 module clock is enabled 1) pit0 module clock is disabled 2 reserved ?
clock module mcf5213 reference manual, rev. 1.1 6-12 freescale semiconductor preliminary 6.6.3.2 peripheral power manage ment register low (ppmrl) 1 cdeport disable clock to the eport module. 0) eport module clock is enabled 1) eport module clock is disabled 0 cdports disable clock to the ports module. 0) ports module clock is enabled 1) ports module clock is disabled figure 6-7. peripheral power management register low 31 30 29 28 27 26 25 24 field ? ? ? ? ? ? ? ? reset 0000_0000 r/w r/w 23 22 21 20 19 18 17 16 field ? ? ? ? ? ? cdintc0 cdtmr3 reset 0000_0000 r/w r/w 15 14 13 12 11 10 9 8 field cdtmr2 cdtmr1 cdtmr0 ? ? cdqspi cdi2c ? reset 0000_0000 r/w r/w 7 6 5 4 3 2 1 0 field cduart2 cduart1 cduart0 cddma cdeim ? cdg ? reset 0000_1000 r/w r/w address base + 18 bit(s) name description 31?18 ? reserved, should be cleared. 17 cdintc0 disable clock to the intc0 module. 0) intc0 module clock is enabled 1) intc0 module clock is disabled 16 cdtmr3 disable clock to the tmr3 module. 0) tmr3 module clock is enabled 1) tmr3 module clock is disabled 15 cdtmr2 disable clock to the tmr2 module. 0) tmr2 module clock is enabled 1) tmr2 module clock is disabled 14 cdtmr1 disable clock to the tmr1 module. 0) tmr1 module clock is enabled 1) tmr1 module clock is disabled 13 cdtmr0 disable clock to the tmr0 module. 0) tmr0 module clock is enabled 1) tmr0 module clock is disabled 12?11 ? reserved, should be cleared.
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-13 preliminary 6.7 functional description this subsection provides a functiona l description of the clock module. 6.7.1 system clock modes the system clock source and pll mode (enabled/disabled) are determined during reset (see table 27-10 ). the values of clkmod[1:0] (and xt al if clkmod0 does not equal 1) are latched during reset and are of no importance after reset is negated. if clkmod1 or clkmod0 change during a reset other than power-on reset, the internal clocks may glitch as the system clock source is changed between external clock mode and pll clock mode. wh enever clkmod1 or clkmod0 is ch anged in reset, an immediate loss-of-lock condition occurs. table 6-9 shows the clockout frequency to clockin frequency relationships for the possible system clock modes. 10 cdqspi disable clock to the qspi module. 0) qspi module clock is enabled 1) qspi module clock is disabled 9 cdi2c disable clock to the i2c module. 0) i2c module clock is enabled 1) i2c module clock is disabled 8 ? reserved, should be cleared. 7 cduart2 disable clock to the uart2 module. 0) uart1 module clock is enabled 1) uart2 module clock is disabled 6 cduart1 disable clock to the uart1 module. 0) uart1 module clock is enabled 1) uart1 module clock is disabled 5 cduart0 disable clock to the uart0 module. 0) uart0 module clock is enabled 1) uart0 module clock is disabled 4 cddma disable clock to the dma module. 0) dma module clock is enabled 1) dma module clock is disabled 3 cdeim disable clock to the eim module. 0) eim module clock is enabled 1) eim module clock is disabled 2 ? reserved, should be cleared. 1 cdg disable clock to the global off-platform modules. 0) global off-platform module clocks are enabled 1) global off-platform module clocks are disabled 0 ? reserved, should be cleared.
clock module mcf5213 reference manual, rev. 1.1 6-14 freescale semiconductor preliminary the external clock is divided by two in ternally to produce the system clocks. 6.7.2 clock operation during reset in external clock mode, the system is static and does not recognize reset until a clock is generated from the reference clock source select ed by the clkmod pins (see section 6.5.4, ?clkmod[1:0] ). in pll mode, the pll operates in se lf-clocked mode (scm) during rese t until the input reference clock to the pll begins operating within the limits given in the electrical specifications. if a pll failure causes a reset, the system enters reset using the reference clock. then the system clock source changes to the pll operating in scm. if scm is not functiona l, the system becomes static. alternately, if the locen bit in syncr is cleared when the pll fails, the system becomes static. if external reset is asserted, the sy stem cannot enter reset unless the pll is capable of operating in scm. 6.7.3 system clock generation in normal pll clock mode, the defau lt system frequency is two times th e reference freque ncy after reset. the rfd[2:0] and mfd[2:0] bits in the syncr select the frequency multiplier. th e lpd[3:0] field in the lpcr register provides additional settings for divi ding down the system clock (including when the pll is disabled) for low power operation. when programming the pll, do not ex ceed the maximum system clock fr equency listed in the electrical specifications. use this procedure to accommodate the frequency overshoot that occurs when the mfd bits are changed: 1. determine the appropriate value for the mfd and rfd fields in the syncr. the amount of jitter in the system clocks can be minimized by select ing the maximum mfd factor that can be paired with an rfd factor to provi de the required frequency. 2. write a value of rfd (from step 1) + 1 to the rfd field of the syncr. 3. write the mfd value from step 1 to the syncr. 4. monitor the lock flag in synsr. when the pl l achieves lock, write the rfd value from step 1 to the rfd field of the syncr. this changes the system clocks frequency to the required frequency. note keep the maximum system clock fre quency below the limit given in the electrical characteristics. table 6-9. clock out and clock in relationships system clock mode pll options 1 1 f ref = input reference frequency f sys = clkout frequency mfd ranges from 0 to 7. rfd ranges from 0 to 7. normal pll clock mode f sys = f ref 2(mfd + 2)/2 rfd 1:1 pll clock mode f sys = f ref external clock mode f sys = f ref
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-15 preliminary 6.7.4 pll operation in pll mode, the pll synthesizes th e system clocks. the pll can multip ly the reference clock frequency by 4x to 18x, provided that the system clock frequenc y remains within the range listed in electrical specifications. for example, if the reference frequenc y is 2 mhz, the pll can synt hesize frequencies of 8 mhz to 36 mhz. in additi on, the rfd can reduce the system frequenc y by dividing the output of the pll. the rfd is not in the feedback loop of the pll, so changing the rfd divisor does not affect pll operation. figure 6-8 shows the external support circuitry for the crys tal oscillator with example component values. actual component values de pend on crystal specifications. the following subsections describe each major block of the pll. refer to figure 6-8 to see how these functional sub-blocks interact. figure 6-8. crystal oscillator example 6.7.4.1 phase and fre quency detector (pfd) the pfd is a dual-latch phase-freque ncy detector. it compares both the phase and frequency of the reference and feedback clocks. the reference clock come s from either the crystal oscillator or an external clock source. the feedback clock comes fr om one of the following: ? clkout in 1:1 pll mode ? vco output divided by two if clkou t is disabled in 1:1 pll mode ? vco output divided by the mfd in normal pll mode when the frequency of the feedback clock equals the frequency of the reference clock, the pll is frequency-locked. if the falling edge of the feedback clock lags the fa lling edge of the reference clock, the pfd pulses the up signal. if the falling edge of the f eedback clock leads the fall ing edge of the reference clock, the pfd pulses the down signal . the width of these pulses relati ve to the reference clock depends on how much the two clocks lead or lag each other. once phase lock is achieved, the pfd continues to pulse the up and down signals for very short duratio ns during each reference clock cycle. these short pulses continually update the pll and prevent th e frequency drift phenomenon known as dead-banding. v ss v sssyn extal xtal rs rf c1 c2 on-chip 8-mhz crystal configurati o c1 = c2 = 16 pf rf = 1 m ? rs = 470 ?
clock module mcf5213 reference manual, rev. 1.1 6-16 freescale semiconductor preliminary 6.7.4.2 charge pump/loop filter in 1:1 pll mode, the charge pump us es a fixed current. in normal mo de the current magnitude of the charge pump varies with the mfd as shown in table 6-10 . the up and down signals from th e pfd control whether the charge pump applies or removes charge, respectively, from the l oop filter. the filter is integrated on the chip. 6.7.4.3 voltage control output (vco) the voltage across the loop filter controls the frequency of the vc o output. the frequency-to-voltage relationship (vco gain) is positive, and the output frequency is four times the target system frequency. 6.7.4.4 multiplication factor divider (mfd) when the pll is not in 1:1 pll mode, the mfd divide s the output of the vco and feeds it back to the pfd. the pfd controls the vco freque ncy via the charge pump and loop filter such that the reference and feedback clocks have the same fr equency and phase. thus, the frequenc y of the input to the mfd, which is also the output of the vco, is the reference frequency multiplied by the same amount that the mfd divides by. for example, if the mfd divides the vc o frequency by six, the pll is frequency locked when the vco frequency is six times the reference frequenc y. the presence of the mfd in the loop allows the pll to perform frequency mu ltiplication, or synthesis. in 1:1 pll mode, the mfd is bypassed, and th e effective multiplicat ion factor is one. 6.7.4.5 pll lock detection the lock detect logic monitors th e reference frequency a nd the pll feedback frequency to determine when frequency lock is achieved. phase lo ck is inferred by the frequency re lationship, but is not guaranteed. the lock flag in the synsr reflects the pll lock stat us. a sticky lock flag, lo cks, is also provided. the lock detect function uses two counters: one is cl ocked by the reference, a nd the other is clocked by the pll feedback. when the reference counter has counted n cycles, its c ount is compared to that of the feedback counter. if the feedback c ounter has also counted n cycles, the process is repeated for n + k counts. then, if the tw o counters still match, the lock criteria is relaxed by 1/2 and the system is notified that the pll has achieved frequency lock. after lock is detected, the lock circuit continues to monitor the reference and feedback frequencies using the alternate count and compare pro cess. if the counters do not match at any comparison time, then the lock flag is cleared to indi cate that the pll has lost lock. at this point, the lock criteria is tightened and the lock detect process is repeated. the alternate count sequences preven t false lock detects due to freque ncy aliasing while the pll tries to lock. alternating between tight and relaxed lock criteria pr events the lock dete ct function from randomly toggling between locked and non-locked status due to phase sensitivities. figure 6-9 shows the sequence for detecting locked and non-locked conditions. table 6-10. charge pump current and mfd in normal mode operation charge pump current mfd 1x 0 mfd < 2 2x 2 mfd < 6 4x 6 mfd
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-17 preliminary in external clock mode, the pll is disabled and cannot lock. figure 6-9. lock detect sequence 6.7.4.6 pll loss of lock conditions once the pll acquires lock after reset, the lock and locks flags are set. if the mfd is changed, or if an unexpected loss of lock condition occu rs, the lock and lock s flags are negated. while the pll is in the non-locked condition, the system clocks continue to be sourced from th e pll as the pll attempts to relock. consequently, during the relocking process, the system clocks fre quency is not well defined and may exceed the maximum system frequency, vi olating the system cloc k timing specifications. however, once the pll has relocked, the lock flag is set. the locks flag remain s cleared if the loss of lock was unexpected. the locks flag is set when the loss of lock is caused by changing mfd. if the pll is intentionally disabled duri ng stop mode, then after exit from stop mode, the locks flag reflects the value prior to entering stop mode once lock is regained. 6.7.4.7 pll loss of lock reset if the lolre bit in the sy ncr is set, a loss of lock condition asserts reset. re set reinitializes the lock and locks flags. therefore, softwa re must read the lol bit in th e reset status register (rsr) to determine if a loss of lock caused the reset. see section 29.4.2, ?reset stat us register (rsr) .? to exit reset in pll mode, the reference must be present, and the pll must achieve lock. in external clock mode, the pll ca nnot lock. therefore, a loss of lo ck condition cannot occur, and the lolre bit has no effect. count n reference cycles and compare number of feedback cycles elapsed start with tight lock criteria reference count feedback count loss of lock detected set tight lock criteria and notify system of loss of lock condition count n + k reference cycles and compare number of feedback cycles elapsed lock detected. set relaxed lock condition and notify system of lock condition reference count feedback count reference count = feedback count = n in same count/compare sequence reference count = feedback count = n + k in same count/compare sequence
clock module mcf5213 reference manual, rev. 1.1 6-18 freescale semiconductor preliminary 6.7.4.8 loss of clock detection the locen bit in the syncr enables the loss of clock detection circui t to monitor the input clocks to the phase and frequency detector ( pfd). when either the reference or feedback clock frequency falls below the minimum frequency, the loss of clock ci rcuit sets the sticky locs flag in the synsr. note in external clock mode, the loss of clock circuit is disabled. 6.7.4.9 loss of clock reset the clock module can assert a reset when a loss of cl ock or loss of lock occurs. when a loss-of-clock condition is recognized, reset is asse rted if the locre bit in syncr is set. the locs bit in synsr is cleared after reset. therefore, the loc bit must be read in rsr to de termine that a loss of clock condition occurred. locre has no effect in external clock mode. to exit reset in pll mode, the reference must be present, and the pll must acquire lock. reset initializes the clock m odule registers to a known star tup state as described in section 6.6, ?memory map and registers .? 6.7.4.10 alternate clock selection depending on which clock source fails, the loss-of-clock circuit switches the system clocks source to the remaining operational clock. the alternat e clock source generates the system clocks until reset is asserted. as table 6-11 shows, if the reference fails, the pll goes out of lock and into self-clocked mode (scm). the pll remains in scm until the ne xt reset. when the pll is operating in scm, the system frequency depends on the value in the rfd fi eld. the scm system frequency stat ed in electrical specifications assumes that the rf d has been programme d to binary 000. if the loss-of-clock c ondition is due to pll failure, the pll reference becomes th e system clocks source until the next reset, even if the pll regains and relocks. a special loss-of-clock condition occurs when both th e reference and the pll fa il. the failures may be simultaneous, or the pll may fail first. in either case, the refere nce clock failure take s priority and the pll attempts to operate in scm. if successful, the pll remains in scm until the next reset. if the pll cannot operate in scm, the system re mains static until the next reset. both the reference and the pll must be functioning properly to exit reset. 6.7.4.11 loss of clock in stop mode table 6-12 shows the resulting actions for a loss of clock in stop mode wh en the device is being clocked by the various clocking methods. table 6-11. loss of clock summary clock mode system clock source before failure reference failure alternate clock selected by loc circuit 1 until reset 1 the loc circuit monitors the reference and feedback inputs to the pfd. see figure 6-8 . pll failure alternate clock selected by loc circuit until reset pll pll pll self-clocked mode pll reference external external clock none na
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-19 preliminary table 6-12. stop mode operation (sheet 1 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments ext x x x x x x ? ? ext 0 0 0 lose reference clock stuck ? ? ? nrm 0 0 0 off off 0 lose lock, f.b. clock, reference clock regain nrm ?lk 1 ?lc no regain stuck ? ? ? nrm x 0 0 off off 1 lose lock, f.b. clock, reference clock regain clocks, but don?t regain lock scm?> unstable nrm 0?>?lk 0?>1 1?>?l c block locs and locks until clock and lock respectively regain; enter scm regardless of locen bit until reference regained no reference clock regain scm?> 0?> 0?> 1?> block locs and locks until clock and lock respectively regain; enter scm regardless of locen bit no f.b. clock regain stuck ? ? ? nrm 0 0 0 off on 0 lose lock regain nrm ?lk 1 ?lc block locks from being cleared lose reference clock or no lock regain stuck ? ? ? lose reference clock, regain nrm ?lk 1 ?lc block locks from being cleared nrm 0 0 0 off on 1 lose lock no lock regain unstable nrm 0?>?lk 0?>1 ?lc block locks until lock regained lose reference clock or no f.b. clock regain stuck ? ? ? lose reference clock, regain unstable nrm 0?>?lk 0?>1 ?lc locs not set because locen = 0
clock module mcf5213 reference manual, rev. 1.1 6-20 freescale semiconductor preliminary nrm 0 0 0 on on 0 ? ? nrm ?lk 1 ?lc lose lock or clock stuck ? ? ? lose lock, regain nrm 0 1 ?lc lose clock and lock, regain nrm 0 1 ?lc locs not set because locen = 0 nrm 0 0 0 on on 1 ? ? nrm ?lk 1 ?lc lose lock unstable nrm 00?>1?lc lose lock, regain nrm 0 1 ?lc lose clock stuck ? ? ? lose clock, regain without lock unstable nrm 00?>1?lc lose clock, regain with lock nrm 0 1 ?lc nrm x x 1 off x x lose lock, f.b. clock, reference clock reset reset ? ? ? reset immediately nrm 0 0 1 on on x ? ? nrm ?lk 1 ?lc lose lock or clock reset ? ? ? reset immediately nrm 1 0 0 off off 0 lose lock, f.b. clock, reference clock regain nrm ?lk 1 ?lc ref not entered during stop; scm entered during stop only during oscillator startup no regain stuck ? ? ? nrm 1 0 0 off on 0 lose lock, f.b. clock regain nrm ?lk 1 ?lc ref mode not entered during stop no f.b. clock or lock regain stuck ? ? ? lose reference clock scm 0 0 1 wakeup without lock table 6-12. stop mode operation (sheet 2 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-21 preliminary nrm 1 0 0 off on 1 lose lock, f.b. clock regain f.b. clock unstable nrm 0?>?lk 0?>1 ?lc ref mode not entered during stop no f.b. clock regain stuck ? ? ? lose reference clock scm 0 0 1 wakeup without lock nrm 1 0 0 on on 0 ? ? nrm ?lk 1 ?lc lose reference clock scm 0 0 1 wakeup without lock lose f.b. clock ref 0 x 1 wakeup without lock lose lock stuck ? ? ? lose lock, regain nrm 0 1 ?lc nrm 1 0 0 on on 1 ? ? nrm ?lk 1 ?lc lose reference clock scm 0 0 1 wakeup without lock lose f.b. clock ref 0 x 1 wakeup without lock lose lock unstable nrm 00?>1?lc nrm 1 0 1 on on x ? ? nrm ?lk 1 ?lc lose lock or clock reset ? ? ? reset immediately nrm 1 1 x off x x lose lock, f.b. clock, reference clock reset reset ? ? ? reset immediately nrm 1 1 0 on on 0 ? ? nrm ?lk 1 ?lc lose clock reset ? ? ? reset immediately lose lock stuck ? ? ? lose lock, regain nrm 0 1 ?lc table 6-12. stop mode operation (sheet 3 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments
clock module mcf5213 reference manual, rev. 1.1 6-22 freescale semiconductor preliminary nrm 1 1 0 on on 1 ? ? nrm ?lk 1 ?lc lose clock reset ? ? ? reset immediately lose lock unstable nrm 00?>1?lc lose lock, regain nrm 0 1 ?lc nrm 1 1 1 on on x ? ? nrm ?lk 1 ?lc lose clock or lock reset ? ? ? reset immediately ref 100xxx ? ? ref 0 x 1 lose reference clock stuck ? ? ? scm 100offx0 pll disabled regain scm scm 0 0 1 wakeup without lock scm 100offx1 pll disabled regain scm scm 0 0 1 scm 1 0 0 on on 0 ? ? scm 0 0 1 wakeup without lock lose reference clock scm table 6-12. stop mode operation (sheet 4 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments
clock module mcf5213 reference manual, rev. 1.1 freescale semiconductor 6-23 preliminary scm 1 0 0 on on 1 ? ? scm 0 0 1 lose reference clock scm note: pll = pll enabled during stop mode. pll = on when stpmd[1:0] = 00 or 01 osc = oscillator enabled during stop mode. oscill ator is on when stpm d[1:0] = 00, 01, or 10 modes nrm = normal pll crystal clock reference or normal pll external reference or pll 1:1 mode. during pll 1:1 or normal external reference mode, the oscillator is never enabled. therefore, during these modes, refer to the osc = on case regardless of stpmd values. ext = external clock mode ref = pll reference mode due to losing pll clock or lock from nrm mode scm = pll self-clocked mode due to lo sing reference clock from nrm mode reset = immediate reset locks ?lk -= expecting previous value of locks before entering stop 0?>?lk = current value is 0 until lock is regained which then will be the previous value before entering stop 0?> = current value is 0 until lock is regained but lock is never expected to regain locs ?lc = expecting previous value of locs before entering stop 1?>?lc = current value is 1 until clock is regained which then will be the previous value before entering stop 1?> = current value is 1 until clock is regained but clk is never expected to regain table 6-12. stop mode operation (sheet 5 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments
clock module mcf5213 reference manual, rev. 1.1 6-24 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 7-1 preliminary chapter 7 power management 7.1 introduction this chapter explains the low- power operation of the device. 7.1.1 features the following features support low-power operation. ? four modes of operation: run, wait, doze, and stop ? ability to shut down most peripherals independently ? ability to shut down clocks to most peripherals independently ? ability to run the device in low-frequency limp mode ? ability to shut down the external fb_clk pin 7.2 memory map/register definition the power management programming model consists of registers fr om both the scm and ccm memory space, as shown below: table 7-1. power management memory map address register access reset value section/page supervisor access only registers 1 1 user access to supervisor only address locations have no effec t and result in a cycl e termination transfer error 0xfc04_0013 wakup control register (wcr) r/w 0x00 7.2.1/7-2 0xfc04_002c peripheral power management set register 0 (ppmsr0) w 0x00 7.2.2/7-3 0xfc04_002d peripheral power management clear register 0 (ppmcr0) w 0x00 7.2.3/7-4 0xfc04_002e peripheral power management set register 1 (ppmsr1) w 0x00 7.2.2/7-3 0xfc04_002f peripheral power management clear register 1 (ppmcr1) w 0x00 7.2.3/7-4 0xfc04_0030 peripheral power management high register 0 (ppmhr0) r/w 0x0000_0000 7.2.4/7-4 0xfc04_0034 peripheral power management low register 0 (ppmlr0) r/w 0x0000_0000 7.2.4/7-4 0xfc04_0038 peripheral power management high register 1 (ppmhr1) r/w 0x0000_0000 7.2.4/7-4 0xfc0a_0007 low-power control register (lpcr) r/w 0x00 7.2.5/7-6 0xfc0a_0010 miscellaneous control register (misccr) r/w see section 7.2.6/7-7
power management mcf5213 reference manual, rev. 1.1 7-2 freescale semiconductor preliminary 7.2.1 wake-up control register implementation of low-power stop m ode and exit from a low-power mode via an interrupt require communication between the core and logic associated wi th the interrupt controller. the wcr is an 8-bit register that enables entry into low-power stop mode, and includes the setting of th e interrupt level needed to exit a low-power mode. note the setting of the low-power mode se lect field, lpcr[lpmd], determines which low-power mode the device enters when a stop instruction is issued. if this field is set to enter stop mode, then the wcr[enbwcr] bit must also be set. the following sequence of operations is genera lly needed to enable this functionality. 1. the wcr register is programmed, setting the enbw cr bit and the desired in terrupt priority level. 2. at the appropriate time, the processor exec utes the privileged stop instruction. once the processor has stopped execution, it asserts a specif ic processor status (p st) encoding. issuing the stop instruction when the wcr[enbwcr] bit is set causes the scm to enter stop mode. 3. the entry into a low-power mode is processe d by the low-power mode control logic, and the appropriate clocks (usually those related to the high-speed processo r core) are disabled. 4. after entering the low-power mode, the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests. th e device waits for an event to generate an interrupt request with a priori ty level greater than the va lue programmed in wcr[prilvl]. 5. once an appropriately high interrupt request leve l arrives, the interrupt controller signals its presence, and the scm responds by asserti ng the request to exit low-power mode. 6. the low-power mode control logi c senses the request si gnal and re-enables th e appropriate clocks. 7. with the processor clocks enabled, the co re processes the pending interrupt request. address: 0x13 (wcr) access: supervisor read/write 7 6543210 r enbwcr 0 0 0 0 prilvl w reset: 0 0 0 0 0 0 0 0 figure 7-1. wake-up control register (wcr) table 7-2. wcr field descriptions field description 7 enbwcr enable wake-up control. 0 wake-up control is disabled 1 wake-up control is enabled
power management mcf5213 reference manual, rev. 1.1 freescale semiconductor 7-3 preliminary 7.2.2 peripheral power management set registers (ppmsr0 & ppmsr1) the ppmsr registers provide a simp le mechanism to set a given bit in the ppmhr & ppmlr registers to disable the clock for a given pe ripheral module without the need to perform a read-modify write on the ppmr. the data value on a register write causes th e corresponding bit in the ppm{h,l}r to be set. the samcd bit provides a global set function forcing the entire contents of the ppmr to be set, disabling all peripheral module clocks. reads of th ese registers return all zeroes. 6?3 reserved, should be cleared. 2?0 prilvl exit low-power mode interrupt priority level. this field defi nes the interrupt priority level needed to exit the low-power mode. address: 0x2c (ppmsr0) 0x2e (ppmsr1) access: supervisor write-only 7 6543210 r 0 0 0 0 0 0 0 0 w samcd smcd reset: 0 0 0 0 0 0 0 0 figure 7-2. peipheral power management set registers (ppmsr n ) table 7-3. ppmsr n field descriptions field description 7 reserved, should be cleared. 6 samcd set all module clock disables. 0 set only those bits specified in the smcd field 1 set all bits in ppmrh and ppmrl, disabling all peripheral clocks 5?0 smcd set module clock disable. set the corresponding bit in ppmr{h,l}, disabling the peripheral clock. table 7-2. wcr field desc riptions (continued) field description prilvl interrupt level needed to exit low-power mode 000 any interrupt request exits low-power mode 001 interrupt request levels [2-7] exit low-power mode 010 interrupt request levels [3-7] exit low-power mode 011 interrupt request levels [4-7] exit low-power mode 100 interrupt request levels [5-7] exit low-power mode 101 interrupt request levels [6-7] exit low-power mode 11 x interrupt request level [7] exits low-power mode
power management mcf5213 reference manual, rev. 1.1 7-4 freescale semiconductor preliminary 7.2.3 peripheral power manageme nt clear registers (ppmcr0 & ppmcr1) the ppmcr registers provide a simple mechanism to clear a give n bit in the ppmhr & ppmlr registers to enable the clock for a given pe ripheral module without the need to perform a read-modify write on the ppmr. the data value on a register write causes th e corresponding bit in the ppm{h,l}r to be clear. a value of 64 to 127 provides a global clear function forc ing the entire contents of the ppmr to be clear, enabling all peripheral module clocks. read s of these registers return all zeroes. 7.2.4 peripheral power management registers (ppmhr0 & ppmlr0) the ppmr registers provide a bit map for controlling the generation of the peripheral clocks for each decoded address space. recall each peripheral module is mapped into 16 kbyte slots within the memory map. the ppmr registers provi de a unique control bit for each of thes e address spaces th at defines whether the module clock for the given space is enabled or disabled. since the operation of the crossbar switch and the system control m odule (scm) are fundamental to the operation of the device, the clocks fo r these modules cannot be disabled. the individual bits of the ppmr can be modified using a read-modify-write to this register directly or indirectly through writes to the ppmsr and ppm cr registers to set/clear individual bits. address: 0x2d (ppmcr0) 0x2f (ppmcr1) access: supervisor write-only 7 6543210 r 0 0 0 0 0 0 0 0 w camcd cmcd reset: 0 0 0 0 0 0 0 0 figure 7-3. peipheral power management clear registers (ppmcr n ) table 7-4. ppmcr n field descriptions field description 7 reserved, should be cleared. 6 camcd clear all module clock disables. 0 clear only those bits specified in the cmcd field 1 clear all bits in ppmrh and ppmrl, enabling all peripheral clocks 5?0 cmcd clear module clock disable. clear the corresponding bit in ppmr{h,l}, enabling the peripheral clock.
power management mcf5213 reference manual, rev. 1.1 freescale semiconductor 7-5 preliminary address: 0x30 (ppmhr0) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset00000000000000 0 0 15141312111098765432 1 0 reset00000000000000 0 0 figure 7-4. peipheral power management high register (ppmhr) address: 0x34 (ppmlr0) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset00000000000000 0 0 15141312111098765432 1 0 reset00000000000000 0 0 figure 7-5. peipheral power management low registers (ppmlr0) table 7-5. ppm register assignments ipsbar peripheral ? off platform plobal space ppmr[1] ? reserved ppmr[2] 0x0080 eim ppmr[3] 0x0100 dma ppmr[4] 0x0200 uart0 ppmr[5] 0x0240 uart1 ppmr[6] 0x0280 uart2 ppmr[7] 0x02c0 reserved ppmr[8] 0x0300 i 2 c ppmr[9] 0x0340 qspi ppmr[10] 0x-380 reserved ppmr[11] 0x03c0 reserved ppmr[12] 0x0400 dma timer0 ppmr[13] 0x0440 dma timer1 ppmr[14] 0x0480 dma timer2 ppmr[15] 0x04c0 dma timer3 ppmr[16] 0x0c00 intc0 ppmr[17] 0x0d00 reserved ppmr[18] 0x0e00 reserved ppmr[19]
power management mcf5213 reference manual, rev. 1.1 7-6 freescale semiconductor preliminary 7.2.5 low-power control register (lpcr) the lpcr register controls chip operation and module operation during low-power modes. 0xfc05_0000 reserved ppmr[20] 0x1000 reserved ppmr[21] ? reserved ppmr[22] ? reserved ppmr[23] ? reserved ppmr[24] ? reserved ppmr[25] ? reserved ppmr[26] ? reserved ppmr[27] ? reserved ppmr[28] ? reserved ppmr[29] ? reserved ppmr[30] ? reserved ppmr[31] 0x0010_0000 ? 0xfc0f_ffff off-platform slaves ppmr[32-47] 0xfc10_0000 ? 0xffff-ffff 63 mbyte off-platform global space ppmf[1] address: 0x07 (lpcr) access: supervisor read/write 7 6543210 r lpmd fwkup stpmd 0 0 0 w reset: 0 0 0 0 0 0 0 0 figure 7-6. low-power control register (lpcr) table 7-5. ppm register assignments (continued) ipsbar peripheral
power management mcf5213 reference manual, rev. 1.1 freescale semiconductor 7-7 preliminary 7.2.6 miscellaneous cont rol register (misccr) the misccr provides clock source selecti on and configuration for internal clocks. table 7-6. lpcr field descriptions field description 7?6 lpmd low-power mode select. used to select the low-power mode the chip enters once the coldfire core executes the stop instruction. these bits must be written prior to instru ction execution for them to take effect. the lpmd bits are readable and writable in all modes. below illustrates the four different power modes that can be configured with the lpmd bit field. 00 run 01 doze 10 wait 11 stop note: if lpcr[lpmd] is cleared, then the device will stop executing code upon issue of a stop instruction. however, no clocks will be disabled. 5 fwkup fast wake-up. determines whether t he system clocks are enabled upon wake-u p from stop mode. this bit must be written before execution of the stop instruction for it to take effect. 0 system clocks enabled only when pll is locked or operating normally. 1 system clocks enabled upon wake-up from stop mode, regardless of pll lock status. note: if fwkup is set before entering stop mode, it should not be cleared upon wake-up from stop mode until after the pll has actually acquired lock. lock status may be obtained by reading the misccr[plllock] bit. also note that fwkup is not effective in limp mode, since the pll never locks in this mode. the system clocks are always enabled upon wake-up from stop mode, regardless of the value of fwkup. 4?3 stpmd fb_clk stop mode bits. controls the operation of the clocks, pll, and oscillator in stop mode as shown below. 2?0 reserved, should be cleared. address: 0x10 (misccr) access: supervisor read/write 1514131211109876543 2 1 0 r 0 0 pll lock limp 0 0000000 lpddiv w reset 001 see note 000000000 0 0 0 note: reset value depends upon chosen reset configuration (rcon[rlimp]). figure 7-7. miscellaneous control register (misccr) stpmd system clocks fb_clk pll oschillator 00 disabled enabled enabled enabled 01 disabled disabled enabled enabled 10 disabled disabled disabled enabled 11 disabled disabled disabled disabled
power management mcf5213 reference manual, rev. 1.1 7-8 freescale semiconductor preliminary 7.3 functional description the functions and characteristics of the low-power modes, and how each module is affected by, or affects these modes are discussed in this section. 7.3.1 peripheral shut down all peripherals, except for the scm and crossbar switch, may have their input clocks individually removed by software in order to re duce power consumption. see section 7.2.4, ?peripheral power management registers (ppmhr0 & ppmlr0),? for more information. a peripheral may be disabled at any time and will remain disabled during a ny low-power mode of operation. 7.3.2 limp mode the device may also be booted into a low-frequency limp mode, in which the pll is bypassed and the device runs from a factor of the input clock (extal). in this mode, extal feeds a 5-bit programmable counter that divides the input clock by 2 n , where n is the value of the programmable counter field, misccr[lpdiv]. the programmed value of the divider may be changed without glitches or otherwise negative affects to the system. while in this mode, the pll is placed in bypass mode to reduce overall system power consumption. when switching from limp mode to normal functional mode, the user must wait for the pll to lock before continuing with code execution. limp mode may also be ente red and exited from by writi ng to the misccr[limp] bit. while in this mode a 2:1 ratio is maintained between the core and the primary bus clock. 7.3.3 low-power modes the system enters a low-power mode by executing a stop instruction. which mode the device actually enters (either stop, wait, or doze) depends on what the user programs into lp cr[lpmd]. entry into any table 7-7. misccr field descriptions field description 15?14 reserved, should be cleared. 13 plllock pll lock status. 0 pll is not locked. 1 pll is locked. 12 limp limp mode enable. selects between the pll and the low-powe r clock divider as the source of all system clocks. 0 normal operation; pll drives all internal clocks. 1 limp mode; low-power clock divider drivers internal clocks. 11?4 reserved, should be cleared. 3?0 lpddiv low power divider. specifies the limp mode divide value used to produce the clock for the coldfire core, bus, and other system clocks. this field is used onl y when limp is set, and ignored otherwise. limp mode clock = oscillator clock / 2 lpdiv
power management mcf5213 reference manual, rev. 1.1 freescale semiconductor 7-9 preliminary of these modes idles the cpu with no cycles active, powers down the syst em, and stops all internal clocks appropriately. during stop mode, the system clock is stopped low. a wake-up event is required to exit a low-power mode and return to ru n mode. wake-up events consist of any of these conditions: ? any type of reset ? any valid, enabled interrupt request exiting from low power mode via an interrupt re quest requires: ? an interrupt request whose prio rity is higher than the value programmed in the wcr[prilvl]. ? an interrupt request whose priori ty is higher than the value programmed in the interrupt priority mask (i) field of the core?s status register. ? an interrupt request from a source which is not masked in the inte rrupt controller?s interrupt mask register. ? an interrupt request which has been enable d at the module of the interrupt?s origin. 7.3.3.1 run mode run mode is the normal system opera ting mode. current consumption in th is mode is related directly to the system clock frequency. 7.3.3.2 wait mode wait mode is intended to be used to stop only th e cpu and memory clocks until a wake-up event is detected. in this mode, peripherals may be programme d to continue ope rating and can generate interrupts, which cause the cpu to exit from wait mode. 7.3.3.3 doze mode doze mode affects the cpu in the same manner as wait mode, except that each peripheral defines individual operational characterist ics in doze mode. peripherals which continue to run and have the capability of producing interrupts may cause the cpu to exit the doze mode and return to run mode. peripherals which are stopped will re start operation on exit fr om doze mode as define d for each peripheral. 7.3.3.4 stop mode stop mode affects the cpu in the same manner as the wa it and doze modes, except that all clocks to the system are stopped and the peripherals cease operation. stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated. when exiting stop mode, most peripherals retain their pre-stop st atus and resume operation. the following subsections specify the operation of each module whil e in and when exiting low-power modes.
power management mcf5213 reference manual, rev. 1.1 7-10 freescale semiconductor preliminary 7.3.4 peripheral behavior in low-power modes 7.3.4.1 coldfire core the coldfire core is disabled duri ng any low-power mode. no recovery time is required when exiting any low-power mode. 7.3.4.2 static random-access memory (sram) sram is disabled du ring any low-power mode. no recovery time is required when exiting any low-power mode. 7.3.4.3 clock module in wait and doze modes, the clocks to the cpu and sram will be stoppe d and the system clocks to the peripherals are enabled. each module may disable the module clocks locally at the module level. in stop mode, all clocks to the system will be stopped. during stop mode, there are se veral options for enabling/di sabling the pll an d/or crystal oscillator (osc); each of these options requires a co mpromise between wake-up recovery time and stop mode power. the pll may be disabled during stop m ode. a wake-up tim e of up to 200 s is required for the pll to re-lock. the osc may also be disabled during stop mode. the time required for the osc to restart is dependent upon the startup time of the crysta l used. power consumption can be reduced in stop mode by disabling either or both of these functi ons via the syncr[stmpd] bits. the external fb_clk signal may be enabled during low-power stop (if the pll is still enabled or bypassed) to support systems using th is signal as the clock source. the system clocks may be enabled during wake-up fr om stop mode without waiting for the pll to lock. this eliminates the wake-u p recovery time, but at the risk of se nding a potentially unstable clock to the system. it is recomme nded, if this option is used, th at the pll frequency divider is set so that the targeted system frequency is no mo re than half the maximum allowed. this will allow for any frequency overshoot of the pll while still keeping the system cloc k within specification. in external clock mode, there are no wait times for the osc startup or pll lock. the external fb_clk output pin may be disabled in the low state to lower power consumption via the syncr[disclk] bit. the extern al fb_clk pin function is enabled by default at reset. 7.3.4.4 chip configuration module the chip configuration module is una ffected by entry into a low-power mode. if low- power mode is exited by a reset, chip configuration may be executed if configured to do so. 7.3.4.5 reset controller a power-on reset (por) will alwa ys cause a chip reset and ex it from any low-power mode.
power management mcf5213 reference manual, rev. 1.1 freescale semiconductor 7-11 preliminary in wait and doze modes, a sserting the external rsti pin for at least four clocks will cause an external reset that will reset the chip a nd exit any low-power modes. in stop mode, the rsti pin synchronization is disabled and asserting the external rsti pin will asynchronously generate an internal reset and exit any low-power modes. regi sters will lose current values and must be reconfigured from reset state if needed. if the phase lock loop (pll) in the clock module is active and if the lolre bit in the s ynthesizer control register are set, then any loss-of-lock will reset the device and exit any low-power modes. if the core or on-chip watchdog timer is still enabled duri ng wait or doze modes, then a watchdog timer timeout may generate a reset to exit these low-power modes. when the cpu is inactive, a software reset ca nnot be generated to exit any low-power mode. 7.3.4.6 system control module (scm) the scm?s core watchdog timer can bring the device out of all low-power modes except stop mode. in stop mode all clocks stop, and the core watchdog timer does not operate. when enabled, the core watchdog can bring the device out of low-power mode in one of two ways. depending on the setting of the cw cr[cwri] field, a core watchdog t imeout may cause a reset of the device. other settings of the cwri field may enable a co re watchdog interrupt and upon a watchdog timeout, this interrupt can bring the device out of low-power mode. this system setup must meet the conditions specified in section 7.3.3, ?low-power modes ,? for the core watchdog interrupt to bring the part out of low-power mode. 7.3.4.7 gpio ports the gpio ports are unaffected by entr y into a low-power mode . these pins may impact low-power current draw if they are configured as out puts and are sourcing current to an ex ternal load. if low-power mode is exited by a reset, the state of th e i/o pins will revert to th eir default direction settings. 7.3.4.8 interrupt controllers (intc0) the interrupt controller is not affe cted by any of the low-power modes. all logic between the input sources and generating the interrupt to the pr ocessor will be combinational to allo w the ability to wake up the core during low-power stop mode when all system clocks are stopped. an interrupt request will cause the cp u to exit a low-power mode only if that interrupt?s priority level is at or above the level programmed in th e interrupt priority mask field of the cpu?s status register (sr) and above the level programmed in the wc r[prilvl]. the interrupt must also be enabled in the interrupt controller?s interrupt mask register as well as at the module from which th e interrupt request would originate. 7.3.4.9 edge port in wait and doze modes, the edge por t continues to operate normally and may be configured to generate interrupts (either an edge transition or low level on an external pin) to exit the low-power modes.
power management mcf5213 reference manual, rev. 1.1 7-12 freescale semiconductor preliminary in stop mode, there is no system cl ock available to perform the edge detect function. thus, only the level detect logic is active (if configured) to allow any lo w level on the external inte rrupt pin to generate an interrupt (if enabled) to exit the stop mode. 7.3.4.10 dma controller in wait and doze modes, the dma cont roller is capable of bringing th e device out of a low-power mode by generating an interrupt either upon completion of a transfer or upon an error condition. the completion of transfer interrupt is generated when dma interrupts are enab led by the setting of a dma_intr[int n ] bit, and an interrupt is generated when the tcd n [done] bit is set. the interrupt upon error condition is generated when the dma_eeir[eei n ] bit is set, and an interrupt is generated when any of the dma_esr bits becomes set. the dma controller is stopped in st op mode and thus cannot cause an exit from this low-power mode. 7.3.4.11 on-chip watchdog timer in stop mode (or in wait/doze mode, if so program med), the watchdog ceases operation and freezes at the current value. when exiting these modes, the watchdog resumes operation from the stopped value. it is the responsibility of software to avoid erroneous operation. when not stopped, the watchdog may generate a reset to exit the low-power modes. 7.3.4.12 programmable interrupt time rs (pit0, pit1, pit2 and pit3) in stop mode (or in doze mode, if so programmed), the programmabl e interrupt timer (pit) ceases operation, and freezes at the current value. when exiting these modes, the pit resumes op eration from the stopped value. it is the responsibility of software to avoid erroneous operation. when not stopped, the pit may generate an interrupt to exit the low-power modes. 7.3.4.13 dma timers (dtim0?dtim3) in wait and doze modes, the dma ti mers may generate an interrupt to exit a low-power mode. this interrupt can be generated when the dma timer is in either input capture mode or reference compare mode. in input capture mode, where the capture enable (ce) field of the timer mode register (dtmr) has a non-zero value and the dma enable (dmaen) bit of the dma timer ex tended mode register (dtxmr) is cleared, an interrupt is issued upon a captured input. in reference compare mode, where the output reference request interrupt enable (orri) bit of dtmr is set and the dtxmr[dmaen] bit is cleared, an interrupt is issued when the time r counter reaches the reference value. dma timer operation is disabl ed in stop mode, but the dma timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes. upon exiting stop mode, the timer will resume operation unless stop mode was exited by reset.
power management mcf5213 reference manual, rev. 1.1 freescale semiconductor 7-13 preliminary 7.3.4.14 queued serial peripheral interface (qspi) in wait and doze modes, the queued serial peripheral in terface (qspi) may generate an interrupt to exit the low-power modes. ? clearing the qspi enable bit ( spe) disables the qspi function. ? the qspi is unaffected by wait mode and ma y generate an interrupt to exit this mode. in stop mode, the qspi stops imme diately and freezes operation, regist er values, state machines, and external pins. during this mode, the qspi clocks ar e shut down. coming out of st op mode returns the qspi to operation from the state prio r to the low-power mode entry. 7.3.4.15 uart modules (uart0, uart1, and uart2) in wait and doze modes, the uart may generate an interrupt to exit the low-power modes. ? clearing the transmit enable bit (te) or the r eceiver enable bit (re) disables uart functions. ? the uarts are unaffected by wa it mode and may generate an interrupt to exit this mode. in stop mode, the uarts stop immediate ly and freeze their opera tion, register values, state machines, and external pins. during this mode, the uart clocks are shut down. coming out of stop mode returns the uarts to operation from the state pr ior to the low-power mode entry. 7.3.4.16 i 2 c module when the i 2 c module is enabled by the setting of the i2cr[ie n] bit and when the device is not in stop mode, the i 2 c module is operable and may generate an interr upt to bring the device out of a low-power mode. for an interrupt to occur, the i2cr[iie] bit must be set to enable interrupts, and the setting of the i2sr[iif] generates the interrupt si gnal to the cpu and interrupt cont roller. the setting of i2sr[iif] signifies either the completion of one byte transfer or the reception of a calling address matching its own specified address when in slave receive mode. in stop mode, the i 2 c module stops immediately a nd freezes operation, register values, and external pins. upon exiting stop mode, the i 2 c resumes operation unless stop mode was exited by reset. 7.3.4.17 jtag the jtag (joint test action group) c ontroller logic is clocked using th e tclk input and is not affected by the system clock. the jtag cannot generate an ev ent to cause the cpu to exit any low-power mode. toggling tclk during any low-pow er mode will increase the system current consumption. 7.3.4.18 bdm entering halt mode via the bdm por t (by asserting the external bkpt pin) will cause th e cpu to exit any low-power mode.
power management mcf5213 reference manual, rev. 1.1 7-14 freescale semiconductor preliminary 7.3.5 summary of peripheral state during low-power modes the functionality of each of the pe ripherals and cpu during the various low-power modes is summarized in table 7-8 . the status of each peripheral during a give n mode refers to the condition the peripheral automatically assumes when the stop instruction is executed and the lpcr[lpmd] field is set for the particular low-power mode. indivi dual peripherals may be disabled by programming its dedicated control bits. the wake-up capability field refe rs to the ability of an interrupt or reset by that peripheral to force the cpu into run mode. table 7-8. cpu and peripherals in low-power modes module peripheral status 1 / wake-up capability 1 ?program? indicates that the peripheral function during th e low-power mode is dependent on programmable bits in the peripheral register map. wait mode doze mode stop mode coldfire core stopped no stopped no stopped no sram stopped no stopped no stopped no clock module enabled yes 3 enabled yes 3 program yes 3 power management enabled no enabled no stopped no chip configuration module enabled no enabled no stopped no reset controller enabled yes 2 2 these modules can generate a reset which will exit any low-power mode. enabled yes 2 enabled yes 2 system control module enabled yes 2 enabled yes 2 stopped no gpio module enabled no enabled no enabled no interrupt controller enabled yes 3 enabled yes 3 enabled yes 3 edge port enabled yes 3 enabled yes 3 stopped yes 3 ema controller enabled yes enabled yes stopped no programmable interrupt timers enabled yes 3 program yes 3 stopped no dma timers enabled yes 3 enabled yes 3 stopped no qspi enabled yes 3 enabled yes 3 stopped no uarts enabled yes 3 3 these modules can generate a interrupt which will exit a lo w-power mode. the cpu will begin to service the interrupt exception after wake-up. enabled yes 3 stopped no i 2 c module enabled yes 3 enabled yes 3 stopped no jtag enablednoenablednoenabledno bdm enabled yes 4 4 the bdm logic is clocked by a separate tclk clock. enteri ng halt mode via the bdm port exits any low-power mode. upon exit from halt mode, the previous low- power mode will be re-entered and changes made in halt mode will remain in effect. enabled yes 4 enabled yes 4
mcf5213 reference manual, rev. 1.1 freescale semiconductor 8-1 preliminary chapter 8 chip configuration module (ccm) 8.1 introduction this chapter describes the various operating configurat ions of the device. it provides a description of signals used by the ccm and a programming model. 8.1.1 block diagram the chip configuration module (ccm) controls the chip configuration and mode of operation for the mcf5213 figure 8-1. chip configuration module block diagram 8.1.2 features ? the ccm performs these operations.selects exte rnal clock or phase-lock loop (pll) mode with internal or external reference ? selects output pad drive strength ? selects low-power configuration ? selects processor status (pstat) and processor debug data (ddata) functions ? selects bdm or jtag mode clock mode output pad strength selection selection reset configuration register chip configuration register chip identification register chip test register
chip configuration module (ccm) mcf5213 reference manual, rev. 1.1 8-2 freescale semiconductor preliminary 8.2 external signal descriptions table 8-1 provides an overview of the ccm signals. 8.2.1 rcon if the external rcon pin is asserted during reset, then various chip functions, including the reset configuration pin functions af ter reset, are configured ac cording to the levels driv en onto the external data pins (see section 8.4, ?functional description ?). the internal configuration signals are driven to reflect the levels on the external configuration pins to allo w for module configuration. 8.2.2 clkmod[1:0] the state of the clkmod[1: 0] pins during reset dete rmines the clock mode after reset. refer to chapter 7, ?clock module? for more information. 8.3 memory map/register definition this subsection provides a descripti on of the memory map and registers. 8.3.1 programming model the ccm programming model cons ists of these registers: ? the chip configuration register (ccr) controls the main chip configuration. ? the reset configuration regi ster (rcon) indicates the default chip configuration. ? the chip identification register (c ir) contains a unique part number. some control register bits are implemented as write- once bits. these bits are al ways readable, but once the bit has been written, additional writes have no effect, except during debug and test operations. some write-once bits can be read and written while in debug mode. when debug mode is exited, the chip configuration module resumes operati on based on the current register va lues. if a write to a write-once register bit occurs while in debug m ode, the register bit remains writable on exit from debug or test mode. table 8-2 shows the accessibility of write-once bits. table 8-1. signal properties name function reset state rcon reset configuration select internal weak pull-up device clkmod[1:0] clock mode select 1 1 refer to chapter 7, ?clock module? for more information. ?
chip configuration module (ccm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 8-3 preliminary 8.3.2 memory map note to safeguard against unintentionally activating test l ogic, write 0x0000 to the above reserved location during initia lization (immediately after reset) to lock out test features. setting any bits in the ccr may lead to unpredictable results. 8.3.3 register descriptions the following subsection describes the ccm registers. 8.3.3.1 chip configuration register (ccr) table 8-2. write-once bits read/write accessibility configuration read/write access all configurations read-always debug operation write-always table 8-3. chip configuration module memory map ipsbar offset [31:24] [23:16] [15:8] [7:0] access 1 1 s = cpu supervisor mode access only. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 0x11_0004 chip configuration register (ccr) low-power control register (lpcr) 2 2 see chapter 8, ?power management,? for a description of the lpcr. it is shown here only to warn against accidental writes to this register. s 0x11_0008 reset configuration register (rcon) chip ident ification register (cir) s 0x11_000c reserved 3 3 writing to reserved addresses with values other than 0 could put the device in a test mode; reading returns 0s. s 0x11_0010 unimplemented 4 4 accessing an unimplemented address has no effect and causes a cycle termination transfer error. ? 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 00000000szenpsten0bme bmt w reset0 00000000 0 0 0 00 1 address ipsbar + 0x11_0004 figure 8-2. chip configuration register (rcon)
chip configuration module (ccm) mcf5213 reference manual, rev. 1.1 8-4 freescale semiconductor preliminary 8.3.3.2 reset configuration register (rcon) at reset, rcon determines the defa ult operation of certain chip functi ons. all default f unctions defined by the rcon values can only be overri dden during reset configuration (see section 8.4.1, ?reset configuration ?) if the external rcon pin is asserted. rcon is a read-only register. table 8-4. ccr field descriptions bits name description 15?7 ? reserved, should be cleared. 6 szen tsiz[1:0] enable. this read/write bit enable s the tsiz[1:0] function of the external pins. 0 tsiz[1:0] function disabled. 1 tsiz[1:0] function enabled. 5 psten pst[3:0]/ddata[3:0] enable. this read/writ e bit enables the processor status (pst) and debug data (ddata)n functions of the external pins. 0 pst/ddata function disabled. 1 pst/ddata function enabled. 4 ? reserved, should be cleared. 3 bme bus monitor enable. this read/write bit enables the bus monitor to operate during external bus cycles. 0 bus monitor disabled for external bus cycles. 1 bus monitor enabled for external bus cycles. ta b l e 8 - 2 shows the read/write accessi bility of this write-once bit. 2?0 bmt bus monitor timing. this field selects t he timeout period (in system clocks) for the bus monitor. 000 65536 001 32768 010 16384 011 8192 100 4096 101 2048 110 1024 111 512 ta b l e 8 - 2 shows the read/write accessi bility of this write-once bit. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 00000000 0rload0000mode w reset0 00000000 0 0 0 00 0 address ipsbar + 0x11_0008 figure 8-3. reset configuration register (rcon)
chip configuration module (ccm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 8-5 preliminary 8.3.3.3 chip identification register (cir) 8.4 functional description three functions are defined within the chip configuration module: 1. reset configuration 2. output pad strength configuration 3. clock mode selections these functions are describe d in the following sections. table 8-5. rcon field descriptions bits name description 15?6 ? reserved, should be cleared. 5 rload pad driver load. reflects the default pad driver strength configuration. 0 2ma (partial) drive strength (this is the default value used for the mcf5213.) 1 10ma (full) drive strength 4?1 ? reserved, should be cleared. 0 mode chip configuration mode. reflects the default chip configuration mode. 0 single-chip mode (this is the value used for the mcf5213.) 1 reserved.) the default mode cannot be overridden during reset configuration. 1514131211109876543210 rpin prn w reset0010000000000000 address ipsbar + 0x11_000a figure 8-4. chip identification register (cir) table 8-6. cir field description bits name description 15?6 pin part identification number. contains a unique identification number for the device. mcf5211 = 0x3c mcf5212 = 0x42 mcf5213 = 0x43 5?0 prn part revision number. this number is increased by one for each new full-layer mask set of this part. th e revision numbers are assigned in chronological order, beginning with zero.
chip configuration module (ccm) mcf5213 reference manual, rev. 1.1 8-6 freescale semiconductor preliminary 8.4.1 reset configuration during reset, the pins for the rese t override functions are immediat ely configured to known states. table 8-7 shows the states of the ex ternal pins while in reset. if the rcon pin is not asserted during reset, the chip configuration and the re set configuration pin functions after reset are determined by rcon or fixed defaults, regardless of the states of the external data pins. the internal configuration signals are driven to levels specified by the rc on register?s reset state for default module configuration. if the rcon pin is asserted during reset, then various chip functions, incl uding the reset c onfiguration pin functions after reset, are configur ed according to the levels driven onto the external data pins. (see table 8-8 ) the internal configurati on signals are driven to reflect the le vels on the external configuration pins to allow for module configuration. table 8-7. reset configuration pin states during reset pin pin function 1 1 if the external rcon pin is not asserted during reset, pin functions are determined by the default operation mode defined in the rcon register. if the external rcon pin is asserted, pin functions are determined by the override values driven on the external data bus pins. i/o output state input state rcon rcon function for all modes 2 2 during reset, the external rcon pin assumes its rcon pin function, but this pin changes to the function defined by the chip operation mode immediately after reset. see ta bl e 8 - 8 . input ? internal weak pull-up device clkmod1, clkmod0 not affected input ? must be driven by external logic table 8-8. configuration during reset 1 1 modifying the default configurations is possible only if the external rcon pin is asserted. pin(s) affected default configuration override pins in reset 2, function all output pins rcon[5] = 1 0 partial strength 1 full strength 4 clock mode no default 3 clkmod1, clkmod0 clock mode 00 external clock mode (pll disabled) 01 1:1 pll mode 10 normal pll mode with external clock reference 11 normal pll mode w/crystal reference
chip configuration module (ccm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 8-7 preliminary 8.4.2 output pad strength configuration output pad strength is de termined during reset conf iguration. once reset is ex ited, the output pad strength configuration can be changed by pr ogramming the pin drive strength re gister as described in section 11.6.6.2. 8.4.3 clock mode selection the clock mode is selected during reset and reflect ed in the pllmode, pllsel, and pllref bits of synsr. once reset is exited, th e clock mode cannot be changed. table 8-9 summarizes clock mode selection during re set configuration. 8.5 reset reset initializes cc m registers to a known start up state as described in section 8.3, ?memory map/register definition.? the ccm controls chip configur ation at reset as described in section 8.4, ?functional description .? 2 the external reset override circuitry drives the data bus pins with the override values while rstout is asserted. it must stop driving the data bus pins within one clkout cycle after rstout is negated. to prev ent contention with the external reset override circuitry, the reset override pins are forced to inputs during reset and do not become outputs until at least one clkout cycle after rstout is negated. rcon must also be negated within one cycle after rstout is negated. 3 there is no default configuration for clock mode selection. the actual values for the clkmod pins must always be driven during reset. once out of reset, the clkmod pins have no effect on the clock mode selection. table 8-9. clock mode selection 1 1 there is no default configuration for clock mode selection. th e actual values for the clkmod pins must always be driven during reset. once out of reset, the clkmod pi ns have no effect on the clock mode selection. clock mode clkmod[1] clkmod[0] pll synsr bits pllmode pllsel pllref external clock mode; pll disabled 0 0 0 0 0 1:1 pll mode 0 1 1 0 0 normal pll mode; external clock reference 1 0 1 1 0 normal pll mode; crystal oscillator reference 1 0 1 1 1
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mcf5213 reference manual, rev. 1.1 freescale semiconductor 9-1 preliminary chapter 9 reset controller module the reset controller is provided to determine the cause of reset, assert the appropr iate reset signals to the system, and then to keep a history of what caused the reset. th e low voltage detec tion module, which generates low-voltage detect (lvd ) interrupts and resets, is implem ented within the reset controller module. 9.1 features module features include: ? seven sources of reset: ? external ? power-on reset (por) ? phase locked-loop (pll) loss of lock ? pll loss of clock ? software ? lvd reset ? software-assertable rsto pin independent of chip reset state ? software-readable status flags indi cating the cause of the last reset ? lvd control and status bits for setup and use of lvd reset or interrupt 9.2 block diagram figure 9-1 illustrates the reset controller and is explained in the following sections. figure 9-1. reset controller block diagram power-on reset pll loss of clock pll loss of lock software reset lv d detect rsti pin reset controller rsto pin to internal resets
reset controller module mcf5213 reference manual, rev. 1.1 9-2 freescale semiconductor preliminary 9.3 signals table 9-1 provides a summary of the rese t controller signal properties. th e signals are described in the following paragraphs. 9.3.1 rsti asserting the external rsti for at least four rising clkout edges ca uses the external reset request to be recognized and latched. 9.3.2 rsto this active-low output signal is driven low when the in ternal reset controller module resets the chip. when rsto is active, the user can drive override options on the data bus. 9.4 memory map and registers the reset controller programming m odel consists of these registers: ? reset control register (rcr), whic h selects reset controller functions ? reset status register (rsr), which refl ects the state of the last reset source see table 9-2 for the memory map and the following para graphs for a description of the registers. 9.4.1 reset control register (rcr) the rcr allows software control fo r requesting a reset, for independe ntly asserting the external rsto pin, and for controlling low-vol tage detect (lvd) functions. table 9-1. reset controller signal properties name direction input hysteresis input synchronization rsti iy y 1 1 rsti is always synchronized except when in low-power stop mode. rsto o? ? table 9-2. reset controller memory map ipsbar offset [31:24] [23:16] [15:8] [7:0] access 1 1 s/u = supervisor or user mode access. 0x11_0000 rcr rsr reserved 2 reserved 2 2 writes to reserved address locations have no effect and reads return 0s. s/u
reset controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 9-3 preliminary 9.4.2 reset status register (rsr) the rsr contains a status bit for every reset source. when reset is entered, the cause of the reset condition is latched along with a value of 0 fo r the other reset sources that were not pending at the time of the reset 7654 0 field softrst frcrstout ? lvdf lvdie lvdre ? lvde reset 0000_0101 r/w r/w address ipsbar + 0x11_0000 figure 9-2. reset control register (rcr) table 9-3. rcr field descriptions bit(s) name description 7 softrst allows software to request a reset. the reset caused by setting this bit clears this bit. 1 software reset request 0 no software reset request 6 frcrstout allows software to assert or negate the external rsto pin. 1 assert rsto pin 0 negate rsto pin caution: external logic driving reset configuration data during reset needs to be considered when asserting the rsto pin when setting frcrstout. 5 ? reserved, should be cleared. 4 lvdf lvd flag. indicates the low-voltage detect st atus if lvde is set. write a 1 to clear the lvdf bit. 1 low voltage has been detected 0 low voltage has not been detected note: the setting of this flag causes an lv d interrupt if lvde and lvdie bits are set and lvdre is cleared when the supply voltage v dd drops below v dd (minimum). the vector for this interrupt is shared with int0 of the eport module. interrupt arbitration in the interrupt service routine is necessary if both of these interrupts are enabled. also, lvdf is not cleared at reset, however it will always initialize to a zero since the part will not come out of reset while in a low-power state (lvde/lvdre bits are enabled out of reset). 3 lvdie lvd interrupt enable. controls the lvd interrupt if lvde is set. this bit has no effect if the lvde bit is a logic 0. 1 lvd interrupt enabled 0 lvd interrupt disabled 2 lvdre lvd reset enable. controls the lvd reset if lvde is set. this bit has no effect if the lvde bit is a logic 0. lvd reset has priority over lvd interrupt, if both are enabled. 1 lvd reset enabled 0 lvd reset disabled 1 ? reserved, should be cleared. 0 lvde controls whether the lvd is enabled. 1 lvd is enabled 0lvd is disabled
reset controller module mcf5213 reference manual, rev. 1.1 9-4 freescale semiconductor preliminary condition. these values are then reflected in rsr. one or more status bits may be set at the same time. the cause of any subsequent reset is also recorded in the register, overwr iting status from the previous reset condition. rsr can be read at any time. writing to rsr has no effect. 9.5 functional description 9.5.1 reset sources table 9-5 defines the sources of reset and the signals driven by the reset controller. 76543210 field ? lvd soft ? por ext loc lol reset reset dependent r/w r address ipsbar + 0x11_0001 figure 9-3. reset status register (rsr) table 9-4. rsr field descriptions bit(s) name description 7 ? reserved, should be cleared. 6 lvd low voltage detect. indicates that the last reset state was caused by an lvd reset. 1 last reset state was caused by an lvd reset 0 last reset state was not caused by an lvd reset 5 soft software reset flag. indicates that the last reset was c aused by software. 1 last reset caused by software 0 last reset not caused by software 4 ? reserved, should be cleared. 3 por power-on reset flag. indicates that the last reset was caused by a power-on reset. 1 last reset caused by power-on reset 0 last reset not caused by power-on reset 2 ext external reset flag. indica tes that the last reset was c aused by an external device asserting the external rsti pin. 1 last reset state caused by external reset 0 last reset not caused by external reset 1 loc loss-of-clock reset flag. in dicates that the last reset state was caused by a pll loss of clock. 1 last reset caused by loss of clock 0 last reset not caused by loss of clock 0 lol loss-of-lock reset flag. indicates that the last reset state was caused by a pll loss of lock. 1 last reset caused by a loss of lock 0 last reset not caused by loss of lock
reset controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 9-5 preliminary to protect data integrity, a sync hronous reset source is not acted upon by the reset control logic until the end of the current bus cycle. reset is then asserted on the next rising edge of the system clock after the cycle is terminated. whenever the reset control logi c must synchronize reset to the end of the bus cycle, the internal bus monitor is automatically enabled regard less of the bme bit state in the chip configuration register (ccr). then, if the current bus cycle is not terminated normally the bus monitor terminates the cycle based on the length of time progr ammed in the bmt field of the ccr. internal byte, word, or longword writes are guaranteed to complete without data corruption when a synchronous reset occurs. ex ternal writes, including longword writes to 16-bit ports, are also guaranteed to complete. asynchronous reset sources usually indi cate a catastrophic failure. ther efore, the reset control logic does not wait for the current bus cycle to complete. reset is asserted immediately to the system. 9.5.1.1 power-on reset at power up, the reset c ontroller asserts rsto . rsto continues to be asserted until v dd has reached a minimum acceptable level a nd, if pll clock mode is selected, unt il the pll achieves phase lock. then after approximately an other 512 cycles, rsto is negated and the part begins operation. 9.5.1.2 external reset asserting the external rsti for at least four rising clkout edges ca uses the external reset request to be recognized and latched. the bus monitor is enabled and the current bus cycle is completed. the reset controller asserts rsto for approximately 512 cycles after rsti is negated and the pll has acquired lock. the part then exits reset and begins operation. in low-power stop mode, the system clocks are stopped. a sserting the external rsti in stop mode causes an external reset to be recognized. 9.5.1.3 loss-of-clock reset this reset condition occurs in pll clock mode when the locre bit in the sync r is set and either the pll reference or the pll itself fail s. the reset controller asserts rsto for approximately 512 cycles after the pll has acquired lock. the part th en exits reset and begins operation. table 9-5. reset source summary source type power on asynchronous external rsti pin (not stop mode) synchronous external rsti pin (during stop mode) asynchronous loss of clock asynchronous loss of lock asynchronous software synchronous lvd reset asynchronous
reset controller module mcf5213 reference manual, rev. 1.1 9-6 freescale semiconductor preliminary 9.5.1.4 loss-of-lock reset this reset condition occurs in pll clock mode when the lolre bit in the s yncr is set and the pll loses lock. the reset controller asserts rsto for approximately 512 cycles after the pll has acquired lock. the part then exits reset and resumes operation. 9.5.1.5 software reset a software reset occurs when the softrst bit is set. if the rsti is negated and the pll has acquired lock, the reset controller asserts rsto for approximately 512 cycles. then the part exits reset and resumes operation. 9.5.1.6 lvd reset the lvd reset will occur when the supply input voltage, v dd, drops below v lvd (minimum). 9.5.2 reset control flow the reset logic contro l flow is shown in figure 9-4 . in this figure, the c ontrol state boxes have been numbered, and these numbers ar e referred to (within parent heses) in the flow descri ption that follows. all cycle counts given are approximate.
reset controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 9-7 preliminary figure 9-4. reset control flow rsti pin or wd timeout or sw reset? loss of clock? loss of lock? rsti negated? pll mode? bus cycle complete? rcon asserted? pll locked? enable bus monitor assert rsto and latch reset status wait 512 clkout cycles latch configuration negate rsto por or lvd assert rsto and latch reset status n n n y y y 1 2 3 n n n 0 5 6 7 8 9 10 11 y y n n y y 12 4 9a 11a y
reset controller module mcf5213 reference manual, rev. 1.1 9-8 freescale semiconductor preliminary 9.5.2.1 synchronous reset requests in this discussion, the reference in pare ntheses refer to the state numbers in figure 9-4 . all cycle counts given are approximate. if the external rsti signal is asserted by an external device fo r at least four rising clkout edges (3), if software requests a reset, the rese t control logic latches the reset re quest internally and enables the bus monitor (5). when the current bus cycle is completed (6), rsto is asserted (7). the reset control logic waits until the rsti signal is negated (8) and for the pll to attain lock (9, 9a) before waiting 512 clkout cycles (1). the reset control logic may latch the conf iguration according to the rcon signal level (11, 11a) before negating rsto (12). if the external rsti signal is asserted by an exte rnal device for at least f our rising clkout edges during the 512 count (10) or during the wait for pll lock (9a), the reset flow switches to (8) and waits for the rsti signal to be negated before continuing. 9.5.2.2 internal reset request if reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss of lock (2), the reset control logic asserts rsto (4). the reset control logic waits for the pll to attain lock (9, 9a) before waiting 512 clkout cycles (1). then the reset control logic may latch the configuration according to the rcon pin level (11, 11a) before negating rsto (12). if loss of lock occurs during the 512 count (10) , the reset flow switches to (9a) and waits for the pll to lock before continuing. 9.5.2.3 power-on reset/low-voltage detect reset when the reset sequence is initiated by power-on reset (0), the same rese t sequence is followed as for the other asynchronous reset sources. 9.5.3 concurrent resets this section describes the c oncurrent resets. as in the previous disc ussion references in parentheses refer to the state numbers in figure 9-4 . 9.5.3.1 reset flow if a power-on reset or low-voltage detect condition is detected during any re set sequence, the reset sequence starts immediately (0). if the external rsti pin is asserted for at l east four rising clkou t edges while waiti ng for pll lock or the 512 cycles, the external reset is recognized. reset proces sing switches to wait for the external rsti pin to negate (8). if a loss-of-clock or loss-of-lock condition is detected while waiting fo r the current bus cycle to complete (5, 6) for an external reset request, the cycle is terminated. the reset status bits ar e latched (7) and reset processing waits for the external rsti pin to negate (8). if a loss-of-clock or loss-of-loc k condition is det ected during the 512 cycle wait, the reset sequence continues after a pll lock (9, 9a).
reset controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 9-9 preliminary 9.5.3.2 reset status flags for a por reset, the por and lvd bits in the rsr are set, and the soft, wdr, ext, loc, and lol bits are cleared even if another t ype of reset condition is detected during the reset sequence for the por. if a loss-of-clock or loss-of-lock condition is detected while waiting fo r the current bus cycle to complete (5, 6) for an external reset reque st, the ext, soft, and/or wdr bits along with the loc and/or lol bits are set. if the rsr bits are latched (7) during the ext, soft, and/or wdr reset sequence with no other reset conditions detected, only the ext, soft, and/or wdr bits are set. if the rsr bits are latched (4) during th e internal reset sequence with the rsti pin not asserted and no soft or wdr event, then the loc a nd/or lol bits are the only bits set. for a lvd reset, the lvd bit in the rsr is set, and the soft, wdr, ex t, loc, and lol bits are cleared to 0 even if another type of reset condition is detected during the reset sequence for lvd.
reset controller module mcf5213 reference manual, rev. 1.1 9-10 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 10-1 preliminary chapter 10 system control module (scm) this section details the functionality of the system control module (scm) which provides the programming model for the system a ccess control unit (sacu), the syst em bus arbiter, a 32-bit core watchdog timer (cwt), and the system control regist ers and logic. specifically, the system control includes the internal peripheral syst em (ips) base address register (i psbar), the processor?s dual-port ram base address register (rambar), and system control register s that include the core watchdog timer control. 10.1 overview the scm provides the control and stat us for a variety of f unctions including base addressing and address space masking for both the ips periphe rals and resources (ipsbar) and th e coldfire core memory spaces (rambar). the cpu core s upports two memory banks, one for the in ternal sram and the other for the internal flash. the sacu provides the mechanism needed to implement secure bus transactions to the system address space. the programming model for the system bus arbitrat ion resides in the scm. the scm sources the necessary control signals to the ar biter for bus mast er management. the cwt provides a means of preventi ng system lockup due to uncontroll ed software loops via a special software service sequence. if periodic software servicing action doe s not occur, the cw t times out with a programmed response (system reset or interrupt) to allow recovery or corrective action to be taken. 10.2 features the scm includes these distinctive features: ? ips base address register (ipsbar) ? base address location for 1-gbyte peripheral space ? user control bits ? processor-local memory base address regi ster (rambar) ? system control registers ? core reset status register (crsr) indicates type of last reset ? core watchdog control register (c wcr) for watchdog timer control ? core watchdog service register (c wsr) to service watchdog timer ? system bus master arbitrat ion programming model (mpark) ? system access control unit (sacu) programming model
system control module (scm) mcf5213 reference manual, rev. 1.1 10-2 freescale semiconductor preliminary ? master privilege register (mpr) ? peripheral access control registers (pacrs) ? grouped peripheral access contro l registers (gpacr0, gpacr1) 10.3 memory map and register definition the memory map for the scm registers is shown in table 10-1 . all the registers in the scm are memory-mapped as offsets within th e 1 gbyte ips address space and accesses are controlled to these registers by the control definiti ons programmed into the sacu. 10.4 register descriptions 10.4.1 internal peripheral system base address register (ipsbar) the ipsbar specifies the base address for the 1 gbyte memory space associated with the on-chip peripherals. at reset, the base address is loaded with a default location of 0x4000_0000 and marked as valid (ipsbar[v]=1). if desired, the address space associated with the internal modules can be moved by loading a different value into the ipsbar at a later time. table 10-1. scm register map ipsbar offset [31:24] [23:16] [15:8] [7:0] 0x00_0000 ipsbar 0x00_0004 ? 0x00_0008 rambar 0x00_000c ppmrh 0x00_0010 crsr cwcr lpicr 1 1 the lpicr is described in chapter 7, ?power management .? cwsr 0x00_0014 dmareqc 2 2 the dmareqc register is described in chapter 14, ?dma controller module ? 0x00_0018 ppmrl 0x00_001c mpark 0x00_0020 mpr ppmrs ppmrc ipsbmt 0x00_0024 pacr0 pacr1 pacr2 pacr3 0x00_0028 pacr4 pacr5 pacr6 pacr7 0x00_002c pacr8 ? ? ? 0x00_0030 gpacr0 gpacr1 ? ? 0x00_0034 ? ? ? ? 0x00_0038 ? ? ? ? 0x00_003c ? ? ? ?
system control module (scm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 10-3 preliminary note accessing reserved ipsbar memory sp ace could result in an unterminated bus cycle that causes the core to hang. only a hard reset will allow the core to recover from this state. therefor e, all bus accesses to ipsbar space should fall within a module?s memory map space. if an address ?hits? in overlappi ng memory regions, the following prio rity is used to determine what memory is accessed: 1. ipsbar 2. rambar 3. chip selects note this is the list of memory access priori ties when viewed from the processor core. see figure 10-1 and table 10-2 for descriptions of the bits in ipsbar. 10.4.2 memory base address register (rambar) the device supports dual-ported local sram memo ry. this processor-local memory can be accessed directly by the core and/or other system bus masters. since this memory provides single-cycle accesses at processor speed, it is ideal for applications where double-buffer sche mes can be used to maximize 31 30 29 16 field ba31 ba30 ? reset 0 1 ? r/w r/w 15 10 field ? v reset ? r/w r/w address ipsbar + 0x000 figure 10-1. ips base address register (ipsbar) table 10-2. ipsbar field description bits name description 31?30 ba base address. defines the base address of the 1-gbyte internal peripheral space. this is the starting address for the ips registers when the valid bit is set. 29?1 ? reserved, should be cleared. 0 v valid. enables/disables the ips base address region. v is set at reset. 0 ips base address is not valid. 1 ips base address is valid.
system control module (scm) mcf5213 reference manual, rev. 1.1 10-4 freescale semiconductor preliminary system-level performance. for example, a dma channel in a typical double-buffer (also known as a ping-pong scheme) application may load data into one portion of the dual-ported sram while the processor is manipulating data in another portion of the sram. once the processor completes the data calculations, it begins processing the just-loaded buffer while the dma moves out the just-calculated data from the other buffer, and reloads the next data bl ock into the just-freed memory region. the process repeats with the processor and the dma ?ping-pongi ng? between alternate re gions of the dual-ported sram. the device design implements th e dual-ported sram in the memory space defined by the rambar register. there are two physi cal copies of the rambar register: one located in the processor core and accessible only via the privileged movec instruct ion at cpu space address 0xc05 and another located in the scm at ipsbar + 0x008. coldfire core accesses to this memory are controlled by the processor-local copy of the rambar, while m odule accesses are enabled by the scm's rambar. the physical base address programmed in both copies of the rambar is typi cally the same value; however, they can be programmed to different valu es. by definition, the base address must be a 0-modulo-size value. the sram modules are configured through the rambar shown in figure 10-2 . ? rambar specifies the base address of the sram. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field ba31 ba30 ba29 ba28 ba27 ba26 ba25 ba2 4 ba23 ba22 ba21 ba20 ba19 ba18 ba17 ba16 reset 0000_0000_0000_0000 r/w r/w 15 10 9 8 0 field ? bde ? reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x008 figure 10-2. memory base address register (rambar) table 10-3. rambar field description bits name description 31?16 ba base address. defines the memory module's base address on a 64-kbyte boundary corresponding to the physical array location within the 4 gbyte address space supported by coldfire. 15?10 ? reserved, should be cleared. 9 bde back door enable. qualifies the module accesses to the memory. 0 disables module acce sses to the module. 1 enables module accesses to the module. note: the spv bit in the cpu?s rambar must also be set to allow dual port access to the sram. for more information, see section 6.2.1, ?sram base address register (rambar) .? 8?0 ? reserved, should be cleared.
system control module (scm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 10-5 preliminary ? all undefined bits are reserve d. these bits are ignored during wr ites to the rambar and return zeros when read. ? the back door enable bit, rambar [bde], is cleared at reset, di sabling the module access to the sram. note the rambar default value of 0x0000_0000 is invalid. the rambar located in the processor?s cpu space mu st be initialized with the valid bit set before the cpu (or modules) can access the on-chip sram (see chapter 6, ?static ram (sram) ? for more information. for details on the processor's view of the local sram memories, see section 6.2.1, ?sram base address register (rambar) .? 10.4.3 core reset stat us register (crsr) the crsr contains a bit for two of th e reset sources to the cpu. a bit se t to 1 indicates the last type of reset that occurred. the crsr is upda ted by the control logic when the re set is complete. only one bit is set at any one time in the crsr. the register reflects the cause of the mo st recent reset. to clear a bit, a logic 1 must be written to the bit location; writing a zero has no effect. note the reset status register (rsr) in the reset controller module (see chapter 29, ?reset controller module ?) provides indication of all reset sources except the co re watchdog timer. 7654 0 field ext ? cwdr ? reset see note r/w r/w address ipsbar + 0x010 note: the reset value of ext and cwdr depend on the last reset source. all other bits are initialized to zero. figure 10-3. core reset status register (crsr) table 10-4. crsr field descriptions bits name description 7 ext external reset. 1 an external device driving rsti caused the last reset. assertion of reset by an external device causes the processor core to init iate reset exception processing. all registers are forced to their initial state. 6 ? reserved, should be cleared.
system control module (scm) mcf5213 reference manual, rev. 1.1 10-6 freescale semiconductor preliminary 10.4.4 core watchdog control register (cwcr) the core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit. the core watchdog timer can be enabled or disabled through cwcr[cwe]. by default it is disabled. if enabled, the watc hdog timer requires the periodic execu tion of a core watchdog servicing sequence. if this periodic servicing action does not occu r, the timer times out, resu lting in a watchdog timer interrupt or a hardware reset, as programmed, by cwcr[cwri]. if the timer times out and the core watchdog transfer acknowledge enable bit (cwcr[cwta]) is set, a watchdog timer interrupt is asserted. if a core watchdog timer interrupt acknowledge cycle has not occurred after another timeout, cwt ta is asserted in an attempt to allow the interrupt acknowledge cycle to pr oceed by terminating the bus cycle. the setting of cwcr[cwtaval] indicates that the watchdog timer ta was asserted. when the core watchdog timer times out and cwcr[cw ri] is programmed for a software reset, an internal reset is asserted and cr sr[cwdr] is set. to prevent the core watchdog timer from interrupting or resetting, the cwsr must be servi ced by performing the following sequence: 1. write 0x55 to cwsr. 2. write 0xaa to the cwsr. both writes must occur in order before the time-out , but any number of instru ctions can be executed between the two writes. this order al lows interrupts and exceptions to oc cur, if necessary , between the two writes. caution should be exercised when changing cwcr values after the so ftware watchdog timer has been enabled with the setting of cw cr[cwe], because it is difficult to determine the state of the core watchdog timer while it is running. th e countdown value is cons tantly compared with the time-out period specified by cwcr[cwt]. the following steps must be taken to change cwt: 1. disable the core watchdog timer by clearing cwcr[cwe]. 2. reset the counter by writing 0x55 and then 0xaa to cwsr. 3. update cwcr[cwt]. 4. re-enable the core watchdog timer by setting cwcr[c we]. this step can be performed in step 3. the cwcr controls the so ftware watchdog timer, time-out periods, and so ftware watchdog ti mer transfer acknowledge. the register can be read at any time, but can be written only if the cwt is not pending. at system reset, the software watchdog timer is disabled. 5 cwdr core watchdog timer reset. 1 the last reset was caused by the core watchdog timer. if cwri in the cwcr is set and the core watchdog timer times out, a hard reset occurs. 4?0 ? reserved, should be cleared. table 10-4. crsr field descriptions bits name description
system control module (scm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 10-7 preliminary 765 32 1 0 field cwe cwri cwt[2:0] cwta cwtaval cwtic reset 0000_0000 r/w r/w address ipsbar + 0x011 figure 10-4. core watchdog control register (cwcr) table 10-5. cwcr field description bits name description 7 cwe core watchdog enable. 0 swt disabled. 1 swt enabled. 6 cwri core watchdog reset/interrupt select. 0 if a time-out occurs, the cwt generates an interrupt to the processor core. the interrupt level for the cwt is programmed in the interrupt control register 7 (icr7) of intc0. 1 a cwt time-out generates a soft reset to the entire device. 5?3 cwt[2:0] core watchdog timing delay. these bits se lect the timeout period for the cwt as shown in ta b l e 8 - 6 . at system reset, the cwt field is cleared signa ling the minimum time-out period but the watchdog is disabled (cwcr[cwe] = 0). the following table shows the core watchdog timer delay. 2 cwta core watchdog transfer acknowledge enable. 0 cwta transfer acknowledge disabled. 1 cwta transfer acknowledge enabled. after one cwt time-out period of the unacknowledged assertion of the cwt interrupt, the transfer acknowledge asserts, which allows cwt to terminate a bus cycle and allow the interrupt acknowledge to occur. 1 cwtaval core watchdog transfer acknowledge valid. 0 cwta transfer acknowledge has not occurred. 1 cwta transfer acknowledge has occurred. write a 1 to clear this flag bit. 0 cwtif core watchdog timer interrupt flag. 0 cwt interrupt has not occurred 1 cwt interrupt has occurred. write a 1 to clear the interrupt request. cwt [2:0] c wt time-out period 000 2 9 bus clock frequency 001 2 11 bus clock frequency 010 2 13 bus clock frequency 011 2 15 bus clock frequency 100 2 19 bus clock frequency 101 2 23 bus clock frequency 110 2 27 bus clock frequency 111 2 31 bus clock frequency
system control module (scm) mcf5213 reference manual, rev. 1.1 10-8 freescale semiconductor preliminary 10.4.5 core watchdog service register (cwsr) the software watchdog service sequence must be performed using the cwsr as a data register to prevent a cwt time-out. the service sequen ce requires two writes to this da ta register: first a write of 0x55 followed by a write of 0xaa. both wr ites must be performed in this or der prior to the cwt time-out, but any number of instructions or accesse s to the cwsr can be executed be tween the two writes. if the cwt has already timed out, writing to this register has no effect in negating the cwt interrupt. figure 10-5 illustrates the cwsr. at system reset, the contents of cwsr are uninitialized. 10.4.6 overview the basic functionality is that of a 4-port, pipelined internal bus ar bitration module with the following attributes: ? the master pointed to by the current arbitration poi nter may get on the bus with zero latency if the address phase is available. all other requesters f ace at least a one cycle ar bitration pipeline delay in order to meet bus timing c onstraints on address phase hold. ? if a requester will get an immediat e address phase (that is, it is pointed to by the current arbitration pointer and the bus address phase is available), it will be the curr ent bus master and is ignored by arbitration. all remaining requesting ports are eval uated by the arbitration algorithm to determine the next-state arbitration pointer. ? there are two arbitration algorithms, fixed and r ound-robin. fixed arbitrati on sets the next-state arbitration pointer to the highest priority requester. round-robin ar bitration sets the next-state arbitration pointer to the highest priority requester (calculated by a dding a requester's fixed priority to the current bus master?s fixed priority and then taking this sum modul o the number of possible bus masters). ? the default priority is dma (m2) > cpu (m0) , where m2 is the highest and m0 the lowest priority. ? there are two actions for an idle arbitration cycle, either leave the current arbi tration pointer as is or set it to the lowest priority requester. ? the anti-lock-out logic for the fixed priority sc heme forces the arbitrat ion algorithm to round-robin if any requester has been held for longer than a specified cycle count. 10.4.7 arbitration algorithms there are two modes of arbitration: fixed and round-robin. this secti on discusses the differences between them. 7 0 field cwsr[7:0] reset uninitialized r/w r/w address ipsbar + 0x013 figure 10-5. core watchdog service register (cwsr)
system control module (scm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 10-9 preliminary 10.4.7.1 round-robin mode round-robin arbitration is the defaul t mode after reset. this scheme cycles through the sequence of masters as specified by mpark[m n _prty] bits. upon completion of a tr ansfer, the master is given the lowest priority and the priority for all other masters is increased by one. if no masters are requesting, the arbitration unit must ?park?, pointing at one of the masters. there are two possibilities, park the arbi tration unit on the last active master, or park pointing to the highest priority master. setting mpark[prk_last] cau ses the arbitration pointer to be parked on the highest priority master. in round-robin mode, programming the timeout enable and lockout bits mpark[13,11:8] will have no effect on the arbitration. 10.4.7.2 fixed mode in fixed arbitration the master with highest priority (as specified by the mpark[m n _prty] bits) will win the bus. that master will relinquish the bus when all transfers to that master are complete. if mpark[timeout] is set, a counter will increment for each master for every cycle it is denied access. when a counter reaches the limit set by mpark[lc kout_time], the arbitrat ion algorithm will be changed to round-robin arbitration mode until all locks are cleared. the arbi tration will then return to fixed mode and the highest priority ma ster will be granted the bus. as in round-robin mode, if no mast ers are requesting, the arbitration pointer will park on the highest priority master if mpark[prk_last] is set, or will park on the master which last requested the bus if cleared. 10.4.8 bus master park register (mpark) the mpark controls the operation of the system bus arbitration module. th e platform bus master connections are defined as: ? master 2 (m2): 4-channel dma ? master 0 (m0): v2 coldfire core 31 26 25 24 23 22 21 20 19 18 17 16 field ? m2_p_en bcr24bit ? m2_prty m0_prty reset 0011_0000_1110_0001 r/w r/w 15 14 13 12 11 8 7 0 field ? fixed timeout prklast lckout_time ? reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x01c figure 10-6. default bus master park register (mpark)
system control module (scm) mcf5213 reference manual, rev. 1.1 10-10 freescale semiconductor preliminary the initial state of the master priorities is m2 > m0. system software should guarantee that the programmed m n _prty fields are unique, otherwise the hardware defaults to the initial-state priorities. 10.5 system access control unit (sacu) this section details the functionality of the syst em access control unit (s acu) which provides the mechanism needed to implement secure bus transact ions to the address space mapped to the internal modules. table 10-6. mpark field description bits name description 31?26 ? reserved, should be cleared. 25 m2_p_en dma bandwith control enable 0 disable the use of the dma's b andwidth control to elevate the priority of its bus requests. 1 enable the use of the dma's bandwidth control to elevate the priority of its bus requests. 24 bcr24bit enables the use of 24 bit by te count registers in the dma module 0 dma bcrs function as 16 bit counters. 1 dma bcrs function as 24 bit counters. 23?22 ? reserved, should be cleared. 21?20 m2_prty master priority level for master 2 (dma controller) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority 19?18 m0_prty master priority level for master 0 (coldfire core) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority 17?16 ? reserved, should be cleared. 15 ? reserved, should be cleared. 14 fixed fixed or round robin arbitration 0 round robin arbitration 1 fixed arbitration 13 timeout timeout enable 0 disable count for when a master is locked out by other masters. 1 enable count for when a master is locked out by other masters and allow access when lckout_time is reached. 12 prklast park on the last active master or hi ghest priority master if no masters are active 0 park on last active master 1 park on highest priority master 11?8 lckout_time lock-out time. lock-out time for a master being denied the bus. the lock out time is defi ned as 2^ lckout_time[3:0]. 7?0 ? reserved, should be cleared.
system control module (scm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 10-11 preliminary 10.5.1 overview the sacu supports the traditional model of two privil ege levels: supervisor and user. typically, memory references with the supervis or attribute have total acces sibility to all the resources in the system, while user mode references cannot acce ss system control and configuration regi sters. in many systems, the operating system executes in supervisor mode, while application soft ware executes in user mode. the sacu further partitions the acce ss control functions into two parts: one control register defines the privilege level associated with each bus master, and anot her set of control registers define the access levels associated with the periphera l modules and the memory space. the sacu?s programming model is phys ically implemented as part of the system control module (scm) with the actual access control logic included as part of the arbitration controller. each bus transaction targeted for the ips space is first checked to see if its privilege rights allow access to the given memory space. if the privilege rights are correct, the acce ss proceeds on the bus. if the privilege rights are insufficient for the targeted memory space, the transf er is immediately aborted and terminated with an exception, and the targeted module not accessed. 10.5.2 features each bus transfer can be classified by its privilege level a nd the reference type. the complete set of access types includes: ? supervisor instruction fetch ? supervisor operand read ? supervisor operand write ? user instruction fetch ? user operand read ? user operand write instruction fetch accesses are associ ated with the execute attribute. it should be noted that while the bus does not implement the concept of reference type (c ode versus data) and only supports the user /supervisor privilege level, the refere nce type attribute is supported by the system bus. accordingly, the access checking associated with both privilege level and reference type is performed in the ips controller usi ng the attributes associated with the reference from the system bus. the sacu partitions the access control m echanisms into three distinct functions: ? master privilege register (mpr) ? allows each bus master to be assigned a privilege level: ? disable the master?s user/supervisor a ttribute and force to user mode access ? enable the master?s user/supervisor attribute ? the reset state provides supervisor privileg e to the processor core (bus master 0). ? input signals allow the non-core bus masters to have their user/s upervisor attribute enabled at reset. this is intended to support the concept of a trusted bus master, and also controls the ability of a bus master to modify the register stat e of any of the sacu control registers; that is, only trusted masters can modi fy the control registers.
system control module (scm) mcf5213 reference manual, rev. 1.1 10-12 freescale semiconductor preliminary ? peripheral access control registers (pacrs) ? nine 8-bit registers cont rol access to 17 of the on- chip peripheral modules. ? provides read/write access rights, supervisor/user privilege levels ? reset state provides supervisor-onl y read/write access to these modules ? grouped peripheral access contro l registers (gpacr0, gpacr1) ? one single register (gpacr0) controls acc ess to 14 of the on-chip peripheral modules ? one register (gpacr1) controls access for ips reads and writes to the flash module
system control module (scm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 10-13 preliminary ? provide read/write/execute access ri ghts, supervisor/user privilege levels ? reset state provides supervisor-only read/wri te access to each of these peripheral spaces 10.5.3 memory map/register definition the memory map for the sacu program-visible regi sters within the system control module (scm) is shown in figure 10-7 . the mpr, pacr, and gpacrs are 8 bits in width. 10.5.3.1 master privile ge register (mpr) the mpr specifies the access privilege level associated with each bus master in the platform. the register provides one bit per bus master, where bit 3 corresponds to master 3 (fast ethernet controller), bit 2 to master 2 (dma controller), bit 1 to master 1 (internal bus master), a nd bit 0 to master 0 (coldfire core). table 10-7. sacu register memory map ipsba r offset [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x020 mpr ppmrs ppmrc ipsbmt 0x024 pacr0 pacr1 pacr2 pacr3 0x028 pacr4 pacr5 pacr6 pacr7 0x02c pacr8 ? ? ? 0x030 gpacr0 gpacr1 ? ? 0x034 ? ? ? ? 0x038 ? ? ? ? 0x03c ? ? ? ? 7 0 field ? mpr[3:0] reset 0000_0011 r/w r/w address ipsbar + 0x020 figure 10-7. master privilege register (mpr) table 10-8. mpr[n] field descriptions bits name description 7?4 ? reserved. should be cleared. 3?0 mpr each 1-bit field defines the access privilege level of the given bus master n . 0 all bus master accesses are in user mode. 1 all bus master accesses use the sourced user/supervisor attribute.
system control module (scm) mcf5213 reference manual, rev. 1.1 10-14 freescale semiconductor preliminary only trusted bus masters can modify the access control registers. if a non-trusted bus master attempts to write any of the sacu control regist ers, the access is aborted with an error termination and the registers remain unaffected. the processor core is connected to bus master 0 and is always treated as a truste d bus master. accordingly, mpr[0] is forced to 1 at reset. 10.5.3.2 peripheral access cont rol registers (pacr0?pacr8) access to several on-chip peripherals is controlled by shared periphera l access control re gisters. a single pacr defines the access level for each of the tw o modules. these modules only support operand reads and writes. each pacr follows the format illustrated in figure 10-8 . for a list of pacrs and the modules that they control, refer to table 10-11 . 76 432 0 field lock1 access_ctrl1 lock0 access_ctrl0 reset 0000_0000 r/w r/w address ipsbar + 0x24 + offset figure 10-8. peripheral access control register (pacr n ) table 10-9. pacr field descriptions bits name description 7 lock1 this bit, when set, prevents subs equent writes to accessctrl1. any attempted write to the pacr generates an error termin ation and the contents of the register are not affected. only a system reset clears this flag. 6?4 access_ctrl1 this 3-bit field defines the acce ss control for the given platform peripheral. the encodings for this field are shown in ta b l e 1 0 - 1 0 . 3 lock0 this bit, when set, prevents subs equent writes to accessctrl0. any attempted write to the pacr generates an error termin ation and the contents of the register are not affected. only a system reset clears this flag. 2?0 access_ctrl0 this 3-bit field defines the acce ss control for the given platform peripheral. the encodings for this field are shown in ta b l e 1 0 - 1 0 . table 10-10. pacr accessctrl bit encodings bits supervisor mode user mode 000 read/write no access 001 read no access 010 read read 011 read no access 100 read/write read/write 101 read/write read
system control module (scm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 10-15 preliminary at reset, these on-chip modules are configured to have only supervisor read/write access capabilities. if an instruction fetch access to any of these peripheral modu les is attempted, the ips bus cycle is immediately terminated with an error. 10.5.3.3 grouped peripheral access control registers (gpacr0 & gpacr1) the on-chip peripheral space starting at ipsbar is s ubdivided into sixteen 64-mbyte regions. each of the first two regions has a unique access cont rol register associated with it. the other fourteen regions are in reserved space; the access control registers for thes e regions are not implement ed. bits [29:26] of the address select the specific gpacrn to be used for a given reference within th e ips address space. these access control registers are 8 bits in width so that read, write, and execute attributes ma y be assigned to the given ips region. note the access control for modules with memory space protected by pacr0?pacr8 are determined by the pacr0?pacr8 settings. the access control is not affected by gpacr0, even though the modules are mapped in its 64-mbyte address space. 110 read/write read/write 111 no access no access table 10-11. peripheral access control registers (pacrs) ipsbar offset name modules controlled access_ctrl1 access_ctrl0 0x024 pacr0 scm ? 0x025 pacr1 ? dma 0x026 pacr2 uart0 uart1 0x027 pacr3 uart2 ? 0x028 pacr4 i 2 c qspi 0x029 ? ? ? 0x02a pacr6 dtim0 dtim1 0x02b pacr7 dtim2 dtim3 0x02c pacr8 intc0 ? 0x02d ? ? ? 0x02e ? ? ? table 10-10. pacr accessctrl bit encodings (continued) bits supervisor mode user mode
system control module (scm) mcf5213 reference manual, rev. 1.1 10-16 freescale semiconductor preliminary at reset, these on-chip modules are configured to have only supervisor read/write access capabilities. bit encodings for the access_ctrl fi eld in the gpacr are shown in table 10-13 . table 10-14 shows the memory space protected by the gpacrs a nd the modules mapped to these spaces. 76?43 0 field lock ? access_ctrl reset 0000_0000 read/write r/w r r/w address ipsbar + 0x030, ipsbar + 0x31 figure 10-9. gpacr register table 10-12. grouped peripheral access contro l register (gpacr) field descriptions bits name description 7 lock this bit, once set, prevents subsequent writ es to the gpacr. any attempted write to the gpacr generates an error termination and the contents of the regist er are not affected. only a system reset clears this flag. 6?4 ? reserved, should be cleared. 3?0 access_ctrl this 4-bit field defines the ac cess control for the given memory region. the encodings for this field are shown in table 10-13 . table 10-13. gpacr access_ctrl bit encodings bits supervisor mode user mode 0000 read / write no access 0001 read no access 0010 read read 0011 read no access 0100 read / write read / write 0101 read / write read 0110 read / write read / write 0111 no access no access 1000 read / write / execute no access 1001 read / execute no access 1010 read / execute read / execute 1011 execute no access 1100 read / write / execute read / write / execute 1101 read / write / execute read / execute 1110 read / write read 1111 read / write / execute execute
system control module (scm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 10-17 preliminary table 10-14. gpacr address space register space protected (ipsbar offset) modules protected gpacr0 0x0000_0000? 0x03ff_ffff ports, ccm, pmm, reset controller, clock, eport, wdog, pit0?pit3, qadc, gpta, gptb, flexcan, cfm (control) gpacr1 0x0400_0000? 0x07ff_ffff cfm (flash module?s backdoor access for programming or access by a bus master other than the core)
system control module (scm) mcf5213 reference manual, rev. 1.1 10-18 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 11-1 preliminary chapter 11 general purpose i/o module 11.1 introduction many of the pins associated with the external interf ace may be used for severa l different functions. their primary function is to provide an external memory interf ace to access off-chip resources. when not used for their primary function, many of the pins may be used as general-purpose digital i/o pins. in some cases, the pin function is set by the operating mode, a nd the alternate pin functions are not supported. the digital i/o pins are grouped into 8-bit ports. some ports do not use all eight bits. each port has registers that configure, monitor, and control the port pins. figure 11-1 is a block diagram of the mcf5213 ports. figure 11-1. general purpose i/o module block diagram ddata[3:0] / pdd[7:4] port qs port as port dd port ua port uc port tc port td pst[3:0] / pdd[3:0] sda / pas[1] / canrx / rxd2 scl / pas[0] / cantx/txd2 qspi_sck / pqs[2] / scl / rts1 qspi_din / pqs[1] / canrx / rxd1 qspi_dout / pqs[0] / cantx rxd0 dtin3 / ptc[3] / dtout3 / pwm6 dtin2 / ptc[2] / dtout2 / pwm4 dtin1 / ptc[1] / dtout1 / pwm2 dtin0 / ptc[0] / dtout0 / pwm0 cts1 / pub[3] / synca / rxd2 rts1 / pub[2] / syncb / txd2 rxd1 / pub[1] txd1 / pub[0] cts0 / pua[3] / canrx rts0 / pua[2] / cantx rxd0 / pua[1] txd0 / pua[0] cts2 / puc[3] rts2 / puc[2] rxd2 / puc[1] txd2 / puc[0] pwm7 / ptd[3] pwm5 / ptd[2] pwm3 / ptd[1] pwm1 / ptd[0] port ta gpt[3] / pta[3] / pwm7 gpt[2] / pta[2] / pwm5 gpt[1] / pta[1] / pwm3 gpt[0] / pta[0] / pwm1 port an an0 / pan[0] an1 / pan[1] an2 / pan[2] an3 / pan[3] an4 / pan[4] an5 / pan[5] an6 / pan[6] an7 / pan[7] port ub qspi_pcs0 / pqs[3] / sda / cts1 port nq irq1 / pnq[1] / synca / pwm1 irq2 / pnq[2] irq3 / pnq[3] irq4 / pnq[4] irq5 / pnq[5] irq6 / pnq[6] irq7 / pnq[7] qspi_pcs1 / pqs[4] qspi_pcs2 / pqs[5] qspi_pcs3 / pqs[6] / synca / syncb
general purpose i/o module mcf5213 reference manual, rev. 1.1 11-2 freescale semiconductor preliminary 11.2 overview the mcf5213 ports module controls the configuration for various external pins, including those used for: ? external bus accesses ? chip selects ? debug data ? processor status ? flexcan transmit/receive data ?i 2 c serial control ? qspi ? uart transmit/receive ? 32-bit dma timers 11.3 features the mcf5213 ports includes these distinctive features: ? control of primary function use on all ports ? digital i/o support for all ports ? registers for storing output pin data ? registers for controlling pin data direction ? registers for reading current pin state ? registers for setting and cleari ng output pin data registers 11.4 signal descriptions refer to chapter 2, ?signal descriptions ,? for more detailed information on the different signals and pins.
general purpose i/o module mcf5213 reference manual, rev. 1.1 freescale semiconductor 11-3 preliminary 11.5 memory map/register definition 11.5.1 ports memory map table 11-1 summarizes all the registers in the mcf5213 ports address space. table 11-1. mcf5213 ports module memory map offset 1 1 the register address is the sum of the ipsbar address and the base address offset. 31?24 23?16 15?8 7?0 access 2 2 s/u = supervisor or user mode access. user mode accesses to supervisor-only addresses have no effect and cause a cycle termination transfer error. port output data registers $0000 reserved s/u $0004 reserved s/u $0008 portnq portdd portan portas s/u $000c reserved portqs portta porttc s/u $0010 porttd portua portub portuc s/u port data direction registers $0014 reserved s/u $0018 reserved s/u $001c ddrnq ddrdd ddran ddras s/u $0020 reserved ddrqs ddrta ddrtc s/u $0024 ddrtd ddrua ddrub ddruc s/u port pin data/set data registers $0028 reserved s/u $002c reserved s/u $0030 portnqp/setnq portddp/setdd portanp/setan portasp/setas s/u $0034 reserved portqsp/setqs p orttap/setta porttcp/settc s/u $0038 porttdp/settd portuap/setu a portubp/setub portucp/setuc s/u port clear output data registers $003c reserved s/u $0040 reserved s/u $0044 clrnq clrdd clran clras s/u $0048 reserved clrqs clrta clrtc s/u $004c clrtd clrua clrub clruc s/u port pin assignment registers $0050 pnqpar pddpar panpar paspar s/u $0054 pqspar ptapar ptcpar s/u $0058 ptdpar puapar pubpar pucpar s/u $005c? $0074 reserved s/u port pad control registers $0078 psrr[31:0] s/u $007c pdsr[31:0] s/u
general purpose i/o module mcf5213 reference manual, rev. 1.1 11-4 freescale semiconductor preliminary 11.6 register descriptions 11.6.1 port output data registers (port n ) the port n registers store the data to be driven on the corresponding port n pins when the pins are configured for digital output. the port n registers with a full 8-bit implementation, are shown in figure 11-2 . the remaining port n registers use fewer than eight bits. their bit de finitions are shown in figure 11-3 , figure 11-4 , figure 11-5 , and figure 11-6 . the port n registers are read/write. at reset, all bits in the port n registers are set. reading a port n register returns the current valu es in the register, not the port n pin values. port n bits can be set by setting the port n register, or by setting the corresponding bits in the port n p/set n register. they can be cleared by clearing the port n register, or by clearing the corresponding bits in the clr n register.
general purpose i/o module mcf5213 reference manual, rev. 1.1 freescale semiconductor 11-5 preliminary figure 11-2. port n ? port output data registers [7:0] figure 11-3. port n ? port output data registers [3:0] figure 11-4. port n ? port output data registers [6:0] figure 11-5. port n ? port output data registers [7:1] figure 11-6. port n ? port output data registers [1:0] portn port n output data bits. drive 1 when port n pin is digital output drive 0 when port n pin is digital output base + $0009 (portdd) base + $000a (portan) 7 6 5 4 3 2 1 0 field port n 7 port n 6 port n 5 port n 4 port n 3 port n 2 port n 1 port n 0 reset 1111_1111 r/w r/w base + $000e (portta) base + $000f (porttc) base + $0010 (porttd) base + $0011 (portua) base + $0012 (portub) base + $0013 (portuc) 7 6 5 4 3 2 1 0 field ? ? ? ? port n 3 port n 2 port n 1 port n 0 reset 0000_1111 r/w r r/w base + $000d (portqs) 7 6 5 4 3 2 1 0 field ? port n 6 port n 5 port n 4 port n 3 port n 2 port n 1 port n 0 reset 0111_1111 r/w r r/w base + $0008 (portnq) 7 6 5 4 3 2 1 0 field port n 7 port n 6 port n 5 port n 4 port n 3 port n 2 port n 1 ? reset 1111_1110 r/w r/w r base + $000b (portas) 7 6 5 4 3 2 1 0 field ? ? ? ? ? ? port n 1 port n 0 reset 0000_0011 r/w r r/w
general purpose i/o module mcf5213 reference manual, rev. 1.1 11-6 freescale semiconductor preliminary 11.6.2 port data direction registers (ddr n) the ddr n registers control the direction of the port n pin drivers when the pins are configured for digital i/o. the ddr n registers are read/write. at reset, all bits in the ddr n registers are cleared to 0s. setting any bit in a ddr n register configures the corresponding port n pin as an output. clearing any bit in a ddr n register configures the corresponding pin as an input.
general purpose i/o module mcf5213 reference manual, rev. 1.1 freescale semiconductor 11-7 preliminary figure 11-7. ddr n ? port data direction registers [7:0] figure 11-8. ddr n ? port data direction registers [3:0] figure 11-9. ddr n ? port data direction registers [6:0] figure 11-10. ddr n ? port data direction registers [7:1] figure 11-11. ddr n ? port data direction registers [1:0] ddr n port n data direction bits. 1 = port n pin configured as output 0 = port n pin configured as input base + $001d (ddrdd) base + $001e (ddran) 7 6 5 4 3 2 1 0 field ddr n 7 ddr n 6 ddr n 5 ddr n 4 ddr n 3 ddr n 2 ddr n 1 ddr n 0 reset 0000_0000 r/w r/w base + $0022 (ddrta) base + $0023 (ddrtc) base + $0024 (ddrtd) base + $0025 (ddrua) base + $0026 (ddrub) base + $0027 (ddruc) 7 6 5 4 3 2 1 0 field ? ? ? ? ddr n 3 ddr n 2 ddr n 1 ddr n 0 reset 0000_0000 r/w r r/w base + $0021 (ddrqs) 7 6 5 4 3 2 1 0 field ? ddrn6 ddr n 5 ddr n 4 ddr n 3 ddr n 2 ddr n 1 ddr n 0 reset 0000_0000 r/w r r/w base + $001c (ddrnq) 7 6 5 4 3 2 1 0 field ddr n 7 ddr n 6 ddr n 5 ddr n 4 ddr n 3 ddr n 2 ddr n 1 ? reset 0000_0000 r/w r/w r base + $001f (ddras) 7 6 5 4 3 2 1 0 field ? ? ? ? ? ? ddr n 1 ddr n 0 reset 0000_0000 r/w r r/w
general purpose i/o module mcf5213 reference manual, rev. 1.1 11-8 freescale semiconductor preliminary 11.6.3 port pin data/set data registers (port n p/set n ) the port n p/set n registers reflect the current pin states and control the sett ing of output pins when the pin is configured for digital i/o. the port n p/set n registers are read/write. at reset, the bits in the port n p/set n registers are set to the current pin states. reading a port n p/set n register returns the cu rrent state of the port n pins. writing 1s to a port n p/set n register sets the corre sponding bits in the port n register. writing 0s has no effect.
general purpose i/o module mcf5213 reference manual, rev. 1.1 freescale semiconductor 11-9 preliminary figure 11-12. port n p/set n ? port pin data/set data registers [7:0] figure 11-13. port n p/set n ? port pin data/set data registers [3:0] figure 11-14. port n p/set n ? port pin data/set data registers [6:0] figure 11-15. port n p/set n ? port pin data/set data registers [7:1] figure 11-16. port n p/set n ? port pin data/set data registers [1:0] port n p/set n port n pin data/set data bits. 1 = port n pin state is 1 (read); set corresponding port n bit (write) 0 = port n pin state is 0 (read) base + $0031 (portdd/setdd) base + $0032 (portan/setan) 7 6 5 4 3 2 1 0 field port n p7 port n p6 port n p5 port n p4 port n p3 port n p2 port n p1 port n p0 reset 1111_1111 r/w r/w base + $0036 (portta/setta) base + $0037 (porttc/settc) base + $0038 (porttd/settd) base + $0039 (portua/setua) base + $003a (portub/setub) base + $003b (portuc/setuc) 7 6 5 4 3 2 1 0 field ? ? ? ? port n p3 port n p2 port n p1 port n p0 reset 0000_1111 r/w r r/w base + $0035 (portqs/setqs) 7 6 5 4 3 2 1 0 field ? port n p6 port n p5 port n p4 port n p3 port n p2 port n p1 port n p0 reset 0111_1111 r/w r r/w base + $0030 (portnq/setnq) 7 6 5 4 3 2 1 0 field port n p7 port n p6 portnp5 port n p4 port n p3 port n p2 port n p1 ? reset 1111_1110 r/w r/w r base + $0033 (portas/setas) 7 6 5 4 3 2 1 0 field ? ? ? ? ? ? port n p1 port n p0 reset 0000_0011 r/w r r/w
general purpose i/o module mcf5213 reference manual, rev. 1.1 11-10 freescale semiconductor preliminary 11.6.4 port clear output data registers (clr n ) writing 0s to a clr n register clears the corr esponding bits in the port n register. writing 1s has no effect. reading the clr n register returns 0s. the clr n registers are read/write. figure 11-17. clrn ? port clear output data registers [7:0] figure 11-18. clr n ? port clear output data registers [3:0] figure 11-19. clr n ? port clear output data registers [6:0] figure 11-20. clr n ? port clear output data registers [7:1] figure 11-21. clr n ? port clear output data registers [1:0] base + $0045 (clrdd) base + $0046 (clran) 7 6 5 4 3 2 1 0 field clr n 7 clr n 6 clr n 5 clr n 4 clr n 3 clr n 2 clr n 1 clr n 0 reset 0000_0000 r/w r/w base + $004a (clrta) base + $004b (clrtc) base + $004c (clrtd) base + $004d (clrua) base + $004e (clrub) base + $004f (clruc) 7 6 5 4 3 2 1 0 field ? ? ? ? clr n 3 clr n 2 clr n 1 clr n 0 reset 0000_0000 r/w r r/w base + $0049 (clrqs) 7 6 5 4 3 2 1 0 field ? clr n 6 clr n 5 clr n 4 clr n 3 clr n 2 clr n 1 clr n 0 reset 0000_0000 r/w r r/w base + $0044 (clrnq) 7 6 5 4 3 2 1 0 field clr n 7 clr n 6 clr n 5 clr n 4 clr n 3 clr n 2 clr n 1 ? reset 0000_0000 r/w r/w r base + $0047 (clras) 7 6 5 4 3 2 1 0 field ? ? ? ? ? ? clr n 1 clr n 0 reset 0000_0000 r/w r r/w
general purpose i/o module mcf5213 reference manual, rev. 1.1 freescale semiconductor 11-11 preliminary clr n port n clear output data register bits. 1 = never returned for reads; no effect for writes 0 = always returned for re ads; clears corresponding port n bit for writes 11.6.5 pin assignment registers all pin assignment registers are read/write. if multiple pins are configured for the one function then the result is undefined. 11.6.5.1 dual function pin assignment registers the dual function pin assignment regist ers allow each pin controlled by each register bit to be configured between the gpio function and the primary function. figure 11-22. p n pa r ? po r t n pin assignment registers dual [7:0] figure 11-23. p n pa r ? po r t n pin assignment registers dual [3:0] p n par port n pin assignment register bits. 1 = pin assumes the primary function for that pin 0 = pin assumes the gpio function for that pin base + $0051 (pddpar) base + $0052 (panpar) 7 6 5 4 3 2 1 0 field p n par7 p n par6 p n par5 p n par4 p n par3 p n par2 p n par1 p n par0 reset 0000_0000 r/w r/w base + $0058 (ptdpar) base + $005b (pucpar) 7 6 5 4 3 2 1 0 field ? ? ? ? p n par3 p n par2 p n par1 p n par0 reset 0000_0000 r/w r r/w
general purpose i/o module mcf5213 reference manual, rev. 1.1 11-12 freescale semiconductor preliminary 11.6.5.2 quad function pin assignment registers the quad function pin assignment regist ers allow each pin controlled by each register bit to be configured between the gpio function, primary function, alte rnate 1 function and the alternate 2 function. figure 11-24. p n pa r ? por t n pin assignment registers quad [13:0] figure 11-25. p n par ? port n pin assignment registers quad [3:0] figure 11-26. p n par ? port n pin assignment registers quad [7:0] p n par port n pin assignment register bits. base + $0054 (pqspar) 15 14 13 12 11 10 9 8 field ? ? p n par6 p n par5 p n par4 reset 0000_0000 r/w r r/w 7 6 5 4 3 2 1 0 field p n par3 p n par2 p n par1 p n par0 reset 0000_0000 r/w r/w base + $0053 (paspar) 7 6 5 4 3 2 1 0 field ? ? ? ? p n par1 p n par0 reset 0000_0000 r/w r r/w base + $0056 (ptapar) base + $0057 (ptcpar) base + $0059 (puapar) base + $005a (pubpar) 7 6 5 4 3 2 1 0 field p n par3 p n par2 p n par1 p n par0 reset 0000_0000 r/w r/w table 11-2. double bit pin assignment register bit bit value pin assignment 00 gpio function 01 primary function 10 alternate 1 function 11 alternate 2 function
general purpose i/o module mcf5213 reference manual, rev. 1.1 freescale semiconductor 11-13 preliminary 11.6.5.3 port nq pin assignment register the port nq pin assignment register contains both quad function (for irq 1 ) and dual function pin assignment controls. refer to the prev ious two sections for the encodings for the different fields. note that the reset value of the pnqpar register defaults to the primary function (irq ) instead of gpio. figure 11-27. pnqpar ? port nq pin assignment register 11.6.6 pad control registers 11.6.6.1 pin slew rate register the pin slew rate register is read/w rite and each bit resets to logic 0. . figure 11-28. pssr ? pin slew rate register [31:0] pssr pin slew rate register control bits. 1 = pin is configured for slow slew rate (delay is approximate ly 10 times slower). 0 = pin is configured for fast slew rate. 11.6.6.2 pin drive strength register the pin drive strength regist er is read/write and each bit resets to logic 0 in single chip mode (mcf5213 default) and logic 1 in ezport and fast mode. base + $0050 (pnqpar) 7 6 5 4 3 2 1 0 field pnqpar7 pnqpar6 pnqpar5 pnqpar4 pnqpar3 pnqpar2 pnqpar1 reset 1111_1101 r/w r/w base + $0078 (psrr) 31 30 29 28 27 26 25 24 field psrr31 pssr30 pssr29 pssr28 pssr27 pssr26 pssr25 pssr24 reset 1 1 each bit resets to logic 0 in single chip mode and logic 1 in ezport/fast mode. r/w r/w 23 22 21 20 19 18 17 16 field pssr23 pssr22 pssr21 pssr20 pssr19 pssr18 pssr17 pssr16 reset 1 r/w r/w 15 14 13 12 11 10 9 8 field pssr15 pssr14 pssr13 pssr12 pssr11 pssr10 pssr9 pssr8 reset 1 r/w r/w 7 6 5 4 3 2 1 0 field pssr7 pssr6 pssr5 pssr4 pssr3 pssr2 pssr1 pssr0 reset 1 r/w r/w
general purpose i/o module mcf5213 reference manual, rev. 1.1 11-14 freescale semiconductor preliminary . figure 11-29. pdsr ? pin drive strength register [31:0] pdsr pin drive strength regi ster control bits. 1 = pin is configured for high drive strength (10ma). 0 = pin is configured for low drive strength (2ma). 11.7 ports interrupts the ports module does not generate interrupt requests. base + $007c (pdsr) 31 30 29 28 27 26 25 24 field pdsr31 pdsr30 pdsr29 pdsr28 pdsr27 pdsr26 pdsr25 pdsr24 reset 1 1 each bit resets to logic 0 in single chip mode and logic 1 in ezport/fast mode. r/w r/w 23 22 21 20 19 18 17 16 field pdsr23 pdsr22 pdsr21 pdsr20 pdsr19 pdsr18 pdsr17 pdsr16 reset 1 r/w r/w 15 14 13 12 11 10 9 8 field pdsr15 pdsr14 pdsr13 pdsr12 pdsr11 pdsr10 pdsr9 pdsr8 reset 1 r/w r/w 7 6 5 4 3 2 1 0 field pdsr7 pdsr6 pdsr5 pdsr4 pdsr3 pdsr2 pdsr1 pdsr0 reset 1 r/w r/w
mcf5213 reference manual, rev. 1.1 freescale semiconductor 12-1 preliminary chapter 12 interrupt controller module this section details the functionality for the interrupt controller. the general fe atures of the interrupt controller include: ? 57 interrupt sources, organized as: ? 50 fully-programmabl e interrupt sources ? 7 fixed-level interrupt sources ? each of the 57 sources has a unique interrupt control register (icr nx ) to define the software-assigned levels and pr iorities within the level ? unique vector number for each interrupt source ? ability to mask any individual interrupt source, plus globa l mask-all capability ? supports both hardware and softwa re interrupt acknowledge cycles ? ?wake-up? signal from low-power stop modes the 57 fully-programmable and seven fixed-level interrupt sources for th e interrupt controller handle the complete set of interrupt sources from all of the m odules on the device. this section describes how the interrupt sources are mapped to the interrupt co ntroller logic and how in terrupts are serviced. 12.1 68k/coldfire interrupt architecture overview before continuing with the specifics of the interrupt controller, a brief review of the inte rrupt architecture of the 68k/coldfire fa mily is appropriate. the interrupt architecture of coldfire is exactly th e same as the m68000 family , where there is a 3-bit encoded interrupt priority level sent from the interrupt contro ller to the core, providi ng 7 levels of interrupt requests. level 7 represents the highe st priority interrupt level, while level 1 is the lowest priority. the processor samples for active interr upt requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask va lue (i) contained in bits 10:8 of the machine?s st atus register (sr). if the priority level is grea ter than the sr[i] field at the sample point, the processor suspends normal instruction execution and initiates interrupt exce ption processing. level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the sr[i] fi eld. for correct operation, the coldfire require that, once asserted, the interrupt source rema in asserted until explic itly disabled by the in terrupt service routine. during the interrupt exception processing, the cpu ente rs supervisor mode, disables trace mode and then fetches an 8-bit vector from the in terrupt controller. this byte-sized operand fetch is known as the interrupt acknowledge (iack) cycl e with the coldfire implementation using a special encoding of the transfer type and transfer modifier attri butes to distinguish this da ta fetch from a ?normal? memory access. the fetched data provides an index into the ex ception vector table which contains 256 addresses, each pointing to the beginning of a specific exception se rvice routine. in particular, ve ctors 64 - 255 of the exception vector table are reserved for user interr upt service routines. the first 64 ex ception vectors are reserved for the processor to handle reset, error conditions (access, addr ess), arithmetic faults, syst em calls, etc. once the interrupt vector number has been re trieved, the processor continues by creating a stack frame in memory. for coldfire, all exception stack frame s are 2 longwords in length, and c ontain 32 bits of vector and status register data, along with th e 32-bit program counter value of the instruction that was interrupted (see
interrupt controller module mcf5213 reference manual, rev. 1.1 12-2 freescale semiconductor preliminary section 2.6, ?exception st ack frame definition ? for more information on the stack frame format). after the exception stack frame is stored in memory, the pr ocessor accesses the 32-bit po inter from the exception vector table using the vector number as the offset, and then jumps to that address to begin execution of the service routine. after the status regi ster is stored in the exception stack frame, the sr[i] mask field is set to the level of the interrupt bei ng acknowledged, effectively masking that level and all lower values while in the service routine. for many peri pheral devices, the processing of th e iack cycle directly negates the interrupt request, while other devices require that reque st to be explicitly nega ted during the processing of the service routine. for this device, , the pr ocessing of the interrupt acknowledge cy cle is fundamentally different than previous 68k/coldfire cores. in the new approach, al l iack cycles are directly handled by the interrupt controller, so the requesting peripheral device is not accessed during the iack. as a result, the interrupt request must be explicitly clea red in the peripheral during the in terrupt service routine. for more information, see section 12.1.1.3, ?interrupt vector determination .? unlike the m68000 family, all coldfire processors guarantee that the first instruction of the service routine is executed before sampling for interrupts is resumed. by making this initial instru ction a load of the sr, interrupts can be safely disabled, if required. during the execution of the service ro utine, the appropriate actions mu st be performed on the peripheral to negate the interrupt request. for more information on ex ception proces sing, see the coldfire programmer?s reference manual at http://www.freescale.com/coldfire . 12.1.1 interrupt controlle r theory of operation to support the interrupt architecture of the 68k/c oldfire programming model, the combined 63 interrupt sources are organized as 7 levels, with each level s upporting up to 9 prioritize d requests. consider the priority structure within a single interrupt level (from highest to lowest priority) as shown in table 12-1 . the level and priority is fully pr ogrammable for all sources except in terrupt sources 1?7. interrupt source 1?7 (from the edgeport module) are fixed at the corr esponding level?s midpoint priority. thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single interrupt level. the ?fixed? interrupt source is hardwired to the given level, and represents the mid- point of the priority within the level. for the table 12-1. interrupt priority within a level icr[2:0] priority interrupt sources 111 7 (highest) 8-63 110 6 8-63 101 5 8-63 100 4 8-63 ? fixed midpoint priority 1-7 011 3 8-63 010 2 8-63 001 1 8-63 000 0 (lowest) 8-63
interrupt controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 12-3 preliminary fully-programmable interrupt sources, the 3-bit level and the 3-bit priori ty within the level are defined in the 8-bit interrupt control register (icr nx ). the operation of the interrupt controller can be br oadly partitioned into three activities: ? recognition ? prioritization ? vector determination during iack 12.1.1.1 interrupt recognition the interrupt controller continuously examines the request sources and the in terrupt mask register to determine if there are active requests. this is the recognition phase. 12.1.1.2 interrupt prioritization as an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit decoded priority level (irq [7:1]) is driven out of the interrupt controller. 12.1.1.3 interrupt vector determination once the core has sampled for pending interrupts a nd begun interrupt exception processing, it generates an interrupt acknowledge cycle (iack). the iack transfer is treated as a memory-mapped byte read by the processor, and routed to the appr opriate interrupt controller. next, th e interrupt controller extracts the level being acknowledged from address bits[4:2], and then de termines the highest pr iority interrupt request active for that level, and returns th e 8-bit interrupt vector for that reque st to complete the cycle. the 8-bit interrupt vector is formed using the following algorithm: for intc0, vector_number = 64 + interrupt source number recall vector_numbers 0 - 63 are reserved for the coldfi re processor and its intern al exceptions. thus, the following mapping of bit positions to vector numbers applies for the intc0: if interrupt source 1 is active and acknowledged, then vector_number = 65 if interrupt source 2 is active and acknowledged, then vector_number = 66 ... if interrupt source 8 is active and acknowledged, then vector_number = 72 if interrupt source 9 is active and acknowledged, then vector_number = 73 ... if interrupt source 62 is active and acknowledged, then vector_number = 126 the net effect is a fixed mapping be tween the bit position within the s ource to the actual interrupt vector number. if there is no active interrupt source for the given level, a special ?spurious interrupt? vector (vector_number = 24) is return ed and it is the responsibility of th e service routine to handle this error situation. note this protocol implies the interrupting peripheral is not accesse d during the acknowledge cycle since the interrupt controller completely services the ac knowledge. this means the in terrupt source must be explicitly disabled in the interrupt service routine. this design provide s unique vector capability for all interrupt requests, regardless of the ?complexity? of the peripheral device.
interrupt controller module mcf5213 reference manual, rev. 1.1 12-4 freescale semiconductor preliminary 12.2 memory map the register programming model for the interrupt controllers is memo ry-mapped to a 256-byte space. in the following discussion, ther e are a number of program- visible registers greater th an 32 bits in size. for these control fields, the physical regi ster is partitioned into two 32-bit values: a regi ster ?high? (the upper longword) and a regi ster ?low? (the lower longword). the nomenclature h and l is used to reference these values. the registers and their lo cations are defined in table 12-3 . the offsets listed star t from the base address for each interrupt controller. the base addresse s for the interrupt controllers are listed below: table 12-2. interrupt controller base addresses interrupt controller number base address intc ipsbar + 0xc00 table 12-3. interrupt controller memory map module offset bits[31:24] bit s[23:16] bits[15:8] bits[7:0] ipsbar + 0x0c00 interrupt pending register high (iprh), [63:32] ipsbar + 0x0c04 interrupt pendin g register low (iprl), [31:1] ipsbar + 0x0c08 interrupt mask re gister high (imrh), [63:32] ipsbar + 0x0c0c interrupt mask register low (imrl), [31:0] ipsbar + 0x0c10 interrupt force register high (intfrch), [63:32] ipsbar + 0x0c14 interrupt force r egister low (intfrcl), [31:1] ipsbar + 0x0c18 irlr[7:1] iacklpr[7:0] reserved ipsbar + 0x0c1c - ipsbar + 0x0c3c reserved ipsbar + 0x0c40 reserved icr01 icr02 icr03 ipsbar + 0x0c44 i cr04 icr05 icr06 icr07 ipsbar + 0x0c48 i cr08 icr09 icr10 icr11 ipsbar + 0x0cx4c i cr12 icr13 icr14 icr15 ipsbar + 0x0c50 i cr16 icr17 icr18 icr19 ipsbar + 0x0c54 i cr20 icr21 icr22 icr23 ipsbar + 0x0c58 i cr24 icr25 icr26 icr27 ipsbar + 0x0c5c icr28 icr29 icr30 icr31 ipsbar + 0x0c60 i cr32 icr33 icr34 icr35 ipsbar + 0x0c64 i cr36 icr37 icr38 icr39 ipsbar + 0x0c68 i cr40 icr41 icr42 icr43 ipsbar + 0x0c6c icr44 icr45 icr46 icr47 ipsbar + 0x0c70 i cr48 icr49 icr50 icr51 ipsbar + 0x0c74 i cr52 icr53 icr54 icr55
interrupt controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 12-5 preliminary 12.3 register descriptions 12.3.1 interrupt pending registers (iprh n , iprl n ) the iprh n and iprl n registers, figure 12-1 and figure 12-2 , are each 32 bits in si ze, and provide a bit map for each interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given source. the state of the interr upt mask register doe s not affect the ipr n . the ipr n is cleared by reset. the ipr n is a read-only register, so any attempted write to this re gister is ignored. bit 0 is not implemented and reads as a zero. ipsbar + 0x0c78 i cr56 icr57 icr58 icr59 ipsbar + 0x0c7c icr60 icr61 icr62 icr63 ipsbar + 0x0c80 ipsbar + 0x0cdc reserved ipsbar + 0x0ce0 swiack reserved ipsbar + 0x0ce4 l1iack reserved ipsbar + 0x0ce8 l2iack reserved ipsbar + 0x0cec l3iack reserved ipsbar + 0x0cf0 l4iack reserved ipsbar + 0x0cf4 l5iack reserved ipsbar + 0x0cf8 l6iack reserved ipsbar + 0x0cfc l7iack reserved 31 16 field int[63:48] reset 0000_0000_0000_0000 r/w r 15 0 field int[47:32] reset 0000_0000_0000_0000 r/w r ipsbar + 0xc00 figure 12-1. interrupt pending register high (iprh n ) table 12-3. interrupt controller memory map (continued) module offset bits[31:24] bit s[23:16] bits[15:8] bits[7:0]
interrupt controller module mcf5213 reference manual, rev. 1.1 12-6 freescale semiconductor preliminary . 12.3.2 interrupt mask register (imrh n , imrl n ) the imrh n and imrl n registers are each 32 bits in size and provide a bit map for each interrupt to allow the request to be disabled (1 = disable the request, 0 = enable the request). the imr n is set to all ones by reset, disabling all inte rrupt requests. the imr n can be read and written. a writ e that sets bit 0 of the imr forces the other 63 bits to be set, disabling all inte rrupt sources, and providing a global mask-all capability. table 12-4. iprh n field descriptions bits name description 31?0 int interrupt pending. each bit corresponds to an interrupt source. the corresponding imrh n bit determines whether an interrupt condition can gener ate an interrupt. at every system clock, the iprh n samples the signal generated by the interrupting source. the corresponding iprh n bit reflects the state of the interrupt signal even if the corresponding imrh n bit is set. 0 the corresponding interrupt source does not have an interrupt pending 1 the corresponding interrupt source has an interrupt pending 31 16 field int[31:16] reset 0000_0000_0000_0000 r/w r 15 10 field int[16:1] ? reset 0000_0000_0000_0000 r/w r ipsbar + 0xc04 figure 12-2. interrupt pending register low (iprl n ) table 12-5. iprl n field descriptions bits name description 31?1 int interrupt pending. each bit corresponds to an interrupt source. the corresponding imrl n bit determines whether an interrupt condition can gener ate an interrupt. at every system clock, the iprl n samples the signal generated by the interrupting source. the corresponding iprl n bit reflects the state of the interrupt signal even if the corresponding imrl n bit is set. 0 the corresponding interrupt source does not have an interrupt pending 1 the corresponding interrupt source has an interrupt pending 0 ? reserved, should be cleared.
interrupt controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 12-7 preliminary . . 31 16 field int_mask[63:48] reset 1111_1111_1111_1111 r/w r/w 15 0 field int_mask[47:32] reset 1111_1111_1111_1111 r/w r/w ipsbar + 0xc08 figure 12-3. interrupt mask register high (imrh n ) table 12-6. imrh n field descriptions bits name description 31?0 int_mask interrupt mask. each bit corresponds to an interrupt source. the corresponding imrh n bit determines whether an interrupt condition can generate an interrupt. the corresponding iprh n bit reflects the state of the interrupt signal even if the corresponding imrh n bit is set. 0 the corresponding interrupt source is not masked 1 the corresponding interrupt source is masked 31 16 field int_mask[31:16] reset 1111_1111_1111_1111 r/w r/w 15 10 field int_mask[16:1] maskall reset 1111_1111_1111_1111 r/w r/w ipsbar + 0xc0c figure 12-4. interrupt mask register low (imrl n )
interrupt controller module mcf5213 reference manual, rev. 1.1 12-8 freescale semiconductor preliminary note if an interrupt source is being mask ed in the interrupt controller mask register (imr) or a modul e?s interrupt mask regi ster while the interrupt mask in the status register (sr[i]) is set to a value lower than the interrupt?s level, a spurious interrupt may occur. this is because by the time the status register acknowledges this interrupt, the interrupt has been masked. a spurious interrupt is generated be cause the cpu cannot determine the interrupt source. to avoid this situat ion for interrupts sources with levels 1-6, first write a higher level interrupt mask to the status register, before setting the mask in the imr or the module?s interrupt mask register. after the mask is set, return the interrupt mask in the status regi ster to its previous value. since level seven in terrupts cannot be disabled in the status register prior to masking, use of the imr or module interrupt mask registers to disable level seven interrupts is not recommended. 12.3.3 interrupt force registers (intfrch n , intfrcl n ) the intfrch n and intfrcl n registers are each 32 bi ts in size and provide a mechanism to allow software generation of interrupt s for each possible source for func tional or debug purposes. the system design may reserve one or more sources to allow so ftware to self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate intfrc n register. the assertion of an interrupt request via the intfrc n register is not affected by the interrupt mask register. the intfrc n register is cleared by reset. table 12-7. imrl n field descriptions bits name description 31?1 int_mask interrupt mask. each bit corresponds to an interrupt source. the corresponding imrl n bit determines whether an interrupt condition can generate an interrupt. the corresponding iprl n bit reflects the state of the interrupt signal even if the corresponding imrl n bit is set. 0 the corresponding interrupt source is not masked 1 the corresponding interrupt source is masked 0 maskall mask all interrupts. setting this bit will force the other 63 bits of the imrh n and imrl n to ones, disabling all interrupt sources, and providing a global mask-all capability.
interrupt controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 12-9 preliminary . 31 16 field intfrch[63:48] reset 0000_0000_0000_0000 r/w r/w 15 0 field intfrch[47:32] reset 0000_0000_0000_0000 r/w r/w ipsbar + 0xc10 figure 12-5. interrupt force register high (intfrch n ) table 12-8. intfrch n field descriptions bits name description 31?0 intfrc interrupt force. allows software generation of interrupts for each possible source for functional or debug purposes. 0 no interrupt forced on corresponding interrupt source 1 force an interrupt on the corresponding source 31 16 field intfrcl[31:16] reset 0000_0000_0000_0000 r/w r/w 15 10 field intfrcl[16:1] ? reset 0000_0000_0000_0000 r/w r/w ipsbar + 0xc14 figure 12-6. interrupt force register low (intfrcl n ) table 12-9. intfrcl n field descriptions bits name description 31?1 intfrc interrupt force. allows software generation of interrupts for each possible source for functional or debug purposes. 0 no interrupt forced on corresponding interrupt source 1 force an interrupt on the corresponding source 0 ? reserved, should be cleared.
interrupt controller module mcf5213 reference manual, rev. 1.1 12-10 freescale semiconductor preliminary 12.3.4 interrupt request level register (irlr n ) this 7-bit register is updated each machine cycle a nd represents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. 12.3.5 interrupt acknowledge level and priority register (iacklpr n ) each time an iack is performed, the interrupt contro ller responds with the v ector number of the highest priority source within th e level being acknowledged. in addition to providing th e vector number directly for the byte-sized iack read, this 8-bit register is al so loaded with information about the interrupt level and priority being acknowledged. this register provides the asso ciation between the acknowledged ?physical? interrupt request number and the program med interrupt level/priority. the contents of this read-only register are described in figure 12-8 and table 12-11 . 7 210 field irq[7:1] ? reset 0000_0000 r/w r address ipsbar + 0xc18 figure 12-7. interrupt request (ir n ) table 12-10. irq n field descriptions bits name description 7?1 irq interrupt requests. represents the prioritized active interrupts for each level. 0 there are no active interrupts at this level 1 there is an active interrupt at this level 0?reserved 76 43 0 field ? level pri reset 0000_0000 r/w r address ipsbar + 0xc19 figure 12-8. iack level and priority register (iacklpr n ) table 12-11. iacklpr n field descriptions bits name description 7?reserved
interrupt controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 12-11 preliminary 12.3.6 interrupt control register (icr nx , ( x = 1, 2,..., 63)) each icr nx specifies the interrupt level (1-7) and the priority within the level (0-7). all icr nx registers can be read, but only icr n 8 to icr n 63 can be written. it is software?s responsibility to program the icr nx registers with unique and non-overla pping level and priority definiti ons. failure to program the icr nx registers in this manner can result in undefined behavior. if a specif ic interrupt request is completely unused, the icr nx value can remain in its reset (and disabled) state. 12.3.6.1 interrupt sources table 10-13 lists the interrupt sources fo r each interrupt request line 6?4 level interrupt level. represents the interrupt level currently being acknowledged. 3?0 pri interrupt priority. represents the priority within the interrupt level of the interrupt currently being acknowledged. 0 priority 0 1 priority 1 2 priority 2 3 priority 3 4 priority 4 5 priority 5 6 priority 6 7 priority 7 8 mid-point priority associated with the fixed level interrupts only 765320 field ? il ip reset 0000_0000 r/w r/w (read only for icr n 1-icr n 7) address see table 12-2 and ta b l e 1 2 - 3 for register offsets figure 12-9. interrupt control register (icr nx ) table 12-12. icr nx field descriptions bits name description 7?6 ? reserved, should be cleared. 5?3 il interrupt level. indicates the interrupt level assigned to each interrupt input. 2?0 ip interrupt priority. indicates the interrupt priority for internal modules within the interrupt-level assignment. 000b represents the lowest priority and 111b represents the highest. for the fixed level interrupt sources, the priority is fixed at the midpoi nt for the level, and the ip field will always read as 000b. table 12-11. iacklpr n field descriptions (continued) bits name description
interrupt controller module mcf5213 reference manual, rev. 1.1 12-12 freescale semiconductor preliminary table 12-13. interrupt source assignment for interrupt controller 0 source module flag source description flag clearing mechanism 1 eport epf1 edge port flag 1 write epf1 = 1 2 epf2 edge port flag 2 write epf2 = 1 3 epf3 edge port flag 3 write epf3 = 1 4 epf4 edge port flag 4 write epf4 = 1 5 epf5 edge port flag 5 write epf5 = 1 6 epf6 edge port flag 6 write epf6 = 1 7 epf7 edge port flag 7 write epf7 = 1 8 scm swti software watchdog timeout cleared when service complete. 9 dma done dma channel 0 transfer complete write done = 1 10 done dma channel 1 transfer complete write done = 1 11 done dma channel 2 transfer complete write done = 1 12 done dma channel 3 transfer complete write done = 1 13 uart0 int uart0 interrupt automatically cleared 14 uart1 int uart1 interrupt automatically cleared 15 uart2 int uart2 interrupt automatically cleared 16 not used (reserved) 17 i 2 c iif i 2 c interrupt write iif = 0 18 qspi int qspi interrupt write 1 to appropriate qir bit 19 dtim0 int dtim0 interrupt write 1 to appropriate dter0 bit 20 dtim1 int dtim1 interrupt write 1 to appropriate dter1 bit 21 dtim2 int dtim2 interrupt write 1 to appropriate dter2 bit 22 dtim3 int dtim3 interrupt write 1 to appropriate dter3 bit
interrupt controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 12-13 preliminary 23 flexcan buf0i message buffer 0 interrupt write 1 to buf0i after reading as 1 24 buf1i message buffer 1 interrupt write 1 to buf1i after reading as 1 25 buf2i message buffer 2 interrupt write 1 to buf2i after reading as 1 26 buf3i message buffer 3 interrupt write 1 to buf3i after reading as 1 27 buf4i message buffer 4 interrupt write 1 to buf4i after reading as 1 28 buf5i message buffer 5 interrupt write 1 to buf5i after reading as 1 29 buf6i message buffer 6 interrupt write 1 to buf6i after reading as 1 30 buf7i message buffer 7 interrupt write 1 to buf7i after reading as 1 31 buf8i message buffer 8 interrupt write 1 to buf8i after reading as 1 32 buf9i message buffer 9 interrupt write 1 to buf9i after reading as 1 33 buf10i message buffer 10 interrupt write 1 to buf10i after reading as 1 34 buf11i message buffer 11 interrupt write 1 to buf11i after reading as 1 35 buf12i message buffer 12 interrupt write 1 to buf12i after reading as 1 36 buf13i message buffer 13 interrupt write 1 to buf13i after reading as 1 37 buf14i message buffer 14 interrupt write 1 to buf14i after reading as 1 38 buf15i message buffer 15 interrupt write 1 to buf15i after reading as 1 39 err_int error interrupt read reported error bits in esr or write 0 to err_int 40 boff_int bus-off interr upt write 0 to boff_int 41 gpt tof timer overflow write tof = 1 or access timcnth/l if tffca = 1 42 paif pulse accumulator input write paif = 1 or access pac if tffca = 1 43 paovf pulse accumulator overflow write paovf = 1 or access pac if tffca = 1 44 c0f timer channel 0 write c0f = 1 or access ic/oc if tffca = 1 45 c1f timer channel 1 write 1 to c1f or access ic/oc if tffca = 1 46 c2f timer channel 2 write 1 to c2f or access ic/oc if tffca = 1 47 c3f timer channel 3 write 1 to c3f or access ic/oc if tffca = 1 48 pmm lvdf lvd write lvdf = 1 49 adc adca adca conversion complete write 1 to eosi0 50 adcb adcb conversion complete write 1 to eosi1 51 adcint adc interrupt wrte 1 to zci, llmti and hlmti 52 not used (reserved) 53 not used (reserved) table 12-13. interrupt source assignment for interrupt controller 0 (continued) source module flag source description flag clearing mechanism
interrupt controller module mcf5213 reference manual, rev. 1.1 12-14 freescale semiconductor preliminary 12.3.7 software and level n iack registers (swiackr, l1iack?l7iack) the eight iack registers can be explicitly addressed via the cpu, or implicitly addressed via a processor-generated interrupt acknowledge cycle during exception processing. in ei ther case, the interrupt controller?s actions are very similar. first, consider an iack cycle to a specific level: that is, a level-n iack . when this type of iack arrives in the interrupt controller, the c ontroller examines all the currentl y-active level n interrupt requests, determines the highest pr iority within the level, and then re sponds with the unique vector number corresponding to that specific interrupt source. the vector number is suppl ied as the data for the byte-sized iack read cycle. in addition to pr oviding the vector number, the interrupt controller also loads the level and priority number for the level into the iack lpr register, where it may be retrieved later. this interrupt controller design al so supports the concept of a software iack. a software iack is a useful concept that allows an interrupt service routine to determine if there are other pending interrupts so that the overhead associated with interrupt excepti on processing (including m achine state save/restore functions) can be minimized. in general, the software iack is pe rformed near the end of an interrupt service routine, and if there are additional active interrupt sources, th e current interrupt service routine (isr) passes control to the appropr iate service routine, but without taking another interrupt exception. when the interrupt controller receives a software iack read, it returns the vect or number associated with the highest level, highest priority unmasked interrupt source for that interrupt controller. the iacklpr register is also loaded as the software iack is performed. if there are no active sources, the interrupt controller returns an al l-zero vector as the operand. for this si tuation, the iacklpr register is also cleared. in addition to the software iack re gisters within each interrupt contro ller, there are global software iack registers. a read from th e global swiack will return the vector number for the highest level and priority unmasked interrupt source from all interrupt controllers. a read from one of the l n iack registers will return the vector for the highest priority unmasked in terrupt within a level for all interrupt controllers. 54 not used (reserved) 55 pit0 pif pit interrupt flag write pif = 1 or write pmr 56 pit1 pif pit interrupt flag write pif = 1 or write pmr 57 not used (reserved) 58 not used (reserved) 59 cfm cbeif sgfm buffer empty write cbeif = 1 60 cfm ccif sgfm command complete cleared automatically 61 cfm pvif protection violation cleared automatically 62 cfm aeif access error cleared automatically 63 pwm pwm pwm interrupt write pwmif = 1 table 12-13. interrupt source assignment for interrupt controller 0 (continued) source module flag source description flag clearing mechanism
interrupt controller module mcf5213 reference manual, rev. 1.1 freescale semiconductor 12-15 preliminary 12.4 low-power wakeup operation the system control module (scm) c ontains an 8-bit low-power interr upt control register (lpicr) used explicitly for controlling the low- power stop mode. this re gister must explicit ly be programmed by software to enter low-power mode. the interrupt controller provides a special combinator ial logic path to provide a special wake-up signal to exit from the low-power stop mode. this sp ecial mode of operation works as follows: ? first, lpicr[6:4] is loaded with the mask level that will be specified while the core is in stop mode. lpicr[7] must be set to enab le this mode of operation. note the wakeup mask level taken from lpi cr[6:4] is adjusted by hardware to allow a level 7 irq to generate a wa keup. that is, the wakeup mask value used by the interrupt controller must be in the range of 0?6. ? second, the processor executes a stop instructi on which places it in stop mode. once the processor is stopped, each interrupt controller en ables a special logic path which evaluates the incoming interrupt sources in a purely combinator ial path; that is, there are no clocked storage elements. if an active interrupt reque st is asserted and the resulting interrupt level is greater than the mask value contained in lpicr[6:4], then th e interrupt controller asserts the wake-up output signal, which is routed to the scm and then to th e pll module to re-enable the device?s clock trees and resume processing. 76 43 0 field vector reset 0000_0000 r/w r address see table 12-2 and ta b l e 1 2 - 3 for register offsets figure 12-10. software and level n iack registers (swiackr, l1iack?l7iack) table 12-14. swiack and l1iack-l7iack field descriptions bits name description 7?0 vector vector number. a read from the swiack regist er returns the vector nu mber associated with the highest level, highest priority unmasked in terrupt source. a read from one of the l n ack registers returns the highest priority unmasked interrupt source within the level.
interrupt controller module mcf5213 reference manual, rev. 1.1 12-16 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 13-1 preliminary chapter 13 edge port module (eport) 13.1 introduction the edge port module (eport) has se ven external inte rrupt pins, irq7 ?irq1 . each pin can be configured individually as a level-sensitive inte rrupt pin, an edge-detecting interrupt pin (rising edge , falling edge, or both), or a general-purpose input/output (i/o) pin. see figure 13-1 . figure 13-1. eport block diagram 13.2 low-power mode operation this section describes the operation of the eport m odule in low-power modes. for more information on low-power modes, see chapter 7, ?power management .? table 13-1 shows eport module operation in low-power modes, and desc ribes how this module may exit from each mode. note the low-power interrupt c ontrol register (lpicr) in the system control module specifies the interrupt level at or above which is needed to bring the device out of a low-power mode. ipbus synchronizer epdr[n] epfr[n] eppar[2n, 2n + 1] epier[n] edge detect d0 stop logic eppdr[n] d1 q d0 d1 q mode epddr[n] to interrupt controller irqx pin rising edge of system clock
edge port module (eport) mcf5213 reference manual, rev. 1.1 13-2 freescale semiconductor preliminary table 13-1. edge port module operation in low-power modes in wait and doze modes, the eport module continue s to operate as it does in run mode. it may be configured to exit the low-power m odes by generating an interrupt reques t on either a sele cted edge or a low level on an external pin. in stop mode, there are no clocks avai lable to perform the edge-detect function. only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode. note the input pin synchronizer is bypassed for the level-detect logic since no clocks are available. 13.3 interrupt/general-pur pose i/o pin descriptions all pins default to general-purpose i nput pins at reset. the pin value is synchronized to the rising edge of clkout when read from the eport pin data register (eppdr). the valu es used in the edge/level detect logic are also synchronized to the rising edge of clkout. these pi ns use schmitt trig gered input buffers which have built in hysteresis de signed to decrease the probability of generating false edge-triggered interrupts for slow rising and falling input signals. when a pin is configured as an output, it is driven to a state whose level is de termined by the corresponding bit in the eport data register (epdr). all bits in the epdr are high at reset. low-power mode eport operation mode exit wait normal any irqx interrupt at or above level in lpicr doze normal any irqx interrupt at or above level in lpicr stop level-sensing only any irqx interrupt set for level-sensing at or above level in lpicr
edge port module (eport) mcf5213 reference manual, rev. 1.1 freescale semiconductor 13-3 preliminary 13.4 memory map and registers this subsection describes the memo ry map and register structure. 13.4.1 memory map refer to table 13-2 for a description of the eport memory map. the eport has an ipsbar offset for base address of 0x0013_0000. 13.4.2 registers the eport programming model cons ists of these registers: ? the eport pin assignment register (eppar) c ontrols the function of each pin individually. ? the eport data direction regist er (epddr) controls the direct ion of each one of the pins individually. ? the eport interrupt enable regi ster (epier) enables interrupt re quests for each pin individually. ? the eport data register (epdr) holds the data to be driven to the pins. ? the eport pin data register (eppdr) reflects the current state of the pins. ? the eport flag register (epfr) indi vidually latches eport edge events. 13.4.2.1 eport pin assignm ent register (eppar) table 13-2. edge port module memory map ipsbar offset bits 15?8 bits 7?0 access 1 1 s = cpu supervisor mode access only. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycl e termination transfer error. 0x0013_0000 eport pin assignment register (eppar) s 0x0013_0002 eport data direction register (epd dr) eport interrupt enable register (epier) s 0x0013_0004 eport data register (epdr) eport pin data register (eppdr) s/u 0x0013_0006 eport flag register (epfr) reserved 2 2 writing to reserved address locations has no effect, and reading returns 0s. s/u 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field eppa7 eppa6 eppa5 eppa4 eppa3 eppa2 eppa1 ? reset 0000_0000_0000_0000 r/w r/w r address ipsbar + 0x0013_0000, 0x0013_0001 figure 13-2. eport pin assignment register (eppar)
edge port module (eport) mcf5213 reference manual, rev. 1.1 13-4 freescale semiconductor preliminary 13.4.2.2 eport data dir ection register (epddr) table 13-3. eppar field descriptions bit(s) name description 15?2 eppax eport pin assignment select fields. the read/write eppax fields configure eport pins for level detection and rising and/or falling edge detection. pins configured as level-sensitive are inve rted so that a logic 0 on the external pin represents a valid interrupt request. level-sensit ive interrupt inputs are not latched. to guarantee that a level-sensitive interrup t request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. level sensitivity must be selected to bring the device out of stop mode with an irqx interrupt. pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. a pin configured fo r edge detection can trigger an interrupt regardless of its configuration as input or output. interrupt requests generated in the eport module can be masked by the interrupt controller module. eppar functionality is independent of the selected pin direction. reset clears the eppax fields. 00 pin irqx level-sensitive 01 pin irqx rising edge triggered 10 pin irqx falling edge triggered 11 pin irqx both falling edge and rising edge triggered 1?0 ? reserved, should be cleared. 765 43210 field epdd7 epdd6 epdd5 epdd4 epdd3 epdd2 epdd1 ? reset 0000_0000 r/w r/w r address ipsbar + 0x0013_0002 figure 13-3. eport data di rection register (epddr) table 13-4. epdd field descriptions bit(s) name description 7?1 epddx setting any bit in the epddr configures the corresponding pin as an output. clearing any bit in epddr configures the corresponding pin as an input. pin direction is independent of the level/edge detection c onfiguration. reset clears epdd7-epdd1. to use an eport pin as an external interrupt request source, its corresponding bit in epddr must be clear. software can generate interrupt requests by programming the eport data register when the epddr selects output. 1 corresponding eport pin configured as output 0 corresponding eport pin configured as input 0 ? reserved, should be cleared.
edge port module (eport) mcf5213 reference manual, rev. 1.1 freescale semiconductor 13-5 preliminary 13.4.2.3 edge port interrupt enable register (epier) 13.4.2.4 edge port data register (epdr) 765 43210 field epie7 epie6 epie5 epie4 epie3 epie2 epie1 ? reset 0000_0000 r/w r/w r address ipsbar + 0x0013_0003 figure 13-4. eport port interrupt enable register (epier) table 13-5. epier field descriptions bit(s) name description 7?1 epiex edge port interrupt enable bits enable eport interrupt requests. if a bit in epier is set, eport generates an interrupt request when: the corresponding bit in the eport flag register (epfr) is set or later becomes set. the corresponding pin level is low and the pin is configured for level-sensitive operation. clearing a bit in epier negates any interrupt request from the corresponding eport pin. reset clears epie7-epie1. 1 interrupt requests from corresponding eport pin enabled 0 interrupt requests from corresponding eport pin disabled 0 ? reserved, should be cleared. 765 43210 field epd7 epd6 epd5 epd4 epd3 epd2 epd1 ? reset 1111_1111 r/w r/w r address ipsbar + 0x0013_0004 figure 13-5. eport port data register (epdr) table 13-6. epdr field descriptions bit(s) name description 7?1 epdx edge port data bits. data written to epdr is stored in an internal register; if any pin of the port is configured as an output, the bi t stored for that pin is driven onto the pin. reading edpr returns the data stored in the register. reset sets epd7-epd1. 0 ? reserved, should be cleared.
edge port module (eport) mcf5213 reference manual, rev. 1.1 13-6 freescale semiconductor preliminary 13.4.2.5 edge port pin data register (eppdr) 13.4.2.6 edge port flag register (epfr) 765 43210 field eppd7 eppd6 eppd5 eppd4 eppd3 eppd2 eppd1 ? reset current pin state 0 r/w r address ipsbar + 0x0013_0005 figure 13-6. eport port pin data register (eppdr) table 13-7. eppdr field descriptions bit(s) name description 7?1 eppdx edge port pin data bits . the read-only eppdr reflects th e current state of the eport pins irq7 ?irq1 . writing to eppdr has no effect, and the write cycle terminates normally. reset does not affect eppdr. 0 ? reserved, should be cleared. 765 43210 field epf7 epf6 epf5 epf4 epf3 epf2 epf1 ? reset 0000_0000 r/w r/w r address ipsbar + 0x0013_0006 figure 13-7. eport port flag register (epfr) table 13-8. epfr field descriptions bit(s) name description 7?1 epfx edge port flag bits. when an eport pin is configured for edge triggering, its corresponding read/write bit in epfr indicates that the selected edge has been detected. reset cl ears epf7-epf1. bits in this register are set when the sele cted edge is detected on the corresponding pin. a bit remains set until cleared by writi ng a 1 to it. writing 0 has no effect. if a pin is configured as level-sensitive (epparx = 00 ), pin transitions do not affect this register. 1 selected edge for irqx pin has been detected. 0 selected edge for irqx pin has not been detected. 0 ? reserved, should be cleared.
mcf5213 reference manual, rev. 1.1 freescale semiconductor 14-1 chapter 14 dma controller module this chapter describes the direct memory access (dma) controller module. it provides an overview of the module and describes in detail its signals and registers. the la tter sections of this chapter describe operations, features, and supported da ta transfer modes in detail. note the designation ? n ? is used throughout this sect ion to refer to registers or signals associated with one of the four identical dma channels: dma0, dma1, dma2 or dma3. 14.1 overview the dma controller module provides an efficient way to move blocks of data with minimal processor interaction. the dma module, shown in figure 14-1 , provides four channels that allow byte, word, longword, or 16-byte burst data tran sfers. each channel has a dedica ted source address register (sar n ), destination address register (dar n ), byte count register (bcr n ), control register (dcr n ), and status register (dsr n ). transfers are dual address to on-chip devices, such as uarts, and gpios. figure 14-1. dma signal diagram note throughout this chapter ?ext ernal request? and dreq are used to refer to a dma request from one of the on-chip uarts or dma timers. mux arbitration/ bus interface data path control internal external channel channel mux registered data path sar0 dar0 bcr0 dcr0 dsr0 channel 0 interrupts sar1 dar1 bcr1 dcr1 dsr1 channel 1 sar2 dar2 bcr2 dcr2 dsr2 channel 2 sar3 dar3 bcr3 dcr3 dsr3 channel 3 bus requests attributes current master attributes write data bus read data bus system bus address system bus size channel enables requests bus signals control control
dma controller module mcf5213 reference manual, rev. 1.1 14-2 freescale semiconductor 14.1.1 dma module features the dma controller module features are as follows: ? four independently programmab le dma controller channels ? auto-alignment feature for s ource or destination accesses ? dual-address transfers ? channel arbitration on transfer boundaries ? data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer ? continuous-mode or cycle-steal transfers ? independent transfer widths for source and destination ? independent source and dest ination address registers
dma transfer overview mcf5213 reference manual, rev. 1.1 freescale semiconductor 14-3 14.2 dma transfer overview the dma module can transfer data faster than the coldfire core. the term ?direct memory access? refers to a fast method of movi ng data within system memory (incl uding memory and peripheral devices) with minimal processor intervention, gr eatly improving over all system performa nce. the dma module consists of four independent, functi onally equivalent channels, so refere nces to dma in this chapter apply to any of the channels. it is not possible to implicitly address all four channels at once. the processor generates dma requests internally by setting dcr[start]; the uart modules and dma timers can generate a dma request by asserting internal dreq signa ls. the processor can program bus bandwidth for each channel. the channels support cycle-steal and continuous transfer modes; see section 14.4.1, ?transfer requests (cyc le-steal and continuous modes) .? the dma controller supports dual-address transfer s. the dma channels support up to 32 data bits. ? dual-address transfers?a dual-addr ess transfer consists of a r ead followed by a write and is initiated by an internal request using the start bi t or by asserting dreq. two types of transfer can occur: a read from a source device or a write to a destination device. see figure 14-2 for more information. figure 14-2. dual-address transfer any operation involving the dma module follows the same three steps: 1. channel initialization?channel registers are load ed with control inform ation, address pointers, and a byte-transfer count. 2. data transfer?the dma accepts requests for operand transfers and provides addressing and bus control for the transfers. 3. channel termination?occurs after the operation is fi nished, either successfully or due to an error. the channel indicates the operation status in the channel?s dsr, described in section 14.3.5, ?dma status registers (dsr0?dsr3) .? 14.3 dma controller module programming model this section describes each internal register and its bit assignment. note that modifying dma control registers during a dma transfer can result in undefined operation. table 14-1 shows the mapping of dma controller registers. note the differences for the byte count re gisters depending on the value of mpark[bcr24bit]. see section 8.5.3, ?bus master park register (mpark) ? for further information. dma dma memory/ peripheral memory/ peripheral control and data control and data
dma controller module mcf5213 reference manual, rev. 1.1 14-4 freescale semiconductor 14.3.1 source address registers (sar0?sar3) sar n , shown in figure 14-3 , contains the address from which the dma controller requests data. note the backdoor enable bit must be set in both the core and scm in order to enable backdoor accesses fr om the dma to sram. see section 8.4.2, ?memory base address register (rambar) ? for more details. table 14-1. memory map for dma controller module registers dma channel ipsbar offset [31:24] [23:16] [15:8] [7:0] 0 0x100 source address register 0 (sar0) [p. 14-4] 0x104 destination address register 0 (dar0) [p. 14-5] 0x108 dma status register 0 (dsr0) [p. 14-8] byte count register 0 (bcr24bit = 1) (bcr0) [p. 14-5] 0x10c dma control register 0 (dcr0) [p. 14-5] 1 0x140 source address register 1 (sar1) [p. 14-4] 0x144 destination address register 1 (dar1) [p. 14-5] 0x148 dma status register 0 (dsr0) [p. 14-8] byte count register 1 (bcr24bit = 1) (bcr0) [p. 14-5] 0x14c dma control register 1 (dcr0) [p. 14-5] 2 0x180 source address register 2 (sar2) [p. 14-4] 0x184 destination address register 2 (dar2) [p. 14-5] 0x188 dma status register 0 (dsr0) [p. 14-8] byte count register 2 (bcr24bit = 1) (bcr0) [p. 14-5] 0x18c dma control register 2 (dcr0) [p. 14-5] 3 0x1c0 source address register 3 (sar3) [p. 14-4] 0x1c4 destination address register 3 (dar3) [p. 14-5] 0x1c8 dma status register 0 (dsr0) [p. 14-8] byte count register 3 (bcr24bit = 1) (bcr0) [p. 14-5] 0x1cc dma control register 3 (dcr0) [p. 14-5] 31 0 field sar reset 0000_0000_0000_0000_0000_0000_0000_0000 r/w r/w address ipsbar + 0x100, 0x140, 0x180, 0x1c0 figure 14-3. source address registers (sar n )
dma controller module programming model mcf5213 reference manual, rev. 1.1 freescale semiconductor 14-5 14.3.2 destination address registers (dar0?dar3) dar n , shown in figure 14-4 , holds the address to which th e dma controller sends data. figure 14-4. destination address registers (dar n ) note the dma should not be used to writ e data to the uar t transmit fifo in cycle steal mode. when the uart inte rrupt is used as a dma request it does not negate fast enough to get a single transfer. the uart transmit fifo only has one entry so the data from the second byte would be lost. 14.3.3 byte count re gisters (bcr0?bcr3) bcr n , shown in figure 14-5 , holds the number of bytes yet to be transferred fo r a given block. the offset within the memory map is based on the value of mpark[bcr24bit]. bcr n decrements on the successful completion of the address transfer of a wr ite transfer. bcr n decrements by 1, 2, 4, or 16 for byte, word, longword, or li ne accesses, respectively. figure 14-5 shows bcr n . figure 14-5. byte count registers (bcr n )?bcr24bit = 1 dsr n [done], shown in figure 14-7 , is set when the block transfer is complete. when a transfer sequenc e is initiated and bcr n [bcr] is not a multiple of 16, 4, or 2 when the dma is configured for line, longword, or wo rd transfers, respectively, dsr n [ce] is set and no tr ansfer occurs. see section 14.3.5, ?dma status registers (dsr0?dsr3) .? 14.3.4 dma control re gisters (dcr0?dcr3) dcr n , shown in figure 14-6 , is used for configuring the dma controller module. note that dcr n [at] is available only if mpark[ bcr24bit] is set. see section 8.5.3, ?bus master park register (mpark) ? for more information. 31 0 field dar reset 0000_0000_0000_0000_0000_0000_0000_0000 r/w r/w address ipsbar + 0x104, 0x144, 0x184, 0x1c4 31 24 23 0 field ? bcr reset ? 0000_0000_0000_0000_0000_0000 r/w r/w address ipsbar + 0x108, 0x148, 0x188, 0x1c8
dma controller module mcf5213 reference manual, rev. 1.1 14-6 freescale semiconductor table 14-2 describes dcr n fields. 31 30 29 28 27 25 24 23 22 21 20 19 18 17 16 field int eext cs aa bwc ? ? sinc ssize dinc dsize start reset 0000_0000_0000_0000 r/w r/w 15 14 0 field ? reset n/a r/w r/w address ipsbar + 0x10c, 0x14c, 0x18c, 0x1cc figure 14-6. dma cont rol registers (dcr n ) table 14-2. dcr n field descriptions bits name description 31 int interrupt on completion of transfer. determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition. 0 no interrupt is generated. 1 internal interrupt signal is enabled. 30 eext enable external request. care should be taken because a collision can occur between the start bit and dreq when eext = 1. 0 external request is ignored. 1 enables external request to initiate transfer. the internal request (initiated by setting the start bit) is always enabled. 29 cs cycle steal. 0 dma continuously makes read/write tr ansfers until the bcr decrements to 0. 1 forces a single read/write transfer per request. t he request may be internal by setting the start bit, or external by asserting dreq. 28 aa auto-align. aa and size determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size. see section 14.4.4.1, ?auto-alignment .? 0 auto-align disabled 1 if ssize indicates a transfer no smaller than dsiz e, source accesses are aut o-aligned; otherwise, destination accesses are auto-aligned. source alignment takes precedence over destination alignment. if auto-alignment is enabled, the appr opriate address register increments, regardless of dinc or sinc.
dma controller module programming model mcf5213 reference manual, rev. 1.1 freescale semiconductor 14-7 27?25 bwc bandwidth control. indicates the number of byte s in a block transfer. when the byte count reaches a multiple of the bwc value, the dma releases the bu s. for example, if bcr24bit is 0, bwc is 001 (512 bytes or value of 0x0200), and bcr is 0x1000, the bus is relinquished after bcr values of 0x0e00, 0x0c00, 0x0a00, 0x0800, 0x 0600, 0x0400, and 0x0200. if bcr24bit is 0, bwc is 110, and bcr is 33000, the bus is released after 232 bytes because the bcr is at 32768, a multiple of 16384. 24-23 ? reserved, should be cleared. 22 sinc source increment. controls whether a source address increments afte r each successful transfer. 0 no change to sar after a successful transfer. 1 the sar increments by 1, 2, 4, or 16, as determined by the transfer size. 21?20 ssize source size. determines the data size of the source bus cycle for the dma control module. 00 longword 01 byte 10 word 11 line (16-byte burst) 19 dinc destination increment. controls whether a dest ination address increments after each successful transfer. 0 no change to the dar after a successful transfer. 1 the dar increments by 1, 2, 4, or 16, depending upon the size of the transfer. 18?17 dsize destination size. determines the data size of the destination bus cycle for the dma controller. 00 longword 01 byte 10 word 11 line (16-byte burst) 16 start start transfer. 0dma inactive 1 the dma begins the transfer in accordance to the va lues in the control registers. start is cleared automatically after one system clock and is always read as logic 0. 15?0 ? reserved, should be cleared. table 14-2. dcr n field descriptions (continued) bits name description encoding bcr24bit = 0 bcr24bit = 1 000 dma has priority and does not negate its request until transfer completes. 001 512 16384 010 1024 32768 011 2048 65536 100 4096 131072 101 8192 262144 110 16384 524288 111 32768 1048576
dma controller module mcf5213 reference manual, rev. 1.1 14-8 freescale semiconductor 14.3.5 dma status registers (dsr0?dsr3) in response to an event, the dma cont roller writes to the appropriate dsr n bit, figure 14-7 . only a write to dsr n [done] results in action. table 14-3 describes dsr n fields. 14.4 dma controller module functional description in the following discussion, the term ?dma request? implies that dcr n [start] or dcr n [eext] is set, followed by assertion of dreq n . the start bit is cleared when the channel begins an internal access. 76543210 field ? ce bes bed ? req bsy done reset 0000_0000 r/w r/w address ipsbar + 0x108, 0x148, 0x18, 0x1c8 figure 14-7. dma status registers (dsr n ) table 14-3. dsr n field descriptions bits name description 7 ? reserved, should be cleared. 6 ce configuration error. occurs when bcr, sar, or dar does not match the requested transfer size, or if bcr = 0 when the dma receives a start condition . ce is cleared at hardware reset or by writing a 1 to dsr[done]. 0 no configuration error exists. 1 a configuration error has occurred. 5 bes bus error on source 0 no bus error occurred. 1 the dma channel terminated with a bus erro r during the read portion of a transfer. 4 bed bus error on destination 0 no bus error occurred. 1 the dma channel terminated with a bus error during the write portion of a transfer. 3 ? reserved, should be cleared. 2 req request 0 no request is pending or the channel is currently active. cleared when the channel is selected. 1 the dma channel has a transfer remaining and the channel is not selected. 1 bsy busy 0 dma channel is inactive. cleared when the dma has finished the last transaction. 1 bsy is set the first time the channel is enabled after a transfer is initiated. 0 done transactions done. set when all dma controller transactions complete, as determined by transfer count or error conditions. when bcr reaches zero, done is set when the final transfer completes successfully. done can also be used to abort a trans fer by resetting the status bits. when a transfer completes, software must clear done before reprogramming the dma. 0 writing or reading a 0 has no effect. 1 dma transfer completed. writing a 1 to this bit clears all dma status bits and can be used in an interrupt handler to clear the dma interrupt and error bits.
dma controller module functional description mcf5213 reference manual, rev. 1.1 freescale semiconductor 14-9 before initiating a dual-address access, the dma module verifies that dcr n [ssize,dsize] are consistent with the source and destin ation addresses. if they are not cons istent, the configuration error bit, dsr n [ce], is set. if misalignment is detected, no transfer occurs, dsr n [ce] is set, and, depending on the dcr configuration, an interrupt event is issued. note that if the auto-align bit, dcr n [aa], is set, error checking is performed on th e appropriate registers. a read/write transfer reads bytes fr om the source address a nd writes them to the de stination address. the number of bytes is the larger of the sizes specified by dcr n [ssize] and dcr n [dsize]. see section 14.3.4, ?dma control registers (dcr0?dcr3) .? source and destination address registers (sar n and dar n ) can be programmed in the dcr n to increment at the completion of a successful transfer. bcr n decrements when an address transfer write completes for a single-address access (dcr n [saa] = 0) or when saa = 1. 14.4.1 transfer requests (cycle -steal and cont inuous modes) the dma channel supports internal and external requests. a request is issued by setting dcr n [start] or by asserting dreq n . setting dcr n [eext] enables recognition of ex ternal dma requests. selecting between cycle-steal and continuous modes minimizes bus usage for either internal or external requests. ? cycle-steal mode (dcr n [cs] = 1)?only one comple te transfer from source to destination occurs for each request. if dcr n [eext] is set, a request can be either internal or external. an internal request is selected by setting dcr n [start]. an external request is initiated by asserting dreq n while dcr n [eext] is set. note that multiple transfers will occur if dreq n is continuously asserted. ? continuous mode (dcr n [cs] = 0)?after an internal or ex ternal request, the dma continuously transfers data until bcr n reaches zero or a multiple of dcr n [bwc] or until dsr n [done] is set. if bcr n is a multiple of bwc, the dma request signa l is negated until the bus cycle terminates to allow the internal arbite r to switch masters. dcr n [bwc] = 000 specifies the maximum transfer rate; other values specify a transfer rate limit. the dma performs the specified number of transfers, then relinquishes bus control. the dma negates its internal bus request on the last transfer before bcr n reaches a multiple of the boundary specified in bwc. on completion, the dma reasserts its bus request to regain mastership at the earliest opportunity. the dma loses bus c ontrol for a minimum of one bus cycle. 14.4.2 data transfer modes each channel supports dual-address transf ers, described in the next section. 14.4.2.1 dual-address transfers dual-address transfers consist of a source data read and a destination data writ e. the dma controller module begins a dual-addr ess transfer sequence du ring a dma request. if no error condition exists, dsr n [req] is set. ? dual-address read?the dma controller drives the sar n value onto the internal address bus. if dcr n [sinc] is set, the sar n increments by the appropriate number of bytes upon a successful read cycle. when the appropriate number of read cy cles complete (multiple reads if the destination size is larger than the source), the dma in itiates the write portion of the transfer. if a termination error occurs, dsr n [bes,done] are set and dma transactions stop. ? dual-address write?the dma controller drives the dar n value onto the address bus. if dcr n [dinc] is set, dar n increments by the appr opriate number of bytes at the completion of a
dma controller module mcf5213 reference manual, rev. 1.1 14-10 freescale semiconductor successful write cycle. bcr n decrements by the approp riate number of bytes. dsr n [done] is set when bcr n reaches zero. if the bcr n is greater than zero, another r ead/write transfer is initiated. if the bcr n is a multiple of dcr n [bwc], the dma request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. if a termination error occurs, dsr n [bes,done] are set and dma transactions stop. 14.4.3 channel initialization and startup before a block transfer starts, channel registers must be initia lized with information describing configuration, request-generatio n method, and the data block. 14.4.3.1 channel prioritization the four dma channels are prioriti zed in ascending order (channel 0 ha ving highest priority and channel 3 having the lowest) or in an order determined by dcr n [bwc]. if the bwc encoding for a dma channel is 000, that channel has priority only over the channel immediately preced ing it. for example, if dcr3[bwc] = 000, dma channel 3 has priority over dma channel 2 (assuming dcr2[bwc] 000) but not over dma channel 1. if dcr0[bwc] = dcr1[bwc] = 000, dma0 still has priority over dm a1. in this case, dcr1[bwc] = 000 does not affect prioritization. simultaneous external requests are prioritized either in ascending order or in an order determined by each channel?s dcr n [bwc] bits. 14.4.3.2 programming the dma controller module note the following general guide lines for programming the dma: ? no mechanism exists within the dma module itself to prevent writes to control registers during dma accesses. ?if the dcr n [bwc] value of sequential channels are equal, the channels are prioritized in ascending order. the sar n is loaded with the source (read) address. if the transfer is from a periph eral device to memory, the source address is the location of th e peripheral data register. if the tran sfer is from memory to either a peripheral device or memory, the source address is the starting a ddress of the data block. this can be any aligned byte address. the dar n should contain the destin ation (write) address. if the transfer is from a peripheral device to memory, or from memory to memory, the dar n is loaded with the starting a ddress of the data block to be written. if the transfer is from memory to a peripheral device, dar n is loaded with the address of the peripheral data register. this addr ess can be any aligned byte address. sar n and dar n change after each cycle depending on dcr n [ssize,dsize, sinc,dinc] and on the starting address. increment values can be 1, 2, 4, or 16 for byte, word, longword, or 16-byte line transfers, respectively. if the address regist er is programmed to remain unchange d (no count), the register is not incremented after the data transfer. bcr n [bcr] must be loaded with the number of byte tran sfers to occur. it is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. dsr n [done] must be cleared for channel startup. as soon as the channel has been initiali zed, it is started by writing a one to dcr n [start] or asserting dreq n , depending on the status of dcr n [eext]. programming the channel for internal requests causes
dma controller module functional description mcf5213 reference manual, rev. 1.1 freescale semiconductor 14-11 the channel to request the bus and start transferring data immediately. if the channel is programmed for external request, dreq n must be asserted before the channel requests the bus. changes to dcr n are effective immediately while the channel is active. to avoid pr oblems with changing a dma channel setup, write a one to dsr n [done] to stop the dma channel. 14.4.4 data transfer this section describes au to-alignment and bandwidth control for dma transfers. 14.4.4.1 auto-alignment auto-alignment allows block transfers to occur at the optimal size based on th e address, byte count, and programmed size. to us e this feature, dcr n [aa] must be set. the sour ce is auto-aligned if dcr n [ssize] indicates a transfer size larger than dcr n [dsize]. source alignmen t takes precedence over the destination when the source and dest ination sizes are equal. otherwise, the destination is auto-aligned. the address register chosen fo r alignment increments regardless of th e increment value. configuration error checking is performed on registers not chosen for alignment. if bcr n is greater than 16, the address de termines transfer size . bytes, words, or longwords are transferred until the address is aligned to the programm ed size boundary, at which ti me accesses begin using the programmed size. if bcr n is less than 16 at the start of a transfer, the num ber of bytes remaining dict ates transfer size. for example, aa = 1, sar n = 0x0001, bcr n = 0x00f0, ssize = 00 (longword) , and dsize = 01 (byte). because ssize > dsize, the source is auto-aligned. error checking is pe rformed on destination registers. the access sequence is as follows: 1. read byte from 0x0001?write 1 byte, increment sar n . 2. read word from 0x0002?write 2 bytes, increment sar n . 3. read longword from 0x0004?wri te 4 bytes, increment sar n . 4. repeat longwords until sar n = 0x00f0. 5. read byte from 0x00f0?write byte, increment sar n . if dsize is another size, data writ es are optimized to wr ite the largest size allo wed based on the address, but not exceeding the configured size. 14.4.4.2 bandwidth control bandwidth control makes it possible to force the dma off the bus to allow access to another device. dcr n [bwc] provides seven le vels of block transfer sizes. if the bcr n decrements to a multiple of the decode of the bwc, the dma bus re quest negates until the bus cycle te rminates. if a request is pending, the arbiter may then pass bus ma stership to another device. if auto-alignment is enabled, dcr n [aa] = 1, the bcr n may skip over the programmed boundary, in whic h case, the dma bus request is not negated. if bwc = 000, the request signa l remains asserted until bcr n reaches zero. dma has priority over the core. note that in this scheme , the arbiter can always force the dma to relinquish the bus. see section 8.5.3, ?bus master park register (mpark) .? 14.4.5 termination an unsuccessful transfer can terminate for one of the following reasons:
dma controller module mcf5213 reference manual, rev. 1.1 14-12 freescale semiconductor ? error conditions?when the mcf5213 encounters a read or write cycle that terminates with an error condition, dsr n [bes] is set for a read and dsr n [bed] is set for a write before the transfer is halted. if the error occurred in a write cycle, data in the internal holding register is lost. ? interrupts?if dcr n [int] is set, the dma drives the appr opriate internal interrupt signal. the processor can read dsr n to determine whether the transfer terminated successfully or with an error. dsr n [done] is then written with a one to clear the interrupt and the done and error bits.
mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-1 preliminary chapter 15 coldfire flash module (cfm) the microcontroller incorporates superflash? tec hnology licensed from sst. the coldfire flash module (cfm) is constructed with four banks of 32k x 16-bit flash to generate a 256-kbyte, 32-bit wide electrically erasable and programmable read-onl y memory array. the cfm is ideal for program and data storage for single-chip applicati ons and allows for fi eld reprogramming without external high-voltage sources. the voltage required to program and erase the flash is generated internally by on-chip charge pumps. program and erase operations are pe rformed under cpu control through a command-driven interface to an internal state m achine. all flash physical bl ocks can be programmed or erased at the same time; however, it is not possible to read from a flash phy sical block while the same block is being programmed or erased. the partitioning of array blocks makes it possible to program or erase one pair of flash physical blocks under the control of software r outines executing out of another pair. note some implementations of this micr ocontroller include only 128 kbytes of flash; half that of th e full feature set device. 15.1 features features of the cfm include: ? 256-kbytes of flash memory on the full featured device, 128-kbytes of flash memory on subset parts. ? basic flash access time of 2 cl ock cycles. optimized processor fl ash interface reduces basic flash access time through interleavi ng and speculative reads. ? automated program and erase operation ? concurrent verify, program, and erase of all array blocks ? read-while-write capability ? optional interrupt on command completion ? flexible scheme for protection agains t accidental program or erase operations ? access restriction controls for both superv isor/user and data/pr ogram space operations ? security for single- chip applications ? single power supply (system v dd ) used for all module operations ? auto-sense amplifier timeout for lo w-power, low-freque ncy read operations note enabling flash security will disable bdm communications. note when flash security is enabled, the chip will boot in single-chip mode regardless of the extern al reset configuration.
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-2 freescale semiconductor preliminary 15.2 block diagram the cfm module shown in figure 15-1 contains the flash physical bloc ks, the coldfire flash bus and ip bus interfaces, flash interface, regist er blocks, and the bist engine. each 128-kbyte flash physical bloc k is arranged as two 32,768-word (16 bits) memory arrays. each of these memory arrays is designated as x h or x l, where x represents one of the f our flash physical blocks (0?3) and h/l represents th e high or low 16 bits of each longword of logical memory. ea ch of these words may be read as either individua l bytes or aligned words. ali gned longword acces s is provided by concatenating the outputs of the each of the two memory arrays within the flash physical block. simple reads of bytes, aligned words, and aligned longw ords require two 66-mhz clock cycles, although the processor?s flash interface includes logic that reduces the effective access time through two-way longword interleaving and speculative reads. flash physical blocks are interl eaved on longword (4-byte) boundaries . therefore, all flash program, erase, and verify commands operate on adjacent flash physical blocks and are initiated with a single aligned 32-bit write to the appropr iate array location. any other write operation will cause a cycle termination transfer error. page erase operates simu ltaneously on two interleavi ng erase pages in adjacent flash physical blocks. each flash phys ical block is organized as 1024 rows of 128 bytes with a single erase page consisting of 8 rows (1024 bytes). since page erase operates simultaneous ly on two interleaving and adjacent physical fl ash blocks, each erase row is comprised of four 16-bit entries in each of two memory arrays within each of two flash phys ical blocks. the first row of flash is made up of 0h_0l_1h_1l [0] through 0h_0l_1h_1l [31], where each [ n ] represents four 16-bit words from each memory array in each of two physical bl ocks, for a total of 256 bytes. since a single erase page cons ists of 8 rows of 256 bytes, or 2048 bytes, the first erase page is physically located at 0h_0l_1h_1l [0] through 0h_0l_1h_1l [255]. mass erase operates simultan eously on two adjacent flash physica l blocks in their entirety and erases a total of 256 kbytes of flash space. an erased flash bit reads 1 and a programmed flas h bit reads 0. the cfm features a sense amplifier timeout (sato) block that automatically reduces cu rrent consumption during reads at low system clock frequencies.
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-3 preliminary figure 15-1. cfm block diagram flash interface ? ? ? sato sato sato sato bist engine internal bus memory array backdoor access flash control registers block 0h 32k x 16 memory array block 0l 32k x 16 memory array block 3h 32k x 16 memory array block 3l 32k x 16 flash physical block 0 flash physical block 3 note: mass erase block 0 (256 kbytes) = flash physical block 0 and flash physical block 1. mass erase block 1 (256 kbytes) = flash physical block 2 and flash physical block 3. v dd v ss
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-4 freescale semiconductor preliminary 15.3 memory map figure 15-2 shows the memory map for the cfm array. the cfm array can resi de anywhere in the memory space of the mcu. the starting address of th e array is determined by th e cfm array base address which must reside on a natural si ze boundary; that is, the cfm array base address must be an integer multiple of the array size. the cf m register space must reside on a 64 byte boundary as determined by the cfm register base address. figure 15-2 shows how multiple 32,768 by 16-bit flash physical blocks interleave to form a contiguous non-volatile memory space. each pa ir of 32-bit blocks (even and odd) interleave every 4 bytes to form a 256-kbyte section of memory. note the cfm on the smaller arrays is c onstructed with two banks of 32k x 16-bit flash arrays to generate 128 kbytes of 32-bit flash memory. figure 15-2. cfm array memory map the cfm module has hardware interl ocks to protect data from acc idental corruption. the cfm memory array is logically divided into 16- kbyte sectors for the purpose of data protection and access control. a flexible scheme allows the protection of any combination of logical sectors (see section 15.3.4.4, ?cfm protection register (cfmprot) ?). a similar mechanism is availabl e to control supervisor/user and program/data space access to these sectors. 0x0007 ffff 0x0004 000c 0x0000 0000 0x0000 0004 0x0000 0008 0x0000 000c 0x0003 ffff 0x0004 0000 0x0004 0004 0x0004 0008 3h[1] 3l[1] 2h[1] 2l[1] 3h[0] 3l[0] 2h[0] 2l[0] 1h[1] 1l[1] 0h[1] 0l[1] 1h[1] 1l[1] 0h[0] 0l[0] logical block 1 (256 kbytes) memory array 2h 2h[31] 2l[31] memory array 2l 2h[0] 2l[0] flash physical block 2 flash physical block 3 3h[31] 3l[31] 3h[0] 3l[0] memory array 3h memory array 3l logical block 0 (256 kbytes) memory array 0h 0h[31] 0l[31] memory array 0l 0h[0] 0l[0] flash physical block 0 flash physical block 1 1h[31] 1l[31] 1h[0] 1l[0] memory array 1h memory array 1l each memory array = 64 kbytes (16 bits wide 32k) each physical block = 128 kbytes (32 bits wide 32k) configuration field (0x0000_0400? 0x0000_0417) 1 the mcf5213 supports only logical block 0.
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-5 preliminary 15.3.1 cfm configuration field the cfm configuration field compri ses 24 bytes of reserved array me mory space that determines the module protection and access re strictions out of reset. data to secure the flas h from unauthorized access is also stored in the cfm configuration field. table 15-1 describes each byte used in this field. 15.3.2 flash base address register (flashbar) the configuration informa tion in the flash base a ddress register (flashbar) controls the operation of the flash module. ? the flashbar holds the base address of the flash. the movec instruction provides write-only access to this register. ? the flashbar can be read or written from the debug module in a similar manner. ? all undefined bits in the register are reserv ed. these bits are ignor ed during writes to the flashbar, and return zeroes when read from the debug module. ? the back door enable bit, flashb ar[bde], is cleared at reset, di sabling back door access to the flash. ? the flashbar valid bit is pr ogrammed according to the chip mode selected at reset (see chapter 27, ?chip configuration module (ccm) ? for more details). all other bits are unaffected. the flashbar register contains several c ontrol fields. these fields are shown in figure 15-3 note the default value of the flashb ar is determined by the chip configuration select ed at reset (see chapter 27, ?chip configuration module (ccm) ? for more information). if ex ternal boot mode is used, then the flashbar located in the processo r?s cpu space will be invalid and it must be initialized with the valid bi t set before the cpu (or modules) can access the on-chip flash. table 15-1. cfm configuration field address offset (from array base address) size in bytes description 0x0000_0400?0x0000_0407 8 back door comparison key 0x0000_0408?0x0000_040b 4 flash prog ram/erase sector protection blocks 0h/0l (see section 15.3.4.4, ?cfm protection register (cfmprot) ?) 0x0000_040c?0x0000_040f 4 flash supervisor/user space restrictions blocks 0h/0l (see section 15.3.4.5, ?cfm su pervisor access register (cfmsacc) ?) 0x0000_0410?0x0000_0413 4 flash program/data space restrictions blocks 0h/0l (see section 15.3.4.6, ?cfm data access register (cfmdacc) ?) 0x0000_0414?0x0000_0417 4 flash security longword (see section 15.3.4.3, ?cfm security register (cfmsec) ?)
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-6 freescale semiconductor preliminary note flash accesses (reads/writ es) by a bus master othe r than the core, (dma controller), or writes to flash by th e core during programming must use the backdoor flash address of ipsbar plus an offset of 0x0400_0000. for example, for a dma transf er from the first locati on of flash when ipsbar is still at its default location of 0x4000_0000, the source register would be loaded with 0x4400_0000. backdoor access to flash for reads can be made by the bus master, but it ta kes 2 cycles longer than a direct read of the flash if using its flashbar address. note the flash is marked as valid on reset based on the rcon (reset configuration) pin state. flash space is valid on re set when booting in single chip mode (rcon pin asserted and d[ 26]/d[17]/d[16] set to 110), or when booting internally in master mode (rcon asserted and d[26]/d[17]/d[16] are set to 111 and d[18] an d d[19] are set to 00). see chapter 27, ?chip configuration module (ccm) ? for more details. when the default reset configuration is not overriden, the mcf5213 will (by de fault) boot up in single chip mode and the fl ash space will be marked as valid at address 0x0. the flash configuration field is chec ked during the reset sequence to see if the flash is secured. if it is the part will always boot fr om internal flash, since it will be marked as valid, regardless of what is done for chip configuration. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 field ba31 ba30 ba29 ba28 ba27 ba26 ba25 ba24 ba23 ba22 ba21 ba20 ba19 ? reset 0000_0000_0000_0000 r/w r/w 15 9876543210 field ? wp ? c/i sc sd uc ud v reset 0000_0001_0010_000 see note r/w r/w r w r r/w address cpu + 0xc04 note: the reset value for the valid bit is determined by the chip mode selected at reset (see chapter 27, ?chip configuration module (ccm) ?). figure 15-3. flash base address register (flashbar)
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-7 preliminary 15.3.3 cfm registers the cfm module also contains a set of control and st atus registers. the memory map for these registers and their accessibility in supervisor and user modes is shown in table 15-3 . table 15-2. flashbar field descriptions bits name description 31?19 ba[31:18] base address field. defines t he 0-modulo-512k base address of the flash module. by programming this field, the flash may be located on any 512kbyte boundary within the processor?s four gigabyte address space. 18?9 ? reserved, should be cleared. 8 wp write protect. write only. allows only read accesses to the flash. when this bit is set, any attempted write access will generate an access error exception to the coldfire processor core. 0 allows read and write accesses to the flash module 1 allows only read accesses to the flash module 7?6 ? reserved, should be cleared. 5?1 c/i, sc, sd, uc, ud address space masks (asn). these five bit fields allow certain types of accesses to be ?masked,? or inhibited from accessing the flash module. the address space mask bits are: c/i cpu space/interrupt acknowledge cycle mask sc supervisor code address space mask sd supervisor data address space mask uc user code address space mask ud user data address space mask for each address space bit: 0 an access to the flash module can occur for this address space 1 disable this address space from the flash module. if a reference using this address space is made, it is inhibited from accessing the flash module, and is processed like any other non-flash reference. these bits are useful for po wer management as detailed in chapter 7, ?power management .? 0 v valid. when set, this bit enables the flash module; otherwise, the module is disabled. 0 contents of flashbar are not valid 1 contents of flashbar are valid table 15-3. cfm register address map ipsbar offset bits 31?24 bits 23?16 bits 15?8 bits 7?0 access 1 0x1d_0000 cfmmcr cfmclkd reserved 2 s 0x1d_0004 reserved 2 s 0x1d_0008 cfmsec s 0x1d_000c reserved 2 s 0x1d_0010 cfmprot s
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-8 freescale semiconductor preliminary 15.3.4 register descriptions the flash registers are desc ribed in this subsection. 15.3.4.1 cfm configurat ion register (cfmcr) the cfmcr is used to configure and control the operation of the cfm array. bits 10 -5 in the cfmcr register are r eadable and writable with restrictions. 0x1d_0014 cfmsacc s 0x1d_0018 cfmdacc s 0x1d_001c reserved 2 s 0x1d_0020 cfmustat reserved 2 s 0x1d_0024 cfmcmd reserved 2 s 1 s = supervisor access only. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2 addresses not assigned to a register and undefined register bits are reserved for expansion. write accesses to these reserved address spaces and reserved register bits have no effect. 15 11 10 9 8 7 6 5 4 0 field ? lock pvie aeie cbeie ccie keyacc ? reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x1d_0000 figure 15-4. cfm module conf iguration register (cfmcr) table 15-4. cfmcr field descriptions bits name description 15?11 ? reserved, should be cleared. 10 lock write lock control. the lock bi t is always readable and is set once. 1 cfmprot, cmfsacc, and cfmdacc register are write-locked. 0 cfmprot, cmfsacc, and cfmdacc register are writable. 9 pvie protection violation interrupt enable. the pvie bit is readable and writable. the pvie bit enables an interrupt in case the protection violation flag, pviol, is set. 1 an interrupt will be requested whenever the pviol flag is set. 0 pviol interrupts disabled. 8 aeie access error interrupt enable. the aeie bit is readable and writable. the aeie bit enables an interrupt in case the access error flag, accerr, is set. 1 an interrupt will be requested whenever the accerr flag is set. 0 accerr interrupts disabled. table 15-3. cfm register address map ipsbar offset bits 31?24 bits 23?16 bits 15?8 bits 7?0 access 1
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-9 preliminary 15.3.4.2 cfm clock divider register (cfmclkd) the cfmclkd is used to set the frequency of the clock used for timed events in program and erase algorithms. all bits in cfmclkd are readable. bit 7 is a read-only status bit, while bits 6?0 can only be written once. 7 cbeie command buffer empty interrupt enable. the cbeie bit is readable and writable. cbeie enables an interrupt request when the command buffer for the flash physical blocks is empty. 1 request an interrupt whenever the cbeif flag is set. 0 command buffer empty interrupts disabled 6 ccie command complete interrupt enable. the ccie bit is readable and writable. ccie enables an interrupt when the command executing for the flash is complete. 1 request an interrupt whenever the ccif flag is set. 0 command complete interrupts disabled 5 keyacc enable security key writing. the keyacc bit is readable and only writable if the keyen bit in the cfmsec register is set. 1 writes to the flash array are interpreted as keys to open the back door. 0 writes to the flash array are interpreted as the start of a program, erase, or verify sequence. 4?0 ? reserved, should be cleared. 765 0 field divld prdiv8 div reset 0000_0000 r/w r r/w address ipsbar + 0x1d_0002 figure 15-5. cfm clock di vider register (cfmclkd) table 15-5. cfmclkd field descriptions bits name description 7 divld clock divider loaded 1 cfmclkd has been written since the last reset. 0 cfmclkd has not been written. 6 prdiv8 enable prescaler divide by 8 1 enables a prescaler that divides the cfm clock by 8 before it enters the cfmclkd divider. 0 the cfm clock is fed directly into the cfmclkd divider. 5?0 div clock divider field. the combination of prdiv8 and div[ 5:0] effectively divides the cfm input clock down to a frequency between 150 khz and 200 khz. the frequency range of the cfm clock is 150 khz to 102.4 mhz. table 15-4. cfmcr field descriptions bits name description
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-10 freescale semiconductor preliminary note cfmclkd must be written with an appropriate value before programming or erasing the flash array. refer to section 15.4.3.1, ?setting the cfmclkd register .? 15.3.4.3 cfm security register (cfmsec) the cfmsec controls the flash security features. note enabling flash security will disable bdm communications. note when flash security is enabled, the chip will boot in single-chip mode regardless of the extern al reset configuration. 31 30 29 16 field keyen secstat ? reset see note r/w r 15 0 field sec reset see note r/w r address ipsbar + 0x1d_0008 note: the secstat bit reset value is determined by the security state of the flash. all ot her bits in the register are loaded at reset from the flash security l ongword stored at the array base address + 0x0000_0414. figure 15-6. cfm security register (cfmsec) table 15-6. cfmsec field descriptions bits name description 31 keyen enable back door key to security 1 back door to flash is enabled. 0 back door to flash is disabled. 30 secstat flash security status 1 flash security is enabled 0 flash security is disabled
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-11 preliminary the security features of the cfm are described in section 15.5, ?flash security operation .? 15.3.4.4 cfm protection register (cfmprot) the cfmprot specifies which flash logical sectors are pr otected from program and erase operations. the cfmprot register is always readable and only writeable when lock = 0. to change which logical sectors are protecte d on a temporary basis, write cfmprot wi th a new value after the lock bit in cfmcr has been cleared. to change the value of cfmprot that will be loaded on reset, the protection byte in the flash configuration fiel d must first be temporarily unprotect ed using the met hod just described before reprogramming the protection bytes. then th e flash protection longwor d at offset 0x1d_0400 must be written with the desired value. 29?16 ? reserved. should be cleared. 15?0 sec[15:0] security field. the sec bits defin e the security state of the device; see below. 31 16 field prot reset see note r/w r/w 15 0 field prot reset see note r/w r/w address ipsbar + 0x1d_0010 note: the cfmprot register is loaded at reset from t he flash program/erase sector protection longword stored at the array base address + 0x0000_0400. figure 15-7. cfm protection register (cfmprot) table 15-6. cfmsec field descriptions bits name description sec[15:0] description 0x4ac8 flash secured 1 1 the 0x4ac8 value was chosen because it represents the coldfire halt instruction, making it unlikely that compiled code accidentally programmed at the security longword in the flash configuration field location would unintentionally secure the device. all other combinations flash unsecured
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-12 freescale semiconductor preliminary the cfmprot controls the protection of thirty-two 16-kbyte flash logical sectors in the 512-kbyte flash array. figure 15-8 shows the association be tween each bit in the cf mprot and its corresponding logical sector. figure 15-8. cfmprot protection diagram 15.3.4.5 cfm supervisor a ccess register (cfmsacc) the cfmsacc specifies the supervisor/user ac cess permissions of fl ash logical sectors. table 15-7. cfmprot field descriptions bits name description 31?0 prot[31:0] sector protection. each flash logical sector can be protected from program and erase operations by setting its corresponding prot bit. 1 logical sector is protected. 0 logical sector is not protected. (array_base + 0x0000_0000) } 16kbyte sector (array_base + 0x0007_ffff) sector 0 sector 1 sector 2 sector 31 (array_base + 0x0000_4000) (array_base + 0x0000_8000) protect[31] protect[2] protected flash logical sectors as defined by cfmprot register (array_base + 0x0007_c000)
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-13 preliminary 15.3.4.6 cfm data acce ss register (cfmdacc) the cfmdacc specifies the data/program a ccess permissions of fl ash logical sectors. 31 16 field supv reset see note r/w r/w 15 0 field supv reset see note r/w r/w address ipsbar + 0x1d_0014 note: the cfmprot register is loaded at reset from the flash supervisor/user space restrictions longword stored at the array base address + 0x0000_040c. figure 15-9. cfm supervisor access register (cfmsacc) table 15-8. cfmsacc field descriptions bits name description 31?0 supv[31:0] supervisor address space assignment. the supv[31:0] bits are always readable and only writable when lock = 0. each flash logical sector can be mapped into supervisor or unrestricted address space. cfmsacc uses the same correspondence between logical sectors and register bits as does cfmprot. see figure 15-8 for details. when a logical sector is mapped into supervisor address space, only cpu supervisor accesses will be allowed. a cpu user access to a location in supervisor address space will result in a cycle termination transfer error. when a logical sector is mapped into unrestricted address space both supervisor and user accesses are allowed. 1 logical sector is mapped in supervisor address space. 0 logical sector is mapped in unrestricted address space.
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-14 freescale semiconductor preliminary 15.3.4.7 cfm user status register (cfmustat) the cfmustat reports flash state machine command status, array access errors , protection violations, and blank check status. note only one cfmustat bit should be cleared at a time. 31 16 field data reset see note r/w r/w 15 0 field data reset see note r/w r/w address ipsbar + 0x1d_0018 note: the cfmprot register is loaded at reset from the flash program/data space restrictions longword stored at the array base address + 0x0000_0410. figure 15-10. cfm data access register (cfmdacc) table 15-9. cfmdacc field descriptions bits name description 31?0 data[31:0] data address space assignment. the data[31:0] bits are always readable and only writable when lock = 0. each flash logical sector can be mapped into data or both data and program address space. cfmdacc uses the same correspondence between logical sectors and register bits as does cfmprot. see figure 15-8 for details. when a logical sector is mapped into data address space, only cpu data accesses will be allowed. a cpu program access to a location in data address space will result in a cycle termination transfer error. when an array sector is mapped into both data and program address space both data and program accesses are allowed. 1 logical sector is mapped in data address space. 0 logical sector is mapped in data and program address space . 765 1 0 field cbeif ccif pviol accerr ? blank ? reset 1100_0000 r/w r/w r r/w address ipsbar + 0x1d_0020 figure 15-11. cfm user status register (cfmustat)
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-15 preliminary 15.3.4.8 cfm command register (cfmcmd) the cfmcmd is the register to which flash pr ogram, erase, and verify commands are written. table 15-10. cfmustat field descriptions bits name description 7 cbeif command buffer empty interrupt flag. th e cbeif flag indicates that the command buffer for the interleaved flash physical blocks is empty and that a new command sequence can be started. clear cbeif by wr iting it to 1. writing a 0 to cbeif has no effect but can be used to abort a command sequence. the cbeif bit can trigger an interrupt request if the cbeie bit is set in cfmmcr. while cbeif is clear, the cfmcmd register is not writable. 1 command buffer is ready to accept a new command. 0 command buffer is full. 6 ccif command complete interrupt flag. the ccif flag indicates that no commands are pending for the flash physical blocks. ccif is set and cleared automatically upon start and completion of a command. writin g to ccif has no effect. the ccif bit can trigger an interrupt request if the ccie bit is set in cfmcr. 1 all commands are completed 0 command in progress 5 pviol protection violation flag. the pviol flag indicates an attempt was made to initiate a program or erase operation in a flash logical sector denoted as protected by cfmprot. clear pviol by writing it to 1. writing a 0 to pviol has no effect. while pviol is set in any this register, it is not possible to launch another command. 1 a protection violation has occurred 0 no failure 4 accerr access error flag. the accerr flag in dicates an illegal access to the cfm array or registers caused by a bad program or erase sequence. accerr is cleared by writing it to 1. writing a 0 to accerr has no effect. while accerr is set in this register, it is not possible to launch another command. see section 15.4.3.4, ?flash user mode illegal operations ,? for details on what sets the accerr flag. 1 access error has occurred 0 no failure 3 ? reserved, should be cleared. 2 blank erase verified flag. the blank flag indicates that the erase verify command (rdary1) has checked the two interleaved flash physical blocks and found them to be blank. clear blank by writing it to 1. writing a 0 has no effect. 1 flash physical blocks verify as erased. 0 if an erase verify command has been requested, and the ccif flag is set, then the selected flash physical blocks are not blank. 1?0 ? reserved, should be cleared. 76 0 field ? cmd reset 0000_0000 r/w r/w address ipsbar + 0x1d_0024 figure 15-12. cfm command register (cfmcmd)
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-16 freescale semiconductor preliminary cfmcmd is readable and writable in all modes. wr ites to bit 7 have no ef fect and reads return 0. 15.4 cfm operation the cfm registers, subject to the restrictions previously noted, can generally be read and written (see section 15.3.4, ?register descriptions ? for details). reads of the cf m array occur normally and writes behave according to the sett ing of the keyacc bit in cfmcr. progr am, erase, and verify operations are initiated by the cpu. special cases of user mode apply when the cp u is in low-power or debug modes and when the mcu boots in mast er mode or emulation mode. 15.4.1 read operations a valid read operation occurs whenever a transfer reque st is initiated by the coldfire core, the address is equal to an address within the vali d range of the cfm memory space, a nd the read/write control indicates a read cycle. in order to reduce power at low sy stem clock frequencies, the sens e amplifier timeout (sato) block minimizes the time during which the sense amplifiers are enabled for r ead operations. the sense amplifier enable signals to the flash ti meout after approximately 50 ns. 15.4.2 write operations a valid write operation occurs whenever a transfer reque st is initiated by the coldfire core, the address is equal to an address within the vali d range of the cfm memory space, a nd the read/write control indicates a write cycle. the action taken on a valid cfm array write depends on th e subsequent user comma nd issued as part of a valid command sequence. only ali gned 32-bit write operations are allowed to the cfm array. byte and word write operations will result in a cycle termination transfer error. table 15-11. cfmcmd field descriptions bits name description 7 ? reserved, should be cleared. 6?0 cmd[6:0] command. valid flash user mode commands are shown in table 15-12 . writing a command in user mode other than those listed in table 15-12 will set the accerr flag in cfmustat. table 15-12. cfmcmd user mode commands command name description 0x05 rdary1 erase verify (all 1s) 0x20 pgm longword program 0x40 pgers page erase 0x41 masers mass erase 0x06 pgersver page erase verify
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-17 preliminary 15.4.3 program and erase operations read and write operations are both us ed for the program and erase algorit hms described in this subsection. these algorithms are controlled by a state machine w hose timebase is derived fr om the cfm module clock via a programmable counter. the command register and associated address and data buffers operate as a two stage fifo so that a new command along with the necessary addre ss and data can be stored while the previous command is still in progress. this pipelining speeds when programming mo re than one longword on a specific row, as the charge pumps can be kept on in between two programmi ng commands, thus savi ng the overhead needed to set up the charge pumps. buffer empty and comman d completion are indicated by flags in the cfm user status register. interrupts wi ll be requested if enabled. 15.4.3.1 setting the cfmclkd register prior to issuing any program or erase commands, cfmclkd must be written to set the flash state machine clock (fclk). the cfm module runs at the system clock frequency 2, but fclk must be divided down from this frequency to a frequency between 150 khz and 200 khz. use the following procedure to set the prdiv8 a nd div[5:0] bits in cfmclkd: 1. if f sys 2 is greater than 12.8 mhz, prdiv8 = 1; otherwise prdiv8 = 0. 2. determine div[5:0] by using the following equation. keep only th e integer portion of the result and discard any fraction. do not round the result. 3. thus the flash state machine clock will be: consider the following example for f sys = 66 mhz: f sys 2 x 200khz x (1 + (prdiv8 x 7)) div[5:0] = f sys 2 x (div[5:0] + 1) x (1 + (prdiv8 x 7)) f clk = f sys 2 x 200khz x (1 + (prdiv8 x 7)) div[5:0] = 66 mhz 400 khz x (1 + (1 x 7)) = = 20 f sys 2 x (div[5:0] + 1) x (1 + (prdiv8 x 7)) f clk = 66 mhz 2 x (20 + 1) x (1 + (1 x 7)) = = 196.43 khz
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-18 freescale semiconductor preliminary so, for f sys = 66 mhz, writing 0x54 to cfmclkd will set f clk to 196.43 khz which is a valid frequency for the timing of program and erase operations. warning for proper program and erase opera tions, it is critical to set f clk between 150 khz and 200 khz. array damage due to overstress can occur when f clk is less than 150 khz. incomplete programming and eras ure can occur when f clk is greater than 200 khz. note command execution time increases proportionally with the period of f clk . when cfmclkd is written, the divld bit is set automatically. if divld is 0, cfmclkd has not been written since the last reset. program and erase commands will not exec ute if this regi ster has not been written (see section 15.4.3.4, ?flash user mode illegal operations ?). 15.4.3.2 program, erase, and verify sequences a command state machine is used to supervise the write sequencin g of program, er ase, and verify commands. to prepare for a command, the cfmustat[cbeif] flag should be tested to ensure that the address, data, and command buffers are empty. if cbeif is set, the command write sequence can be started. this three-step command write seque nce must be strictly followed. no intermediate writes to the cfm module are permitted between these three steps. the command write sequence is: 1. write the 32-bit longword to be programmed to it s location in the cfm arra y. the address and data will be stored in internal buffers. all address bits are valid for program commands. the value of the data written for verify and er ase commands is ignored. for mass erase or verify, the address can be any location in the cfm array. for page erase, address bits [9:0] are ignored. note the page erase command operates simu ltaneously on adjacent erase pages in two interleaved flas h physical blocks. thus, a single erase page is effectively 2 kbyte. 2. write the program, erase, or verify command to cfmcmd , the command buffer. see section 15.4.3.3, ?flash valid commands .? 3. launch the command by writing a 1 to the cbeif flag. this clears cbeif. when command execution is complete, the flash state machine se ts the ccif flag. the cbeif flag is also set again, indicating that the address, data, and command buffers are ready for a new command sequence to begin. the flash state machine flags erro rs in command write sequences by means of the accerr and pviol flags in the cfmustat register . an erroneous comma nd write sequence self-a borts and sets the appropriate flag. the acce rr or pviol flags must be cleared before commencing another command write sequence.
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-19 preliminary note by writing a 0 to cbeif, a command sequence can be aborted after the longword write to the cf m array or the command write to the cfmcmd and before the command is launched. the accerr flag will be set on aborted commands and must be cl eared before a new command write sequence. a summary of the programmi ng algorithm is shown in figure 15-13 . the flow is similar for the erase and verify algorithms with the exce ptions noted in step 1 above. 15.4.3.3 flash valid commands table 15-13 summarizes the valid flash user commands. table 15-13. flash user commands cfmcmd meaning description 0x05 erase verify verify that all 256 kbytes of flash from two interleaving physical blocks are erased. if both blocks are erased, the blank bit will be set in the cfmustat register upon command completion. 0x20 program program a 32-bit longword. 0x40 page erase erase 2 kbyte of flash. two 1024- byte pages from interleaving physical blocks are erased in this operation. 0x41 mass erase erase all 256 kbytes of flash from two interleaving physical blocks. a mass erase is only possible when no protect bits are set for that block. 0x06 page erase verify verify that the two 1024-byte pages are erased. if both pages are erased, the blank bit will be set in the cfmustat register upon command completion.
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-20 freescale semiconductor preliminary figure 15-13. example program algorithm write cfmclkd read cfmclkd divld set? write program data write program command 0x20 to cfmcmd write 0x80 to clear cfmustat yes no cbeif bit yes clock register written check 1. 2. 3. cfmustat accerr bit write 0x10 to clear no yes no protection violation check access error check read cfmustat no no address, data, command buffer empty check next write? yes no to array address cfmustat pviol bit write 0x20 to clear yes bit polling for command completion check read cfmustat yes note: command sequence aborted by writing 0x00 to cfmustat note: command sequence aborted by writing 0x00 to cfmustat exit read cfmustat no start yes cbeif set? pviol set? accerr set? cbeif set? ccif set?
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-21 preliminary 15.4.3.4 flash user mode illegal operations the accerr flag will be set during a command write sequence if any of the il legal operations below are performed. such operations will cause th e command sequence to immediately abort. 1. writing to the cfm array before initializing cfmclkd. 2. writing to the cfm array while in emulation mode. 3. writing a byte or a word to the cfm array. only 32-bit longword programming is allowed. 4. writing to the cfm array while cbeif is not set. 5. writing an invalid user command to the cfmcmd. 6. writing to any cfm other than cfmcmd after writing a longword to the cfm array. 7. writing a second command to cfmcmd before executing the previously written command. 8. writing to any cfm register other than cfmu stat (to clear cbeif) after writing to the command register. 9. entering stop mode while a program or erase comma nd is in progress. 10. aborting a command sequence by writing a 0 to cbeif after the longword write to the cfm array or after writing a command to cfmcmd and before launching it. the pviol flag will be set duri ng a command write sequence after th e longword write to the cfm array if any of the illegal operations be low are performed. such operations will cause the command sequence to immediately abort. 1. writing to an address in a protected area of the cfm array. 2. writing a mass erase command to cfmcmd wh ile any logical sector is protected (see section 15.3.4.4, ?cfm protection register (cfmprot) ?). if a flash physical block is read during a program or erase operati on on that block (cfmustat bit ccif = 0), the read will return non-valid data and the accerr flag will not be set. 15.4.4 stop mode if a command is active (ccif = 0) when the mc u enters stop mode, the command sequence monitor performs the following: 1. the command in progress aborts 2. the flash high voltage circuitry switches off and any pending command (cbeif = 0) does not executed when the mcu exits stop mode. 3. the ccif and accerr flags are set if a comma nd is active when the mcu enters stop mode. note the state of any longwor d(s) being programmed or any erase pages/physical blocks being erased is not guaranteed if the mcu enters stop mode with a command in progress. warning active commands are immediately aborted when the mcu enters stop mode. do not execute the stop in struction during program and erase operations.
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-22 freescale semiconductor preliminary 15.5 flash security operation the cfm array provides secu rity information to the integration module and the rest of the mcu. a longword in the flash configuration fi eld stores this information. this l ongword is read automatically after each reset and is stored in the cfmsec register. note enabling flash security will disable bdm communications. in user mode, security can be bypa ssed via a back door access sche me using an 8-byte long key. upon successful completion of the back door access sequence, the module output signal a nd status bit indicating that the chip is secure are cleared. the cfm may be unsecured via one of two methods: 1. executing a back door access scheme. 2. passing an erase verify check.
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 freescale semiconductor 15-23 preliminary 15.5.1 back door access if the keyen bit is set, security can be bypassed by: 1. setting the keyacc bit in the cf m configuration re gister (cfmmcr). 2. writing the correct 8-byte back door compar ison key to the cfm ar ray at addresses 0x0000_0400 to 0x0000_0407. this operation must consist of two 32-bit writes to address 0x0000_0400 and 0x0000_0404 in that order. the two back door writ e cycles can be separated by any number of bus cycles. 3. clearing the keyacc bit. 4. if all 8 bytes written match the array contents at addresses 0x0000_0400 to 0x0000_0407, then security is bypassed until the next reset. note the security of the flash as define d by the flash secu rity longword at address 0x0000_0414 is not changed by the back door method of unsecuring the device. after the next reset the de vice is again secured and the same back door key remains in effect unless changed by progr am or erase operations. the back door method of unsecuring the device has no effect on the program and erase protections defined by the cfm protection regi ster (cfmprot). 15.5.2 erase verify check security can be disabled by verifying that the cfm array is blank. if requir ed, the mass erase command can be executed for each pair of flas h physical blocks that comprise th e array. the eras e verify command must then be executed for all flash physical blocks within the array. the cfm will be unsecured if the erase verify command determines that the entire array is bl ank. after the next reset, the security state of the cfm will be determined by the flash securi ty longword, which, after being erased, will read 0xffff_ffff, thus unsecuring the module. 15.6 reset the cfm array is not accessible for a ny operations via the address and da ta buses during reset. if a reset occurs while any command is in prog ress that command will immediatel y abort. the stat e of any longword being programmed or any eras e pages/physical blocks bei ng erased is not guaranteed. 15.7 interrupts the cfm module can request an interrupt when all co mmands are completed or when the address, data, and command buffers are empty. table 15-14 shows the cfm interrupt mechanism. table 15-14. cfm interrupt sources interrupt source interrupt flag local enable command, data and address buffers empty cbeif (cfmustat) cbeie (cfmcr)
coldfire flash module (cfm) mcf5213 reference manual, rev. 1.1 15-24 freescale semiconductor preliminary all commands are completed ccif (cfmustat) ccie (cfmcr) access error accerr (cfmustat) aeie (cfmcr) table 15-14. cfm interrupt sources interrupt source interrupt flag local enable
mcf5213 reference manual, rev. 1.1 freescale semiconductor 16-1 preliminary chapter 16 ezport ezport is a serial flash programming interface that allows the flash me mory contents on a 32 bit general purpose microcontroller to be read, erased and programmed from off- chip in a compatible format to many standalone flash memory chips. 16.1 features the ezport includes the following features: ? serial interface that is compatible with a subset of the spi format. ? able to read, erase and program flash memory. ? able to reset the micro-controller, allowing it to boot from the flash memo ry after the memory has been configured. 16.2 modes of operation the ezport can operate in one of two different modes, enabled or disabled. ? enabled when enabled, the ezport ?steals? access to th e flash memory, preventing access from other cores or peripherals. the rest of the mi cro-controller is disabled when the ezport is enabled to avoid conflicts. ? disabled when the ezport is disabled, the rest of the mi cro-controller can access flash memory as normal. figure 16-1 is a block diagram of the ezport.
ezport mcf5213 reference manual, rev. 1.1 16-2 freescale semiconductor preliminary figure 16-1. ezport block diagram 16.3 external signal description 16.3.1 overview table 16-1 contains a list of ez port external signals. 16.3.2 detailed signal descriptions 16.3.2.1 ezpck ? ezport clock serial clock for data transfers. serial data in (ezpd) and chip select (e z pcs ) are registered on the rising edge of ezpck while serial data out (ezpq) is driven on the falling edge of ezpck.the maximum frequency of the ezport clock is ha lf the system clock frequency for all commands except when executing table 16-1. signal descriptions name description i/o ezpck ezport clock input e z pcs ezport chip select input ezpd ezport serial data in input ezpq ezport serial data out output flash controller ezport flash memory micro-controller core ezport enabled ezpcs ezpck ezpd ezpq g reset controller reset reset out
ezport mcf5213 reference manual, rev. 1.1 freescale semiconductor 16-3 preliminary the read data command. when executing the read data command, the ezport clock has a maximum frequency of one eighth the system clock frequency. 16.3.2.2 e z pcs ? ezport chip select chip select for signalling the start and end of serial transfers. if e z pcs is asserted during and when the micro-controller?s reset out si gnal is negated then ezport is enabled out of reset; otherw ise it is disabled. once ezport is enabled, asserting e z pcs commences a serial data tran sfer, which continues until e z pcs is negated again.. the negation of e z pcs indicates the current command is finished and resets the ezport state machine so that it is re ady to receive the next command. 16.3.2.3 ezpd ? ezport serial data in serial data in for data transfers. serial data in (ezpd) is registered on th e rising edge of ezpck. all commands, addresses and data are shifted in most significant bit first. when ezport is driving output data on ezpq, the data shifted in ezpd is ignored. 16.3.2.4 ezpq ? ezport serial data out serial data out for data transfers. serial data out (ezpq) is driven on the falling edge of ezpck. it is tri-stated unless e z pcs is asserted and the ezport is driving data out. all data is shifted out most significant bit first. 16.4 command definition the ezport receives commands from an external device and translates those comm ands into flash memory accesses. table 16-2 lists the supported commands. table 16-2. ezport commands command description code address bytes dummy bytes data bytes compatible commands 1 1 lists the compatible commands on the st microelectronics serial flash memory parts. wren write enable 0x06 0 0 0 wren wrdi write disable 0x04 0 0 0 wrdi rdsr read status register 0x05 0 0 1 rdsr wrcr write config register 0x01 0 0 1 wrsr read read data 0x03 3 0 1+ read fast_read read data at high speed 0x0b 3 1 1+ fast_read pp page program 0x02 3 0 4 to 256 pp se sector erase 0xd8 3 0 0 se be bulk erase 0xc7 0 0 0 be reset reset chip 0xb9 0 0 0 dp
ezport mcf5213 reference manual, rev. 1.1 16-4 freescale semiconductor preliminary 16.4.1 command descriptions 16.4.1.1 write enable the write enable command sets the write enable regist er bit in the status regi ster. the write enable bit must be set for a write configurat ion register (wrcr), page program (pp), sector erase (se) or bulk erase (be) command to be accepted. the write enable register bit clears on re set, on a write disable command and at the completion of a write, program or erase command. this command should not be used if a write is already in progress. 16.4.1.2 write disable the write disable command clears the write enab le register bit in the status register. this command should not be used if a write is already in progress. 16.4.1.3 read status register the read status register command returns th e contents of the ezport status register. write in progress (wip) status flag that sets after a write configuration register (wrcr), page pr ogram (pp), sector erase (se) or bulk erase (be) command is accepted and clears once the flash memo ry erase or program is completed. only the read status register (rdsr) command is accepted while a write is in progress. 1 = write is in progress. only accept rdsr command. 0 = write is not in progress.accept any command. write enable (wen) control bit that must be set befo re a write configuration register (wrcr), page progr am (pp), sector erase (se) or bulk erase (be) command is accep ted. is set by the write enable (wren) command and cleared by reset or a write di sable (wrdi) command. it also cl ears on completion of a write, erase or program command. 1 = enables the following writ e, erase or program command. 0 = disables the following wr ite, erase or program command. configuration register loaded (crl) ezport status register 7 6 5 4 3 2 1 0 r fs wef crl wen wip w reset: 0/1 1 1 reset value reflects if flash security is enabled or disabled out of reset. 0 0 0 0 0 0 0 unimplemented or reserved.
ezport mcf5213 reference manual, rev. 1.1 freescale semiconductor 16-5 preliminary status flag that indicates if the configuration re gister has been loaded. th e configuration register initializes the flash controllers cl ock configuration register to gene rate a divided down clock from the system clock that runs at a frequency of 150khz to 200 khz. this register must be initialized before any erase or program commands are accepted. 1 = configuration register has been loade d, erase and program commands are accepted. 0 = configuration register has not been loade d, erase and program commands are not accepted. write error flag (wef) status flag that indicates if there has been an error with an erase or program instruction inside the flash controller due to attempting to program or erase a prot ected sector, or if there is an error in the flash memory after performing a bulk er ase command. the flag clears after a read status register (rdsr) command. 1 = error on previous erase/program command. 0 = no error on previous erase/program command. flash security (fs) status flag that indicates if the flash memory is in secure mode. in se cure mode, the following commands are not accepted: read (read), fast read (fast_read), page program (pp), sector erase (se). secure mode can be exited by performing a bulk erase (be) command (which erases the entire contents of the flash memory). 1 = flash is in secure mode. 0 = flash is not in secure mode. 16.4.1.4 write conf iguration register the write configuration command upda tes the flash controlle r?s clock configurati on register. the clock configuration register divides down the flash controller?s internal system clock to a 150khz to 200 khz clock. this register must be initialized before any erase or program commands are issued to the flash controller. this command should not be used if th e write error flag is se t, a write is in progress or the configuration register has already been loaded (as it is a write-once register). prdiv enables prescaler divide by 8. 1 = enables a prescaler that divides the syst em clock by 8 before it enters the divider. 0 = the system clock is fed directly into the divider. div[5:0] ezport configuration register 7 6 5 4 3 2 1 0 r w prdiv8 div[5:0] : unimplemented or reserved.
ezport mcf5213 reference manual, rev. 1.1 16-6 freescale semiconductor preliminary clock divider field. the combinati on of prdiv8 and div[5:0] effect ively divides the system clock down to a frequency be tween 150 khz and 200 khz. 16.4.1.5 read data the read data command returns data from the flash memory, starting at the address specified in the command word. data will continue being returned for as long as the ezport chip select (e z pcs ) is asserted, with the address automatically incremen ting. when the address reaches the highest flash memory address, it will wrap around to the lowest flash memory address. in this wa y, the entire contents of the flash memory can be returned by one command. for this command to return the correct data, the ezpo rt clock (ezpck) must run at no more than divide by eight of the internal system clock. this command should not be used if th e write error flag is set, or a writ e is in progress. this command is not accepted if flash security is enabled. 16.4.1.6 read data at high speed this command is identical to the read data command, except for the inclusion of a dummy byte following the address bytes and before the first data byte is returned. this allows the command to run at any frequency of the ezport cloc k (ezpck) up to and including half the internal system clock frequency of the micro-controller .this command should not be used if the write error flag is set, or a write is in progress. this command is not accepted if flash security is enabled. 16.4.1.7 page program the page program command programs locations in flash memory that have previously been erased. the starting address of the memory to program is sent after the command word and must be a 32 bit aligned address (the two lsbs must be zero). after every four bytes of data are received by the ezport, that 32 bit word is programmed into flash memory with the addr ess automatically incremen ting after each write. for this reason, the number of bytes to program must be a multiple of four. only a maximum of 256 bytes can be programmed at a time; when th e address reaches the highest addr ess within any given 256 byte space of memory, it will wrap around to the lowest address in that 256 byte space of memory. this command should not be used if the write error flag is set, a write is in progress, the write enable bit is not set or the configuration regi ster has not been written.this command is not accepted if flash security is enabled. the write error flag will set if there is an attemp t to program a protected area of the flash memory. 16.4.1.8 sector erase the sector erase command erases th e contents of a 2kbyte space of flash memory. the three byte address sent after the command byte can be a ny address within the space to erase.
ezport mcf5213 reference manual, rev. 1.1 freescale semiconductor 16-7 preliminary this command should not be used if the write error flag is set, a write is in progress, the write enable bit is not set or the configuration regist er has not been written. this command is not accepted if flash security is enabled. the write error flag will set if there is an atte mpt to erase a protected area of the flash memory. 16.4.1.9 bulk erase the bulk erase command erases the entire contents of flash memory, ignoring any protected sectors or flash security. the write error flag will set if the bulk erase command does not successfully erase the entire contents of flash me mory. flash security will be disabled if the bulk erase command is followed by a reset chip command. this command should not be used if the write error flag is set, a write is in progress, the write enable bit is not set or the configuration register has not been written. 16.4.1.10 reset chip the reset chip command forces the chip into th e reset state. if the ezport chip select (e z pcs ) pin is asserted at the end of the reset period then ezpo rt will be enabled, otherwise it will be disabled. this command allows the chip to boot up from flash memory after it has been programmed by an external source. this command should not be used if a write is in progress. 16.5 functional description the ezport provides a simple interf ace to connect an external device to the flash memory on board a 32 bit micro-controller. th e interface itself is compatible with the spi interface (with th e ezport operating as a slave) running in either of the two following modes with data transmitted mo st significant bit first: ? cpol = 0, cpha = 0 ? cpol = 1, cpha = 1 commands are issued by the external device to erase, program or read the cont ents of the flash memory. the serial data out from th e ezport is tri-stated unle ss data is being driven, allo wing the signal to be shared among several different ezpo rt (or compatible) devices in parallel , provided they have different chip selects. 16.6 initialization/application information prior to issuing any program or eras e commands, the clock configuration register must be written to set the flash state machine clock (fclk). the flash cont roller module runs at the system clock frequency divide by 2, but fclk must be divided down from this frequency to a frequency between 150 khz and 200 khz. use the following procedure to set the prdi v8 and div[5:0] bits in the clock configuration register.
ezport mcf5213 reference manual, rev. 1.1 16-8 freescale semiconductor preliminary 1. if f sys is greater than 25.6 mhz, prdiv8 = 1; otherwise prdiv8 = 0. 2. determine div[5:0] by using the following equation. keep only the in teger portion of the result and discard any fraction. do not round the result. 3. thus the flash state machine clock will be: so, for fsys = 66 mhz, wr iting 0x54 to the clock configuration regi ster will set fclk to 196.43 khz which is a valid frequency for the timi ng of program and erase operations. for proper program and erase operati ons, it is critical to set fclk between 150 khz and 200 khz. array damage due to overstress can occur when fclk is less than 150 khz. incomplete programming and erasure can occur when fclk is greater than 200 khz. div fsys 2x200khzx 1 prdiv8x7 () + () ------------------------------------------------------------------------------ - = fclk fsys 2x div 1 + () x 1 prdiv8x7 () + () ------------------------------------------------------------------------------------ =
mcf5213 reference manual, rev. 1.1 freescale semiconductor 17-1 preliminary chapter 17 programmable interrupt timer modules (pit0?pit1) 17.1 introduction this chapter describes the opera tion of the two programmable in terrupt timer modules, pit0?pit1. 17.1.1 overview each pit is a 16-bit timer that pr ovides precise interrupts at regular intervals with minimal processor intervention. the timer can either count down from the value written in th e modulus register, or it can be a free-running down-counter. 17.1.2 block diagram figure 17-1. pit block diagram 17.1.3 low-power mode operation this subsection describes the operation of the pi t modules in low-power modes and debug mode of operation. low-power modes are describe d in the power management module, chapter 8, ?power management.? table 17-1 shows the pit module operation in low- power modes, and how it can exit from each mode. internal bus clock (f sys/ ) 16-bit pmr n 16-bit pit counter count = 0 internal bus 16-bit pcntr n internal bus en ovw doze dbg prescaler pre[3:0] rld pif pie load counter to interrupt controller
programmable interrupt timer modules (pit0?pit1) mcf5213 reference manual, rev. 1.1 17-2 freescale semiconductor preliminary note the low-power interrupt control regist er (lpicr) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode. in wait mode, the pit module continue s to operate as in run mode and can be configured to exit the low-power mode by generati ng an interrupt request. in doze mode with the pcsr n [doze] bit set, pit module operation stops. in doze mode with the pcsr n [doze] bit cleared, doze mode does not affect pit operation. when doze mode is exited, the pit continues to operate in the state it was in prior to doze mode. in stop mode, the internal bus clock is absent, and pit module operation stops. in debug mode with the pcsr n [dbg] bit set, pit module operation stops. in debug mode with the pcsr n [dbg] bit cleared, debug mode does not affect pit operation. when debug mode is exited, the pit continues to operate in its pr e-debug mode state, but any update s made in debug mode remain. 17.2 memory map/register definition this section contains a memory map, shown in table 17-2 , and describes the register structure for pit0?pit1. table 17-1. pit module operation in low-power modes low-power mode pit operation mode exit wait normal n/a doze normal if pcsr n [doze] cleared, stopped otherwise any interrupt at or above level in lpicr, will exit doze mode if pcsr n [doze] is set. otherwise interrupt assertion has no effect. stop stopped no debug normal if pcsr n [dbg] cleared, stopped otherwise no. any interrupt will be serviced upon normal exit from debug mode table 17-2. programmable interrupt timer modules memory map ipsbar offset register access 1 reset value section/page pit 0 pit 1 supervisor access only registers 2 0x15_0000 0x16_0000 pit control and status register (pcsr n ) r/w 0x0000 17.2.1/17-3 0x15_0002 0x16_0002 pit modulus register (pmr n ) r/w 0x0000 17.2.2/17-5
programmable interrupt timer modules (pit0?pit1) mcf5213 reference manual, rev. 1.1 freescale semiconductor 17-3 preliminary 17.2.1 pit control and st atus register (pcsr n ) the pcsr n registers configure the corresponding timer?s operation. user/supervisor access registers 0x15_0004 0x16_0004 pit count register (pcntr n ) r 0xffff 17.2.3/17-5 1 accesses to reserved address locations have no effect and result in a cycle termination transfer error. 2 user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. ipsbar offset: 0x15_0000 (pcsr0) 0x16_0000 (pcsr 1 ) access: supervisor read/write 1514131211109876543210 r0000 pre 0 doze dbg ovw pie pif rld en w w1c reset000000000 0000000 figure 17-2. pit control and status register (pcsr n ) table 17-2. programmable interrupt timer modules memory map (continued) ipsbar offset register access 1 reset value section/page pit 0 pit 1
programmable interrupt timer modules (pit0?pit1) mcf5213 reference manual, rev. 1.1 17-4 freescale semiconductor preliminary table 17-3. pcsr n field descriptions field description 15?12 reserved, should be cleared. 11?8 pre prescaler. the read/write prescaler bits select the internal bus cl ock divisor to generate the pit clock. to accurately predict the timing of the next count, ch ange the pre[3:0] bits only when the enable bit (en) is clear. changing pre[3:0] resets the prescaler counter. system reset and th e loading of a new value into the counter also reset the prescaler counter. setting the en bit and writing to pre[3: 0] can be done in this same write cycle. clearing the en bit stops the prescaler counter. 7 reserved, should be cleared. 6 doze doze mode bit. the read/write doze bit controls the fu nction of the pit in doze mode. reset clears doze. 0 pit function not affected in doze mode 1 pit function stopped in doze mode. when doze mode is ex ited, timer operation continues from the state it was in before entering doze mode. 5 dbg debug mode bit. controls the functi on of the pit in halted/debug mode. reset clears dbg. during debug mode, register read and write accesses functi on normally. when debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain. 0 pit function not affected in debug mode 1 pit function stopped in debug mode note: changing the dbg bit from 1 to 0 during debug mode starts the pit timer. likewise, changing the dbg bit from 0 to 1 during debug mode stops the pit timer. 4 ovw overwrite. enables writing to pmr n to immediately overwrite the value in the pit counter. 0 value in pmr n replaces value in pit counter when count reaches 0x0000. 1 writing pmr n immediately replaces value in pit counter. 3 pie pit interrupt enable. this read/write bit enables the pif flag to generate interrupt requests. 0 pif interrupt requests disabled 1 pif interrupt requests enabled 2 pif pit interrupt flag. this read/write bit is set when the pit counter reaches 0x0000. clear pif by writing a 1 to it or by writing to pmr. writing 0 has no effect. reset clears pif. 0 pit count has not reached 0x0000. 1 pit count has reached 0x0000. pre internal bus clock divisor decimal equivalent 0000 2 0 1 0001 2 1 2 0010 2 2 4 ... ... ... 1101 2 13 8192 1110 2 14 16384 1111 2 15 32768
programmable interrupt timer modules (pit0?pit1) mcf5213 reference manual, rev. 1.1 freescale semiconductor 17-5 preliminary 17.2.2 pit modulus register (pmr n ) the 16-bit read/write pmr n contains the timer modulus value that is loaded into the pit counter when the count reaches 0x0000 and the pcsr n [rld] bit is set. when the pcsr n [ovw] bit is set, pmr n is transparent, and the value written to pmr n is immediately loaded into the pit counter. the prescaler counter is reset (0xffff) anytime a new value is loaded into the pit counter and also during reset. reading the pmr n returns the value written in the modulus latch. reset initializes pmr n to 0xffff. 17.2.3 pit count register (pcntr n ) the 16-bit, read-only pcntr n contains the counter value. reading the 16-bit counter wi th two 8-bit reads is not guaranteed to be coherent. writing to pcntr n has no effect, and write cycles are terminated normally. 17.3 functional description this section describes th e pit functional operation. 1 rld reload bit. the read/write reload bit enables loading the value of pmr n into the pit counter when the count reaches 0x0000. 0 counter rolls over to 0xffff on count of 0x0000 1 counter reloaded from pmr n on count of 0x0000 0 en pit enable bit. enables pit operation. when the pit is di sabled, the counter and prescaler are held in a stopped state. this bit is read anytime, write anytime. 0 pit disabled 1 pit enabled ipsbar offset: 0x15_0002 (pmr0) 0x16_0002 (pmr 1 ) access: supervisor read/write 1514131211109876543210 r pm w reset000000000 0000000 figure 17-3. pit modulus register (pmr n ) ipsbar offset: 0x15_0004 (pcntr0) 0x16_0004 (pcntr 1 ) access: user read only 1514131211109876543210 rpc w reset111111111 1111111 figure 17-4. pit count register (pcntr n ) table 17-3. pcsr n field descriptions (continued) field description
programmable interrupt timer modules (pit0?pit1) mcf5213 reference manual, rev. 1.1 17-6 freescale semiconductor preliminary 17.3.1 set-and-forget timer operation this mode of operation is selected when the rld bit in the pcsr register is set. when the pit counter reaches a count of 0x0000, the pif flag is set in pcsr n . the value in the modulus register is loaded into the counter, and the c ounter begins decrementing toward 0x0000. if the pcsr n [pie] bit is set, the pif flag issues an interrupt request to the cpu. when the pcsr n [ovw] bit is set, the counter can be directly initialized by writing to pmr n without having to wait for the count to reach 0x0000. figure 17-5. counter reloading from the modulus latch 17.3.2 free-running timer operation this mode of operation is selected when the pcsr n [rld] bit is clear. in this mode, the counter rolls over from 0x0000 to 0xffff without reloading from th e modulus latch and c ontinues to decrement. when the counter reaches a count of 0x0000, the pcsr n [pif] flag is set. if the pcsr n [pie] bit is set, the pif flag issues an interr upt request to the cpu. when the pcsr n [ovw] bit is set, the counter can be directly initialized by writing to pmr n without having to wait for the count to reach 0x0000. figure 17-6. counter in free-running mode 17.3.3 timeout specifications the 16-bit pit counter and pr escaler supports different timeout periods . the prescaler divides the internal bus clock period as selected by the pcsr n [pre] bits. the pmr n [pm] bits select the timeout period. 0x0002 0x0001 0x0000 0x0005 0x0005 pit clock counter modulus pif 0x0002 0x0001 0x0000 0xffff 0x0005 pit clock counter modulus pif
programmable interrupt timer modules (pit0?pit1) mcf5213 reference manual, rev. 1.1 freescale semiconductor 17-7 preliminary 17.3.4 interrupt operation table 17-4 shows the interrupt request generated by the pit. the pif flag is set when the pit counter reaches 0x0000. the pie bit enables the pif flag to generate interrupt requests. clear pif by writing a 1 to it or by writing to the pmr. table 17-4. pit interrupt requests interrupt request flag enable bit timeout pif pie
programmable interrupt timer modules (pit0?pit1) mcf5213 reference manual, rev. 1.1 17-8 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-1 preliminary chapter 18 general purpose timer module (gpt) 18.1 introduction this device has one 4-channel gene ral purpose timer module (gpt). it c onsists of a 16-bit counter driven by a 7-stage programmable prescaler. a timer overflow function allows so ftware to extend the timing capabil ity of the system beyond the 16-bit range of the counter. each of the four timer channels can be config ured for input capture, which can capture the time of a selected tran sition edge, or for output compare, which can generate output waveforms and timer software delays. these f unctions allow simultaneous input waveform measurements and output waveform generation. additionally, one of the channels, channel 3, can be configured as a 16-bit pulse accumulator that can operate as a simple event counter or as a gated tim e accumulator. the pulse accumulator uses the gpt channel 3 input/output pin in either even t mode or gated time accumulation mode. 18.2 features features of the genera l-purpose timer include: ? four 16-bit input captur e/output compare channels ? 16-bit architecture ? programmable prescaler ? pulse widths variable fr om microseconds to seconds ? single 16-bit pulse accumulator ? toggle-on-overflow feature for pulse-w idth modulator (pwm) generation ? external timer cloc k input (synca/syncb)
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-2 freescale semiconductor preliminary 18.3 block diagram figure 18-1. gpt block diagram prescaler channel 0 pt0 16-bit counter system logic pr[2:0] divide-by-64 gptc0h:gptc0l edge detect gptpacnth:gptpacntl paov f pedge paov i pa m o d pa e 16-bit comparator gptcnth:gptcntl 16-bit latch channel 1 gptc1h:gptc1l 16-bit comparator 16-bit latch 16-bit counter interrupt logic tof toi c0f c1f edge detect pt1 logic edge detect cxf channel 2 channel3 gptc3h:gptc3l 16-bit comparator 16-bit latch c3f pt3 logic edge detect ios0 ios1 ios3 om:ol0 tov0 om:ol1 tov1 om:ol3 tov3 edg1a edg1b edg3a edg3b edg0a edg0b tcre channel 3 output compare pa i f clear counter pa i f pa i interrupt logic cxi interrupt request interrupt request paov f ch. 3 compare ch.3 capture ch. 1 capture mux clk[1:0] pac l k paclk/256 paclk/65536 pac l k paclk/256 paclk/65536 te clock ch. 1 compare ch. 0 compare ch. 0 capture pa input mux gptx0 pin gptx1 pin gptx3 pin x syncx pin divide by 2 divide by 2 system clock
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-3 preliminary 18.4 low-power mode operation this subsection describes the operation of the ge neral purpose time module in low-power modes and halted mode of operation. low-pow er modes are described in chapter 7, ?power management .? table 18-1 shows the general purpose timer module opera tion in the low-power modes, and shows how this module may facilitate exit from each mode. table 18-1. watchdog module operation in low-power modes general purpose timer opera tion stops in stop mode. when stop mode is exited, the general purpose timer continues to operate in its pre-stop mode state. 18.5 signal description table 18-2 provides an overview of the signal properties. 18.5.1 gpt[2:0] the gpt[2:0] pins are for channel 2?0 input capt ure and output compare functions. these pins are available for general-purpose i nput/output (i/o) when not conf igured for timer functions. 18.5.2 gpt3 the gpt3 pin is for channel 3 input capture and out put compare functions or for the pulse accumulator input. this pin is available fo r general-purpose i/o when not c onfigured for timer functions. low-power mode watchdog operation mode exit wait normal no doze normal no stop stopped no halted normal no table 18-2. signal properties pin name gptport register bit function reset state pull-up gpt0 portt n 0 gpt channel 0 ic/oc pin input active gpt1 portt n 1 gpt channel 1 ic/oc pin input active gpt2 portt n 2 gpt channel 2 ic/oc pin input active gpt3 portt n 3 gpt channel 3 ic/oc or pa pin input active sync n porte[3:0] 1 1 synca is available on either porte3 or porte1 ; syncb is available on either porte2 or porte0. gpt counter synchronization input active
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-4 freescale semiconductor preliminary 18.5.3 sync n the sync n pin is for synchronization of th e timer counter. it can be used to synchronize the counter with externally-timed or clocked events. a hi gh signal on this pin clears the counter. 18.6 memory map and registers table 20-3 shows the memory map of the gpt module. the base address for gpt is ipsbar + 0x1a_0000. note reading reserved or unimplemented lo cations returns zer oes. writing to reserved or unimplemented locations has no effect. table 18-3. gpt module memory map ipsbar offset bits 7?0 access 1 0x1a_0000 gpt ic/oc select register (gptios) s 0x1a_0001 gpt compare force register (gptcforc) s 0x1a_0002 gpt output compare 3 mask register (gptoc3m) s 0x1a_0003 gpt output compare 3 data register (gptoc3d) s 0x1a_0004 gpt counter register (gptcnt) s 0x1a_0005 gpt system control register 1 (gptscr1) s 0x1a_0006 reserved 2 ? 0x1a_0007 gpt toggle-on-overflow register (gpttov) s 0x1a_0008 gpt control register 1 (gptctl1) s 0x1a_0009 reserved (2) ? 0x1a_000a gpt control register 2 (gptctl2) s 0x1a_000b gpt interrupt enable register (gptie) s 0x1a_000c gpt system control register 2 (gptscr2) s 0x1a_000d gpt flag register 1 (gptflg1) s 0x1a_000e gpt flag register 2 (gptflg2) s 0x1a_000f gpt channel 0 register high (gptc0h) s 0x1a_0010 gpt channel 0 register low (gptc0l) s 0x1a_0011 gpt channel 1 register high (gptc1h) s 0x1a_0012 gpt channel 1 register low (gptc1l) s 0x1a_0013 gpt channel 2 register high (gptc2h) s 0x1a_0014 gpt channel 2 register low (gptc2l) s 0x1a_0015 gpt channel 3 register high (gptc3h) s
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-5 preliminary 18.6.1 gpt input capture/output compare select register (gptios) 0x1a_0016 gpt channel 3 register low (gptc3l) s 0x1a_0017 pulse accumulator control register (gptpactl) s 0x1a_0018 pulse accumulator flag register (gptpaflg) s 0x1a_0019 pulse accumulator counter register high (gptpacnth) s 0x1a_001a pulse accumulator count er register low (gptpacntl) s 0x1a_001b reserved (2) ? 0x1a_001c gpt port data register (gptport) s 0x1a_001d gpt port data direction register (gptddr) s 0x1a_001e gpt test register (gpttst) s 1 s = cpu supervisor mode access only. 2 writes have no effect, reads return 0s, and the access terminates without a transfer error exception. 743 0 field ? ios reset 0000_0000 r/w r/w address ipsbar + 0x00_0400, 0x00_0440, 0x00_0480, 0x00_04c0 figure 18-2. gpt input capture/output compare select register (gptios) table 18-4. gptios field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 ios i/o select. the ios[3:0] bits enable input capture or output compare operation for the corresponding timer channels. these bits are read anytime (always read 0x00), write anytime. 1 output compare enabled 0 input capture enabled table 18-3. gpt module memory map (continued) ipsbar offset bits 7?0 access 1
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-6 freescale semiconductor preliminary 18.6.2 gpt compare force register (gpcforc) note a successful channel 3 output compar e overrides any compare on channels 2:0. for each oc3m bit that is set, the output compare action reflects the corresponding oc3d bit. 18.6.3 gpt output compare 3 mask register (gptoc3m) 743 0 field ? foc reset 0000_0000 r/w r/w address ipsbar + 0x00_0401, 0x00_0441, 0x00_0481, 0x00_04c1 figure 18-3. gpt input compare force register (gpcforc) table 18-5. gptcforc field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 foc force output compare.setting an foc bit causes an immediate output compare on the corresponding channel. forcing an ou tput compare does not set the output compare flag. these bits are read anytime, write anytime. 1 force output compare 0 no effect 743 0 field ? oc3m reset 0000_0000 r/w r/w address ipsbar + 0x00_0402, 0x00_0442, 0x00_0482, 0x00_04c2 figure 18-4. gpt output compare 3 mask register (gptoc3m)
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-7 preliminary 18.6.4 gpt output compare 3 data register (gptoc3d) note a successful channel 3 output compare overrides any channel 2:0 compares. for each oc3m bit that is set, the output compare action reflects the corresponding oc3d bit. 18.6.5 gpt counter register (gptcnt) table 18-6. gptoc3m field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 oc3m output compare 3 mask. setting an oc 3m bit configures the corresponding portt n pin to be an output. oc3m n makes the gpt port pin an output regardless of the data direction bit when the pin is configured for output compare (iosx = 1). the oc3m n bits do not change the state of the portt n ddr bits. these bits are read anytime, write anytime. 1 corresponding portt n pin configured as output 0 no effect 743 0 field ? oc3d reset 0000_0000 r/w r/w address ipsbar + 0x00_0403, 0x00_0443, 0x00_0483, 0x00_04c3 figure 18-5. gpt output compare 3 data register (gptoc3d) table 18-7. gptoc3d field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 oc3d output compare 3 data. when a successful channel 3 output compare occurs, these bits transfer to the portt n data register if the corresponding oc3m n bits are set. these bits are read an ytime, write anytime. 15 0 field cntr reset 0000_0000_0000_0000 r/w read only address ipsbar + 0x00_0404, 0x00_0444, 0x00_0484, 0x00_04c4 figure 18-6. gpt counter register (gptcnt)
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-8 freescale semiconductor preliminary 18.6.6 gpt system control register 1 (gptscr1) table 18-8. gptcnt field descriptions bit(s) name description 15?0 cntr read-only field that provides the cu rrent count of the timer counter. to ensure coherent reading of the timer counter, su ch that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. a write to gptcnt may have an extra cycle on the first count because the write is not synchronized with the prescale r clock. the write occurs at least one cycle before the synchronization of the prescaler clock. these bits are read anytime. they should be written to only in test (special) mode; writing to them has no effect in normal modes. 7 6543 0 field gpten ? tffca ? reset 0000_0000 r/w r/w address ipsbar + 0x00_0405, 0x00_0445, 0x00_0485, 0x00_04c5 figure 18-7. gpt system control register 1 (gptscr1) table 18-9. gptscr1 field descriptions bit(s) name description 7 gpten enables the general purpose timer. when the timer is disabled, only the registers are accessible. clearing gpten reduces power consumption. these bits are read anytime, write anytime. 1 gpt enabled 0 gpt and gpt counter disabled 6?5 ? reserved, should be cleared. 4 tffca timer fast flag clear all. en ables fast clearing of the main timer interrupt flag registers (gptflg1 and gptflg2) and the pa flag register (gptpaflg). tffca eliminates the software overhead of a separate clear sequence. see figure 18-8 . when tffca is set: an input capture read or a write to an output compare channel clears the corresponding channel flag, cxf. any access of the gpt count regist ers (gptcnth/l) clears the tof flag. any access of the pa counter register s (gptpacnt) clears both the paovf and paif flags in gptpaflg. writing logic 1s to the flags clea rs them only when tffca is clear. 1 fast flag clearing 0 normal flag clearing 3?0 ? reserved, should be cleared.
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-9 preliminary figure 18-8. fast clear flag logic 18.6.7 gpt toggle-on-overflow register (gpttov) 18.6.8 gpt control register 1 (gptctl1) 7 6543 0 field ? tov reset 0000_0000 r/w r/w address ipsbar + 0x00_0408, 0x00_0448 figure 18-9. gpt toggle-on-overflow register (gpttov) table 18-10. gpttov field description bit(s) name description 7?4 ? reserved, should be cleared. 3?0 tov toggles the output compare pin on overflow for each channel. this feature only takes effect when in output compare mode. when set, it takes precedence over forced output compare but not channel 3 override ev ents. these bits are read anytime, write anytime. 1 toggle output compare pin on overflow feature enabled 0 toggle output compare pin on overflow feature disabled 7 654321 0 field om3 ol3 om2 ol2 om1 ol1 om0 ol0 reset 0000_0000 r/w r/w address ipsbar + 0x00_0409, 0x00_0449 figure 18-10. gpt control register 1 (gptctl1) clear write gptc n registers read gptc n registers tffca data bit n write gptflg1 register c n f c n f flag
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-10 freescale semiconductor preliminary 18.6.9 gpt control register 2 (gptctl2) 18.6.10 gpt interrupt enable register (gptie) table 18-11. gptcl1 field descriptions bit(s) name description 7?0 omx/olx output mode/output leve l. selects the output action to be taken as a result of a successful output compare on each channel. when either om n or ol n is set and the ios n bit is set, the pin is an output regardle ss of the state of the corresponding ddr bit. these bits are read anytime, write anytime. 00 gpt disconnected from output pin logic 01 toggle oc n output line 10 clear oc n output line 11 set oc n line note: channel 3 shares a pin with the pulse accumulator input pin. to use the pai input, clear both the om3 and ol3 bits and clear the oc3m3 bit in the output compare 3 mask register. 7 654321 0 field edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a reset 0000_0000 r/w r/w address ipsbar + 0x00_040b, 0x00_044b figure 18-11. gpt control register 2 (gptctl2) table 18-12. gptlctl2 field descriptions bit(s) name description 7?0 edg n [b:a] input capture edge control. configures the input captur e edge detector circuits for each channel. these bits are read anytime, write anytime. 00 input capture disabled 01 input capture on rising edges only 10 input capture on falling edges only 11 input capture on any edge (rising or falling) 7 6543 0 field ? ci reset 0000_0000 r/w r/w address ipsbar + 0x00_040c, 0x00_044c figure 18-12. gpt interrupt enable register (gptie)
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-11 preliminary 18.6.11 gpt system control register 2 (gptscr2) table 18-13. gptie field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 c n i channel interrupt enable. enables the c[3:0]f flags in gpt flag register 1 to generate interrupt requests for each channel. these bits are read anytime, write anytime. 1 corresponding channel interrupt requests enabled 0 corresponding channel interrupt requests disabled 7 65432 0 field toi ? pupt rdpt tcre pr reset 0000_0000 r/w r/w address ipsbar + 0x00_040d, 0x00_044d figure 18-13. gpt system control register 2 (gptscr2) table 18-14. gptscr2 field descriptions bit(s) name description 7 toi enables timer overflow interrupt requests. 1 overflow interrupt requests enabled 0 overflow interrupt requests disabled 6 ? reserved, should be cleared. 5 pupt enables pull-up resistors on the gpt po rts when the ports are configured as inputs. 1 pull-up resistors enabled 0 pull-up resistors disabled 4 rdpt gpt drive reduction. reduces the output driver size. 1 output drive reduction enabled 0 output drive reduction disabled 3 tcre enables a counter reset after a channel 3 compare. 1 counter reset enabled 0 counter reset disabled note: when the gpt channel 3 registers co ntain 0x0000 and tcre is set, the gpt counter registers remain at 0x0000 all the time. when the gpt channel 3 registers contain 0xffff and tcre is set, tof does not get set even though the gpt counter registers go from 0xffff to 0x0000.
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-12 freescale semiconductor preliminary 18.6.12 gpt flag register 1 (gptflg1) 18.6.13 gpt flag register 2 (gptflg2) 2?0 pr n prescaler bits. select the prescaler divisor for the gpt counter. 000 prescaler divisor 1 001 prescaler divisor 2 010 prescaler divisor 4 011 prescaler divisor 8 100 prescaler divisor 16 101 prescaler divisor 32 110 prescaler divisor 64 111 prescaler divisor 128 note: the newly selected prescaled clock does not take effect until the next synchronized edge of the prescaled clock w hen the clock count transitions to 0x0000.) 7 6543 0 field ? cf reset 0000_0000 r/w r/w address ipsbar + 0x00_040e, 0x00_044e figure 18-14. gpt flag register 1 (gptflg1) table 18-15. gptflg1 field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 c n f channel flags. a channel flag is set when an input capture or output compare event occurs. these bits are read anytime, write an ytime (writing 1 clears the flag, writing 0 has no effect). note: when the fast flag clear all bit, gpts cr1[tffca], is set, an input capture read or an output compare write clears the corresponding channel flag. when a channel flag is set, it does not inhibit subsequen t output compares or input captures. 7 6543 0 field tof ? cf reset 0000_0000 r/w r/w address ipsbar + 0x00_040f, 0x00_044f figure 18-15. gpt flag register 2 (gptflg2) table 18-14. gptscr2 field descriptions (continued) bit(s) name description
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-13 preliminary note: when the fast flag clear all bit, gptscr1[tffca], is se t, any access to the gpt coun ter registers clears gpt flag register 2. 18.6.14 gpt channel registers (gptc n ) table 18-16. gptflg2 field descriptions bit(s) name description 7 tof timer overflow flag. set when the gpt coun ter rolls over from 0x ffff to 0x0000. if the toi bit in gptscr2 is also set, tof ge nerates an interrupt request. this bit is read anytime, write anytime (writing 1 clears the flag, and writing 0 has no effect). 1 timer overflow 0 no timer overflow note: when the gpt channel 3 registers cont ain 0xffff and tcre is set, tof does not get set even though the gpt counter r egisters go from 0xffff to 0x0000. when tof is set, it does not inhibit subsequent overflow events. 6?4 ? reserved, should be cleared. 3?0 c n f channel flags. a channel flag is set when an input capture or output compare event occurs. these bits are read anytime, write an ytime (writing 1 clears the flag, writing 0 has no effect). 15 0 field ccnt reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x00_0410, 0x0 0_0412, 0x00_0414, 0x00_0416, 0x1b_0010, 0x1b_0012, 0x1b_0014, 0x1b_0016 figure 18-16. gpt channel[0:3] register (gptc n ) table 18-17. gptc n field descriptions bit(s) name description 15?0 ccnt when a channel is configured for input capture (ios n = 0), the gpt channel registers latch the value of the free-running counter when a defined transition occurs on the corresponding input capture pin. when a channel is configured for output compare (ios n = 1), the gpt channel registers contain the output compare value. to ensure coherent reading of the gpt counte r, such that a timer rollover does not occur between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. these bits are read anytim e, write anytime (for the output compare channel); writing to the input capture channel has no effect.
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-14 freescale semiconductor preliminary 18.6.15 pulse accumulator co ntrol register (gptpactl) 7 6543 0 field ? pae pamod pedge clk paovi pai reset 0000_0000 r/w r/w address ipsbar + 0x 00_0418, 0x1b_0018 figure 18-17. pulse accumulator control register (gptpactl) table 18-18. gptpactl field descriptions bit(s) name description 7 ? reserved, should be cleared. 6 pae enables the pulse accumulator. 1 pulse accumulator enabled 0 pulse accumulator disabled note: the pulse accumulator can operate in event mode even when the gpt enable bit, gpten, is clear. 5 pamod pulse accumulator mode. selects event counter mode or gated time accumulation mode. 1 gated time accumulation mode 0 event counter mode 4 pedge pulse accumulator edge. selects falling or rising edges on the pai pin to increment the counter. in event counter mode (pamod = 0): 1 rising pai edge increments counter 0 falling pai edge increments counter in gated time accumulati on mode (pamod = 1): 1 low pai input enables divide-by-64 clock to pulse accumulator and trailing rising edge on pai sets paif flag. 0 high pai input enables divide-by-64 clock to pulse accumulator and trailing falling edge on pai sets paif flag. note: the timer prescaler generates the divide-by-64 clock. if the timer is not active, there is no divide-by-64 clock. to operate in gated time accumulation mode: 1. apply logic 0 to rsti pin. 2. initialize registers for pulse accumulator mode test. 3. apply appropriate level to pai pin. 4. enable gpt. 3?2 clk select the gpt counter input clock. changing the clk bits causes an immediate change in the gpt counter clock input. 00 gpt prescaler clock (when pae = 0, the gpt prescaler clock is always the gpt counter clock.) 01 paclk 10 paclk/256 11 paclk/65536
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-15 preliminary 18.6.16 pulse accumulator flag register (gptpaflg) note when the fast flag clear all enable bit, gptscr1[tffca], is set, any access to the pulse accumulator counter regist ers clears all the flags in gptpaflg. 1 paovi pulse accumulator overflow interrupt enable. enables the paovf flag to generate interrupt requests. 1 paovf interrupt requests enabled 0 paovf interrupt requests disabled 0 pai pulse accumulator input interrupt enable. enables the paif flag to generate interrupt requests. 1 paif interrupt requests enabled 0 paif interrupt requests disabled 7210 field ? paovf paif reset 0000_0000 r/w r/w address ipsbar + 0x 00_0419, 0x1b_0019 figure 18-18. pulse accumulator flag register (gptpaflg) table 18-19. gptpaflg field descriptions bit(s) name description 7?2 ? reserved, should be cleared. 1 paovf pulse accumulator overflow flag. set when the 16-bit pulse accumulator rolls over from 0xffff to 0x0000. if the gptpactl[paovi] bit is also set, paovf generates an interrupt request. clear paovf by writing a 1 to it. this bit is read anytime, write anytime. (writing 1 clears t he flag; writing 0 has no effect.) 1 pulse accumulator overflow 0 no pulse accumulator overflow 0 paif pulse accumulator input flag. set when the selected edge is detec ted at the pai pin. in event counter mode, the event edge sets paif. in gated time accumulation mode, the trailing edge of the gate signal at the pai pin sets paif. if the pai bit in gptpactl is also set, paif generates an interrupt request. clear paif by writing a 1 to it. 1 active pai input 0 no active pai input table 18-18. gptpactl field descriptions (continued) bit(s) name description
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-16 freescale semiconductor preliminary 18.6.17 pulse accumulator counter register (gptpacnt) 18.6.18 gpt port data register (gptport) 15 0 field pacnt reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x00_041a, 0x1b_001b figure 18-19. pulse accumulator counter register (gptpacnt) table 18-20. gptpacr field descriptions bit(s) name description 15?0 pacnt contains the number of active input edges on the pai pin since the last reset. note: reading the pulse accumulator counter registers immediately after an active edge on the pai pin may miss the last count since the input first has to be synchronized with the bus clock. to ensure coherent reading of the pa c ounter, such that the counter does not increment between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. these bits ar e read anytime, write anytime. 7 6543 0 field ? portt reset 0000_0000 r/w r/w address ipsbar + 0x00_041d, 0x1b_001d figure 18-20. gpt port data register (gptport) table 18-21. gptport field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 portt gpt port input capture/output compare data. data written to gptport is buffered and drives the pins only when they are configured as general-purpose outputs. reading an input (ddr bit = 0) reads the pin state; reading an output (ddr bit = 1) reads the latched value. writing to a pin configured as a gpt output does not change the pin state. these bits are read anytime (read pin state when corresponding portt n bit is 0, read pin driver state when corresponding gptddr bit is 1), write anytime.
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-17 preliminary 18.6.19 gpt port data di rection register (gptddr) 18.7 functional description the general purpose timer (gpt) module is a 16-bit, 4-channel timer with input capture and output compare functions and a pulse accumulator. 18.7.1 prescaler the prescaler divides the module clock by 1 or 16 . th e pr[2:0] bits in gptscr2 select the prescaler divisor. 18.7.2 input capture clearing an i/o select bit, ios n , configures channel n as an input capture cha nnel. the input capture function captures the time at which an external event oc curs. when an active edge occurs on the pin of an input capture channel, the timer tr ansfers the value in the gpt counter into the gpt channel registers, gptc n . the minimum pulse width for the input captur e input is greater th an two module clocks. the input capture function does not for ce data direction. the gpt port data direction register controls the data direction of an input capture pin. pin conditions such as risi ng or falling edges can trigger an input capture only on a pin configured as an input. an input capture on channel n sets the c n f flag. the c n i bit enables the c n f flag to generate interrupt requests. 7 6543 0 field ? ddrt gpt function ? ic/oc pulse accumulator function ? pai ? reset 0000_0000 r/w r/w address ipsbar + 0x00_041e, 0x1b_001e figure 18-21. gpt port data direction register (gptddr) table 18-22. gptddr field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 ddrt control the port logic of portt n . reset clears the portt n data direction register, configuring all gpt port pins as inputs. thes e bits are read anytime, write anytime. 1 corresponding pin configured as output 0 corresponding pin configured as input
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-18 freescale semiconductor preliminary 18.7.3 output compare setting an i/o select bit, ios n , configures channel n as an output compare channel. the output compare function can generate a periodic pul se with a programmable polarity, duration, and frequency. when the gpt counter reaches the value in the channel register s of an output compare channel, the timer can set, clear, or toggle the channel pin. an output compar e on channel n sets the c n f flag. the c n i bit enables the c n f flag to generate interrupt requests. the output mode and level bits, om n and ol n , select, set, clear, or toggl e on output compare. clearing both om n and ol n disconnects the pin from the output logic. setting a force output compare bit, foc n , causes an output compare on channel n . a forced output compare does not set the channel flag. a successful output compare on channel 3 overrid es output compares on all other output compare channels. a channel 3 output compare can cause bits in the output compare 3 data register to transfer to the gpt port data register, depending on the output comp are 3 mask register. the output compare 3 mask register masks the bits in the output compare 3 data register. the gpt counter reset enable bit, tcre, enables channel 3 output compares to reset the gp t counter. a channel 3 output compare can reset the gpt counter even if the oc3/pai pin is being used as the pulse accumulator input. an output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. writing to the portt n bit of an output compare pin does not aff ect the pin state. the value written is stored in an internal latch. when the pin becomes available for gene ral-purpose output, the last value written to the bit appears at the pin. 18.7.4 pulse accumulator the pulse accumulator (pa) is a 16-bit counter that can operate in two modes: 1. event counter mode: counts edge s of selected polarity on the pulse accumulator input pin, pai 2. gated time accumulation mode: count s pulses from a divide-by-64 clock the pa mode bit, pamod, selects the mode of operation. the minimum pulse width for the pai input is greater than two module clocks. 18.7.5 event counter mode clearing the pamod bit configures the pa for event counter operation. an active edge on the pai pin increments the pa. the pa edge b it, pedge, selects falli ng edges or rising edges to increment the pa. an active edge on the pai pin sets th e pa input flag, paif. the pa input interrupt enable bit, pai, enables the paif flag to generate interrupt requests.
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-19 preliminary note the pai input and gpt channel 3 use the same pin. to use the pai input, disconnect it from the output logic by clearing the channel 3 output mode and output level bits, om3 and ol3. also clear the channel 3 output compare 3 mask bit, oc3m3. the pa counter register, gptpacnt, reflects the num ber of active input edges on the pai pin since the last reset. the pa overflow flag, paovf, is set when the pa rolls over from 0xffff to 0x0000. the pa overflow interrupt enable bit, paovi, enables the paovf flag to generate interrupt requests. note the pa can operate in event counter m ode even when the gpt enable bit, gpten, is clear. 18.7.6 gated time accumulation mode setting the pamod bit configures the pa for gated time accumulation operation. an active level on the pai pin enables a divide-by-64 clock to drive the pa. the pa edge bit, pedge, selects lo w levels or high levels to enable the divide-by-64 clock. the trailing edge of the active level at the pai pin se ts the pa input flag, paif. the pa input interrupt enable bit, pai, enables the paif flag to generate interrupt requests. note the pai input and gpt channel 3 use the same pin. to use the pai input, disconnect it from the output logic by clearing the channel 3 output mode and output level bits, om3 and ol3. also clear the channel 3 output compare mask bit, oc3m3. the pa counter register, gptpacnt, reflects the number of pulses from the divide- by-64 clock since the last reset. note the gpt prescaler generates the divi de-by-64 clock. if the timer is not active, there is no divide-by-64 clock.
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-20 freescale semiconductor preliminary figure 18-22. channel 3 output compare/pulse accumulator logic 18.7.7 general-purpose i/o ports an i/o pin used by the timer defau lts to general-purpose i/o unless an internal function which uses that pin is enabled. the portt n pins can be configured for either an input capture function or an output compare function. the ios n bits in the gpt ic/oc select register configure the portt n pins as either input capture or output compare pins. the portt n data direction register controls the data di rection of an input capture pin. external pin conditions trigger input captures on input capture pins conf igured as inputs. to configure a pin for input capture: 1. clear the pin?s ios bit in gptios. 2. clear the pin?s ddr bit in portt n ddr. 3. write to gptctl2 to select the input edge to detect. portt n ddr does not affect the data direction of an output compare pin. the output compare function overrides the data direction regist er but does not affect the state of the data direction register. to configure a pin for output compare: 1. set the pin?s ios bit in gptios. 2. write the output compare value to gptc n . 3. clear the pin?s ddr bit in portt n ddr. 4. write to the om n /ol n bits in gptctl1 to select the output action. table 18-23 shows how various timer setti ngs affect pin functionality. table 18-23. gpt settings and pin functions gpten ddr 1 gptios edgx [b:a] omx/ olx 2 oc3mx 3 pin data dir. pin driven by pin function comments 00x 4 x x x in ext. digital input gpt disabled by gpten = 0 0 1 x x x x out data reg. digital output gpt disabled by gpten = 0 pa d om3 ol3 channel 3 output compare pulse accumulator oc3m3
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-21 preliminary 1 0 0 (ic) 0 (ic disabled) x 0 in ext. digital input input capture disabled by edg n setting 1 1 0 0 x 0 out data reg. digital output i nput capture disabled by edg n setting 1 0 0 <> 0 x 0 in ext. ic and digital input normal settings for input capture 1 1 0 <> 0 x 0 out data reg. digital output input capture of data driven to output pin by cpu 1 0 0 <> 0 x 1 in ext. ic and digital input oc3m setting has no effect because ios = 0 1 1 0 <> 0 x 1 out data reg. digital output oc3m setting has no effect because ios = 0; input capture of data driven to output pin by cpu 101 (oc)x (3) 0 5 0 in ext. digital input output compare takes place but does not affect the pin because of the om n /ol n setting 1 1 1 x 0 0 out data reg. digital output output compare takes place but does not affect the pin because of the om n /ol n setting 1 0 1 x <> 0 0 out oc action output compare pin readable only if ddr = 0 (5) 1 1 1 x <> 0 0 out oc action output compare pin driven by oc action (5) 1 0 1 x x 1 out oc action/ oc3d n output compare (ch 3) pin readable only if ddr = 0 6 1 1 1 x x 1 out oc action/ oc3d n output compare/ oc3d n (ch 3) pin driven by channel oc action and oc3d n via channel 3 oc (6) 1 when ddr set the pin as input (0), reading t he data register will return the state of th e pin. when ddr set the pin as output ( 1), reading the data register will return the content of the data latc h. pin conditions such as rising or falling edges can trigger an input capture on a pin configured as an input. 2 om n /ol n bit pairs select the output action to be taken as a result of a successful output compare. when either om n or ol n is set and the ios n bit is set, the pin is an output regard less of the state of the corresponding ddr bit. 3 setting an oc3m bit configures the corresponding portt n pin to be output. oc3m n makes the portt n pin an output regardless of the data direction bit when the pin is configured for output compare (ios n = 1). the oc3m n bits do not change the state of the portt n ddr bits. 4 x = don?t care 5 an output compare overrides the data direct ion bit of the output compare pin but does not change the state of the data directio n bit. enabling output compare disables data register drive of the pin. table 18-23. gpt settings and pin functions (continued) gpten ddr 1 gptios edgx [b:a] omx/ olx 2 oc3mx 3 pin data dir. pin driven by pin function comments
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-22 freescale semiconductor preliminary 18.8 reset reset initializes the gpt registers to a known startup state as described in section 18.6, ?memory map and registers .? 18.9 interrupts table 18-24 lists the interrupt reque sts generated by the timer. 18.9.1 gpt channel interrupts (c n f) a channel flag is set when an input capture or outpu t compare event occurs. clea r a channel flag by writing a 1 to it. note when the fast flag clear all bit, gp tscr1[tffca], is set, an input capture read or an output compare write cl ears the corresponding channel flag. when a channel flag is set, it does not inhibit subsequent output compares or input captures 18.9.2 pulse accumulator overflow (paovf) paovf is set when the 16-bit pulse accumulator rolls over from 0xffff to 0x0000. if the paovi bit in gptpactl is also set, paovf generates an interrupt request. clear paovf by writing a 1 to this flag. note when the fast flag clear all enable bit, gptscr1[tffca], is set, any access to the pulse accumulator counter regist ers clears all the flags in gptpaflg. 6 a successful output compare on channel 3 causes an output value determined by oc3d n value to temporarily override the output compare pin state of any other ou tput compare channel.the next oc action for the specific channel will st ill be output to the p in. a channel 3 output compare can cause bits in the output compare 3 data register to transfer to the gpt port data register, depending on the output compare 3 mask register. table 18-24. gpt interrupt requests interrupt request flag enable bit channel 3 ic/oc c3f c3i channel 2 ic/oc c2f c2i channel 1 ic/oc c1f c1i channel 0 ic/oc c0f c0i pa overflow paovf paovi pa input paif pai timer overflow tof toi
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 freescale semiconductor 18-23 preliminary 18.9.3 pulse accumulator input (paif) paif is set when the selected edge is detected at the pai pin. in event counter mode, the event edge sets paif. in gated time accumulation mode , the trailing edge of th e gate signal at the pai pin sets paif. if the pai bit in gptpactl is also set, paif generates an interrupt request. clear paif by writing a 1 to this flag. note when the fast flag clear all enable bit, gptscr1[tffca], is set, any access to the pulse accumulator counter regist ers clears all the flags in gptpaflg. 18.9.4 timer overflow (tof) tof is set when the gpt counter rolls over from 0x ffff to 0x0000. if the gptscr2[toi] bit is also set, tof generates an interrupt request. cl ear tof by writing a 1 to this flag. note when the gpt channel 3 registers co ntain 0xffff and tcre is set, tof does not get set even though the gpt c ounter registers go from 0xffff to 0x0000. when the fast flag clear all bit, gpts cr1[tffca], is set, any access to the gpt counter registers clear s gpt flag register 2. when tof is set, it does not i nhibit future overflow events.
general purpose timer module (gpt) mcf5213 reference manual, rev. 1.1 18-24 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 19-1 preliminary chapter 19 dma timers (dtim0?dtim3) 19.1 introduction this chapter describes the configuration and operati on of the four direct memory access (dma) timer modules (dtim0, dtim1, dtim2, and dtim3). these 32-bit timers provi de input capture and reference compare capabilities with optional signaling of events using interrupt s or dma triggers. additionally, programming examples are included. note the designation ? n ? is used throughout this secti on to refer to registers or signals associated with one of the four identical t imer modules?dtim0, dtim1, dtim2, or dtim3. 19.1.1 overview each dma timer module has a separate register set for configuration and control. the timers can be configured to operate from the system clock or from an exte rnal clocking source using the dt n in signal. if the system clock is sele cted, it can be divided by 16 or 1. the select ed clock source is routed to an 8-bit programmable prescaler that clocks the actual dma timer counter register (dtcn n ). using the dtmr n , dtxmr n , dtcr n , and dtrr n registers, the dma timer may be conf igured to assert an output signal, generate an interrupt, or initiate a dma transfer on a particular event. note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 13, ?general purpose i/o module? ) prior to configuring the dma timers. figure 19-1 is a block diagram of one of the four identical timer modules.
dma timers (dtim0?dtim3) mcf5213 reference manual, rev. 1.1 19-2 freescale semiconductor preliminary figure 19-1. dma timer block diagram 19.1.2 features each dma timer module has the following features: ? maximum timeout period of 266,521 seconds at 66 mhz (~74 hours) ? 15-ns resolution at 66 mhz ? programmable sources for the cloc k input, including external clock ? programmable prescaler ? input-capture capability with progr ammable trigger edge on input pin ? programmable mode for the out put pin on reference compare ? free run and restart modes ? programmable interrupt or dma request on input capture or reference-compare 19.2 memory map/register definition the following features are programmable through the timer registers, shown in table 19-1 : 19.2.1 prescaler the prescaler clock input is selected from system clock (divided by 1 or 16) or from the corresponding timer input, dt n in. dt n in is synchronized to the system cloc k. the synchronization delay is between two and three system clocks. the corresponding dtmr n [clk] selects the clock input source. a programmable prescaler divide s the clock input by values from 1 to 256. the pres caler output is an input to the 32-bit counter, dtcn n . dma timer divider dma timer mode register (dtmr n ) prescaler mode bits dma timer counter register (dtcn n ) 31 0 dma timer reference register (dtrr n ) 31 0 dma timer capture register (dtcr n ) 31 0 dma timer event register (dter n ) capture detection dt n in dt n out clock (contains incrementing value) (reference value for comparison with dtcn) (latches dtcn value when triggered by dt n in) (indicates capture or when dtcn = dtrr n ) to interrupt clock generator dma timer extended mode register (dtxmr n ) dma request 0 0 15 7 7 0 controller internal bus clock (1 or 16 )
dma timers (dtim0?dtim3) mcf5213 reference manual, rev. 1.1 freescale semiconductor 19-3 preliminary 19.2.2 capture mode each dma timer has a 32-bit ti mer capture register (dtcr n ) that latches the counter value when the corresponding input capture edge detector senses a defined dt n in transition. the cap ture edge bits (dtmr n [ce]) select the type of transition that triggers the capture and sets the timer event register capture event bit, dter n [cap]. if dter n [cap] is set and dtxmr n [dmaen] is one, a dma request is asserted. if dter n [cap] is set and dtxmr n [dmaen] is zero, an interrupt is asserted. 19.2.3 reference compare each dma timer can be configur ed to count up to a referen ce value, at which point dter n [ref] is set. if dtmr n [orri] is one and dtxmr n [dmaen] is zero, an interrupt is asserted. if dtmr n [orri] is one and dtxmr n [dmaen] is one, a dma request is assert ed. if the free r un/restart bit dtmr n [frr] is set, a new count starts. if it is clear, the timer keeps running. 19.2.4 output mode when a timer reaches the reference value select ed by dtrr, it can send an output signal on dt n out. dt n out can be an active-low pulse or a toggle of the current output, as selected by the dtmr n [om] bit. 19.2.5 memory map the timer module registers, shown in table 19-1 , can be modified at any time. table 19-1. dma timer module memory map ipsbar offset register access reset value section/page dma timer 0 dma timer 1 dma timer 2 dma timer 3 0x00_0400 0x00_0440 0x00_0480 0x00_04c0 dma timer n mode register (dtmr n ) r/w 0x0000 19.2.6/19-4 0x00_0402 0x00_0442 0x00_0482 0x00_04c2 dma timer n extended mode register (dtxmr n ) r/w 0x0000 19.2.7/19-5 0x00_0403 0x00_0443 0x00_0483 0x00_04c3 dma timer n event register (dter n ) r/w 0x0000 19.2.8/19-6 0x00_0404 0x00_0444 0x00_0484 0x00_04c4 dma timer n reference register (dtrr n ) r/w 0x1111_1111 19.2.9/19-7
dma timers (dtim0?dtim3) mcf5213 reference manual, rev. 1.1 19-4 freescale semiconductor preliminary 19.2.6 dma timer mode registers (dtmr n ) dtmrs, shown in figure 19-2 , program the prescaler and various timer modes. 0x00_0408 0x00_0448 0x00_0488 0x00_04c8 dma timer n capture register (dtcr n ) r/w 0x0000_0000 19.2.10/19-8 0x00_040c 0x00_044c 0x00_048c 0x00_04cc dma timer n counter register (dtcn n ) r 0x0000_0000 19.2.11/19-8 ipsbar offset: 0x00_0400 ( dtmr0 ) 0x00_0440 ( dtmr1 ) 0x00_0480 ( dtmr2 ) 0x00_04c0 ( dtmr3 ) access: user read/write 1514131211109876543210 r ps ce om orri frr clk rst w reset000000000 0000000 figure 19-2. dma timer mode registers (dtmr n ) table 19-2. dtmr n field descriptions field description 15?8 ps prescaler value. the prescaler is programmed to divide the clock input (system clock/(16 or 1) or clock on dt n in) by values from 1 (ps = 0x00) to 256 (ps = 0xff). 7?6 ce capture edge. 00 disable capture event output 01 capture on rising edge only 10 capture on falling edge only 11 capture on any edge 5 om output mode. 0 active-low pulse for one system clock cycle (-ns resolution at 3 mhz). 1 toggle output. 4 orri output reference request, interrupt enable. if orri is set when dter n [ref] = 1, a dma request or an interrupt occurs, depending on the value of dtxmr n [dmaen] (dma request if =1, interrupt if =0). 0 disable dma request or interrupt for reference reached (does not affect dma request or interrupt on capture function). 1 enable dma request or interrupt upon reaching the reference value. table 19-1. dma timer module memory map (continued) ipsbar offset register access reset value section/page dma timer 0 dma timer 1 dma timer 2 dma timer 3
dma timers (dtim0?dtim3) mcf5213 reference manual, rev. 1.1 freescale semiconductor 19-5 preliminary 19.2.7 dma timer extended mode registers (dtxmr n ) the dtxmr n register programs dma request a nd increment modes for the timers. 3 frr free run/restart 0 free run. timer count continues to increment after reaching the reference value. 1 restart. timer count is reset immediately after reaching the reference value. 2?1 clk input clock source for the timer 00 stop count 01 system clock divided by 1 10 system clock divided by 16. note that this clock sour ce is not synchronized with the timer; thus successive time-outs may vary slightly. 11 dt n in pin (falling edge) 0 rst reset timer. performs a software timer reset similar to an external reset, although other register values can still be written while rst = 0. a transition of rst from 1 to 0 resets register values. the timer counter is not clocked unless the timer is enabled. 0 reset timer (software reset) 1 enable timer ipsbar offset: 0x 00_04 02 ( dtxmr0 ) 0x 00_044 2 ( dtxmr1 ) 0x 00_048 2 ( dtxmr2 ) 0x 00_04c 2 ( dtxmr3 ) access: user read/write 7 6543210 r dmaen 000 0 00 mode16 w reset: 0 0 0 0 0 0 0 0 figure 19-3. dma timer extended mode registers (dtxmr n ) table 19-3. dtxmr n field descriptions field description 7 dmaen dma request. enables dma request output on coun ter reference match or capture edge event. 0 dma request disabled 1 dma request enabled 6?1 reserved, should be cleared. 0 mode16 selects the increment mode for the timer. mode16 = 1 is intended to exercise the upper bits of the 32-bit timer in diagnostic software without requiring the timer to count th rough its entire dynamic range. when set, the counter?s upper 16 bits mirror its lower 16 bits. all 32 bits of the counter are still compared to the reference value. 0 increment timer by 1 1 increment timer by 65,537 table 19-2. dtmr n field descriptions (continued) field description
dma timers (dtim0?dtim3) mcf5213 reference manual, rev. 1.1 19-6 freescale semiconductor preliminary 19.2.8 dma timer event registers (dter n ) dter n , shown in figure 19-4 , reports capture or refere nce events by setting dter n [cap] or dter n [ref]. this reporting is done regardless of th e corresponding dma request or interrupt enable values, dtxmr n [dmaen] and dtmr n [orri,ce]. writing a 1 to either dter n [ref] or dter n [cap] clears it (writing a 0 doe s not affect bit value); both bits can be cleared at the same time. if configured to generate an interrupt re quest, the ref and cap bits should be cleared early in the interr upt service routine so th e timer module can negate the interrupt request signal to the interrupt controller. if configured to generate a dma request, the processing of the dma data transfer automatically clears both the ref an d cap flags via the internal dma ack signal. ipsbar offset: 0x00_0403 (dter0) 0x00_0443 (dter1) 0x00_0483 (dter2) 0x00_04c3 (dter3) access: user read/write 7 6543210 r0 0 0 0 0 0 ref cap w w1c w1c reset: 0 0 0 0 0 0 0 0 figure 19-4. dma timer event registers (dter n ) table 19-4. dter n field descriptions field description 7?2 reserved, should be cleared.
dma timers (dtim0?dtim3) mcf5213 reference manual, rev. 1.1 freescale semiconductor 19-7 preliminary 19.2.9 dma timer reference registers (dtrr n ) each dtrr n , shown in figure 19-5 , contains the reference value compared with the respective free-running timer counter (dtcn n ) as part of the output-compare f unction. the reference value is not matched until dtcn n equals dtrr n , and the prescaler indicates that dtcn n should be incremented again. thus, the reference regi ster is matched after dtrr n +1 time intervals. 1 ref output reference event. the counter value, dtcn n, equals the reference value, dtrr n . writing a one to ref clears the event condition. writing a zero has no effect. 0 cap capture event. the counter value has been latched into dtcr n . writing a one to cap clears the event condition. writing a zero has no effect. table 19-4. dter n field descriptions (continued) field description ref dtmr n [orri] dtxmr n [dmaen] 0x x no event 1 0 0 no request asserted 1 0 1 no request asserted 1 1 0 interrupt request asserted 1 1 1 dma request asserted cap dtmr n [ce] dtxmr n [dmaen] 0xx x no event 1 00 0 disable capture event output 1 00 1 disable capture event output 1 01 0 capture on rising edge & trigger interrupt 1 01 1 capture on rising edge & trigger dma 1 10 0 capture on falling edge & trigger interrupt 1 10 1 capture on falling edge & trigger dma 1 11 0 capture on any edge & trigger interrupt 1 11 1 capture on any edge & trigger dma
dma timers (dtim0?dtim3) mcf5213 reference manual, rev. 1.1 19-8 freescale semiconductor preliminary 19.2.10 dma timer capture registers (dtcr n ) each dtcr n latches the corresponding dtcn n value during a capture operation when an edge occurs on dt n in, as programmed in dtmr n . the system clock is assumed to be the clock source. dt n in cannot simultaneously function as a clocking source and as an input capture pin. inde terminate operation will result if dt n in is set as the clock source when the input capture mode is used. 19.2.11 dma timer counters (dtcn n ) the current value of the 32-bit dt cns can be read at a nytime without affecti ng counting. writing to dtcn n clears it. the timer counter in crements on the clock source rising edge (system cl ock 1, system clock 16, or dt n in). ipsbar offset: 0x 00_04 04 ( dtrr0 ) 0x 00_044 4 ( dtrr1 ) 0x 00_048 4 ( dtrr2 ) 0x 00_04c 4 ( dtrr3 ) access: user read/write 313029282726252423222120191817161514131211109876543210 r ref w reset11111111111111111111111111111111 figure 19-5. dma timer re ference registers (dtrr n ) ipsbar offset: 0x 00_04 08 ( dtcr0 ) 0x 00_044 8 ( dtcr1 ) 0x 00_048 8 ( dtcr2 ) 0x 00_04c 8 ( dtcr3 ) access: user read-only 313029282726252423222120191817161514131211109876543210 r cap (32-bit capture counter value) w reset00000000000000000000000000000000 figure 19-6. dma timer capture registers (dtcr n ) ipsbar offset: 0x 00_04 0c ( dtcn0 ) 0x 00_044 c ( dtcn1 ) 0x 00_048 c ( dtcn2 ) 0x 00_04c c ( dtcn3 ) access: user read/write 313029282726252423222120191817161514131211109876543210 r cnt (32-bit timer counter value count) w reset00000000000000000000000000000000 figure 19-7. dma timer counters (dtcn n )
dma timers (dtim0?dtim3) mcf5213 reference manual, rev. 1.1 freescale semiconductor 19-9 preliminary 19.3 initialization/application information the general-purpose timer modules are typically used in the foll owing manner, though this is not necessarily the program order in which these actions must occur: ? the dtmr n and dtxmr n registers are configured for th e desired function and behavior. ? count and compare to a reference value stored in the dtrr n register ? capture the timer value on an edge detected on dt n in ? configure dt n out output mode ? increment counter by 1 or by 65,537 (16-bit mode) ? enable/disable interrupt or dma request on counter reference ma tch or capture edge ? the dtmr n [clk] register is configured to select the clock source to be routed to the prescaler. ? system clock (can be divided by 1 or 16) ?dt n in, the maximum value of dt n in is 1/5 of the internal bus clock, as described in the device?s electrical characteristics note dt n in may not be configured as a cl ock source when the timer capture mode is selected or indete rminate operation will result. ? the 8-bit dtmr n [ps] prescaler value is set. ? using dtmr n [rst] the counter is cleared and started. ? timer events are either handled with an interrupt service routine, a dma request, or by a software polling mechanism. 19.3.1 code example the following code provides an exam ple of how to initialize dma timer0 and how to use the timer for counting time-out periods. dtmr0 equ ipsbarx+0x400 ;timer0 mode register dtmr1 equ ipsbarx+0x440 ;timer1 mode register dtrr0 equ ipsbarx+0x404 ;timer0 reference register dtrr1 equ ipsbarx+0x444 ;timer1 reference register dtcr0 equ ipsbarx+0x408 ;timer0 capture register dtcr1 equ ipsbarx+0x448 ;timer1 capture register dtcn0 equ ipsbarx+0x40c ;timer0 counter register dtcn1 equ ipsbarx+0x44c ;timer1 counter register dter0 equ ipsbarx+0x403 ;timer0 event register dter1 equ ipsbarx+0x443 ;timer1 event register * tmr0 is defined as: * *[ps] = 0xff, divide clock by 256 *[ce] = 00 disable capture event output *[om] = 0 output=active-low pulse *[orri] = 0, disable ref. match output *[frr] = 1, restart mode enabled *[clk] = 10, system clock/16 *[rst] = 0, timer0 disabled
dma timers (dtim0?dtim3) mcf5213 reference manual, rev. 1.1 19-10 freescale semiconductor preliminary move.w #0xff0c,d0 move.w d0,tmr0 move.l #0x0000,d0;writing to the timer counter with any move.l do,tcn0 ;value resets it to zero move.l #0xafaf,do ;set the timer0 reference to be move.l #d0,trr0 ;defined as 0xafaf the simple example below uses timer0 to count time -out loops. a time-out occurs when the reference value, 0xafaf, is reached. timer0_ex clr.l do clr.l d1 clr.l d2 move.l #0x0000,d0 move.l d0,tcn0 ;reset the counter to 0x0000 move.b #0x03,d0 ;writing ones to ter0[ref,cap] move.b d0,ter0 ;clears the event flags move.w tmr0,d0 ;save the contents of tmr0 while setting bset #0,d0 ;the 0 bit. this enables timer 0 and starts counting move.w d0,tmr0 ;load the value back into the register, setting tmr0[rst] t0_loop move.b ter0,d1 ;load ter0 and see if btst #1,d1 ;ter0[ref] has been set beq t0_loop addi.l #1,d2 ;increment d2 cmp.l #5,d2 ;did d2 reach 5? (i.e. timer ref has timed) beq t0_finish ;if so, end timer0 example. otherwise jump back. move.b #0x02,d0 ;writing one to ter0[ref] clears the event flag move.b d0,ter0 jmp t0_loop t0_finish halt ;end processing. example is finished 19.3.2 calculating time-out values the formula below determines time-out periods for various reference values: eqn. 19-1 when calculating time-out periods, add 1 to th e prescaler to simplify calculating, because dtmr n [ps] = 0x00 yields a prescaler of 1 and dtmr n [ps] = 0xff yields a prescaler of 256. for example, if a 66-mhz time r clock is divided by 16, dtmr n [ps] = 0x7f, and the timer is referenced at 0xfbc5 (64453 decimal), the ti me-out period is as follows: eqn. 19-2 timeout period 1 clock frequency ? () 1 or 16 () dtmr n [ps] 1 + () dtrr n [ref] 1 + () = timeout period 1 66 10 6 -------------------- 16 127 1 + () 64453 1 + () 2.00s ==
mcf5213 reference manual, rev. 1.1 freescale semiconductor 20-1 preliminary chapter 20 queued serial peripheral interface (qspi) 20.1 introduction this chapter describes the queued serial peripher al interface (qspi) module. following a feature set overview is a description of opera tion including details of the qspi?s internal ram organization. the chapter concludes with the progra mming model and a timing diagram. 20.1.1 block diagram figure 20-1 illustrates the qspi module. figure 20-1. qspi block diagram queue control block queue pointer 4 done comparator end queue pointer status regs delay counter control logic control regs 80-byte qspi ram chip selects command divide by 2 baud rate generator msb lsb logic array qspi_clk qspi_din 8 /16 bit shift reg . rx/tx data reg. qspi_dout 4 4 internal bus qspi address register qspi data register internal bus clock (f sys/ ) qspi_cs[:0]
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 20-2 freescale semiconductor preliminary 20.1.2 overview the queued serial peripheral interf ace module provides a serial periphe ral interface with queued transfer capability. it allows users to queue up to 16 tran sfers at once, eliminating cpu intervention between transfers. transfer ram in the qspi is indirectly accessible us ing address and data registers. note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 13, ?general purpose i/o module? ) prior to configuring the qspi module. 20.1.3 features features include the following: ? programmable queue to support up to 16 transfers without user intervention ? supports transfer sizes of 8 to 16 bits in 1-bit increments ? four peripheral chip-select lines for control of up to 15 devices ? baud rates from 129.4 kbps to 16.6 mbps at 66 mhz internal bus frequency ? programmable delays before and after transfers ? programmable qspi clock phase and polarity ? supports wraparound mode for continuous transfers 20.1.4 external signals description the module provides access to as many as 15 devi ces with a total of seven signals: qspi_dout, qspi_din, qspi_clk, qspi_cs0, q spi_cs1, qspi_cs2, and qspi_cs3. peripheral chip-selec t signals, qspi_cs n , are used to select an external device as th e source or destination for serial data transfer. signals are asserted whenev er a command in the queue is executed. more than one chip-select signal can be asserted simultaneously. although qspi_cs n will function as simple chip selects in most applications, up to 15 devices can be selected by decoding th em with an external 4-to-16 decoder. table 20-1. qspi input and output signals and functions signal name hi-z or actively driven function qspi data output (qspi_dout) configurable serial data output from qspi qspi data input (qspi_din) n/a serial data input to qspi serial clock (qspi_clk) actively driven clock output from qspi peripheral chip selects (qspi_cs n ) actively driven peripheral selects
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 freescale semiconductor 20-3 preliminary 20.1.5 modes of operation because the qspi module only operates in master m ode, the master bit in the qspi mode register, qmr[mstr], must be set for the q spi to function properly. the qspi can initiate serial transfers but cannot respond to transfers init iated by other qspi masters. 20.2 memory map/register definition table 20-2 is the qspi register memory map. r eading reserved locations returns zeros. 20.2.1 qspi mode register (qmr) the qmr, shown in figure 20-2 , determines the basic operating modes of the q spi module. parameters such as qspi_clk polarity and phase, baud rate , master mode operation, and tr ansfer size are determined by this register. the data output high impedance enable, dohie, cont rols the operation of qspi_dout between data transfers. when dohie is cleared, qspi_dout is actively driven between transfers. when dohie is set, qspi_dout assumes a high impedance state. note because the qspi doe s not operate in slave mode , the master mode enable bit, qmr[mstr], must be set for th e qspi module to operate correctly. table 20-2. qspi memory map ipsbar offset 1 1 addresses not assigned to a register and undef ined register bits are reserved for expansion. register access reset value section/page 0x00_0340 qspi mode register (qmr) r/w 0x0104 20.2.1/20-3 0x00_0344 qspi delay register (qdlyr) r/w 0x0404 20.2.2/20-5 0x00_0348 qspi wrap register (qwr) r/w 2 2 see the register description for special cases. some bits may be read- or write-only. 0x0000 20.2.3/20-6 0x00_034c qspi interrupt register (qir) r/w 2 0x0000 20.2.4/20-6 0x00_0350 qspi address register (qar) r/w 2 0x0000 20.2.5/20-8 0x00_0354 qspi data register (qdr) r/w 0x0000 20.2.6/20-8 ipsbar offset: 0x00_0340 access: user read/write 1514131211109 876543210 r mstr dohie bits cpol cpha baud w reset0 0 0000010 0000100 figure 20-2. qspi mode register (qmr)
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 20-4 freescale semiconductor preliminary table 20-3. qmr field descriptions field description 15 mstr master mode enable. 0 reserved, do not use. 1 the qspi is in master mode. must be se t for the qspi module to operate correctly. 14 dohie data output high impedance enable. selects qspi_dout mode of operation. 0 default value after reset. qspi_dout is actively driven between transfers. 1 qspi_dout is high impedance between transfers. 13?10 bits transfer size. determines the number of bits to be transferred for each entry in the queue. 9 cpol clock polarity. defines the clock polarity of qspi_clk. 0 the inactive state value of qspi_clk is logic level 0. 1 the inactive state value of qspi_clk is logic level 1. 8 cpha clock phase. defines the qspi_clk clock-phase. 0 data captured on the leading edge of qspi_clk and changed on the following edge of qspi_clk. 1 data changed on the leading edge of qspi_clk a nd captured on the follo wing edge of qspi_clk. 7?0 baud baud rate divider. the baud rate is selected by writing a va lue in the range 2?255. a value of zero disables the qspi. a value of 1 is an invalid setting. the desired qspi_clk baud rate is related to the internal bus clock and qmr[baud] by the following expression: qmr[baud] = f sys/ /(2 [desired qspi_clk baud rate]) bits bits per transfer 0000 16 0001?0111 reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 freescale semiconductor 20-5 preliminary figure 20-3 shows an example of a qspi clocking and data transfer. figure 20-3. qspi clocking and data transfer example 20.2.2 qspi delay register (qdlyr) ipsbar offset: 0x00_0344 access: user read/write 1514131211109 876543210 r spe qcd dtl w reset0 0 0001000 0000100 figure 20-4. qspi delay register (qdlyr) table 20-4. qdlyr field descriptions field description 15 spe qspi enable. when set, the qspi initiates transfers in master mode by executing co mmands in the command ram. automatically cleared by the qspi when a transfer completes. the user can also clear this bit to abort transfer unless qir[abrtl] is set. the recommended method for aborting transfers is to set qwr[halt]. 14?8 qcd qspi_clk delay. when the dsck bit in the command ram is set this field determines the length of the delay from assertion of the chip selects to valid qspi_clk transition. see section 20.3.3, ?transfer delays? for information on setting this bit field. 7?0 dtl delay after transfer. when the dt bit in the command ram is set this field determines t he length of delay after the serial transfer. qspi_clk qspi_dout qspi_din qspi_cs a b qmr[cpol] = 0 qmr[cpha] = 1 qcr[cont] = 0 chip selects are active low a = qdlyr[qcd] b = qdlyr[dtl] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 20-6 freescale semiconductor preliminary 20.2.3 qspi wrap register (qwr) 20.2.4 qspi interrupt register (qir) ipsbar offset: 0x00_0348 access: user read/write 1514131211109 876543210 r halt wren wrto csiv endqp cptqp newqp w reset0 0 0 00000 00000000 figure 20-5. qspi wrap register (qwr) table 20-5. qwr field descriptions field description 15 halt halt transfers. assertion of this bit causes the qspi to stop execution of commands once it has completed execution of the current command. 14 wren wraparound enable. enables wraparound mode. 0 execution stops after executing the command pointed to by qwr[endqp]. 1 after executing command pointed to by qwr[endqp], wrap back to entry zero, or the entry pointed to by qwr[newqp] and continue execution. 13 wrto wraparound location. determines where the qspi wraps to in wraparound mode. 0 wrap to ram entry zero. 1 wrap to ram entry pointed to by qwr[newqp]. 12 csiv qspi_cs inactive level. 0 qspi chip select outputs return to zero when not driv en from the value in the current command ram entry during a transfer (that is, inactive state is 0, chip selects are active high). 1 qspi chip select outputs return to one when not driven from the value in the current command ram entry during a transfer (that is, inactive state is 1, chip selects are active low). 11?8 endqp end of queue pointer. points to the ram entry that co ntains the last transfer description in the queue. 7?4 cptqp completed queue entry pointer. points to the ram entry t hat contains the last comma nd to have been completed. this field is read only. 3?0 newqp start of queue pointer. this 4-bit field points to the firs t entry in the ram to be executed on initiating a transfer. ipsbar offset: 0x00_034c access: user read/write 15 141312 11 109876543 210 r wcefb abrtb 0 abrtl wcefe abrte 0 spife 0 0 0 0 wcef abrt 0 spif w w1c w1c w1c reset0 000 0 00000000000 figure 20-6. qspi interrupt register (qir)
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 freescale semiconductor 20-7 preliminary the command and data ram in the qspi are indirectly accessible wi th qdr and qar as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands. a write to qdr causes data to be written to the ram entry specified by qar[addr]. this also causes the value in qar to increment. correspondingly, a read at qdr returns the data in the ram at the address specified by qar[addr]. this also causes qar to increment. a read access requires a single wait state. note the qar does not wrap after the last que ue entry within each section of the ram. the application software mu st handle address range errors. table 20-6. qir field descriptions field description 15 wcefb write collision access error enable. a write collision occu rs during a data transfer when the ram entry containing the current command is written to by the cpu with the qdr. when this bit is asserted, the write access to qdr results in an access error. 14 abrtb abort access error enable. an abort occurs when qdlyr[spe] is cleared during a transfer. when set, an attempt to clear qdlyr[spe] during a transfer results in an access error. 13 reserved, should be cleared. 12 abrtl abort lock-out. when set, qdlyr[spe] ca nnot be cleared by writ ing to the qdlyr. qdlyr[ spe] is only cleared by the qspi when a transfer completes. 11 wcefe write collision (wcef) interrupt enable. 0 write collision interrupt disabled 1 write collision interrupt enabled 10 abrte abort (abrt) interrupt enable. 0 abort interrupt disabled 1 abort interrupt enabled 9 reserved, should be cleared. 8 spife qspi finished (spif) interrupt enable. 0 spif interrupt disabled 1 spif interrupt enabled 7?4 reserved, should be cleared. 3 wcef write collision error flag. indicates that an attempt has been made to write to the ram entry that is currently being executed. writing a 1 to this bit cl ears it and writing 0 has no effect. 2 abrt abort flag. indicates that qdlyr[spe] has been cleared by t he user writing to the qdlyr rather than by the qspi completing the command queue. writing a 1 to this bit clears it and writing 0 has no effect. 1 reserved, should be cleared. 0 spif qspi finished flag. asserted when the qspi has complet ed all the commands in the queue. set on completion of the command pointed to by qwr[endqp], and on comp letion of the current command after assertion of qwr[halt]. in wraparound mode, this bit is set every time the command pointed to by qwr[endqp] is completed. writing a 1 to this bit clears it and writing 0 has no effect.
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 20-8 freescale semiconductor preliminary 20.2.5 qspi address register (qar) the qar is used to specify the location in the qspi ram that read and write ope rations affect. as shown in section 20.3.1, ?qspi ram? , the transmit ram is located at addresses 0x0 to 0xf, the receive ram is located at 0x10 to 0x1f, and the command ram is locat ed at 0x20 to 0x2f. 20.2.6 qspi data register (qdr) the qdr, shown in figure 20-8 , is used to access qspi ram indir ectly. the cpu reads and writes all data from and to the qspi ram through this register. 20.2.7 command ram re gisters (qcr0?qcr15) the qspi cannot modify information in command ram. however, it can access the command ram by using the upper byte of the qdr. there are 16 bytes in the command ram. each byte is di vided into two fields. the chip select field enables external peripherals for transfer. the co mmand field provides transfer operations. note the command ram is accessed only us ing the most significant byte of qdr and indirect addre ssing based on qar[addr]. figure 20-9 shows the command ram register. ipsbar offset: 0x0x00_0350 access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000 addr w reset0000000000000000 figure 20-7. qspi address register (qar) ipsbar offset: 0x0x00_0354 access: user read/write 1514131211109876543210 r data w reset0000000000000000 figure 20-8. qspi data register (qdr) address: qar[addr] access: cpu write-only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r wcontbitsedtdsck qspi_cs 00000000 reset???????????????? figure 20-9. command ram registers (qcr0?qcr15)
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 freescale semiconductor 20-9 preliminary table 20-7. qcr0?qcr15 field descriptions field description 15 cont continuous. 0 chip selects return to inactive level defined by qwr[csiv] when a single word transfer is complete. 1 chip selects return to inactive level defined by qwr[csiv] only after the transfer of the queue entries (max of 16 words). note: in order to keep the chip selects asserted beyond 16 words, the qwr[cs iv] bit must be set to control the level that the chip selects retu rn to after the first transfer. 14 bitse bits per transfer enable. 0 eight bits 1 number of bits set in qmr[bits] 13 dt delay after transfer enable. 0 default reset value. 1 the qspi provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have a latency requirement. the delay between transfers is determined by qdlyr[dtl]. 12 dsck chip select to qspi_clk delay enable. 0 chip select valid to qspi_clk transition is one-half qspi_clk period. 1 qdlyr[qcd] specifies the delay fr om qspi_cs valid to qspi_clk. ?8 qspi_cs peripheral chip selects. used to select an external device for serial data transfer. more than one chip select may be active at once, and more than one device can be connected to each chip select. each bit maps directly to the corresponding qspi_cs n pin. if more than four chip selects are needed, then an external demultiplexor can be used with the qspi_cs n pins. 7?0 reserved, should be cleared.
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 20-10 freescale semiconductor preliminary figure 20-10. qspi timing 20.3 functional description the qspi uses a dedicated 80-byte block of static ram accessible both to the module and the cpu to perform queued operations. the ram is divi ded into three segments as follows: ? 16 command control bytes (command ram) ? 32 transmit data bytes (transfer ram) ? 32 receive data bytes (transfer ram) the ram is organized so that 1 byte of command cont rol data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0?0xf). note throughout coldfire documentation, ?wor d? is used to designate a 16-bit data unit. the only exceptions to this appear in discussions of serial communication modules such as qspi that support variable-length data units. to simplify these discussions, the functional unit is referred to as a ?word? regardless of length. qspi_cs n qspi_clk qspi_dout qspi_din qs1 qs1: qspi_cs to qspi_clk qs2: qspi_clk to qspi_dout valid qs3: qspi_clk to qspi_dout hold qs4: qspi_din to qspi_clk setup qs2 qs3 qs4 qs5 qs5: qspi_din to qspi_clk hold 1t1 0 ns 10 ns 10 ns min max 20 ns 1t1 is defined as the clock period in ns.
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 freescale semiconductor 20-11 preliminary the user initiates qspi operation by loading a queue of commands in command ram, writing transmit data into transmit ram, and then enabling the q spi data transfer. the qspi executes the queued commands and sets the completion flag in the qspi interrupt register (qir [spif]) to signal their completion. as another option, qir[spife] can be enable d to generate an interrupt. the qspi uses four queue pointers. th e user can access three of them thr ough fields in qspi wrap register (qwr): ? the new queue pointer, qwr[newqp], poi nts to the first command in the queue. ? an internal queue pointer points to the command currently being executed. ? the completed queue pointer, qwr[cptqp], points to the last command executed. ? the end queue pointer, qw r[endqp], points to the final command in the queue. the internal pointer is initialized to the same value as qwr[newqp]. during normal operation, the following sequence repeats: 1. the command pointed to by the internal pointer is executed. 2. the value in the internal point er is copied into qwr[cptqp]. 3. the internal pointer is incremented. execution continues at the internal pointer address unless the qwr[newqp] value is changed. after each command is executed, qwr[endqp] and qwr[cptqp] are compar ed. when a match occurs, qir[spif] is set and the qspi stops unless wrap around mode is enabled. setting qwr[wren] enables wraparound mode. qwr[newqp] is cleared at reset. when the qspi is enabled, execution begins at address 0x0 unless another value has been written into qwr[newqp]. qwr[endqp] is clea red at reset but is changed to show the last queue entry before the qspi is enabled. qwr[newqp] and qwr[endqp] can be written at any time. when the qwr[newqp] value changes, the internal pointer value also changes unless a transfer is in progress, in which case the tran sfer completes normally. leaving qwr[newqp] and qwr[endqp] set to 0x0 causes a single transf er to occur when the qspi is enabled. data is transferred relative to qspi _clk which can be generated in any one of four combin ations of phase and polarity using qmr[cpha,cpol]. da ta is transferred with the most significant bit (msb) first. the number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a value into the bitse field of th e command ram (qcr[bitse]). 20.3.1 qspi ram the qspi contains an 80-byte bloc k of static ram that can be accessed by both the user and the qspi. this ram does not appear in the device memory map because it can only be accessed by the user indirectly through the qspi addre ss register (qar) and the qspi da ta register (qdr). the ram is divided into three segments with 16 addresses each: ? receive data ram, the initial destination for all incoming data ? transmit data ram, a buffer for all out-bound data ? command ram, where commands are loaded
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 20-12 freescale semiconductor preliminary the transmit and command ram are user write- only. the receive ram is user read-only. figure 20-11 shows the ram configuration. the ram contents are undefined immedi ately after a reset. the command and data ram in the qspi is indire ctly accessible with qdr and qar as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data and 16 bytes of commands. a write to qdr causes data to be written to th e ram entry specified by qar[addr] and causes the value in qar to increment. correspondingly, a read at qdr returns the data in the ram at the address specified by qar[addr]. this also causes qar to increment. a read access requires a si ngle wait state. 20.3.1.1 receive ram data received by the qspi is stored in the receive ram segment locate d at 0x10 to 0x1f in the qspi ram space. the user reads this segment to retrieve data fr om the qspi. data words with less than 16 bits are stored in the least significant bits of the ram. unus ed bits in a receive queue entry are set to zero upon completion of the indi vidual queue entry. qwr[cptqp] shows which queue entrie s have been executed. the user can query this field to determine which locations in receiv e ram contain valid data. 20.3.1.2 transmit ram data to be transmitted by the qspi is stored in the transmit ram segm ent located at addresses 0x0 to 0xf. the user normally writes 1 word in to this segment for each queue co mmand to be executed. the user cannot read data in the transmit ram. relative address register function 0x00 qtr0 transmit ram 0x01 qtr1 ... ... 16 bits wide 0x0f qtr15 0x10 qrr0 receive ram 0x11 qrr1 ... ... 16 bits wide 0x1f qrr15 0x20 qcr0 command ram 0x21 qcr1 ... ... 8 bits wide 0x2f qcr15 figure 20-11. qspi ram model
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 freescale semiconductor 20-13 preliminary outbound data must be written to tr ansmit ram in a right-justified fo rmat. the unused bits are ignored. the qspi copies the data to its data serializer (shift register) for transmission. th e data is transmitted most significant bit first and remains in tran smit ram until overw ritten by the user. 20.3.1.3 command ram the cpu writes one byte of control information to this segment for ea ch qspi command to be executed. command ram, referred to as qcr0?15, is wr ite-only memory from a user?s perspective. command ram consists of 16 bytes wi th each byte divided into two fiel ds. the peripheral chip select field controls the qspi_cs signal levels for the tr ansfer. the command contro l field provides transfer options. a maximum of 16 commands can be in the queue. queue execution proceeds from the address in qwr[newqp] through the address in qwr[endqp]. the qspi executes a queue of comm ands defined by the control bits in each command ram entry which sequence the following actions: ? chip-select pins are activated. ? data is transmitted from transmit ra m and received into the receive ram. ? the synchronous transfer cl ock qspi_clk is generated. before any data transfers begin, control data must be written to the comm and ram, and any out-bound data must be written to tr ansmit ram. also, the queue pointers must be initialized to the first and last entries in the command queue. data transfer is synchronized with the internally generated qspi_clk, whos e phase and polarity are controlled by qmr[cpha] and qmr[cpol]. these c ontrol bits determine wh ich qspi_clk edge is used to drive outgoing data and to latch incoming data. 20.3.2 baud rate selection the maximum qspi clock frequency is one-fourth the clock frequency of the internal bus clock (f sys/2 ). baud rate is selected by writing a value from 2?255 into qmr[baud]. the qspi uses a prescaler to derive the qspi_clk rate from th e internal bus clock divided by two. a baud rate value of zero turns off the qspi_clk. the desired qspi_clk baud rate is related to the internal bus clock and qmr[baud] by the following expression:
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 20-14 freescale semiconductor preliminary 20.3.3 transfer delays the qspi supports programmable delays for the qspi_c s signals before and after a transfer. the time between qspi_cs assertion and the l eading qspi_clk edge, and the time between the end of one transfer and the beginning of the next, ar e both independently programmable. the chip select to clock delay enable bit in command ram, qcr[dsck], enables the programmable delay period from qspi_cs asserti on until the leading edge of qspi_c lk. qdlyr[qcd] determines the period of delay before the leading edge of qspi_c lk. the following expression determines the actual delay before the qspi _clk leading edge: qdlyr[qcd] has a range of 1?127. when qdlyr[qcd] or qcr[dsck] e quals zero, the standard delay of one-half the qspi_clk period is used. the command ram delay after transmit enable bit, qcr[dt], enables the programmable delay period from the negation of the qspi_cs signa ls until the start of the next tran sfer. the delay after transfer can be used to provide a peripheral deselect interval. a delay can also be inserted between consecutive transfers to allow serial a/d conve rters to complete conversion. there are two transfer delay options: the user can choose to delay a standard period after serial transfer is co mplete or can specify a delay period. writing a value to qdlyr[dtl] specifies a delay period. qcr[dt] determines whether the standard delay period (dt = 0) or the specified delay period (dt = 1) is used. the following expression is used to calculate the delay when dt = 1: where qdlyr[dtl] has a ra nge of 1?255. a zero value for dtl causes a delay-after-transfer value of 8192/f sys/ . standard delay period (dt = 0) is calculated by the following: adequate delay between transfer s must be specified for long data streams because the qspi modul e requires time to load a transmit ram entry for transfer. receiving devices need at least the st andard delay between successi ve transfers. if the intern al bus clock is operating at a slower rate, the delay between tran sfers must be increased proportionately. table 20-8. qspi_clk frequency as function of internal bus clock and baud rate internal bus clock = 66 mhz qmr [baud] qspi_clk 216.5mhz 48.25mhz 84.1mhz 16 2.06 mhz 32 1.0 mhz 255 12.9 khz qmr[baud] f sys 2 ? 2 [desired qspi_clk baud rate] ----------------------------------------------------------------------------------- = qspi_cs-to-qspi_clk delay qdlyr[qcd] f sys/2 ------------------------------------ - = delay after transfer 32 qdlyr[dtl] f sys/2 ------------------------------------------------ (dt = 1) = standard delay after transfer 17 f sys/2 ---------- (dt = 0) =
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 freescale semiconductor 20-15 preliminary 20.3.4 transfer length there are two transfer lengt h options. the user can choos e a default value of 8 bits or a programmed value of 8 to 16 bits. the progr ammed value must be written into qm r[bits]. the comm and ram bits per transfer enable field, qcr[bitse], determines whethe r the default value (bitse = 0) or the bits[3?0] value (bitse = 1) is used. qmr[bi ts] gives the required number of bits to be transferred, with 0b0000 representing 16. 20.3.5 data transfer the transfer operation is initiated by setting qdlyr[spe]. shortly afte r qdlyr[spe] is set, the qspi executes the command at the command ram address poi nted to by qwr[newqp] . data at the pointer address in transmit ram is loaded into the data seri alizer and transmitted. data that is simultaneously received is stored at the poi nter address in receive ram. when the proper number of bits has been transferred, the qspi stores the working queue pointer value in qwr[cptqp], increments the worki ng queue pointer, and loads the next data for transfer from the transmit ram. the command pointed to by the incr emented working queue pointer is executed next unless a new value has been written to qwr[newqp]. if a new queue pointer value is written while a transfer is in progress, the curr ent transfer is completed normally. when the cont bit in the command ram is set, th e qspi_cs signals are asse rted between transfers. when cont is cleared, qspi_cs n are negated between transfers. no te, the qspi_cs signals are not high impedance. when the qspi reaches the end of th e queue, it asserts the sp if flag, qir[spif]. if qi r[spife] is set, an interrupt request is generated when qir[spif] is asserte d. then the qspi clears qdlyr[spe] and stops, unless wraparound mode is enabled. wraparound mode is enabled by setting qwr[wren]. th e queue can wrap to pointer address 0x0, or to the address specified by qwr[newqp], depending on the state of qwr[wrto]. in wraparound mode, the qspi cycles through the que ue continuously, even while requesting interrupt service. qdlyr[spe] is not cleared when the last co mmand in the queue is executed. new receive data overwrites previously received data in the receive ram. each time the end of the queue is reached, qir[spife] is set. qir[spif] is not automatically rese t. if interrupt driven qspi service is used, the service routine must clear qir[spif] to abort the current reques t. additional interr upt requests during servicing can be prevente d by clearing qir[spife]. there are two recommended met hods of exiting wraparound mode: clearing qwr[wren] or setting qwr[halt]. exiting wraparound mode by clearing qdlyr[spe] is not recommended because this may abort a serial transfer in progress. the qspi sets spif, clears qdlyr[spe], a nd stops the first time it reaches the end of the queue after qwr[wren] is cleared. after qwr[ha lt] is set, the qspi finishes the current transfer, then stops executing commands. after the qspi stops, qdlyr[spe] can be cleared.
queued serial peripheral interface (qspi) mcf5213 reference manual, rev. 1.1 20-16 freescale semiconductor preliminary 20.3.6 initialization/ap plication information the following steps are necessary to set up the qspi 12-bit data tran sfers and a qspi_clk of 4.125 mhz. the qspi ram is set up for a queue of 16 transfers. all qspi_cs signals are used in this example. 1. write the qmr with 0xb308 to set up 12-bit data words with the data shifted on the falling clock edge, and a qspi_clk frequency of 4.125 mhz (assuming a 66-mhz internal bus clock). 2. write qdlyr with the desired delays. 3. write qir with 0xd00f to enable write collisi on, abort bus errors, a nd clear any interrupts. 4. write qar with 0x0020 to select the first command ram entry. 5. write qdr with 0x7e00, 0x7e00, 0x7e 00, 0x7e00, 0x7d00, 0x7d00, 0x7d00, 0x7d00, 0x7b00, 0x7b00, 0x7b00, 0x7b00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for each chip select. the chip selects are active low in this example. 6. write qar with 0x0000 to select the first transmit ram entry. 7. write qdr with sixteen 12-bit words of data. 8. write qwr with 0x0f00 to set up a queue be ginning at entry 0 and ending at entry 15. 9. set qdlyr[spe] to enable the transfers. 10. wait until the transfers are complete. qir[spif] is set when the transfers are complete. 11. write qar with 0x0010 to select the first receive ram entry. 12. read qdr to get the received data for each transfer. 13. repeat steps 5 through 13 to do another transfer.
mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-1 preliminary chapter 21 uart modules 21.1 introduction this chapter describes the use of the three univers al asynchronous receiver/t ransmitters (uarts) and includes programming examples. note the designation ? n ? is used throughout this secti on to refer to registers or signals associated with one of the three identical uart modules: uart0, uart1, or uart2. 21.1.1 overview each uart can be clocked by the internal bus cloc k, eliminating the need for an external uart clock. as figure 21-1 shows, each uart module inte rfaces directly to the cpu and consists of the following: ? serial communication channel ? programmable clock generation ? interrupt control logic and dma request logic ? internal channel control logic figure 21-1. uart block diagram serial interrupt control logic u n cts u n rts u n rxd u n txd or external clock (dt n in) internal channel control logic programmable clock communications channel generation uart internal bus clock (f sys/2 ) dma request logic transmit dma request receive dma request interrupt request (to interrupt controller) (to dma controller) external signals
uart modules mcf5213 reference manual, rev. 1.1 21-2 freescale semiconductor preliminary note uart n can be clocked by the dt n in pin. however, if the timers are used, then input capture mode is not available for that timer. the serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus cl ock or an external clock using the timer pin. the transmitter converts parallel data from the cpu to a serial bit stream, inserting appropriate start, stop, and parity bits. it outputs the resulting stream on the channel transmitter serial data output (u n txd). see section 21.4.2.1, ?transmitter .? the receiver converts serial data from th e channel receiver se rial data input (u n rxd) to parallel format, checks for a start, stop, and parity bits, or break conditions, and transf ers the assembled character onto the bus during read operations. the receiver may be pol led, interrupt driven, or use dma requests for servicing. see section 21.4.2.2, ?receiver .? note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 13, ?general purpose i/o module? ) prior to configuring the uart module. 21.1.2 features the device contains three independent ua rt modules with the following features: ? each clocked by an external clock or by the internal bus clock (eli minating a need for an external uart clock) ? full-duplex asynchronous/synchronous receiver/transmitter channel ? quadruple-buffered receiver ? double-buffered transmitter ? independently programmable receiver and transmitter clock sources ? programmable data format: ? 5?8 data bits plus parity ? odd, even, no parity, or force parity ? one, one-and-a-half, or two stop bits ? each channel programmable to normal (full-duplex ), automatic echo, local loop-back, or remote loop-back mode ? automatic wake-up mode for multidrop applications ? four maskable interrupt conditions ? all three uarts have dma request capability ? parity, framing, and overrun error detection ? false-start bit detection ? line-break detection and generation
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-3 preliminary ? detection of breaks originating in the middle of a character ? start/end break interrupt/status 21.2 external signal description figure 21-1 shows both the external and internal signal groups. an internal interrupt request signal is provided to notify the interrupt c ontroller of an interrupt condition. the output is the logica l nor of unmasked uisr n bits. the interrupt level and priority are programmed in the interrupt controller. see chapter 14, ?interrupt controller modules? for more information. note that the uarts can also be configured to auto matically transfer data by using the dma rather than interrupting the core. when there is data in the recei ver fifo or when the transmit holding register is empty, a dma request can be issued. for more information on generating dma requests, refer to section 21.4.6.1.2, ?setting up the uart to request dma service ,? and chapter 16, ?enhanced direct memory access (edma).? table 21-1 briefly describes th e uart module signals. note the terms ?assertion? and ?negation? are used to avoid confusion between active-low and active-high signals. ?ass erted? indicates that a signal is active, independent of the voltage level; ?negated? indicates that a signal is inactive. table 21-1. uart module signals signal description transmitter serial data output (u n txd) u n txd is held high (mark condition) when the tr ansmitter is disabled, idle, or operating in the local loop-back mode. data is shifted out on u n txd on the falling edge of the clock source, with the least significant bit (lsb) sent first. receiver serial data input (u n rxd) data received on u n rxd is sampled on the rising edge of the clock source, with the lsb received first. clear-to- send (u n cts ) this input can generate an interrupt on a change of state. request-to-send (u n rts ) this output can be programmed to be negated or asserted automatically by either the receiver or the transmitter. when connected to a transmitter?s u n cts , u n rts can control serial data flow.
uart modules mcf5213 reference manual, rev. 1.1 21-4 freescale semiconductor preliminary figure 21-2 shows a signal configuration for a uart/rs-232 interface. figure 21-2. uart/rs-232 interface 21.3 memory map/register definition this section contains a detailed de scription of each regist er and its specific f unction. flowcharts in section 21.4.6, ?programming ,? describe basic uart module pr ogramming. the opera tion of the uart module is controlled by writing control bytes into the appropriate registers. table 21-2 is a memory map for uart module registers. note uart registers are accessible only as bytes. note interrupt can mean either an interrupt request asserted to the cpu or a dma request. table 21-2. uart module memory map ispbar offset register access reset value section/page uart0 uart1 uart2 0x00_0200 0x00_0240 0x00_0280 uart mode registers 1 (umr1 n ), (umr2 n ) r/w 0x00 21.3.1/21-5 21.3.2/21-6 0x00_0204 0x00_0244 0x00_0284 uart status register (usr n ) r 0x00 21.3.3/21-8 uart clock select register 1 (ucsr n ) w 0x00 21.3.4/21-9 0x00_0208 0x00_0248 0x00_0288 uart command registers (ucr n ) w 0x00 21.3.5/21-10 0x00_020c 0x00_024c 0x00_028c uart receive buffers (urb n )r0xff 21.3.6/21-12 uart transmit buffers (utb n ) w 0x00 21.3.7/21-13 0x00_0210 0x00_0250 0x00_0290 uart input port change register (uipcr n )r[u n cts ] 21.3.8/21-13 uart auxiliary control register (uacr n ) w 0x00 21.3.9/21-14 u n rts do2 di1 u n cts u n txd u n rxd di2 do1 rs-232 transceiver uart
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-5 preliminary 21.3.1 uart mode registers 1 (umr1 n ) the umr1 n registers control configuration. umr1 n can be read or written when the mode register pointer points to it, at reset or after a reset mode register pointer command using ucr n [misc]. after umr1 n is read or written, th e pointer points to umr2 n . 0x00_0214 0x00_0254 0x00_0294 uart interrupt status register (uisr n ) r 0x00 21.3.10/21-14 uart interrupt mask register (uimr n ) w 0x00 0x00_0218 0x00_0258 0x00_0298 uart baud rate generator register (ubg1 n )w 2 0x00 21.3.11/21-16 0x00_021c 0x00_025c 0x00_029c uart baud rate generator register (ubg2 n )w 2 0x00 21.3.11/21-16 0x00_0234 0x00_0274 0x00_02b4 uart input port register (uip n )r0xff 21.3.12/21-17 0x00_0238 0x00_0278 0x00_02b8 uart output port bit set command register (uop1 n )w 2 0x00 21.3.13/21-17 0x00_023c 0x00_027c 0x00_02bc uart output port bit reset command register (uop0 n )w 2 0x00 21.3.13/21-17 1 umr1 n , umr2 n , and ucsr n should be changed only after the receiver/trans mitter is issued a software reset command. that is, if channel operation is not disabled, undesirable results may occur. 2 reading this register results in undesir ed effects and possible incorrect transmission or reception of characters. register contents may also be changed. address: 0x00_0200 (umr10) 0x00_0240 (umr11) 0x00_0280 (umr12) access: user read/write 1 7 6543210 r rxrts rxirq/ ffull err pm pt b/c w reset: 0 0 0 0 0 0 0 0 1 after umr1 n is read or written, the pointer points to umr2 n figure 21-3. uart mode registers 1 (umr1 n ) table 21-2. uart module memory map (continued) ispbar offset register access reset value section/page uart0 uart1 uart2
uart modules mcf5213 reference manual, rev. 1.1 21-6 freescale semiconductor preliminary 21.3.2 uart mode register 2 (umr2 n ) the umr2 n registers control uart module configuration. umr2 n can be read or written when the mode register pointer points to it, wh ich occurs after any access to umr1 n . umr2 n accesses do not update the pointer. table 21-3. umr1 n field descriptions field description 7 rxrts receiver request-to-send. allows the u n rts output to control the u n cts input of the transmitting device to prevent receiver overrun. if both the receiver and transmitter are incorrectly programmed for u n rts control, u n rts control is disabled for both. transmitter rts control is configured in umr2 n [txrts]. 0 the receiver has no effect on u n rts . 1 when a valid start bit is received, u n rts is negated if the uart's fifo is full. u n rts is reasserted when the fifo has an empty position available. 6 rxirq/ ffull receiver interrupt select. 0 rxrdy is the source that generates interrupt or dma requests. 1 ffull is the source that gene rates interrupt or dma requests. 5 err error mode. configures t he fifo status bits, usr n [rb,fe,pe]. 0 character mode. the usr n values reflect the status of the character at the top of the fifo. err must be 0 for correct a/d flag information when in multidrop mode. 1 block mode. the usr n values are the logical or of the status for a ll characters reaching the top of the fifo since the last reset error status command for the channel was issued. see section 21.3.5, ?uart command registers (ucrn) .? 4?3 pm parity mode. selects the parity or multidrop mode for the ch annel. the parity bit is added to the transmitted character, and the receiver performs a parity check on incoming dat a. the value of pm affects pt, as shown below. 2 pt parity type. pm and pt together select parity type (pm = 0x) or determine whether a data or address character is transmitted (pm = 11). 1?0 b/c bits per character. select the number of data bits per character to be sent. the values shown do not include start, parity, or stop bits. 00 5 bits 01 6 bits 10 7 bits 11 8 bits pm parity mode parity type (pt= 0) parity type (pt= 1) 00 with parity even parity odd parity 01 force parity low parity high parity 10 no parity n/a 11 multidrop mode data character address character
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-7 preliminary address: 0x00_0200 (umr20) 0x00_0240 (umr21) 0x00_0280 (umr22) access: user read/write 1 7 6543210 r cm txrts txcts sb w reset: 0 0 0 0 0 0 0 0 1 after umr1 n is read or written, the pointer points to umr2 n figure 21-5. uart mode register 2 (umr2 n ) table 21-4. umr2 n field descriptions field description 7?6 cm channel mode. selects a channel mode. section 21.4.3, ?looping modes ,? describes individual modes. 00 normal 01 automatic echo 10 local loop-back 11 remote loop-back 5 txrts transmitter ready-to-send. controls negation of u n rts to automatically terminate a message transmission. attempting to program a receiver and transmitter in the same channel for u n rts control is not permitted and disables u n rts control for both. 0 the transmitter has no effect on u n rts . 1 in applications where the transmitter is disabled after tran smission completes, setting this bit automatically clears uop[rts] one bit time after any characters in the chan nel transmitter shift and holding registers are completely sent, including the programmed number of stop bits.
uart modules mcf5213 reference manual, rev. 1.1 21-8 freescale semiconductor preliminary 21.3.3 uart status registers (usr n ) the usr n registers, shown in figure 21-6 , show the status of the transmit ter, the receiver, and the fifo. 4 txcts transmitter clear-to-send. if both txcts and txrts are se t, txcts controls the operation of the transmitter. 0 u n cts has no effect on the transmitter. 1 enables clear-to-send operation. th e transmitter checks the state of u n cts each time it is ready to send a character. if u n cts is asserted, the character is sent; if it is deasserted, the channel u n txd remains in the high state and transmission is delayed until u n cts is asserted. changes in u n cts as a character is being sent do not affect its transmission. 3?0 sb stop-bit length control. selects the length of the stop bi t appended to the transmitted char acter. stop-bit lengths of 9/16 to 2 bits are programmable for 6?8 bit characters. lengths of 1-1/16 to 2 bits are programmable for 5-bit characters. in all cases, the receiver checks only for a high condition at the center of t he first stop-bit position, that is, one bit time after the last data bit or after the parity bit, if parity is enabled. if an external 1x clock is used for the transmitter, clearing bit 3 selects one stop bit and setting bit 3 selects two stop bits for transmission. address: 0x00_0204 (ucsr0) 0x00_0244 (ucsr1) 0x00_0284 (ucsr2) access: user read-only 7 6543210 r rb fe pe oe txemp txrdy ffull rxrdy w reset: 0 0 0 0 0 0 0 0 figure 21-6. uart status register (usr n ) table 21-4. umr2 n field descriptions (continued) field description sb 5 bits 6?8 bits sb 5?8 bits 0000 1.063 0.563 1000 1.563 0001 1.125 0.625 1001 1.625 0010 1.188 0.688 1010 1.688 0011 1.250 0.750 1011 1.750 0100 1.313 0.813 1100 1.813 0101 1.375 0.875 1101 1.875 0110 1.438 0.938 1110 1.938 0111 1.500 1.000 1111 2.000
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-9 preliminary 21.3.4 uart clock select registers (ucsr n ) the ucsrs select an external cloc k on the dtin input (divided by 1 or 16) or a prescaled internal bus clock as the clocking source for th e transmitter and receiver. see section 21.4.1, ?transmitter/receiver clock source .? the transmitter and receiver can use different clock sources. to use the internal bus clock for both, set ucsr n to 0xdd. table 21-5. usr n field descriptions field description 7 rb received break. the received break circuit detects breaks th at originate in the middle of a received character. however, a break in the middle of a character must pers ist until the end of the next detected character time. 0 no break was received. 1 an all-zero character of the programmed length was rece ived without a stop bit. only a single fifo position is occupied when a break is received. further entries to the fifo are inhibited until u n rxd returns to the high state for at least one-half bit time, which is equal to two successive edges of the uart clock. rb is valid only when rxrdy = 1. 6 fe framing error. 0 no framing error occurred. 1 no stop bit was detected when the corresponding data c haracter in the fifo was re ceived. the stop-bit check occurs in the middle of the first stop-bit position. fe is valid only when rxrdy = 1. 5 pe parity error. valid only if rxrdy = 1. 0 no parity error occurred. 1 if umr1 n [pm] = 0 x (with parity or force parity), the correspondin g character in the fifo was received with incorrect parity. if umr1 n [pm] = 11 (multidrop), pe stores the received address or data (a/d) bit. pe is valid only when rxrdy = 1. 4 oe overrun error. indicates whether an overrun occurs. 0 no overrun occurred. 1 one or more characters in the received data stream ha ve been lost. oe is set upon receipt of a new character when the fifo is full and a character is already in the sh ift register waiting for an empty fifo position. when this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. oe is cleared by the reset error status command in ucr n . 3 temp transmitter empty. 0 the transmit buffer is not empty. either a character is being shifted out, or the transmitter is disabled. the transmitter is enabled/disabled by programming ucr n [tc]. 1 the transmitter has underrun (both the transmitter holding register and transmi tter shift registers are empty). this bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission. 2 txrdy transmitter ready. 0 the cpu loaded the transmitter holding r egister or the transmitter is disabled. 1 the transmitter holding register is em pty and ready for a character. txrdy is set when a character is sent to the transmitter shift register or when the transmitter is firs t enabled. if the transmitter is disabled, characters loaded into the transmitter holding register are not sent. 1 ffull fifo full. 0 the fifo is not full but may hold up to two unread characters. 1 a character was received and the receiver fifo is now full . any characters received when the fifo is full are lost. 0 rxrdy receiver ready. 0 the cpu has read the receive buffer and no characters remain in the fifo after this read. 1 one or more characters were received and are waiting in the receive buffer fifo.
uart modules mcf5213 reference manual, rev. 1.1 21-10 freescale semiconductor preliminary 21.3.5 uart command registers (ucr n ) the ucrs, shown in figure 21-8 , supply commands to the uart. only multiple commands that do not conflict can be specified in a single write to a ucr n . for example, reset transmitter and enable transmitter cannot be specified in one command. address: 0x00_0204 (ucsr0) 0x00_0244 (ucsr1) 0x00_0284 (ucsr2) access: user write-only 7 6543210 r w rcs tcs reset: 0 0 0 0 0 0 0 0 figure 21-7. uart clock select register (ucsr n ) table 21-6. ucsr n field descriptions field description 7?4 rcs receiver clock select. selects the cl ock source for the receiver channel. 1101 prescaled internal bus clock (f sys/2 ) 1110 dtin divided by 16 1111 dtin 3?0 tcs transmitter clock select. se lects the clock source fo r the transmitter channel. 1101 prescaled internal bus clock (f sys/2 ) 1110 dtin divided by 16 1111 dtin address: 0x00_0208 (ucr0) 0x00_0248 (ucr1) 0x00_0288 (ucr2) access: user write-only 7 6543210 r w 0 misc tc rc reset: 0 0 0 0 0 0 0 0 figure 21-8. uart command register (ucr n )
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-11 preliminary table 21-7 describes ucr n fields and commands. examples in section 21.4.2, ?transmitter and receiver operating modes ,? show how these commands are used. table 21-7. ucr n field descriptions field description 7 reserved, should be cleared. 6?4 misc misc field (this field selects a single command) command description 000 no command ? 001 reset mode register pointer causes the mode register pointer to point to umr1 n . 010 reset receiver immediately disables the receiver, clears usr n [ffull,rxrdy], and reinitializes the receiver fifo pointer. no other regist ers are altered. because it places the receiver in a known state, use this command instead of receiver disable when reconfiguring the receiver. 011 reset transmitter immediately disables the transmitter and clears usr n [txemp,txrdy]. no other registers are altered. because it places t he transmitter in a known state, use this command instead of transmitter disable when reconfiguring the transmitter. 100 reset error status clears usr n [rb,fe,pe,oe]. also used in block mode to clear all error bits after a data block is received. 101 reset break ? change interrupt clears the delta break bit, uisr n [db]. 110 start break forces u n txd low. if the transmitter is empty, the break may be delayed up to one bit time. if the transmitter is active, the break starts when character transmission completes. the break is delayed until any character in the transmitter shift register is sent. any character in the transmitter hold ing register is sent after the break. the transmitter must be enabled for the command to be accepted. this command ignores the state of u n cts . 111 stop break causes u n txd to go high (mark) within two bit times. any characters in the transmit buffer are sent.
uart modules mcf5213 reference manual, rev. 1.1 21-12 freescale semiconductor preliminary 21.3.6 uart receive buffers (urb n ) the receive buffers (shown in figure 21-9 ) contain one serial shift regi ster and three receiver holding registers, which act as a fifo. u n rxd is connected to the serial shif t register. the cpu reads from the top of the fifo while the receiver shifts and updates from the bottom when the shift register is full (see figure 21-20 ). rb contains the character in the receiver. 3?2 tc tc field (this field selects a single command) 1?0 rc rc (this field select s a single command) table 21-7. ucr n field descriptions (continued) field description command description 00 no action taken causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled. 01 transmitter enable enables operation of the channel?s transmitter. usr n [txemp,txrdy] are set. if the transmitter is already enabled, this command has no effect. 10 transmitter disable terminates transmitter operation and clears usr n [txemp,txrdy]. if a character is being sent when the transmitter is disabled, transmission completes before the transmitter becomes inactive. if the trans mitter is already disabled, the command has no effect. 11 ? reserved, do not use. command description 00 no action taken causes the receiver to stay in its curre nt mode. if the receiver is enabled, it remains enabled; if disabled, it remains disabled. 01 receiver enable if the uart module is not in multidrop mode (umr1 n [pm] 11), receiver enable enables the channel's receiver and forces it into search-for-start-bit state. if the receiver is already enabled, this command has no effect. 10 receiver disable disables the receiver immediately. any character being received is lost. the command does not affect receiver status bits or other control registers. if the uart module is programmed for local loop-back or multidrop mode, the receiver operates even though this command is selected. if the receiver is already disabled, the command has no effect. 11 ? reserved, do not use.
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-13 preliminary 21.3.7 uart transmit buffers (utb n ) the transmit buffers consist of th e transmitter holding register and th e transmitter shift register. the holding register accepts characters from the bus master if channel?s usr n [txrdy] is set. a write to the transmit buffer clears usr n [txrdy], inhibiting any more characters until the shift register can accept more data. when the shift register is empty, it checks if the holding regist er has a valid char acter to be sent (txrdy = 0). if there is a va lid character, the shift register loads it and sets usr n [txrdy] again. writes to the transmit buffer when the cha nnel?s txrdy = 0 and when the transm itter is disabled have no effect on the transmit buffer. figure 21-10 shows utb n . tb contains the character in the transmit buffer. 21.3.8 uart input port change registers (uipcr n ) the uipcrs, shown in figure 21-11 , hold the current state and the change-of-state for u n cts . address: 0x00_020c (urb0) 0x00_024c (urb1) 0x00_028c (urb2) access: user read-only 7 6543210 r rb w reset: 1 1 1 1 1 1 1 1 figure 21-9. uart receive buffer (urb n ) address: 0x00_020c (utb0) 0x00_024c (utb1) 0x00_028c (utb2) access: user write-only 7 6543210 r w tb reset: 0 0 0 0 0 0 0 0 figure 21-10. uart transmit buffer (utb n ) address: 0x00_0210 (uipcr0) 0x00_0250 (uipcr1) 0x00_0290 (uipcr2) access: user read-only 7 6543210 r 0 0 0 cos 0 0 0 cts w reset: 0 0 0 0 1 1 1 u n cts figure 21-11. uart input port change register (uipcr n )
uart modules mcf5213 reference manual, rev. 1.1 21-14 freescale semiconductor preliminary 21.3.9 uart auxiliary control register (uacr n ) the uacrs, shown in figure 21-9 , control the input enable. 21.3.10 uart interrupt status/mask registers (uisr n /uimr n ) the uisrs, shown in figure 21-13 , provide status for all pote ntial interrupt sources. uisr n contents are masked by uimr n . if corresponding uisr n and uimr n bits are set, the internal interrupt output is asserted. if a uimr n bit is cleared, the state of the corresponding uisr n bit has no effect on the output. the uisr n and uimr n registers share the same space in memory . reading this regist er provides the user with interrupt status, while writing controls the mask bits. table 21-8. uipcr n field descriptions field description 7?5 reserved, should be cleared. 4 cos change of state (high-to-low or low-to-high transition). 0 no change-of-state since the cpu last read uipcr n . reading uipcr n clears uisr n [cos]. 1 a change-of-state longer than 25?50 s occurred on the u n cts input. uacr n can be programmed to generate an interrupt to the cpu when a change of state is detected. 3?1 reserved, should be cleared. 0 cts current state of clear-to-send. starting two serial cl ock periods after reset, cts reflects the state of u n cts . if u n cts is detected asserted at that time, cos is set, which initiates an interrupt if uacr n [iec] is enabled. 0 the current state of the u n cts input is asserted. 1 the current state of the u n cts input is deasserted. address: 0x00_0210 (uacr0) 0x00_0250 (uacr1) 0x00_0290 (uacr2) access: user write-only 7 6543210 r w 0 0 0 0 0 0 0 iec reset: 0 0 0 0 0 0 0 0 figure 21-12. uart auxiliary control register (uacr n ) table 21-9. uacr n field descriptions field description 7?1 reserved, should be cleared. 0 iec input enable control. 0 setting the corresponding uipcr n bit has no effect on uisr n [cos]. 1uisr n [cos] is set and an interrupt is generated when the uipcr n [cos] is set by an external transition on the u n cts input (if uimr n [cos] = 1).
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-15 preliminary note true status is pr ovided in the uisr n regardless of uimr n settings. uisr n is cleared when the uart module is reset. address: 0x00_0214 (uisr0) 0x00_0254 (uisr1) 0x00_0294 (uisr2) access: user read/write 7 6543210 r (uisr n ) cos 0 0 0 0 db ffull/ rxrdy txrdy w (uimr n ) cos 0 0 0 0 db ffull/ rxrdy txrdy reset: 0 0 0 0 0 0 0 0 figure 21-13. uart interrupt status/mask registers (uisr n /uimr n ) table 21-10. uisr n /uimr n field descriptions field description 7 cos change-of-state. 0uipcr n [cos] is not selected. 1 change-of-state occurred on u n cts and was programmed in uacr n [iec] to cause an interrupt. 6?3 reserved, should be cleared. 2 db delta break. 0 no new break-change condition to report. section 21.3.5, ?uart command registers (ucrn) ,? describes the reset break - change interrupt command. 1 the receiver detected the beginning or end of a received break. 1 ffull/ rxrdy status of fifo or receiver, depending on umr1[ffull/rxrdy] bit. duplicate of usr n [fifo] & usr n [rxrdy] 0 txrdy transmitter ready. this bit is the duplication of usr n [txrdy]. 0 the transmitter holding register was loaded by the cpu or the transmitter is disabled. characters loaded into the transmitter holding register when txrdy = 0 are not sent. 1 the transmitter holding register is empt y and ready to be loaded with a character. uimr n [ffull/rxrdy] uisr n [ffull/rxrdy] umr1 n [ffull/rxrdy] 0 (rxrdy) 1 (fifo) 0 0 receiver not ready fifo not full 1 0 receiver not ready fifo not full 0 1 receiver is ready, do not interrupt fifo is full, do not interrupt 1 1 receiver is ready, interrupt fifo is full, interrupt
uart modules mcf5213 reference manual, rev. 1.1 21-16 freescale semiconductor preliminary 21.3.11 uart baud rate ge nerator registers (ubg1 n /ubg2 n ) the ubg1 n registers hold the msb, and the ubg2 n registers hold the lsb of the preload value. ubg1 n and ubg2 n concatenate to provide a divider to the inte rnal bus clock for tran smitter/receiver operation, as described in section 21.4.1.2.1, ?internal bus clock baud rates .? note the minimum value that can be loaded on the concatenation of ubg1 n with ubg2 n is 0x0002. the ubg2 n reset value of 0x00 is invalid and must be written to before the uart transmit ter or receiver are enabled. both ubg1 n and ubg2 n are write-only and cannot be read by the cpu. address: 0x00_0218 (ubg10) 0x00_0258 (ubg11) 0x00_0298 (ubg12) access: user write-only 7 6543210 r w divider msb reset: 0 0 0 0 0 0 0 0 figure 21-14. uart baud rate generator register (ubg1 n ) address: 0x00_021c (ubg20) 0x00_025c (ubg21) 0x00_029c (ubg22) access: user write-only 7 6543210 r w divider lsb reset: 0 0 0 0 0 0 0 0 figure 21-15. uart baud rate generator register (ubg2 n )
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-17 preliminary 21.3.12 uart input port register (uip n ) the uip n registers, shown in figure 21-17 , show the current state of the u n cts input. 21.3.13 uart output port command registers (uop1 n /uop0 n ) the u n rts output can be asserted by writing a 1 to uop1 n [rts] and negated by writing a 1 to uop0 n [rts]. see figure 21-18 . address: 0x00_0234 (uip0) 0x00_0274 (uip1) 0x00_02b4 (uip2) access: user read-only 7 6543210 r 0 0 0 0 0 0 0 cts w reset: 1 1 1 1 1 1 1 1 figure 21-17. uart input port register (uip n ) table 21-12. uip n field descriptions field description 7?1 reserved, should be cleared. 0 cts current state of clear-to-send. the u n cts value is latched and reflects the state of the input pin when uip n is read. note: this bit has the same function and value as uipcr n [rts]. 0 the current state of the u n cts input is logic 0. 1 the current state of the u n cts input is logic 1. address: 0x00_0238 (uop10) 0x00_023c (uop00) 0x00_0278 (uop11) 0x00_027c (uop01) 0x00_02b8 (uop12) 0x00_02bc (uop02) access: user write-only 7 6543210 r w rts reset: 0 0 0 0 0 0 0 0 figure 21-18. uart output port command registers (uop1 n /uop0 n ) table 21-13. uop1 n /uop0 n field descriptions field description 7?1 reserved, should be cleared. 0 rts output port output. controls asse rtion (uop1)/negation (uop0) of u n rts output. 0 not affected. 1 asserts u n rts in uop1. negates u n rts in uop0.
uart modules mcf5213 reference manual, rev. 1.1 21-18 freescale semiconductor preliminary 21.4 functional description this section describes operation of the clock source generator, tran smitter, and receiver. 21.4.1 transmitter/receiver clock source the internal bus clock serves as the basic timing reference for the cl ock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each uart. the clock generator might not produce standard baud rates if the internal bus clock is used, so enable the 16-bit divider. 21.4.1.1 programmable divider as figure 21-19 shows, the uart n transmitter and receiver can us e the following clock sources: ? an external clock signal on the dt n in pin. when not divided, dt n in provides a synchronous clock mode; when divide d by 16, it is asynchronous . ? the internal bus clock supplies an asynchronous cl ock source that is divide d by 32 and then divided by the 16-bit value programmed in ubg1 n and ubg2 n . see section 21.3.11, ?uart baud rate generator registers (ubg1n/ubg2n) .? the choice of dtin or internal bus clock is programmed in the ucsr. figure 21-19. clocking source diagram note if dt n in is a clocking source for either the timer or uart, that timer module cannot use dt n in for timer input capture. uart on-chip tin 1 16 clock generator 16-bit divider 32 tin clocking sources programmed in ucsr timer module dt n out dt n in u n txd u n rxd tx rx rx buffer tx buffer f sys/2 16-bit divider 16-bit divider
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-19 preliminary 21.4.1.2 calculati ng baud rates the following sections describe how to calculate baud rates. 21.4.1.2.1 internal bus clock baud rates when the internal bus clock is the uart clocking source, it goes through a di vide-by-32 prescaler and then passes through the 16-bit divider of the concatenated ubg1 n and ubg2 n registers. the baud-rate calculation is as follows: eqn. 21-1 using a 66 mhz internal bus cloc k and letting baud rate = 9600, then eqn. 21-2 therefore ubg1 n = 0x00 and ubg2 n = 0xd6. 21.4.1.2.2 external clock an external source clock (dt n in) can be used as is or divided by 16. if f extc is the external clock frequency, then the baud rate can be described with this equation: eqn. 21-3 21.4.2 transmitter and receiver operating modes figure 21-20 is a functional block diagra m of the transmitter and receiver showing the command and operating registers, which are descri bed generally in the following sect ions and described in detail in section 21.3, ?memory map/ register definition .? baudrate f sys 2 ? 32 x divider [] ----------------------------------- = divider 66 mhz 32 x 9600 [] ------------------------------ - 215 decimal () 0x00d6 hexadecimal () == = baudrate f extc (16 or 1) (16-bit divider) --------------------------------------------------------------- - =
uart modules mcf5213 reference manual, rev. 1.1 21-20 freescale semiconductor preliminary figure 21-20. transmitter and receiver functional diagram 21.4.2.1 transmitter the transmitter is enabled thr ough the uart command register (ucr n ). when it is ready to accept a character, the uart sets usr n [txrdy]. the transmitter converts parall el data from the cpu to a serial bit stream on u n txd. it automatically sends a start bit foll owed by the programmed number of data bits, an optional parity bit, and the progr ammed number of stop bits. the lsb is sent first. data is shifted from the transmitter output on the fall ing edge of the clock source. after the stop bits are sent, if no new characte r is in the transmitter holding register, the u n txd output remains high (mark condition) and the transmitter empty bit, usr n [txemp], is set. transmission resumes and txemp is cleared when the cpu load s a new character into the uart transmit buffer (utb n ). if the transmitter r eceives a disable command, it continues until any charact er in the transmitter shift register is completely sent. if the transmitter is reset through a software command, opera tion stops immediately (see section 21.3.5, ?uart command registers (ucrn) ?). the transmitter is reenabled through the ucr n to resume operation after a disabl e or software reset. if the clear-to-send operation is enabled, u n cts must be asserted for the character to be transmitted. if u n cts is negated in the middle of a transmission, the character in the shift register is sent and u n txd remains in mark state until u n cts is reasserted. if the transmitter is forced to send a continuous low condition by issuing a send break command, the transmitter ignores the state of u n cts . receiver shift register uart command register (ucr n )w uart status register (usr n ) r transmitter shift register uart mode register 1 (umr1 n )r/w uart mode register 2 (umr2 n )r/w transmitter holding register w receiver holding register 3 receiver holding register 2 receiver holding register 1 r uart receive uart buffer (urb n ) (4 registers) uart n external interface u n rxd u n txd transmit buffer (utb n ) (2 registers) fifo
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-21 preliminary if the transmitter is programme d to automatically negate u n rts when a message transmission completes, u n rts must be asserted manually before a message is se nt. in applications in which the transmitter is disabled after transmis sion is complete and u n rts is appropriately programmed, u n rts is negated one bit time after the character in the sh ift register is completely transmit ted. the transmitter must be manually reenabled by reasserting u n rts before the next message is to be sent. figure 21-21 shows the functional timing information for the transmitter. figure 21-21. transmitter timing diagram 21.4.2.2 receiver the receiver is enabled through its ucr n , as described in section 21.3.5, ?uart command registers (ucrn) .? when the receiver detects a high-to-low (mark-to-space) tr ansition of the start bit on u n rxd, the state of u n rxd is sampled eight times on the edge of the bit time clock starti ng one-half clock af ter the transition (asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). if u n rxd is sampled high, the start bit is invalid and the search for the valid start bit begins again. if u n rxd is still low, a valid start bit is assumed and the receiver continues samp ling the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. data on the u n rxd input is sampled on the rising edge of the c1 1 c2 c3 break c4 c6 u n txd tr a n s m i t t e r enabled usr n [txrdy] w 2 wwwwwww u n cts 3 u n rts 4 manually asserted by bit - set command manually asserted start break c5 not transmitted c6 c4 stop break c3 c2 c1 1 c1 in transmission 3 umr2 n [txcts] = 1 1 c n = transmit characters 2 w = write 4 umr2 n [txrts] = 1 internal module select
uart modules mcf5213 reference manual, rev. 1.1 21-22 freescale semiconductor preliminary programmed clock source. the lsb is received first. the data is then transferred to a receiver holding register and usr n [rxrdy] is set. if the character is less th an eight bits, the most significant unused bits in the receiver holding register are cleared. after the stop bit is detected, the re ceiver immediately looks for the next start bit. however, if a non-zero character is received without a stop bit (fr aming error) and u n rxd remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit were detected. parity error, framing error, overrun error, and r eceived break conditions set the respective pe, fe, oe, rb error and break flags in the usr n at the received character boundary and are valid only if usr n [rxrdy] is set. if a break condition is detected (u n rxd is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register and usr n [rb,rxrdy] are set. u n rxd must return to a high condition for at least one-half bit ti me before a search for the next start bit begins. the receiver detects the beginning of a break in the middle of a character if the break pe rsists through the next character time. if the break begins in the mi ddle of a character, the r eceiver places the damaged character in the rx fifo and sets the corresponding usr n error bits and usr n [rxrdy]. then, if the break lasts until the next character time, the receiver pl aces an all-zero character into the rx fifo and sets usr n [rb,rxrdy]. figure 21-22 shows receiver functional timing. figure 21-22. receiver timing 21.4.2.3 fifo the fifo is used in the uart?s receive buffer logic. th e fifo consists of three receiver holding registers. the receive buffer consists of the fifo and a receiver shift register connected to the u n rxd (see c1 c2 c4 c6 c7 c8 c3 c5 c6, c7, and c8 will be lost (c2) status data (c3) status data (c4) status data c5 will be lost reset by command u n txd receiver enabled usr n [rxrdy] overrun u n rts 1 internal module select usr n [ffull] (c1) status data usr n [oe] automatically asserted when ready to receive manually asserted first time, automatically negated if overrun occurs uop0[rts] = 1 1 umr2 n [txrts] = 1
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-23 preliminary figure 21-20 ). data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the fifo. thus, da ta flowing from the receiver to the cpu is quadruple-buffered. in addition to the data byt e, three status bits, pari ty error (pe), framing erro r (fe), and received break (rb), are appended to each data character in the fifo; oe (overrun error) is not appended. by programming the err bit in the channel?s mode register (umr1 n ), status is provided in character or block modes. usr n [rxrdy] is set when at least one character is availa ble to be read by the cpu. a read of the receive buffer produces an output of data from the top of the fifo. after the read cycle, the data at the top of the fifo and its associated st atus bits are popped and the receiver shift register can add new data at the bottom of the fifo. the fifo-full status bi t (ffull) is set if all three positions are filled with data. either the rxrdy or ffull bit can be selected to cause an in terrupt and either txrdy or rxrdy can be used to generate a dma request. the two error modes are selected by umr1 n [err] as follows: ? in character mode (umr1 n [err] = 0, status is given in the usr n for the character at the top of the fifo. ? in block mode, the usr n shows a logical or of all character s reaching the top of the fifo since the last reset error status command. status is updated as char acters reach the top of the fifo. block mode offers a data-r eception speed advantage wher e the software overhead of error-checking each character cannot be tolerated. ho wever, errors are not detected until the check is performed at the end of an entire messa ge?the faulting character is not identified. in either mode, reading the usr n does not affect the fifo. the fifo is popped only when the receive buffer is read. the usr n should be read before reading the rece ive buffer. if all three receiver holding registers are full, a new character is held in the receive r shift register until space is available. however, if a second new character is rece ived, the contents of the ch aracter in the receiver sh ift register is lost, the fifos are unaffected, and usr n [oe] is set when the receiver det ects the start bit of the new overrunning character. to support flow control, the receiver can be programmed to automatically negate and assert u n rts , in which case the receiver automatically negates u n rts when a valid start bit is detected and the fifo is full. the receiver asserts u n rts when a fifo position becomes availa ble; therefore, overrun errors can be prevented by connecting u n rts to the u n cts input of the transmitting device. note the receiver can still read characters in the fifo if the receiver is disabled. if the receiver is reset, the fifo, u n rts control, all receiver status bits, and interrupts, and dma requests are reset. no more characters are received until the receiver is reenabled. 21.4.3 looping modes the uart can be configured to operate in various l ooping modes, as shown in figure 21-22 . these modes are useful for local and remote system diagnostic functions. the modes are de scribed in the following paragraphs and in section 21.3, ?memory map/register definition .?
uart modules mcf5213 reference manual, rev. 1.1 21-24 freescale semiconductor preliminary the uart?s transmitter and receiver should be disabl ed when switching between modes. the selected mode is activated immediately upon m ode selection, regardless of whet her a character is being received or transmitted. 21.4.3.1 automatic echo mode in automatic echo mode, shown in figure 21-23 , the uart automatically rese nds received data bit by bit. the local cpu-to-receiver communi cation continues normally, but th e cpu-to-transmitter link is disabled. in this mode, received data is cl ocked on the receiver clock and re-sent on u n txd. the receiver must be enabled, but the transmitter need not be. figure 21-23. automatic echo because the transmitter is inactive, usr n [txemp,txrdy] are inactive and data is sent as it is received. received parity is checked but no t recalculated for transmission. charac ter framing is also checked, but stop bits are sent as they are recei ved. a received break is echoed as rece ived until the next valid start bit is detected. 21.4.3.2 local loop-back mode figure 21-24 shows how u n txd and u n rxd are internally connected in local loop-back mode. this mode is for testing the operation of a local uart module channel by se nding data to the transmitter and checking data assembled by the rece iver to ensure proper operations. figure 21-24. local loop-back features of this local loop- back mode are as follows: ? transmitter and cpu-to-rece iver communications continue normally in this mode. ?u n rxd input data is ignored. ?u n txd is held marking. ? the receiver is clocked by the transmitter clock. the transmitter must be enabled, but the receiver need not be. 21.4.3.3 remote loop-back mode in remote loop-back mode, shown in figure 21-25 , the channel automatically tr ansmits received data bit by bit on the u n txd output. the local cpu-to-tra nsmitter link is disabled. this mode is useful in testing disabled disabled u n rxd input u n txd output tx rx cpu cpu disabled disabled u n rxd input u n txd output tx rx
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-25 preliminary receiver and transmitter operation of a remote channel. for this mode, the transmitter uses the receiver clock. because the receiver is not active, received data cannot be read by the cpu and all status conditions are inactive. received parity is not check ed and is not recalculated for transm ission. stop bits ar e sent as they are received. a received break is echoed as receive d until the next valid start bit is detected. figure 21-25. remote loop-back 21.4.4 multidrop mode setting umr1 n [pm] programs the uart to ope rate in a wake-up mode for multidrop or multiprocessor applications. in this mode, a mast er can transmit an address charac ter followed by a block of data characters targeted for one of up to 256 slave stations. although slave stations have their ch annel receivers disabled, they cont inuously monitor the master?s data stream. when the master sends an address character, the sl ave receiver channel notif ies its respective cpu by setting usr n [rxrdy] and generating an inte rrupt (if programmed to do so ). each slave station cpu then compares the received address to its station addre ss and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. sl ave stations not a ddressed continue monitoring the data stream. data fiel ds in the data stream are separate d by an address character. after a slave receives a block of data, it s cpu disables the receiver and rep eats the process. functional timing information for multidrop mode is shown in figure 21-26 . cpu disabled disabled u n rxd input u n txd input tx rx disabled disabled
uart modules mcf5213 reference manual, rev. 1.1 21-26 freescale semiconductor preliminary figure 21-26. multidrop mode timing diagram a character sent from the master st ation consists of a start bit, a programmed number of data bits, an address/data (a/d) bit flag, and a programmed number of stop bits. a/d = 1 indicates an address character; a/d = 0 indicates a data character. the polarity of a/d is selected through umr1 n [pt]. umr1 n should be programmed before enabling the transmitter and load ing the corresponding data bits into the transmit buffer. in multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. if the receiver is disabled, it sets the rxrdy bit and loads the character into the receiver holding register fifo provi ded the received a/d bit is a one (address tag). the character is discarded if the received a/d bit is zero (data tag). if the receiver is enabled, all received characters are transferred to the cpu through the receive r holding register during read operations. in either case, the data bits are loaded into the data portion of the fifo while the a/d bit is loaded into the status portion of the fifo normal ly used for a parity error (usr n [pe]). framing error, overrun error, and break detection operate normally. th e a/d bit takes the place of the parity bit; therefore, parity is ne ither calculated nor checked. messages in this mode may st ill contain error detection and correction information. one way to pr ovide error detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. add1 u n txd transmitter enabled usr n [txrdy] c0 add2 11 internal module select a/d a/d a/d add1 u n rxd receiver enabled usr n [rxrdy] c0 add2 11 internal module select a/d a/d a/d 0 a/d 0 a/d (c0) status data (add 2) status data add 1 peripheral station master station umr1 n [pm] = 11 umr1 n [pm] = 11 umr1 n [pt] = 1 add 1 umr1 n [pt] = 0 c0 umr1 n [pt] = 2 add 2 umr1 n [pm] = 11
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-27 preliminary 21.4.5 bus operation this section describes bus operati on during read, write, and interrupt acknowledge cycles to the uart module. 21.4.5.1 read cycles the uart module responds to reads with byte data. reserved registers return zeros. 21.4.5.2 write cycles the uart module accepts write data as bytes only. wr ite cycles to read-only or reserved registers complete normally wit hout exception processing, but data is ignored. 21.4.6 programming the software flowchart, figure 21-27 , consists of the following: ? uart module initialization?these routines c onsist of sinit and ch chk (see sheet 1 p. 21-30 and sheet 2 p. 21-31). before sinit is called at sy stem initialization, the calling routine allocates 2 words on the system fifo. on return to the cal ling routine, sinit passes uart status data on the fifo. if sinit finds no errors , the transmitter and receiver are enabled. sinit calls chchk to perform the checks. when calle d, sinit places the uart in lo cal loop-back mode and checks for the following errors: ? transmitter never ready ? receiver never ready ? parity error ? incorrect character received ? i/o driver routine?this routine (see sheet 4 p. 21-33 and sheet 5 p. 21-34) consists of inch, the terminal input character routin e which gets a character from the receiver, and outch, which sends a character to the transmitter. ? interrupt handling?consists of sirq (see shee t 4 p. 21-33), which is executed after the uart module generates an interrupt cau sed by a change-in-break (begi nning of a break). sirq then clears the interrupt source , waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 21.4.6.1 interrupt and dma request initialization 21.4.6.1.1 setting up the uart to generate co re interrupts the list below gives the steps needed to properly ini tialize the uart to generate an interrupt request to the core. 1. initialize icr x register in the interrupt controller. 2. unmask appropriate bits in imr in the interrupt controller. 3. unmask appropriate bits in the core?s st atus register (sr) to enable interrupts.
uart modules mcf5213 reference manual, rev. 1.1 21-28 freescale semiconductor preliminary 4. if txrdy or rxrdy are being us ed to generate interrupt reques ts, then verify that dmareqc (in the scm) does not also assign the uart?s txrdy and rxrdy into dma channels 5. initialize interrupts in the uart, see table 21-14 . 21.4.6.1.2 setting up the uart to request dma service the uart is capable of generati ng two different dma request si gnals?transmit dma requests and receive dma requests. the transmit dma request signal is asserted when the txr dy (transmitter ready) in the uart interrupt status register, uisr n [txrdy], is set. when the transmit dm a request signal is a sserted, the dma can initiate a data copy, reading the next character to be trans mitted from memory and wr iting it into the uart transmit buffer (utb n ). this would allow the dma channel to stream data from memory to the uart for transmission without processor in tervention. once the entire message has been moved into the uart, the dma would typically generate an end-of-data-transfer interrupt re quest to the cpu. the resulting interrupt service routine (isr) could query the uart programming model to determine the end-of-transmission status. similarly, the receive dma request signal is assert ed when the ffull/rxrdy (fifo full or receive ready) flag in the interrupt status register, uisr n [ffull/rxrdy], is set. when the receive dma request signal is asserted, the dma can initiate a data move , reading the appropriate characters from the uart receive buffer (urb n ) and storing them in memory . this allows the dma channe l to stream data from the uart receive buffer into memory without processo r intervention. once the entire message has been moved from the uart, the dma would typically generate an end-of-data-transfer interrupt request to the cpu. the resulting interrupt service routine (i sr) should query the uart programming model to determine the end-of-transmission st atus. in typical applications, th e receive dma request should be configured to use rxrdy directly (a nd not ffull) to remove any comp lications related to retrieving the final characters from the fifo buffer. the implementation described in this section allows independent dma processi ng of transmit and receive data while still supporting interrupt notification to the processor for cts change-of-state and delta break error handling. table 21-14. uart interrupts register bit interrupt umr1 n 6rxirq uimr n 7 change of state (cos) uimr n 2 delta break uimr n 1 rxfifo full uimr n 0txrdy
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-29 preliminary to configure the uart for dma requests: 1. initialize the dmareqc in the scm to map th e desired uart dma requests to the desired dma channels. for example; setting dmareqc[7:4] to 1000 maps uart0 receive dma requests to dma channel 1; setting dmareq c[11:8] to 1101 maps uart1 tr ansmit dma requests to dma channel 2; and so on. it is possible to independe ntly map transmit based and receive based uart dma requests in the dmareqc. 2. disable interrupts using the uimr register. the appropriate uimr bits must be cleared so that interrupt requests are disabled for those conditions for which a dma request is desired. for example; to generate transmit dma request s from uart1, then uimr1[txrdy] should be cleared. this will prevent txr dy from generating an interrupt request while a transmit dma request is generated. 3. configure the gpacr and appropriate pacr regi sters located in the scm for dma access to ipsbar space. 4. initialize the dma channel. th e dma should be configur ed for cycle steal m ode and a source and destination size of one byte. this will cause a single byte to be transfer red for each uart dma request. table 21-15 shows the dma requests. 21.4.6.2 uart module initialization sequence table 21-16 shows the uart module initialization sequence. table 21-15. uart dma requests register bit dma request uisr n 1 receive dma request uisr n 0 transmit dma request table 21-16. uart module initialization sequence register setting ucr n reset the receiver and transmitter. reset the mode pointer (misc[2?0] = 0b001). uimr n enable the desired interrupt sources. uacr n initialize the input enable control (iec bit). ucsr n select the receiver and transmitter cloc k. use timer as source if required. umr1 n if preferred, program operation of receiver ready-to-send (rxrts bit). select receiver-ready or fifo-full notification (rxrdy/ffull bit). select character or bloc k error mode (err bit). select parity mode and type (pm and pt bits). select number of bits per character (b/cx bits).
uart modules mcf5213 reference manual, rev. 1.1 21-30 freescale semiconductor preliminary umr2 n select the mode of operation (cmx bits). if preferred, program operation of transmitter ready-to-send (txrts). if preferred, program operation of clear-to-send (txcts bit). select stop-bit length (sbx bits). ucr n enable transmitter and/or receiver. figure 21-27. uart mode programming flowchart (sheet 1 of 5) table 21-16. uart module initialization sequence (continued) register setting serial module sinit initiate: channel interrupts chk1 call chchk save channel status enable any errors ? y n enable receiver assert request to send sinitr return
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-31 preliminary figure 21-27. uart mode programming flowchart (sheet 2 of 5) chchk chchk place channel in local loopback mode enable transmitter clear status word txchk is transmitter ready ? y n sndchr rxchk send character to transmitter has character been received ? n y a waited too long ? n n waited too long ? y y set transmitter- never-ready flag set receiver- never-ready flag b
uart modules mcf5213 reference manual, rev. 1.1 21-32 freescale semiconductor preliminary figure 21-27. uart mode programming flowchart (sheet 3 of 5) a b b frchk have framing error ? set framing error flag prchk have pa r i t y e r r o r ? set parity error flag get character from receiver same as transmitted character ? set incorrect character flag n n y chrchk y n disable transmitter rstchn restore to original mode return
uart modules mcf5213 reference manual, rev. 1.1 freescale semiconductor 21-33 preliminary figure 21-27. uart mode programming flowchart (sheet 4 of 5) was irq caused by beginning of a break ? sirq abrki n clear change-in- break status bit abrki1 n has end-of-break irq arrived yet ? y y clear change-in- break status bit remove break character from receiver fifo replace return address on system stack and monitor warm start address sirqr rte n y does channel a receiver have a character ? inch place character in d0 return
uart modules mcf5213 reference manual, rev. 1.1 21-34 freescale semiconductor preliminary figure 21-27. uart mode programming flowchart (sheet 5 of 5) outch is transmitter ready ? n y send character to transmitter return
mcf5213 reference manual, rev. 1.1 freescale semiconductor 22-1 preliminary chapter 22 i 2 c interface 22.1 introduction this chapter describes the i 2 c module, clock synchronization, and i 2 c programming model registers. it also provides extensiv e programming examples. 22.2 overview i 2 c is a two-wire, bidirectional seri al bus that provides a simple, effi cient method of data exchange, minimizing the interconnecti on between devices. this bus is suit able for applications that require occasional communication betwee n many devices over a short distance. the flexible i 2 c bus allows additional devices to be connected to the bus for expansion and system development. the interface is designed to operate up to 100 kbps with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of the inte rnal bus clock divided by 20, with reduced bus loading. the maximum communication le ngth and the number of devices that can be connected are limited by a maxi mum bus capacitance of 400 pf. the i 2 c system is a true multiple-master bus; it uses arbitration and collision detection to prevent data corruption in the event that multip le devices attempt to control the bus simultaneously. this feature supports complex applications with multiprocessor cont rol and can be used for ra pid testing and alignment of end products through external connect ions to an assembly-line computer. note the i 2 c module is designed to be compatible with the philips i 2 c bus protocol. for information on syst em configuration, protocol, and restrictions, see the i 2 c bus specification, version 2.1 . note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 13, ?general purpose i/o module? ) prior to configuring the i 2 c module. 22.3 features the i 2 c module has the following key features: ? compatibility with i 2 c bus standard version 2.1 ? support for 3.3-v tolerant devices ? multiple-master operation
i 2 c interface mcf5213 reference manual, rev. 1.1 22-2 freescale semiconductor preliminary ? software-programmable for one of 50 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection figure 22-1 is a block diagram of the i 2 c module. figure 22-1. i 2 c module block diagram address compare in/out data shift start, stop, input sync clock control registers and coldfire interface address decode i 2 c address data mux i2c_sda i2c_scl address irq data and arbitration control register internal bus register (iadr) i 2 c frequency divider register (ifdr) i 2 c data i/o register (i2dr) i 2 c status register (i2sr) i 2 c control register (i2cr)
i 2 c interface mcf5213 reference manual, rev. 1.1 freescale semiconductor 22-3 preliminary figure 22-1 shows the i 2 c registers, which are described in section 22.5, ?memory map/register definition? : ?i 2 c address register (i2adr) ?i 2 c frequency divider register (i2fdr) ?i 2 c control register (i2cr) ?i 2 c status register (i2sr) ?i 2 c data i/o register (i2dr) 22.4 i 2 c system configuration the i 2 c module uses a serial da ta line (i2c_sda) and a serial clock line (i2c_scl ) for data transfer. for i 2 c compliance, all devices connected to these two signals must have ope n drain or open collector outputs. the logic and function is exercised on both lines with external pull-up resistors. out of reset, the i 2 c default state is as a slave receiver. thus , when not programmed to be a master or responding to a slave transmit address, the i 2 c module should return to the de fault slave receiver state. see section 22.6.1, ?initialization sequence,? for exceptions. normally, a standard communication is composed of four parts: start signal, slave addr ess transmission, data transfer, and stop signal. these ar e discussed in the following sections. 22.4.1 start signal when no other device is bus master (both i2c_scl and i2c_sda lines are at logic high), a device can initiate communication by sendi ng a start signal (see a in figure 22-2 ). a start signal is defined as a high-to-low transition of i2c_sd a while i2c_scl is high. this signal denotes th e beginning of a data transfer (each data transfer can be se veral bytes long) and awakens all slaves. figure 22-2. i 2 c standard communication protocol 12345678 12345678 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address r/w ack bit data byte no ack bit stop signal lsb msb lsb msb i2c_sda i2c_scl start signal a b d c e f i2c_scl held low while interrupt is serviced interrupt bit set (byte complete)
i 2 c interface mcf5213 reference manual, rev. 1.1 22-4 freescale semiconductor preliminary 22.4.2 slave address transmission the master sends the slave address in the first byte after the start signa l (b). after the seven-bit calling address, it sends the r/w bit (c), wh ich tells the slave data transfer direction (0 = write transfer, 1 = read transfer). each slave must have a unique address. an i 2 c master must not transmit it s own slave address; it cannot be master and slave at the same time. the slave whose address matches that sent by the master pulls i2c_sda low at the ninth serial clock (d) to return an acknowledge bit. 22.4.3 data transfer when successful slave addressing is achieve d, the data transfer can proceed (see e in figure 22-2 ) on a byte-by-byte basis in the dire ction specified by the r/w bi t sent by the calling master. data can be changed only while i2c_scl is low and must be held stable while i2c_scl is high, as figure 22-2 shows. i2c_scl is pulsed once fo r each data bit, with the msb being sent first. the receiving device must acknowledge each byte by pulling i2c_sda low at the ninth clock; therefore, a data byte transfer takes nine clock pulses. see figure 22-3 . figure 22-3. data transfer 22.4.4 acknowledge the transmitter releases the i2 c_sda line high during the acknow ledge clock pulse as shown in figure 22-4 . the receiver pulls down the i2c_sda line dur ing the acknowledge cloc k pulse so that it remains stable low during the high period of the clock pulse. if it does not acknowledge the master, the slave receiver must l eave i2c_sda high. the master can then generate a stop signal to abort the data transfer or generate a start signal (r epeated start, shown in figure 22-5 and discussed in section 22.4.6, ?repeated start? ) to start a new calling sequence. 123456789 5678 i2c_scl 4 3 2 1 bit6 bit4 bit3 bit2 bit1 bit5 i2c_sda bit7 bit0 bit6 bit4 bit3 bit2 bit1 bit5 bit0 bit7 start signal ack from receiver stop no ack bit data byte slave address r/w signal interrupt bit set (byte complete) i2c_scl held low while interrupt is serviced 9
i 2 c interface mcf5213 reference manual, rev. 1.1 freescale semiconductor 22-5 preliminary figure 22-4. acknowledgement by receiver if the master receiver does not acknowledge the slav e transmitter after a byte transmission, it means end-of-data to the slave. the slave releases i2c_sda for the master to generate a stop or start signal ( figure 22-4 ). 22.4.5 stop signal the master can terminate communicat ion by generating a stop signal to free the bus. a stop signal is defined as a low-to-high transition of i2c_sda while i2c_scl is at logical high (see f in figure 22-2 ). the master can generate a stop even if the slave has generated an acknowledgment, at which point the slave must release the bus. the master may also ge nerate a start signal foll owing a calling address, without first generating a stop signal. refer to section 22.4.6, ?repeated start.? 22.4.6 repeated start a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. the master uses a repeated star t to communicate with anot her slave or with the same slave in a different mode (transmit /receive mode) without releasing the bus. figure 22-5. repeated start 56789 i2c_scl 4 3 2 1 bit6 bit4 bit3 bit2 bit1 bit5 i2c_sda by transmitter bit7 bit0 start signal r/w i2c_sda by receiver ack i2c_scl 1234567 8 12 5 678 34 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w 99 xx new calling address r/w no stop ack bit stop signal repeated start signal ack bit r/w calling address start i2c_sda msb lsb msb lsb signal a
i 2 c interface mcf5213 reference manual, rev. 1.1 22-6 freescale semiconductor preliminary various combinations of read/w rite formats are then possible: ? the first example in figure 22-6 is the case of master-transmitter transmitting to slave-receiver. the transfer directi on is not changed. ? the second example in figure 22-6 is the master reading the slave immediately after the first byte. at the moment of the first acknowledge, the mast er-transmitter becomes a master-receiver and the slave-receiver becomes slave-transmitter. ? in the third example in figure 22-6 , the start condition and slave a ddress are both repeated using the repeated start signal. this is to communicat e with same slave in a different mode without releasing the bus. the master transmits data to the slave first, and then the master reads data from slave by reversi ng the r/w bit. figure 22-6. data transfer, combined format 1 note: no acknowledge on the last byte 22.4.7 clock synchronization and arbitration i 2 c is a true multi-master bus that allows more than one master to be connected to it. if two or more master devices simultaneously request control of the bus, a clock synchronization proc edure determines the bus clock. because wire-and logic is performed on the i2c_scl line, a high-to-low transition on the i2c_scl line affects all the devices connected on the bus. the devices start counting their low period and once a device?s clock has gone low, it holds the i2c_sc l line low until the clock high state is reached. however, the change of low to high in this device?s clock may not change the state of the i2c_scl line if another device clock is st ill within its low period. th erefore, synchronized cloc k i2c_scl is held low by the device with the longest low period. st a 7bit slave address 0 a register address data a/a r/w sp from master to slave from slave to master st = start sp = stop a = acknowledge (i2c_sda low) a = not acknowledge (i2c_sda high) st a 7bit slave address 1 a data data a r/w sp st a 1 a/a data r/w rept a 7-bit slave 0 a data data a/a r/w sp rept st = repeated start st address 7-bit slave address example 1: example 2: example 3: master transmits to slave master reads from slave
i 2 c interface mcf5213 reference manual, rev. 1.1 freescale semiconductor 22-7 preliminary devices with shorter low periods enter a high wait state during this time (see figure 22-8 ). when all devices concerned have counted off their low period, the synchronized clock (i2c_scl) line is released and pulled high. at this poi nt, the device clocks and the i2c_scl line are synchronize d, and the devices start counting their high periods. the first device to complete its high period pulls the i2c_scl line low again. the relative priority of the conte nding masters is determined by a data arbitration procedure. a bus master loses arbitration if it transmits logic 1 while another master tran smits logic 0. the losing masters immediately switch over to slave receive m ode and stop driving i2c_sda output (see figure 22-7 ). in this case the transition from master to slave mode does not generate a stop condition. meanwhile, hardware sets i2sr[ial] to indicate loss of arbitration. figure 22-7. arbitration procedure figure 22-8. clock synchronization 22.4.8 handshaking and clock stretching the clock synchronization mechanism can be used as a handsha ke in data transfers. slave devices can hold i2c_scl low after completing one byte transfer. in such a case, the cl ock mechanism halts the bus clock and forces the master clock into wait states until the slave releases i2c_scl. i2c_scl i2c_sda by master1 i2c_sda by master2 i2c_sda master 2 loses arbitration, and becomes slave-receiver internal counter reset i2c_scl1 i2c_scl2 i2c_scl wait start counting high period
i 2 c interface mcf5213 reference manual, rev. 1.1 22-8 freescale semiconductor preliminary slaves may also slow down the transf er bit rate. after the master has driven i2c_scl low, the slave can drive i2c_scl low for the required period and then re lease it. if the slave i2c_scl low period is longer than the master i2c_scl low period, the result ing i2c_scl bus signal low period is stretched. 22.5 memory map/register definition table 22-1 lists the configuration registers used in the i 2 c interface. 22.5.1 i 2 c address register (i2adr) the i2adr holds the address the i 2 c responds to when addressed as a slav e. note that it is not the address sent on the bus during the addr ess transfer when the module is performing a master transfer. table 22-1. i 2 c module memory map ipsbar offset register access reset value section/page 0x0300 i 2 c address register (i2adr) r/w 0x00 22.5.1/22-8 0x0304 i 2 c frequency divider register (i2fdr) r/w 0x00 22.5.2/22-9 0x0308 i 2 c control register (i2cr) r/w 0x00 22.5.3/22-10 0x030c i 2 c status register (i2sr) r/w 0x81 22.5.4/22-11 0x0310 i 2 c data i/o register (i2dr) r/w 0x00 22.5.5/22-12 address: 0x0300 (i2adr) access: user read/write 7 6543210 r adr 0 w reset: 0 0 0 0 0 0 0 0 figure 22-9. i 2 c address register (i2adr) table 22-2. i2adr field descriptions field description 7?1 adr slave address. contains the specific slave address to be used by the i 2 c module. slave mode is the default i 2 c mode for an address match on the bus. 0 reserved, should be cleared.
i 2 c interface mcf5213 reference manual, rev. 1.1 freescale semiconductor 22-9 preliminary 22.5.2 i 2 c frequency divider register (i2fdr) the i2fdr, shown in figure 22-10 , provides a programmable pres caler to configure the i 2 c clock for bit-rate selection. address: 0x0304 (i2fdr) access: user read/write 7 6543210 r 0 0 ic w reset: 0 0 0 0 0 0 0 0 figure 22-10. i 2 c frequency divider register (i2fdr) table 22-3. i2fdr field descriptions field description 7?6 reserved, should be cleared. 5?0 ic i 2 c clock rate. prescales the clock for bit -rate selection. the serial bit clock frequency is equal to the internal bus clock divided by the divider shown below. due to potentially slow i2c_scl and i2c_sda rise and fall times, bus signals are sampled at the prescaler frequency. ic divider ic divider ic divider ic divider 0x00 28 0x10 288 0x20 20 0x30 160 0x01 30 0x11 320 0x21 22 0x31 192 0x02 34 0x12 384 0x22 24 0x32 224 0x03 40 0x13 480 0x23 26 0x33 256 0x04 44 0x14 576 0x24 28 0x34 320 0x05 48 0x15 640 0x25 32 0x35 384 0x06 56 0x16 768 0x26 36 0x36 448 0x07 68 0x17 960 0x27 40 0x37 512 0x08 80 0x18 1152 0x28 48 0x38 640 0x09 88 0x19 1280 0x29 56 0x39 768 0x0a 104 0x1a 1536 0x2a 64 0x3a 896 0x0b 128 0x1b 1920 0x2b 72 0x3b 1024 0x0c 144 0x1c 2304 0x2c 80 0x3c 1280 0x0d 160 0x1d 2560 0x2d 96 0x3d 1536 0x0e 192 0x1e 3072 0x2e 112 0x3e 1792 0x0f 240 0x1f 3840 0x2f 128 0x3f 2048
i 2 c interface mcf5213 reference manual, rev. 1.1 22-10 freescale semiconductor preliminary 22.5.3 i 2 c control register (i2cr) the i2cr is used to enable the i 2 c module and the i 2 c interrupt. it also contains bits that govern operation as a slave or a master. address: 0x0308 (i2cr) access: user read/write 7 6543210 r ien iien msta mtx txak rsta 0 0 w reset: 0 0 0 0 0 0 0 0 figure 22-11. i 2 c control register (i2cr) table 22-4. i2cr field descriptions field description 7 ien i 2 c enable. controls the software reset of the entire i 2 c module. if the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and star ts operating when the next start condition is detected. master mode is not aware that the bus is busy; so initiating a start cycle may co rrupt the current bus cycle, ultimately causing either the current master or the i 2 c module to lose arbitration, after which bus operation returns to normal. 0the i 2 c module is disabled, but regi sters can still be accessed. 1the i 2 c module is enabled. this bit must be set before any other i2cr bits have any effect. 6 iien i 2 c interrupt enable. 0i 2 c module interrupts are disabled, but currently pending interrupt condition is not cleared. 1i 2 c module interrupts are enabled. an i 2 c interrupt occurs if i2sr[iif] is also set. 5 msta master/slave mode select bit. if the master loses arbitr ation, msta is cleared without generating a stop signal. 0 slave mode. changing msta from 1 to 0 generates a stop and selects slave mode. 1 master mode. changing msta from 0 to 1 signals a start on the bus and selects master mode. 4 mtx transmit/receive mode select bit. selects th e direction of master and slave transfers. 0 receive 1 transmit. when the device is addressed as a slave, softwa re should set mtx according to i2sr[srw]. in master mode, mtx should be set according to the type of transfer required. therefore, when the mcu addresses a slave device, mtx is always 1. 3 txak transmit acknowledge enable. specifies the value driven onto i2c_sda during acknowledge cycles for both master and slave receivers. note that writing txak applies only when the i 2 c bus is a receiver. 0 an acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. 1 no acknowledge signal response is sent (that is, acknowledge bit = 1). 2 rsta repeat start. always read as 0. attempting a repeat star t without bus mastership ca uses loss of arbitration. 0 no repeat start 1 generates a repeated start condition. 1?0 reserved, should be cleared.
i 2 c interface mcf5213 reference manual, rev. 1.1 freescale semiconductor 22-11 preliminary 22.5.4 i 2 c status register (i2sr) this i2sr contains bits that indi cate transaction direction and status. address: 0x030c (i2sr) access: user read/write 7 6543210 r icf iaas ibb ial 0 srw iif rxak w reset: 1 0 0 0 0 0 0 1 figure 22-12. i 2 c status register (i2sr) table 22-5. i2sr field descriptions field description 7 icf i 2 c data transferring bit. while one byte of data is transferred, icf is cleared. 0 transfer in progress 1 transfer complete. set by the falling edge of the ninth clock of a byte transfer. 6 iaas i 2 c addressed as a slave bit. the cpu is interrupted if i2cr [iien] is set. next, the cpu must check srw and set its tx/rx mode accordingly. writing to i2cr clears this bit. 0 not addressed. 1 addressed as a slave. set when its own address (iadr) matches the calling address. 5 ibb i 2 c bus busy bit. indicates the status of the bus. 0 bus is idle. if a stop signal is detected, ibb is cleared. 1 bus is busy. when start is detected, ibb is set. 4 ial i 2 c arbitration lost. set by hardware in the following circum stances. (ial must be cleared by software by writing zero to it.) i2c_sda sampled low when the master drives high during an address or data-transmit cycle. i2c_sda sampled low when the master drives hi gh during the acknowledge bit of a data-receive cycle. a start cycle is attempted when the bus is busy. a repeated start cycle is requested in slave mode. a stop condition is detected wh en the master did not request it. 3 reserved, should be cleared. 2 srw slave read/write. when iaas is set, srw indicates the va lue of the r/w command bit of the calling address sent from the master. srw is valid only when a complete transf er has occurred, no other transfers have been initiated, and the i 2 c module is a slave and has an address match. 0 slave receive, master writing to slave. 1 slave transmit, master reading from slave. 1 iif i 2 c interrupt. must be cleared by software by writing a zero in the interrupt routine. 0no i 2 c interrupt pending 1 an interrupt is pending, which causes a processor interrup t request (if iien = 1). set when one of the following occurs: complete one byte transfer (set at the falling edge of the ninth clock) reception of a calling address that matches it s own specific address in slave-receive mode arbitration lost 0 rxak received acknowledge. the val ue of i2c_sda during the acknowledge bit of a bus cycle. 0 an acknowledge signal was received after the completion of 8-bit data transmission on the bus 1 no acknowledge signal was detected at the ninth clock.
i 2 c interface mcf5213 reference manual, rev. 1.1 22-12 freescale semiconductor preliminary 22.5.5 i 2 c data i/o register (i2dr) in master-receive mode, reading the i2 dr allows a read to occur and for the next data byte to be received. in slave mode, the same function is available once the i 2 c has received its slave address. 22.6 i 2 c programming examples the following examples show programming for initia lization, signaling start, post-transfer software response, signaling stop, and generating a repeated start. 22.6.1 initialization sequence before the interface can transfer serial data , registers must be initialized, as follows: 1. set i2fdr[ic] to obtain i2c_scl fre quency from the system bus clock. see section 22.5.2, ?i 2 c frequency divider register (i2fdr).? 2. update the i2adr to de fine its slave address. 3. set i2cr[ien] to enable the i 2 c bus interface system. 4. modify the i2cr to select or deselect master/slave mode, tran smit/receive mode, and interrupt-enable or not. address: 0x0310 (i2dr) access: user read/write 7 6543210 r data w reset: 0 0 0 0 0 0 0 0 figure 22-13. i 2 c data i/o re gister (i2dr) table 22-6. i2dr field description field description 7?0 data i 2 c data. in master transmit mode, when dat a is written to this register, a data transfer is initiated. the most significant bit is sent first. in master receive mode, reading th is register initiates the recept ion of the next byte of data. in slave mode, the same functions are available after an address match has occurred. note: in master transmit mode, the first by te of data written to i2dr following assertion of i2cr[msta] is used for the address transfer and should comprise the calling address (in position d7?d1) concatenated with the required r/w bit (in position d0). this bit (d0) is not automatically appended by t he hardware, software must provide the appropriate r/w bit. note: i2cr[msta] generates a start when a master does not already own the bus. i2cr[rsta] generates a start (restart) without the master fi rst issuing a stop (i.e., the master already owns the bus). in order to start the read of data, a dummy read to this register starts the read pr ocess from the slave. the next read of the i2dr register contains the actual data.
i 2 c interface mcf5213 reference manual, rev. 1.1 freescale semiconductor 22-13 preliminary note if i2sr[ibb] is set when the i 2 c bus module is enabled, execute the following pseudocode sequence before proceeding with normal initialization code. this issues a stop command to the slave device, placing it in idle state as if it were just power-cycled on. i2cr = 0x0 i2cr = 0xa0 dummy read of i2dr i2sr = 0x0 i2cr = 0x0 22.6.2 generation of start after completion of the initialization procedure, seri al data can be transmitted by selecting the master transmitter mode. on a multiple-mast er bus system, i2sr[ibb] must be tested to determine whether the serial bus is free. if the bus is free (ibb = 0), the start signal a nd the first byte (the slave address) can be sent. the data written to the data register comprises the address of the de sired slave and the lsb indicates the transfer direction. the free time between a stop and the next start conditi on is built into the hard ware that generates the start cycle. depending on the relative frequencies of the sy stem clock and the i2c_scl period, it may be necessary to wait until the i2c is busy after writing the calling address to the i2dr before proceeding with the following instructions. the following example signals start and transm its the first byte of da ta (slave address): chflag move.b i2sr,-(a0) ;check i2sr[mbb] btst.b #5, (a0)+ bne.s chflag ;if i2sr[mbb] = 1, wait until it is clear txstart move.b i2cr,-(a0) ;set transmit mode bset.b #4,(a0) move.b (a0)+, i2cr move.b i2cr, -(a0) ;set master mode bset.b #5, (a0) ;generate start condition move.b (a0)+, i2cr move.b calling,-(a0) ;transmit the calling address, d0=r/w move.b (a0)+, i2dr ifree move.b i2sr,-(a0) ;check i2sr[mbb] ;if it is clear, wait until it is set. btst.b #5, (a0)+ beq.s ifree; 22.6.3 post-transfer software response sending or receiving a byte sets the i2sr[icf], wh ich indicates one byte co mmunication is finished. i2sr[iif] is also set. an interrupt is generated if the interrupt func tion is enabled during initialization by setting i2cr[iien]. software must first clear i2sr[i if] in the interrupt routine. i2sr[icf] is cleared either by reading from i2dr in receive mode or by writing to i2dr in transmit mode.
i 2 c interface mcf5213 reference manual, rev. 1.1 22-14 freescale semiconductor preliminary software can service the i2c i/o in the main program by monitoring the iif bit if the interrupt function is disabled. polling should monitor iif ra ther than icf because that operation is different when arbitration is lost. when an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the address is sent. if master receive mode is required, i2cr[mtx] should be toggled. during slave-mode address cycles (i2 sr[iaas] = 1), i2sr[srw] is read to determine the direction of the next transfer. mtx is programmed accordingly. for slave-mode data cycles (iaas = 0) , srw is invalid. mtx should be read to determine the current transfer direction. the following is an example of a software response by a master transm itter in the interrupt routine (see figure 22-14 ). i2sr lea.l i2sr,-(a7) ;load effective address bclr.b #1,(a7)+ ;clear the iif flag move.b i2cr,-(a7) ;push the address on stack, btst.b #5,(a7)+ ;check the msta flag beq.s slave ;branch if slave mode move.b i2cr,-(a7) ;push the address on stack btst.b #4,(a7)+ ;check the mode flag beq.s receive ;branch if in receive mode move.b i2sr,-(a7) ;push the address on stack, btst.b #0,(a7)+ ;check ack from receiver bne.b end ;if no ack, end of transmission transmit move.b databuf,-(a7) ;stack data byte move.b (a7)+, i2dr ;transmit next byte of data 22.6.4 generation of stop a data transfer ends when the mast er signals a stop, which can occur af ter all data is sent, as in the following example. mastx move.b i2sr, -(a7) ;if no ack, branch to end btst.b #0,(a7)+ bne.b end move.b txcnt,d0 ;get value from the transmitting counter beq.s end ;if no more data, branch to end move.b databuf,-(a7) ;transmit next byte of data move.b (a7)+,i2dr move.b txcnt,d0 ;decrease the txcnt subq.l #1,d0 move.b d0,txcnt bra.s emastx;exit end lea.l i2cr,-(a7) ;generate a stop condition bclr.b #5,(a7)+ emastx rte ;return from interrupt for a master receiver to terminate a data transf er, it must inform the sl ave transmitter by not acknowledging the last data byte. this is done by set ting i2cr[txak] before re ading the next-to-last byte. before the last byte is re ad, a stop signal must be generated, as in the following example. masr move.b rxcnt,d0 ;decrease rxcnt subq.l #1,d0 move.b d0,rxcnt beq.s enmasr ;last byte to be read
i 2 c interface mcf5213 reference manual, rev. 1.1 freescale semiconductor 22-15 preliminary move.b rxcnt,d1 ;check second-to-last byte to be read extb.l d1 subi.l #1,d1; bne.s nxmar ;not last one or second last lamar bset.b #3,i2cr ;disable ack bra nxmar enmasr bclr.b #5,i2cr ;last one, generate stop signal nxmar move.b i2dr,rxbuf ;read data and store rte 22.6.5 generation of repeated start after the data transfer, if the mast er still wants the bus, it can signa l another start followed by another slave address without signaling a st op, as in the following example. restart move.b i2cr,-(a7) ;repeat start (restart) bset.b #2, (a7) move.b (a7)+, i2cr move.b calling,-(a7) ;transmit the calling address, d0=r/w- move.b calling,-(a7) move.b (a7)+, i2dr 22.6.6 slave mode in the slave interrupt service routin e, software should poll the i2sr[iaas] bit to determine if the controller has received its slave address. if iaas is set, so ftware should set the transm it/receive mode select bit (i2cr[mtx]) according to the i2sr [srw]. writing to the i2cr clears th e iaas automatically. the only time iaas is read as set is from the interrupt at the end of the address cycle where an address match occurred; interrupts resulti ng from subsequent data transfers will have iaas cleared. a data transfer can now be initiated by writing information to i2dr for sl ave transmits, or read from i2dr in slave-receive mode. a dummy read of i2dr in sl ave/receive mode releases i2c_scl, allowing the master to send data. in the slave transmitter routine, i2 sr[rxak] must be tested before se nding the next byte of data. setting rxak means an end-of-data signal fr om the master receiver, after wh ich software must switch it from transmitter to receiver mode . reading i2dr then releases i2c_scl so that the master can generate a stop signal. 22.6.7 arbitration lost if several devices try to engage the bus at the sa me time, one becomes mast er. hardware immediately switches devices that lose arbitration to slave receive mode. data output to i2c_sda stops, but i2c_scl is still generated until the end of th e byte during which arbitrat ion is lost. an interrupt occurs at the falling edge of the ninth clock of this transf er with i2sr[ial] = 1 and i2cr[msta] = 0. if a device that is not a ma ster tries to transmit or execute a start, hardware will inhi bit the transmission, clear msta without signaling a stop, ge nerate an interrupt to the cpu, and set ial to indicate a failed attempt to engage the bus. when considering these case s, the slave service routine should first test ial and software should clear it if it is set.
i 2 c interface mcf5213 reference manual, rev. 1.1 22-16 freescale semiconductor preliminary figure 22-14. flow-chart of typical i 2 c interrupt routine clear master mode? tx/rx ? last byte transmitted ? rxak= 0 ? end of addr cycle (master rx) ? write next byte to i2dr switch to rx mode dummy read from i2dr generate stop signal read data from i2dr and store set txak =1 generate stop signal 2nd last byte to be last byte to be ? arbitration lost? clear ial iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to i2dr set rx mode dummy read from i2dr ack from receiver ? tx next byte read data from i2dr and store switch to rx mode dummy read from i2dr rte yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iif address cycle data cycle read read?
mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-1 preliminary chapter 23 analog-to-digital converter (adc) 23.1 introduction the analog-to-digital converter (adc ) consists of two separate and co mplete adcs, each with their own sample and hold circuits. the converters share a co mmon voltage reference a nd common digital control module. 23.2 features the adc?s characteristics include: ? 12-bit resolution ? maximum adc clock frequency of 5.33mhz, 187.5ns period ? sampling rate up to 1.78 million samples per second 1 ? single conversion time of 8.5 adc clock cycles (8.5 187.5ns = 1.595 s) ? additional conversion time of 6 adc clock cycles (6 187.5ns = 1.126 s) ? eight conversions in 26.5 adc clocks (26.5 187.5ns = 4.972 s) using simultaneous mode ? ability to simultaneously sample and hold two inputs ? ability to sequentially scan a nd store up to eight measurements ? internal multiplex to se lect two of eight inputs ? power savings modes allow automatic s hutdown/startup of all or part of adc ? those inputs not selected tolerate injected/sour ced current without aff ecting adc performance, supporting operation in noisy industrial environments. ? optional interrupts at the end of a scan, if an out-of-range limit is ex ceeded (high or low), or at zero crossing ? optional sample correction by subtra cting a pre-programmed offset value ? signed or unsigned result ? single ended or differenti al inputs for all input pins with support for an arbi trary mix of input types 23.3 block diagram the adc function, shown in figure 23-1 , consists of two four-channel i nput select functio ns, interfacing with two independent samp le and hold (s/h) circui ts, which feed two 12-bit adcs. the two converters store their results in a buffer, awaiting further processing. 1. once in loop mode, the time between each conversion is six adc clock cycles (1.125 s). using simultaneous conversion two samples are captured in 1.126 s, providing an overall sample rate of 1,776,667 samples per second.
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-2 freescale semiconductor preliminary figure 23-1. dual adc block diagram 23.4 functional description the adc?s conversion process is either initiated by a s ync signal from one of tw o input pins (syncx) or by writing 1 to a start n bit. starting a single conversion actually be gins a sequence of conve rsions, or a scan of up to eight single ended or differential samples one at a ti me in sequential scan mode. the ope ration of the module in sequential scan mode is shown in figure 23-2 . irq anb3 anb2 anb1 anb0 scaling & cyclic converter b 12 ana3 ana2 ana1 ana0 scaling & cyclic converter a 12 ? ? ? digital output storage registers 16 bus interface data syncx controller v refh voltage v refl sample/hold reference circuit mux mux
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-3 preliminary figure 23-2. sequential mode operation of the adc scan sequence is determined by de fining eight sample slots in clst1/ 2 registers, processed in order sample0-7 during sequential scan or in order sa mple0-3 by converter a and in order sample4-7 by converter b in parallel scan. sample slots may be disabled using the sdis register. the following pairs of analog inputs can be configured as a differen tial pair ana0-1, ana2-3, anb0-1, and anb2-3. when configured as a diff erential pair, a reference to either member of the differential pair by a sample slot results in a differential measurement using that differential pair. parallel scan can be simultaneous or non-simultaneous. duri ng simultaneous scan, the scans in the two converters are done simultaneously always resulting in simultane ous pairs of conversions, one by converter a and one by converter b. the two converte rs share the same start, stop, sync, end-of-scan interrupt enable control, and interrupt. scanning in both converters is terminated when either converter encounters a disabled sample. in n on-simultaneous scan, the parallel scans in the two converters are achieved independently. the two conv erters have their own start, stop, sync, end-of-scan interrupt enable controls, and end-of-scan interrupts. scanning in either converter term inates only when that converter encounters a disabled sample in its part of sd is register (ds0-ds3 for a, ds4-ds7 for b). ana3 ana2 ana1 ana0 v+ v refl channel select v? adca 12 single-ended vs crossbars allow ana0-3 to be stored in samples 4-7, or anb0-3 to be stored in samples 0-3 differential 12 + offst[0:3] 13 zero crossing logic + ? hilim[4:7] > rslt[0:3] zero crossing or error limit interrupt lolim[4:7] < 12 12 + offst[4:7] 13 zero crossing logic + ? rslt[4:7] 12 anb3 anb2 anb1 anb0 v+ v refl channel select v? adcb single-ended vs differential 12 hilim[0:3] > lolim[0:3] < te s t d a ta (from cpu) te s t d a ta (from cpu) adc2 adc1 adc0 end of scan b interrupt end of scan a interrupt irq logic
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-4 freescale semiconductor preliminary figure 23-3. parallel mode operation of the adc the adc can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform the scan sequence repeatedly until manuall y stopped. the single scan (once mode) differs from the triggered mode only in that sync input signals mu st be re-armed after each using a once mode scan and subsequent sync inputs are ignored until the sync input is re -armed. this arming can occur anytime after the sync pulse occurs, even while th e scan it initiated is still in process. optional interrupts can be generated at the end of a scan sequence. interrupts are available simply to indicate the scan ended, that a sa mple was out of range, or at seve ral different zero crossing conditions. out-of-range is determined by the hi gh and low limit registers. to understand the operation of the adc it is important to understand the features and limi tations of each of the functional parts. ana3 ana2 ana1 ana0 v+ v refl channel select v? adca 12 single-ended vs crossbars do not operate in differential 12 + offst[0:3] 13 zero crossing logic + ? hilim[4:7] > rslt[0:3] zero crossing or error limit interrupt lolim[4:7] < 12 12 + offst[4:7] 13 zero crossing logic + ? rslt[4:7] 12 anb3 anb2 anb1 anb0 v+ v refl channel select v? adcb single-ended vs differential 12 hilim[0:3] > lolim[0:3] < te s t d a ta (from cpu) te s t d a ta (from cpu) adc2 adc1 adc0 end of scan b interrupt end of scan a interrupt irq logic this mode
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-5 preliminary 23.4.1 input mux function the input mux function is shown in figure 23-4 . the channel select and single ended vs. differential switches are indirectly controlled based on settings within the list1, list2, sdis registers and the chncfg field of the ctrl1 register. 1. muxing for sequential mode, single-ended conversions?during ea ch conversion cycle (sample), any one input of the two muxes can be directed to any rslt n register. 2. muxing for sequential mode, di fferential conversions?during any conversion cy cle (sample), either member of a differential pair may be referenced as a sa mple, resulting in a differential measurement on that pair being stored in the corresponding rslt n register. 3. muxing for parallel mode, single-ended conve rsions?during any conve rsion cycle (sample), any of ana0-ana3 can be direct ed to an rslt0-3 result regi ster and any of anb0-anb3 can be directed to the rslt4-7. 4. muxing for parallel mode, differential conve rsions?during any conv ersion cycle (sample), either member of differential pair ana0/1 or either member of differential pair ana2/3 can be referenced as a sample, resulting in a differential measurement of that pair being stored in one of the rslt0-3 registers. likewise either member of differential pair anb0/1 or either member of differential pair anb2/3 can be referenced as a sample, resulting in a differential measurement of that pair being stored in one of the rslt4-7 registers. details of switch operation is shown in table 23-2 . internally, all measurements are performed differentially. during singl e ended measurements, v refl is used as the negative (-) input voltage while the selected analog input is used as the positive ( + ) input. table 23-2. analog mux controls for each conversion mode conversion mode chan nel select switches single ended differential switches sequential, single ended the two 1-of-4 select muxes can be set for the appropriate input line. the lower switch selects v refl for the v- input of the a/d. the upper switch is always closed so that any of the four inputs can get to the v+ a/d input. sequential, differential the ch annel select switches are turned on in pairs, providing a dual 1-of-2 select function, such that either of the two differential channels can be routed to the a/d input. the upper switch is open and the bottom switch selects the differential channel for the v- input of the a/d. parallel, single ended the two 1-of-4 select muxes can be set for the appropriate input line. the lower switch is selects v refl for the v- input of the a/d. the upper switch is always closed so that any of the four inputs can get to the v+ a/d input. parallel, differential the ch annel select switches are turned on in pairs, providing a dual 1-of-2 select function, such that either of the two differential channels can be routed to the a/d input. the upper and lower switches are open and the middle switch is closed, providing the differential channel to the differential input of the a/d.
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-6 freescale semiconductor preliminary figure 23-4. input select mux 23.4.2 adc sample conversion the adc consists of a cyclic, algor ithmic architecture using two recu rsive sub-ranging sections (rsd#1 and rsd#2), shown in figure 23-5 . each sub-ranging section resolves a single bit for each conversion clock, resulting in an overall convers ion rate of two bits per clock cy cle. each sub-ranging section is designed to run at a maximum clock speed of 5.33mhz . thus a complete 12-bit conversion takes six adc clocks (1.125ms), not including sa mple or post processing time. ana3 ana2 ana1 ana0 v refl v+ v? channel select to converter a single-ended interface function mux configuration for differential vs channel select single-ended vs differential anb3 anb2 anb1 anb0 v refl v+ v? channel select to converter b single-ended interface function ana3 ana2 ana1 ana0 v refl v+ v? channel select to converter a differential interface function anb3 anb2 anb1 anb0 v refl v+ v? channel select to converter b differential interface function channel select single-ended vs differential channel select single-ended vs differential channel select single-ended vs differential mux configuration for single-ended
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-7 preliminary figure 23-5. cyclic adc ? top level block diagram the adc has two input modes. the input mode for a given sample is determined by the chncfg field of the ctrl1 register. the two input modes are: 1. single-ended mode (chncfg bi t=0)?in single-ended mode, input mux of the adc selects one of the analog inputs and directs it to the plus te rminal of the a/d core. the minus terminal of the a/d core is connected to the v refl reference during this mode. th e adc measures the voltage of the selected analog input and compares it against the (v refh - v refl ) reference voltage range. 2. differential mode (chncfg bit = 1)?in diff erential mode, the adc measures the voltage difference between two analog inputs and compares that against the (v refh - v refl ) voltage range. the input is selected as an input pair: ana0/1, ana2/3, anb0 /1 or anb2/3. in this mode, the plus terminal of the a/d core is connected to the even analog input while the minus terminal is connected to the odd analog input. a mix and match combination of single-ended and diff erential configurations may exist. for example: ? ana0 and ana1 differential , ana2 and ana3 single-ended ? anb0 and anb1 differential, an d anb2 and anb3 single-ended 23.4.2.1 single- ended samples the adc module performs a ratio metric conversion. for single ended measurements, the digital result is proportional to the ratio of the analog input to the reference voltage in the following formula: interface function rsd#1 1 rsd#2 2 cyclic adc core adcb mux ana3 ana2 ana1 ana0 v+ v refl channel select v? single-ended vs differential interface function rsd#1 1 rsd#2 2 v+ v? cyclic adc core adca anb3 anb2 anb1 anb0 v+ v refl channel select v? single-ended vs differential v+ v? mux
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-8 freescale semiconductor preliminary 23.4.2.2 differential samples for differential measurements, the digital result is pr oportional to the ratio of the difference in the inputs to the difference in the reference voltages (v refh and v refl ). figure 23-6 shows typical configurations for differential inputs. when converting differenti al measurements, the following formula is useful: singleendedvalue round v in v reflo ? v refh v reflo ? -------------------------------------------- - 4095 () 8 = vin = applied voltage at the input pin vrefh and vrefl = voltage at the external referenc e pins on the device (t ypically vrefh = vssa and vrefl = vdda) note: the 12-bit result is rounded to the nearest lsb. note: the adc is a 12-bit function with 4096 possibl e states. however, the 12 bits have been left shifted three bits on the 16-bit data bus so its ma gnitude, as read from the data bus, is now 32760. differentialvalue round v in 1v in 2 ? v refh v reflo ? ------------------------------------------ - 4095 () 8 = v in = applied voltage at the input pin v refh and v refl = voltage at the external reference pins on the device (typically v refh = v ssa and v refl = v dda ) note: the 12-bit result is rounded to the nearest lsb. note: the adc is a 12-bit function with 4096 possibl e states. however, the 12 bits have been left shifted three bits on the 16-bit data bus so its ma gnitude, as read from the data bus, is now 32760.
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-9 preliminary figure 23-6. typical connections for differential measurements 23.4.3 adc data processing as shown in figure 23-7 , the raw result of the adc conversion pr ocess is sent to an adder for offset correction. the adder subtracts the offst n register value from each sample and the result is then stored in the corresponding result register (rslt n ). concurrent to this the raw adc value is checked for limit violations and the rslt n values are checked for zero-crossing. a ppropriate interrupts are asserted, if enabled. the sign of the result is calculated from the adc unsi gned result minus the respec tive offset register. if the offset register is programmed with a value of zero, the result regist er value is unsigned and equals the cyclic converter unsigned result. the range of the result (rslt) register is $0000?$7ff8, assuming the offset (offst) register is set to zero. the processor can write to the resu lt registers whenever the adc is in stop mode or powered down. the data from this write operation is tr eated as if it came from the adc an alog core; so the limit checking, zero crossing, and the offset registers? f unction as if in normal mode. for ex ample, if the ad c is stopped and the processor writes to rslt5 register, the data writte n to the rslt5 register is muxed to the adc digital logic inputs, processed, and stored into rslt5 as if the analog core had provided the data. this test data must be left justified by three bits (as shown in the rslt register definition) and does not include the sign bit. the sign bit (sext) is calculated dur ing subtraction of the corresponding offst n offset value. + ? an+ an? differential buffer will center about mid-point an+ an? v ref /2 center tap held at (v refh + v refl ) /2 note: normally, v refl is v refh potential set to v ssa = 0v
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-10 freescale semiconductor preliminary figure 23-7. result register data manipulation 23.4.4 sequential vs. parallel sampling all scan modes make use of the ei ght sample slots in the clst1 and clst2 registers. these slots are used to define which single-ended i nput or differential input pair is measured at each step in a scan sequence. the sdis register is used to disable unneeded slots. differential measurements are made on input pairs ana0/1, ana2/ 3, anb0/1, and anb2/3 using the chncfg field of the ctrl1 register. a single ended measurement will be made if a sample slot refers to an input not configured as a member of a differen tial pair by chncfg. a diff erential measurement will be made if a sample slot refers to either member of a differential pair. refer to the chncfg field description in the ctrl1 register for details of differential and single ended measurement. scan modes are either seque ntial or parallel, as defined by the smod e field of the ctrl1 register. in sequential scans, up to eight sample slots are sample d one at a time in the order sample 0-7. each sample slot may refer to any of the eight analog i nputs (ana0-3 and anb0-3), thus the same input may v+ v? adca 12 12 + offst[0:3] 13 zero crossing logic + ? hilim[4:7] > rslt[0:3] zero crossing or error limit interrupt lolim[4:7] < 12 12 + offst[4:7] 13 zero crossing logic + ? rslt[4:7] 12 v+ v? adcb 12 hilim[0:3] > lolim[0:3] < te s t d a ta (from cpu) te s t d a ta (from cpu) adc2 adc1 adc0 end of scan b interrupt end of scan a interrupt irq logic
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-11 preliminary be referenced by more than one sa mple slot. scanning is initiated when the start0 bit is written as 1 or, if the sync0 bit is 1, when the sync0 input goes high. a scan ends when the first disabled sample slot is encountered in the sdis regi ster. completion of the scan triggers the eosi0 interrupt if the interrupt is enabled by the eosie0 bit. the start0 bit and s ync0 input are ignored while a scan is in process. scanning stops and cannot be initiated when the stop0 bit is set. parallel scans differ in that convert er a collects up to four samples (sample 0-3) in parallel to converter b collecting up to four samples (sample 4-7). sa mples 0-3 may only refere nce inputs ana0-3 and samples 4-7 may only reference inputs anb0-3. within these constraints, an y sample may reference any pin and the same input may be refe renced by more than one sample slot. by default (when simult=1), paralle l scans of the converters are initiat ed together when the start0 bit is written as 1 or, if the sync0 bit is 1, when th e sync0 input goes high. the scan in both converters terminates when either converter en counters a disabled sample slot in sdis. completion of a scan triggers the eosi0 interrupt provided the eosie0 interrupt enable is set. samples are always taken simultaneously in both the a and b converters. setting the stop0 bit st ops and prevents the initia tion of scanning in both converters. setting simult=0 (non-simultaneous mode) causes parallel scanning to operate independently in the a and b converter. each converter has its own set of start n , stop n , sync n , and eosie n control bits, sync n input, eosi n interrupt, and cip n status indicators ( n = 0 for converter a, n = 1 for converter b). though still operating in parallel, the scans in th e a and b converter star t and stop independently according to their own controls and may be si multaneous, phase shifted, or asynchronous depending on when scans are initiated on the respective converters. the a and b converter may be of different length (still up to a maximum of four) and each converter ?s scan completes when a disabled sample is encountered in that converters sa mple list only. stop0 only stops th e a converter and stop1 only stops the b converter. looping scan modes repeat independe ntly, with the a convert er capturing sample 0-3 and b converter capturing sample 4- 7. in loop modes, each converter independently restarts its scan after capturing its samples. 23.4.5 scan sequencing scan modes break down into three types based on how they repeat. these types are once, triggered, or loop. be certain to read section 23.4.4, ?sequential vs. parallel sampling ? to understand the operation of sequential and parallel scan m odes before proceeding further. during a once mode scan a single seque ntial or parallel scan is execut ed. once scan modes differ from triggered scan modes in that they mu st be re-armed after each use. wh ile all scan modes ignore sync pulses occurring while a scan is in proces s, once scan modes will continue to ignore sync pulses even after the scan completes until re-armed. re-arming, however , can occur any time including during the scan by writing to a ctrl n register. if operating in a se quential mode or simultaneous parallel write to the ctrl1 register. if operating in a non-simu ltaneous parallel mode, re-arm c onverter a by writing to the ctrl1 register and converter b by wr iting to the ctrl2 register. triggered scan modes are identical to the correspon ding once scan modes except that re-arming of sync inputs is not necessary.
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-12 freescale semiconductor preliminary loop scan modes automatically restart a scan as s oon as the previous scan completes. in the loop sequential mode up to eight samples ar e captured in each loop and the next scan st arts immediately after the completion of the previous scan. in loop parallel scan modes, both convert ers restart together if simult=1 and restart independently if simult=0. all subsequent start and sync pulses will be ignored after the scan begins. scanning can only be term inated by setting a stop n bit. use stop0 in the ctrl1 register if operating in a sequential or simultane ous parallel mode. if ope rating in a non-simultaneous parallel mode use stop0 to stop converter a and stop1 in the ctrl2 register to stop converter b. 23.4.6 power management the five supported power modes are de scribed below. they ar e presented in order fr om highest to lowest power utilization at the expense of increased conversion latency and/or st artup delay. please see the clocks section ( figure 23.4.7 ) for details of the various clocks referenced below. 23.4.6.1 power management modes 1. normal power mode this mode operates when: ? at least one adc converter is powered up (pd0 or pd1=0 in the pwr register); ? both auto power-down and auto standby modes are disabled (apd=0, asb=0 in adcpower); ? the adc?s clock is enabled (adc=1 in the sim module?s sim_pce register). in this mode the adc uses the conversion clock as the adc clock source both when active or idle. to minimize conversion latency it is recommended the conversion clock be configured to 5.33mhz. no startup delay (defined by pudelay in the pwr register) is imposed. 2. auto power-down mode this mode operates when: ? at least one adc converter is powered up (pd0 or pd1=0 in the pwr register); ? auto power-down mode enabled (apd=1 in the pwr register); ? the adc?s clock is enabled (adc=1 in the sim module?s sim_pce register). auto power-down and standby modes can be used toge ther by setting apd=1 in the above configuration. this hybrid mode converts at an adc clock rate of 100khz using standby current mode when active and gates off the adc clock and powers down the convert ers when idle. a startup delay of pudelay adc clock cycles execute at the start of all scans while the adc engage s the conversion clock and the adc powers up, stabilizing in the standby current mode. this provides the lo west possible power configuration for adc operation. 3. auto standby mode this mode operates when: ? at least one adc converter is powered up (pd0 or pd1=0 in the pwr register); ? auto power-down is disabled (apd=0 in the pwr register); ? auto standby is enabled (asb=1 in the pwr register); ? the adc?s clock is enabled (adc=1 in the sim module?s sim_pce register);
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-13 preliminary ? either the relaxation oscillator must be enable d for 8mhz operation or the external oscillator clock must be running at 8mhz in this mode. in auto standby mode, the adc uses the convers ion clock when active and the100khz standby clock when idle. the standby (low current) state automatically engages when the adc is idle. it is recommended that the conversion clock be configured at or near 5.33mhz to minimize conversi on latency. the adc will execute a startup delay of pudelay adc clocks at the start of all scans, allowi ng the adc to switch to the conversion clock and to revert fr om standby to normal current mode. it is recommended the conversion cl ock be configured at or near 5.33m hz to minimize conversion latency when active. in this mode, the adc uses the conve rsion clock when active and gates off the conversion clock and powers down the converters when idle. a startup delay of p udelay adc clocks is executed at the start of all scans, allowing the adc to st abilize when switching to normal current mode from a completely powered off condition. th is mode uses less power than no rmal and more power than auto standby. it requires more startup latency (than auto st andby) when leaving the idle state to start a scan (higher pudelay value). 4. power-down mode this mode operates when: ? both adc converters are powered down (pd0=pd1=1 in the pwr register); ? the adc?s clock is disabled (adc=0 in the sim module?s sim_pce register). in this configuration, the clock trees to the adc and all of its analog components are shut down and the adc uses no power. 23.4.6.2 power management details the adc voltage reference and converters are power ed down (pdn=1 in the pwr register) on reset. individual converters can be manuall y powered down when not in use (p d0=1 or pd1=1) and the voltage reference can be automatically power ed down when no converter is in use (pd2=1), or manually powered up when no converters are powered (pd2=0). when the adc voltage reference is pow ered down, output reference voltages are set to low (v ssa ). a delay of pudelay adc clock cycles is imposed whenever pd0 or pd1 are cleared to power-up a converter and whenever the ad c goes from an idle (neith er converter has a scan in process) to an active state when not operating in normal power mode. the adc is active when at least one converter has a scan in process. a device recommends the use of two pu delay values, a large valu e for full power-up and a smaller value for going from standby current levels to full power-up. th e following paragraphs provide an explanation of how to use pudelay when starting the adc up or changing modes. when starting up in normal mode, first set pudelay to the large power-up value. next, clear the pd0 and or pd1 bits to power-up the required converters. poll the status bits (psts n in the pwr register) until all required converters are powered up. following polling, start scan operations. the value in pudelay will provide a power-up delay before scans begin. since normal mode does not use pudela y at start of scans, no further delays will be imposed. when starting up using auto standby mode, first use th e normal mode startup pr ocedure. before starting scan operations, set pudelay to the smaller value, and then set asb in the pwr register. auto standby
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-14 freescale semiconductor preliminary mode will automatically reduce cu rrent levels until active and then impose a pudelay wait to allow current levels to rise from standby to normal levels. when starting up using auto power-down mode, first use the normal mode startup procedure. before starting scan operations, set pudelay to the large pow er-up value. next, set apd in the pwr register. finally, clear the pd0 and or pd1 bits for the requi red converters. converters remain powered off until scanning goes active at which time the large p udelay executes as the adc goes from powered down to fully powered at the start of the scan. in auto power-down mode, when th e adc goes from idle to active, a converter is only powered up if it is required for the scan, as determined by the clst1, clst2, and sdis registers. it is recommended to power-off both converters (pd0=pd1=1 in the pwr register) when re-configuring clocking or power controls to av oid generating bad samples, ensuring proper delays are applied when powering up or starting scans. attempts to start a scan during the pudelay time -out will be ignored unt il the appropriate psts n bits are cleared in the pwr register. any attempt to use a converter when powered down, or with the voltage reference disabled, results in invalid results. it is po ssible to read adc result registers af ter converter power down to see results calculated before power-down. however, a new scan sequence must be starte d with a sync n pulse or a write to the start n bit before new results will be available. 23.4.6.3 adc stop mode of operation any conversion sequence in progress can be stopped by setting the relevant stop n bit. any further sync pulses, or writes to the start n bit, are ignor ed until the stop n bit is cleared. once in this stop mode, the results registers can be modified by writes from the processor. any write to rslt n registers in the adc stop mode is treated as if the analog core supplied the data, so limit checking, ze ro crossing, and associated interrupts can occur if enabled. 23.4.7 adc clock 23.4.7.1 general the adc has two external clock inputs used to drive two clock domains within the adc module. table 23-3. adc clock summary clock input source characteristics peripheral clock (=system clock) 1/2 core clock maximum rate is pll output divi ded by 2 if pll enabled. when pll disabled, max rate is oscillator clock divided by 2. adc 8mhz clock relaxation oscillator (8mhz), crystal oscillator (1-16mhz), or external oscillator provides 8mhz for auto standby power saving mode.
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-15 preliminary 23.4.7.2 description of clock operation as shown in figure 23-8 , the conversion clock is th e primary source for the adc clock and is always selected as the adc clock when conversions are in process. the div value in the ctrl2 register should be configured so the conversion clock freque ncy falls between 100khz and 5.33mhz. operating the adc at out-of-spec clock frequencies will degr ade conversion accuracy. similarly, modifying the parameters affect clock ra tes or power modes while the regulators are powered up (pd0=0 or pd1=0) will also degrade conversion accuracy. the conversion clock adc uses for sampling is calcu lated using the ipbus clock and the clock divisor bits within the ctrl2 register. please see section 23.5.1, ?control 1 register (ctrl1) ? or section 23.5.2, ?control 2 register (ctr l2) under sequential scan modes ? . the adc clock is active 100 percent of the time while in loop modes, or if pow er management is set to normal. it is also active during all adc power-up for a period of time dete rmined by the pudelay field in the power (pwr) register. after the power-up delay times out, the adc clock continues until the completion of the adc n scan when operating in auto standby or auto power-down modes. figure 23-8. adc clock generation the oscillator clock feeds a 80:1 divider, generatin g the auto standby clock. the auto standby clock is selected as the adc clock during the auto standby po wer mode when both converters are idle. the auto standby power mode requires an 8mhz oscillator clock from the relaxation oscillator, crysta l oscillator or external oscillator. 23.4.7.3 adc clock resynchronization at start of scan at the fastest adc speed, each adc cl ock period is 6 system clock periods long. when asserting the start of a scan, either by writing to a start n bit or by a sync n signal, the adc clock is re-synchronized to align it to the system clock. this allows the commanded scan to begi n as soon as possible rather than wait up to five additional system cloc ks for the start of the next ad c clock period. this is shown in figure 23-9 for both sequential and simultaneous parallel modes of op eration. in these mode s both adc operate off of the same start signal. 0 0 1 ctrl2:div (+2 x [div+1]) peripheral (system) clock 1/2 core frequency 0 1 auto power-down adc idle disabled (apd=0) auto standby enabled (asb=1) standby current mode status adc bit in sim_pce (+80) oscillator clock (8mhz) adc clock auto standby clock (100khz) adc conversion clock div
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-16 freescale semiconductor preliminary in a parallel scan mode when simult=0 both adcs operate using independent start n bits and sync n signals. as shown in figure 23-10 , the first scan started will be re -synchronized to the system clock but the second scan may wait up to five additional system cloc ks before starting. als o, please note that which converter is synchronized to the system clock depends on which convert first starts to use the adc. the case shown has adca synchronized, but one could easily imagine the case where the adca start comes after instead of before the adcb start. in this cas e adcas start would be dela yed up to five additional system clock periods instead of adcbs. if there is a known timing relations hip between adca and adcb when operating in a non-simultaneous parallel mode then the applicati on can control which adc starts firs t and gets the re-synchronized clock. the application can also control the delay to starting the second adc scan so that its start signal aligns with the adc clock and the start of the second adc is not delayed. figure 23-9. adc clock resynchronization for sequential and simultaneous parallel modes start0 asserted adc conversion clock resynchronized adc scans start system clock old adc clock adc clock after resynchronization adca scan adcb scan
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-17 preliminary figure 23-10. adc clock resynchronization for non-simultaneous parallel modes 23.4.8 voltage reference pins v refh & v refl the voltage difference between v refh and v refl provides the reference voltage that all analog inputs are measured against. the reference voltage should be pr ovided from a low noise filt ered source capable of providing up to 1ma of reference current. start0 asserted system clock old adc clock adc clock after resynchronization adca scan adcb scan adcb scan start adcb scan should start here start1 asserted adc conversion clock resynchronized adca scan start delay in start because adc clock cannot be resynchronized: 5 system clocks wait for next rising edge of adc conversion clock
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-18 freescale semiconductor preliminary figure 23-11. adc voltage reference circuit when tying v refh to the same potential as v dda relative measurements are being made with respect to the amplitude of v dda . it is imperative special precautions be taken assuring the voltage applied to v refh be as noise free as possible. any noise residing on the v refh voltage is directly tr ansferred to the digital result. figure 23-11 illustrates the internal workings of the adc voltage reference circuit.v refh must be noise filtered; a minimum configurat ion is shown in the figure. 23.4.9 supply pins v dda and v ssa dedicated power supply pins are provided for the purposes of reducing noise coupling and to improve accuracy. the power provide d to these pins is sugge sted to come from a low noise filtered source. uncoupling capacitors ought to be connected between v dda and v ssa . 23.5 register definitions a register address is the su m of a base address and an address offs et. the base address is defined at the device level and the address offset is defined at the module level. table 23-4. adc memory map device peripheral base address mcf5213 adc $00f080 v refh (ana2) external reference voltage 0.1f v refl (anb2) 1.0mh v rl sel_vrefl v refh to adc v refl to adc sel_vrefh v rh
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-19 preliminary table 23-5 lists the adc registers in as cending address order, including th eir acronyms and address offset of each register. adc uses adc n _base plus the given offset de pending on the adc being used. the adc peripheral has 43 registers. bits of each of the 43 registers are summarized in figure 23-12 . details of each follow. table 23-5. adc register summary ipsbar offset acronym register name access type location 0x0019_0000 ctrl1 control register 1 read/write section 23.5.1 0x0019_0001 ctrl2 control register 2 read/write section 23.5.2 section 23.5.3 0x0019_0002 zxctrl zero crossing control register read/write section 23.5.4 0x0019_0003 clst1 channel list register 1 read/write section 23.5.5 0x0019_0004 clst2 channel list register 2 read/write 0x0019_0005 csdis sample disable register read/write section 23.5.6 0x0019_0006 cstat status register read/write section 23.5.7 0x0019_0007 limstat limit status register read/write section 23.5.8 0x0019_0008 zxstat zero crossing status register read/write section 23.5.9 0x0019_0009?10 rslt0-7 result registers 0-7 read/write section 23.5.10 0x0019_00011?18 lolimt0-7 low limit registers 0-7 read/write section 23.5.11 0x0019_00019?20 hilimt0-7 high limit registers 0-7 read/write 0x0019_00021?28 offst0-7 offset registers 0-7 read/write section 23.5.12 0x0019_00029 pwr power control register read/write section 23.5.13 0x0019_0002a vref voltage reference register read/write section 23.5.14
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-20 freescale semiconductor preliminary add. offset register acronym 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 ctrl 1 r 0 stop0 0 sync 0 eosie 0 zcie llmti e hlmti e chncfg 0 smode w start 0 $1 ctrl 2 simultaneous mode r 0 0 0 0 0 0 0 0 0 0 0 div w ctrl 2 parallel mode r 0 stop1 0 sync 1 eosie 1 0 0 0 0 0 simult div w start 1 $2 zxctrl r zce7 zce6 zce5 zce4 zce3 zce2 zce1 zce0 w $3 c lst1 r 0 sample3 0 sample2 0 sample1 0 sample0 w $4 c lst2 r 0 sample7 0 sample6 0 sample5 0 sample4 w $5 sdis r 0 0 0 0 0 0 0 0 ds7 ds6 ds5 ds4 ds3 ds2 ds1 ds0 w figure 23-12. adc register map summary
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-21 preliminary 23.5.1 control 1 register (ctrl1) bits 14, 13, 12, and 11 in ctrl1 cont rol all types of scans except parallel scans in the b converter when simult=0 in the ctrl2 register. simult=0 bits 14, 13, 12, and 11 in ctrl are used to control converter b scans in parallel scan modes while the equivalent bits in cr1 are used for converter a. figure 23-13. control 1 (ctrl1) register $6 stat rcip0cip1 0 eosi 1 eosi 0 zci llmti hlmt rdy7 rdy6 rdy5 rdy4 rdy3 rdy2 rdy1 rdy0 w $7 limstat r hls7 hls6 hls5 hls4 hls3 hls2 hls1 hls0 lls7 lls6 lls5 lls4 lls3 lls2 lls1 lls0 w $8 zxstat r 0 0 0 0 0 0 0 0 zcs7 zcs6 zcs5 zcs4 zcs3 zcs2 zcs1 zcs0 w $9-$10 rslt n r sext rslt 0 0 0 w test_data $11-$1 8 lolim n r 0 llmt 0 0 0 w $19-$2 0 hilim n r 0 hlmt 0 0 0 w $21-$2 8 offst n r 0 offset 0 0 0 w $29 pwr r asb 0 0 psts 2 psts 1 psts 0 pudelay apd pd2 pd1 pd0 w $2a vref r sel_v refh sel_v refl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 0 read as 0 w reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field ? stop0 start0 sync0 eosie0 zcie llmtie hlmtie chncfg ? smode reset0 1 0 1 0 0 0 0 0000 0101 r/w ? r/w w r/w ? r/w address ipsbar + 0x19_0000 figure 23-12. adc register map summary (continued)
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-22 freescale semiconductor preliminary 23.5.1.1 reserved?bit 15 this bit is reserved or not implemented. it is read as 0 and cannot be modified by writing. 23.5.1.2 stop 0 (stop0)?bit 14 when stop0 is asserted, the current scan is stoppe d and no further scans can start. any further sync0 input pulses (see sync0 bit 12) or writes to the st art0 bit are ignored until the stop0 bit is cleared. after the adc is in stop mode, the result registers can be modified by the processor. any changes to the result registers in stop m ode are treated as if the analog core s upplied the data. therefore, limit checking, zero crossing, and associated interrupts can occur if enabled. this is not the same as the device?s stop mode. ? 0 = normal operation ? 1 = stop mode 23.5.1.3 start conversion (start0)?bit 13 a scan is started by writing 1 to the start0 bit. this is a write-only bit. writing 1 to the start0 bit again will be ignored until the end of the current scan. ? 0 = no action ? 1 = start command is issued the adc must be in a stable power configuration prior to wr iting the start bit. refer to the functional description of power m odes for further details. 23.5.1.4 synchronization 0 enable (sync0)?bit 12 a conversion may be initiated by a sserting a positive edge on the sy nc0 input. any subsequent sync0 input pulses while the scan re mains in process are ignored. ? 0 = scan is initiated by a write to start0 bit only ? 1 = use a sync0 input pulse or start0 bit to initiate a scan the adc must be in a stable power mode prior to sync0 input assertion. refer to the functional description of power m odes for further details. in once scan modes, only the first sync0 input pulse is honored. subsequent sync0 input pulses are ignored until sync0 input is re-armed by writing to the ctrl1 regi ster, usually by simp ly rewriting 1 to sync0. this is achieved at any time, even during the execution of the scan. 23.5.1.5 end of scan interrupt enable 0 (eosie0)?bit 11 this bit enables an eosi0 interrupt to be generated upon co mpletion of the scan. fo r looping scan modes, the interrupt will trigger after the comp letion of each iteration of the loop. ? 0 = interrupt disabled ? 1 = interrupt enabled
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-23 preliminary 23.5.1.6 zero crossing interrupt enable (zcie)?bit 10 this bit enables the zero crossing in terrupt if the current result value has a sign change from the previous result as configured by the zxctrl register. ? 0 = interrupt disabled ? 1 = interrupt enabled 23.5.1.7 low limit interrupt enable (llmtie)?bit 9 this bit enables the low limit exceeded interrupt when the current result value is less than the low limit register value. the raw result value is compared to the lolim register, bits llmt[11:0], be fore the offset register value is subtracted. ? 0 = interrupt disabled ? 1 = interrupt enabled 23.5.1.8 high limit interrupt enable (hlmtie)?bit 8 this bit enables the high limit exceeded interrupt if the curren t result value is grea ter than the high limit register value. the raw result value is compared to the high limit (hilim) re gister, bits hlmt[11:0], before the offset register value is subtracted. ? 0 = interrupt disabled ? 1 = interrupt enabled 23.5.1.9 channel configure (chncfg)?bits 7 ? 4 the inputs can be configured for either single-ended or differ ential conversions. differential measurements retu rn the max value 32760 (= 4095 8) when the plus ( + ) input is v refh and the minus ( ?) input is v refl , return 0 when the plus ( + ) input is at v refl and the minus ( ?) input is at v refl , and scale linearly between based on the voltage di fference between the two signals. single ended table 23-6. chncfg bit settings bit settings inputs description xxx1 ana0 ? ana1 configured as differential pair (ana0 is + and ana1 is ? ) xxx0 both configured as single ended inputs xx1x ana2 ? ana3 configured as differential pair (ana2 is + and ana3 is ? ) xx0x both configured as single ended inputs x1xx anb0 ? anb1 configured as differential pair (anb0 is + and anb1 is ? ) x0xx both configured as single ended inputs 1xxx anb2 ? anb3 configured as differential pair (anb2 is + and anb3 is ? ) 0xxx both configured as single ended inputs
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-24 freescale semiconductor preliminary measurements return the max va lue 32760 when the input is at v refh , return 0 when the input is at v refl , and scale linearly between based on the amount by which the input exceeds v refl . 23.5.1.10 scan mode cont rol (smode)?bits 2-0 smode controls the scan mode of the adc module. all scan modes make use of the eight sample slots defined by the clst1 and clst2 registers. a scan is the process of stepping through these sample slots, converting the analog input i ndicated by that slot, and storing the re sult. un-required slots may be disabled by writing 1 to the appropriate bits of the sdis register. input pairs ana0-1, ana2-3, anb0-1, and anb0-1 may be configured as differential pairs using the chncfg field. when a slot in clst n refers to either member of a differ ential pair a differential measurement on that pair wi ll be made, otherwis e a single ended measurement wi ll be taken on that input. the details of differential and si ngle ended measurement are described in the description of the chncfg field. smode determines whether the slots are used to pe rform a sequential scan up to eight samples or two parallel scans up to four samples. smode controls how these scans are initiated and terminated. it also controls whether the scans are performed once or repetitively. for more details, please see section figure 23-3., ?parallel mode operation of the adc ? . parallel scans may be simultane ous (simult=1) or non- simultaneous. during simu ltaneous parallel scans a and b converters scan synchr onously using one set of shared c ontrols (ctrl1 register). during non-simultaneous (simult=0) scans the a and b converters operate as ynchronously with each converter using its own independent set of controls (ctrl1 for a and ctrl2 for b). refer to the simult bit description for further details. note the simult bit only applies to para llel operating modes and is ignored during sequential operating modes. ? 000 = once sequential upon start, or an enabled sync signal, samples are taken one at a time starting with sample0 until a first disabled samp le is encountered. if no disabled samp le is encountered in sdis register, conversion concludes after sample7. if the scan is initiated by a sync signal only one scan will be completed until the converter is re armed by writing to the ctrl1 register. ? 001 = once parallel upon start, or an armed and enabled sync signa l, converter a will capture samples 0-3 and converter b will capture sample s 4-7. by default (simult=1), sa mples are taken simultaneously (synchronously) and scanning stops when either c onverter encounters a disabled sample or both converters complete all four samples. when simult=0, samples are taken asynchronously and scanning stops when each converter encounters a disa bled sample in its part of the sdis register or completes all four samples. if the scan is initiated by a sync signal only one scan will be completed till the converter is rearmed by writing to the ctrl1 register. (when simult=0 the b converter must be re-armed separate ly by writing to the ctrl2 register.) ? 010 = loop sequential upon an initial start or enabled sync pulse, up to eight samples are taken one at a time until a
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-25 preliminary disabled sample is encountered. the process repeats until the stop0 bit is se t. while a loop mode is running, any additional star t commands or sync pulses are ignored. if auto standby (power:asb=1) or auto power-down (power:apd =1) is the selected power mode control, the power-up delay defined by pudelay will be applied only on the first conversion. ? 011= loop parallel upon an initial start or enabled sync pulse, converter a will captu re samples0-3 and converter b will capture samples4-7. each time a converter co mpletes its current scan, it immediately restarts its scan sequence. this continues until a stop n bit is asserted. whil e a loop is running, any additional start commands or sync pulses are i gnored. by default (simul t=1), samples are taken simultaneously (synchronously) and scanning stops when either co nverter encounters a disabled sample or both converters complete all four samples. when simult=0, samples are taken asynchronously and scanning stops wh en each converter encounters a disabled sample in its part of the sdis register or completes all four samp les. if auto standby or auto power-down is the selected power mode control, the power-up dela y defined by pudelay will be applied only on the first conversion. ? 100 = triggered sequential upon start, or an enabled sync signal, samples are taken one at a time starti ng with sample0, until a first disabled sample is encountered. if no disabled sample is encountered, conversion concludes after sample7. if external sync is enable d new scans will be star ted for each sync pulse that is non-overlapping with a current scan in progress. ? 101 = triggered parallel (default) upon start, or an enabled sync signal, convert er a will convert sample s0-3 and converter b will convert samples4-7 in parallel. by defau lt (simult=1), samples ar e taken simultaneously (synchronously) and scanning stops when either c onverter encounters a disabled sample or both converters complete all four samples. when simult=0, samples are taken asynchronously and scanning stops when each converter encounters a disa bled sample in its part of the sdis register or completes all four samples. if external sync is enabled (sync0=1) new s cans will be started for each sync pulse as long as the adc has completed the previous scan (stat:cip n =0). ? 110 = reserved use ? 111 = reserved use 23.5.2 control 2 register (ctrl2 ) under sequential scan modes operating mode dependencies occur when the adc?s s can mode (smode in the ctrl1 register) is set to once sequential, loop sequential, or triggered sequential bits 15 ? 5 are reserved. only the div field is available.
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-26 freescale semiconductor preliminary figure 23-14. control 2 (ctrl2) regist er under sequential scan modes 23.5.2.1 reserved?bits 15?5 this bit field is reserved and should not be modified by writing. 23.5.2.2 clock divisor select (div)?bits 4 ? 0 the divider circuit genera tes the adc clock by dividing the system clock by 2 (div[4:0]+1). a div value must be chosen so the adc clock does not exceed 5.33mhz. the following table shows adc clock frequency based on the value of div fo r these various occs configurations. 23.5.3 control 2 register (ctr l2) under parallel scan modes operating mode dependencies of this register occur when the adc?s scan mode (smode in the ctrl1 register) is set to once parallel, loop parallel, or triggered parallel bits 14 ? 11, and 5 are no longer reserved. these bits are used to control the operation of converter b. 1514131211109876543210 field reserved div 0000000000000010 r/w r/w address ipsbar + 0x19_0001 table 23-7. adc clock frequency for various conversion clock sources div divisor rosc standby 400khz rosc normal 8mhz pll 64 mhz external clk 200khz sys clock 4mhz sys clock 32mhz sys clock clk/2 sys clock 0_0000 2 100k 2.00m 16.0m clk/4 0_0001 4 100k 1.00m 8.00m clk/8 0_0010 6 100k 500k 5.33m clk/12 0_0011 8 100k 250k 4.00m clk/16 0_0100 10 100k 125k 3.20m clk/20 ?? ? ? ? ? ?? ? ? ? ? 1_1111 64 100k 62.5k 500k clk/128
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-27 preliminary by default, simult=1 and converter b operates togeth er with converter a. in this case bits 14, 13, 12, and 11 in ctrl2 do not affect converter b operat ion. when simult=0 and smode is a parallel scan bits 14 ? 11 in ctrl2 along with the sync1 input are used to control the converter b scan. in this case eosie1 enables the eosi1 interrupt, signaling the end of a b converter scan. also, the cip1 bit in the stat register is used to indicat e a converter b scan is active. figure 23-15. control 2 (ctrl2) register under parallel scan modes 23.5.3.1 reserved?bit 15 this bit is reserved or not implemented. it is read as 0 and cannot be modified by writing. 23.5.3.2 stop (stop1)?bit 14 during parallel scan modes when simult=0, setting stop1 stops parallel scan s in the b converter and prevents new ones from star ting. any further sync1 input pulses (please see sync1 bit) or writes to the start1 bit are ignored until the st op1 bit is cleared. after the adc is in stop mode, the b converter results registers can be modified by the processor. any changes to the result registers in stop mode are treated as if the analog core supplied the data. th erefore, limit checking, zer o crossing, and associated interrupts can occur if enabled. this is not the same as the device?s stop mode . ? 0 = normal operation ? 1 = stop command issued 23.5.3.3 start conversion (start1)?bit 13 during parallel scan modes when si mult=0, a b converter parallel scan is started by writing 1 to the start1 bit. this is a write-only bit. writing 1 to the start1 bit again will be ignored until the end of the current scan. ? 0 = no action ? 1 = start a b converter parallel scan the adc must be in a stable power configuration prior to writing the start bit. refer to the functional description of power m odes for further details. 15 14 13 12 11 109876 5 4 3 2 1 0 field ? stop1 start1 sync1 eosie1 0 0 0 0 0 simu lt div 0 1 0 1 0 00000 0 00010 r/w ? r/w w r/w ? r/w address ipsbar + 0x19_0001
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-28 freescale semiconductor preliminary 23.5.3.4 sync1 enable (sync1)?bit 12 during parallel scan modes when si mult=0, setting sync1 to 1 permits a b converter parallel scan to be start by asserting the sync1 input for at leas t one adc clock cycle. a ny additional sync1 input pulses will be ignored until the end of the scan. ? 0 = b converter parallel scan is in itiated by a write to start1 bit only ? 1 = use a sync1 input pulse or start1 b it to initiate a b converter parallel scan the adc must be in a stable power mode prior to sync1 input assertion. please refer to the functional description of power m odes for further details. in once scan modes, only a first sync1 input pulse is honored. subsequent sync1 input pulses are ignored until the sync1 input is re -armed by writing to the ctrl2 regi ster, usually by simply rewriting 1 to sync1. this can be done at any time, including while the scan remains in process. 23.5.3.5 reserved?bits 10?6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 23.5.3.6 end of scan interrupt enable 1 (eosie1)?bit 11 during parallel scan modes when simult=0, this bi t enables an eosi1 interr upt to be generated upon completion of a b converter parall el scan. for looping scan mode, th e interrupt will trigger upon the completion of each it eration of the loop . ? 0 = interrupt disabled ? 1 = interrupt enabled 23.5.3.7 simultaneous mode (simult)?bit 5 this bit only affects pa rallel scan modes. when simult=1 (default value) parallel scans operate in simultaneous mode. the scans in the a and b converter operate simultaneously and always result in pairs of simult aneous conversions in the a and b converter. start0, stop0, sync0, and eosie0 control bits and the sync 0 input are used to start and stop scans in both converters simultaneously. a scan ends in both converters when either converter encounters a disabled sample slot. when the parallel scan completes, the eosi0 triggers if eosien0 is set. the cip0 status bit indicates th at a parallel scan is in process. when simult=0, parallel scans in the a and b converters operate inde pendently. the b converter has its own independent set of the above controls (start1, stop1, sy nc1, eosie1, sync1) designed to control its operation and repor t its status. each converter ? s scan continues until its sample list is exhausted (four samples) or a disabled sample its part of sdis is encountered. for looping para llel scan mode, each converter starts its next iteration as soon as the previous iteration in that converter is complete and continues until the stop bit for that converter is asserted. ? 0 = parallel scans done independently ? 1 = parallel scans done simultaneously (default)
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-29 preliminary 23.5.3.8 clock divisor select (div)?bits 4 ? 0 the divider circuit genera tes the adc clock by dividing the system clock by 2 (div[4:0]+1). a div value must be chosen so the ad c clock does not exceed 5.33mhz. table 23-8 shows adc clock frequency based on the value of div for thes e various occs configurations. 23.5.4 zero crossing control register (zxctrl) the adc zero crossing control (zxctr l) register provides the ability to monitor the selected channels and determine the direction of zero crossing triggering the optional interr upt. zero crossing logic monitors only the sign change betwee n current and previous samp le. zce0 bit monitors the sample stored in rslt0, zce1 bit monitors rslt1, zce7 bit monitors rslt7. when the zero cros sing is disabled for a selected result register, sign changes are not moni tored or updated in the zxstat register. figure 23-16. zero crossing control (zxctrl) register 23.5.4.1 zero crossing enable n ( zce n )?bits 15?0 for each channel, n , setting the zce n field allows detection of the indicated zero crossing condition, provided the corresponding of fset register (offst n ) has a value offset , 0 < offset < 0x7ff8. ? 00 = zero crossing disabled table 23-8. adc clock frequency for various conversion clock sources div divisor rosc standby 400khz rosc normal 8mhz pll 64 mhz external clk 200khz sys clock 4mhz sys clock 32mhz sys clock clk/2 sys clock 0_0000 2 100k 2.00m 16.0m clk/4 0_0001 4 100k 1.00m 8.00m clk/8 0_0010 6 100k 500k 5.33m clk/12 0_0011 8 100k 250k 4.00m clk/16 0_0100 10 100k 125k 3.20m clk/20 ?? ? ? ? ? ?? ? ? ? ? 1_1111 64 100k 62.5k 500k clk/128 1514131211109876543210 field zce7 zce6 zce5 zce4 zce3 zce2 zce1 zce0 reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x19_0002
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-30 freescale semiconductor preliminary ? 01 = zero crossing enabled for positive to negative sign change ? 10 = zero crossing enabled for negative to positive sign change ? 11 = zero crossing enabled for any sign change 23.5.5 channel list 1 and 2 registers (clst1 and clst2) the channel list register c ontains an ordered list of the analog i nput channels to be converted when the next scan is initiated. if all sample s are enabled in the sdis register, a sequential scan of inputs proceeds in order of sample0 through sample 7. if one of the paralle l sampling modes is se lected instead, the converter a sampling order is sample0-3 and the converter b sampli ng order is sample4-7. figure 23-17. channel list 1 (clst1) register figure 23-18. channel list 2 (clst2) register 23.5.5.1 reserved?bits 15, 11, 7 and 3 these bits are reserved or are not implemented. they are read as 0 and cannot be modified by writing. 23.5.5.2 sample n (sample4)?bits 2, 1, and 0 the value of the sample n field is used to select the input channel to be sampled. 1514131211109876543210 field sample3 sample2 sample1 sample0 reset 0011_0010_0001_0000 r/wrr/wrr/wrr/wrr/w address ipsbar + 0x19_0003 1514131211109876543210 field sample7 sample6 sample5 sample4 reset 0111_0110_0101_0100 r/w r r/w r r/w r r/w r r/w address ipsbar + 0x19_0004 table 23-9. adc input conversion for sample bits sample n [2:0] adc input pins selected sequential mode parallel mode n =0,1,2,...,7 n =0,1,2,3 (conv. a) n =4,5,6,7 (conv. b) single ended differential
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-31 preliminary in sequential modes, the sample sl ots are converted in order from sample0 to sample7. analog input pins can be sampled in any order, including sampling the same input pin more than once. in parallel modes, converter a processes sample slots sample0 through sample3 while converter b processes sample slots sample4 through sample7. si nce converter a only has access to analog inputs ana0 through ana3, sample slots sample0-3 should onl y contain binary values between 000 and 011. likewise, since converter b only has access to analog inputs anb0 thr ough anb3, sample slots sample4-7 should only contain binary values betw een 100 and 111. no damage will occur if this constraint is violated but results are undefined. when inputs are configured as differ ential pairs, a reference to either analog input in a di fferential pair by a sample slot implies a differential measurement on th e pair. the details of single ended and differential measurement are described under the chncfg field. sample slots are di sabled using the sdis register. 23.5.6 sample disable register (sdis) this register is an extension to the clst1and cl st2, providing the ability to enable only the desired samples programmed in the sample0?s ample7. at reset all samples are enabled. for example, if in a sequential mode and bit ds5 is set to 1, sample0 th rough sample4 are sampled. however, if parallel mode is selected and bits ds 5 or ds1 are set to 1, only sa mple0 and sample4 are sampled. figure 23-19. sample disable (sdis) register 000 000 ana0 ana0+, ana1 ? 001 001 ana1 010 010 ana2 ana2+, ana3 ? 011 011 ana3 100 100 anb0 anb0+, anb1 ? 101 101 anb1 110 110 anb2 anb2+, anb3 ? 111 111 anb3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field reserved ds7 ds6 ds5 ds4 ds3 ds2 ds1 ds0 reset00000000 0 0 0 0 0 0 0 0 r/w ? r/w address ipsbar + 0x19_0005 table 23-9. adc input conversion for sample bits
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-32 freescale semiconductor preliminary 23.5.6.1 reserved?bits 15 ? 8 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 23.5.6.2 disable sample (ds n )?bits 7 ? 0 the respective sample n field can be enabled or disabled where n = 0 ? 7. ?0 = enable sample n ? 1 = disable sample n and all subsequent samples. whic h samples are actually disabled will depend on the conversion mode, sequential/p arallel, and the value of simult. 23.5.7 status register (stat) this register provides the curren t status of the adc module. rdy n bits are cleared by reading their corresponding result (rslt n ) registers. hlmti and llm ti bits are cleared by wr iting 1 to each asserted bit in the adc limit status (limstat) register. likewi se, the zci bit, bit-10, is cleared by writing 1 to each asserted bit in the adc zero cros sing status (zxstat) register. the eosi n bits are cleared by writing 1 to them. please see figure 23-19 for more information regard ing the operation of interrupts. except for cip0 and cip1 all bits in the stat register are sticky . once set to a 1 state, they require some specific action to clear them. they are not cl eared automatically on the next scan sequence. figure 23-20. status (stat) register 23.5.7.1 conversion in progress 0 (cip0)?bit 15 this bit indicates when a scan is in progress. ? 0 = idle state ? 1 = a scan cycle is in progress. the adc will ignore all sync pulse s or start commands. this bit supports any sequential scan or parallel sc an with simult=1. when ex ecuting a parallel scan with simult = 0 this bit services the scan of c onverter a while the cip1 bit services the scan of converter b. 23.5.7.2 conversion in progress 1 (cip1)?bit 14 this bit indicates when a scan is in progress. ? 0 = idle state 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field cip0 cip1 0 eosi1 eosi0 zci llmti hlmti rdy7 rdy6 rdy5 rdy4 rdy3 rdy2 rdy1 rdy0 reset0000 000 0 00000000 r/w r ? r/w r address ipsbar + 0x19_0006
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-33 preliminary ? 1 = a scan cycle is in progress. the adc will ignore all sync pul ses or start commands this refers only to a b converter scan in non- simultaneous (simult=0) parallel scan modes. 23.5.7.3 reserved?bit 13 this bit is reserved or not implemented. it is read as 0 and cannot be modified by writing. 23.5.7.4 end of scan in terrupt 1 (eosi1)?bit 12 this bit indicates whether a scan of analog inputs ha ve been completed since the last read of the stat register or since a reset. the eosi1 bit is cleared by writing 1 to it. this bit cannot be set by software. ? 0 = a scan cycle has not been co mpleted, no end of scan irq pending ? 1 = a scan cycle has been completed, end of scan irq pending in looping scan modes, this interrupt is triggered at the completion of each it eration of the loop. this interrupt is triggered only by the completion of a b converter scan in non-simultaneous (simult=0) parallel scan modes. in this case the eosi0 interrupt is triggered wh en converter a completes its scan. 23.5.7.5 end of scan in terrupt 0 (eosi0)?bit 11 this bit indicates whether a scan of analog inputs ha s been completed since the last read of the stat register or since a reset. the eosi0 bit is cleared by writing 1 to it. this bit cannot be set by software. eosi0 is the preferred bit to poll for scan completion if interrupts are not enabled. ? 0 = a scan cycle has not been co mpleted, no end of scan irq pending ? 1 =a scan cycle has been completed, end of scan irq pending in looping scan modes, this interrupt is triggere d at the completion of ea ch iteration of a loop. this interrupt is triggered upon the completion of a ny sequential scan or para llel scan with simult=1. when executing parallel scans with simult = 0 this interrupt is triggered wh en converter a completes it scan while the eosi1inte rrupt services converter b. 23.5.7.6 zero crossing interrupt (zci)?bit 10 this bit is asserted at the completion of an indi vidual conversion experiencing a zero crossing enabled in adc zero crossing control (zxctrl) re gister. the bit is set as soon as an enabled zero crossing event occurs rather than at the end of the adc scan. the zci bit is cleared by writin g 1 to all active zcs[7:0] bits in the zxstat register. ? 0 = no zci interrupt request ? 1 = zero crossing encountered ; irq pending if zcie is set
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-34 freescale semiconductor preliminary 23.5.7.7 low limit inte rrupt (llmti)?bit 9 if any low limit (lolim n ) register is enabled by having a value other than $0000, low limit checking is enabled. this bit is set at the co mpletion of an individual conversion wh ich may or may not be the end of a scan. the llmti bit is cleared by writing 1 to all act ive lls[7:0] bits in the limstat register. ? 0 = no low limit interrupt request ? 1 = low limit exceeded, irq pending if llmtie is set 23.5.7.8 high limit interrupt (hlmti)?bit 8 if any high limit (hilim n ) register is enabled by ha ving a value other than 0x 7ff8, high limit checking is enabled. this bit is set at the completion of an individual conversi on which may or ma y not be the end of a scan. the hlmti bit is cleared by writing 1 to all ac tive hls[7:0] bits in the limstat register. ? 0 = no high limit interrupt request ? 1 = high limit exceeded, irq pending if hlmtie is set 23.5.7.9 ready sample 7 ? 0 (rdy n )?bits 7 ? 0 these bits indicate sample s seven through zero are r eady to be read. the rdy n bits are set as the individual channel conversions are completed and stored in a rslt n register. these bits are cleared after a read from the corres ponding adc results (rslt n ) register. if polling the rdy n bits to determine if a particular sample is executed, care should be taken not to start a new scan until all enabled samples are completed. note rdy n bits can be cleared when th e debugger reads the corresponding results register during a debug session. ? 0 = sample not ready or has been read ? 1 = sample ready to be read figure 23-21 illustrates how five interrupts sources are combined into three entries in the interrupt vector table.
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-35 preliminary figure 23-21. adc interrupt sources 23.5.8 limit status register (limstat) the adc limit status (limstat) register latches in the result of the comparison between the result of the sample in the rslt n register and the respecti ve limit register, hilim n or lolim n . here is an example. if the result for rslt0 is gr eater than the value program med into the hilim0, then set the hls0 bit to 1. an interrupt is generated if the hlmtie bit is set in ctrl1. these bits are sticky . once set, the bits require a specifi c modification to clear them. they are not cleared automatically by subsequent conversions. a bit may only be cleare d by writing a value of one to that specific bit. figure 23-22. limit status (limstat) register 23.5.9 zero crossing st atus register (zxstat) the adc zero crossing status (zxs tat) register latches in the re sult of the comparison between the current result of the sample and the previous result of the same results re gister. for example, if the result for the channel programmed in sample0 changes sign from the previous conve rsion and the respective zce bit in zxctrl register is set to 11b (any edge change) then set the zcs0 bit to 1. an interrupt is generated if the zcie bit is set in the ctrl1 register. these bits are sticky . once set, they require a write to clear them. they are not cleared automatically by subsequent convers ions. a bit may only be cleared by writing a value of 1 to that specific bit. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field hls7 hls6 hls5 hls4 hls3 hls2 hls1 hls0 lls7 lls6 lls5 lls4 lls3 lls2 lls1 lls0 reset00000000 0 0 0 0 0 0 0 0 r/w r/w address ipsbar + 0x19_0007 eosi0 eosie0 eosi1 eosie1 zci zcie adc zero crossing or limit error llmtie hlmti hltmie llmti (adc_err_int ) adcb conversion complete (adc_cc1_int ) adca conversion complete (adc_cc0_int )
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-36 freescale semiconductor preliminary figure 23-23. zero crossing status (zxstat) register 23.5.9.1 reserved?bits 15 ? 8 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 23.5.9.2 zero crossing status (zcs[7:0])?bits 7 ? 0 the zero crossing condition is determined by examinin g the adc value after it has been adjusted by the offset for the result register. please see figure 23-7 . each bit of the register is cleared by writing 1 to that register bit. ? 0 = a. a sign change did not occu r in a comparing the current rslt n value and the previous rslt n value, or b. zero crossing control is disabled for sample n in the adc zero crossing control (zxctrl) register ? 1 = in a comparison between the current channelx result and the previous channelx result, a sign change condition occurred as de fined in the adc zero crossi ng control (zxctrl) register 23.5.10 result 0-7 registers (rslt0?7) the eight result registers contain the converted result s from a scan. the sample0 result is loaded into rslt0 register, sample1 result in rslt1 register, and so on. in a simultaneous parallel scan mode, the first channel pair, designated by sample0 and sa mple4 in register list1/2, is stored in rslt0 and rslt4, respectively. when writing to this register, only th e rslt portion of the value written is used. this value is modified as shown in figure 23-7 and the result of the subtract ion is stored. the sext bit is only set as a result of this subtraction and is not directly determined by the value written. adc result register 0 ? address: adc_base + $9 adc result register 1 ? address: adc_base + $a adc result register 2 ? address: adc_base + $b adc result register 3 ? address: adc_base + $c adc result register 4 ? address: adc_base + $d adc result register 5 ? address: adc_base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field zcs7 zcs6 zcs5 zcs4 zcs3 zcs2 zcs1 zcs0 reset00000000 0 0 0 0 0 0 0 0 r/w ? r/w address ipsbar + 0x19_0008
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-37 preliminary adc result register 6 ? address: adc_base + $f adc result register 7 ? address: adc_base + $10 figure 23-24. result (rslt0 ? 7) registers 23.5.10.1 sign extend (sext)?bit 15 sext is the sign-extend bit of the re sult. when the sext bit is set to 1, it implies a negative result. when the sext bit is set to 0, it implies a positive result. if only pos itive results are required, then the respective adc offset (offst n ) register must be set to a value of 0. 23.5.10.2 digital result of the conversion (rslt)?bits 14 ? 3 rslt can be interpreted as either a signed integer or a signed fixed point (fract ional) number. as a fixed point number, the rslt can be used directly. as a signed inte ger, one has the option to right shift with sign extend (asr) three places to fit it into the range [0,4095]. or one can accept the number as presented in the register, knowing there are missing codes because the lowe r three lsbs are always zero. negative results, sext = 1, are always presented in twos complement form at. if it is a re quirement of an application, the result regist ers always be positive, the offset register (offst n) must always be set to 0. the interpretation of the numbers programme d into the adc limit and offset (lolim n , hilim n , and offst n ) registers should match your interp retation of the result register. 23.5.10.3 test data (test_data)?bits 14 ? 3 when the adc is stopped or in power-down mode this field can be written by accessing the register in the memory map. please see section 23.4.3, ?adc data processing more information. 23.5.10.4 reserved?bits 2 ? 0 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 23.5.11 low and high limit registers (lolim0-7 and hilim0-7) each adc sample is compared against the values in the limit registers. the comparison is based upon the raw conversion value be fore the offset correctio n is applied. refer to figure 23-7 . adc limit registers (lolim n and hilim n) correspond to results (rslt n ) registers. the high limit register is used for the comparison of result > high limit . the low limit register is used for the comparison of 1514131211109876543210 field sext rslt 0 0 0 reset0 000000000000000 r/w r r/w ? address ipsbar + 0x19_0009 - 0x19_0010
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-38 freescale semiconductor preliminary result < low limit . the limit checking can be disabled by progr amming the respective limit register with 0x7ff8 for the high limit and 0x0000 for the low lim it. at reset, limit checking is disabled. adc low limit register 0 ? address: adc_base + $11 adc low limit register 1 ? address: adc_base + $12 adc low limit register 2 ? address: adc_base + $13 adc low limit register 3 ? address: adc_base + $14 adc low limit register 4 ? address: adc_base + $15 adc low limit register 5 ? address: adc_base + $16 adc low limit register 6 ? address: adc_base + $17 adc low limit register 7 ? address: adc_base + $18 figure 23-25. low limit register (lolim0 ? 7) adc high limit register 0 ? address: adc_base + $19 adc high limit register 1 ? address: adc_base + $1a adc high limit register 2 ? address: adc_base + $1b adc high limit register 3 ? address: adc_base + $1c adc high limit register 4 ? address: adc_base + $1d adc high limit register 5 ? address: adc_base + $1e adc high limit register 6 ? address: adc_base + $1f adc high limit register 7 ? address: adc_base + $20 figure 23-26. high limit register (hilim0?7) 1514131211109876543210 field ? llmt 0 0 0 reset0 000000000000000 r/w ? r/w ? address ipsbar + 0x19_0011 - 0x19_0018 1514131211109876543210 field ? hlmt 0 0 0 reset0 000000000000000 r/w ? r/w ? address ipsbar + 0x19_0019 - 0x19_0020
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-39 preliminary 23.5.12 offset registers (offst0?7) value of the offset (offst n ) register is used to correct the adc re sult before it is stored in the rslt n registers. adc offset register 0 ? address: adc_base + $21 adc offset register 1 ? address: adc_base + $22 adc offset register 2 ? address: adc_base + $23 adc offset register 3 ? address: adc_base + $24 adc offset register 4 ? address: adc_base + $25 adc offset register 5 ? address: adc_base + $26 adc offset register 6 ? address: adc_base + $27 adc offset register 7 ? address: adc_base + $28 figure 23-27. offset 0-7 (offst0-7) registers the offset value is subtracted from the adc result . in order to obtain unsigned results, the respective offset register should be programme d with a value of $0000, thus giving a result range of $0000 to $7ff8. 23.5.13 power control register (pwr) this register controls the power management feat ures of the adc module. there are manual power-down control bits for the two adc convert ers and the shared voltage referenc e generator. there are also five distinct power modes. the followi ng terms are used to describe power modes and their related controls. 1. powered down state each converter and the voltage reference generato r can individually be put into a powered down state. when powered down, the unit consumes no power. results of scans referencing a powered down converter are undefined. the vol tage reference generator and at least one converter must be powered up to use the adc module. 2. manual power-down controls each converter and the voltage reference genera tor have a manual power control bit capable of forcing that component into the power down state. also, each c onverter and the voltage reference generator can be powered up/down automa tically as part of adc operation. 3. idle state the adc module is idle when neither of the two converters has a scan in process. 1514131211109876543210 field ? offset 0 0 0 reset0 000000000000000 r/w ? r/w ? address ipsbar + 0x19_0021 - 0x19_0028
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-40 freescale semiconductor preliminary 4. active state the adc module is active when at least one of the two converters has a scan in process. 5. current mode ? normal current mode is used to power the converters at cl ock rates above 100khz. ? standby current mode uses less pow er and is engaged only when the adc clock is at 100khz. the current mode active does not affect the number of adc clock cycles required to do a conversion or the accuracy of a conversion. the adc module may change the curr ent mode when idle as part of the power saving strategy. both converters will be in the sa me current mode at all times. in addition to the power modes, startup delay is defined as: ? auto power-down and auto standby power mode s cause a startup delay when the adc module goes between the idle and active states to allow time to switch clocks or power configurations. the number of adc clocks used in the start up delay is defined by the pudelay field. see the discussion of power modes in the f unctional description section 23.4, ?functional description ? for details of the five power mode s and how to configure them. see section 23.4.7, ?adc clock ? for a more detailed description of the clocking system and the control of current mode. figure 23-28. power control (pwr) register 23.5.13.1 auto standby (asb)?bit 15 the asb bit selects auto standby mode. asb is ignored if apd is 1. when the adc is idle, auto standby mode selects the standby clock as the adc clock s ource and puts the converters into standby current mode. at the start of any scan, the conversion cl ock is selected as the adc clock and a delay of pudelay adc clock cycles is imposed for current levels to stabilize. after this delay, the adc will initi ate the scan. when the adc returns to the idle st ate, the standby clock is again select ed and the converters revert to the standby current state. ? 0 = auto standby mode disabled ? 1 = auto standby mode enabled 23.5.13.2 reserved?bits 14?13 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 23.5.13.3 voltage reference power status 2 (psts2)?bit 12 psts2 is a read-only bit. it simply reflects whether the voltage reference circuit is currently enabled. 15141312 11 10987654 3 2 1 0 field asb ? ? psts2 psts1 psts0 pudelay apd pd2 pd1 pd0 reset0 00 0 0 0 001101 0 1 1 1 r/w r/w ? r r/w address ipsbar + 0x19_0029
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-41 preliminary ? 0 = voltage reference circuit is currently powered up ? 1 = voltage reference circuit is currently powered down 23.5.13.4 converter b power status 1 (psts1)?bit 11 psts1 is a read-only bit. it is asserted immediately followi ng a write of 1 to pd1. it is deasserted pudelay adc clock cycles af ter writing 0 to pd1 if apd is 0. this bit can be read as a status bit to determine when the adc is ready for operation. duri ng auto power-down mode, this bit indicates the current powered stat e of converter b. ? 0 = adc converter b is currently powered up ? 1 = adc converter b is currently powered down 23.5.13.5 converter a power status 0 (psts0)?bit 10 psts0 is a read-only bit. it is asserted immediately followi ng a write of 1 to pd0. it is deasserted pudelay adc clock cycles af ter writing 0 to pd0 if apd is 0. this bit can be read as a status bit to determine when the adc is ready for operation. duri ng auto power-down mode, this bit indicates the current powered stat e of converter a. ? 0 = adc converter a is currently powered up ? 1 = adc converter a is currently powered down 23.5.13.6 power-up delay (pudelay)?bits 9?4 this 6-bit field determines the number of adc cl ocks provided to power-up an adc converter (after setting pd0 or pd1 to 0) be fore allowing a scan to start. it also determines the number of adc clocks of delay provided in auto power-down (apd) and au to standby (asb) modes be tween when the adc goes from the idle to active state and when the scan is allowed to start. the defa ult value is 13 adc clocks. accuracy of the initial c onversions in a scan will be degraded if pudelay is set to too small a value. note pudelay defaults to a value typically sufficient for any power mode. the latency of a scan can be reduced by reducing pudelay to the lowest value for which accuracy is not degraded. please refer to the device data sheet for further details. 23.5.13.7 auto power-down (apd)?bit 3 auto power-down mode powers down converters when not in use for a scan. ap d takes precedence over asb. when a scan is started in apd mode, a dela y of pudelay adc clock cy cles is imposed during which the needed converter(s), if id le, are powered up. the adc will then initiate a scan equivalent to when apd is not active. when the scan is co mpleted, the converter(s) are powered down again. ? 0 = auto power-down mode is not active ? 1 = auto power-down mode is active
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-42 freescale semiconductor preliminary note if asb or apd is asserted while a scan is in progress, that scan is unaffected and the adc will wait to enter its low power state unt il after all conversions are complete and both adcs are idle. note asb and apd are not useful in looping modes. the continuous nature of scanning means the low power state can never be entered. 23.5.13.8 power-down control for volt age reference circuit 2 (pd2)?bit 2 this bit controls the power-down of the adc?s voltage reference current. ? 0 = manually power-up voltage reference circuit ? 1 = power-down voltage reference circui t is controlled by pd0 and pd1 (default) the voltage reference circuit is shared by both converters. when pd 2=1 the voltage re ference will be activated whenever pd1 or pd0 are pow ered up. it is not usually nece ssary to modify this bit, since powering down both converter a and converter b will automatical ly power-down the voltage reference. 23.5.13.9 manual power-down for converter b (pd1)?bit 1 this bit forces adc converter b to power-down. ? 0 = power-up adc converter b ? 1 = power-down adc converter b asserting pd1 powers down converter b immediately. the results of a sc an using converter b will be invalid while pd1 is assert ed. when pd1 is cleared, c onverter b is either cont inuously powered up (apd = 0) or automatically powered up when needed (apd=1). when clearing pd1 in any power mode except auto power-down (apd=1), wait pudelay adc clock cycles before initiating a scan to stabilize pow er levels within the converter . the psts1 bit can be polled to determine when the pudelay time has elapsed. failure to follow this procedure can result in loss of accuracy of the first two samples. 23.5.13.10 manual power-down for converter a (pd0)?bit 0 this bit forces adc converter a to power-down. ? 0 = power-up adc converter a ? 1 = power-down adc converter a asserting pd0 powers down converter a immediately. the results of a sc an using converter a will be invalid while pd0 is asserted. when pd0 is cleared, converter a is either co ntinuously powered up (apd = 0) or automatically powered up when needed (apd=1). when clearing pd0 in any power mode except auto power-down (apd=1), wait pudelay adc clock cycles before initiating a scan to stabilize pow er levels within the converter . the psts0 bit can be polled
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-43 preliminary to determine when the pudelay time has elapsed. failure to follow this pro cedure can result in loss of accuracy of the first two samples. 23.5.14 voltage reference register (vref) in earlier series this register supported ad c calibration and had a differen t name. improvements in adc performance have eliminated the need for on-ch ip calibration support, hence the new name. figure 23-29. voltage reference (vref) register 23.5.14.1 select v refh source (sel_vrefh)?bit 15 this bit selects the source of the v refh reference for conversions. ? 0 = internal vr x ? 1 = ana2 23.5.14.2 select v refl source (sel_vrefl)?bit 14 this bit selects the source of the v refl reference for conversions. ? 0 = internal vr x ?1 = anb2 15 14 131211109876543210 field sel_vrefh sel_vrefl reserved reset 0 0 00000000000000 r/w r/w ? address ipsbar + 0x19_002a
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-44 freescale semiconductor preliminary 23.5.14.3 reserved?bits 13?0 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing.
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 freescale semiconductor 23-45 preliminary
analog-to-digital converter (adc) mcf5213 reference manual, rev. 1.1 23-46 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-1 preliminary chapter 24 pulse width modulation (pwm) module 24.1 introduction this chapter describes the configuration and operati on of the pulse width modulation (pwm) module. it includes a block diagram, programming model, and functional description. 24.1.1 overview the pwm module shown in figure 24-1 , generates a synchronous series of pulses having programmable period and duty cycle. with a suitable low-pass filte r, the pwm can be used as a digital-to-analog converter. figure 24-1. pwm block diagram summary of the main features include: ? double-buffered period and duty cycle internal bus clock (f sys/3 ) clock select pwm clocks period and duty counter channel 3 period and duty counter channel 2 period and duty counter channel 1 period and duty counter channel 0 pwm channels alignment polarity control pwmout3 pwmout2 pwmout1 pwmout0 enable period and duty counter channel 5 period and duty counter channel 4 pwmout5 pwmout4 period and duty counter channel 7 period and duty counter channel 6 pwmout7 pwmout6
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-2 freescale semiconductor preliminary ? left- or center-aligned outputs ? eight independent pwm modules ? byte-wide registers provide program mable duty cycle and period control ? four programmable clock sources note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 11, ?general purpose i/o module ?) prior to configuring the pwm module. 24.2 memory map/register definition this section describes the registers and control bi ts in the pwm module. th ere are eight independent pwm modules, each with its own control and counter registers. the memory map for the pwm is shown in below. table 24-1. pwm memory map address 1,2 1 addresses not assigned to a register and undefined register bits are reserved for expansion. write accesses to these reserved address spaces and reserved register bits have no effect. 2 32-bit access to any of these registers will result in a bus transfer error (see section 11.2.6, ?scm interrupt register (scmir)? ). register access reset value section/page 0x001b_0000 pwm enable register (pwme) r/w 0x00 24.2.1/24-3 0x001b_0001 pwm polarity register (pwmpol) r/w 0x00 24.2.2/24-4 0x001b_0002 pwm clock select register (pwmclk) r/w 0x00 24.2.3/24-4 0x001b_0003 pwm prescale clock sele ct register (pwmprclk) r/w 0x00 24.2.4/24-5 0x001b_0004 pwm center align enable register (pwmcae) r/w 0x00 24.2.5/24-6 0x001b_0005 pwm control register (pwmctl) r/w 0x00 24.2.6/24-7 0x001b_0008 pwm scale a register (pwmscla) r/w 0x00 24.2.7/24-8 0x001b_0009 pwm scale b register (pwmsclb) r/w 0x00 24.2.8/24-8 0x001b_000c ... 0x001b_0013 pwm channel n counter register (pwmcnt n ) r/w 0x00 24.2.9/24-9 0x001b_0014 ... 0x001b_001b pwm channel n period register (pwmper n )r/w0xff 24.2.10/24-10 0x001b_001c ... 0x001b_0023 pwm channel n duty register (pwmdty n )r/w0xff 24.2.11/24-11 0x001b_0024 pwm shutdown register (pwmsdn) r/w 0x00 24.2.12/24-11
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-3 preliminary 24.2.1 pwm enable register (pwme) each pwm channel has an enable bit (pwme n ) to start its waveform output. while in run mode, if all eight pwm output channels are disabled (pwme[7: 0] = 0) the prescaler counter shuts off for power savings. see section 24.3.2.1, ?pwm enable? for more information. address: 0x001b_0000 (pwme) access: user read/write 7 6543210 r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w reset: 0 0 0 0 0 0 0 0 figure 24-2. pwm enable register (pwme) table 24-2. pwme field descriptions field description 7 pwme5 pwm channel 7 output enable. if enabled, the pwm signal becomes available at pwmout7 when its corresponding clock source begins its next cycle. 0 pwm output disabled 1 pwm output enabled 6 pwme4 pwm channel 6 output enable. if enabled, the pwm signal becomes available at pwmout6 when its corresponding clock source begins its next cycle. if pw mctl[con67] is set, then this bit has no effect and pwmout6 is disabled. 0 pwm output disabled 1 pwm output enabled 5 pwme5 pwm channel 5 output enable. if enabled, the pwm signal becomes available at pwmout5 when its corresponding clock source begins its next cycle. 0 pwm output disabled 1 pwm output enabled 4 pwme4 pwm channel 4 output enable. if enabled, the pwm signal becomes available at pwmout4 when its corresponding clock source begins its next cycle. if pw mctl[con45] is set, then this bit has no effect and pwmout4 is disabled. 0 pwm output disabled 1 pwm output enabled 3 pwme3 pwm channel 3 output enable. if enabled, the pwm signal becomes available at pwmout3 when its corresponding clock source begins its next cycle. 0 pwm output disabled 1 pwm output enabled 2 pwme2 pwm channel 2 output enable. if enabled, the pwm signal becomes available at pwmout2 when its corresponding clock source begins its next cycle. if pw mctl[con23] is set, then this bit has no effect and pwmout2 is disabled. 0 pwm output disabled 1 pwm output enabled, if pwmctl[con23]=0
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-4 freescale semiconductor preliminary 24.2.2 pwm polarity register (pwmpol) the starting polarity of each pwm channel waveform is determined by the associated pwmpol[ppol n ] bit. if the polarity is changed wh ile a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. 24.2.3 pwm clock select register (pwmclk) each pwm channel has the capability of selecting one of two clocks. fo r channels 0, 1, 4, and 5 the clock choices are clock a or sa. for cha nnels 2, 3, 6, and 7 the choices are cl ock b or sb. the clock selection is done with the below pwmclk[pclk n ] control bits. if a clock select is changed while a pwm signal is being generated, a truncated or stretc hed pulse can occur during the transition. 1 pwme1 pwm channel 1 output enable. if enabled, the pwm signal becomes available at pwmout1 when its corresponding clock source begins its next cycle. 0 pwm output disabled 1 pwm output enabled 0 pwme0 pwm channel 0 output enable. if enabled, the pwm signal becomes available at pwmout0 when its corresponding clock source begins its next cycle. if pw mctl[con01] is set, then this bit has no effect and pwmout0 is disabled. 0 pwm output disabled 1 pwm output enabled, if pwmctl[con01]=0 address: 0x001b_0001 (pwmpol) access: user read/write 7 6543210 r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w reset: 0 0 0 0 0 0 0 0 figure 24-3. pwm polarity register (pwmpol) table 24-3. pwmpol field descriptions field description 7?0 ppol n pwm channel n polarity. the even-numbered channels? polari ty has no effect when the corresponding pwmctl[con n(n+1) ] bit is set. for example, if pwmctl[con 01] = 1 then pwmpol[ppo l0] has no affect. 0 pwm channel n output is low at the beginning of the period, then goes high when the duty count is reached 1 pwm channel n output is high at the beginning of the period, t hen goes low when the duty count is reached table 24-2. pwme field descriptions (continued) field description
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-5 preliminary 24.2.4 pwm prescale clock select register (pwmprclk) the pwmprclk register selects the prescale clock source fo r clocks a and b indepe ndently. if the clock prescale is changed while a pwm si gnal is being generated, a truncated or stretched pulse can occur during the transition. address: 0x001b_0002 (pwmclk) access: user read/write 7 6543210 r pclk7 pclk6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w reset: 0 0 0 0 0 0 0 0 figure 24-4. pwm clock se lect register (pwmclk) table 24-4. pwmclk field descriptions field description 7?0 pclk n pwm channel n clock select. selects between one of two clock sources for each pwm channel. see section 24.2.4, ?pwm prescale clock sele ct register (pwmprclk)? and section 24.2.7, ?pwm scale a register (pwmscla)? for more information on how the different clock rates are generated. the even-numbered channels? clock select has no effect when the corresponding pwmctl[con n(n+1) ] bit is set. for example, if pwmctl[con01] = 1 then pwmclk[pclk0] has no affect. address: 0x001b_0003 (pwmprclk) access: user read/write 7 6543210 r 0 pckb 0 pcka w reset: 0 0 0 0 0 0 0 0 figure 24-5. pwm prescale clock select register (pwmprclk) pclk6 & pclk7 (pwm6 & pclk7 clock source) pclk4 & pclk5 (pwm4 & pwm5 clock source) pclk2 & pclk3 (pwm2 & pwm3 clock source) pclk0 & pclk1 (pwm0 & pwm1 clock source) 0b a b a 1sbsasbsa
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-6 freescale semiconductor preliminary 24.2.5 pwm center align en able register (pwmcae) the pwmcae register contains eight control bits for the selection of center-aligned outputs or left-aligned outputs for each pwm channel. write th ese bits only when the corresponding channel is disabled. see section 24.3.2.5, ?left-aligned outputs? and section 24.3.2.6, ?center-aligned outputs? for a more detailed descrip tion of the pwm output modes. table 24-5. pwmprclk field descriptions field description 7 reserved, should be cleared. 6?4 pckb clock b prescalar select. these three bits control the rate of clock b which can be used for pwm channels 2, 3, 6 and 7. 3 reserved, should be cleared. 2?0 pcka clock a prescalar select. these three bits control the rate of clock a which can be used for pwm channels 0, 1, 4 and 5. address: 0x001b_0004 (pwmcae) access: user read/write 7 6543210 r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w reset: 0 0 0 0 0 0 0 0 figure 24-6. pwm center align enable register (pwmcae) pckb clock b rate 000 internal bus clock 2 0 001 internal bus clock 2 1 ... ... 111 internal bus clock 2 7 pcka clock a rate 000 internal bus clock 2 0 001 internal bus clock 2 1 ... ... 111 internal bus clock 2 7
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-7 preliminary 24.2.6 pwm control register (pwmctl) the pwmctl register provides various cont rol of the pwm module. change the con n(n+1) bits only when both corresponding channels are disabled. see section 24.3.2.7, ?pwm 16-bit functions? for a more detailed description of the concatenation function. table 24-6. pwmcae field descriptions field description 7?0 cae n center align enable for channel n . the even-numbered channels? center align enable has no effect when the corresponding pwmctl[con n(n+1) ] bit is set. for example, if pwmctl[con01] = 1 then pwmcae[cae0] has no affect. 0 channel n operates in left-aligned output mode 1 channel n operates in center-aligned output mode address: 0x001b_0005 (pwmctl) access: user read/write 7 6543210 r con67 con45 con23 con01 pswai pfrz 0 0 w reset: 0 0 0 0 0 0 0 0 figure 24-7. pwm control register (pwmctl) table 24-7. pwmctl field descriptions field description 7 con67 concatenates pwm channels 6 and 7 to form one 16-bit pwm channel. 0 channels 6 and 7 are separate 8-bit pwms 1 concatenate pwm 6 and 7. channel 6 becomes the high order byte and channel 6 the low order byte. pwmout7 is the output for this 16-bit pwm signal, and pwmout6 is disabled. the channel 7 clock select, polarity, center align enable, and enable bits control this concatenated output. 6 con45 concatenates pwm channels 4 and 5 to form one 16-bit pwm channel. 0 channels 4 and 5 are separate 8-bit pwms 1 concatenate pwm 4 and 5. channel 4 becomes the high order byte and channel 5 the low order byte. pwmout5 is the output for this 16-bit pwm signal, and pwmout4 is disabled. the channel 5 clock select, polarity, center align enable, and enable bits control this concatenated output. 5 con23 concatenates pwm channels 2 and 3 to form one 16-bit pwm channel. 0 channels 2 and 3 are separate 8-bit pwms 1 concatenate pwm 2 and 3. channel 2 becomes the high order byte and channel 3 the low order byte. pwmout3 is the output for this 16-bit pwm signal, and pwmout2 is disabled. the channel 3 clock select, polarity, center align enable, and enable bits control this concatenated output. 4 con01 concatenates pwm channels 0 and 1 to form one 16-bit pwm channel. 0 channels 0 and 1 are separate 8-bit pwms 1 concatenate pwm 0 and 1. channel 0 becomes the high order byte and channel 1 the low order byte. pwmout1 is the output for this 16-bit pwm signal, and pwmout0 is disabled. the channel 1 clock select, polarity, center align enable, and enable bits control this concatenated output. 3 pswai pwm stops in doze mode. disables the input clock to the prescaler while in doze mode. 0 allow the clock to the prescaler while in doze mode 1 stop the input clock to the prescaler whenever the core is in doze mode
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-8 freescale semiconductor preliminary 24.2.7 pwm scale a register (pwmscla) pwmscla is the programmable scale value used in sc aling clock a to generate clock sa. clock sa is generated according to the following equation: eqn. 24-1 any value written to this register will cause the scale counter to load the new scale value (pwmscla). 24.2.8 pwm scale b register (pwmsclb) pwmsclb is the programmable scale value used in sc aling clock b to generate clock sb. clock sb is generated according to the following equation: eqn. 24-2 2 pfrz pwm counters stop in debug mode (bkpt asserted). 0 allow pwm counters to continue while in debug mode 1 disable pwm input clock to the prescaler when the core is in debug mode. useful for emulation as it allows the pwm function to be suspended. 1?0 reserved, should be cleared. address: 0x001b_0008 (pwmscla) access: user read/write 7 6543210 r scalea w reset: 0 0 0 0 0 0 0 0 figure 24-8. pwm scale a register (pwmscla) table 24-8. pwmscla field descriptions field description 7?0 scalea part of divisor used to form clock sa from clock a. table 24-7. pwmctl field descriptions (continued) field description clock sa clock a 2pwmscla ---------------------------------------- - = scalea value 0x00 256 0x01 1 0x02 2 ... ... 0xff 255 clock sb clock b 2pwmsclb ---------------------------------------- =
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-9 preliminary any value written to this register will cause the scale counter to load the new scale value (pwmsclb). 24.2.9 pwm channel counter registers (pwmcnt n ) each channel has a dedicated 8-bit up/down counter whic h runs at the rate of the selected clock source, pwmclk[pclk n ]. the user can read the counters at any time without affecting the count or the operation of the pwm channel. any value written to the counter causes the counter to reset to 0x00, the counter direction to be set to up for center-ali gned mode, the immediate lo ad of both duty and period registers with values from the buffers, and the output to change accord ing to the polarity bit. the counter is also cleared at the end of the effective period (see section 24.3.2.5, ?left- aligned outputs? and section 24.3.2.6, ?center-aligned outputs? for more details). when the channel is disabled (pwme n =0), the pwmcnt n register does not count. when a channel is enabled (pwme n =1), the associated pwm counter starts at the count in the pwmcnt n register. for more detailed information on the operation of the counters, refer to section 24.3.2.4, ?pwm timer counters.? address: 0x001b_0009 (pwmsclb) access: user read/write 7 6543210 r scaleb w reset: 0 0 0 0 0 0 0 0 figure 24-9. pwm scale b register (pwmsclb) table 24-9. pwmsclb field descriptions field description 7?0 scaleb divisor used to form clock sb from clock b. scaleb value 0x00 256 0x01 1 0x02 2 ... ... 0xff 255
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-10 freescale semiconductor preliminary 24.2.10 pwm channel period registers (pwmper n ) the pwm period registers determine the period of the associated pwm channel. refer to section 24.3.2.3, ?pwm period and duty? for more information. calculating the output period depe nds on the output mode (center- aligned has twi ce the period as left-aligned mode) as well as pwmper n . see the below equation: eqn. 24-3 for boundary case programmi ng values (e.g. pwmper n = 0x00), please refer to section 24.3.2.8, ?pwm boundary cases .? address: 0x001b_000c (pwmcnt0) 0x001b_000d (pwmcnt1) 0x001b_000e (pwmcnt2) 0x001b_000f (pwmcnt3) 0x001b_0010 (pwmcnt4) 0x001b_0011 (pwmcnt5) 0x001b_0012 (pwmcnt6) 0x001b_0013 (pwmcnt7) access: user read/write 7 6543210 r count w reset: 0 0 0 0 0 0 0 0 figure 24-10. pwm counter registers (pwmcnt n ) table 24-10. pwmcnt n field descriptions field description 7?0 count current value of the pwm up counte r. resets to zero when written. address: 0x001b_0014 (pwmper0) 0x001b_0015 (pwmper1) 0x001b_0016 (pwmper2) 0x001b_0017 (pwmper3) 0x001b_0018 (pwmper4) 0x001b_0019 (pwmper5) 0x001b_001a (pwmper6) 0x001b_001b (pwmper7) access: user read/write 7 6543210 r period w reset: 1 1 1 1 1 1 1 1 figure 24-11. pwm period registers (pwmper n ) pwm n period channel clock period pwmcae cae n [] 1 + () pwmper n =
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-11 preliminary 24.2.11 pwm channel duty registers (pwmdty n ) the pwm duty registers determine the duty cycle of the associated pwm channel. to calculate the output duty cycle (high time as a percentage of period) for a particular channel: eqn. 24-4 for boundary case programming values (e.g. pwmdty n = 0x00 or pwmdty n >pwmper n ), please refer to section section 24.3.2.8, ?pwm boundary cases.? 24.2.12 pwm shutdown register (pwmsdn) the pwm shutdown register provi des emergency shutdown functiona lity of the pwm module. the pwmsdn[7:1] bits are ignored if pwmsdn[sdnen] is cleared. table 24-11. pwmper n field descriptions field description 7?0 period period counter for the output pwm signal. if period = 0x00, the pwm n output is always high (ppol n =1) or always low (ppol n =0). see section 24.3.2.8, ?pwm boundary cases? for other special cases. address: 0x001b_001c (pwmdty0) 0x001b_001d (pwmdty1) 0x001b_001e (pwmdty2) 0x001b_001f (pwmdty3) 0x001b_0020 (pwmdty4) 0x001b_0021 (pwmdty5) 0x001b_0022 (pwmdty6) 0x001b_0023 (pwmdty7) access: user read/write 7 6543210 r duty w reset: 1 1 1 1 1 1 1 1 figure 24-12. pwm duty registers (pwmdty n ) table 24-12. pwmdty n field descriptions field description 7?0 duty contains the duty value used to determine when a transition will occur on the pwm output signal. when a match occurs with the corresponding pwmcnt n register, the pwm output will toggle. if duty = 0x00, the pwm n output is always low (ppol n =1) or always high (ppol n =0). see section 24.3.2.8, ?pwm boundary cases? for other special cases. duty cycle 1 pwmpol ppol n [] pwmdty n pwmper n ------------------------------ ? ? ?? ?? 100% =
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-12 freescale semiconductor preliminary 24.3 functional description 24.3.1 pwm clock select there are four available clocks na med clock a, b, sa (scaled a), a nd sb (scaled b), all of which are based on the internal bus clock. clock a and b can be programmed to run at 1, 1/2, ..., 1/128 times the internal bus clock. clock sa and sb use clock a and b respectively as an input and divi des it further with a relo adable counter. the rates available for clock sa and sb are programmable to run at clock a a nd b divided by 2, 4, ..., or 512. each address: 0x24 (pwmsdn) access: read/write 7 6543210 r if ie 0 lv l 0 pwm7in pwm7il sdnen w w1c restart reset: 0 0 0 0 0 0 0 0 figure 24-13. pwm shutdown register (pwmsdn) table 24-13. pwmsdn field descriptions field description 7 if pwm interrupt flag. any change in state of pwm7in will be fl agged by setting this bit. the flag is cleared by writing a ?1? to it. writing ?0? has no effect. 0 no change in pwm7in input 1 change in pwm7in input 6 ie pwm interrupt enable. an interrupt will be triggered to the device?s interrupt controller when pwmsdn[if] is set. 0 interrupt is disabled 1 interrupt is enabled 5 restart pwm restart. after setting the restart bit, the pwm cha nnels start running after the corresponding counter resets to zero. also, if emergency shutdown is cleared (after being set), the pwm outputs will restart after the corresponding counter resets to zero. this bit is self-clearing, so is always read as zero. 4 lv l pwm shutdown output level. describes the behaivor of the pwm outputs when pwm7in input is asserted and pwmsdn[sdnen] is set. 0 pwm outputs are forced to logic 0 1 pwm outputs are forced to logic 1 3 reserved, should be cleared. 2 pwm7in pwm channel 7 input status. reflects the current status of the pwmout7 pin. read only. 1 pwm7il pwm channel 7 input polariy. if pwmsdn[sdnen] is set, this bit sets the active level of the pwm 7 channel 0 pwm 7 input is active low 1 pwn 7 input is active high 0 sdnen pwm emergency shutdown enable. if set, the pin asso ciated with pwm channel 7 is forced to input and the emergency shutdown feature is enabled. 0 emergency shutdown is disabled 1 emergency shutdown is enabled
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-13 preliminary pwm channel has the capability of selecting one of two clocks, either the prescaled clock (clock a or b) or the scaled clock (clock sa or sb). the block diagram in figure 24-14 shows the four different clocks and how the scaled clocks are created. figure 24-14. pwm clock select block diagram 24.3.1.1 prescaled clock (a or b) the internal bus clock is the input clock to the pwm prescaler which can be disabled when the device is in debug mode by setting the pwmctl[pfrz] bit. this is useful for reducing power consumption and for emulation in order to freeze the pwm. the input clock is also disabled when all pwm channels are disabled (pwme n =0). internal bus clock (f sys/ ) pwmscla 2 1 0 pclr4 1 0 pclr5 pwmprclk pwmsclb 1 0 pclr2 1 0 pclr3 [pckb] pwmprclk [pcka] clock a clock sa clock clock b clock sb 2 clock to pwm4 clock to pwm5 clock to pwm2 clock to pwm3 1 0 pclr6 1 0 pclr7 clock to pwm6 clock to pwm7 1 0 pclr0 1 0 pclr1 clock to pwm0 clock to pwm1
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-14 freescale semiconductor preliminary clock a and b are scaled values of the input clock. th e value is software selectable for both clock a and b and has options of 1, 1/2, ..., or 1/128 times the internal bus clock. th e value selected for clock a and b are determined by the pwmprclk[pcka n ] and pwmprclk[pckb n ] bits. 24.3.1.2 scaled clock (sa or sb) the scaled a (sa) and scal ed b (sb) clocks use cloc k a and b respectively as i nputs and divide it further with a user programmable value a nd then divide this by 2. the ra tes available for clock sa are programmable to run at clock a divided by 2, 4, ..., or 512. similar rates are available for clock sb. clock sa equals clock a di vided by two times the value in the pwmscla register: eqn. 24-5 similarly, clock sb is generated according to the following equation: eqn. 24-6 as an example, consider the case in which the user writes 0xff into the pwms cla register. clock a for this case is selected to be intern al bus clock divide d by 4. a pulse will occur at a rate of once every 255 4 bus cycles. passing this through the di vide by two circuit pr oduces a clock signal of the internal bus clock divided by 2040. similarly, a value of 0x01 in the pwmscla register when clock a is internal bus clock divided by 4 will produce an internal bus clock divided by 8 rate. writing to pwmscla or pwmsclb causes the a ssociated 8-bit down counter to be re-loaded. otherwise, when changing rates th e counter would have to count down to 0x01 before counting at the proper rate. forcing the associated counter to re-load the scale regist er value every time pwmscla or pwmsclb is written prevents this. writing to the scale registers wh ile channels are operating can cause irregularities in the pwm outputs. 24.3.1.3 clock select each pwm channel has the capability of selecting one of two clocks. fo r channels 0, 1, 4, and 5 the clock choices are clock a or sa. for channels 2, 3, 6 and 7 the choices are clock b or sb. the clock selection is done with the pwmclk[pclk x ] control bits. changing clock control bits while channels are ope rating can cause irregular ities in the pwm outputs. 24.3.2 pwm channel timers the main part of the pwm module is the actual timers. each of the time r channels has a counter, a period register and a duty register (each are 8-bit). the waveform output period is controlled by a match between the period register and the value in the counter. the duty is controlled by a match between the duty register and the counter value and causes th e state of the output to change dur ing the period. the starting polarity of the output is also selectable on a per channel basis. figure 24-15 shows a block diagram for a pwm timer. clock sa clock a 2pwmscla ---------------------------------------- - = clock sb clock b 2pwmsclb ---------------------------------------- =
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-15 preliminary figure 24-15. pwm timer channel block diagram 24.3.2.1 pwm enable each pwm channel has an enable bit (pwme n ) to start its waveform output. when any of the pwme n bits are set (pwme n =1), the associated pwm output signal is enabled immediately. however, the actual pwm waveform is not avai lable on the associated pwm output until it s clock source begins its next cycle due to the synchronization of pwme n and the clock source. an exception to this is when channels are concatenated. refer to section 24.3.2.7, ?pwm 16-bit functions? for more detail. note that the first pwm cycle after enabling the channe l can be irregular. when the channel is disabled (pwme n =0), the counter for the channel does not count. 24.3.2.2 pwm polarity each channel has a polarity bit to al low starting a waveform cycle with a high or low signal. this is shown on the block diagram as a mux select. when one of the bits in the pwmpol register is set, the associated pwm channel output is high at the beginning of the waveform, then goes low when the duty count is reached. conversely, if the polarity bit is zero, the out put starts low and then goe s high when the duty count is reached. 24.3.2.3 pwm period and duty dedicated period and duty registers exist for each cha nnel and are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: ? the effective period ends ? the pwmcnt n register is written (c ounter resets to 0x00) ? the channel is disabled, pwme n =0 in this way, the output of the pwm will always be either the old wave form or the new waveform, not some variation in between. if the channe l is not enabled, then writes to th e period and duty registers will go directly to the latches as well as the buffer. a change in duty or period can be forced into ef fect immediately by writing the new value to the duty and/or period registers and then writ ing to the counter. this forces the counter to reset and the new duty pwmcnt n pwmdty n pwmper n up /down reset pwmcae = 1 pwmcae = 0 clock source from figure 24-14 ppol n 0 1 pwmout n pwme n
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-16 freescale semiconductor preliminary and/or period values to be latched. in addition, since the counter is read able it is possible to know where the count is with respect to the duty value a nd software can be used to make adjustments . when forcing a new period or duty into effect immediat ely, an irregular pwm cycle can occur. depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. 24.3.2.4 pwm timer counters each channel has a dedicated 8-bit up/ down counter which runs at the rate of the selected clock source (see figure 24-14 for the available clock sources and rates). th e counter compares to two registers, a duty register and a period re gister as shown in figure 24-15 . when the pwm counter ma tches the duty register the output flip-flop changes state cau sing the pwm waveform to also ch ange state. a match between the pwm counter and the period register behaves differently depending on wh at output mode is selected as shown in figure 24-15 and described in section 24.3.2.5, ?left-aligned outputs? and section 24.3.2.6, ?center-aligned outputs.? each channel counter can be read at anytime wit hout affecting the count or the operation of the pwm channel. any value written to the counter causes the counter to reset to 0x00, the counter direction to be set to up, the immediate load of both duty and pe riod registers with valu es from the buffers, a nd the output to change according to the polarity bit. when the channel is disabled (pwme n = 0), the counter stops. when a channel becomes enabled (pwme n = 1), the associated pwm counter continues from the count in the pwmcnt n register. this allows the waveform to cont inue where it left off when the channel is re-enabled. when the channel is disa bled, writing ?0? to the period regist er will cause the counter to reset on the next selected clock. note if the user wants to start a new ?clean? pwm waveform without any ?history? from the old waveform, the user must write to channel counter (pwmcnt n ) prior to enabling the pwm channel (pwme n =1). generally, writes to the counter are done prior to en abling a channel in order to start from a known state. however, writing a counter can also be done while th e pwm channel is enabled (c ounting). the effect is similar to writing the counter when the channel is disabled except that the new period is started immediately with the output set accord ing to the polarity bit. writing to the counter while the channel is enabled can cause an irregular pwm cycle to occur. the counter is cleared at the en d of the effective period (see section 24.3.2.5, ?left-aligned outputs ? and section 24.3.2.6, ?center-aligned outputs? for more details). table 24-14. pwm timer counter conditions counter clears (0x00) counter counts counter stops when pwmcnt n register written to any value when pwm channel is enabled (pwme n = 1). counts from last value in pwmcnt n . when pwm channel is disabled (pwme n =0) effective period ends
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-17 preliminary 24.3.2.5 left-aligned outputs the pwm timer provides the choice of two types of outputs, left- or center-aligned outputs. they are selected with the pwmcae[cae n ] bits. if the cae n bit is cleared, the co rresponding pwm output will be left-aligned. in left-aligned output mode, the 8-bit counter is configured as an up counter only. it compares to two registers, a duty register and a period regi ster as shown in the block diagram in figure 24-15 . when the pwm counter matches the duty regist er the output flip-flop changes stat e causing the pwm waveform to also change state. a match between the pwm counter and the period register resets the counter and the output flip-flop as shown in figure 24-15 as well as performing a load from the double buffer period and duty register to the associated registers as described in figure 24.3.2.3 . the counter counts from 0 to the value in the period register minus 1. note changing the pwm output mode from le ft-aligned output to center-aligned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 24-16. pwm left-aligned output waveform to calculate the output frequency in left-aligned output mode for a particular channel, take the selected clock source frequency for the channel (a, b, sa, or sb) and divide it by the value in the period register for that channel. eqn. 24-7 the pwm n duty cycle (high time as a percen tage of period) is expressed as: eqn. 24-8 24.3.2.5.1 left-align ed output example as an example of a left-aligned output, consider the following case: clock source = internal bus clock, wher e internal bus clock = mhz (ns period) ppol n = 0, pwmper n = 4, pwmdty n = 1 pwm n frequency = mhz 4 = mhz pwm n period = ns pwmdty n period = pwmper n ppol n =0 ppol n =1 pwm n frequency clock (a, b, sa, or sb) pwmper n ---------------------------------------------------------- = duty cycle 1 pwmpol ppol n [] pwmdty n pwmper n ------------------------------- ? ? ?? ?? 100% =
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-18 freescale semiconductor preliminary shown below is the output waveform generated: figure 24-17. pwm left-aligned output example waveform 24.3.2.6 center-aligned outputs for center-aligned output mode selection, set the pwmcae[cae n ] bit and the corresponding pwm output will be center-aligned. the 8-bit counter operates as an up/ down counter in this m ode and is set to up whenever the counter is equal to 0x00. the c ounter compares to two register s, a duty register and a peri od register as shown in the block diagram in figure 24-15 . when the pwm counter matches the duty register the output flip-flop changes state causing the pwm waveform to also ch ange state. a match between the pwm counter and the period register changes the counter directio n from an up-count to a down-count. when the pwm counter decrements and matches the duty register again, the output fl ip-flop changes state causing the pwm output to also change state. when the pwm counter decrements and r eaches zero, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated regi sters is performed as described in figure 24.3.2.3 . the counter counts from 0 up to the value in the period register and then back down to 0. thus the effective period is pwmper n 2. changing the pwm output mode from left-aligned output to center-ali gned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 24-18. pwm center-aligned output waveform pwmn duty cycle 1 1 4 -- - ? ?? ?? 100% 75% = = period = ns duty cycle = 75% e=ns ppol n =0 ppol n =1 period = pwmper n 2 pwmdty n pwmper n pwmper n pwmdty n
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-19 preliminary to calculate the output frequency in center-aligned output mode for a particular ch annel, take the selected clock source frequency for the channe l (a, b, sa, or sb) and divide it by twice the value in the period register for that channel. eqn. 24-9 the pwm n duty cycle (high time as a percen tage of period) is expressed as: eqn. 24-10 24.3.2.6.1 center-aligned output example as an example of a center-aligned output, consider the following case: clock source = internal bus clock, wher e internal bus clock= mhz (ns period) ppol n = 0, pwmper n = 4, pwmdty n = 1 pwm n frequency = mhz / (2 4) = mhz pwm n period = ns shown below is the output waveform generated. figure 24-19. pwm center-aligned output example waveform 24.3.2.7 pwm 16-bit functions the pwm timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater pwm resolution. this 16-b it channel option is achieved through the concatena tion of two 8-bit channels. the pwmctl register contains four concatenation control bits, each of which is used to concatenate a pair of pwm channels into one 16-bit channel. cha nnels 0 and 1 are concatenated with the con01 bit, channels 2 and 3 are concatenated with the con23 bit, and so on. change these bits only when both corresponding channels are disabled. as shown in figure 24-20 , when channels 2 and 3 are concatenat ed, channel 2 registers become the high order bytes of the double byte channel. when channe ls 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. when using the 16-bit concatenated mode, the clock s ource is determined by the low order 8-bit channel clock select control bits (the odd numbered channel) . the resulting pwm is out put to the pins of the corresponding low order 8-bit channel as also shown in figure 24-20 . the polarity of the resulting pwm output is controlled by the ppol n bit of the corresponding low order 8-bit channel as well. pwm n frequency clock (a, b, sa, or sb) 2p wmper n ---------------------------------------------------------- = duty cycle 1 pwmpol ppol n [] pwmdty n pwmper n ------------------------------- ? ? ?? ?? 100% = pwmn duty cycle 1 1 4 -- - ? ?? ?? 100% 75% = = duty cycle = 75% e=ns period = ns e=ns
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-20 freescale semiconductor preliminary once concatenated mode is enabled (pwmctl[con nn ] bits set) then enabling/disabling the corresponding 16-bit pwm channel is controlled by the low order pwme n bit. in this case, the high order bytes? pwme n bits have no effect and their corresponding pwm output is disabled. in concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. figure 24-20. pwm 16-bit mode either left- or center-aligned output mode can be used in concatenated mode and is controlled by the low order cae n bit. the high order cae n bit has no effect. the table shown below is used to summarize which channels are used to set the various control bits when in 16-bit mode. table 24-15. 16-bit concatenation mode summary con nn pwme n ppol n pclk n cae n pwm n output con67 pwm7 ppol7 pclk7 cae7 pwmout7 con45 pwm5 ppol5 pclk5 cae5 pwmout5 con23 pwme3 ppol3 pclk3 cae3 pwmout3 con01 pwme1 ppol1 pclk1 cae1 pwmout1 pwmcnt4 pwmout5 high low period/duty compare pwmcnt5 clock source 5 pwmcnt2 pwmout3 high low period/duty compare pwmcnt3 clock source 3 pwmcnt0 pwmout1 high low period/duty compare pwmcnt1 clock source 1 pwmcnt6 pwmout7 high low period/duty compare pwmcnt7 clock source 7
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 freescale semiconductor 24-21 preliminary 24.3.2.8 pwm boundary cases the following table summarizes the boundary conditions for the pwm regardless of the output mode (left- or center-aligned) and 8-bit (nor mal) or 16-bit (concatenation): table 24-16. pwm boundary cases pwmdty n pwmper n ppol n pwm n output 0x00 (indicates no duty) >0x00 1 always low 0x00 (indicates no duty) >0x00 0 always high xx 0x00 1 (indicates no period) 1 counter = 0x00 and does not count. 1 always high xx 0x00 1 (indicates no period) 0always low pwmper n xx 1 always high pwmper n xx 0 always low
pulse width modulation (pwm) module mcf5213 reference manual, rev. 1.1 24-22 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-1 preliminary chapter 25 flexcan 25.1 introduction the flexcan is a communication controller implemen ting the controller area network (can) protocol, an asynchronous communi cations protocol used in automotive and industrial control syst ems. it is a high speed (1 mbps), short distance, prio rity based protocol that can comm unicate using a variety of mediums (for example, fiber optic cable or an unshielded twisted pair of wi res). the flexcan supports both the standard and extended identifier (i d) message formats specified in the can protocol specification, revision 2.0, part b. the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this fi eld: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness, and required bandwidth. a ge neral working knowledge of the can protocol revision 2.0 is assumed in this docu ment. for details, refer to the ca n protocol revision 2.0 specification. 25.1.1 block diagram a block diagram describing th e various submodules of the flexcan module is shown in figure 25-1 . each submodule is described in detail in subsequent sections. the message buffer architecture is shown in figure 25-2 . figure 25-1. flexcan block diagram and pinout ? ? mb3 mb2 mb1 mb0 clocks, address and data buses, can protocol interface message buffer management can n tx can n rx bus interface unit max mb # internal bus interface interrupt and test signals flexcan ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mb mb [0:]
flexcan mcf5213 reference manual, rev. 1.1 25-2 freescale semiconductor preliminary figure 25-2. flexcan message buffer architecture 25.1.1.1 the can system a typical can system is shown below in figure 25-3 . figure 25-3. typical can system each can station is connected physi cally to the can bus through a tran sceiver. the tran sceiver provides the transmit drive, waveshaping, and receive/com pare functions required for communicating on the can bus. it can also provide protecti on against damage to the flexcan caused by a defective can bus or defective stations. data buffer 0 buffer 14 id time stamp data length data buffer 15 ? ? ? ? ? ? ? ? mask 15 mask 14 transparent to user rx shifter tx shifter serial buffers tx rx control global mask interrupt request data ? ? ? ? ? ? transmit/receive message buffers buffer can bus flexcan can n rx transceiver can station 1 can station 2 can n tx coldfire processor can station n
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-3 preliminary 25.1.2 features following are the main feat ures of the flexcan module: ? full implementation of the can pr otocol specification version 2.0b ? standard data and remote fr ames (up to 109 bits long) ? extended data and remote fr ames (up to 127 bits long) ? 0?8 bytes data length ? programmable bit rate up to 1 mbps ? content-related addressing ? up to flexible message buffers of zero to eight bytes data length, each configurable as rx or tx, all supporting standard and extended messages ? listen-only mode capability ? three programmable mask regist ers: global (for mbs 0?13), sp ecial for mb14, and special for mb15 ? programmable transmission priority scheme: lowest id or lowest buffer number ? time stamp based on 16-bit free-running timer ? global network time, synchr onized by a specific message ? programmable i/o modes ? maskable interrupts ? independent of the transm ission medium (an external transceiver is assumed) ? open network architecture ? multimaster bus ? high immunity to emi ? short latency time due to an arbitration scheme for high-priority messages 25.1.3 modes of operation 25.1.3.1 normal mode in normal mode, the module operates receiving and/or transmitting message frames, errors are handled normally, and all the can protocol functions are enabled. user and supe rvisor modes differ in the access to some restricted control registers. 25.1.3.2 freeze mode freeze mode is entered by: ? setting canmcr n [frz], and ? setting canmcr n [halt], or by asserting the bkpt signal. once entry into freeze mode is reque sted, the flexcan waits until an in termission or idle condition exists on the can bus, or until the flexcan enters the erro r passive or bus off state. once one of these
flexcan mcf5213 reference manual, rev. 1.1 25-4 freescale semiconductor preliminary conditions exists, the flexcan waits for the completio n of all internal activit y such as arbitration, matching, move-in, and move-out. when this happens, the following events occur: ? the flexcan stops tran smitting/receiving frames. ? the prescaler is disabled, thus halting all can bus communication. ? the flexcan ignores its rx pins an d drives its tx pins as recessive. ? the flexcan loses synchronization with the can bus and the notrdy and frzack bits in canmcr n are set. ? the cpu is allowed to read and write the e rror counter registers (in other modes they are read-only). after engaging one of the mechanisms to place the flexcan in freeze mode, the user must wait for the frzack bit to be set before accessing any other registers in the flexcan, otherwise unpredictable operation may occur. in freeze mode, all me mory mapped registers are accessible. to exit freeze mode, the bkpt line must be negated or the halt bit in canmcr n must be cleared. once freeze mode is exited, the flexca n will resynchronize with the can bus by waiting for 11 consecutive recessive bits before beginning to participate in can bus communication. 25.1.3.3 module disabled mode this mode disables the flexcan modul e; it is entered by setting canmcr n [mdis]. if the module is disabled during freeze mode, it shuts down the system clocks, sets the lpmack bit, and clears the frzack bit. if the module is disabled during transmissi on or reception, flexca n does the following: ? waits to be in either idle or bus-off state, or else waits for th e third bit of intermission and then checks it to be recessive ? waits for all internal activities such as ar bitration, matching, move-in, and move-out to finish ? ignores its rx input pin and dr ives its tx pin as recessive ? shuts down the system clocks the bus interface unit conti nues to operate, enabling the cpu to ac cess memory mapped registers, except the free-running timer, the error count er register and the message buffe rs, which cannot be accessed when the module is disabled. exiting from this mode is done by negating the mdis bit, which will resume the clocks and negate the lpmack bit. 25.1.3.4 loop-back mode the module enters this mode when the lpb bit in th e control register is set. in this mode, flexcan performs an internal loop back that can be used fo r self test operation. the bit stream output of the transmitter is internally fed back to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic 1). flexcan behaves as it normally does when transmitting and treats its own transmitted messag e as a message received from a re mote node. in this mode, flexcan ignores the bit sent duri ng the ack slot in the can frame acknowle dge field to ensure proper reception of its own message. both transmit and receive interrupts are generated.
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-5 preliminary 25.1.3.5 listen-only mode in listen-only mode, transmission is disabled, all error counters are fr ozen and the module operates in a can error passive mode. only me ssages acknowledged by another c an station will be received. if flexcan detects a message that ha s not been acknowledged it will fl ag a bit0 error (without changing the rec), as if it was trying to acknowledge the me ssage. because the module does not influence the can bus in this mode, the device is capable of functioning like a monitor or for auto matic bit-rate detection. 25.2 external signal description each flexcan module has two i/o signals connected to the external mpu pins: can0tx, can0rx, can1tx, and can1rx. can n tx transmits serial data to th e can bus transceiver, while can n rx receives serial data from the can bus transceiver. 25.3 memory map/register definition the flexcan module address space is sp lit into 128 bytes starting at the base address, and then an extra bytes starting at the base addre ss +128. the upper are fully used for the message buffer structures, as described in section 25.3.9, ?message buffer structure.? out of the lower 128 bytes , only part is occupied by various registers. table 25-1. flexcan memory map offset register affected by hard reset affected by soft reset access reset value section/page flexcan supervisor-only access registers 0x1c_000 0 flexcan module configuration register (canmcr) y y r/w 0xd890_000f 25.3.1/25-6 supervisor/user access registers 0x1c_000 4 flexcan control register (canctrl) y n r/w 0x0000_0000 25.3.2/25-8 0x1c_000 8 free running timer (timer) y y r/w 0x0000_0000 25.3.3/25-10 0xc_0010 rx global mask (rxgm ask) y n r/w 0x1fff_ffff 25.3.4/25-11 0x1c_001 4 rx buffer 14 mask (rx14mask) y n r/w 0x1fff_ffff 25.3.4/25-11 0x1c_001 8 rx buffer 15 mask (rx15mask) y n r/w 0x1fff_ffff 25.3.4/25-11 0x1c_001 c error counter register (errcnt) y y r/w 0x0000_0000 25.3.6/25-14 0x1c_002 0 error and status register (errstat) y y r/w 0x0000_0000 25.3.6/25-14
flexcan mcf5213 reference manual, rev. 1.1 25-6 freescale semiconductor preliminary note the flexcan has no hard-wired prot ection against invalid bit/field programming within its regi sters. specifically, no pr otection is provided if the programming does not meet can protocol requirements. programming the flexcan control regi sters is typically done during syst em initialization, prior to the flexcan becoming synchronized with the can bus. th e configuration registers can be changed after synchronization by halting the fl excan module. this is done wh en the user sets the canmcr n [halt] bit. the flexcan responds by setting the canmcr n [notrdy] bit. 25.3.1 flexcan configuration register (canmcr n ) canmcr n defines global system configurations, such as the module operation mode and maximum message buffer configuration. most of the fields in this register can be accessed at any time, except the maxmb field, which should only be change d while the module is in freeze mode. 0x1c_002 8 interrupt mask register (imask) y y r/w 0x0000_0000 25.3.7/25-15 0x1c_003 0 interrupt flag register (iflag) y y r/w 0x0000_0000 25.3.8/25-16 0x1c_008 0 message buffers 0?15 (mb0?15) n n r/w 25.3.9/25-16 ipsbar offset: 0x1c_0000 (canmcr0) access: supervisor read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r mdis frz 0 halt not rdy 0 soft rst frz ack supv 00 lpm ack 0 000 w reset110110001 0 0100 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset000000000 0 0 11 1 1 figure 25-4. flexcan configur ation register (canmcr n ) table 25-1. flexcan memory map (continued) offset register affected by hard reset affected by soft reset access reset value section/page flexcan
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-7 preliminary table 25-2. canmcr n field descriptions field description 31 mdis module disable. this bit controls whether flexcan is enabled or not. when disabled, flexcan shuts down the flexcan clocks that drive the can interface and message buffer sub-module. this is the only bit in canmcr n not affected by soft reset. see section 25.1.3.3, ?module disabled mode,? for more information. 0 enable the flexcan module, clocks enabled 1 disable the flexcan module, clocks disabled 30 frz freeze mode enable. when set, the flexcan can enter freeze mode when the bkpt line is asserted or the halt bit is set. clearing this bit causes the flexcan to exit freeze mode. refer to section 25.1.3.2, ?freeze mode,? for more information. 0 flexcan ignores the bkpt signal and the canmcr n [halt] bit. 1 flexcan module enabled to enter debug mode. 29 reserved, should be cleared. 28 halt halt flexcan. setting this bit puts the flexcan module into freeze mode. it has the same effect as assertion of the bkpt signal. this bit is set after reset and should be cleared after initializing the message buffers and control registers. flexcan message buffer receive and transmit func tions are inactive until this bit is cleared. while in freeze mode, the cpu has write access to the error counte r register (errcnt n ), that is otherwise read-only. 0 the flexcan operates normally 1 flexcan enters freeze mode if frz = 1 27 notrdy flexcan not ready. this bit indicates that the flexcan is eith er in disable or freeze mode. this bit is read-only and it is cleared once the flexcan exits these modes. 0 flexcan is either in normal mode, listen-only mode, or loop-back mode. h1flexcan is in disable or freeze mode. 26 reserved, should be cleared. 25 softrst soft reset. when set, the flexcan resets its internal state machines (sequencer, error counters, error flags, and timer) and the host interface registers (canmcr n [except the mdis bit], timer, errcnt, errstat, imask, and iflag). the configuration registers that control the interface with the can bus are not changed (canctrl n , rxgmask n , rx14mask n , rx15mask n ). message buffers are also not changed. this allows softrst to be used as a debug feature while the system is running. since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. the softrst bit remains set while reset is pending and is automatically cleared when reset completes. the user s hould poll this bit to know when the soft reset has completed. 0 soft reset cycl e completed 1 soft reset cycle initiated 24 frzack freeze acknowledge. indicates that the flexcan module has entered freeze mode. the user should poll this bit after freeze mode has been requested, to know when the module has actually entered freeze mode. when freeze mode is exited, this bit is cleared once the flexcan prescaler is enabled. this is a read-only bit. 0 the flexcan has exited freeze mode and the prescaler is enabled. 1 the flexcan has entered freeze mode, and the prescaler is disabled. 23 supv supervisor/user data space. places the flexcan registers in either supervisor or user data space. 0 registers with access controlled by the supv bit are accessi ble in either user or supervisor privilege mode. 1 registers with access controlled by the supv bit are restricted to supervisor mode. 22?21 reserved, should be cleared.
flexcan mcf5213 reference manual, rev. 1.1 25-8 freescale semiconductor preliminary 25.3.2 flexcan contro l register (canctrl n ) canctrl n is defined for specific flexcan control featur es related to the can bus, such as bit-rate, programmable sampling point within an rx bit, loop back mode, listen-only mode, bus off recovery behavior, and interrupt enabling. it al so determines the divisi on factor for the clock pr escaler. most of the fields in this register should only be changed while the module is disa bled or in freez e mode. exceptions are the boffmsk, errmsk, and boffrec bits which can be accessed at any time. 20 lpmack low power mode acknowledge. indicates that flexcan is disabled. disabled mode cannot be entered until all current transmission or reception processes have finished , so the cpu can poll the lpmack bit to know when the flexcan has actually entered low power mode. see section 25.1.3.3, ?module disabled mode,? for more information. this bit is read-only. 0 flexcan not disabled. 1 flexcan is in disabled mode. 19? reserved, should be cleared. ?0 maxmb maximum number of message buffers. defines the maximum number of message buffers that will take part in the matching and arbitration process. the reset value (0xf) is equivalent to message buffer (mb) configuration. this field should be changed only while the module is in freeze mode. note: ipsbar offset: 0x1c_0004 (canctrl0) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r presdiv rjw pseg1 pseg2 w reset000000000 0 0000 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r boff msk err msk clk_ src lpb 0000 smp boff rec tsyn lbuf lom propseg w reset000000000 0 0000 0 0 figure 25-5. flexcan cont rol register (canctrl n ) table 25-2. canmcr n field descriptions (continued) field description maximum mbs in use = maxmb + 1
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-9 preliminary table 25-3. canctrl n field descriptions field description 31?24 presdiv prescaler division factor. defines the ratio between the cloc k source frequency (set by clk_src bit) and the serial clock (s clock) frequency. the s clock period defines the time quantum of the can prot ocol. for the reset value, the s clock frequency is equal to the clock source frequency. the maximum value of this register is 0xff, that gives a minimum s clock frequency equal to the clock source frequency divided by 256. for more information refer to section 25.4.8, ?bit timing .? eqn. 25-1 eqn. 25-2 23?22 rjw resynchronization jump width. defines the maximum number of time quanta (one time quantum is equal to the s clock period) that a bit time can be changed by one resynchronization. the valid programmable values are 0 ? 3. 21?19 pseg1 phase buffer segment 1. defines the length of phase buff er segment 1 in the bit time. the valid programmable values are 0 ? 7. 18?16 pseg2 phase buffer segment 2. defines the length of phase buff er segment 2 in the bit time. the valid programmable values are 1 ? 7. 15 boffmsk bus off interrupt mask. 0 bus off interrupt disabled 1 bus off interrupt enabled 14 errmsk error interrupt mask. 0 error interrupt disabled 1 error interrupt enabled 13 clk_src clock source. selects the clock source for the can interfac e to be fed to the prescalar. this bit should only be changed while the module is disabled. 0 clock source is extal 1 clock source is the internal bus clock, f sys/2 12 lpb loop back. configures flexcan to operate in loop-back mode. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is fed back internally to the receiver input. the rx can input pin is ignored and t he tx can output goes to the recessive state (logic 1). flexcan behaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignor es the bit sent during the ack slot in the can frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. both transmit and receive interrupts are generated. 0 loop back disabled 1 loop back enabled 11?8 reserved, should be cleared. 7 smp sampling mode. determines whether the flexcan module will sample each received bit one time or three times to determine its value. 0 one sample, taken at the end of phase buffer segment 1, is used to determine the value of the received bit. 1 three samples are used to determine the value of the received bit. the samples are taken at the normal sample point and at the two preceding periods of the s-clock; a majority rule is used. s clock frequency f sys/2 or extal presdiv + 1 ------------------------------------------ = resync jump width = (rjw + 1) time quanta phase buffer segment 1 ( pseg1 + 1) time quanta = phase buffer segment 2 (pseg 2 + 1) time quanta =
flexcan mcf5213 reference manual, rev. 1.1 25-10 freescale semiconductor preliminary 25.3.3 flexcan free runnin g timer register (timer n ) this register represents a 16-bit free running counter that can be r ead and written to by the cpu. the timer starts from 0x0000 after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the flex can bit-clock (which de fines the baud rate on the can bus). during a message transmission/recepti on, it increments by one for each bit that is received or transmitted. when there is no message on the bus, it counts using the pr eviously programmed baud ra te. during freeze mode, the timer is not incremented. the timer value is captured at the be ginning of the identifier (id) field of any frame on the can bus. this captured value is written into the timestamp entry in a message buffer after a successful reception or transmission of a message. writing to the timer is an indirect operation. the data is first written to an auxili ary register and then an internal request/acknowledge procedur e across clock domains is executed. all this is transparent to the 6 boffrec bus off recovery mode. defines how flexcan recovers from bu s off state. if this bit is cleared, automatic recovering from bus off state occurs according to the can specification 2.0b . if the bit is set, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is cleared by the user. if the bit is cleared before 128 sequences of 11 recessive bits are detected on the can bus, then bus off recovery happens as if the boffrec bit had never been set. if the bit is cleared after 128 sequences of 11 recessive bits occurred, then flexcan will re-synchronize to the bus by waiting for 11 recessive bits before joining the bus. after clearing, the boffrec bit can be set again during bus off, but it will only be effective the next time the module enters bus off. if boffrec was cleared when the module entered bus off, setting it during bus off will not be effective for the current bus off recovery. 0 automatic recovering from bus off stat e enabled, according to can spec 2.0b 1 automatic recovering from bus off state disabled 5 tsyn timer synchronize mode. enables the mechanism that resets the free-running timer each time a message is received in message buffer 0. this feature provides t he means to synchronize multiple flexcan stations with a special ?sync? message (global network time). 0 timer synchronization disabled. 1 timer synchronization enabled. note: there can be a bit clock skew of four to five co unts between different flexcan modules that are using this feature on the same network. 4 lbuf lowest buffer transmitted first. defines the ordering mechanism for message buffer transmission. 0 message buffer with lowest id is transmitted first 1 lowest numbered buffer is transmitted first 3 lom listen-only mode. configures flexcan to operate in listen -only mode. in this mode transmission is disabled, all error counters are frozen, and the modul e operates in a can error passive mode. only messages acknowledged by another can station will be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. 0 flexcan module is in normal active operation; listen-only mode is deactivated 1 flexcan module is in listen-only mode operation 2?0 propseg propagation segment. defines the le ngth of the propagation segment in t he bit time. the valid programmable values are 0 ? 7. note: a time-quantum = 1 s clock period. table 25-3. canctrl n field descriptions (continued) field description propagation segmen t time (propseg + 1) time-quanta =
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-11 preliminary user, except for the fact that the da ta will take some time to be actuall y written to the register. if desired, software can poll the register to discove r when the data was actually written. 25.3.4 rx mask registers (rxgmask n , rx14mask n , rx15mask n ) these registers are used as acceptance masks for r eceived frame ids. three ma sks are defined: a global mask (rxgmask n ) used for rx buffers 0?13 and two sepa rate masks for buffers 14 (rx14mask n ) and 15 (rx15mask n ). the meaning of each mask bit is the following: mi n bit = 0: the corresponding incoming id bit is ?don?t care?. mi n bit = 1: the corresponding id bit is checked agains t the incoming id bit, to see if a match exists. note that these masks are used both for standard and extende d id formats. the value of the mask registers should not be changed while in normal operation (only while in freeze mode), as locked frames that matched a message buffer (mb) through a mask may be transferred into the mb (upon release) but may no longer match. ipsbar offset: 0x1c_0008 (timer0) access: user read/write 313029282726252423222120191817161514131211109876543210 r 0 0 0 0 0 00000000 0 0 0 timer w reset00000000000000000000000000000000 figure 25-6. flexcan ti mer register (timer n ) table 25-4. timer n field descriptions field description 31?16 reserved, should be cleared. 15?0 timer free running timer. captured at the beginning of the identif ier (id) field of any frame on the can bus. this captured value is written into the timestamp entry in a message bu ffer after a successful reception or transmission of a message. table 25-5. mask examples for normal/extended messages base id id28.................id18 ide extended id id17......................................id0 match mb2-id 1 1 1 1 1 1 1 1 0 0 0 0 mb3-id 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mb4-id 0 0 0 0 0 0 1 1 1 1 1 0 mb5-id 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mb14-id 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 rx_global_mask 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 rx_msg in 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mb3 1 rx_msg in 2 1 1 1 1 1 1 1 1 0 0 1 0 mb2 2
flexcan mcf5213 reference manual, rev. 1.1 25-12 freescale semiconductor preliminary 25.3.5 flexcan error coun ter register (errcnt n ) this register has two 8-bit fields reflecting the value of tw o flexcan error counters: transmit error counter (txectr) and receive error counter (rxectr). the rules for increas ing and decreasing these counters are described in the can protocol and are comple tely implemented in the flexcan module. both counters are read-only except in freeze mode, where they can be written by the cpu. rx_msg in 3 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 3 rx_msg in 4 0 1 1 1 1 1 1 1 0 0 0 0 4 rx_msg in 5 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mb14 5 rx14mask 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 rx_msg in 6 1 0 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6 rx_msg in 7 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mb14 7 1 match for extended format (mb3). 2 match for normal format. (mb2). 3 mismatch for mb3 because of id0. 4 mismatch for mb2 because of id28. 5 mismatch for mb3 because of id28 , match for mb14 (uses rx14mask n ). 6 mismatch for mb14 because of id27 (uses rx14mask n ). 7 match for mb14 (uses rx14mask n ). offset: 0x1c_0010 (rxgmask0) 0x1c_0014 (rx14mask0) 0x1c_0018 (rx15mask0) access: user read/write 313029282726252423222120191817161514131211109876543210 r 0 0 0 mi standard id mi extended id w reset00011111111111111111111111111111 figure 25-7. flexcan rx mask registers (rxgmask n , rx14mask n , rx15mask n ) table 25-6. rx xx mask n field descriptions field description 31?29 reserved, should be cleared. 28?18 mi28?18 standard id mask bits. these bits are the same mask bits for the standard and extended formats. 17?0 mi17?0 extended id mask bits. these bits are used to mask comparison only in extended format. table 25-5. mask examples for normal/extended messages (continued) base id id28.................id18 ide extended id id17......................................id0 match
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-13 preliminary writing to the errcnt n register while in fr eeze mode is an indirect operation. the data is first written to an auxiliary register and then an internal re quest/acknowledge procedure across clock domains is executed. all this is transparent to the user, except for the fact that the data will take some time to be actually written to the register. if desired, software can poll the regist er to discover when the data was actually written. flexcan responds to any bus state as described in the protocol, e.g. transmit error-activ e or error-passive flag, delay its transmission start time (error-passive), and avoid any influence on the bus when in bus off state. the following are the basic rule s for flexcan bus state transitions. ? if the value of txectr or rxec tr increases to be greater than or equal to 128, the fltconf field in the error and status register (errstat n ) is updated to reflect error-passive state. ? if the flexcan state is error-pa ssive, and either txec tr or rxectr decrem ents to a value less than or equal to 127 while the other alre ady satisfies this condition, the errstat n [fltconf] field is updated to reflect error-active state. ? if the value of txectr increases to be greater than 255, the errstat n [fltconf] field is updated to reflect bus off state, a nd an interrupt may be issued. the value of txectr is then reset to zero. ? if flexcan is in bus off state, then txectr is cascaded together with another inte rnal counter to count the 128th occurrences of 11 consecutive rece ssive bits on the bus. hence, txectr is reset to zero and counts in a manner where the internal counter counts 11 such bits and then wraps around while incrementing the txectr. when txectr reaches the value of 128, the errstat n [fltconf] field is updated to be error-active and both erro r counters are reset to zero. at any instance of dominant bit fo llowing a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zer o without affecting the txectr value. ? if during system start- up, only one node is operating, then its txectr increases in each message it is trying to transmit, as a result of acknowledge erro rs (indicated by the errstat n [ackerr] bit). after the transition to error-passive stat e, the txectr does not increment anymore by acknowledge errors. therefore the devi ce never goes to the bus off state. ? if the rxectr increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. at the next successful message reception, the counter is set to a value between 119 and 127 to resume to error-active state. ipsbar offset: 0x1c_001c (errcnt0) access: user read/write 313029282726252423222120191817161514131211109876543210 r 0 0 0 0 0 00000000 0 0 0 rxectr txectr w reset00000000000000000000000000000000 figure 25-8. flexcan error counter register (errcnt n )
flexcan mcf5213 reference manual, rev. 1.1 25-14 freescale semiconductor preliminary 25.3.6 flexcan error and st atus register (errstat n ) errstat n reflects various error conditions, some general status of the devi ce, and is the source of three interrupts to the cpu. the reported er ror conditions (bits 15:10) are those occurred since the last time the cpu read this register. the read action cl ears bits 15-10. bits 9?3 are status bits. most bits in this register are r ead only, except for boffint, waki nt, and errint, which are interrupt flags that can be cleared by writing 1 to them. writing 0 has no effect. refer to section 25.5.1, ?interrupts.? table 25-7. errcnt n field descriptions field description 31?16 reserved, should be cleared. 15?8 rxectr receive error counter. indicates current number of receive errors. 7?0 txectr transmit error counter. indicates current number of transmit errors. ipsbar offset: 0x1c_0020 (canctrl0) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0000 0 00 0 000 w reset000000000 0 0000 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bit1 err bit0 err ack err crc err frm err stf err tx wrn rx wrn idle txrx flt conf 0 boff int err int 0 w reset000000000 0 0000 0 0 figure 25-9. flexcan error and status register (errstat n ) table 25-8. errstat n field descriptions field description 31?16 reserved, should be cleared. 15 bit1err bit1 error. indicates inconsistency between the transmitted and received bit in a message. 0 no transmit bit error 1 at least one bit sent as recessive was received as dominant note: the transmit bit error field is not modified during the ar bitration field or the ack slot bit time of a message, or by a transmitter that detects dominant bits while sending a passive error frame. 14 bit0err bit0 error. indicates inconsistency between the transmitted and received bit in a message. 0 no transmit bit error 1 at least one bit sent as dominant was received as recessive 13 ackerr acknowledge error. indicates whether an acknowledgment has been correctly received for a transmitted message. 0 no ack error was detected since the last read of this register. 1 an ack error was detected since the last read of this register.
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-15 preliminary 25.3.7 interrupt mask register (imask n ) imask n contains one interrupt mask bit per buffer. it enables the cpu to determine which buffer will generate an interrupt after a suc cessful transmission/reception (tha t is, when the corresponding iflag n bit is set). 12 crcerr cyclic redundancy check error. indicates whether or not a crc error has been detected by the receiver. 0 no crc error was detected since the last read of this register. 1 a crc error was detected since the last read of this register. 11 frmerr message form error. 0 no form error was detected since t he last read of this register. 1 a form error was detected since the last read of this register. 10 stferr bit stuff error. 0 no bit stuffing error was detected sinc e the last read of this register. 1 a bit stuffing error was detected since the last read of this register. 9 txwrn transmit error status flag. reflects the st atus of the flexcan transmit error counter. 0 transmit error counter < 96 1 txerrcounter 96 8 rxwrn receiver error status flag. reflects the st atus of the flexcan receive error counter. 0 receive error counter < 96 1 rxerrcounter 96 7 idle idle status. indicates when ther e is activity on the can bus. 0 the can bus is not idle. 1 the can bus is idle. 6 txrx transmit/receive status. indicates when the flexcan modul e is transmitting or receiving a message. txrx has no meaning when idle = 1. 0 the flexcan is receiving a message if idle = 0. 1 the flexcan is transmitting a message if idle = 0. 5?4 fltconf fault confinement state. indicates the confinement state of the flexca n module, as shown below. if the canctrl n [lom] bit is set, fltconf will indica te error-passive. since the canctrl n register is not affected by soft reset, the fltconf field will not be affe cted by soft reset if the lom bit is set. 00 error active 01 error passive 1x bus off 3 reserved, should be cleared. 2 boffint bus off interrupt. used to request an interrupt when the fl excan enters the bus off state. the user must write a 1 to clear this bit. writing 0 has no effect. 0 no bus off interrupt requested. 1 this bit is set when the flexcan stat e changes to bus off. if the canctrl n [boffmsk] bit is set an interrupt request is generated. this interrupt is not requested after reset. 1 errint error interrupt. indicates that at least one of the errstat n [15:10] bits is set. the user must write a 1 to clear this bit. writing 0 has no effect. 0 no error interrupt request. 1 at least one of the error bits is set. if the canctrl n [errmsk] bit is set, an interrupt request is generated. 0 reserved, should be cleared. table 25-8. errstat n field descriptions (continued) field description
flexcan mcf5213 reference manual, rev. 1.1 25-16 freescale semiconductor preliminary 25.3.8 interrupt flag register (iflag n ) iflag n contains one interrupt flag bi t per buffer. each successful transmission/reception sets the corresponding iflag n bit and, if the corresponding imask n bit is set, will ge nerate an interrupt. the interrupt flag is cleared by writ ing a 1, while writing 0 has no effect. 25.3.9 message buffer structure the message buffer memory map starts at an offs et of 0x80 from the flexca n?s base address (can0: 0x1c_0000. the -byte message buffer space is full y used by the message buffer structures. each message buffer consists of a control and status fiel d that configures the message buffer, an identifier field for frame identification, a nd up to eight bytes of data. ipsbar offset: 0x1c_002a (imask0) access: user read/write 313029282726252423222120191817161514131211109876543210 reset00000000000000000000000000000000 figure 25-10. flexcan interru pt mask register (imask n ) table 25-9. imask n field descriptions field description ?0 buf n m buffer interrupt mask. enables the respective flexcan message buffer (mb0 to mb) interrupt. these bits allow the cpu to designate which buffers will generate inte rrupts after successful transmission/reception. 0 the interrupt for the corresponding buffer is disabled. 1 the interrupt for the corresponding buffer is enabled. note: setting or clearing an imask n bit can assert or negate an interrupt request, if the corresponding iflag n bit it is set. ipsbar offset: 0x1c_0030 (iflag0) access: user read/write 313029282726252423222120191817161514131211109876543210 reset00000000000000000000000000000000 figure 25-11. flexcan interrupt flags register (iflag n ) table 25-10. iflag n field descriptions field description ?0 buf n i buffer interrupt flag. indicates a su ccessful transmission/reception for the corresponding message buffer. if the corresponding imask n bit is set, an interrupt request will be generated. the user must write a 1 to clear an interrupt flag; writing 0 has no effect. 0 no such occurrence. 1 the corresponding buffer has successful ly completed transmission or reception.
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-17 preliminary figure 25-12. flexcan message buffer memory map the message buffer structure used by the flexcan module is shown in figure 25-13 . both standard and extended frames used in the can specification version 2.0, part b are represented. a standard frame is represented by the 11-bit standard identifier, and an extended frame is represente d by the combined 29-bits of the standard identifier (11 bits) and the extended identifier (18 bits). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0 code srr ide rtr length time stamp 0x4 standard id[28:18] extended id[17:0] 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 figure 25-13. message buffer structure for both extended and standard frames control/status 8 byte data fields 0x80 0x84 0x88 message buffer 0 message buffer 1 message buffer 2 0x8f 0x90 0xa0 0x9f 0xaf 0xb0 flexcan base address offset message buffer 3 identifier message buffer message buffer 0x17f 0x170 0x16f
flexcan mcf5213 reference manual, rev. 1.1 25-18 freescale semiconductor preliminary table 25-11. message buffer field descriptions field description 31?28 reserved, should be cleared. 27?24 code message buffer code. can be accessed (read or write) by the cpu and by the flexcan module itself, as part of the message buffer matching and arbitration process. the encoding is shown in ta b l e 2 5 - 1 2 and table 25-13 . see section 25.4, ?functional overview,? for additional information. 23 reserved, should be cleared. 22 srr substitute remote request. fixed recessive bit, used onl y in extended format. it must be set by the user for transmission (tx buffers) and will be stored with the value received on the can bus for rx receiving buffers. it can be received as either recessive or dominant. if flexcan re ceives this bit as dominant, then it is interpreted as arbitration loss. 0 dominant is not a valid value for transmission in extended format frames 1 recessive value is compulsory for transmission in extended format frames 21 ide id extended bit. identifies whether the frame format is standard or extended. 0 standard frame format 1 extended frame format 20 rtr remote transmission request. used for requesting transmissi ons of a data frame. if flexcan transmits this bit as 1 (recessive) and receives it as 0 (dominant), it is interp reted as arbitration loss. if this bit is transmitted as 0 (dominant), then if it is received as 1 (recessive), the flex can module treats it as bit error. if the value received matches the value transmitted, it is considered as a successful bit transmission. 0 indicates the current mb has a data frame to be transmitted 1 indicates the current mb has a remote frame to be transmitted 19?16 length length of data in bytes. indicates the length (in bytes) of t he rx or tx data; data is located in offset 0x8 through 0xf of the mb space (see figure 25-13 ). in reception, this field is written by the flexcan module, copied from the dlc (data length code) field of the received frame. dlc is defined by the can specification and refers to the data length of the actual frame before it is copied into the me ssage buffer. in transmission, this field is written by the cpu and is used as the dlc field valu e of the frame to be transmitted. when rtr is set, the frame to be tran smitted is a remote frame and will be transmitted without the data field, regardless of the length field. 15?-0 time stamp free-running counter time stamp. stores the value of th e free-running timer which is captured when the beginning of the identifier (id) field appears on the can bus. 31?29 reserved, should be cleared. 28?0 id standard frame identifier: in st andard frame format, only the 11 most signif icant bits (28 to 18) are used for frame identification in both receive and transmit cases. the 18 least significant bits are ignored. extended frame identifier: in extended frame format, all bits (both the 11 bits of the standard frame identifier and the 18 bits of the extended frame identifier) are used for frame identification in both receive and transmit cases. 31?24, 23?16, 15?8, 7?0 data data field. up to eight bytes can be used for a data frame. for rx frames, the data is stor ed as it is received from the can bus. for tx frames, the cpu provides the data to be transmitted within the frame.
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-19 preliminary table 25-12. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment 0000 inactive: mb is not active. ? mb does not participate in the matching process. 0100 empty: mb is active and empty. 0010 mb participates in the matching process. when a frame is received successfully, the code is automatically updated to full. 0010 full: mb is full. 0010 the act of re ading the control & status (c/s) word followed by unlocking the mb does not make the code return to empty. it remains full. if a new frame is written to the mb after the c/s word was read and the mb was unlocked, the code still remains full. 0110 if the mb is full and a new frame should be written into this mb before the cpu had time to read it, the mb is overwritten, and th e code is automatically updated to overrun. 0110 overrun: a frame was overwritten into a full buffer. 0010 if the code indicates overrun but the cpu reads the c/s word and then unlocks the mb, when a new frame is written to the mb, the code returns to full. 0110 if the code already indicates overrun, and yet another new frame must be written, the mb will be overwritten again, and the code will remain overrun. 0xy1 1 1 note that for transmit message buffers (see table 25-13 ), the busy bit should be ignored upon read. busy: flexcan is updating the contents of the mb with a new receive frame. the cpu should not try to access the mb. 0010 an empty buffer was written with a new frame (xy was 01). 0110 a full/overrun buffer was overwritten (xy was 11). table 25-13. message buffer code for tx buffers mb n [rtr] initial tx code code after successful transmission description x 1000 ? inactive: message buffer not ready for transmit and will participate in the arbitration process. 0 1100 1000 data frame to be transmi tted once, unconditionally. after transmission, the mb automatica lly returns to the inactive state. 1 1100 0100 remote frame to be transmitted unconditionally once, and message buffer becomes an rx message buffer with the same id for data frames.
flexcan mcf5213 reference manual, rev. 1.1 25-20 freescale semiconductor preliminary 25.4 functional overview the flexcan module is flexible in that each one of its 16 message buffers (mbs) can be assigned either as a transmit buffer or a receive buf fer. each mb, which is up to 8 bytes long, is also assigned an interrupt flag bit that indicates successful comple tion of either trans mission or reception. an arbitration algorithm decides th e prioritization of mbs to be transmitted base d on either the message id or the mb ordering. a matching algorithm makes it possible to st ore received frames only into mbs that have the same id programmed on its id field. a masking scheme ma kes it possible to match the id programmed on the mb with a range of ids on received can frames. data coherency mechanisms are implemented to guarantee data integrity during mb manipulation by the cpu. before proceeding with the functional description, an important concept must be explained. a message buffer is said to be ?activ e? at a given time if it can participate in the matchi ng and arbitration algorithms that are happening at that t ime. an rx mb with a 0000 c ode is inactive (refer to table 25-12 ). similarly, a tx mb with a 1000 code is inactive (refer to table 25-13 ). an mb not programme d with either 0000 or 1000 will be temporarily deactivated (w ill not participate in the current arbitration/matchi ng run) when the cpu writes to the c/s field of that mb. 25.4.1 transmit process the cpu prepares or changes an mb for transmission by ex ecuting the following steps: 1. writing the control/status word to hold tx mb inactive (code = 1000). 2. writing the id word. 3. writing the data bytes. 4. writing the control/status word (active code, length). 0 1010 1010 transmit a data frame whenever a remote request frame with the same id is received. this message buffer participates simultaneously in both the matc hing and arbitration processes. the matching process compares the id of the incoming remote request frame with the id of the mb. if a match occurs, this message buffer is allowed to participate in the current arbitration process and the code field is automatically updated to 1110 to allow the mb to participate in future arbitration runs. when the frame is eventually transmitted successfully, the code automatically returns to 1010 to restart the process again. 0 1110 1010 this is an intermediate code that is automatically written to the message buffer as a result of match to a remote request frame. the data frame will be transmitted unconditionally once, and then the code will autom atically return to 1010. the cpu can also write this code with the same effect. table 25-13. message buffer code for tx buffers (continued) mb n [rtr] initial tx code code after successful transmission description
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-21 preliminary note the first and last steps are mandatory! the first write to the control/status word is importa nt in case there was pendi ng reception or transmission. the write operation immedi ately deactivates the mb , removing it from any cu rrently ongoing arbitration or id matching processes, givi ng time for the cpu to program the rest of the mb (see section 25.4.5.2, ?message buffer deactivation? ). once the mb is activated in the four th step, it will participate in the arbitration process and eventually be transmitted according to its priori ty. at the end of the successful transmission, the value of the free running timer (timer n ) is written into the message buffer?s time stamp field, the code field in the control and status word is updated, a status flag is set in the iflag n register and an interrupt is genera ted if allowed by the corresponding imask n register bit. the new code field after transmission depends on the code that was used to activate the mb in step four (see table 25-13 ). 25.4.2 arbitration process the arbitration process is an algor ithm executed by the me ssage buffer management (mbm) that scans the entire mb memory looking for the highest priority message to be transmitte d. all mbs programmed as transmit buffers will be scanned to find the lowe st id or the lowest mb number, depending on the canctrl n [lbuf] bit. note if canctrl n [lbuf] is cleared, the arbitrat ion considers not only the id, but also the rtr and ide bits placed insi de the id at the sa me positions they are transmitted in the can frame. the arbitration process is tri ggered in the following events: ? during the crc field of the can frame ? during the error delimiter field of the can frame ? during intermission, if the winner mb defined in a previous arbitrat ion was deactivated, or if there was no mb to transmit, but the cpu wrote to the c/s word of a ny mb after the previous arbitration finished ? when mbm is in idle or bus off state and the cpu writes to the c/s word of any mb ? upon leaving freeze mode once the highest priority mb is sel ected, it is transferred to a tem porary storage space called serial message buffer (smb), which has the same structure as a normal mb but is not user accessible. this operation is called ?move-out.? at the first opportunity window on th e can bus, the message on the smb is transmitted according to the can protocol rules. flexcan transmits up to eight data bytes, even if the dlc (data length code) value is bigger. refer to section 25.4.5.1, ?serial message buffers (smbs),? for more information on serial message buffers.
flexcan mcf5213 reference manual, rev. 1.1 25-22 freescale semiconductor preliminary 25.4.3 receive process the cpu prepares or changes an mb for frame reception by executing the following steps: 1. writing the control/status word to hold rx mb inactive (code = 0000). 2. writing the id word. 3. writing the control/status word to mark the rx mb as active and empty (code = 1000). note the first and last steps are mandatory! the first write to the control/status word is important in case there wa s a pending reception or transmission. the write operation immedi ately deactivates the mb , removing it from any cu rrently ongoing arbitration or matching process, giving time for the cpu to progra m the rest of the mb. once the mb is activated in the third step, it will be able to receive can fr ames that match the programmed id. at the end of a successful reception, the value of the free running timer (timer n ) is written into the time stamp field, the received id, data (8 bytes at most) and length fields are stored, the code field in the control and status word is updated (see table 25-12 ), and a status flag is set in the iflag n register and an interrupt is generated if allowed by the corresponding imask n bit. the cpu should read a receive frame from its mb in the following way: 1. read the control/status word (mandatory?activates internal lock for this buffer). 2. read the id (optional?needed only if a mask was used). 3. read the data field words. 4. read the free-running timer (rel eases internal lock ?optional). upon reading the control and status word, if the busy bit is set in the code field, then the cpu should defer the access to the mb until this bit is negated. reading the free r unning timer is not mandatory. if not executed the mb remains locked, unless the cpu read s the c/s word of another mb. note that only a single mb is locked at a time. th e only mandatory cpu read operation is the one on the control and status word to assure data coherency. the cpu should synchronize to frame reception by an iflag n bit for the specific mb (see section 25.3.8, ?interrupt flag re gister (iflagn)? ), and not by the control/status wo rd code field fo r that mb. polling the code field does not work because once a fram e was received and the cpu services the mb (by reading the c/s word followed by unlocking the mb), th e code field will not return to empty. it will remain full, as explained in table 25-12 . if the cpu tries to workaround th is behavior by writing to the c/s word to force an empty code after reading the mb , the mb is actually deactiv ated from any currently ongoing matching process. as a result, a newly received frame matchi ng the id of that mb may be lost. in summary, never do polling by directly reading th e c/s word of the mbs. instead, read the iflag n register. note that the received identifier field is always stored in the matching mb, thus the contents of the id field in an mb may change if the match was due to masking.
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-23 preliminary 25.4.3.1 self-received frames self-received frames are frames that are sent by the flexcan a nd received by itself. the flexcan sends a frame externally through th e physical layer onto the c an bus, and if the id of the frame matches the id of the flexcan mb, then the fram e will be received by the flexcan. such a frame is a self-received frame. note that flexcan does not receive frames transmitt ed by itself if another device on the can bus has an id that matches the flexcan rx mb id. 25.4.4 matching process the matching process is an algorithm that scans th e entire mb memory looki ng for rx mbs programmed with the same id as the one received from the can bus . only mbs programmed to receive will participate in the matching process for received frames. while the id, dlc and data fields ar e retrieved from the can bus, they ar e stored temporarily in the serial message buffer ( section 25.4.5.1, ?serial mess age buffers (smbs)? ). the matching process takes place during the crc field. if a matching id is found in one of the mbs, th e contents of the smb will be transferred to the matched mb during the sixth bit of the end-of-f rame field of the can protocol. this operation is called ?move-in?. if a ny protocol error (crc, ack, etc.) is detected, than the move-in operation does not happen. an mb with a matching id is ?free to receive? a new frame if the mb is not locked (see section 25.4.5.3, ?locking and releasi ng message buffers? ) and the code field is either empty or else it is full or overrun but the cpu has already serviced the mb (read the c/s word and then unlocked the mb). matching to a range of ids is possibl e by using id accepta nce masks (rxgmask n , rx14mask n , and rx15mask n ). during the matching algorithm, if a mask bit is asserted, th en the corresponding id bit is compared. if the mask bit is negated, the corresponding id bit is ?don?t care?. 25.4.5 message buffer handling in order to maintain data cohere ncy and flexcan proper ope ration, the cpu must obe y the rules described in section 25.4.1, ?transmit process? and section 25.4.3, ?receive process.? any form of cpu accessing a mb structure within flexcan ot her than those specified may cause flexcan to behave in an unpredictable way. 25.4.5.1 serial message buffers (smbs) to allow double buffering of messages, the flexcan has two shadow buffers called serial message buffers. these two buffers are used by the flexcan for buffering both received messages and messages to be transmitted. only one smb is active at a time, and its function depends upon the operation of the flexcan at that time. at no time does the user ha ve access to or visibility of these two buffers. 25.4.5.2 message buffer deactivation if the cpu wants to change the function of an active mb, the recommended proce dure is to put the module into freeze mode and then change the code field of that mb. this is a safe procedure because the flexcan waits for pending can bus and mb moving act ivities to finish before entering freeze mode.
flexcan mcf5213 reference manual, rev. 1.1 25-24 freescale semiconductor preliminary nevertheless, a mechanism is provide d to maintain data coherence when the cpu writes to the control and status word of active mbs out of freeze mode. any cpu write access to the c/s word of an mb causes that mb to be excluded from the transmit or receive processes during the current matching or arbitration round. this mechanism is called mb deactivation. it is temporary, affecting only for the current match/arbitration round. the purpose of deactivation is data coherency. the match/arbitration process scans the mbs to decide which mb to transmit or receive. if the cpu updates the mb in the middle of a match or arbitration process, the data of that mb may no longer be coherent, ther efore that mb is deactivated. even with the coherence mechanism described above, wr iting to the c/s word of active mbs when not in freeze mode may produce undesira ble results. examples are: ? matching and arbitration are one-p ass processes. if mbs are deactivated after they are scanned, no re-evaluation is done to determine a new match/ winner. if an rx mb with a matching id is deactivated during the matching proce ss after it was scanned, then this mb is marked as invalid to receive the frame, and flexcan wi ll keep looking for another matc hing mb within the ones it has not scanned yet. if it can not find one, then the message will be lost . suppose, for example, that two mbs have a matching id to a recei ved frame, and the user deactivat ed the first matching mb after flexcan has scanned the second. the received frame will be lost ev en if the second matching mb was ?free to receive?. ? if a tx mb containing the lowest id is deacti vated after the flexcan has scanned it, then the flexcan will look for anot her winner within the mb s that it has not yet sc anned. therefore, it may transmit an mb that may not have the lowest id at the time because a lo wer id might be present that it had already scanned before the deactivation. ? there is a point in time until which the deactivati on of a tx mb causes it not to be transmitted (end of move-out). after this point, it is transmitted bu t no interrupt is issued and the code field is not updated. 25.4.5.3 locking and releasing message buffers besides message buffer deactivation, the lock/relea se/busy mechanism is de signed to guarantee data coherency during the receive process. the followi ng examples demonstrate how the lock/release/busy mechanism will affect flexcan operation. 1. reading a control/status word of a message buffe r triggers a lock for that message buffer. a new received message frame that matche s the message buffer cannot be wr itten into this message buffer while it is locked. 2. to release a locked message buffer, the cpu ei ther locks another message buffer (by reading its control/status word) or globally releases any locked message buff er (by reading the free-running timer). 3. if a receive frame with a matchi ng id is received during the time the message buffer is locked, the receive frame will not be immediat ely transferred into that message buffer, but will remain in the smb. there is no indication when this occurs. 4. when a locked message buffer is released, if a fr ame with a matching identifier exists within the smb, then this frame will be transferred to the matching message buffer.
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-25 preliminary 5. if two or more receive frames with matchi ng ids are received while a message buffer with a matching id is locked, the last received frame with that id is kept within the serial message buffer, while all preceding ones are lost. there is no indi cation of lost messages when this occurs. 6. if the user reads the control/ status word of a receive messag e buffer while a frame is being transferred from a serial message buffer, the bu sy code will be indicate d. the user should wait until this code is cleared before continuing to read from the message buffer to ensure data coherency. in this situation, the read of the cont rol/status word will not lock the message buffer. polling the control/status word of a receive message buffer can lock it , preventing a message from being transferred into that buffer. if the control/status word of a receive message buffer is read, it should then be followed by a read of the control/s tatus word of another buffer, or by reading the free-running timer, to ensure that the locked buffer is unlocked. note deactivation takes precedence over locki ng. if the cpu deactivates a locked rx mb, then its lock status is negate d, and the mb is marked as invalid for the current matching round. any pendi ng message on the smb will not be transferred to the mb anymore. 25.4.6 can protocol related frames 25.4.6.1 remote frames the remote frame is a message frame which is transm itted to request a data frame. the flexcan can be configured to transmit a data frame automatically in response to a remote frame, or to transmit a remote frame and then wait for the responding data frame to be received. when transmitting a remote frame, th e user initializes a message buffer as a transmit message buffer with the rtr bit set. once this remote frame is tran smitted successfully, the transmit message buffer automatically becomes a receive message buffer, w ith the same id as the remote frame that was transmitted. when a remote frame is received by the flexcan, th e remote frame id is compared to the ids of all transmit message buffers programme d with a code of 1010. if there is an exact matching id, the data frame in that message buffer is tran smitted. if the rtr bit in the matching transmit message buffer is set, the flexcan will transmit a remote frame as a response. a received remote frame is not stored in a receive message buffer. it is only used to trigger the automatic transmission of a frame in response. the mask registers are not us ed in remote frame id matching. all id bits (except rtr) of the incoming received frame must match for the re mote frame to trigger a response transmission. the matching message buffer immediately enters the internal arbitration process, but is considered as a normal tx mb, with no higher priority. the data length of this frame is independent of the data length code (dlc) field in the remo te frame that initiated its transmission.
flexcan mcf5213 reference manual, rev. 1.1 25-26 freescale semiconductor preliminary 25.4.6.2 overload frames overload frame transmissions are not initiated by the flexcan unless certain conditions are detected on the can bus. these conditions include: ? detection of a dominant bit in the first or second bit of intermission. ? detection of a dominant bit in th e seventh (last) bit of the end- of-frame (eof) field in receive frames. ? detection of a dominant bit in the eighth (last) bit of the error frame de limiter or overload frame delimiter. 25.4.7 time stamp the value of timer n is sampled at the beginning of the iden tifier field on the can bus. for a message being received, the time stam p will be stored in the timestamp en try of the receive message buffer at the time the message is written into that buffer. for a message being transm itted, the timestamp entry will be written into the transm it message buffer once the transmission has completed successfully. the free-running timer can optionally be reset upon the reception of a frame into message buffer 0. this feature allows network ti me synchronization to be performed. see the canctrl n [tsyn] bit. 25.4.8 bit timing the flexcan module canctrl n register configures the bit ti ming parameters required by the can protocol. the clk_src, presdiv, rjw, pseg1, ps eg2, and the propseg fields allow the user to configure the bit timing parameters. the canctrl n [clk_src] bit defines whether the module uses the internal bus clock or the output of the crystal oscillator via the extal pin. the crystal oscillator clock s hould be selected whenever a tight tolerance (up to 0.1%) is required fo r the can bus timing. the crystal os cillator clock ha s better jitter performance than pll generated clocks . the value of this bit should not be changed unless the module is in disable mode (canmcr n [mdis] bit is set) the presdiv field controls a prescaler that generates the serial clock (s-clock), whose period defines the ?time quantum? used to co mpose the can waveform. a time quantum is the atomic unit of time handled by the can engine. figure 25-14. can engine clocking scheme oscillator clock (extal) canctrl n [clk_src] prescaler (1 .. 256) s clock 1 0 (f sys/2 ) internal bus clock
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-27 preliminary a bit time is subdivided into three segments 1 (reference figure 25-15 and table 25-14 ): ? sync_seg: this segment has a fixed length of one time quantum. signal e dges are expected to happen within this section ? time segment 1: this segment includes the propa gation segment and the phase segment 1 of the can standard. it can be programmed by setti ng the propseg and the pseg1 fields of the canctrl n register so that their sum (plus 2) is in the range of 4 to 16 time quanta ? time segment 2: this segment represents the ph ase segment 2 of the can standard. it can be programmed by setting the ps eg2 field of the canctrl n register (plus 1) to be 2 to 8 time quanta long eqn. 25-3 figure 25-15. segments within the bit time table 25-15 gives an overview of the can compliant segmen t settings and the related parameter values. 1. for further explanation of the underlying concepts please refer to iso/dis 11519 ? 1, section 10.3. reference also the bosch can 2.0a/b protocol specification dated september 1991 for bit timing. table 25-14. time segment syntax syntax description sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node samples the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. f tq f sys/2 or extal presdiv + 1 () -------------------------------------- - = bit rate f tq (number of time quanta) ------------------------------------------------------------- = sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + pseg1 + 2) (pseg2 + 1) transmit point
flexcan mcf5213 reference manual, rev. 1.1 25-28 freescale semiconductor preliminary note it is the user?s responsibility to ensure the bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the value implemented in the flexcan module 25.5 flexcan initialization sequence initialization of the flexcan includes the initial conf iguration of the message buffers and configuration of the can communication parameters following a reset, as well as any reconfiguration which may be required during operation. the flexcan m odule may be reset in three ways: ? device level hard reset which resets all memory mapped registers asynchronously ? device level soft reset, which resets some of the memory mapped registers synchronously (refer to table 25-1 to see which registers ar e affected by soft reset) ?canmcr n [soft_rst] bit, which has the same ef fect as the device level soft reset soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. therefore, it may ta ke some time to fully prop agate its effects. the canmcr n [soft_rst] bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. also, soft reset can not be applied while cl ocks are shut down in any of the low power modes. the low power mode should be exited and the clocks resumed before applying soft reset. the clock source, canctrl n [clk_src], should be selected while the module is in disable mode. after the clock source is selected a nd the module is enabled (canmcr n [mdis] bit cleared), the flexcan automatically enters freeze mode. in freeze mode, the flexcan is un-synchronized to the can bus, the canmcr n register?s halt and frz bits are set, the internal state machines are disabled, and the canmcr n register?s frz_ack and not_ rdy bits are set. the can n tx pin is in re cessive state and the flexcan does not initiate any tr ansmission or reception of can frames. note th at the message buffers are not affected by reset, so they are not automatically initialized. table 25-15. can standard compliant bit time segment settings time segment 1 time segment 2 re-synchronization jump width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 9 .. 16 8 1 .. 4
flexcan mcf5213 reference manual, rev. 1.1 freescale semiconductor 25-29 preliminary for any configuration change/i nitialization, the flexcan must be in freeze mode (see section 25.1.3.2, ?freeze mode? ). the following is a generic initializati on sequence applicable to the flexcan module: 1. initialize all operation modes in the canctrl n register. a) initialize the bit timing paramete rs propseg, psegs1, pseg2, and rjw b) select the s-clock rate by programming the presdiv field. c) select the internal arbitr ation mode via the lbuf bit. 2. initialize message buffers a) the control/status word of all me ssage buffers must be written ei ther as an active or inactive message buffer. b) all other entries in each message buf fer should be initia lized as required. 3. initialize rxgmask n , rx14mask n , and rx15mask n registers for acceptance mask as needed 4. initialize flexcan interrupt handler a) initialize the interrupt controller re gisters for any needed interrupts. see ,? for more information. b) set the required mask bits in the imask n register (for all message buffer interrupts) and the canctrl n (for bus off and error interrupts). 5. clear the canmcr n [halt] bit. at this point, the flexcan will attempt to synchronize with the can bus. 25.5.1 interrupts there are three interrupt sources for the flexcan module. a combined interrupt for all 16 mbs is generated by combining all the interrupt sources from mb s. this interrupt gets generated when any of the 16 mb interrupt sources generates a interrupt. in this case, the cpu must read the iflag n register to determine which mb caused the interrupt. the other tw o interrupt sources (bus off and error) act in the same way, and are located in the errstat n register. the bus off and error interrupt mask bits are located in the canctrl n register.
flexcan mcf5213 reference manual, rev. 1.1 25-30 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-1 preliminary chapter 26 debug module 26.1 introduction this chapter describes the revision b+ enhanced hardware debug module. 26.1.1 overview the debug module is shown in figure 26-1 . figure 26-1. processor/debug module interface depending upon the package, some devices contain only the allpst signal and do not have the pst[3:0] and ddata[3:0] signals. allpst is a logical ?and? of the pst[3:0] signals, and when asserted reflects that the core is halted. debug support is divided into three areas: ? real-time trace support?the ability to dete rmine the dynamic execution path through an application is fundamental for debugging. the coldfire solution im plements an 8-bit parallel output bus that reports processor execution status and data to an external emulator system. see section 26.3, ?real-time trace support .? ? background debug mode (bdm)?provides low-le vel debugging in the coldfire processor complex. in bdm, the processor complex is halted and a variety of commands can be sent to the processor to access memory, registers, and periphe rals. the external emulator uses a three-pin, serial, full-duplex co mmunication port. see section 26.5, ?background debug mode (bdm) ,? and section 26.4, ?memory map/register definition .? ? real-time debug support?bdm requi res the processor to be ha lted, which many real-time embedded applications ca nnot do. external development system s can access memory because the hardware supports concurrent operation of th e processor and bdm-initiated commands. debug interrupts let real-time systems ex ecute a unique service routine that can quickly save the contents coldfire cpu core debug module high-speed communication port dsclk, dsi, dso control bkpt core bus trace port pst[3:0], ddata[3:0] pstclk (f sys )
debug module mcf5213 reference manual, rev. 1.1 26-2 freescale semiconductor preliminary of key registers and variables and retu rn the system to normal operation. see section 26.6, ?real-time debug support . 26.1.1.1 the new debug module hardware (rev. b+) the revision b+ debug module features a small enhancement over revisi on b: the addition of three pc breakpoint registers (pcbr1?3). th ese new registers are mapped to drc[3:0] addresses 0x18, 0x1a, and 0x1b. additional pc br eakpoints enable rom/flash software de bugging. however, there are no masking registers associated with these new registers. 26.1.1.2 enhancements over revision a the new debug hardware also contai ns the same enhancements that re vision b has over revision a, while maintaining backwards compatibility with revisi on a. these enhancements are discussed below. the revision b/b+ implementation has added regist ers that eliminate restrictions between bdm commands and the use of the hardware breakpoint logic. in some cases, the additional hardware is not program-visible; in other cases, there have been extensions to the debug module programming model. the register containing the bdm memory address is not a program-visible resource. rather, it is a register loaded automatically during the execution of a bd m command. in the rev. b design, the execution of a bdm command does not affect the hardware breakpo int logic unless those regi sters are specifically accessed. the other register added to the debug module program ming model is the bdm address attribute register (baar). the baar is mapped to a drc[ 3:0] address of 0x05. this 8-bit re gister is equivalent in format of the low-order byte of the aatr register (see section 26.4.3, ?bdm address attribute (baar)? ). this register specifies the memory space attributes as sociated with all bdm memory-referencing commands. additionally, a bit was added to the csr register (csr[bkd]) that confi gures the debug module to assert or not assert an interrupt to the processor when the bkpt signal is asserted. the le vel 1 and level 2 triggers are also configurable to trigger on either an and or an or conditi on. the revision a debug module only triggers on an and condition. 26.2 e xternal signal description table 26-1 describes debug module signals. al l coldfire debug signa ls are unidirectional and related to a rising edge of the processor?s clock signal. th e standard 26-pin debug connector is shown in section 26.8, ?freescale-recommended bdm pinout .?
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-3 preliminary figure 26-2 shows pstclk timing with respect to pst and ddata. figure 26-2. pstclk timing 26.3 real-time trace support real-time trace, which defines the dynamic execution pa th, is a fundamental de bug function. the coldfire solution is to include a parallel ou tput port providing encoded processor status and data to an external development system. this port is partitioned into tw o 4-bit nibbles: one nibble allows the processor to transmit processor status, (pst), and the other allows operand da ta to be disp layed (debug data , ddata). the processor status may not be related to the current bus transfer. external development systems can us e pst outputs with an external im age of the program to completely track the dynamic execution path. this tracking is complicated by any cha nge in flow, where branch target table 26-1. debug module signals signal description development serial clock (dsclk) internally synchronized input. (the logic level on dsclk is validated if it has the same value on two consecutive rising pstclk edges.) clocks the serial communication port to the debug module during packet transfers. maximum frequency is 1/5 the processor status clock (pstclk) speed. at the synchronized rising edge of dscl k, the data input on dsi is sampled and dso changes state. development serial input (dsi) internally synchronized input that provides data input for the serial communication port to the debug module. development serial output (dso) provides serial output communication for debug module responses. dso is registered internally. breakpoint (bkpt ) input used to request a man ual breakpoint. assertion of bkpt puts the processor into a halted state after the current instruction completes. halt status is reflected on processor status signals (pst[3:0]) as the value 0xf. also, in rev b and b+ if the csr[bkd] bit is set, the assertion of the bkpt signal will generate a debug interrupt exception to the processor. debug data (ddata[3:0]) these output signals display the re gister breakpoint status as a default, or optionally, captured address and operand values. the capturing of data va lues is controlled by the setting of the csr. additionally, execution of the wddata instructio n by the processor captures operands which are displayed on ddata. these signals are updated each processor cycle. these signals are not implemented on packages containing fewer than 100 pins. processor status (pst[3:0]) these output signals report the processor status. ta bl e 2 6 - 2 shows the encoding of these signals. these outputs indicate the current status of the processor pipeline and, as a result, are not related to the current bus transfer. the pst value is upda ted each processor cycle. these signals are not implemented on packages containing fewer than 100 pins. all processor status outputs (allpst) allpst is a logical ?and? of the four pst signals is provided on all packages. pst[3:0] and ddata[3:0] are not available on the low cost (less than 100 pin) packages. when asserted, reflects that the core is halted. pst or ddata pstclk
debug module mcf5213 reference manual, rev. 1.1 26-4 freescale semiconductor preliminary address calculation is based on the c ontents of a program-visible regist er (variant addressing). ddata outputs can be configured to display the target address of such instruct ions in sequential nibble increments across multiple processor cl ock cycles, as described in section 26.3.1, ?begin execution of taken branch (pst = 0x5) .? two 32-bit storage elements form a fifo buffer connecting the processor?s high-speed local bus to the external development system th rough pst[3:0] and ddata[3:0]. the buffer captures branch target addresses and certai n data values for eventual displa y on the ddata port, one nibble at a time starting with the l east significant bit (lsb). execution speeds affected only when bot h storage elements contain valid data to be dumped to the ddata port. the core stalls until one fifo entry is available. table 26-2 shows the encoding of these signals. table 26-2. processor status encoding pst[3:0] definition hex binary 0x0 0000 continue execution. many instructions execute in one processor cycle. if an instruction requires more processor clock cycles, subsequent clock cycles are indicated by driving pst outputs with this encoding. 0x1 0001 begin execution of one instruction. for most inst ructions, this encoding signals the first processor clock cycle of an instruction?s execution. certain chan ge-of-flow opcodes, plus the pulse and wddata instructions, generate different encodings. 0x2 0010 reserved 0x3 0011 entry into user-mode. signaled after execution of the instruction that caused the coldfire processor to enter user mode. 0x4 0100 begin execution of pulse and wddata instructions. pulse defines logic analyzer triggers for debug and/or performance analysis. wddata lets the co re write any operand (byte, word, or longword) directly to the ddata port, independent of debug module configuration. when wddata is executed, a value of 0x4 is signaled on the pst port, followe d by the appropriate marker, and then the data transfer on the ddata port. transfer length depends on the wddata operand size. 0x5 0101 begin execution of taken branch. for some opcodes, a branch target address may be displayed on ddata depending on the csr settings. csr also co ntrols the number of address bytes displayed, indicated by the pst marker value preceding t he ddata nibble that begins the data output. see section 26.3.1, ?begin execution of taken branch (pst = 0x5).? also indicates that the sync_pc command has been issued. 0x6 0110 reserved 0x7 0111 begin execution of return from exception (rte) instruction. 0x8? 0xb 1000? 1011 indicates the number of bytes to be displayed on the ddata port on subsequent processor clock cycles. the value is driven onto the pst port o ne pstclk cycle before the data is displayed on ddata. 0x8 begin 1-byte transfer on ddata. 0x9 begin 2-byte transfer on ddata. 0xa begin 3-byte transfer on ddata. 0xb begin 4-byte transfer on ddata. 0xc 1100 exception processing. exceptions that enter em ulation mode (debug interrupt or optionally trace) generate a different encodi ng, as described below. because the 0xc encoding defines a multiple-cycle mode, pst outputs are driven with 0xc unt il exception processing completes.
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-5 preliminary 26.3.1 begin execution of taken branch (pst = 0x5) pst is 0x5 when a taken branch is executed. for some opcodes, a branch target address may be displayed on ddata depending on the csr settings. csr also c ontrols the number of address bytes displayed, which is indicated by the pst marker value immediately preceding the dd ata nibble that begins the data output. bytes are displayed in least-to-mos t-significant order. the processor captures only those target addresses associated with taken branches which use a variant addressing mode; that is, rte and rts instructions, jmp and jsr instructions using address register indi rect or indexed addressing modes, and all exception vectors. the simplest example of a branch in struction using a variant address is the compiled code for a c language case statement. typically, the evalua tion of this statement uses the vari able of an expression as an index into a table of offsets, where each offset points to a unique case within the structure. for such change-of-flow operations, the coldfire processor us es the debug pins to output the following sequence of information on successive processor clock cycles: 1. use pst (0x5) to identify that a taken branch was executed. 2. using the pst pins, opti onally signal the target address to be displayed sequentially on the ddata pins. encodings 0x9?0xb identify the number of bytes displayed . 3. the new target address is optionally available on subsequent cycles using the ddata port. the number of bytes of the target a ddress displayed on this port is configurable (2, 3, or 4 bytes). another example of a variant branch inst ruction would be a jmp (a0) instruction. figure 26-3 shows the pst and ddata outputs that indicate a jmp (a0) execution (assuming the csr was programmed to display the lower 2 bytes of an address). 0xd 1101 entry into emulator mode. displayed during emulation mode (debug interrupt or optionally trace). because this encoding defines a mu ltiple-cycle mode, pst outputs are driven with 0xd until exception processing completes. 0xe 1110 processor is stopped. appears in multiple- cycle format when the processor executes a stop instruction. the coldfire processor remains st opped until an interrupt occurs, thus pst outputs display 0xe until the stopped mode is exited . 0xf 1111 processor is halted. because this encoding defin es a multiple-cycle mode, the pst outputs display 0xf until the processor is restarted or reset. (see section 26.5.1, ?cpu halt ?) table 26-2. processor status encoding (continued) pst[3:0] definition hex binary
debug module mcf5213 reference manual, rev. 1.1 26-6 freescale semiconductor preliminary figure 26-3. example jmp instruction output on pst/ddata pst 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. thus, the subsequent 4 nibbles of ddata display the lower 2 bytes of addr ess register a0 in least-to-most-significant nibble orde r. the pst output after the jmp inst ruction completes depends on the target instruction. the pst can continue with the next instruction before the address has completely displayed on ddata because of the dd ata fifo. if the fifo is full and the next instruction has captured values to display on ddata, the pipeline stalls (pst = 0x0) until space is available in the fifo. 26.4 memory map/register definition in addition to the existing bdm comm ands that provide access to the pr ocessor?s registers and the memory subsystem, the debug module contains 19 registers to support the require d functionality. these registers are also accessible from the processor?s supe rvisor programming model by executing the wdebug instruction (write only). thus, the breakpoint hardware in the debug module can be wr itten by the external development system using the debug serial interface or by the operating system running on the processor core. software is responsible for guaranteeing that accesses to these res ources are serializ ed and logically consistent. hardware provides a lock ing mechanism in the csr to allow the external development system to disable any attempted writes by the processor to the breakpoint re gisters (setting csr[ipw]). bdm commands must not be issued if the coldfire pro cessor is using the wdebug instruction to access debug module registers or the resulting behavior is undefined, while dsclk is quiescent. these registers, shown in table 26-3 , are treated as 32-bit quantities, regardless of the number of implemented bits. these registers are also accessed through the bdm port by the commands, wdmreg and rdmreg , described in section 26.5.3.3, ?command set descriptions .? these commands contain a 5-bit field, drc, that specifie s the register, as shown in table 26-3 . table 26-3. debug module memory map drc[4?0] register access reset value section/page 0x00 configuration/status register (csr) see note 0x0090_0000 26.4.2/26-7 0x06 address attribute trigger register (aatr) see note 0x0005 26.4.4/26-10 0x07 trigger definition register (tdr) see note 0x0000_0000 26.4.5/26-11 0x08 pc breakpoint register (pbr) see note undefined 26.4.6/26-13 0x09 pc breakpoint mask register (pbmr) see note undefined 26.4.6/26-13 0x0c address high breakpoint register (abhr) see note undefined 26.4.7/26-14 0x0d address low breakpoint register (ablr) see note undefined 26.4.7/26-14 ddata 0x0 0x0 a[3:0] 0x5 0x9 default pst a[7:4] a[11:8] a[15:12] default default default pstclk
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-7 preliminary note debug control registers can be written by the external development system or the cpu through the wdebug instru ction. csr is write-only from the programming model. it can be read or written through the bdm port using the rdmreg and wdmreg commands. 26.4.1 shared debug resources the debug module implementation provi des a common hardware struct ure for both bdm and breakpoint functionality. certain hardware st ructures are used for both bdm a nd breakpoint purposes as shown in table 26-4 . thus, loading a register to perform a specific function that shares hardwa re resources is destructive to the shared function. for example, if an operand address breakpoint is lo aded into the debug module, a bdm command to access memory overwrites an address breakpoint in abhr. if a data breakpoint is configured, a bdm write command overwrites the data breakpoint in dbr. 26.4.2 configuration/st atus register (csr) the csr defines the debug configuration for the pro cessor and memory subsyste m and contains status information from the breakpoint logi c. csr is write-only from the pr ogramming model. it can be read from and written to through the bdm port. csr is accessible in supervis or mode as debug control register 0x00 using the wdebug instruction and through the bdm port using the rdmreg and wdmreg commands. 0x0e data breakpoint register (dbr) see note undefined 26.4.8/26-15 0x0f data breakpoint mask register (dbmr) see note undefined 26.4.8/26-15 note: each debug register is accessed as a 32-bit register; reserved fields are not used (don?t care). table 26-4. shared bdm/breakpoint hardware register bdm function breakpoint function aatr bus attributes for all memory commands attributes for address breakpoint abhr address for all memory commands address for address breakpoint dbr data for all bdm write commands data for data breakpoint drc[4:0]: 0x00 (csr) access: supervisor write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset0000000000000 0 0 0 figure 26-4. configuration/status register (csr) table 26-3. debug module memory map (continued) drc[4?0] register access reset value section/page
debug module mcf5213 reference manual, rev. 1.1 26-8 freescale semiconductor preliminary table 26-5. csr field descriptions field description 31?28 bstat breakpoint status. provides read-only status information co ncerning hardware breakpoints. bstat is cleared by a tdr write or by a csr read when either a level-2 breakpoin t is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled. 0000 no breakpoints enabled 0001 waiting for level-1 breakpoint 0010 level-1 breakpoint triggered 0101 waiting for level-2 breakpoint 0110 level-2 breakpoint triggered 27 fof fault-on-fault. if fof is set, a catastrophic halt occurred and forced entry into bdm. fof is cleared whenever csr is read. 26 trg hardware breakpoint trigger. if trg is set, a hardware break point halted the processor core and forced entry into bdm. reset, the debug go command, or reading csr will clear trg. 25 halt processor halt. if halt is set, the processor executed a halt and forced entry into bdm. reset, the debug go command, or reading csr will clear halt. 24 bkpt breakpoint assert. if bkpt is set, bkpt was asserted, forcing the processor into bdm. reset, the debug go command, or reading csr will clear bkpt. 23?20 hrl hardware revision level. indicates the level of debug module functionality. an emulator could use this information to identify the level of functionality supported. 1001 revision b+ (this is the only valid value for this processor) 19?18 reserved, should be cleared. 17 pcd pst/ddata disable. disables the pst/ddata output signal. pstclk is unaffected, it re mains under the control of the disclk bit in the syncr register. 0 normal operation 1 disables the generation of the pstddata output signal s, and forces these signals to remain quiescent 16 ipw inhibit processor writes. setting ipw inhibits processor-ini tiated writes to the debug module?s programming model registers. ipw can be modified only by command s from the external development system. 15 map force processor references in emulator mode. 0 all emulator-mode references are mapped into supervisor code and data spaces. 1 the processor maps all references while in emulator mode to a special address space, tt = 10, tm = 101 or 110. 14 trc force emulation mode on trace exception. if trc = 1, the processor enters emulator mode when a trace exception occurs. if trc=0, the processor enters supervisor mode. 13 emu force emulation mode. if emu = 1, the processo r begins executing in emulator mode. see section 26.6.1.1, ?emulator mode .? 12?11 ddc debug data control. controls operand data capture for ddata, which displays the number of bytes defined by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long displays 32 bits (one nibble at a time acro ss multiple pstclk cycles). see ta b l e 2 6 - 2 . 00 no operand data is displayed. 01 capture all write data. 10 capture all read data. 11 capture all read and write data. 10 uhe user halt enable. selects the cpu privilege leve l required to execute the halt instruction. 0 halt is a supervisor-only instruction. 1 halt is a supervisor/user instruction.
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-9 preliminary 26.4.3 bdm address attribute (baar) the baar register defines the address space fo r memory-referencing bdm commands. baar[r, sz] are loaded directly from the bdm command, while th e low-order 5 bits can be programmed from the external development system. to maintain compatibility with the rev. a implemen tation, this register is loaded any time the aatr is writte n. the baar is initialized to a valu e of 0x05, setting supervisor data as the default address space. 9?8 btb branch target bytes. defines the number of bytes of branch target address ddata displays. 00 0 bytes 01 lower 2 bytes of the target address 10 lower 3 bytes of the target address 11 entire 4-byte target address see section 26.3.1, ?begin execution of taken branch (pst = 0x5) .? 7 reserved, should be cleared. 6 npl non-pipelined mode. determines whether the core operates in pipelined or mode or not. 0 pipelined mode 1 nonpipelined mode. the processor effectively executes one instruction at a time with no overlap. this adds at least 5 cycles to the execution time of each inst ruction. given an average execution latency of 1.6 cycles/instruction, throughput in non-pipeline mode would be 6.6 cycles/instruction, approximately 25% or less of pipelined performance. regardless of the npl state, a triggered pc breakpoint is always reported before the triggering instruction executes. in normal pipeline operation, the occurrence of an addre ss and/or data breakpoint trigger is imprecise. in non-pipeline mode, triggers are always reported before the next instruction begins execution and trigger reporting can be considered precise. 5 ipi ignore pending interrupts. 1 core ignores any pending interrupt requests signalled while in single-instruction-step mode. 0 core services any pending interrupt requests that were signalled while in single-step mode. 4 ssm single-step mode. setting ssm puts the processor in single-step mode. 0 normal mode. 1 single-step mode. the processor halt s after execution of each instruction. while halted, any bdm command can be executed. on receipt of the go command, the processor executes the next instruction and halts again. this process continues until ssm is cleared. 3?0 reserved, should be cleared. drc[4:0]: 0x05 (baar) access: supervisor write-only 7 6543210 r w r sz tt tm reset: 0 0 0 0 0 1 0 1 figure 26-5. bdm address at tribute register (baar) table 26-5. csr field descriptions (continued) field description
debug module mcf5213 reference manual, rev. 1.1 26-10 freescale semiconductor preliminary 26.4.4 address attribute trigger register (aatr) the aatr defines address attributes and a mask to be matched in the trigger. the register value is compared with address attribute si gnals from the processor?s local high-speed bus, as defined by the setting of the trigger definition re gister (tdr). aatr is accessible in supervisor mode as debug control register 0x06 using the wdebug instruct ion and through the bdm port using the wdmreg command. table 26-6. baar field description field description 7 r read/write. 0write 1read 6?5 sz size. 00 longword 01 byte 10 word 11 reserved 4?3 tt transfer type. see the tt defini tion in the aa tr description, section 26.4.4, ?address at tribute trigger register (aatr).? 2?0 tm transfer modifier. see the tm definition in the aatr description, section 26.4.4, ?address at tribute trigger register (aatr).? drc[4:0]: 0x06 (aatr) access: supervisor write-only 1514131211109876543210 r w rm szm ttm tmm r sz tt tm reset00000000 00000101 figure 26-6. address attribute trigger register (aatr) table 26-7. aatr field descriptions field description 15 rm read/write mask. setting rm masks r in address comparisons. 14?13 szm size mask. setting an szm bit masks the co rresponding sz bit in address comparisons. 12?11 ttm transfer type mask. setting a ttm bit masks the co rresponding tt bit in address comparisons. 10?8 tmm transfer modifier mask. setting a tmm bit masks the corresponding tm bit in address comparisons. 7 r read/write. r is compared with the r/w signal of the processor?s local bus.
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-11 preliminary 26.4.5 trigger definition register (tdr) the tdr configures the operation of the hardware breakpoint logic that corresponds with the abhr/ablr/aatr, pbr/pbmr, a nd dbr/dbmr registers within the debug module. the tdr controls the actions taken under the defined conditions. breakpoi nt logic may be configured as a one- or two-level trigger. tdr[31?16] define the second-level tr igger and bits 15?0 define the first-level trigger. note the debug module has no hardware inte rlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable tdr (by clearing tdr[29,13]) be fore defining triggers. a write to tdr clears the csr trigger status bits, cs r[bstat]. tdr is accessible in supervisor mode as debug control register 0x07 using the wdebug instruction and through the bdm port using the wdmreg command. 6?5 sz size. compared to the processor?s local bus size signals. 00 longword 01 byte 10 word 11 reserved 4?3 tt transfer type. compared with the local bus transfer type signals. 00 normal processor access 01 reserved 10 emulator mode access 11 acknowledge/cpu space access these bits also define the tt encoding for bdm memory commands. in this case, the 01 encoding generates an external master or dma access (for backward compatib ility). these bits are used to decode the tm bits. 2?0 tm transfer modifier. compared with the local bus transfer modi fier signals, which give supplemental information for each transfer type. these bits also def ine the tm encoding for bdm memory commands (for backward compatibility). table 26-7. aatr field descriptions (continued) field description tm tt=00 (normal mode) tt=10 (emulator mode) tt=11 (acknowledge/cpu space transfers) 000 reserved reserved cpu space access 001 user data access reserved interrupt ack level 1 010 user code access reserved interrupt ack level 2 011 reserved reserved interrupt ack level 3 100 reserved reserved interrupt ack level 4 101 supervisor data access emulator mode access interrupt ack level 5 110 supervisor code access emulator code access interrupt ack level 6 111 reserved reserved interrupt ack level 7
debug module mcf5213 reference manual, rev. 1.1 26-12 freescale semiconductor preliminary drc[4:0]: 0x07 (tdr) access: supervisor write-only second level trigger 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w trc ebl edlw edwl edwu edll edlm edum eduu di eai ear eal epc pci reset0000000000000000 first level trigger 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r w l2t l1t ebl edlw edwl edwu edll edlm edum eduu di eai ear eal epc pci reset0000000000000000 figure 26-7. trigger definition register (tdr) table 26-8. tdr field descriptions field description 31?30 trc trigger response control. determines how the processor responds to a completed trigger condition. the trigger response is always displayed on ddata. 00 display on ddata only 01 processor halt 10 debug interrupt 11 reserved 15 l2t level-2 trigger. determines the logic operation for the trigger between the pc_condition and the (address_range & data_condition) where the inclusion of a data_condition is optional. the coldfire debug architecture supports the creation of single or double-level triggers. 0 level-2 trigger = pc_condition & address_range & data_condition 1 level-2 trigger = pc_condition | (address_range & data_condition) note: debug rev a only had the ?and? condition available for the triggers. 14 l1t level-1 trigger. determines the logic operation for the trigger between the pc_condition and the (address_range & data_condition) where the inclusion of a data_condition is optional. the coldfire debug architecture supports the creation of single or double-level triggers. 0 level-1 trigger = pc_condition & address_range & data_condition 1 level-1 trigger = pc_condition | (address_range & data_condition) note: debug rev a only had the ?and? condition available for the triggers. 29 & 13 ebl enable breakpoint. global enable for the breakpoint trigger . setting tdr[ebl] enables a breakpoint trigger. clearing it disables all breakpoints at that level.
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-13 preliminary 26.4.6 program counter breakpoi nt/mask registers (pbr, pbmr) the pbr register defines an instructi on address for use as part of the tri gger. this register?s contents are compared with the processor?s progr am counter register wh en tdr is configured appropriately. pbr bits are masked by setting corresponding pbmr bits. results are compared with the processor?s program counter register, as defined in tdr. figure 26-8 shows the pc breakpoint register. the pc breakpoint register is acce ssible in supervisor mode using the wdebug instruction and through the bdm port using the rdmreg and wdmreg commands using values shown in section 26.5.3.3, ?command set descriptions .? 28?22 & 12?6 ed x setting an ed x bit enables the corresponding data breakpoint condition based on the size and placement on the processor?s local data bus. clearing all ed x bits disables data breakpoints. 21 & 5 di data breakpoint invert. provides a way to invert the logi cal sense of all the data break point comparators. this can develop a trigger based on the occurrence of a data value other t han the dbr contents. 20?18 & 4?2 ea x enable address bits. setting an ea bit enables the corresponding address breakpoint. clearing all three bits disables the breakpoint. 17 & 1 epc enable pc breakpoint. 0 disable pc breakpoint 1 enable pc breakpoint 16 & 0 pci breakpoint invert. if set, this bit allows execution outside a given region as defined by pbr and pbmr to enable a trigger. if cleared, the pc breakpoint is defined within the region defined by pbr and pbmr. table 26-8. tdr field descriptions (continued) field description bits field description 28 & 12 edlw data longword. entire processor?s local data bus. 27 & 11 edwl lower data word. 26 & 10 edwu upper data word. 25 & 9 edll lower lower data byte. low-order byte of the low-order word. 24 & 8 edlm lower middle data byte. high-order byte of the low-order word. 23 & 7 edum upper middle data byte. low-order byte of the high-order word. 22 & 6 eduu upper upper data byte. high-order byte of the high-order word. bits field description 20 & 4 eai enable address breakpoint inverted. breakpoint is based outside the range between ablr and abhr. 19 & 3 ear enable address breakpoint range. the breakpoint is based on the inclusive range defined by ablr and abhr. 18 & 2 eal enable address breakpoint low. the breakpoint is based on the address in the ablr.
debug module mcf5213 reference manual, rev. 1.1 26-14 freescale semiconductor preliminary figure 26-8 shows pbmr. pbmr is accessible in supervis or mode as debug control register 0x09 using the wdebug instruction and via the bdm port using the wdmreg command. 26.4.7 address breakpoint registers (ablr, abhr) the ablr and abhr, shown in figure 26-10 , define regions in the proces sor?s data address space that can be used as part of the trigger. these register values are compared with the address for each transfer on the processor?s high-speed local bus. th e trigger definition register (tdr) identifies the trigger as one of three cases: 1. identical to the value in ablr 2. inside the range bound by ablr and abhr inclusive 3. outside that same range abhr is accessible in supervisor mode as debug c ontrol register 0x0c using the wdebug instruction and via the bdm port using the rdmreg and wdmreg commands. ablr is accessi ble in supervisor mode as debug control register 0x0d using the wdeb ug instruction and via the bdm port using the wdmreg command. drc[4:0]: 0x08 (pbr) access: supervisor write-only 313029282726252423222120191817161514131211109876543210 r waddress reset???????????????????????????????? figure 26-8. program counter breakpoint register (pbr) table 26-9. pbr field descriptions field description 31?1 address pc breakpoint address. the address to be co mpared with the pc as a breakpoint trigger. drc[4:0]: 0x09 (pbmr) acce ss: supervisor write-only 313029282726252423222120191817161514131211109876543210 r wmask reset???????????????????????????????? figure 26-9. program counter breakpoint mask register (pbmr) table 26-10. pbmr field descriptions field description 31?0 mask pc breakpoint mask. a zero in a bit position causes the corresponding pbr bit to be compared to the appropriate pc bit. setting a pbmr bit causes the corresponding pbr bit to be ignored.
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-15 preliminary 26.4.8 data breakpoint/mask registers (dbr, dbmr) the dbr specifies data patterns used as part of the trigger into debug mode. dbr bits are masked by setting the corresponding dbmr bits, as defined in td r. dbr is accessible in supervisor mode as debug control register 0x0e, using the wdebug in struction and through th e bdm port using the rdmreg and wdmreg commands. dbmr is accessible in supervisor mode as debug control register 0x0f, using the wdebug instruction and via the bdm port using the wdmreg command. drc[4:0]: 0x0c (abhr) 0x0d (ablr) access: supervisor write-only 313029282726252423222120191817161514131211109876543210 r waddress reset???????????????????????????????? figure 26-10. address breakpoint registers (ablr, abhr) table 26-11. ablr field description field description 31?0 address low address. holds the 32-bit address marking the lower bound of the address breakpoint range. breakpoints for specific addresses are programmed into ablr. table 26-12. abhr field description field description 31?0 address high address. holds the 32-bit address marking the upper bound of the address breakpoint range. drc[4:0]: 0x0e (dbr) 0x0f (dbmr) access: supervisor write-only 313029282726252423222120191817161514131211109876543210 r w data (dbr); mask (dbmr) reset???????????????????????????????? figure 26-11. data breakpoint & mask registers (dbr & dbmr) table 26-13. dbr field descriptions field description 31?0 data data breakpoint value. contains the value to be compared with the data value from the processor?s local bus as a breakpoint trigger.
debug module mcf5213 reference manual, rev. 1.1 26-16 freescale semiconductor preliminary the dbr supports both aligned and misaligned references. table 26-15 shows relationships between processor address, access size, and location within the 32-bit data bus. 26.5 background debug mode (bdm) the coldfire family implements a low-level system debugger in th e microprocessor in a dedicated hardware module. communication with the development system is handled through a dedicated, high-speed serial command interf ace. although some bdm operations, su ch as cpu register accesses, require the cpu to be halted, other bdm commands, su ch as memory accesses, ca n be executed while the processor is running. 26.5.1 cpu halt although most bdm operations can occur in parallel with cpu operations, unrestricted bdm operation requires the cpu to be halted. the sources that can ca use the cpu to halt are listed below in order of priority: 1. a catastrophic fault-on-fault condition automatically halts the processor. 2. a hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of bkpt . this type of halt is always first made pending in the processor. next, the processor samples for pending halt and interrupt conditions once per instruction. when a pending condition is asserted, the processor halts execution at the next sample point. see section 26.6.1, ?theory of operation .? table 26-14. dbmr field descriptions field description 31?0 mask data breakpoint mask. the 32-bit mask for the data breakpoint trigger. clearing a dbr bit allows the corresponding dbr bit to be compared to the appropriate bit of the processor?s local data bus. setting a dbmr bit causes that bit to be ignored. table 26-15. access size and operand data location a[1:0] access size operand location 00 byte d[31:24] 01 byte d[23:16] 10 byte d[15:8] 11 byte d[7:0] 0x word d[31:16] 1x word d[15:0] xx longword d[31:0]
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-17 preliminary 3. the execution of a halt instruction immediately suspends execution. attempting to execute halt in user mode while csr[uhe] = 0 gene rates a privilege violation exception. if csr[uhe] = 1, halt can be executed in user m ode. after halt executes , the processor can be restarted by serial shifting a go command into the debug module. execution continues at the instruction after halt. 4. the assertion of the bkpt input is treated as a pseudo-interr upt; that is, the halt condition is postponed until the processor core samples for halts/interrupts. the processor samples for these conditions once during the execution of each instruct ion. if there is a pending halt condition at the sample time, the processor suspends execution and enters the halted state. the assertion of bkpt should be considered in the following two special cases: ? after the system reset signal is negated, the proc essor waits for 16 processor clock cycles before beginning reset exception processing. if the bkpt input is asserted within eight cycles after rsti is negated, the processor enters th e halt state, signaling halt stat us (0xf) on the pst outputs. while the processor is in this state, all resources accessible through the debug m odule can be referenced. this is the only chance to force the proc essor into emulation mode through csr[emu]. after system initialization, th e processor?s response to the go command depends on the set of bdm commands performed while it is halted for a breakpoint. specific ally, if the pc register was loaded, the go command causes the processo r to exit halted state and pa ss control to the instruction address in the pc, bypassing normal reset excepti on processing. if the pc was not loaded, the go command causes the processor to exit halted state and continue reset exception processing. ? the coldfire architecture also handles a special case of bkpt being asserted while the processor is stopped by execution of the st op instruction. for this case, th e processor exits the stopped mode and enters the halted st ate, at which point, all bdm commands may be ex ercised. when restarted, the processor continues by executing the next se quential instruction, that is, the instruction following the stop opcode. the csr[27?24] bits indicate the halt source, showing the highest prio rity source for multiple halt conditions. 26.5.2 bdm serial interface when the cpu is halted and pst reflects the halt status, the development system can send unrestricted commands to the debug module. the debug module impl ements a synchronous seri al protocol using two inputs (dsclk and dsi) and one output (dso), where dso is specified as a delay relative to the rising edge of the processor clock. see table 26-1 . the development system serves as the serial communication channel master and must generate dsclk. the serial channel operates at a fr equency from dc to 1/5 of the pstc lk frequency. the channel uses full-duplex mode, where data is se nt and received simultaneously by both master and slave devices. the transmission consists of 17-bit packets composed of a status/contro l bit and a 16-bit data word. as shown in figure 26-12 , all state transitions are enab led on a rising edge of pstclk when dsclk is high; that is, dsi is sampled and dso is driven.
debug module mcf5213 reference manual, rev. 1.1 26-18 freescale semiconductor preliminary figure 26-12. bdm serial interface timing dsclk and dsi are synchronized inputs. dsclk acts as a pseudo clock enable and is sampled on the rising edge of the processor clock as well as the dsi. dso is delayed from the ds clk-enabled clk rising edge (registered after a bdm state machine state change). all events in the debug module?s serial state machine are based on the processor clock rising edge. dsclk must also be sampled low (on a positive edge of clk) between each bit exch ange. the msb is transferred first. because dso changes state based on an internally-recognized rising edge of dsclk, dso cannot be used to indicate the start of a serial transfer. the development system must count clock cy cles in a given transfer. c1?c4 are described as follows: ? c1?first synchronization cycl e for dsi (dsclk is high). ? c2?second synchronization cycl e for dsi (dsclk is high). ? c3?bdm state machine changes state depending upon dsi and whet her the entire input data transfer has been transmitted. ? c4?dso changes to next value. note a not-ready response can be ignored except during a memory-referencing cycle. otherwise, the de bug module can accept a new se rial transfer after 32 processor clock periods. 26.5.2.1 receive packet format the basic receive packet, figure 26-13 , consists of 16 data bits and 1 status bit. 151514131211109876543210 s data field figure 26-13. receive bdm packet c1 c2 c3 c4 dsclk next state bdm state machine dso dsi current state current next past current pstclk
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-19 preliminary 26.5.2.2 transmit packet format the basic transmit packet, figure 26-14 , consists of 16 data bits and 1 reserve bit. 26.5.3 bdm command set table 26-18 summarizes the bdm command set. subsequent paragraphs contain deta iled descriptions of each command. issuing a bdm comm and when the processor is accessi ng debug module registers using the wdebug instruction causes undefined behavior. table 26-16. receive bdm packet field description field description 16 s status. indicates the status of cpu-generated message s listed below. the not-ready response can be ignored unless a memory-referencing cycle is in progress. otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 15?0 data data. contains the message to be se nt from the debug module to the de velopment system. t he response message is always a single word, with the data field encoded as shown above. 151514131211109876543210 ?data figure 26-14. transmit bdm packet table 26-17. transmit bdm packet field description field description 16 reserved, should be cleared. 15?0 data data bits 15?0. contains the data to be sent from the development system to the debug module. table 26-18. bdm command summary command mnemonic description cpu state 1 section command (hex) read a/d register rareg / rdreg read the selected address or data register and return the results through the serial interface. halted 26.5.3.3.1 0x218 {a/d, reg[2:0]} write a/d register wareg / wdreg write the data operand to the specified address or data register. halted 26.5.3.3.2 0x208 {a/d, reg[2:0]} s data message 0 xxxx valid data transfer 0 ffff status ok 1 0000 not ready with response; come again 1 0001 error?terminated bus cycle; data invalid 1 ffff illegal command
debug module mcf5213 reference manual, rev. 1.1 26-20 freescale semiconductor preliminary unassigned command opcodes are reserved by free scale. all unused command formats within any revision level perform a nop and return the illegal command response . read memory location read read the data at the memory location specified by the longword address. steal 26.5.3.3.3 0x1900?byte 0x1940?word 0x1980?lword 2 write memory location write write the operand data to the memory location specified by the longword address. steal 26.5.3.3.4 0x1800?byte 0x1840?word 0x1880?lword 2 dump memory block dump used with read to dump large blocks of memory. an initial read is executed to set up the starting address of the block and to retrieve the first result. a dump command retrieves subsequent operands. steal 26.5.3.3.5 0x1d00?byte 0x1d40?word 0x1d80?lword 2 fill memory block fill used with write to fill large blocks of memory. an initial write is executed to set up the starting address of the block and to supply the first operand. a fill command writes subsequent operands. steal 26.5.3.3.6 0x1c00?byte 0x1c40?word 0x1c80?lword 2 resume execution go the pipeline is flushed and refilled before resuming instruction execution at the current pc. halted 26.5.3.3.7 0x0c00 no operation nop perform no operation; may be used as a null command. parallel 26.5.3.3.8 0x0000 synchronize pc to pst/ddata sync _ pc capture the current pc and display it on the pst/ddata outputs parallel 26.5.3.3.9 0x0001 read control register rcreg read the system control regi ster. halted 26. 5.3.3.10 0x2980 write control register wcreg write the operand data to the system control register. halted 26.5.3.3.11 0x2880 read debug module register rdmreg read the debug module register. parallel 26.5.3.3.12 0x2d {0x4 3 drc[4:0]} write debug module register wdmreg write the operand data to the debug module register. parallel 26.5.3.3.13 0x2c {0x4 3 drc[4:0]} 1 general command effect and/or requirements on cpu operation: - halted. the cpu must be halted to perform this command. - steal. command generates bu s cycles that can be interleaved with bus accesses. - parallel. command is executed in parallel with cpu activity. 2 lword = longword 3 0x4 is a three-bit field. table 26-18. bdm command summary (continued) command mnemonic description cpu state 1 section command (hex)
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-21 preliminary 26.5.3.1 coldfire bdm command format all coldfire family bdm commands include a 16-bit operation word fo llowed by an optional set of one or more extension words, as shown in figure 26-15 . 26.5.3.1.1 extension words as required some commands require extension words for addre sses and/or immediate data . addresses require two extension words because only absolute long addre ssing is permitted. longwor d accesses are forcibly longword-aligned and word accesses are forcibly word-aligned. immediat e data can be 1 or 2 words long. byte and word data each re quires a single extension word and longwor d data requires two extension words. operands and addresses are transfer red most-significant word first. in the following descriptions of the bdm command set, the optional set of extension word s is defined as address, data, or operand data. 151514131211109876543210 operation 0 r/w op size 0 0 a/d register extension word(s) figure 26-15. bdm command format table 26-19. bdm field descriptions field description 15?10 operation specifies the command. these values are listed in table 26-18 . 9 reserved, should be cleared. 8 r/w direction of operand transfer. 0 data is written to the cpu or to memory from the development system. 1 the transfer is from the cpu to the development system. 7?6 op size operand data size for sized operations. addresses are expre ssed as 32-bit absolute values. note that a command performing a byte-sized memory read leaves the upper 8 bi ts of the response data undefined. referenced data is returned in the lower 8 bits of the response. 5?4 reserved, should be cleared. 3 a/d address/data. determines whether the register field specifies a data or address register. 0 indicates a data register. 1 indicates an address register. 2?0 register contains the register number in comm ands that operate on processor registers. operand size bit values 00 byte 8 bits 01 word 16 bits 10 longword 32 bits 11 reserved ?
debug module mcf5213 reference manual, rev. 1.1 26-22 freescale semiconductor preliminary 26.5.3.2 command sequence diagrams the command sequence diagram in figure 26-16 shows serial bus traffic for commands. each bubble represents a 17-bit bus transfer. the top half of each bubble indicates the data the development system sends to the debug module; the bot tom half indicates the debug module?s response to the previous development system commands. command and resu lt transactions overlap to minimize latency. figure 26-16. command sequence diagram the sequence is as follows: ? in cycle 1, the development system command is issued ( read in this example). the debug module responds with either the low-orde r results of the prev ious command or a comm and complete status of the previous command, if no results are required. ? in cycle 2, the development system supplies the high-order 16 address bits. the debug module returns a not-ready response unless the received command is dec oded as unimplemented, which is indicated by the illegal command encoding. if this occurs, the development system should retransmit the command. note a not-ready response can be ignored except during a memory-referencing cycle. otherwise, the de bug module can accept a new se rial transfer after 32 processor clock periods. ? in cycle 3, the development system supplies the low-order 16 address bits. the debug module always returns a not-ready response. ? at the completion of cycle 3, the debug module initiates a memory read operation. any serial transfers that begin during a memory access return a not-ready response. xxx ?not ready? read (long) ??? ms addr ?not ready? ls addr ?not ready? next cmd ?not ready? next cmd ?not ready? next cmd ls result commands transmitted to the debug module command code transmitted during this cycle high-order 16 bits of memory address low-order 16 bits of memory address non-serial-related next command code sequence taken if operation has not completed activity read memory location xxx berr xxx ms result xxx ?illegal? responses from the debug module results from previous command sequence taken if illegal command is received by debug module data used from this transfer sequence taken if bus error occurs on memory access high- and low-order 16 bits of result
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-23 preliminary ? results are returned in the two serial transfer cycles after the memory access completes. for any command performing a byte-sized memory read opera tion, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. the ne xt command?s opcode is sent to the debug module during the fi nal transfer. if a memory or regi ster access is terminated with a bus error, the error status (s = 1, data = 0x0001) is returned instead of result data. 26.5.3.3 command set descriptions the following sections describe the commands summarized in table 26-18 . note the bdm status bit (s) is 0 for nor mally completed commands; s = 1 for illegal commands, not-ready responses , and transfers with bus-errors. section 26.5.2, ?bdm serial interface ,? describes the receive packet format. freescale reserves unassigned comm and opcodes for future expansion. unused command formats in any revision level perform a nop and return an illegal command response. 26.5.3.3.1 read a/d register ( rareg / rdreg ) read the selected address or data re gister and return the 32-bit result. a bus error response is returned if the cpu core is not halted. command/result formats: command sequence: figure 26-18. rareg / rdreg command sequence operand data: none result data: the contents of the selected register are returned as a longword value, most-significant word first. 1514131211109876543210 command 0x2 0x1 0x8 a/d register result d[31:16] d[15:0] figure 26-17. rareg / rdreg command format rareg/rdreg ??? next cmd ls result next cmd ?not ready? xxx berr xxx ms result
debug module mcf5213 reference manual, rev. 1.1 26-24 freescale semiconductor preliminary 26.5.3.3.2 write a/d register ( wareg / wdreg ) the operand longword data is written to the specified addr ess or data register. a wr ite alters all 32 register bits. a bus error response is returned if the cpu core is not halted. command format: command sequence: figure 26-20. wareg / wdreg command sequence operand data: longword data is wri tten into the specified address or data register. the data is supplied most-significant word first. result data: command complete status is i ndicated by returning 0xffff (with s cleared) when the register write is complete. 26.5.3.3.3 read memory location ( read ) read data at the longword addre ss. address space is defined by baar[tt,tm]. hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addr esses are longword-aligned. 1514131211109876543210 0x2 0x0 0x8 a/d register d[31:16] d[15:0] figure 26-19. wareg / wdreg command format wareg/wdreg ??? ls data ?not ready? next cmd ?not ready? xxx berr ms data ?not ready? next cmd ?cmd complete?
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-25 preliminary command/result formats: command sequence: figure 26-22. read command sequence operand data: the only operand is the longw ord address of the requested location. result data: word results return 16 bits of data; l ongword results return 32. bytes are returned in the lsb of a word result; the upper byte is undefined. 0x0001 (s = 1) is returned if a bus error occurs. 1514131211109876543210 byte command 0x1 0x9 0x0 0x0 a[31:16] a[15:0] result x x x x x x x x d[7:0] word command 0x1 0x9 0x4 0x0 a[31:16] a[15:0] result d[15:0] longword command 0x1 0x9 0x8 0x0 a[31:16] a[15:0] result d[31:16] d[15:0] figure 26-21. read command/result formats xxx ?not ready? read (long) ??? ms addr ?not ready? ls addr ?not ready? next cmd ?not ready? next cmd ls result read memory location xxx berr xxx ms result xxx ?not ready? read (b/w) ??? ms addr ?not ready? ls addr ?not ready? next cmd ?not ready? read memory location xxx berr next cmd result
debug module mcf5213 reference manual, rev. 1.1 26-26 freescale semiconductor preliminary 26.5.3.3.4 write me mory location ( write ) write data to the memory location specified by th e longword address. the address space is defined by baar[tt,tm]. hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword ad dresses are longword-aligned. command formats: 1514131211109876543210 byte0x10x80x00x0 a[31:16] a[15:0] xxxxxxxx d[7:0] word0x10x80x40x0 a[31:16] a[15:0] d[15:0] longword 0x1 0x8 0x8 0x0 a[31:16] a[15:0] d[31:16] d[15:0] figure 26-23. write command format
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-27 preliminary command sequence: figure 26-24. write command sequence operand data: this two-operand inst ruction requires a longword abso lute address that specifies a location to which the data op erand is to be written. byte data is sent as a 16-bit word, justified in the lsb; 16- and 32-bi t operands are sent as 16 and 32 bits, respectively. result data: command complete status is i ndicated by returning 0xffff (with s cleared) when the register wr ite is complete. a value of 0x0001 (with s set) is returned if a bus error occurs. 26.5.3.3.5 dump memory block ( dump ) dump is used with the read command to access large blocks of memory. an initial read is executed to set up the starting address of the block and to retrieve the first result. if an initial read is not executed before the first dump , an illegal command response is returned. the dump command retrieves subsequent operands. the initial addres s is incremented by the operand size ( 1, 2, or 4) and saved in a temporary register. subsequent dump commands use this address, perform the memory read, increment it by the current operand size, and store the update d address in the temporary register. xxx ?not ready? write (long) ??? ms addr ?not ready? ls addr ?not ready? write memory location next cmd ?cmd complete? ms data ?not ready? next cmd ?not ready? xxx berr xxx ?not ready? write (b/w) ??? ms addr ?not ready? ls addr ?not ready? write memory location next cmd ?cmd complete? data ?not ready? next cmd ?not ready? xxx berr ls data ?not ready?
debug module mcf5213 reference manual, rev. 1.1 26-28 freescale semiconductor preliminary note dump does not check for a valid address; it is a valid command only when preceded by nop , read , or another dump command. otherwise, an illegal command response is returned. nop can be used for intercommand padding without corrupting the address pointer. the size field is examined each time a dump command is processed, allowing the operand size to be dynamically altered. command/result formats: command sequence: figure 26-26. dump command sequence operand data: none 15 12 11 8 7 4 3 0 byte command 0x1 0xd 0x0 0x0 result xxxxxxxx d[7:0] word command 0x1 0xd 0x4 0x0 result d[15:0] longword command 0x1 0xd 0x8 0x0 result d[31:16] d[15:0] figure 26-25. dump command/result formats xxx ?not ready? dump (b/w) ??? xxx ?illegal? next cmd ?not ready? next cmd ?not ready? read memory location xxx berr next cmd result xxx ?not ready? dump (long) ??? xxx ?illegal? next cmd ?not ready? next cmd ?not ready? read memory location xxx berr next cmd ms result next cmd ls result
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-29 preliminary result data: requested data is re turned as either a word or longword. byte data is returned in the least-significant byte of a word result. word results return 16 bits of significant data; longword results return 32 bits. a valu e of 0x0001 (with s set) is returned if a bus error occurs. 26.5.3.3.6 fill memory block ( fill ) a fill command is used with the write command to access large bloc ks of memory. an initial write is executed to set up the starting address of th e block and to supply the first operand. the fill command writes subsequent operands. the init ial address is incremented by the op erand size (1, 2, or 4) and saved in a temporary register after the memory write. subsequent fill commands use this address, perform the write, increment it by the current operand size, and store the updated address in the temporary register. if an initial write is not executed preceding the first fill command, the illegal command response is returned. note the fill command does not check for a valid address? fill is a valid command only when preceded by another fill , a nop , or a write command. otherwise, an illegal comma nd response is returned. the nop command can be used for intercommand padding wit hout corrupting the address pointer. the size field is examined each time a fill command is processed, allowing the operand size to be altered dynamically. command formats: 1514131211109876543210 byte 0x1 0xc 0x0 0x0 xxxxxxxx d[7:0] word 0x1 0xc 0x4 0x0 d[15:0] longword 0x1 0xc 0x8 0x0 d[31:16] d[15:0] figure 26-27. fill command format
debug module mcf5213 reference manual, rev. 1.1 26-30 freescale semiconductor preliminary command sequence: figure 26-28. fill command sequence operand data: a single opera nd is data to be writte n to the memory location. byte data is sent as a 16-bit word, justified in the least-si gnificant byte; 16- and 32-bit operands are sent as 16 and 32 bits, respectively. result data: command complete status (0xffff) is returned when the register write is complete. a value of 0x0001 (with s set) is returned if a bus error occurs. 26.5.3.3.7 resume execution ( go ) the pipeline is flushed a nd refilled before normal inst ruction execution resumes. prefetching begins at the current address in the pc and at the current privileg e level. if any register (such as the pc or sr) is altered by a bdm command while the processo r is halted, the u pdated value is used when prefetching resumes. if a go command is issued and the cpu is not halted, the command is ignored. command sequence: figure 26-30. go command sequence 1514131211109876543210 0x0 0xc 0x0 0x0 figure 26-29. go command format xxx ?not ready? fill (b/w) ??? data ?not ready? next cmd ?not ready? write memory location xxx berr next cmd ?cmd complete? xxx ?illegal? next cmd ?not ready? xxx ?not ready? fill (long) ??? ms data ?not ready? ls data ?not ready? write memory location xxx berr next cmd ?cmd complete? xxx ?illegal? next cmd ?not ready? next cmd ?not ready? go ??? next cmd ?cmd complete?
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-31 preliminary operand data: none result data: the command-complete response ( 0xffff) is returned during the next shift operation. 26.5.3.3.8 no operation ( nop ) nop performs no operation and may be us ed as a null command where required. command formats: command sequence: figure 26-32. nop command sequence operand data: none result data: the command-complete response, 0xffff (with s cleared), is returned during the next shift operation. 26.5.3.3.9 synchronize pc to the pst/ddata lines ( sync _ pc ) capture the current pc (program counter) and di splay it on the pst/ddata outputs. after the debug module receives the command, it sends a signal to the coldfire core th at the current pc must be displayed. the core then forces an instruction fetch at the ne xt pc with the address be ing captured in the ddata logic under control of the csr[btb] bits. the specific sequence of pst and ddata values is defined below: 1. debug signals a sync _ pc command is pending. 2. cpu completes the current instruction. 3. cpu forces an instruction fetch to the next pc, generates a pst = $5 value indicating a taken branch and signals ddata. ddata captures the instruction address corresponding to the pc. ddata generates a pst marker ($9?$b) as define d by csr[btb] and displays the captured pc address. this command can be used to dynamically access th e pc for performance monitoring. the execution of this command is considerably less obtrusive to the real-time operation of an application than a halt-cpu/read-pc/resu me command sequence. format: 1514131211109876543210 0x00x00x00x0 figure 26-31. nop command format 1514131211109876543210 0x0 0x0 0x0 0x1 nop ??? next cmd ?cmd complete?
debug module mcf5213 reference manual, rev. 1.1 26-32 freescale semiconductor preliminary command sequence: operand data: none result data: the command comple te response, $ffff (with the stat us bit cleared), is returned during the next shift operation. 26.5.3.3.10 read co ntrol register ( rcreg ) reads the selected control register and returns the 32- bit result. accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. the se cond and third words of the command form a 32-bit address, which the deb ug module uses to generate a special bus cycle to access the specified control register. the 12-bit rc field is the same as that used by the movec instruction. command/result formats: rc encoding: 1514131211109876543210 command 0x2 0x9 0x8 0x0 0x0 0x0 0x0 0x0 0x0 rc result d[31:16] d[15:0] figure 26-33. rcreg command/result formats table 26-20. control register map rc register definition 0x004 access control register (acr0) 0x005 access control register (acr1) 0x800 other stack pointer (other_a7) 0x801 vector base register (vbr) 0x804 mac status register (macsr) 0x805 mac mask register (mask) 0x806 mac accumulator 0 (acc0) 0x80e status register (sr) 0x80f program register (pc) 0xc04 flash base address register (flashbar) 0xc05 ram base address register (rambar) sync_pc ??? next cmd ?cmd complete?
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-33 preliminary command sequence: figure 26-34. rcreg command sequence operand data: the only operand is the 32-bi t rc control register select field. result data: control regist er contents are returned as a l ongword, most-significant word first. the implemented portion of registers smaller than 32 bi ts is guaranteed correct; other bits are undefined. bdm accesses of the stack pointe r registers (a7: ssp, usp) the v2 core supports two unique stac k pointer (a7) registers: the supe rvisor stack pointer (ssp) and the user stack pointer (usp). the hardware implemen tation of these two progr ammable-visible 32-bit registers does not uniquely identify one as the ssp and th e other as the usp. rather, the hardware uses one 32-bit register as the currently-activ e a7 and the other register is name d simply the ?other_a7?. thus, the contents of the two hardware registers is a function of the operating mode of the processor: if sr[s] = 1 then a7 = supervisor stack pointer other_a7 = user stack pointer else a7 = user stack pointer other_a7 = supervisor stack pointer the bdm programming model supp orts reads and writes to the a7 and other_a7 registers directly. it is the responsibility of the external development system to determin e the mapping of the two hardware registers (a7, other_a7) to the two program-visible de finitions (supervisor and us er stack pointers), based on the supervisor bit of the status register. 26.5.3.3.11 write co ntrol register ( wcreg ) the operand (longword) data is written to the specified c ontrol register. the write al ters all 32 register bits. command/result formats: xxx ?not ready? rcreg ??? ms addr ?not ready? ms addr ?not ready? next cmd ?not ready? read control register xxx berr next cmd ms result next cmd ls result
debug module mcf5213 reference manual, rev. 1.1 26-34 freescale semiconductor preliminary command sequence: figure 26-36. wcreg command sequence operand data: this instruction re quires two longword operands. the first selects the register to which the operand data is to be wri tten; the second contains the data. result data: successful write operations return 0xffff. bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001. 26.5.3.3.12 read debug module register ( rdmreg ) read the selected de bug module register and return the 32-bit result. the only va lid register selection for the rdmreg command is csr (drc = 0x00). note that this read of the csr clears csr[fof, trg, halt, bkpt]; as well as the trigger status bits (csr[bstat]) if either a le vel-2 breakpoint ha s been triggered or a level-1 breakpoint has b een triggered and no level-2 breakpoint has been enabled. command/result formats: 1514131211109876543210 command 0x2 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 r c result d[31:16] d[15:0] figure 26-35. wcreg command/result formats xxx ?not ready? wcreg ??? ms addr ?not ready? ms addr ?not ready? write control register next cmd ?cmd complete? ms data ?not ready? next cmd ?not ready? xxx berr ls data ?not ready?
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-35 preliminary table 26-21 shows the definition of drc encoding. command sequence: figure 26-38. rdmreg command sequence operand data: none result data: the contents of th e selected debug register are retu rned as a longword value. the data is returned most-significant word first. 26.5.3.3.13 write debug module register ( wdmreg ) the operand (longword) data is written to the sp ecified debug module register. al l 32 bits of the register are altered by the write. dsclk must be inactive wh ile the debug module register writes from the cpu accesses are performed usi ng the wdebug instruction. command format: table 26-3 shows the definition of the drc write encoding. command sequence: 1514131211109876543210 command 0x2 0xd 100 dr c result d[31:16] d[15:0] figure 26-37. rdmreg command/result formats table 26-21. definition of drc encoding?read drc[4:0] debug register defini tion mnemonic initial state page 0x00 configuration/ status csr 0x0 p. 26-7 0x01?0x1f reserved ? ? ? 1514131211109876543210 0x2 0xc 100 drc d[31:16] d[15:0] figure 26-39. wdmreg bdm command format rdmreg ??? xxx ms result next cmd ls result xxx ?illegal? next cmd ?not ready?
debug module mcf5213 reference manual, rev. 1.1 26-36 freescale semiconductor preliminary figure 26-40. wdmreg command sequence operand data: longword data is written into the specified debug register. the data is supplied most-significant word first. result data: command complete st atus (0xffff) is returned when register write is complete. 26.6 real-time debug support the coldfire family provides s upport debugging real-time applications. for these types of embedded systems, the processor must conti nue to operate during debug. the founda tion of this area of debug support is that while the processor cannot be halted to al low debugging, the system can generally tolerate small intrusions into th e real-time operation. the debug module provides four types of breakpoints?pc with mask, pc without mask, operand address range, and data with mask. these breakpoints can be co nfigured into one- or two- level triggers with the exact trigger response also progr ammable. the debug module programmi ng model can be written from either the external development system using the debug serial interface or from the processor?s supervisor programming model using the wdeb ug instruction. only csr is readable using the external development system. 26.6.1 theory of operation breakpoint hardware can be configured to respond to triggers in several ways . the desired response is programmed into tdr. as shown in table 26-22 , when a breakpoint is triggered, an indication (csr[bstat]) is provided on the ddata output port when it is not displaying ca ptured processor status, operands, or branch addresses. table 26-22. ddata[3:0]/csr[bstat] breakpoint response ddata[3:0] 1 csr[bstat] 1 1 encodings not shown are reserved for future use. breakpoint status 0000 0000 no breakpoints enabled 0010 0001 waiting for level-1 breakpoint 0100 0010 level-1 breakpoint triggered 1010 0101 waiting for level-2 breakpoint 1100 0110 level-2 breakpoint triggered wdmreg ??? ms data ?not ready? ls data ?not ready? xxx ?illegal? next cmd ?not ready? next cmd ?cmd complete?
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-37 preliminary the breakpoint status is also posted in the csr. no te that csr[bstat] is cleared by a csr read when either a level-2 breakpoint is trigge red or a level-1 breakpoint is triggered and a le vel-2 breakpoint is not enabled. status is also cleared by writing to tdr. bdm instructions use the appropriate registers to load and configure breakpoints. as the system operates, a breakpoint trigger generates the response defined in tdr. pc breakpoints are treated in a precise manner?except ion recognition and processi ng are initiated before the excepting instruction is execute d. all other breakpoint events are recognized on the processor?s local bus, but are made pending to the proc essor and sampled like other interr upt conditions. as a result, these interrupts are imprecise. in systems that tolerate the processor being halted, a bdm-entry can be used. with tdr[trc] = 01, a breakpoint trigger causes the core to halt (pst = 0xf). if the processor core cannot be halted, the debug interrupt can be used. with the configuration tdr[trc] = 10 the breakpoint trigger becomes a debug inte rrupt to the processor, which is treated higher than the nonmaskable level-7 interrupt request. as wi th all interrupts, it is made pending until the processor reaches a sample point, which occurs once pe r instruction. again, the hardware forces the pc breakpoint to occur before the targeted instruction ex ecutes. this is possible because the pc breakpoint is enabled when interrupt sampling occurs. for addre ss and data breakpoints, reporting is considered imprecise because several instructi ons may execute after the triggeri ng address or data is detected. as soon as the debug interrupt is recognized, the processor aborts execution and initiates exception processing. this event is signaled externally by th e assertion of a unique pst value (pst = 0xd) for multiple cycles. the core enters emulator mode when exception pro cessing begins. after the standard 8-byte exception stack is created, th e processor fetches a unique exce ption vector, 12, from the vector table. (refer to the coldfire programmer?s reference manual ). execution continues at the instruct ion address in the vector correspondi ng to the breakpoint triggered. all interrupts are ignored while the processor is in emulator mode. the debug in terrupt handler can use supervisor instructions to save the necessary context, such as the state of all program-visible registers into a reserved memory area. when debug interrupt operati ons complete, the rte instruction execut es and the processor exits emulator mode. after the debug interrupt handler completes ex ecution, the external development system can use bdm commands to read the reserved memory locations. if a hardware breakpoint such as a pc trigger is le ft unmodified by the debug interrupt service routine, another debug interrupt is generate d after the completion of the r te instruction. therefore the debug interrupt service routine should clear the respective tdr setting. in the rev. a implementation, if a hardware breakpoint (e.g., a pc trigger) is left unmodified by the debug interrupt service routine, anothe r debug interrupt is generated afte r the rte instruction completes execution. in the rev. b desi gn, the hardware has been modified to inhibit the generati on of another debug interrupt during the first instruction after the rte exit s emulator mode. this beha vior is consistent with the existing logic involving tr ace mode, where the execution of the fi rst instruction occurs before another trace exception is generated. this rev. b enhancemen t disables all hardware breakpoints until the first instruction after the rte has completed executi on, regardless of the programmed trigger response.
debug module mcf5213 reference manual, rev. 1.1 26-38 freescale semiconductor preliminary 26.6.1.1 emulator mode emulator mode is used to facilitate non-intrusive emulat or functionality. this mode can be entered in three different ways: ? setting csr[emu] forces the processor into emulator mode. emu is examined only if rsti is negated and the processor begins reset exception processing. it can be set while the processor is halted before reset exception processing begins. see section 26.5.1, ?cpu halt .? ? a debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins. ? setting csr[trc] forces the processor into emulation mode when trace exception processing begins. while operating in emulation mode, the processor exhibits the following properties: ? all interrupts are ignored, including level-7 interrupts. ? if csr[map] = 1, all caching of memory and the sram module are di sabled. all memory accesses are forced into a sp ecially mapped address space si gnaled by tt = 0x2, tm = 0x5 or 0x6. this includes stack frame writes a nd the vector fetch for the excepti on that forced entry into this mode. the rte instruction exits emulation mode. the proc essor status output port provides a unique encoding for emulator mode entry (0xd) and exit (0x7). 26.6.2 concurrent bdm an d processor operation the debug module supports concurrent operation of both the processo r and most bdm commands. bdm commands may be executed while the processor is r unning, except those followi ng operations that access processor/memory registers: ? read/write address and data registers ? read/write control registers for bdm commands that access memory, the debug module requests the processor?s local bus. the processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debu g module to perform its ac cess. after the debug module bus cycle, the processor reclaims the bus. breakpoint registers must be carefull y configured in a development syst em if the processor is executing. the debug module contains no hardware interlocks, so tdr should be di sabled while breakpoint registers are loaded, after which tdr can be wr itten to define the exact trigger. this prevents spurious breakpoint triggers. because there are no hardware interlocks in the de bug unit, no bdm operations are allowed while the cpu is writing the debug?s register s (dsclk must be inactive).
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-39 preliminary 26.7 processor status, ddata definition this section specifies the coldfire processor and debug modul e?s generation of the pr ocessor status (pst) and debug data (ddata) output on an instruction ba sis. in general, the pst/ddata output for an instruction is defined as follows: pst = 0x1, {pst = [0x89b], ddata= operand} where the {...} definition is optional operand info rmation defined by the setting of the csr. the csr provides capabilities to di splay operands based on reference t ype (read, write, or both). a pst value {0x8, 0x9, or 0xb} identifies th e size and presence of valid data to follow on the ddata output {1, 2, or 4 bytes}. additionally, for certain change-of- flow branch instructions , csr[btb] provides the capability to display the target instruction addr ess on the ddata output {2, 3, or 4 bytes} using a pst value of {0x9, 0xa, or 0xb}. 26.7.1 user instruction set table 26-23 shows the pst/ddata specifica tion for user-mode instructions . rn represents any {dn, an} register. in this definition, the ?y? suffix generall y denotes the source and ?x ? denotes the destination operand. for a given instruction, the optional operand data is displayed only for thos e effective addresses referencing memory. the ?dd? nomencl ature refers to the ddata outputs. table 26-23. pst/ddata specification for user-mode instructions instruction operand syntax pst/ddata add.l y,rx pst = 0x1, {pst = 0xb, dd = source operand} add.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} addi.l #imm,dx pst = 0x1 addq.l #imm,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} addx.l dy,dx pst = 0x1 and.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} and.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} andi.l #imm,dx pst = 0x1 asl.l {dy,#imm},dx pst = 0x1 asr.l {dy,#imm},dx pst = 0x1 bitrev.l dx pst = 0x1 byterev.l dx pst = 0x1 bcc.{b,w} if taken, then pst = 0x5, else pst = 0x1 bchg #imm,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bchg dy,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bclr #imm,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bclr dy,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination}
debug module mcf5213 reference manual, rev. 1.1 26-40 freescale semiconductor preliminary bra.{b,w} pst = 0x5 bset #imm,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bset dy,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} bsr.{b,w} pst = 0x5, {pst = 0xb, dd = destination operand} btst #imm,x pst = 0x1, {pst = 0x8, dd = source operand} btst dy,x pst = 0x1, {pst = 0x8, dd = source operand} clr.b x pst = 0x1, {pst = 0x8, dd = destination operand} clr.l x pst = 0x1, {pst = 0xb, dd = destination operand} clr.w x pst = 0x1, {pst = 0x9, dd = destination operand} cmp.l y,rx pst = 0x1, {pst = 0xb, dd = source operand} cmpi.l #imm,dx pst = 0x1 divs.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} divs.w y,dx pst = 0x1, {pst = 0x9, dd = source operand} divu.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} divu.w y,dx pst = 0x1, {pst = 0x9, dd = source operand} eor.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} eori.l #imm,dx pst = 0x1 ext.l dx pst = 0x1 ext.w dx pst = 0x1 extb.l dx pst = 0x1 ff1.l dx pst = 0x1 jmp x pst = 0x5, {pst = [0x9ab], dd = target address} 1 jsr x pst = 0x5, {pst = [0x9ab], dd = target address}, {pst = 0xb , dd = destination operand} 1 lea y,ax pst = 0x1 link.w ay,#imm pst = 0x1, {pst = 0xb, dd = destination operand} lsl.l {dy,#imm},dx pst = 0x1 lsr.l {dy,#imm},dx pst = 0x1 move.b y,x pst = 0x1, {pst = 0x8, dd = source}, {pst = 0x8, dd = destination} move.l y,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} move.w y,x pst = 0x1, {pst = 0x9, dd = source}, {pst = 0x9, dd = destination} move.w ccr,dx pst = 0x1 move.w {dy,#imm},ccr pst = 0x1 table 26-23. pst/ddata specification for user-mode instructions (continued) instruction operand syntax pst/ddata
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-41 preliminary movem.l #list,x pst = 0x1, {pst = 0xb, dd = destination},... 2 movem.l y,#list pst = 0x1, {pst = 0xb, dd = source},... 2 moveq #imm,dx pst = 0x1 muls.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} muls.w y,dx pst = 0x1, {pst = 0x9, dd = source operand} mulu.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} mulu.w y,dx pst = 0x1, {pst = 0x9, dd = source operand} neg.l dx pst = 0x1 negx.l dx pst = 0x1 nop pst = 0x1 not.l dx pst = 0x1 or.l y,dx pst = 0x1, {pst = 0xb, dd = source operand} or.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} ori.l #imm,dx pst = 0x1 pea y pst = 0x1, {pst = 0xb, dd = destination operand} pulse pst = 0x4 rems.l y,dx:dw pst = 0x1, {pst = 0xb, dd = source operand} remu.l y,dx:dw pst = 0x1, {pst = 0xb, dd = source operand} rts pst = 0x1, {pst = 0xb, dd = source operand}, pst = 0x5, {pst = [0x9ab], dd = target address} scc dx pst = 0x1 sub.l y,rx pst = 0x1, {pst = 0xb, dd = source operand} sub.l dy,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} subi.l #imm,dx pst = 0x1 subq.l #imm,x pst = 0x1, {pst = 0xb, dd = source}, {pst = 0xb, dd = destination} subx.l dy,dx pst = 0x1 swap dx pst = 0x1 trap #imm pst = 0x1 3 trapf pst = 0x1 tst.b x pst = 0x1, {pst = 0x8, dd = source operand} tst.l x pst = 0x1, {pst = 0xb, dd = source operand} tst.w x pst = 0x1, {pst = 0x9, dd = source operand} unlk ax pst = 0x1, {pst = 0xb, dd = destination operand} table 26-23. pst/ddata specification for user-mode instructions (continued) instruction operand syntax pst/ddata
debug module mcf5213 reference manual, rev. 1.1 26-42 freescale semiconductor preliminary exception processingpst = 0xc,{pst = 0xb,dd = destination},// stack frame {pst = 0xb,dd = destination},// stack frame {pst = 0xb,dd = source},// vector read pst = 0x5,{pst = [0x9ab],dd = target}// handler pc the pst/ddata specification for the reset exception is shown below: exception processingpst = 0xc, pst = 0x5,{pst = [0x9ab],dd = target} // handler pc the initial references at address 0 and 4 are never captured nor displa yed since these ac cesses are treated as instruction fetches. for all types of exception processing, the pst = 0xc value is driven at all times, unless the pst output is needed for one of the optional marker values or for the taken branch indicator (0x5). table 26-24 shows the pst/ddata specification fo r multiply-accumulat e instructions. wddata.b y pst = 0x4, {pst = 0x8, dd = source operand wddata.l y pst = 0x4, {pst = 0xb, dd = source operand wddata.w y pst = 0x4, {pst = 0x9, dd = source operand 1 for jmp and jsr instructions, the optiona l target instruction address is disp layed only for those effective address fields defining variant addressing modes. this includes the followi ng x values: (an), (d16,an), (d8,an,xi), (d8,pc,xi). 2 for move multiple instructions (movem), the processor au tomatically generates line-sized transfers if the operand address reaches a 0-modulo-16 boundary and there are four or mo re registers to be transferred. for these line-sized transfers, the operand data is never captured nor displayed, regardless of the csr value. the automatic line-sized burst transfers are provided to maximize performance during these sequential memory access operations. 3 during normal exception processing, the pst output is driven to a 0xc indicating the exception processing state. the exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed. table 26-24. pst/ddata specif ication for mac instructions instruction operand syntax pst/ddata mac.l ry,rx,accx pst = 0x1 mac.l ryrx,,rw,accx pst = 0x1, {pst = 0xb, dd = source operand} mac.w ry,rx,accx pst = 0x1 mac.w ry,rx,,rw,accx pst = 0x1, {pst = 0xb, dd = source operand} move.l y,accx pst = 0x1 move.l accy,accx pst = 0x1 move.l y,macr pst = 0x1 move.l y,mask pst = 0x1 move.l y,accext01 pst = 0x1 move.l y,accext23 pst = 0x1 table 26-23. pst/ddata specification for user-mode instructions (continued) instruction operand syntax pst/ddata
debug module mcf5213 reference manual, rev. 1.1 freescale semiconductor 26-43 preliminary 26.7.2 supervisor instruction set the supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below. the pst/ddata specificati on for these opcodes is shown in table 26-25 . the move-to-sr, stldsr, and rte in structions include an optional pst = 0x3 value, indicating an entry into user mode. additionally, if th e execution of a rte instruction retu rns the processor to emulator mode, a multiple-cycle status of 0xd is signaled. similar to the exception processing mode, the stopped state (pst = 0xe) and the halted state (pst = 0xf) display this status throughout th e entire time the coldfire processor is in the given mode. 26.8 freescale-recommended bdm pinout the coldfire bdm connector, figure 26-41 , is a 26-pin berg connector arranged 2 13. move.l accy,rx pst = 0x1 move.l macsr,ccr pst = 0x1 move.l macsr,rx pst = 0x1 move.l mask,rx pst = 0x1 move.l accext01,rx pst = 0x1 move.l accext23,rx pst = 0x1 msac.l ry,rx,accx pst = 0x1 msac.l ry,rx,,rw,accx pst = 0x1, {pst = 0xb, dd = source operand} msac.w ry,rx,accx pst = 0x1 msac.w ry,rx,,rw,accx pst = 0x1, {pst = 0xb, dd = source operand} table 26-25. pst/ddata specification for supervisor-mode instructions instruction operand syntax pst/ddata cpushl pst = 0x1 halt pst = 0x1, pst = 0xf move.w sr,dx pst = 0x1 move.w {dy,#imm},sr pst = 0x1, {pst = 0x3} movec ry,rc pst = 0x1 rte pst = 0x7, {pst = 0xb, dd = source operand}, {pst = 3}, { pst =0xb, dd =source operand}, pst = 0x5, {[pst = 0x9ab], dd = target address} stldsr.w #imm pst = 0x1, {pst = 0xa, dd = destination operand, pst = 0x3} stop #imm pst = 0x1, pst = 0xe wdebug y pst = 0x1, {pst = 0xb, dd = source, pst = 0xb, dd = source} table 26-24. pst/ddata specification for mac instructions (continued) instruction operand syntax pst/ddata
debug module mcf5213 reference manual, rev. 1.1 26-44 freescale semiconductor preliminary figure 26-41. recommended bdm connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 developer reserved 1 gnd gnd rsti pad-voltage 2 gnd pst2 pst0 ddata2 ddata0 freescale reserved gnd core-voltage bkpt dsclk developer reserved 1 dsi dso pst3 pst1 ddata3 ddata1 gnd freescale reserved 2 supplied by target 1 pins reserved for bdm developer use. ta pstclk
mcf5213 reference manual, rev. 1.1 freescale semiconductor 27-1 preliminary chapter 27 ieee 1149.1 test access port (jtag) 27.1 introduction the joint test action group or jtag is a dedicated user -accessible test logic, th at complies with the ieee 1149.1 standard for boundary-scan testability, to help with system diagnostic and manufacturing testing. this architecture provides access to all data and chip control pins fr om the board-edge connector through the standard four-pin test access por t (tap) and the jtag reset pin, trst . 27.1.1 block diagram figure 27-1 shows the block diagram of the jtag module. figure 27-1. jtag block diagram tdo/dso bkpt 5-bit tap instruction register 40 1-bit bypass register 32-bit idcode register trst /dsclk tclk tms/bkpt 0 31 0 tap controller tdi/dsi 1 0 jtag module to debug module 5-bit tap instruction decoder 1 0 disable dsclk force bkpt = 1 dsi = 0 jtag_en dso dsi dsclk 1-bit test_ctrl register boundary scan register
ieee 1149.1 test access port (jtag) mcf5213 reference manual, rev. 1.1 27-2 freescale semiconductor preliminary 27.1.2 features the basic features of the jtag module are the following: ? performs boundary-scan operations to te st circuit board electrical continuity ? bypasses instruction to reduce the sh ift register path to a single cell ? sets chip output pins to safety stat es while executing the bypass instruction ? samples the system pins during operati on and transparently shift out the result ? selects between jtag tap controller and background debug module (bdm) using a dedicated jtag_en pin 27.1.3 modes of operation the jtag_en pin can select between the following modes of operation: ? jtag mode (jtag_en = 1) ? bdm - background debug mode (for more information, refer to section 26.5, ?background debug mode (bdm)? ) (jtag_en = 0) 27.2 external signal description the jtag module has five input and one out put external signals, as described in table 27-1 . 27.2.1 jtag enable (jtag_en) the jtag_en pin selects between the debug module and jtag. if jtag _en is low, the debug module is selected; if it is high, the jtag is selected. table 27-2 summarizes the pin f unction selected depending upon jtag_en logic state. table 27-1. signal properties name direction functio n reset state pull up jtag_en input jtag/bdm selector input ? ? tclk input jtag test clock input ? active tms/bkpt input jtag test mode select / bdm breakpoint ? active tdi/dsi input jtag test data input / bdm development serial input ? active trst /dsclk input jtag test reset input / bdm development serial clock ? active tdo/dso output jtag test data output / bdm development serial output hi-z / 0 ?
ieee 1149.1 test access port (jtag) mcf5213 reference manual, rev. 1.1 freescale semiconductor 27-3 preliminary when one module is selected, the input s into the other module are disabled or forced to a known logic level as shown in table 27-3 , in order to disable the corresponding module. note the jtag_en does not support dyna mic switching between jtag and bdm modes. 27.2.2 test clock input (tclk) the tclk pin is a dedicated jtag clock input to s ynchronize the test logic. pulses on tclk shift data and instructions into the tdi pin on the rising edge and out of the tdo pin on the falling edge. tclk is independent of the processo r clock. the tclk pin ha s an internal pull-up resistor and holding tclk high or low for an indefinite period does not cause jtag test logic to lose state information. 27.2.3 test mode select /breakpoint (tms/bkpt ) the tms pin is the test mode sel ect input that sequences the tap st ate machine. tms is sampled on the rising edge of tclk. the tms pin ha s an internal pull-up resistor. the bkpt pin is used to request an exte rnal breakpoint. assertion of bkpt puts the processor into a halted state after the current instruction completes. 27.2.4 test data input/develo pment serial input (tdi/dsi) the tdi pin receives serial test and data, which is sampled on the rising edge of tclk. register values are shifted in least significant bit (lsb) first. the tdi pin has an internal pull-up resistor. the dsi pin provides data input for the debug module serial communication port. table 27-2. pin function selected jtag_en = 0 jtag_en = 1 pin name module selected bdm jtag ? pin function ? bkpt dsi dso dsclk tclk tms tdi tdo trst tclk bkpt dsi dso dsclk table 27-3. signal state to the disable module jtag_en = 0 jtag_en = 1 disabling jtag trst = 0 tms = 1 ? disabling bdm ? disable dsclk dsi = 0 bkpt = 1
ieee 1149.1 test access port (jtag) mcf5213 reference manual, rev. 1.1 27-4 freescale semiconductor preliminary 27.2.5 test reset/development serial clock (trst /dsclk) the trst pin is an active low asynchronous reset input with an internal pull-up resistor that forces the tap controller to the test-logic-reset state. the dsclk pin clocks the serial communication por t to the debug module. ma ximum frequency is 1/5 the processor clock speed. at the rising edge of dsclk, the data input on dsi is sampled and dso changes state. 27.2.6 test data output/develop ment serial ou tput (tdo/dso) the tdo pin is the lsb-first data output. data is cl ocked out of tdo on the fa lling edge of tclk. tdo is tri-stateable and is actively driven in the shift-ir and shift-dr controller states. the dso pin provides serial output data in bdm mode. 27.3 memory map/register definition the jtag module registers are not memory mapped and are only accessible through the tdo/dso pin. 27.3.1 instruction shift register (ir) the jtag module uses a -bit shift register with no pa rity. the ir transfers its value to a parallel hold register and applies an instruction on the falling edge of tclk when the tap state machine is in the update-ir state. to load an instruct ion into the shift portion of the ir, place the serial da ta on the tdi pin before each rising edge of tc lk. the msb of the ir is the bit closest to the tdi pin, and the lsb is the bit closest to the tdo pin. see section 27.4.3, ?jtag instructions? for a list of possible instruction codes. 27.3.2 idcode register the idcode is a read-only register; its value is chip dependent. for more information, see section 27.4.3.1, ?idcode instruction .? ir[4:0]: 0_0001 (idcode) access: user read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r prn dc pin jedec id w reset0000011101 device dependent 000000011101 figure 27-2. idcode register
ieee 1149.1 test access port (jtag) mcf5213 reference manual, rev. 1.1 freescale semiconductor 27-5 preliminary 27.3.3 bypass register the bypass register is a single-bit shift register path from tdi to tdo when the bypass, clamp, or highz instructions are selected. after entry into the capture-dr state, the single-bit shift register is set to a logic 0. therefore, the first bit shifted out after selecting the bypass regist er is always a logic 0. 27.3.4 test_ctrl register the test_ctrl register is a 1-bit shift register path from tdi to tdo when the enable_test_ctrl instruction is selected. the tes t_ctrl transfers its value to a parallel hold register on the rising edge of tclk when the tap st ate machine is in the update-dr state. the dse bit selects the drive strength used in jtag mode. 27.3.5 boundary scan register the boundary scan register is connected between tdi and tdo when the extest or sample/preload instruction is select ed. it captures input pin data, fo rces fixed values on output pins, and selects a logic value and direct ion for bidirectional pins or hi gh impedance for tri-stated pins. the boundary scan register cont ains bits for bonded-out and non bonded-out signals excluding jtag signals, analog signals, power supplie s, compliance enable pins, devi ce configuration pins, and clock signals. table 27-4. idcode field descriptions field description 31?28 prn part revision number. indicate the revision number of the device. 27?22 dc freescale design center number. 21?12 pin part identification number. indicate the device number. 11?1 jedec joint electron device engineering council id bits. indicate the reduced jedec id for freescale. 0 id idcode register id. this bit is set to 1 to identify the register as the idcode regist er and not the bypass register according to the ieee standard 1149.1. ir[4:0]: 0_0110 access: user read-only 0 r dse w reset 0 figure 27-3. 1-bit test_ctrl register
ieee 1149.1 test access port (jtag) mcf5213 reference manual, rev. 1.1 27-6 freescale semiconductor preliminary 27.4 functional description 27.4.1 jtag module the jtag module consists of a tap controller state machine, which is responsible for generating all control signals that execute the jtag inst ructions and read/wr ite data registers. 27.4.2 tap controller the tap controller is a state machine that changes state based on the sequence of logical values on the tms pin. figure 27-4 shows the machine?s states. the value show n next to each state is the value of the tms signal sampled on the rising edge of the tclk signal. asserting the trst signal asynchronously resets the tap contro ller to the test-logic-reset state. as figure 27-4 shows, holding tms at logic 1 while clocking tclk through at least five rising edges also causes the state machine to en ter the test-logic-reset state, whatever the initial state.
ieee 1149.1 test access port (jtag) mcf5213 reference manual, rev. 1.1 freescale semiconductor 27-7 preliminary figure 27-4. tap controller state machine flow 27.4.3 jtag instructions table 27-5 describes public and private instructions. 27.4.3.1 idcode instruction the idcode instruction selects the 32-bit idcode register for connect ion as a shift path between the tdi and tdo pin. this instruction allows interrogation of the mcu to determine its version number and other part identification da ta. the shift register lsb is forced to logic 1 on the rising edge of tclk following entry into the cap ture-dr state. therefore, the first bit to be shifted out after selecting the idcode register is always a logic 1. the remaining 31 bits are also forced to fixed values on the rising edge of tclk following entr y into the capture-dr state. run-test/idle test-logic-reset 1 1 select dr-scan capture-dr exit1-dr pause-dr update-dr select ir-scan shift-dr exit2-dr capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 0 0 1 1 0 0 0 1 1 10 0 0 1 1 0 0 1 1 0 1 0 1 10 1 1 0 0 1 0
ieee 1149.1 test access port (jtag) mcf5213 reference manual, rev. 1.1 27-8 freescale semiconductor preliminary idcode is the default instruction placed into the inst ruction register when the tap resets. thus, after a tap reset, the idcode register is selected automatically. 27.4.3.2 sample/preload instruction the sample/preload instru ction has two functions: ? preload - initialize the boundary scan register update cells before selecting extest or clamp. this is achieved by ignoring the data shifting out on the tdo pin and shifting in initialization data. the upda te-dr state and the falling edge of tclk can then transfer this data to the update cells. the data is applied to the ex ternal output pins by the extest or clamp instruction. 27.4.3.3 extest instruction the external test (extest) instruction selects the b oundary scan register. it fo rces all output pins and bidirectional pins configured as outputs to the values preloaded wi th the sample/preload instruction and held in the boundary scan update registers. extest can also confi gure the direction of bidirectional pins and establish high-impedance st ates on some pins. extest asserts internal reset for the mcu system logic to force a predictable internal state wh ile performing external boundary scan operations. 27.4.3.4 enable_test_ctrl instruction the enable_test_ctrl instruction selects a -bit shift register (test_ct rl) for connection as a shift path between the tdi and tdo pin. when the user transitions the tap controller to the update_dr state, the register transfers its value to a parallel hold register. 27.4.3.5 highz instruction the highz instruction eliminates the need to bac kdrive the output pins during circuit-board testing. highz turns off all output drivers, including the 2- state drivers, and selects the bypass register. highz also asserts internal reset for the mcu system logic to force a pred ictable internal state. 27.4.3.6 clamp instruction the clamp instruction selects the 1- bit bypass register and asserts inte rnal reset while simultaneously forcing all output pins and bidirecti onal pins configured as outputs to th e fixed values that are preloaded and held in the boundary scan update register. clam p enhances test efficiency by reducing the overall shift path to a single b it (the bypass register) while conducting an extest type of instruction through the boundary scan register. 27.4.3.7 bypass instruction the bypass instruction selects the bypass register, creating a single-bit shift register path from the tdi pin to the tdo pin. bypass enhances test efficiency by reducing the overall shift path when a device other than the coldfire processor is the device under test on a board design with multiple chips on the overall boundary scan chain. the shift register lsb is fo rced to logic 0 on the rising edge of tclk after
ieee 1149.1 test access port (jtag) mcf5213 reference manual, rev. 1.1 freescale semiconductor 27-9 preliminary entry into the capture-dr state. therefore, the first bit shifted out after select ing the bypass register is always logic 0. this differen tiates parts that support an idcode regi ster from parts that support only the bypass register. 27.5 initialization/application information 27.5.1 restrictions the test logic is a static logic design, and tclk can be stopped in either a high or low state without loss of data. however, the system cloc k is not synchronized to tclk in ternally. any mixe d operation using both the test logic and the system functi onal logic requires external synchronization. using the extest instruction requires a circuit-board test environment that avoids devi ce-destructive configurations in which mcu output drivers ar e enabled into actively driven networks. low-power stop mode considerations: ? the tap controller must be in th e test-logic-reset state to either enter or remain in the low-power stop mode. leaving the test-logic-reset state negate s the ability to achieve low-power, but does not otherwise affect de vice functionality. ? the tclk input is not blocke d in low-power stop mode. to c onsume minimal power, the tclk input should be externally connected to ev dd . ? the tms, tdi, and trst pins include on-chip pull-up resist ors. for minimal power consumption in low-power stop mode, these three pi ns should be either connected to ev dd or left unconnected. 27.5.2 nonscan chain operation keeping the tap controller in the test -logic-reset state ensures that the s can chain test logic is transparent to the system logic. it is recomm ended that tms, tdi, tclk, and trst be pulled up. trst could be connected to ground. however, si nce there is a pull-up on trst , some amount of current results. the internal power-on reset input initia lizes the tap controller to the test-logic-reset state on power-up without asserting trst .
ieee 1149.1 test access port (jtag) mcf5213 reference manual, rev. 1.1 27-10 freescale semiconductor preliminary
mcf5213 reference manual, rev. 1.1 freescale semiconductor a-1 preliminary appendix a register memory map table a-1 summarizes the address, name, and byte assi gnment for registers within the mcf5213 cpu space. table a-2 lists an overview of the memory map for the on-chip modules, and table a-3 is a detailed memory map including all of th e registers for on-chip modules. table a-1. cpu space register memory map address name mnemonic size cpu @ 0x002 cache control register cacr 32 cpu @ 0x004 access control register 0 acr0 32 cpu @ 0x005 access control register 1 acr1 32 cpu @ 0x800 other stack pointer other_a7 32 cpu @ 0x801 vector base register vbr 32 cpu @ 0x804 mac status register macsr 8 cpu @ 0x805 mac mask register mask 16 cpu @ 0x806 mac accumulator 0 acc0 16 cpu @ 0x80e status register sr 16 cpu @ 0x80f program counter pc 32 cpu @ 0xc04 flash base address register flashbar 32 cpu @ 0xc05 ram base address register rambar 32
register memory map mcf5213 reference manual, rev. 1.1 a-2 freescale semiconductor preliminary table a-2. module memory map overview address module size 0x0000_0000 on-chip flash/ram array 1g ipsbar + 0x00_0000 system control module 64 bytes ipsbar + 0x00_0040 reserved 64 bytes ipsbar + 0x00_0080 reserved 128 bytes ipsbar + 0x00_0100 dma (channel 0) 64 bytes ipsbar + 0x00_0110 dma (channel 1) 64 bytes ipsbar + 0x00_0120 dma (channel 2) 64 bytes ipsbar + 0x00_0130 dma (channel 3) 64 bytes ipsbar + 0x00_0140 reserved 196 bytes ipsbar + 0x00_0200 uart0 64 bytes ipsbar + 0x00_0240 uart1 64 bytes ipsbar + 0x00_0280 uart2 64 bytes ipsbar + 0x00_02c0 reserved 64 bytes ipsbar + 0x00_0300 i 2 c64 bytes ipsbar + 0x00_0340 qspi 64 bytes ipsbar + 0x00_0140 reserved 128 bytes ipsbar + 0x00_0400 dma timer 0 64 bytes ipsbar + 0x00_0440 dma timer 1 64 bytes ipsbar + 0x00_0480 dma timer 2 64 bytes ipsbar + 0x00_04c0 dma timer 3 64 bytes ipsbar + 0x00_0500 reserved 1792 ipsbar + 0x00_0c00 interrupt controller 0 256 bytes ipsbar + 0x00_0d00 reserved 256 ipsbar + 0x00_0e00 reserved 256 ipsbar + 0x00_0f00 global interrupt acknowledge cycles 256 bytes ipsbar + 0x00_1000 reserved 1m-4k ipsbar + 0x10_0000 ports 64k ipsbar + 0x11_0000 reset controller, chip configuration, and power management 64k ipsbar + 0x12_0000 clock module 64k ipsbar + 0x13_0000 edge port 64k ipsbar + 0x14_0000 reserved 64k ipsbar + 0x15_0000 programmable interval timer 0 64k ipsbar + 0x16_0000 programmable interval timer 1 64k ipsbar + 0x17_0000 reserved 64k ipsbar + 0x18_0000 reserved 64k
register memory map mcf5213 reference manual, rev. 1.1 freescale semiconductor a-3 preliminary ipsbar + 0x19_0000 adc 64k ipsbar + 0x1a_0000 general purpose timer a 64k ipsbar + 0x1b_0000 pwm 64k ipsbar + 0x1c_0000 flexcan 64k ipsbar + 0x1d_0000 cfm (fla sh) control registers 64k ipsbar + 0x1e_0000 reserved 63m+128k ipsbar + 0x400_0000 cfm (flash) memory for ips reads and writes 512k table a-3. register memory map address name mnemonic size scm registers ipsbar + 0x000 internal peripheral s ystem base address register ipsbar 32 ipsbar + 0x008 copy of rambar rambar 32 ipsbar + 0x00c reserved ? ipsbar + 0x010 core reset status register crsr 8 ipsbar + 0x011 core watchdog control register cwcr 8 ipsbar + 0x012 low-power interr upt control register lpicr 8 ipsbar + 0x013 core watchdog service register cwsr 8 ipsbar + 0x014 dma request co ntrol register dmareqc 32 ipsbar + 0x01c default bus master park register mpark 32 ipsbar + 0x020 master pr ivilege register mpr 8 ipsbar + 0x024 peripheral access control register 0 pacr0 8 ipsbar + 0x025 peripheral access control register 1 pacr1 8 ipsbar + 0x026 peripheral access control register 2 pacr2 8 ipsbar + 0x027 peripheral access control register 3 pacr3 8 ipsbar + 0x028 peripheral access control register 4 pacr4 8 ipsbar + 0x02a peripheral access control register 5 pacr5 8 ipsbar + 0x02b peripheral access control register 6 pacr6 8 ipsbar + 0x02c peripheral access control register 7 pacr7 8 ipsbar + 0x02e peripheral access control register 8 pacr8 8 ipsbar + 0x030 grouped peripheral a ccess control register 0 gpacr0 8 ipsbar + 0x031 grouped peripheral a ccess control register 1 gpacr1 8 dma registers table a-2. module memory map overview (continued) address module size
register memory map mcf5213 reference manual, rev. 1.1 a-4 freescale semiconductor preliminary ipsbar + 0x100 source address register 0 sar0 32 ipsbar + 0x104 destination address register 0 dar0 32 ipsbar + 0x108 byte count register 0 bcr0 32 ipsbar + 0x10c dma status register 0 dsr0 8 ipsbar + 0x120 source address register 1 sar1 32 ipsbar + 0x124 destination address register 1 dar1 32 ipsbar + 0x128 byte count register 1 bcr1 32 ipsbar + 0x12c dma status register 1 dsr1 8 ipsbar + 0x130 source address register 2 sar2 32 ipsbar + 0x134 destination address register 2 dar2 32 ipsbar + 0x138 byte count register 2 bcr2 32 ipsbar + 0x13c dma status register 2 dsr2 8 ipsbar + 0x140 source address register 3 sar3 32 ipsbar + 0x144 destination address register 3 dar3 32 ipsbar + 0x148 byte count register 3 bcr3 32 ipsbar + 0x14c dma status register 3 dsr3 8 uart registers ipsbar + 0x200 uart mode register 0 1 umr10, umr20 8 ipsbar + 0x204 (read) uart status register 0 usr0 8 (write) uart clock select register 0 1 ucsr0 8 ipsbar + 0x208 (read) reserved 8 (write) uart command register 0 ucr0 8 ipsbar + 0x20c (read) uart receive buffer 0 urb0 8 (write) uart transmit buffer 0 utb0 8 ipsbar + 0x210 (read) uart input port change register 0 uipcr0 8 (write) uart auxiliary control register 0 1 uacr0 8 ipsbar + 0x214 (read) uart interr upt status register 0 uisr0 8 (write) uart interrupt mask register 0 uimr0 8 ipsbar + 0x218 (read) reserved 8 uart baud rate generator register 10 ubg10 8 ipsbar + 0x21c (read) reserved 8 uart baud rate generator register 20 ubg20 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 freescale semiconductor a-5 preliminary ipsbar + 0x234 (read) uart input port register 0 uip0 8 (write) reserved 8 ipsbar + 0x238 (read) reserved 8 (write) uart output port bit set command register 0 uop10 8 ipsbar + 0x23c (read) reserved 8 (write) uart output port bit reset command register 0 uip00 8 ipsbar + 0x240 uart mode registers 1 1 umr11, umr21 8 ipsbar + 0x244 (read) uart status register 1 usr1 8 (write) uart clock select register 1 1 ucsr1 8 ipsbar + 0x248 (read) reserved 8 (write) uart command register 1 ucr1 8 ipsbar + 0x24c (uart/read) uart receive buffer 1 urb1 8 (uart/write) uart transmit buffer 1 utb1 8 ipsbar + 0x250 (read) uart input port change register 1 uipcr1 8 (write) uart auxiliary control register 1 1 uacr1 8 ipsbar + 0x254 (read) uart interr upt status register 1 uisr1 8 (write) uart interrupt mask register 1 uimr1 8 ipsbar + 0x258 (read) reserved 8 uart baud rate generator register 11 ubg11 8 ipsbar + 0x25c (read) reserved 8 uart baud rate generator register 21 ubg21 8 ipsbar + 0x274 (read) uart input port register 1 uip1 8 (write) reserved 8 ipsbar + 0x278 (read) reserved 8 (write) uart output port bit set command register 1 uop11 8 ipsbar + 0x27c (read) reserved 8 (write) uart output port bit reset command register 1 uip01 8 ipsbar + 0x280 uart mode register 2 1 umr12, umr22 8 ipsbar + 0x284 (read) uart status register 2 usr2 8 (write) uart clock select register 2 1 ucsr2 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 a-6 freescale semiconductor preliminary ipsbar + 0x288 (read) reserved 8 (write) uart command register 2 ucr2 8 ipsbar + 0x28c (read) uart receive buffer 2 urb2 8 (write) uart transmit buffer 2 utb2 8 ipsbar + 0x290 (read) uart input port change register 2 uipcr2 8 (write) uart auxiliary control register 2 1 uacr2 8 ipsbar + 0x294 (read) uart interr upt status register 2 uisr2 8 (write) uart interrupt mask register 2 uimr2 8 ipsbar + 0x298 (read) reserved 8 uart baud rate generator register 12 ubg12 8 ipsbar + 0x29c (read) reserved 8 uart baud rate generator register 22 ubg22 8 ipsbar + 0x2b4 (read) uart input port register 2 uip2 8 (write) reserved 8 ipsbar + 0x2b8 (read) reserved 8 (write) uart output port bit set command register 2 uop12 8 ipsbar + 0x2bc (read) reserved 8 (write) uart output port bit reset command register 2 uip02 8 i 2 c registers ipsbar + 0x300 i 2 c address register i2adr 8 ipsbar + 0x304 i 2 c frequency divider register i2fdr 8 ipsbar + 0x308 i 2 c control register i2cr 8 ipsbar + 0x30c i 2 c status register i2sr 8 ipsbar + 0x310 i 2 c data i/o register i2dr 8 qspi registers ipsbar + 0x340 qspi m ode register qmr 16 ipsbar + 0x344 qspi de lay register qdlyr 16 ipsbar + 0x348 qspi wrap register qwr 16 ipsbar + 0x34c qspi interrupt register qir 16 ipsbar + 0x350 qspi address register qar 16 ipsbar + 0x354 qspi da ta register qdr 16 dma timer registers table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 freescale semiconductor a-7 preliminary ipsbar + 0x400 dma timer mode register 0 dtmr0 16 ipsbar + 0x402 dma timer extended mode register 0 dtxmr0 8 ipsbar + 0x403 dma timer event register 0 dter0 8 ipsbar + 0x404 dma timer reference register 0 dtrr0 32 ipsbar + 0x408 dma timer ca pture register 0 dtcr0 32 ipsbar + 0x40c dma timer counter register 0 dtcn0 32 ipsbar + 0x440 dma timer mode register 1 dtmr1 16 ipsbar + 0x442 dma timer extended mode register 1 dtxmr1 8 ipsbar + 0x443 dma timer event register 1 dter1 8 ipsbar + 0x444 dma timer reference register 1 dtrr1 32 ipsbar + 0x448 dma timer ca pture register 1 dtcr1 32 ipsbar + 0x44c dma timer counter register 1 dtcn1 32 ipsbar + 0x480 dma timer mode register 2 dtmr2 16 ipsbar + 0x482 dma timer extended mode register 2 dtxmr2 8 ipsbar + 0x483 dma timer event register 2 dter2 8 ipsbar + 0x484 dma timer reference register 2 dtrr2 32 ipsbar + 0x488 dma timer ca pture register 2 dtcr2 32 ipsbar + 0x48c dma timer counter register 2 dtcn2 32 ipsbar + 0x4c0 dma timer mode register 3 dtmr3 16 ipsbar + 0x4c2 dma timer extended mode register 3 dtxmr3 8 ipsbar + 0x4c3 dma timer event register 3 dter3 8 ipsbar + 0x4c4 dma timer reference register 3 dtrr3 32 ipsbar + 0x4c8 dma timer capture register 3 dtcr3 32 ipsbar + 0x4cc dma timer co unter register 3 dtcn3 32 interrupt controller 0 ipsbar + 0xc00 interrupt pending register high 0 iprh0 32 ipsbar + 0xc04 interrupt pending register low 0 iprl0 32 ipsbar + 0xc08 interrupt mask register high 0 imrh0 32 ipsbar + 0xc0c interrupt mask register low 0 imrl0 32 ipsbar + 0xc10 interrupt force register high 0 intfrch0 32 ipsbar + 0xc14 interrupt force register low 0 intfrcl0 32 ipsbar + 0xc18 interrupt level request register 0 ilrr0 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 a-8 freescale semiconductor preliminary ipsbar + 0xc19 interrupt acknowledge le vel and priority register 0 iacklpr0 8 ipsbar + 0xc41 interrupt control register 0-01 icr001 8 ipsbar + 0xc42 interrupt control register 0-02 icr002 8 ipsbar + 0xc43 interrupt control register 0-03 icr003 8 ipsbar + 0xc44 interrupt control register 0-04 icr004 8 ipsbar + 0xc45 interrupt control register 0-05 icr005 8 ipsbar + 0xc46 interrupt control register 0-06 icr006 8 ipsbar + 0xc47 interrupt control register 0-07 icr007 8 ipsbar + 0xc48 interrupt control register 0-08 icr008 8 ipsbar + 0xc49 interrupt control register 0-09 icr009 8 ipsbar + 0xc4a interrupt cont rol register 0-10 icr010 8 ipsbar + 0xc4b interrupt cont rol register 0-11 icr011 8 ipsbar + 0xc4c interrupt cont rol register 0-12 icr012 8 ipsbar + 0xc4d interrupt cont rol register 0-13 icr013 8 ipsbar + 0xc4e interrupt cont rol register 0-14 icr014 8 ipsbar + 0xc4f interrupt control register 0-15 icr015 8 ipsbar + 0xc51 interrupt control register 0-17 icr017 8 ipsbar + 0xc52 interrupt control register 0-18 icr018 8 ipsbar +0xc53 interrupt cont rol register 0-19 icr019 8 ipsbar + 0xc54 interrupt control register 0-20 icr020 8 ipsbar + 0xc55 interrupt control register 0-21 icr021 8 ipsbar + 0xc56 interrupt control register 0-22 icr022 8 ipsbar + 0xc57 interrupt control register 0-23 icr023 8 ipsbar + 0xc58 interrupt control register 0-24 icr024 8 ipsbar + 0xc59 interrupt control register 0-25 icr025 8 ipsbar + 0xc5a interrupt cont rol register 0-26 icr026 8 ipsbar + 0xc5b interrupt cont rol register 0-27 icr027 8 ipsbar + 0xc5c interrupt cont rol register 0-28 icr028 8 ipsbar + 0xc5d interrupt cont rol register 0-29 icr029 8 ipsbar + 0xc5e interrupt cont rol register 0-30 icr030 8 ipsbar + 0xc5f interrupt control register 0-31 icr031 8 ipsbar + 0xc60 interrupt control register 0-32 icr032 8 ipsbar + 0xc61 interrupt control register 0-33 icr033 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 freescale semiconductor a-9 preliminary ispbar + 0xc62 interrupt control register 0-34 icr034 8 ipsbar + 0xc63 interrupt control register 0-35 icr035 8 ipsbar + 0xc64 interrupt control register 0-36 icr036 8 ipsbar + 0xc65 interrupt control register 0-37 icr037 8 ipsbar + 0xc66 interrupt control register 0-38 icr038 8 ipsbar + 0xc67 interrupt control register 0-39 icr039 8 ipsbar + 0xc68 interrupt control register 0-40 icr040 8 ipsbar + 0xc69 interrupt control register 0-41 icr041 8 ipsbar + 0xc6a interrupt cont rol register 0-42 icr042 8 ipsbar + 0xc6b interrupt cont rol register 0-43 icr043 8 ipsbar + 0xc6c interrupt cont rol register 0-44 icr044 8 ipsbar + 0xc6d interrupt co ntrol register 0-45 icr45 8 ipsbar + 0xc6e interrupt cont rol register 0-46 icr046 8 ipsbar + 0xc6f interrupt control register 0-47 icr047 8 ipsbar + 0xc70 interrupt control register 0-48 icr048 8 ipsbar + 0xc71 interrupt control register 0-49 icr049 8 ipsbar + 0xc72 interrupt control register 0-50 icr050 8 ipsbar + 0xc73 interrupt control register 0-51 icr051 8 ipsbar + 0xc74 interrupt control register 0-52 icr052 8 ipsbar + 0xc75 interrupt control register 0-53 icr053 8 ipsbar + 0xc76 interrupt control register 0-54 icr054 8 ipsbar + 0xc77 interrupt control register 0-55 icr055 8 ipsbar + 0xc78 interrupt control register 0-56 icr056 8 ipsbar + 0xc79 interrupt control register 0-57 icr057 8 ipsbar + 0xc7a interrupt cont rol register 0-58 icr058 8 ipsbar + 0xc7b interrupt cont rol register 0-59 icr059 8 ipsbar + 0xc7c interrupt cont rol register 0-60 icr060 8 ipsbar + 0xc7d interrupt cont rol register 0-61 icr061 8 ipsbar + 0xc7e interrupt cont rol register 0-62 icr062 8 ipsbar + 0xce0 software interrupt acknowledge register 0 swackr0 8 ipsbar + 0xce4 level 1 interrupt acknowledge register 0 l1iackr0 8 ipsbar + 0xce8 level 2 interrupt acknowledge register 0 l2iackr0 8 ipsbar + 0xcec level 3 interrupt acknowledge register 0 l3iackr0 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 a-10 freescale semiconductor preliminary ipsbar + 0xcf0 level 4 interrupt acknowledge register 0 l4iackr0 8 ipsbar + 0xcf4 level 5 interrupt acknowledge register 0 l5iackr0 8 ipsbar + 0xcf8 level 6 interrupt acknowledge register 0 l6iackr0 8 ipsbar + 0xcfc level 7 interrupt acknowledge register 0 l7iackr0 8 global interrupt acknowledge cycle registers ipsbar + 0xfe4 global level 1 interrupt acknowledge register gl1iackr 8 ipsbar + 0xfe8 global level 2 interrupt acknowledge register gl2iackr 8 ipsbar + 0xfec global level 3 interr upt acknowledge re gister gl3iackr 8 ipsbar + 0xff0 global level 4 interr upt acknowledge re gister gl4iackr 8 ipsbar + 0xff4 global level 5 interr upt acknowledge re gister gl5iackr 8 ipsbar + 0xff8 global level 6 interr upt acknowledge re gister gl6iackr 8 ipsbar + 0xffc global level 7 interr upt acknowledge re gister gl7iackr 8 gpio registers ipsbar + 0x10_0000 reserved ? 8 ipsbar + 0x10_0001 reserved ? 8 ipsbar + 0x10_0002 reserved ? 8 ipsbar + 0x10_0003 reserved ? 8 ipsbar + 0x10_0004 reserved ? 8 ipsbar + 0x10_0005 reserved ? 8 ipsbar + 0x10_0006 reserved ? 8 ipsbar + 0x10_0007 reserved ? 8 ipsbar + 0x10_0008 port nq out data register portnq 8 ipsbar + 0x10_0009 port dd output data register portdd 8 ipsbar + 0x10_000a port an output data register portan 8 ipsbar + 0x10_000b port as output data register portas 8 ipsbar + 0x10_000c reserved ? 8 ipsbar + 0x10_000d port qs out put data register portqs 8 ipsbar + 0x10_000e port ta output data register portta 8 ipsbar + 0x10_000f port tc output data register porttc 8 ipsbar + 0x10_0010 port td output data register porttd 8 ipsbar + 0x10_0011 port ua output data register portua 8 ipsbar + 0x10_0012 port ub output data register portub 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 freescale semiconductor a-11 preliminary ipsbar + 0x10_0013 port uc output data register portuc 8 ipsbar + 0x10_0014 reserved ? 8 ipsbar + 0x10_0015 reserved ? 8 ipsbar + 0x10_0016 reserved ? 8 ipsbar + 0x10_0017 reserved ? 8 ipsbar + 0x10_0018 reserved ? 8 ipsbar + 0x10_0019 reserved ? 8 ipsbar + 0x10_001a reserved ? 8 ipsbar + 0x10_001b reserved ? 8 ipsbar + 0x10_001c port nq data direction register ddrnq 8 ipsbar + 0x10_001d port dd data direction register ddrdd 8 ipsbar + 0x10_001e port an data direction register ddran 8 ipsbar + 0x10_001f port as data direction register ddras 8 ipsbar + 0x10_0020 reserved ? 8 ipsbar + 0x10_0021 port qs data direction register ddrqs 8 ipsbar + 0x10_0022 port ta data direction register ddrta 8 ipsbar + 0x10_0023 port tc data direction register ddrtc 8 ipsbar + 0x10_0024 port td data direction register ddrtd 8 ipsbar + 0x10_0025 port ua data direction register ddrua 8 ipsbar + 0x10_0026 port ub data direction register ddrub 8 ipsbar + 0x10_0027 port uc data direction register ddruc 8 ipsbar + 0x10_0028 reserved ? 8 ipsbar + 0x10_0029 reserved ? 8 ipsbar + 0x10_002a reserved ? 8 ipsbar + 0x10_002b reserved ? 8 ipsbar + 0x10_002c reserved ? 8 ipsbar + 0x10_002d reserved ? 8 ipsbar + 0x10_002e reserved ? 8 ipsbar + 0x10_002f reserved ? 8 ipsbar + 0x10_0030 port nq pin data/set data register portnq/ setnq 8 ipsbar + 0x10_0031 port dd pin data/set data register portddp/ setdd 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 a-12 freescale semiconductor preliminary ipsbar + 0x10_0032 port an pin data/set data register portddp/ setan 8 ipsbar + 0x10_0033 port as pin data/set data register portelp/ setas 8 ipsbar + 0x10_0034 reserved ? 8 ipsbar + 0x10_0035 port qs pin data/set data register portqsp/ setqs 8 ipsbar + 0x10_0036 port ta pin data/set data register portsdp/ setta 8 ipsbar + 0x10_0037 port tc pin data/set data register porttcp/ settc 8 ipsbar + 0x10_0038 port td pin data/set data register porttdp/ settd 8 ipsbar + 0x10_0039 port ua pin data/set data register portuap/ setua 8 ipsbar + 0x10_003a port ub pin data/set data register portuap/ setub 8 ipsbar + 0x10_003b port uc pin data/set data register portuap/ setuc 8 ipsbar + 0x10_003c reserved ? 8 ipsbar + 0x10_003d reserved ? 8 ipsbar + 0x10_003e reserved ? 8 ipsbar + 0x10_003f reserved ? 8 ipsbar + 0x10_0040 reserved ? 8 ipsbar + 0x10_0041 reserved ? 8 ipsbar + 0x10_0042 reserved ? 8 ipsbar + 0x10_0043 reserved ? 8 ipsbar + 0x10_0044 port nq clear output data register clrnq 8 ipsbar + 0x10_0045 port dd clear output data register clrdd 8 ipsbar + 0x10_0046 port an clear output data register clran 8 ipsbar + 0x10_0047 port as clear output data register clras 8 ipsbar + 0x10_0048 reserved ? 8 ipsbar + 0x10_0049 port qs clear output data register clrqs 8 ipsbar + 0x10_004a port ta clear output data register clrta 8 ipsbar + 0x10_004b port tc clear output data register clrtc 8 ipsbar + 0x10_004c port td clear output data register clrtd 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 freescale semiconductor a-13 preliminary ipsbar + 0x10_004d port ua clear output data register clrua 8 ipsbar + 0x10_004e port ub clear output data register clrub 8 ipsbar + 0x10_004f port uc clear output data register clruc 8 ipsbar + 0x10_0050 port nq pin assignment register pnqpar 8 ipsbar + 0x10_0051 port dd pin assignment register pddpar 8 ipsbar + 0x10_0052 port an pin assignment register panpar 8 ipsbar + 0x10_0054 port qs pin assignment register pqspar 16 ipsbar + 0x10_0056 port ta pin assignment register ptapar 8 ipsbar + 0x10_0057 port tc pin assignment register ptcpar 8 ipsbar + 0x10_0058 port td pin assignment register ptdpar 8 ipsbar + 0x10_0059 port ua pin assignment register puapar 8 ipsbar + 0x10_005a port ub pin assignment register pubpar 8 ipsbar + 0x10_005b port uc pin assignment register pucpar 8 ipsbar + 0x10_0078 pin slew rate register pssr 32 ipsbar + 0x10_007c pin drive strengthregister pdsr 32 reset control, chip configuration, and power management registers ipsbar + 0x11_0000 reset control register rcr 8 ipsbar + 0x11_0001 reset status register rsr 8 ipsbar + 0x11_0004 chip configuration register ccr 16 ipsbar + 0x11_0007 low-power control register lpcr 8 ipsbar + 0x11_0008 reset configuration register rcon 16 ipsbar + 0x11_000a chip identification register cir 16 clock module registers ipsbar + 0x12_0000 synthesizer control register syncr 16 ipsbar + 0x12_0002 synthesizer status register synsr 16 edge port registers ipsbar + 0x13_0000 eport pin assignment register eppar 16 ipsbar + 0x13_0002 eport data direction register epddr 8 ipsbar + 0x13_0003 eport interrupt enable register epier 8 0x0013_0004 eport data register epdr 8 ipsbar + 0x13_0005 eport pin data register eppdr 8 0x0013_0006 eport flag register epfr 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 a-14 freescale semiconductor preliminary programmable interrupt timer 0 registers ipsbar + 0x15_0000 pit control and status register 0 pcsr 0 16 ipsbar + 0x15_0002 pit modulus register 0 pmr 0 16 ipsbar + 0x15_0004 pit count register 0 pcntr 0 16 programmable interrupt timer 1 registers ipsbar + 0x16_0000 pit control and status register 1 pcsr 1 16 ipsbar + 0x16_0002 pit modulus register 1 pmr 1 16 ipsbar + 0x16_0004 pit count register 1 pcntr 1 16 adc registers ipsbar + 0x19_0000 adc module configuration register adcmcr 16 ipsbar + 0x19_0006 port qa data register portqa 8 ipsbar + 0x19_0007 port qb data register portqb 8 ipsbar + 0x19_0008 port qa data direction register ddrqa 8 ipsbar + 0x19_0009 port qb data direction register ddrqb 8 ipsbar + 0x19_000a adc control register 0 acr0 16 ipsbar + 0x19_000c adc control register 1 acr1 16 ipsbar + 0x19_000e adc control register 2 acr2 16 ipsbar + 0x19_0010 adc status register 0 asr0 16 ipsbar + 0x19_0012 adc status register 1 asr1 16 ipsbar + 0x19_0200? 0x19_027e conversion command word table ccw0? ccw63 64x16 ipsbar + 0x19_0280? 0x19_02fe right justified, unsigned result register rjurr0? rjurr63 64x16 ipsbar + 0x19_0300? 0x19_037e left justified, signed result register ljsrr0? ljsrr63 64x16 ipsbar + 0x19_0380? 0x19_03fe left justified, unsigned result register ljurr0? ljurr63 64x16 general purpose timer a registers ipsbar + 0x1a_0000 gpta ic/oc select register gptaios 8 ipsabar + 0x1a_0001 gpta compar e force register gptacforc 8 ipsbar + 0x1a_0002 gpta output compare 3 mask register gptaoc3m 8 ipsbar + 0x1a_0003 gpta output compare 3 data register gptaoc3d 8 ipsbar + 0x1a_0004 gpta counter register gptacnt 16 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 freescale semiconductor a-15 preliminary ipsbar + 0x1a_0006 gpta system control register 1 gptascr1 8 ipsbar + 0x1a_0008 gpta toggle-on-overflow register gptatov 8 ipsbar + 0x1a_0009 gpta control register 1 gptactl1 8 ipsbar + 0x1a_000b gpta control register 2 gptactl2 8 ipsbar + 0x1a_000c gpta interr upt enable register gptaie 8 ipsbar + 0x1a_000d gpta system control register 2 gptascr2 8 ipsbar + 0x1a_000e gpta fl ag register 1 gptaflg1 8 ipsbar + 0x1a_000f gpta fl ag register 2 gptaflg2 8 ipsbar + 0x1a_0010 gpta channel 0 register gptac0 16 ipsbar + 0x1a_0012 gpta channel 1 register gptac1 16 ipsbar + 0x1a_0014 gpta channel 2 register gptac2 16 ipsbar + 0x1a_0016 gpta channel 3 register gptac3 16 ipsbar + 0x1a_0018 pulse accumulator control register gptapactl 8 ipsbar + 0x1a_0019 pulse accumulator flag register gptpaflg 8 ipsbar + 0x1a_001a pulse accumulator counter register gptapacnt 8 ipsbar + 0x1a_001d gpta port data register gptaport 8 ipsbar + 0x1a_001e gpta port da ta direction register gptaddr 8 pulse width modulator ipsbar + 0x1b_0000 pwm enable register pwme 8 ipsbar + 0x1b_0001 pwm polarity register pwmpol 8 ipsbar + 0x1b_0002 pwm clock select register pwmclk 8 ipsbar + 0x1b_0003 pwm prescale clock select register pwmprclk 8 ipsbar + 0x1b_0004 pwm center align enable register pwmcae 8 ipsbar + 0x1b_0005 pwm control register pwmctl 8 ipsbar + 0x1b_0008 pwm scale a register pwmscla 8 ipsbar + 0x1b_0009 pwm scale b register pwmsclb 8 ipsbar + 0x1b_000c pwm channel counter register 0 pwmcnt0 8 ipsbar + 0x1b_000d pwm channel counter register 1 pwmcnt1 8 ipsbar + 0x1b_000e pwm channel counter register 2 pwmcnt2 8 ipsbar + 0x1b_000f pwm channel counter register 3 pwmcnt3 8 ipsbar + 0x1b_0010 pwm channel counter register 4 pwmcnt4 8 ipsbar + 0x1b_0011 pwm channel counter register 5 pwmcnt5 8 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 a-16 freescale semiconductor preliminary ipsbar + 0x1b_0012 pwm channel counter register 6 pwmcnt6 8 ipsbar + 0x1b_0013 pwm channel counter register 7 pwmcnt7 8 ipsbar + 0x1b_0014 pwm channel period register 0 pwmper0 8 ipsbar + 0x1b_0015 pwm channel period register 1 pwmper1 8 ipsbar + 0x1b_0016 pwm channel period register 2 pwmper2 8 ipsbar + 0x1b_0017 pwm channel period register 3 pwmper3 8 ipsbar + 0x1b_0018 pwm channel period register 4 pwmper4 8 ipsbar + 0x1b_0019 pwm channel period register 5 pwmper5 8 ipsbar + 0x1b_001a pwm channel period register 6 pwmper6 8 ipsbar + 0x1b_001b pwm channel period register 7 pwmper7 8 flexcan registers ipsbar + 0x1c_0000 module configuration register canmcr 16 ipsbar + 0x1c_0004 flexcan control register canctrl 32 ipsbar + 0x1c_0008 free running timer timer 32 ipsbar + 0x1c_000c reserved --- 32 ipsbar + 0x1c_0010 rx global mask rxgmask 32 ipsbar + 0x1c_0014 rx buffer 14 mask rx14mask 32 ipsbar + 0x1c_0018 rx buffer 15 mask rx15mask 32 ipsbar + 0x1c_001c error counter register errcnt 32 ipsbar + 0x1c_0020 error and status errstat 32 ipsbar + 0x1c_0024 reserved --- 32 ipsbar + 0x1c_0028 interrupt mask register imask 32 ipsbar + 0x1c_002c reserved --- 32 ipsbar + 0x1c_0030 interrupt flag register iflag 32 ipsbar + 0x1c_0080 message buffer 0 - message buffer 15 mbuff0? mbuff15 16x16bytes flash registers ipsbar + 0x1d_0000 cfm configuration register cfmmcr 16 ipsbar + 0x1d_0002 cfm clock divider register cfmclkd 8 ipsbar + 0x1d_0008 cfm security register cfmsec 32 ipsbar + 0x1d_0010 cfm protection register cfmprot 32 ipsbar + 0x1d_0014 cfm supervisor access register cfmsacc 32 ipsbar + 0x1d_0018 cfm data access register cfmdacc 32 table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 freescale semiconductor a-17 preliminary ipsbar + 0x1d_0020 cfm user status register cfmustat 8 ipsbar + 0x1d_0024 cfm command register cfmcmd 8 1 umr1 n , umr2 n , and ucsr n should be changed only after the receiver/transmitter is issued a software reset command. that is, if channel operation is not disabled, undesirable results may occur. table a-3. register memory map (continued) address name mnemonic size
register memory map mcf5213 reference manual, rev. 1.1 a-18 freescale semiconductor preliminary