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freescale semiconductor data sheet: advance information document number: imx53cec rev. 2, 5/2011 mcimx53xd package information plastic package case tepbga-2 19 x 19 mm, 0.8 mm pitch case fc-pbga pop 12 x 12 mm ordering information see table 1 on page 3 ? 2011 freescale semiconductor, inc. all rights reserved. this document contains information on a new pr oduct. specifications and information herein are subject to change without notice. 1 introduction the i.mx53xd multimedia application processor is freescale semiconductor?s latest addition to a growing family of multimedia-foc used products offering high performance processing optim ized for lowest power consumption. the i.mx53xd processor feat ures freescale?s advanced implementation of the arm? core, which operates at clock speeds as high as 1 ghz and interfaces with ddr2/lvddr2-800, lpddr2- 800, or ddr3-800 dram memories. this device is suitable for applications such as the following: ? tablets, high-end mobile internet devices (mid) ? smart mobile devices ? thin clients ? internet monitors, media phones, high-end portable media players (pmp) with hd video capability ? gaming consoles the flexibility of the i.mx53xd architecture allows for its use in a wide variety of applications. as the heart of i.mx53xd applications processors for consumer products 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. ordering information . . . . . . . . . . . . . . . . . . . . . . . 3 1.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1. special signal considerations . . . . . . . . . . . . . . . 17 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1. chip-level conditions . . . . . . . . . . . . . . . . . . . . . 17 4.2. power supplies requirements and restrictions . 25 4.3. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4. output buffer impedance characteristics . . . . . . 35 4.5. i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . 39 4.6. system modules timing . . . . . . . . . . . . . . . . . . . . 46 4.7. external peripheral interfaces parameters . . . . . . 68 4.8. xtal electrical specifications . . . . . . . . . . . . . . 146 5. boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . 147 5.1. boot mode configuration pins . . . . . . . . . . . . . . 147 5.2. boot devices interfaces allocation . . . . . . . . . . . 148 5.3. power setup during boot . . . . . . . . . . . . . . . . . . 149 6. package information and contact assignments . . . . . 150 6.1. 19x19 mm package information . . . . . . . . . . . . . 150 6.2. 19 x 19 mm, 0.8 pitch ball map . . . . . . . . . . . . . 169 6.3. pop 12 x 12 mm package on package (pop) information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
i.mx53xd applications processors for consumer products, rev. 2 2 freescale semiconductor introduction the application chipset, the i.mx53xd processor pr ovides all the interfaces fo r connecting peripherals, such as wlan, bluetooth?, gps, hard dr ive, camera sensors, and dual displays. features of the i.mx53xd proc essor include the following: ? applications processor?the i. mx53xd processors boost the capab ilities of high -tier portable applications by satisfying th e ever increasing mips needs of operating systems and games. freescale?s dynamic voltage and frequency scal ing (dvfs) provides significant power reduction, allowing the device to run at lower voltage a nd frequency with sufficient mips for tasks such as audio decode. ? multilevel memory system?the multilevel memo ry system of the i.mx 53xd is based on the l1 instruction and data caches, l2 cache, intern al and external memory. the i.mx53xd supports many types of external memo ry devices, including ddr2, lo w voltage ddr2, lpddr2, ddr3, nor flash, psram, cellular ra m, nand flash (mlc and slc ), onenand?, and managed nand including emmc up to rev 4.4. ? smart speed technology?the i.mx53xd device has power management throughout the ic that enables the rich suite of multimedia features a nd peripherals to consume minimum power in both active and various low power m odes. smart speed technology enab les the designer to deliver a feature-rich product requiring levels of po wer far lower than i ndustry expectations. ? multimedia powerhouse?the multimedia perform ance of the i.mx53xd processor arm core is boosted by a multilevel cache system, neon (inc luding advanced simd, 32-bit single-precision floating point support) and vector floating point coprocessors. th e system is further enhanced by a multistandard hardware video codec, autonom ous image processing uni t (ipu), sd and hd720p triple video (tv) encoder w ith triple video dac, and a pr ogrammable smart dma (sdma) controller. ? powerful graphics acceler ation?graphics is the key to m obile game, navigation, web browsing, and other applications. the i.mx53xd processors provide two independent, integrated graphics processing units: an opengl ? es 2.0 3d graphics accelerato r (33 mtri/s, 200 mpix/s, and 800 mpix/s z-plane performance) and an open vg? 1.1 2d graphics acc elerator (200 mpix/s). ? interface flexibility?the i.mx53xd processor s upports connection to a variety of interfaces, including lcd controller for two displays and cmos sensor in terface, high-speed usb on-the-go with phy, plus three high-speed usb hosts, multiple expansion card ports (high-speed mmc/sdio host and others), 10/100 ethernet controller, and a vari ety of other popular interfaces (pata, uart, i 2 c, and i 2 s serial audio, among others). ? advanced security?the i.mx53xd processors deliver hardware-e nabled security features that enable secure e-commerce, digi tal rights management (drm), information encryption, secure boot, and secure software downloads. for deta iled information about the i.mx53xd security features contact a fr eescale representative. the i.mx53xd application processor is a follow-on to the i.mx51, with improved performance, power efficiency, and multimedia capabilities.
introduction i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 3 1.1 ordering information table 1 provides ordering information. 1.2 features the i.mx53xd multimedia applications processor (a p) is based on the arm platform, which has the following features: ? mmu, l1 instruction and l1 data cache ? unified l2 cache ? target frequency of the core (including neon, vfpv3 and l1 cache): 1 ghz ? neon coprocessor (simd media processing archit ecture) and vector floating point (vfp-lite) coprocessor supporting vfpv3 ? trustzone the memory system consists of the following components: ? level 1 cache: ? instruction (32 kbyte) ? data (32 kbyte) ? level 2 cache: ? unified instruction and data (256 kbyte) ? level 2 (internal) memory: ? boot rom, including hab (64 kbyte) ? internal multimedia/shared, fast access ram (128 kbyte) ? secure/non-secure ram (16 kbyte) table 1. ordering information part number 1 1 part numbers with a pc prefix indicate non production engineering parts. mask set features case tempera ture range ( c) package 2 2 case tepbga-2 is rohs co mpliant, lead-free ms l (moisture sensitivity level) 3. PCIMX535DVV1C n78c 1 ghz, full feature set -20 to +85 19 x 19 mm, 0.8 mm pitch bga case tepbga-2 mcimx535dvv1c n78c 1 ghz, full feature set -20 to +85 19 x 19 mm, 0.8 mm pitch bga case tepbga-2 pcimx538dzk1c n78c 1 ghz, full feature set -20 to +85 12 x 12 mm pop mcimx538dzk1c n78c 1 ghz, full feature set -20 to +85 12 x 12 mm pop
i.mx53xd applications processors for consumer products, rev. 2 4 freescale semiconductor introduction ? external memory interfaces: ? 16/32-bit ddr2-800, lv-ddr2-800 or ddr3-800 up to 2 gbyte ? 32-bit lpddr2 ? 8/16-bit nand slc/mlc flash, up to 66 mhz, 4/8/14/16-bit ecc ? 8/16-bit nor flash, psram, and cellular ram. ? 32-bit multiplexed mode nor flash, psram & cellular ram. ? 8-bit asynchronous (dtack mode) eim interface. ? all eim pins are muxed on othe r interfaces (data with nfc pins ). i/o muxing logic selects eim port, as primary m uxing at system boot. ? samsung onenand? and managed nand in cluding emmc up to rev 4.4 (in muxed i/o mode) the i.mx53xd system is built around the following system on chip interfaces: ? 64-bit amba axi v1.0 bus?used by arm platform, multimedia ac celerators (such as vpu, ipu, gpu3d, gpu2d) and the external memory controller (extmc) operating at 200 mhz. ? 32-bit amba ahb 2.0 bus?used by the rest of the bus master peripherals operating at 133 mhz. ? 32-bit ip bus?peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 mhz. the i.mx53xd makes use of dedicated hardware accel erators to achieve state-of-the-art multimedia performance. the use of hardwa re accelerators provides both high performance and low power consumption while freeing up th e cpu core for other tasks. the i.mx53xd incorporates the fo llowing hardware accelerators: ? vpu, version 3?video processing unit ? gpu3d?3d graphics processing unit, opengl es 2.0, version 3, 33 mtri/s, 200 mpix/s, and 800 mpix/s z-plane performance, 256 kbyte ram memory ? gpu2d?2d graphics accelerator, openvg 1.1, version 1, 200 mpix/s performance, ? ipu, version 3m?image processing unit ? asrc?asynchronous sample rate converter the i.mx53xd includes the following interfaces to external devices: note not all interfaces are available simultaneously, depending on i/o multiplexer configuration. ? hard disk drives: ? pata, up to u-dma mode 5, 100 mbyte/s ? sata i, 1.5 gbps ?displays: ? five interfaces available. total rate of all in terfaces is up to 180 mpix els/s, 24 bpp. up to two interfaces may be active at once.
introduction i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 5 ? two parallel 24-bit display ports. the prim ary port is up to 165 mpix/s (for example, uxga at 60 hz). ? lvds serial ports: one dual channel port up to 165 mpix/s or two independent single channel ports up to 85 mp/s (for example, wxga at 60 hz) each. ? tv-out/vga port up to 150 mpix/s (for example, 1080p60). ? camera sensors: ? two parallel 20-bit camera por ts. primary up to 180-mhz peak clock frequency, secondary up to 120-mhz peak clock frequency. ? expansion cards: ? four sd/mmc card ports: thre e supporting 416 mbps (8-bit i/ f) and one enhanced port supporting 832 mbps (8-bit, emmc 4.4). ?usb ? high-speed (hs) usb 2.0 otg (up to 480 mbps), with integrated hs usb phy ? three usb 2.0 (480 mbps) hosts: ? high-speed host with integr ated on-chip high-speed phy ? two high-speed hosts for external hs/fs tran sceivers through ulpi/serial, support ic-usb ? miscellaneous interfaces: ? one-wire (owire) port ? three i2s/ssi/ac97 ports, suppo rting up to 1.4 mbps, each connected to audio multiplexer (audmux) providing four external ports. ? five uart rs232 ports, up to 4.0 mbps each. one supports 8-wire, the other four support 4-wire. ? two high speed enhanced cspi (e cspi) ports plus one cspi port ? three i 2 c ports, supporting 400 kbps ? fast ethernet controller, i eee1588 v1 compliant, 10/100 mbps ? two controller area network (flexcan) interfaces, 1 mbps each ? sony phillips digital interface (spdif), rx and tx ? enhanced serial audio interface ( esai), up to 1.4 mbps each channel ? key pad port (kpp) ? two pulse-width modulators (pwm) ? gpio with interrupt capabilities the system supports efficient and smart power control and clocking: ? supporting dvfs (dynamic voltage and frequency scaling) tec hnique for low power modes ? power gating srpg (state retention power gating) for arm core and neon ? support for various levels of system power modes ? flexible clock gating control scheme ? on-chip temperature monitor ? on-chip oscillator amplifier supporting 32.768 khz external crystal
i.mx53xd applications processors for consumer products, rev. 2 6 freescale semiconductor introduction ? on-chip ldo voltage regulators for plls security functions are enabled and acce lerated by the following hardware: ? arm trustzone including the tz architecture (sep aration of interrupts, memory mapping, and so on) ? secure jtag controller (sjc)?pr otecting jtag from debug port at tacks by regulating or blocking the access to the system debug features ? secure real-time cloc k (srtc)?tamper resistant rtc wi th dedicated power domain and mechanism to detect voltage and clock glitches ? real-time integrity checker, version 3 (rtic v3)?rtic type1, enhanced with sha-256 engine ? saharav4 lite?cryptographic accelerator that includes true random number generator (trng) ? security controller, version 2 (sccv2)?impr oved scc with aes engine, secure/non-secure ram and support for multiple ke ys as well as tz/non-tz separation ? central security unit (csu)?enhancement for the iim (ic identification module). csu is configured during boot by e-fuses, and determines the security level operation mode as well as the trustzone (tz) policy ? advanced high assurance boot (a-hab)?hab with the following embedded enhancements: sha-256, 2048-bit rsa key, version control mechan ism, warm boot, csu, and tz initialization note the actual feature set depends on the part number as described in table 1 . functions such as video hardware acc eleration with 2d and 3d hardware graphics acceleration may not be enabled for specific part numbers.
architectural overview i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 7 2 architectural overview the following subsections provide an architectural overview of the i.mx53xd processor system. 2.1 block diagram figure 1 shows the functional modules in the i.mx53xd processor system. figure 1. i.mx53xd system block diagram note the numbers in brackets indicate numbe r of module instances. for example, pwm (2) indicates two separate pwm peripherals. application processor smart dma (sdma) shared peripherals ap peripherals arm cortex a8 arm cortex a8 platform timers cspi uart (4) gpt pwm (2) epit (2) gpiox32 (7) wdog (2) owire i 2 c(3) iomuxc iim audmux kpp boot rom ssi (2) rticv3 sccv2 srtc csu fuse box debug dap tpiu firi saharav4 lite security tzic image processing usb otg + 3 hs ports cti (2) ecspi internal usb phy2 usb phy1 external memory i/f ram 144 kb subsystem (ipu) tv-encoder ldb lcd display-1,2 domain (ap) composite cvbs/ s-video component rgb, ycc (hd tv-out / vga) sjc neon, vfpv3 l2 cache 256 kb etm, cti0,1 l1 i/d cache irda xvr wlan usb otg (dev/host) jtag (ieee1149.1) bluetooth keypad access. conn. mmc/sd emmc/esd gps rf/if rf / if ic?s audio, power mngmnt. spba flexcan (2) digital audio can i/f esdhcv2 (3) uart spdif rx/tx asrc video proc. unit (vpu) 3d graphics proc. unit (gpu3d) g-memory 256 kb 2d graphics proc. unit ( gpu2d ) axi and ahb switch fabric lv ds (wsxga+) battery ctrl device nor/nand flash ethernet 10/100 mbps fec (ieee1588) camera (2) 64 kb clock and reset pll (4) ccm gpc src xtalosc(2) camp (2) temperature sensor esdhcv3 camera (2) (extmc) lcd display (2) ssi ecspi esai p-ata sata + temp mon sata / p-ata hdd ddr2/ddr3/ lpddr2
i.mx53xd applications processors for consumer products, rev. 2 8 freescale semiconductor modules list 3 modules list the i.mx53xd processor contains a va riety of digital and analog modules. table 2 describes these modules in alphabetical order. table 2. i.mx53xd digital and analog blocks block mnemonic block name subsystem brief description arm arm platform arm the arm cortex a8 tm platform consists of the arm processor version r2p5 (with trustzone) and its essentia l sub-blocks. it contains the 32 kbyte l1 instruction cache, 32 kbyte l1 data cache, level 2 cache controller and a 256 kbyte l2 cache. the platform also contains an event monitor and debug modules. it also has a neon coprocessor with simd media processing architecture, a register file with 32/64-bit general-purpose registers, an integer execute pi peline (alu, shift, mac), dual single-precision floating point execute pipelines (fadd, fmul), a load/store and permute pipeline and a non-pipelined vector floating point (vfp lite) coprocessor supporting vfpv3. asrc asynchronous sample rate converter multimedia peripherals the asynchronous sample rate converter (asrc) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. the asrc supports concurrent sample rate conversion of up to 10 channels of about ?120 db thd+n. the sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. the asrc supports up to three sampling rate pairs. audmux digital audio multiplexer multimedia peripherals the audmux is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, ssi1, ssi2, and ssi3) and peripheral serial interfaces (audio and voice codecs). the audmux has seven ports (three internal and four external) with identical functionality and programmi ng models. a desired connectivity is achieved by configuring two or more audmux ports. camp-1 camp-2 clock amplifier clocks, resets, and power control clock amplifier ccm gpc src clock control module global power controller system reset controller clocks, resets, and power control these modules are responsible for clock and reset distribution in the system, as well as for system power management. the system includes four plls. cspi ecspi-1 ecspi-2 configurable spi, enhanced cspi connectivity peripherals full-duplex enhanced synchronous serial interface, with data rates 16-60 mbit/s. it is configurable to support master/slave modes. in master mode it supports four slave selects for multiple peripherals. csu central security unit security the central security unit (csu) is responsible for setting comprehensive security policy within the i.mx53xd platform, and for sharing security information between the various securi ty modules. the security control registers (scr) of the csu are set duri ng boot time by the high assurance boot (hab) code and are locked to prevent further writing.
modules list i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 9 debug debug system system control the debug system provides real-time trace debug capability of both instructions and data. it supports a trace protocol that is an integral part of the arm real time debug solution (realview). real-time tracing is controlled by specif ying a set of triggering and filtering resources, which include address and data comparators, three cross-system triggers (cti), counters, and sequencers. debug access port (dap) ?the dap provides real-time access for the debugger without halting the core to system memory, peripheral register, debug configuration registers and jtag scan chains. extmc external memory controller connectivity peripherals the extmc is an external and internal memory interface. it performs arbitration between multi-axi masters to multi-memory controllers, divided into four major channels, fast memories (ddr2/ddr3/lpddr2) channel, slow memories (nor-flash / psr am / nand-flash etc.) channel, internal memory (ram, rom) channel and graphical memory (gmem) channel. in order to increase the bandwidth performance, the extmc separates the buffering and the arbitration between different channels so parallel accesses can occur. by separating the channels, slow accesses do not interfere with fast accesses. extmc features: ? 64-bit and 32-bit axi ports ? enhanced arbitration scheme for fast channel, including dynamic master priority, and taking into account which pages are open or closed and what type (read or writ e) was the last access ? flexible bank interleaving ? support 16/32-bit ddr2-800 or ddr3-800 or lpddr2. ? support up to 2 gbyte ddr memories. ? support nfc, eim signal muxing scheme. ? support 8/16/32-bit nor-flash/psram memories (sync and async operating modes), at slow frequency. (8-bit is not supported on d[23]-d[16]). ? support 4/8/14/16-bit ecc, page sizes of 512-b, 2-kb and 4-kb nand-flash (including mlc) ? multiple chip selects (up to 4). ? enhanced ddr memory controller, supporting access latency hiding ? support watermark for security (internal and external memories) epit-1 epit-2 enhanced periodic interrupt timer timer peripherals each epit is a 32-bit ?set and forget? timer that starts counting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. it has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly. esai enhanced serial audio interface connectivity peripherals the enhanced seri al audio interface (esai) provi des a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, spdif transceivers, and other processors. the esai consists of independent transmitter and receiver sections, each section with its own clock generator. the esai has 12 pins for data and clocking connection to external devices. table 2. i.mx53xd digital and analog blocks (continued) block mnemonic block name subsystem brief description
i.mx53xd applications processors for consumer products, rev. 2 10 freescale semiconductor modules list esdhcv3-3 ultra-high- speed emmc / sd host controller connectivity peripherals ultra high-speed emmc / sd host controller, enhanced to support emmc 4.4 standard specification, for 832 mbps. ? port 3 is specifically enhanced to support emmc 4.4 specification, for double data rate (832 mbps, 8-bit port). esdhcv3 is backward compatible to esdhcv2 and supports all the features of esdhcv2 as described below. esdhcv2-1 esdhcv2-2 esdhcv2-4 enhanced multi-media card / secure digital host controller enhanced multimedia card / secure digital host controller ? ports 1, 2, and 4 are compatible with the ?mmc system specification? version 4.3, full support and supporting 1, 4 or 8-bit data. the generic features of the esdhcv2 module, when serving as sd / mmc host, include the following: ? can be configured eit her as sd / mmc controller ? supports esd and emmc standard, for sd/mmc embedded type cards ? conforms to sd host controller standard specification, version 2.0, full support. ? compatible with the sd memory card specification, version 1.1 ? compatible with the sdio card specification, version 1.2 ? designed to work with sd memo ry, minisd memory, sdio, minisdio, sd combo, mmc and mmc rs cards ? configurable to work in one of the following modes: - sd/sdio 1-bit, 4-bit - mmc 1-bit, 4-bit, 8-bit ? full/high speed mode. ? host clock frequency variable between 32 khz to 52 mhz ? up to 200 mbps data transfer for sd/sdio cards using 4 parallel data lines ? up to 416 mbps data transfer for mmc cards using 8 parallel data lines fec fast ethernet controller connectivity peripherals the ethernet media access controller (mac) is designed to support both 10 mbps and 100 mbps ethernet/ieee st d 802.3? networks . an external transceiver interface and transceiver function are required to complete the interface to the media. the i.mx53xd also consists of hw assist for ieee1588? standard. see, tsu and ce_rtc (ieee1588) section for more details. firi fast infrared interface connectivity peripherals fast infrared interface flexcan-1 flexcan-2 flexible controller area network connectivity peripherals the controller area network (can) protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus. meets the following specific requirements of this application: real -time processing, reliable operation in the extmc environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan is a full implementation of the can protocol specification, version 2.0 b (iso 11898), which supports both standar d and extended message frames at 1 mbps. table 2. i.mx53xd digital and analog blocks (continued) block mnemonic block name subsystem brief description
modules list i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 11 gpio-1 gpio-2 gpio-3 gpio-4 gpio-5 gpio-6 gpio-7 general purpose i/o modules system control peripherals these modules are used for general pur pose input/output to external ics. each gpio module supports up to 32 bits of i/o. gpt general purpose timer timer peripherals each gpt is a 32-bit ?free-running? or ?set and forget? mode timer with a programmable prescaler and compare and capture register. a timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. when the timer is configured to ope rate in ?set and forget? mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. the counter has output compare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. gpu3d graphics processing unit multimedia peripherals the gpu, version 3, provides hardware acceleration for 2d and 3d graphics algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to hd1080 resolution. it supports color representation up to 32 bits per pixel. gpu enables high-performance mobile 3d and 2d vector graphics at rates up to 33 mtriangles/s, 200 mpix/s, 800 mpix/s (z). gpu2d graphics processing unit-2d multimedia peripherals the gpu2d version 1, provides hardware acceleration for 2d graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to hd1080 resolution. i2c-1 i2c-2 i2c-3 i 2 c controller connectivity peripherals i 2 c provides serial interface for controlling peripheral devices. data rates of up to 400 kbps are supported. iim ic identification module security the ic identification module (ii m) provides an interface for reading, programming, and/or overriding identific ation and control information stored in on-chip fuse elements. the module supports electrically programmable poly fuses (e-fuses). the iim also provides a set of volatile software-accessible signals that can be used for software control of hardware elements not requiring non-volat ility. the iim provides the primary user-visible mechanism for interfacing with on-chip fuse elements. among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, jtag secure mode , boot characteristics, and various control signals requiring permanent non- volatility. the iim also provides up to 28 volatile control signals. the iim consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module. iim interfaces to the electrical fuse array (split to banks). enabled to set up boot modes, security levels, security keys and many other system parameters. i.mx53xda consists of 4 x 256-bit + 1x 128-bit fuse-banks (total 1152 bits) through iim interface. table 2. i.mx53xd digital and analog blocks (continued) block mnemonic block name subsystem brief description
i.mx53xd applications processors for consumer products, rev. 2 12 freescale semiconductor modules list iomuxc iomux control system control peripherals this module enables flexible i/o mult iplexing. each i/o pad has default as well as several alternate functions. the alternate functions are software configurable. ipu image processing unit multimedia peripherals version 3m ipu enables connectivity to displays, relevant processing and synchronization. it supports two display ports and two camera ports, through the following interfaces: ? legacy parallel interfaces ? single/dual channel lvds display interface ? analog tv or vga interfaces the processing includes: ? image enhancement?color adjustment and gamut mapping, gamma correction and contrast enhancement ? video/graphics combining ? support for display backlight reduction ? image conversion?resizing, rotation, inversion and color space conversion ? hardware de-interlacing support ? synchronization and control capabilities, allowing autonomous operation. kpp keypad port connectivity peripherals the kpp supports an 8 8 external keypad matrix. the kpp features are as follows: ? open drain design ? glitch suppression circuit design ? multiple keys detection ? standby key press detection ldb lvds display bridge connectivity peripherals lvds display bridge is used to connect the ipu (image processing unit) to external lvds display interface. ldb supports two channels; each channel has following signals: ? 1 clock pair ? 4 data pairs on-chip differential drivers are provided for each pair. owire one-wire interface connectivity peripherals one-wire support provided for inte rfacing with an on- board eeprom, and smart battery interfaces, for example, dallas ds2502. pata parallel ata connectivity peripherals the pata block is a at attachment host interface. its main use is to interface with hard disk drives and optical disc drives. it interfaces with the ata-6 compliant device over a number of ata signals. it is possible to connect a bus buffer between the host side and the device side. pwm-1 pwm-2 pulse width modulation connectivity peripherals the pulse-width modulator (pwm) has a 16-bit counter and is optimized to generate sound from stored sample audio images. it can also generate tones. the pwm uses 16-bit resolution and a 4 x 16 data fifo to generate sound. intram internal ram internal memory internal ram, shared with vpu. the on-chip memory controller (ocram) module, is an interface between the system?s axi bus, to the internal (on-chip) sram memory module. it is used for controlling the 128 kb multim edia ram, through a 64-bit axi bus. bootrom boot rom internal memory supports secure and regular boot modes. the rom controller supports rom patching. table 2. i.mx53xd digital and analog blocks (continued) block mnemonic block name subsystem brief description
modules list i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 13 rtic run-time integrity checker security protecting read only data from modification is one of the basic elements in trusted platforms. the run-time integrity checker, version 3 (rtic) block is a data-monitoring device responsible for ensuring that the memory content is not corrupted during program execution. the rtic mechanism periodically checks the integrity of code or data sections during normal os run-time execution without interfering with normal operation. the purpose of the rtic is to ensure the integrity of the peripheral memory contents, protect against unauthorized external memory elements replacement and assist with boot authentication. sahara sahara security accelerator security sahara (symmetric/asymmetric hashing and random accelerator), version 4, is a security coprocessor. it implements symmetric encryption algorithms, (aes, des, 3des, rc4 and c2), public key algorithms (rsa and ecc), hashing algorithms (md5, sha-1, sha-224 and sha-256), and a hardware true random number generator. it has a slave ip bus interface for the host to write configuration and command information, and to read status information. it also has a dma controller, with an ahb bus interface, to reduce the burden on the host to mo ve the required data to and from memory. sata serial ata connectivity peripherals sata hdd interface, includes the sata controller and the phy. it is a complete mixed-signal ip solution for sata hdd connectivity. sccv2 security controller, ver. 2 security the security controller is a security assurance hardware module designed to safely hold sensitive data, such as encryption keys, digital right management (drm) keys, passwords and biometrics reference data. the sccv2 monitors the system?s alert signal to determine if the data paths to and from it are secure, that is, it c annot be accessed from outside of the defined security perimeter. if not, it erases all sensitive data on its internal ram. the sccv2 also features a key encryption module (kem) that allows non-volatile (external memory) stora ge of any sensitive data that is temporarily not in use. the kem utilize s a device-specific hidden secret key and a symmetric cryptographic algorithm to transform the sensitive data into encrypted data. sdma smart direct memory access system control peripherals the sdma is multi-channel flexible dma engine. it helps in maximizing system performance by off loading va rious cores in dynamic data routing. the sdma features list is as follows: ? powered by a 16-bit instruction-set micro-risc engine ? multi-channel dma supports up to 32 time-division multiplexed dma channels ? 48 events with total flexibility to trigger any combination of channels ? memory accesses including linear, fifo, and 2d addressing ? shared peripherals between arm and sdma ? very fast context-switching with two-level priority-based preemptive multi-tasking ? dma units with auto-flush and prefetch capability ? flexible address management for dma transfers (increment, decrement, and no address changes on source and destination address) ? dma ports can handle unidirectional and bidirectional flows (copy mode) ? up to 8-word buffer for configurable burst transfers to / from the extmc ? support of byte swapping and crc calculations ? a library of scripts and api is available table 2. i.mx53xd digital and analog blocks (continued) block mnemonic block name subsystem brief description
i.mx53xd applications processors for consumer products, rev. 2 14 freescale semiconductor modules list secram secure / non-secure ram internal memory secure / non-secure inter nal ram, controlled by scc. sjc secure jtag interface system control peripherals jtag manipulation is a known hacker?s method of executing unauthorized program code, getting control over secure applications, and running code in privileged modes. the jtag port provides a debug access to several hardware blocks including the ar m processor and the system bus. the jtag port must be accessible during platform initial laboratory bring-up, manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. howeve r, in order to properly secure the system, unauthorized jtag usage should be strictly forbidden. in order to prevent jtag manipulation while allowing access for manufacturing tests and software debugging, the i.mx53xd processor incorporates a mechanism for regulating jtag access. sjc provides four different jtag security modes that can be selected through an e-fuse configuration. spba shared peripheral bus arbiter system control peripherals spba (shared peripheral bus arbiter) is a two-to-one ip bus interface (ip bus) arbiter. spdif sony philips digital interface multimedia peripherals a standard digital audio transmission protocol developed jointly by the sony and philips corporations. both transmitter and receiver functionalists are supported. srtc secure real time clock security the srtc incorporates a special system state retenti on register (ssrr) that stores system parameters duri ng system shutdown modes. this register and all srtc counters are powered by dedicated supply rail nvcc_srtc_pow. the nvcc_srtc_pow can be energized separately even if all other supply rails are shut down. this register is helpful for storing warm boot parameters. the ssrr also stores the system security state. in case of a securi ty violation, the ssrr mark the event (security violation indication). ssi-1 ssi-2 ssi-3 i2s/ssi/ac97 interface connectivity peripherals the ssi is a full-duplex synchronous interface used on the i.mx53xda processor to provide connectivity with off-chip audio peripherals. the ssi interfaces connect internally to the audmux for mapping to external ports. the ssi supports a wide variety of protoc ols (ssi normal, ssi network, i2s, and ac-97), bit depths (up to 24 bits per word), and clock/frame sync options. each ssi has two pairs of 8 x 24 fifos and hardware support for an external dma controller in order to minimize its impact on system performance. the second pair of fifos provides hardware interleaving of a second audio stream, which reduces cpu overhead in use cases where two time slots are being used simultaneously. table 2. i.mx53xd digital and analog blocks (continued) block mnemonic block name subsystem brief description
modules list i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 15 iptp ieee1588 precision time protocol connectivity peripherals the ieee 1588-2002 (v ersion 1) standard defines a precision time protocol (ptp) - which is a time-transfer prot ocol that enables synchronization of networks (for example, ethernet), to a high degree of accuracy and precision. the ieee1588 hardware assist is composed of the two blocks: time stamp unit and real time clock, which provide the timestamping protocol?s functionality, generating and reading the needed timestamps. the hardware-assisted implementation delivers more precise clock synchronization at significantly lower cpu load compared to purely software implementations. temperature monitor (part of sata block) system control peripherals the temperature sensor is an internal module to the i.mx53xd that monitors the die temperature. the m onitor is capable in generating sw interrupt, or trigger the ccm, to r educe the core operating frequency. tve tv encoder multimedia the tv encoder, version 2.1 is implemented in c onjunction with the image processing unit (ipu) allowing handheld devices to display captured still images and video directly on a tv or lcd projector. it supports composite pal/ntsc, vga, s-video, and component up to hd1080p analog video outputs. tzic trustzone aware interrupt controller arm/control the trustzone interrupt controller (t zic) collects interrupt requests from all i.mx53xd sources and routes them to the arm core. each interrupt can be configured as a normal or a secure interrupt. software force registers and software priority masking are also supported. uart-1 uart-2 uart-3 uart-4 uart-5 uart interface connectivity peripherals each of the uart blocks supports the following serial data transmit/receive protocols and configurations: ? 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) ? programmable bit-rates up to 4 mbps. this is a higher max baud rate relative to the 1.875 mbps, which is specified by the tia/eia-232-f standard. ? 32-byte fifo on tx and 32 half-word fifo on rx supporting auto-baud ? irda 1.0 support (up to sir speed of 115200 bps) ? option to operate as 8-pins full uart, dce, or dte usb usb controller connectivity peripherals usb supports usb2.0 480 mhz, and contains: ? one high-speed otg sub-block with integrated hs usb phy ? one high-speed host sub-block with integrated hs usb phy ? two identical high-speed host modules the high-speed otg module, which is in ternally connected to the hs usb phy, is equipped with transceiver-less logic to enable on-board usb connectivity without usb transceivers all the usb ports are equipped with standard digital interfaces (ulpi, hs ic-usb) and transceiver-less logic to enable onboard usb connectivity without usb transceivers. table 2. i.mx53xd digital and analog blocks (continued) block mnemonic block name subsystem brief description
i.mx53xd applications processors for consumer products, rev. 2 16 freescale semiconductor modules list vpu video processing unit multimedia peripherals a high-performing video processing unit (vpu) version 3, which covers many sd-level video decoders and sd-level encoders as a multi-standard video codec engine as well as severa l important video processing such as rotation and mirroring. vpu features: ? mpeg-2 decode, mail-high profile, up to 1080i/p resolution, 40 mbps bit rate ? mpeg4/xvid decode, sp/asp profile, up to 1080 i/p resolution, 40 mbps bit rate ? h.263 decode, p0/p3 profile, up to 16cif resolution, 20 mbps bit rate ? sorenson h.263 decode, 4cif resolution, 8 mbps bit rate ? h.264 decode, bp/mp/hp profile, up to 1080 i/p resolution, 40 mbps bit rate ? vc1 decode, sp/mp/ap profile, up to 1080 i/p resolution, 40 mbps bit rate ? rv10 decode, 8/9/2010 profile, up to 1080 i/p resolution, 40 mbps bit rate ? divx decode, 3/4/5/6 profile, up to 1080 i/p resolution, 40 mbps bit rate ? mjpeg decode, baseline profile, up to 8192 x 8192 resolution, 40 mpixel/s bit rate for 4:4:4 format ?mpeg2 1 encode, main-main profile, up to d1 resolution, 15 mbps bit rate ? mpeg4 encode, simple profile, up to 720p resolution, 12 mbps bit rate 2 ? h.263 encode, p0/p3 profile, up to 4cif resolution, 8 mbps bit rate 2 ? h.264 encode, baseline profile, up to 720p resolution, 14 mbps bit rate 2 ? mjpeg encode, baseline profile, up to 8192 x 8192 resolution, 80 mpixel/s bit rate for 4:2:2 format wdog-1 watch dog timer peripherals the watch dog timer supports two comparison points during each counting period. each of the comparison points is configurable to evoke an interrupt to the arm core, and a second point evokes an external event on the wdog line. wdog-2 (tz) watch dog (trustzone) timer peripherals the trustzone watchdog (tz wdog) timer module protects against trustzone starvation by providing a method of escaping normal mode and forcing a switch to the tz mode. tz starvation is a situation where the normal os prevents switching to the tz mode. this situation should be avoided, as it can compromise the s ystem?s security. once the tz wdog module is activated, it must be serviced by tz software on a periodic basis. if servicing does not take place, the timer times out. upon a time-out, the tz wdog asserts a tz mapped interrupt that forces switching to the tz mode. if it is still not served, the tz wdog asserts a security violation signal to the csu. the tz wdog module cannot be programmed or deactivated by a normal mode sw. xtalosc 24 mhz crystal oscillator clocking provides a crystal oscillator am plifier that supports a 24-mhz external crystal xtalosc_ 32k 32.768 khz crystal oscillator i/f clocking provides a crystal oscillator amplif ier that supports a 32.768-khz external crystal. 1 video partially performed in hardware accelerator (70%) and partially in software. 2 vpu can generate higher bit rate than the maximum specified by the corresponding standard. table 2. i.mx53xd digital and analog blocks (continued) block mnemonic block name subsystem brief description
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 17 3.1 special signal considerations the package contact assign ments can be found in section 6, ?package information and contact assignments.? signal descriptions are defined in the i.mx53 reference manual. special signal considerations information is co ntained in chapter 1 of i.mx53 system development user's guide. document number is mx53ug. 4 electrical characteristics this section provides the device and module-level elec trical characteristics for the i.mx53xd processor. note this electrical specificat ion is preliminary. these sp ecifications are not fully tested or guaranteed at this early st age of the product life cycle. finalized specifications will be published afte r thorough characterization and device qualifications have been completed. 4.1 chip-level conditions this section provides the device-level el ectrical characteris tics for the ic. see table 3 for a quick reference to the individual tables and sections. 4.1.1 absolute maximum ratings caution stresses beyond those listed under table 4 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditi ons beyond those indicated under table 7 is not implied. exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability. table 3. i.mx53xd chip-level conditions for these characteristics, ? topic appears ? absolute maximum ratings table 4 on page 18 tepbga-2 package ther mal resistance data table 5 on page 18 i.mx53xd operating ranges table 7 on page 20 external clock sources table 8 on page 22 maximal supply currents table 9 on page 23 usb interface current consumption table 10 on page 25
i.mx53xd applications processors for consumer products, rev. 2 18 freescale semiconductor electrical characteristics 4.1.2 thermal resistance 4.1.2.1 tepbga-2 package thermal resistance table 5 provides the tepbga-2 packag e thermal resistance data. table 4. absolute maximum ratings parameter description symbol min max unit peripheral core supply voltage vcc ?0.3 1.35 v arm core supply voltage vddgp ?0.3 1.35 v supply voltage uhvio supplies denoted as i/o supply ?0.5 3.6 v supply voltage for non uhvio supplies denoted as i/o supply ?0.5 3.3 v usb vbus vbus ? 5.25 v input voltage on usb_otg_dp, usb_otg_dn, usb_h1_dp, usb_h1_dn pins usb_dp/usb_dn ?0.3 3.63 1 1 usb_dn and usb_dp can tolerate 5 v for up to 24 hours. v input/output voltage range v in /v out ?0.5 ovdd +0.3 2 2 the term ovdd in this section refers to the associated supply rail of an input or output. the association is described in ta bl e 1 1 2 on page 154 . the maximum range can be superseded by the dc tables. v esd damage immunity: v esd v ? human body model (hbm) ? charge device model (cdm) ? ? 2000 500 storage temperature range t storage ?40 150 o c table 5. tepbga-2 package thermal resistance data rating board symbol value unit junction to ambient (natural convection) 1, 2 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2 per jedec jesd51-2 with the single layer board horizontal. board meets j esd51-9 specification. single layer board (1s) r ja 28 c/w junction to ambient (natural convection) 1, 2, 3 four layer board (2s2p) r ja 16 c/w junction to ambient (at 200 ft/min) 1, 3 single layer board (1s) r jma 21 c/w junction to ambient (at 200 ft/min) 1, 3 four layer board (2s2p) r jma 13 c/w junction to board 4 ?r jb 6c/w junction to case 5 ?r jc 4c/w junction to package top (natural convection) 6 ? jt 4c/w
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 19 4.1.2.2 pop package thermal resistance table 6 provides the pop package thermal resistance data. 3 per jedec jesd51-6 with the board horizontal. 4 thermal resistance between the die and the printed circuit b oard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. table 6. pop package thermal resistance data 1 1 calculated for just the i.mx53xd package , without the top mounted memory package. rating board symbol as designed center array of pillars used for ground unit junction to ambient (natural convection) 2, 3 2 junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, powe r dissipation of other components on the board, and board thermal resistance. 3 per jedec jesd51-2 with the single layer board ho rizontal. board meets jesd51-9 specification. single layer board (1s) r ja 45 45 c/w junction to ambient (natural convection) 2, 3, 4 4 per jedec jesd51-6 with the board horizontal. four layer board (2s2p) r ja 23 22 c/w junction to ambient (at 200 ft/min) 2, 4 single layer board (1s) r jma 36 35 c/w junction to ambient (at 200 ft/min) 2, 4 four layer board (2s2p) r jma 19 18 c/w junction to board 5 5 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. ?r jb 8.4 7.2 c/w junction to case 6 6 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). ?r jc <0.1 <0.1 c/w junction to package top (natural convection) 7 7 thermal characterization parameter indicating the temper ature difference between package top and the junction temperature per jedec jesd51-2. ? jt 22c/w
i.mx53xd applications processors for consumer products, rev. 2 20 freescale semiconductor electrical characteristics 4.1.3 operating ranges table 7 provides the operating ranges of i.mx53xd processor. table 7. i.mx53xd operating ranges symbol parameter minimum 1 nominal 2 maximum 1 unit vddgp 3 arm core supply voltage f arm 167 mhz 0.85 0.9 0.95 v arm core supply voltage f arm 400 mhz 0.9 0.95 1.05 v arm core supply voltage f arm 800 mhz 1.05 1.1 1.15 v arm core supply voltage f arm 1000 mhz 1.2 1.25 1.3 v arm core supply voltage stop mode 0.8 0.85 1.3 v vcc peripheral supply voltage 1.25 1.3 1.35 v peripheral supply voltage?stop mode 0.9 0.95 1.35 v vdda 4 memory arrays voltage 1.25 1.30 1.35 v memory arrays voltage?stop mode 0.9 0.95 1.35 v vddal1 4 l1 cache memory arrays voltage 1.25 1.30 1.35 v l1 cache memory arrays voltage?stop mode 0.9 0.95 1.35 v vdd_dig_pll 5 pll digital supplies?external regulator option 1.25 1.3 1.35 v vdd_ana_pll 6 pll analog supplies?external regulator option 1.75 1.8 1.95 v nvcc_ckih esd protection of the ckih pins, fuse read supply and 1.8v bias for the uhvio pads 1.65 1.8 1.95 v nvcc_lcd nvcc_jtag gpio digital power supplies 1.65 1.8 or 2.775 3.1 v nvcc_lvds lvds interface supply 2.25 2.5 2.75 v nvcc_lvds_bg lvds band gap supply 2.25 2.5 2.75 v nvcc_emi_dram ddr supply ddr2 range 1.7 1.8 1.9 v ddr supply lpddr2 range 1.14 1.2 1.3 ddr supply lv-ddr2 range 1.47 1.55 1.63 1.42 1.5 1.58 ddr supply ddr3 range 1.42 1.5 1.58 vdd_fuse 7 fusebox program supply (write only) 3.0 ? 3.3 v
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 21 nvcc_nandf nvcc_sd1 nvcc_sd2 nvcc_pata nvcc_keypad nvcc_gpio nvcc_fec nvcc_eim_main nvcc_eim_sec nvcc_csi ultra high voltage i/o (uhvio) supplies: v ? uhvio_l 1.65 1.8 1.95 ? uhvio_h 2.5 2.775 3.1 ? uhvio_uh 3.0 3.3 3.6 tvdac_dhvdd 8 tvdac_ahvddrgb 8 tve digital and analog power supply, tve-to-dac level shifter supply, cable detector supply, analog power supply to rgb channel 2.69 2.75 2.91 v for gpio use only, when tve is not in use 1.65 1.8 or 2.775 3.1 v nvcc_srtc_pow srtc core and slow i/o supply (gpio) 9 1.25 1.3 1.35 v nvcc_reset lvio 1.65 1.8 or 2.775 3.1 v usb_h1_vdda25 usb_otg_vdda25 nvcc_xtal usb_phy analog supply, oscillator amplifier analog supply 10 2.25 2.5 2.75 v usb_h1_vdda33 usb_otg_vdda33 usb phy i/o analog supply 3.0 3.3 3.6 v vbus see ta b l e 4 on page 18 and ta b l e 1 0 5 on page 146 for details. note that this is not a power supply. ???? vdd_reg 11 power supply input for the integrated linear regulators 2.37 2.5 2.63 v vp sata phy core power supply 1.25 1.3 1.35 v vph sata phy i/o supply voltage 2.25 2.5 2.75 v tj junction temperature ?20 95 12 105 o c 1 voltage at the package power supply contact must be maintained between the minimum and maximum voltages. the design must allow for supply tolerances and system voltage drops. 2 the nominal values for the supplies indicate the target setpoint for a tolerance no tighter than 50 mv. use of supplies with a tighter tolerance allows reduction of the setpoint with commensurate power savings. 3 a voltage transition is allowed for the required supply ramp up to the nominal value prior to achieving a clock speed increase. similarly, to accommodate a frequency reduction, a voltage transition is allowed for a supply ramp down to the nominal value after the frequency is decreased. 4 vdda and vddal1 can be driven by the vdd_dig_pll internal regulator using external connections. when operating in this configuration, the regulator is still oper ating at the default 1.2 v, as bootup start. during bootup initialization, software s hould increase this regulator voltage to match vcc (1.3 v nominal) in order to reduce internal leakage current. 5 by default, vdd_dig_pll is driven from internal on-die 1.2 v linear regulator (ldo). in this case, there is no need driving this supply externally. ldo output to vdd_dig_pll should be configured by software after power-up to 1.3 v output. a bypass capacitor of minimal value 22 f should be connected to this pad in any case w hether it is driven internally or externally. use of the on-chip ldo is preferred. see i. mx53 system development user?s guide. table 7. i.mx53xd operating ranges (continued) symbol parameter minimum 1 nominal 2 maximum 1 unit
i.mx53xd applications processors for consumer products, rev. 2 22 freescale semiconductor electrical characteristics 4.1.4 external clock sources the i.mx53xd device has four external input system clocks, a low frequency (ckil), a high frequency (xtal), and two general purpose ckih1 and ckih2 clocks. the ckil is used for low-frequency functions. it supplies the clock for wake-up circuit, power-down real time clock operation, and slow syst em and watch-dog counters. the clock input can be connected to either external oscillator or a crystal us ing internal oscillator amplifier. the system clock input xtal is used to generate the main system clock. it supplies the plls and other peripherals. the system clock input can be connected to ei ther external oscillator or a crystal using internal oscillator amplifier. ckih1 and ckih2 provide additional clock source opt ion for peripherals that require specific and accurate frequencies. table 8 shows the interface frequency requirements. refer to chapter 1 of the i.mx53 system development user's guide for additional clock a nd oscillator information. document number is mx53ug. 4.1.5 maximal supply currents table 9 represents the maximal momentary current transients on power lines, and should be used for power supply selection. maximal currents higher by far than the average power consumpt ion of typical use cases. for typical power consumption information, refer to i.mx53xd power consum ption application note. 6 by default, the vdd_ana_pll is driven from internal on-die 1.8 v linear regulator (ldo). in this case there is no need driving this supply externally. a bypass capacitor of minimal value 22 f should be connected to this pad in any case whether it is driven internally or externally. use of the on-chip ldo is preferred. see i.mx53 syst em development user?s guide. 7 after fuses are programmed, freescale strongly recommends the best practice of reading the fuse s to verify that they are written correctly. in read mode, vdd_fuse should be floated or grounded. tying vdd_fuse to a positive supply (3.0 v?3.3 v) increases the possibility of inadvertently bl owing fuses and is not recommended in read mode. 8 if not using tve module or other pads in this power dom ain for the product, the tvdac_dhvdd and tvdac_ahvddrgb can remain floating. 9 gpio pad operational at low frequency 10 the analog supplies should be isolated in the applicat ion design. use of series inductors is recommended. 11 vdd_reg is power supply input for the integrated linear re gulators of vdd_ana_pll and vdd_dig_pll when they are configured to the internal supply option. vddr_reg st ill has to be tied to 2.5 v supply when vdd_ana_pll and vdd_dig_pll are configured for external power supply mode although in this case it is not used as supply source. 12 lifetime of 21,900 hours based on 95 c junc tion temperature at nominal supply voltages. table 8. external input clock frequency parameter description symbol min typ max unit ckil oscillator 1 1 external oscillator or a crystal with internal oscillator amplifier. f ckil ? 32.768 2 /32.0 2 recommended nominal frequency 32.768 khz. ?khz ckih1, ckih2 operating frequency f ckih1 , f ckih2 see table 33, "camp electrical parameters (ckih1, ckih2)," on page 47 mhz xtal oscillator f xtal 22 24 27 mhz
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 23 table 9. maximal supply currents power line conditions max current unit vddgp 1000 mhz arm clock. 1700 ma vcc 800 ma vdda+vddal1 100 ma vdd_dig_pll 10 ma vp 20 ma vdd_ana_pll 10 ma mvcc_xtal 25 ma vdd_reg 325 ma vdd_fuse fuse write mode operation 120 ma nvcc_emi_dram 1.8v (ddr2) 800 ma 1.5v (ddr3) 650 ma 1.2v (lpddr2) 250 ma tvdac_dhvdd + tvdac_ahvddrgb 200 ma nvcc_srtc_pow <1 ma usb_h1_vdda25 + usb_otg_vdda25 50 ma usb_h1_vdda33 + usb_otg_vdda33 20 ma vph 60 ma nvcc_ckih use maximal io eq 1 , n=4 nvcc_csi use maximal io eq 1 , n=20 nvcc_eim_main use maximal io eq 1 , n=39 nvcc_eim_sec use maximal io eq 1 , n=16 nvcc_emi_dram use maximal io eq 1 , n=78 nvcc_fec use maximal io eq 1 , n=11 nvcc_gpio use maximal io eq 1 , n=13 nvcc_jtag use maximal io eq 1 , n=6 nvcc_kpad use maximal io eq 1 , n=11 nvcc_lcd use maximal io eq 1 , n=29 nvcc_lvds use maximal io eq 1 , n=20
i.mx53xd applications processors for consumer products, rev. 2 24 freescale semiconductor electrical characteristics nvcc_lvds_bg use maximal io eq 1 , n=1 nvcc_nandf use maximal io eq 1 , n=8 nvcc_pata use maximal io eq 1 , n=29 nvcc_rest use maximal io eq 1 , n=5 nvcc_sd1 use maximal io eq 1 , n=6 nvcc_sd2 use maximal io eq 1 , n=6 nvcc_xtal use maximal io eq 1 , n=2 1 general equation for estimated, maximal power consumption of an io power supply: imax = n * c * v * (0.5 * f) where: n - number of io pins supplies by the power line c - equivalent external capacitive load v - io voltage (0.5 * f) - data change rate. up to 0.5 of the clock rate (f). table 9. maximal supply currents (continued) power line conditions max current unit
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 25 4.1.6 usb-oh-3 (otg + 3 host ports) module and the two usb phy (otg and h1) current consumption table 10 shows the usb interfa ce current consumption. 4.2 power supplies requir ements and restrictions the system design must comply with power-up sequence, power-down sequence and steady state guidelines as described in th is section to guarantee the reliable ope ration of the device. any deviation from these sequences may result in the following situations: ? excessive current during power-up phase ? prevention of the device from booting ? irreversible damage to the i.mx 53xd processor (wor st-case scenario) 4.2.1 power-up sequence the following observations should be considered: ?the consequent steps in power up sequence should not start before the previous step supplies have been stabilized within 90-110% of their nominal voltage, unless stated otherwise. ?nvcc_srtc_pow should remain powered on cont inuously, to maintain internal real-time clock status. otherwise, it has to be powe red on together with vcc, or preceding vcc. ?the vcc should be powered on together , or any time after nvcc_srtc_pow. ?nvcc_ckih should be powere d on after vcc is stable a nd before other io supplies (nvcc_xxx) are powered on. table 10. usb interfac e current consumption parameter conditions typical at 25 c max unit analog supply 3.3 v usb_h1_vdda33 usb_otg_vdda33 full speed rx 5.5 6 ma tx 7 8 high speed rx 5 6 tx 5 6 analog supply 2.5 v usb_h1_vdda25 usb_otg_vdda25 full speed rx 6.5 7 ma tx 6.5 7 high speed rx 12 13 tx 21 22 digital supply vcc (1.2 v) full speed rx 8 ? ma tx 8 ? high speed rx 8 ? tx 8 ?
i.mx53xd applications processors for consumer products, rev. 2 26 freescale semiconductor electrical characteristics ?io supplies (nvcc_xxx) below or equal to 2.8 v nom./3.1 v max. should not precede nvcc_ckih. they can start powering on during nvcc_ckih ramp-up, before it is stabilized. within this group, the s upplies can be powered-up in any order. ?io supplies (nvcc_xxx) above 2.8 v nom./3.1 v max. should be powered on only after nvcc_ckih is stable. ?in case vdd_dig_pll and vdd_ana_pll are powe red on from internal voltage regulator (default case for i.mx53xd), there ar e no related restrictions on vdd_re g, as it is used as their internal regulators power source. if vdd_dig_pll and vdd_ana_ pll are powered on externally, to reduce current leakage during the power-up, it is recommended to activ ate the vdd_reg before or at the same time with vdd_dig_pll and vdd _ana_pll. if this sequencing is not possible, make sure that the 2.5 v vdd_reg supply shut-off output impedance is higher than 1 k when it is inactive. ?vdd_reg supply is requi red to be powered on to enable ddr operation. it must be powered on after vcc and before nvcc_em i_dram. the sequence should be: vcc vdd_reg nvcc_emi_dram ?nvcc_eim_dram_2p5 pop additional power line timing is the same as dvv_reg ?vdda and vddal1 can be powered on anytime be fore por_b, regardless of any other power signal. ?vddgp can be powered on anytime before po r_b, regardless of any other power signal. ?vp and vph can be powered up together, or an ytime after, the vcc. vp and vph should come before por. ?tvdac_dhvdd and tvdac_ahvd drgb should be powered from the same regulator. this is due to esd diode protection circuit, that may cause current leakage if one of the supplies is powered on before the other. note the por_b input must be immediatel y asserted at power-up and remain asserted until after the last power rail reaches its working voltage.
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 27 figure 2 shows the power-up sequence diagram. figure 2. power up detailed sequence 1 note need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 v supply (for example, from the parts that use both 1.8 v and the 3.3 v supply). 1. if fuse writing is required, vdd_fuse should be powered on after nvcc_ckih is stable. nvcc_ckih (in any order, after nvcc_ckih por_b t>0 t>0 vcc 90% 90% (in any order, if needed) t>0 90% 90% nvcc_srtc_pow (may remain on) 90% io supplies below or equal to io supplies above 2. 8 v nom./3.1 v max 2.8 v nom./3.1 v max. 90% t>0 90% t>0 t>0 vdd_reg nvcc_emi_dram t>0 (in any order) vp, vph t>0 90% ramp up start, if needed) (in any order) vdda,vddal1,vddgp t>0 90%
i.mx53xd applications processors for consumer products, rev. 2 28 freescale semiconductor electrical characteristics 4.2.2 power-down sequence power-down sequence should follow one of the following two options: option 1: switch all supplies down simultaneously with further free discharge. a deviation of few microseconds of actual power-down of th e different power rails is acceptable. option 2: switch down supplies, in any or der, keeping the following rules: ? nvcc_ckih must be powered down at the same ti me or after the uhvio io cell supplies (for full supply list, refer to ta b l e 7 , ultra high voltage i/o (uhvio) supplies ) . a deviation of few microseconds of actual power-down of the different power rails is acceptable. ? vdd_reg must be powered down at the sa me time or after nvc c_emi_dram supply. a deviation of few microseconds of actual power-down of the different power rails is acceptable. ? if all of the following conditions are met: ?1. vdd_reg is powered down to 0v (not hi-z) ?2. vdd_dig_pll and vdd_ana_pll are provided externally, ?3. vdd_reg is powered down befo re vdd_dig_pll and vdd_ana_pll then the following rule should be kept: vdd_ reg output impedance must be higher than 1 k , when inactive. 4.2.3 power supplies usage ? all io pins should not be externally driven while the io power supply for the pin (nvcc_xxx) is off. this can cause internal latch-up and malfuncti ons due to reverse curren t flows. for information about io power supply of each pin refer to ?power rail? columns in pin list tables of section 6, ?package information and contact assignments.? ? if not using sata interface and the embedde d thermal sensor, the vp and vph should be grounded. in particular, keeping vph turned off while the vp is powered on is not recommended and might lead to excessive power consumption. ? when internal clock source is used for sata temperature monitor the usb_phy supplies and pll need to be active because they are providing the clock. ? if not using tve the module, the tvdac _dhvdd and tvdac_a hvddrgb can remain floating. if only the gpio pads in tvdac_ahvdd rgb domain are in use, the supplies can be set to gpio pad voltage range (1.65 v to 3.1 v). 4.3 i/o dc parameters this section includes the dc parameters of the following i/o types: ? general purpose i/o (gpio) ? double data rate 3 i/o (ddr3) for ddr2/lvddr2, lpddr2 and ddr3 modes ? low voltage i/o (lvio) ? ultra high voltage i/o (uhvio) ?lvds i/o
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 29 note the term ?ovdd? in this section refers to the asso ciated supply rail of an input or output. the association is shown in table 112 . figure 3. circuit for parameters voh and vol for io cells 4.3.1 general purpose i/o (gpio) dc parameters the parameters in table 11 are guaranteed per the operating ranges in table 7 , unless otherwise noted. table 11 shows dc parameters for gpio pa ds, operating at two supply ranges: ? 1.1 v to 1.3 v ? 1.65 v to 3.1 v table 11. gpio i/o dc electrical characteristics parameter symbol test co nditions min typ max unit high-level output voltage 1 voh iout = ?1 ma iout= specified ioh drive ovdd ? 0.15 0.8*ovdd ?? v low-level output voltage 1 vol iout = 1 ma iout= specified iol drive ??0.15 0.2 ovdd v high-level output current (1.1-1.3v ovdd) ioh vout = 0.8 ovdd low drive medium drive high drive max drive ?0.85 ?1.7 ?2.5 ?3.4 ?? ma low-level output current (1.1-1.3v ovdd) iol vout = 0.2 ovdd low drive medium drive high drive max drive 0.9 1.9 2.9 3.8 ?? ma high-level output current (1.65-3.1v ovdd) ioh vout = 0.8 ovdd low drive medium drive high drive max drive ?2.1 ?4.2 ?6.3 ?8.4 ?? ma
i.mx53xd applications processors for consumer products, rev. 2 30 freescale semiconductor electrical characteristics 4.3.2 lpddr2 i/o dc parameters the lpddr2 i/o pads support ddr2/lvddr 2, lpddr2, and ddr3 operational modes. 4.3.2.1 ddr2 mode i/o dc parameters the ddr2 interface fully complies with jesd79-2e ddr2 jedec standard release april, 2008. the parameters in table 12 are guaranteed per the operating ranges in table 7 , unless otherwise noted. low-level output current (1.65-3.1v ovdd) iol vout = 0.2 ovdd low drive medium drive high drive max drive 2.1 4.2 6.3 8.4 ?? ma high-level dc input voltage 1, 2 vih ? 0.7 ovdd ? ovdd v low-level dc input voltage 1, 2 vil ? 0 ? 0.3 ovdd v input hysteresis vhys ovdd = 1.875 v ovdd = 2.775 v 0.25 0.34 0.45 ?v schmitt trigger vt+ 2, 3 vt+ ? 0.5 ovdd ? ? v schmitt trigger vt? 2, 3 vt? ? ? ? 0.5 ovdd v input current (no pull-up/down) iin vin = ovdd or 0 ? ? 2 a input current (22 k pull-up) iin vin = 0 v vin = ovdd ??161 2 a input current (47 k pull-up) iin vin = 0 v vin = ovdd ??76 2 a input current (100 k pull-up) iin vin = 0 v vin= ovdd ??36 2 a input current (100 k pull-down) iin vin = 0 v vin = ovdd ??2 36 a keeper circuit resistance ? 130 4 ?k 1 overshoot and undershoot conditions (transitions above ovdd and below gnd) on switching pads must be held below 0.6 v, and the duration of the overshoot /undershoot must not exceed 10 % of the system clock cycle. overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. non-compliance to this specification may affect de vice reliability or cause permanent damage to the device. 2 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. mo notonic input transition time is from 0.1 ns to 1 s. 3 hysteresis of 250 mv is guaranteed over all oper ating conditions when hysteresis is enabled. 4 use an off-chip pull resistor of less than 60 k to override this keeper. table 11. gpio i/o dc electrical characteristics (continued) parameter symbol test co nditions min typ max unit
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 31 4.3.2.2 lpddr2 mode i/o dc parameters the lpddr2 interface fully complies with jesd 209-2b lpddr2 jedec standard release june, 2009. table 12. ddr2 i/o dc electrical parameters 1 1 note that the jedec sstl_18 specificat ion (jesd8-15a) for a sstl interface for class ii operation supersedes any specification in this document. parameters symbol test co nditions min typ max unit high-level output voltage 2 2 ovdd is the i/o power supply (1.7 v?1.9 v for ddr2) voh ? 0.9*ovdd ? ? v low-level output voltage vol ? ? ? 0.1*ovdd v output minimum source current 3 3 (vout - ovdd) / ioh must be less than 21 for values of vout between ovdd and ovdd-0.28 v. ioh ovdd=1.7 v, vout=1.42 v ?13.4 ? ? ma output min sink current 4 4 vout / iol must be less than 21 for values of vout between 0 v and 280 mv. iol ovdd=1.7 v, vout=280 mv 13.4 ? ? ma input reference voltage vref 0.49*ovdd 0.5*ovdd 0.51*ovdd dc input high voltage (data pins) vihd (dc) ? vref+0.125v ? ovdd+0.3 v dc input low voltage (data pins) vild (dc) ? ?0.3 ? vref-0.125v v dc input voltage range of each differential input 5 5 vin(dc) specifies the allowable dc voltage exertion of each differential input. vin (dc) ? ?0.3 ? ovdd+0.3 v dc differential input voltage required for switching 6 6 vid(dc) specifies the input differential voltage |vtr-vcp| require d for switching, where vtr is the ?true? input level and vcp is the ?complementary? input level. the minimum value is equal to vih(dc) -vil(dc). vid (dc) ? 0.25 ? ovdd+0.6 v termination voltage vtt vtt vref ? 0.04 vref vref + 0.04 v input current (no pull-up/down) iin vin = 0 v vin=ovdd ? ? ? ? 1 1 a keeper circuit resistance ? ? ? 130 7 7 use an off-chip pull resistor of less than 60 k to override this keeper. ?k table 13. lpddr2 i/o dc electrical parameters 1 parameters symbol test co nditions min typ max unit high-level output voltage voh ? 0.9*ovdd ? ? v low-level output voltage vol ? ? ? 0.1*ovdd v input reference voltage vref 0.49*ovdd 0.5*ovdd 0.51*ovdd dc input high voltage vih(dc) ? vref+0.13v ? ovdd v dc input low voltage vil(dc) ? ovss ? vref-0.13v v
i.mx53xd applications processors for consumer products, rev. 2 32 freescale semiconductor electrical characteristics 4.3.2.3 ddr3 mode i/o dc parameters the ddr3 interface fully complies with jesd79-3d ddr3 jedec standard release april, 2008. the parameters in table 14 are guaranteed per the operating ranges in table 7 , unless otherwise noted. differential input logic high vih(diff) 0.26 see note 2 differential input logic low vil(diff) see note 2 -0.26 input current (no pull-up/down) iin vin = 0 v vin=ovdd ? ? ? ? 1 1 a pull-up/pull-down impedance mismatch -15 +15 % 240 ohm unit calibration resolution 10 ohm keeper circuit resistance ? ? ? 140 3 ?k 1 note that the jedec lpddr2 specif ication (jesd209_2b) supersedes any specification in this document. 2 the single-ended signals need to be within the respective limits (vih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. 3 use an off-chip pull resistor of less than 60 k to override this keeper. table 14. ddr3 i/o dc electrical parameters parameters symbol test conditions min typ max unit high-level output voltage voh ? 0.8*ovdd 1 1 ovdd ? i/o power supply (1.425 v?1.575 v for ddr3) ??v low-level output voltage vol ? ? ? 0.2*ovdd v dc input logic high vih(dc) ? vref 2 +0.1 2 vref ? ddr3 external reference voltage ?ovddv dc input logic low vil(dc) ? ovss ? vref-0.1 v differential input logic high vih(diff) ? 0.2 ? see note 3 v differential input logic low vil(diff) ? see note 3 ?-0.2v over/undershoot peak vpeak ? ? ? 0.4 v over/undershoot area (above ovdd or below ovss) varea ? ? ? 0.67 v x ns termination voltage vtt vtt tracking ovdd/2 0.49*ovdd vref 0.51*ovdd v input current (no pull-up/down) iin vi = 0 v vi=ovdd ? ? ? ? 1 1 a pull-up/pull-down impedance mismatch ? minimum impedance configuration ?? 3 240 unit calibration resolution ? ? ? ? 10 keeper circuit resistance ? ? ? 130 4 ?k table 13. lpddr2 i/o dc electrical parameters 1 (continued)
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 33 4.3.3 low voltage i/o (lvio) dc parameters the parameters in table 15 are guaranteed per the operating ranges in table 7 , unless otherwise noted. the lvio pads opera te only as inputs. 3 the single-ended signals need to be within the respective limits (vih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. 4 use an off-chip pull resistor of less than 60 k to override this keeper. table 15. lvio dc electrical characteristics dc electrical characteristics symb ol test conditions min typ max unit high-level dc input voltage 1, 2 1 overshoot and undershoot condit ions (transitions above ovdd and below gnd) on switching pads must be held below 0.6 v, and the duration of the overshoot/undersh oot must not exceed 10% of the system clock cycle. overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. monotonic input transition time is fr om 0.1 ns to 1 s. vil and vih do not apply when hysteresis is enabled. vih ? 0.7 ovdd ? ovdd v low-level dc input voltage 1, 2 vil ? 0 ? 0.3 ovdd v input hysteresis vhys ovdd = 1.875 v ovdd = 2.775 v 0.35 0.62 1.27 ?v schmitt trigger vt+ 2, 3 3 hysteresis of 350 mv is guaranteed over all o perating conditions when hysteresis is enabled. vt+ ? 0.5 ovdd ? ? v schmitt trigger vt? 2, 3 vt? ? ? ? 0.5 ovdd v input current (no pull-up/down) iin vin = ovdd or 0 v ? ? 1 a input current (22 k pull-up) iin vin = 0 v vin = ovdd ? ? 161 1 a input current (47 k pull-up) iin vin = 0 v vin = ovdd ??76 1 a input current (100 k pull-up) iin vin = 0 v vin = ovdd ??36 1 a input current (100 k pull-down) iin vin = 0 v vin = ovdd ?? 1 36 a keeper circuit resistance ? ? 130 4 4 use an off-chip pull resistor of less than 60 k to override this keeper. ?k
i.mx53xd applications processors for consumer products, rev. 2 34 freescale semiconductor electrical characteristics 4.3.4 ultra-high voltage i/o (uhvio) dc parameters the parameters in table 16 are guaranteed per the operating ranges in table 7 , unless otherwise noted. table 16. uhvio dc electrical characteristics dc electrical characteristics symbol test conditions min typ max unit high-level output voltage 1 voh iout = ?1ma iout= specified ioh drive ovdd?0.15 0.8 * ovdd ??v low-level output voltage 1 vol iout = 1ma iout= specified ioh drive ? ? 0.15 0.2 * ovdd v high-level output current, low voltage mode ioh_lv vout = 0.8 ovdd low drive medium drive high drive ?2.2 ?4.4 ?6.6 ??ma high-level output current, high voltage mode ioh_hv vout = 0.8 ovdd low drive medium drive high drive ?5.1 ?10.2 ?15.3 ??ma low-level output current, low voltage mode iol_lv vout = 0.2 ovdd low drive medium drive high drive 2.2 4.4 6.6 ??ma low-level output current, high voltage mode iol_hv vout = 0.2 ovdd low drive medium drive high drive 5.1 10.2 15.3 ??ma high-level dc input voltage 1, 2 vih ? 0.7 ovdd ? ovdd v low-level dc input voltage 1, 2 vil ? 0 ? 0.3 ovdd v input hysteresis vhys low voltage mode high voltage mode 0.38 0.95 ?0.43 1.33 v schmitt trigger vt+ 2, 3 vt+ ? 0.5 ovdd ? ? v schmitt trigger vt? 2, 3 vt? ? ? ? 0.5 ovdd v input current (no pull-up/down) iin vin = ovdd or 0 v ? ? 1 a input current (22 k pull-up) iin vin = 0 vin = ovdd ? ? 202 1 a input current (75 k pull-up) iin vin = 0 vin = ovdd ??61 1 a input current (100 k pull-up) iin vin = 0 vin = ovdd ??47 1 a input current (360 k pull-down) iin vin = 0 vin = ovdd ?? 1 5.7 a keeper circuit resistance ? ? ? 130 4 ?k
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 35 4.3.5 lvds i/o dc parameters the lvds interface complies with tia/eia 644-a standard. see tia/eia standard 644-a, ?electrical characteristics of low voltage differential signaling (lvd s) interface circuits? for details. table 17 shows the low voltage differential si gnaling (lvds) dc elect rical characteristics. 4.4 output buffer impedance characteristics this section defines the i/o impedance parameters of the i.mx53xd processor for the following i/o types: ? general purpose i/o (gpio) ? double data rate 3 i/o (ddr3) for ddr2/lvddr2, lpddr2, and ddr3 modes ? ultra high voltage i/o (uhvio) ?lvds i/o note output driver impedance is measured with ?long? transmission line of impedance ztl attached to i/o pad and incident wave launched into transmission lime. rpu/r pd and ztl form a voltag e divider that defines specific voltage of incident wave relative to ovdd. output driver impedance is calculated from this voltage divider (see figure 4 ). 1 overshoot and undershoot conditions (transitions above ovdd and below gnd) on switching pads must be held below 0.6 v, and the duration of the overshoot/unders hoot must not exceed 10% of the system clock cycle. overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 to maintain a valid level, the transitioning edge of the input must sustain a constant slew ra te (monotonic) from the current dc level to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. vil and vih do not apply when hysteresis is enabled. 3 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. 4 use an off-chip pull resistor of less than 60 k to override this keeper. table 17. lvds dc electrical characteristics dc electrical characteristics symb ol test conditions min typ max unit output differential voltage v od rload=100 padp, ?padn 250 350 450 mv output high voltage v oh 1.25 1.375 1.6 v output low voltage v ol 0.9 1.025 1.25 offset voltage v os 1.125 1.2 1.375
i.mx53xd applications processors for consumer products, rev. 2 36 freescale semiconductor electrical characteristics figure 4. impedance matching load for measurement ipp_do cload = 1p ztl , l = 20 inches predriver pmos (rpu) nmos (rpd) pad ovdd ovss t,(ns) 0 u,(v) ovdd t,(ns) 0 vdd vin (do) vout (pad) u,(v) vref rpu = vovdd?vref1 vref1 ztl rpd = ztl vref2 vovdd?vref2 vref1 vref2
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 37 4.4.1 gpio output buffer impedance table 18 shows the gpio output buffer impedance. 4.4.2 ddr output driver average impedance the ddr2/lvddr2 interface fully co mplies with jesd79-2e ddr2 je dec standard release april, 2008. the ddr3 interface fully complies with jesd79- 3d ddr3 jedec standard release april, 2008. table 18. gpio output buffer impedance parameter symbol test conditions min typ max unit ovdd 2.775 v ovdd 1.875 v output driver impedance rpu low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength, ztl = 37.5 80 40 27 20 104 52 35 26 150 75 51 38 250 125 83 62 output driver impedance rpd low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 max drive strength, ztl = 37.5 64 32 21 16 88 44 30 22 134 66 44 34 243 122 81 61
i.mx53xd applications processors for consumer products, rev. 2 38 freescale semiconductor electrical characteristics table 19 shows ddr output driver average impedance of the i.mx53 processor. table 19. ddr output driver average impedance 1 1 output driver impedance is controlled across pvts (process, voltages, and temperatures) using calibration procedure and pu_*cal, pd_*cal input pins. parameter symbol test conditions drive strength (dse) unit 000 001 010 011 100 101 110 111 output driver impedance rdrv 2 2 output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across pvts. lpddr1/ddr2 mode nvcc_dram = 1.8 v ddr_sel = 00 calibration resistance = 300 3 3 calibration is done against external reference resistor. value of the resistor should be varied depending on ddr mode and ddr_sel setting. hi-z 300 150 100 75 60 50 43 ddr2 mode nvcc_dram = 1.8 v ddr_sel = 01 calibration resistance = 180 3 hi-z 180 90 60 45 36 30 26 ddr2 mode nvcc_dram = 1.8 v ddr_sel = 10 calibration resistance = 200 3 hi-z 200 100 66 50 40 33 28 ddr2 mode nvcc_dram= 1.8 v ddr_sel = 11 calibration resistance = 140 3 hi-z 140 70 46 35 28 23 20 lpddr2 mode nvcc_dram= 1.2 v ddr_sel = 01 4 calibration resistance = 160 3 4 if ddr_sel = ?01? or ddr_sel = ?11? are selected with nvcc_ dram = 1.2 v for lpddr2 operation, the external reference resistor value must be 160 for a correct zq calibration. in any case, refer ence resistors attached to the ddr memory devices should be kept to 240 per the jedec standard. hi-z 160 80 53 40 32 27 23 lpddr2 mode nvcc_dram = 1.2 v ddr_sel = 10 calibration resistance = 240 3 hi-z 240 120 80 60 48 40 34 lpddr2 mode nvcc_dram = 1.2 v ddr_sel = 11 4 calibration resistance = 160 3 hi-z 160 80 53 40 32 27 23 ddr3 mode nvcc_dram = 1.5 v ddr_sel = 00 calibration resistance = 200 3 hi-z 240 120 80 60 48 48 34
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 39 4.4.3 uhvio output buffer impedance table 20 shows the uhvio output buffer impedance. 4.4.4 lvds i/o output buffer impedance the lvds interface complies with tia/eia 6 44-a standard. see, tia/eia standard 644-a, ?electrical characteristics of low voltage differential signaling (lvd s) interface circuits? for details. 4.5 i/o ac parameters this section includes the ac parameters of the following i/o types: ? general purpose i/o (gpio) ? double data rate 3 i/o (ddr3) for ddr2/lvddr2, lpddr2 and ddr3 modes ? low voltage i/o (lvio) ? ultra high voltage i/o (uhvio) ?lvds i/o the load circuit and output transi tion time waveforms are shown in figure 5 and figure 6 . figure 5. load circuit for output figure 6. output transition time waveform table 20. uhvio output buffer impedance parameter symbol test conditions min typ max unit ovdd 1.95 v ovdd 3.0 v ovdd 1.875 v ovdd 3.3 v ovdd 1.65 v ovdd 3.6 v output driver impedance rpu low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 98 49 32 114 57 38 124 62 41 135 67 45 198 99 66 206 103 69 output driver impedance rpd low drive strength, ztl = 150 medium drive strength, ztl = 75 high drive strength, ztl = 50 97 49 32 118 59 40 126 63 42 154 77 51 179 89 60 217 109 72 test point from output under test cl cl includes package, probe and fixture capacitance 0v ovdd 20% 80% 80% 20% tr tf output (at pad)
i.mx53xd applications processors for consumer products, rev. 2 40 freescale semiconductor electrical characteristics 4.5.1 gpio i/o ac electrical characteristics ac electrical characteristics for gpio i/o in slow and fast modes are presented in the table 21 and table 22 , respectively. note that the fast or slow i/o behavior is determin ed by the appropriate control bit in the iomuxc control registers. table 21. gpio i/o ac parameters slow mode parameter symbol test condition min typ max unit output pad transition times (max drive) tr, tf 15 pf 35 pf ?? 1.91/1.52 3.07/2.65 ns output pad transition times (high drive) tr, tf 15 pf 35 pf ?? 2.22/1.81 3.81/3.42 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf ?? 2.88/2.42 5.43/5.02 ns output pad transition times (low drive) tr, tf 15 pf 35 pf ?? 4.94/4.50 10.55/9.70 ns output pad slew rate (max drive) 1 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. tps 15 pf 35 pf 0.5/0.65 0.32/0.37 ?? v/ns output pad slew rate (high drive) 1 tps 15 pf 35 pf 0.43/0.54 0.26/0.41 ?? output pad slew rate (medium drive) 1 tps 15 pf 35 pf 0.34/0.41 0.18/0.2 ?? output pad slew rate (low drive) 1 tps 15 pf 35 pf 0.20/0.22 0.09/0.1 ?? output pad di/dt (max drive) tdit ? ? ? 30 ma/ns output pad di/dt (high drive) tdit ? ? ? 23 output pad di/dt (medium drive) tdit ? ? ? 15 output pad di/dt (low drive) tdit ? ? ? 7 input transition times 2 2 hysteresis mode is recommended for input s with transition times greater than 25 ns. trm ? ? ? 25 ns table 22. gpio i/o ac parameters fast mode parameter symbol test condition min typ max unit output pad transition times (max drive) tr, tf 15 pf 35 pf ? ? 1.45/1.24 2.76/2.54 ns output pad transition times (high drive) tr, tf 15 pf 35 pf ? ? 1.81/1.59 3.57/3.33 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf ? ? 2.54/2.29 5.25/5.01 ns
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 41 4.5.2 lpddr2 i/o ac electrical characteristics the ddr2/lvddr2 interface mode fully complies with jesd79-2e ddr2 jedec standard release april, 2008. the ddr3 interface mode fully compli es with jesd79-3d ddr3 jedec standard release april, 2008. table 23 shows the ac parameters for lpddr2 i/o operating in ddr2 mode. output pad transition times (low drive) tr, tf 15 pf 35 pf ?? 4.82/4.5 10.54/9.95 ns output pad slew rate (max drive) 1 tps 15 pf 35 pf 0.69/0.78 0.36/0.39 ?? v/ns output pad slew rate (high drive) 1 tps 15 pf 35 pf 0.55/0.62 0.28/0.30 ?? v/ns output pad slew rate (medium drive) 1 tps 15 pf 35 pf 0.39/0.44 0.19/0.20 ?? v/ns output pad slew rate (low drive) 1 tps 15 pf 35 pf 0.21/0.22 0.09/0.1 ?? v/ns output pad di/dt (max drive) tdit ? ? ? 70 ma/ns output pad di/dt (high drive) tdit ? ? ? 53 ma/ns output pad di/dt (medium drive) tdit ? ? ? 35 ma/ns output pad di/dt (low drive) tdit ? ? ? 18 ma/ns input transition times 2 trm ? ? ? 25 ns 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 2 hysteresis mode is recommended for inputs with transition time greater than 25 ns. table 23. lpddr2 i/o ddr2 mode ac characteristics 1 1 note that the jedec sstl_18 specificat ion (jesd8-15a) for class ii operation supersedes any specification in this document. parameter symbol test condition min typ max unit ac input logic high vih(ac) ? vref+0.25 ?? v ac input logic low vil(ac) ??? vref-0.25 v ac differential input voltage 2 vid(ac) ? 0.5 ? ovdd v input ac differential cross point voltage 3 vix(ac) ? vref ? 0.175 ?vref+0.175 v output ac differential cross point voltage 4 vox(ac) ? vref ? 0.125 ?vref+0.125 v single output slew rate tsr at 25 to vref 0.4 ? 2 v/ns skew between pad rise/fall asymmetry + skew caused by ssn t skd clk=266mhz clk=400mhz ??0.2 0.1 ns table 22. gpio i/o ac parameters fast mode (continued) parameter symbol test condition min typ max unit
i.mx53xd applications processors for consumer products, rev. 2 42 freescale semiconductor electrical characteristics table 24 shows the ac parameters for lpddr2 i/o operating in lpddr2 mode. table 25 shows the ac parameters for lpddr2 i/o operating in ddr3 mode. 2 vid(ac) specifies the input differential voltage |vtr ? vcp| requir ed for switching, where vtr is the ?true? input signal and vcp is the ?complementary? input signal. the mini mum value is equal to vih(ac) ? vil(ac). 3 the typical value of vix(ac) is expected to be about 0.5 * ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which di fferential input signal must cross. 4 the typical value of vox(ac) is expected to be about 0.5 * ovdd and vox(ac) is expected to track variation in ovdd. vox(ac) indicates the voltage at which diff erential output signal must cross. table 24. lpddr2 i/o lpddr2 mode ac characteristics 1 1 note that the jedec lpddr2 spec ification (jesd209_2b) supersedes an y specification in this document. parameter symbol test condition min typ max unit ac input logic high vih(ac) ? vref + 0.22 ? ovdd v ac input logic low vil(ac) ? 0 ? vref ? 0.22 v ac differential input high voltage 2 2 vid(ac) specifies the input differential vo ltage |vtr ? vcp| required for switching, wher e vtr is the ?true? input signal and vcp is the ?complementary? input signal. the minimum value is equal to vih(ac) ? vil(ac). vidh(ac) ? 0.44 ? ? v ac differential input low voltage vidl(ac) ? ? ? 0.44 v input ac differential cross point voltage 3 3 the typical value of vix(ac) is expected to be about 0.5 * ovdd. and vix(ac) is expec ted to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. vix(ac) relative to ovdd/2 -0.12 ? 0.12 v over/undershoot peak vpeak ? ? ? 0.35 v over/undershoot area (above ovdd or below ovss) varea 266mhz ? ? 0.6 v*ns single output slew rate tsr 50ohm to vref. 5pf load. drive impedance= 40ohm +-30% 1.5 ? 3.5 v/ns 50ohm to vref. 5pf load.drive impedance= 60ohm +-30% 1?2.5 skew between pad rise/fall asymmetry + skew caused by ssn t skd clk=266mhz clk=400mhz ??0.2 0.1 ns table 25. lpddr2 i/o ddr3 mode ac characteristics 1 parameter symbol test condition min typ max unit ac input logic high vih(ac) ? vref + 0.175 ? ovdd v ac input logic low vil(ac) ? 0 ? vref ? 0.175 v ac differential input voltage 2 vid(ac) ? 0.35 ? ? v input ac differential cross point voltage 3 vix(ac) ? vref ? 0.15 ? vref + 0.15 v
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 43 4.5.3 lvio i/o ac electrical characteristics ac electrical characteristics for lvio i/o in slow and fast modes are presented in the table 26 and table 27 , respectively. note that the fast or slow i/o behavior is determin ed by the appropriate control bit in the iomuxc control registers. output ac differential cross point voltage 4 vox(ac) ? vref ? 0.15 ? vref + 0.15 v single output slew rate tsr at 25 to vref 2.5 ? 5 v/ns skew between pad rise/fall asymmetry + skew caused by ssn t skd clk=266mhz clk=400mhz ??0.2 0.1 ns 1 note that the jedec jesd79_3c specification supersedes any specification in this document. 2 vid(ac) specifies the input differential volt age |vtr-vcp| required for switching, where vtr is the ?true? input signal and vcp is the ?complementary? input signal. the mini mum value is equal to vih(ac) ? vil(ac). 3 the typical value of vix(ac) is expected to be about 0.5 * ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which di fferential input signal must cross. 4 the typical value of vox(ac) is expected to be about 0.5 * ovdd and vox(ac) is expected to track variation in ovdd. vox(ac) indicates the voltage at which diff erential output signal must cross. table 26. lvio i/o ac parameters in slow mode parameter symbol test condition min typ max unit input transition times 1 1 hysteresis mode is recommended for input s with transition times greater than 25 ns. trm ? ? ? 25 ns table 25. lpddr2 i/o ddr3 mo de ac characteristics 1 (continued) parameter symbol test condition min typ max unit
i.mx53xd applications processors for consumer products, rev. 2 44 freescale semiconductor electrical characteristics 4.5.4 uhvio i/o ac elec trical characteristics table 28 shows the ac parameters for uhvio i/ o operating in low output voltage mode. table 29 shows the ac parameters for uhvio i/o operating in high output voltage mode. table 27. lvio i/o ac parameters in fast mode parameter symbol test condition min typ max unit input transition times 1 1 hysteresis mode is recommended for inputs with transition time greater than 25 ns. trm ? ? ? 25 ns table 28. ac electrical characteristics of uhvio pad (low output voltage mode) parameter symbol test condition min typ max unit output pad transition times (high drive) tr, tf 15 pf 35 pf ? ? 1.59/1.69 3.05/3.30 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf ? ? 2.16/2.35 4.45/4.84 output pad transition times (low drive) tr, tf 15 pf 35 pf ? ? 4.06/4.42 8.79/9.55 output pad slew rate (high drive) 1 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. tps 15 pf 35 pf 0.63/0.59 0.33/0.30 ?? v/ns output pad slew rate (medium drive) 1 tps 15 pf 35 pf 0.46/0.42 0.22/0.21 ?? output pad slew rate (low drive) 1 tps 15 pf 35 pf 0.25/0.23 0.11/0.11 ?? output pad di/dt (high drive) tdit ? ? ? 43.6 ma/ns output pad di/dt (medium drive) tdit ? ? ? 32.3 output pad di/dt (low drive) tdit ? ? ? 18.24 input transition times 2 2 hysteresis mode is recommended for input s with transition times greater than 25 ns. trm ? ? ? 25 ns table 29. ac electrical characteristics of uhvio pad (high output voltage mode) parameter symbol test condition min typ max unit output pad transition times (high drive) tr, tf 15 pf 35 pf ? ? 1.72/1.92 3.46/3.70 ns output pad transition times (medium drive) tr, tf 15 pf 35 pf ? ? 2.38/2.56 5.07/5.25 output pad transition times (low drive) tr, tf 15 pf 35 pf ? ? 4.55/4.58 10.04/9.94
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 45 4.5.5 lvds i/o ac electrical characteristics the differential output transiti on time waveform is shown in figure 7 . figure 7. differential lvds driv er transition time waveform table 30 shows the ac parameters for lvds i/o. output pad slew rate (high drive) 1 tps 15 pf 35 pf 1.05/0.94 0.52/0.49 ?? v/ns output pad slew rate (medium drive) 1 tps 15 pf 35 pf 0.76/0.71 0.36/0.34 ?? output pad slew rate (low drive) 1 tps 15 pf 35 pf 0.40/0.93 0.18/0.18 ?? output pad di/dt (high drive) tdit ? ? ? 82.8 ma/ns output pad di/dt (medium drive) tdit ? ? ? 65.6 output pad di/dt (low drive) tdit ? ? ? 43.1 input transition times 2 trm ? ? ? 25 ns 1 tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 2 hysteresis mode is recommended for input s with transition times greater than 25 ns. table 30. ac electrical characteristics of lvds pad parameter symbol test condition min typ max unit transition low to high time 1 1 measurement levels are 20- 80% from output voltage. t tlh rload = 100 , cload = 2 pf 0.26 ? 0.5 ns transition high to low time 1 t thl 0.26 ? 0.5 operating frequency f ? ? 300 ? mhz offset voltage imbalance vos ? ? ? 150 mv table 29. ac electrical characteristics of uhv io pad (high output voltage mode) (continued) parameter symbol test condition min typ max unit
i.mx53xd applications processors for consumer products, rev. 2 46 freescale semiconductor electrical characteristics 4.6 system modules timing this section contains the timing and electrical para meters for the modules in the i.mx53xd processor. 4.6.1 reset timings parameters figure 8 shows the reset timing and table 31 lists the timing parameters. figure 8. reset timing diagram 4.6.2 wdog reset timing parameters figure 9 shows the wdog reset timing and table 32 lists the timing parameters. figure 9. watchdog_rst timing diagram note ckil is approximately 32 khz. t ckil is one period or approximately 30 s. 4.6.3 clock amplifier parameters (ckih1, ckih2) the input to clock amplifier (camp) is internally ac -coupled allowing direct inte rface to a square wave or sinusoidal frequency source. no ex ternal series capacitors are required. table 31. reset timing parameters id parameter min max unit cc1 duration of reset_in to be qualified as valid (input slope = 5 ns) 50 ? ns table 32. watchdog_rst timing parameters id parameter min max unit cc5 duration of watchdog_reset assertion 1 ? t ckil reset_in cc1 (input) watchdog_rst cc5 (input)
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 47 table 33 shows the electrical parameters of camp. 4.6.4 dpll electrical parameters table 34 shows the electrical parameters of digital phase-locked loop (dpll). table 33. camp electrical parameters (ckih1, ckih2) parameter min typ max unit input frequency 8.0 ? 40.0 mhz vil (for square wave input) 0 ? 0.3 v vih (for square wave input) 1 1 nvcc_ckih is the supply voltage of camp. nvcc_ckih ? 0.25 ? nvcc_ckih v sinusoidal input amplitude 0.4 ? vdd vp-p output duty cycle 45 50 55 % table 34. dpll electrical parameters parameter test conditions/remarks min typ max unit reference clock frequency range 1 1 device input range cannot exceed the electr ical specifications of the camp, see ta b l e 3 3 . ?10?100mhz reference clock frequency range after pre-divider ?10?40mhz output clock frequency range (dpdck_2) ? 300 ? 1025 mhz pre-division factor 2 2 the values specified here are internal to dpll. inside the dpll, a ?1? is added to the value specified by the user. therefore, the user has to enter a value ?1? less than the desired value at the inputs of dpll for pdf and mfd. ?1?16? multiplication factor integer part ? 5 ? 15 ? multiplication factor numerator 3 3 the maximum total multiplication factor (mfi + mfn/mfd) allowed is 15. therefore, if the mfi value is 15, mfn value must be zero. should be less than denominator ?67108862 ? 67108862 ? multiplication factor denominator 2 ? 1 ? 67108863 ? output duty cycle ? 48.5 50 51.5 % frequency lock time 4 (fol mode or non-integer mf) ???398 t d pdref phase lock time ? ? ? 100 s frequency jitter 5 (peak value) ? ? 0.02 0.04 t dck phase jitter (peak value) fpl mode, integer and fractional mf ? 2.0 3.5 ns power dissipation f dck = 300 mhz at avdd = 1.8 v, dvdd = 1.2 v f dck = 650 mhz at avdd = 1.8 v, dvdd = 1.2 v ? ? 0.65 (avdd) 0.92 (dvdd) 1.98 (avdd) 1.8 (dvdd) mw
i.mx53xd applications processors for consumer products, rev. 2 48 freescale semiconductor electrical characteristics 4.6.5 nand flash controller (nfc) parameters this section provides the relative ti ming requirements among vari ous signals of nfc at the module level, in each operational mode. timing parameters in figure 10 , figure 11 , figure 12 , figure 13 , figure 15 , and table 36 show the default nfc mode (asymmetric mode) us ing two flash clock cycles pe r one access of re_b and we_b. timing parameters in figure 10 , figure 11 , figure 12 , figure 14 , figure 15 , and table 36 show symmetric nfc mode using one flash clock cycl e per one access of re_b and we_b. with reference to the timing diagrams, a high is defi ned as 80% of signal value a nd low is defined as 20% of signal value. all parameters are given in nanosec onds. the bga contact load used in calculations is 20 pf (except for nf16 - 40 pf) and there is maximum drive strengt h on all contacts. all timing parameters are a function of t, which is the period of the flas h_clk clock (?enfc_clk? at system level). this clock frequency can be controlled by th e user, configuring ccm (soc clock controller). the clock is derived from emi_sl ow_clk after single divider. figure 35 demonstrates several examples of clock frequency settings. note a potential limitation for minimum clock frequency may exist for some devices. when the clock frequency is too low, the data bus capturing might occur after the specified t rhoh (re_b high to output hold) period. setting the clock frequency above 25.6 mhz (tha t is, t = 39 ns) guaranties a proper operation for devices having t rhoh > 15 ns. it is also recommended that the nfc_freq_sel fuse be set accordi ngly to initiate the boot with 33.33 mhz clock. 4 t dpdref is the time period of the reference clock after predivider. a ccording to the specification, the maximum lock time in fol mode is 398 cycles of divided reference clock when dpll starts after full reset. 5 tdck is the time period of the output clock, dpdck_2. table 35. nfc clock settings examples emi_slow_clk (mhz) nfc_podf (division f actor) enfc_clk (mhz) t-clock period (ns) 100 (boot mode) 7 1 1 boot value nfc_freq_sel fuse high (burned) 14.29 70 3 2 2 boot value nfc_freq_sel fuse low 33.33 30 133 4 33.33 30 3 44.33 3 3 for rbb_mode=1, using nandf_rb0 signal for ready/busy indica tion. this mode require setting the delay line. see the reference manual for details. 22.5 266 3 15
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 49 lower frequency operation can be suppo rted for most available devices in the market, relying on data lines bus-ke eper logic. this depends on device behavior on the data bus in the time interval between data output valid to data output high-z state. in nand devi ce parameters this period is marked between t rhoh and t rhz (re_b high to output high-z). in most devices, the data transition from valid value to high-z occurs without going through other states. setting the da ta bus pads to bus-keep er mode in the iomuxc registers, keeps the data bus valid in ternally after the specified hold time, allowing proper capturing with slower clock. figure 10. command latch cycle timing figure 11. address latch cycle timing nfcle nfce_b nfwe_b nfio[7:0] command nf9 nf8 nf1 nf2 nf5 nf3 nf4 nfce_b nfwe_b nfale nfio[7:0] address nf9 nf8 nf5 nf3 nf4 nf6 nf11 nf10 nf7
i.mx53xd applications processors for consumer products, rev. 2 50 freescale semiconductor electrical characteristics figure 12. write data latch timing figure 13. read data latch timing, asymmetric mode figure 14. read data latch timing, symmetric mode nfce_b nfwe_b nfio[15:0] data to nf nf9 nf8 nf5 nf3 nf11 nf10 nfce_b nfre_b nfrb_b nfio[15:0] data from nf nf13 nf15 nf14 nf17 nf12 nf16 nfce_b nfre_b nfrb_b nfio[15:0] data from nf nf13 nf15 nf14 nf12 nf16 nf18
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 51 figure 15. other timing parameters nfcle nfce_b nfre_b nfrb_b nfwe_b nf20 nf19 nf21 nf22
i.mx53xd applications processors for consumer products, rev. 2 52 freescale semiconductor electrical characteristics table 36. nfc?timing characteristics id parameter symbol asymmetric mode min symmetric mode min max nf1 nfcle setup time t cls 2t + 0.1 2t + 0.1 ? nf2 nfcle hold time t clh t ? 4.45 t ? 4.45 ? nf3 1 1 in case of num_of_devices is greater than 0 (for example, interleaved mode), then only during the data phase of symmetric mode the setup time will equal 1.5t + 0.95. nfce_b setup time t cs 3t + 0.95 3t+0.95 ? nf4 nfce_b hold time t ch 2t?5.55 1.5t?5.55 ? nf5 nfwe_b pulse width t wp t?1.4 0.5t?1.4 ? nf6 nfale setup time t als 2t + 0.1 2t + 0.1 ? nf7 nfale hold time t alh t ? 4.45 t ? 4.45 ? nf8 data setup time t ds t?0.9 0.5t?0.9 ? nf9 data hold time t dh t ? 5.55 0.5t ? 5.55 ? nf10 write cycle time t wc 2t t?0.5 ? nf11 nfwe_b hold time t wh t ? 1.15 0.5t ? 1.15 ? nf12 ready to nfre_b low t rr 9t + 8.9 9t + 8.9 ? nf13 nfre_b pulse width t rp 1.5t 0.5t?1 ? nf14 read cycle time t rc 2t t ? nf15 nfre_b high hold time t reh 0.5t ? 1.15 0.5t ? 1.15 ? nf16 2 2 t dsr is calculated by the following formula: asymmetric mode: t dsr = t repd + t dpd + 1 / 2 t ? tdl 2 symmetric mode: t dsr = t repd + t dpd ? tdl 2 t repd + t dpd = 11.2 ns (including clock skew) where t repd is re propogation delay in the chip including i/o pad delay, and t dpd is data propogation delay from i/o pad to extmc including i/o pad delay. t dsr can be used to determine t rea max parameter with the following formula: t rea = 1.5t ? t dsr . data setup on read t dsr 11.2 + 0.5t ? tdl 3 3 tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (t aclk ). default is 1/4 aclk period for each delay-line unit, so all 4 dela y lines together generates a total of 1 aclk period. t aclk is ?emi_slow_clk? of the system, which default value is 7.5 ns (133 mhz). 11.2 ? tdl 2 ? nf17 4 data hold on read t dhr 0?2t aclk +t nf18 5 data hold on read t dhr ?tdl 2 ?11.2 2t aclk +t nf19 cle to re delay t clr 9t 9t ? nf20 ce to re delay t cre t?3.45 t?3.45 t+0.3 nf21 we high to re low t whr 10.5t 10.5t ? nf22 we high to busy t wb ??6t
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 53 4.6.6 external interface module (eim) the following subsections pr ovide information on the eim. 4.6.6.1 eim signal cross reference table 37 is a guide intended to help the user identify signals in the ex ternal interface m odule chapter of the reference manual which are identical to those mentioned in this data sheet. 4.6.6.2 eim interface pads allocation eim supports16-bit and 8-bit devices operating in addre ss/data separate or multiplexed modes. in some of the modes the eim and the nand flash have shared data bus. table 38 provides eim interface pads allocation in different modes. 4 nf17 is defined only in asymmetric operation mode. nf17 max value is equivalent to max t rhz value that can be used with nfc. t aclk is ?emi_slow_clk? of the system. 5 nf18 is defined only in symmetric operation mode. t dhr (min) is calculated by the following formula: tdl 2 ? (t repd + t dpd ) where t repd is re propogation delay in the chip including i/o pad delay, and t dpd is data propogation delay from i/o pad to extmc including i/o pad delay. nf18 max value is equivalent to max t rhz value that can be used with nfc. t aclk is ?emi_slow_clk? of the system. table 37. eim signal cross reference reference manual eim chapter nomenclature data sheet nomenclature, reference manual external signal s and pin multiplexing chapter, and iomuxc controller chapter nomenclature bclk eim_bclk csx eim_csx we_b eim_rw oe_b eim_oe bey_b eim_ebx adv eim_lba addr eim_a[25:16], eim_da[15:0] addr/m_data eim_dax (addr/data muxed mode) data eim_nfc_d (data bus shared with nand flash) eim_dx (dedicated data bus) wait_b eim_wait
i.mx53xd applications processors for consumer products, rev. 2 54 freescale semiconductor electrical characteristics table 38. eim internal module multiplexing setup non multiplexed address/data mode multiplexed address/data mode 8 bit 16 bit 32 bit 16 bit 32 bit mum = 0, dsz = 111 mum = 0, dsz = 111 mum = 0, dsz = 111 mum = 0, dsz = 001 mum = 0, dsz = 010 mum = 0, dsz = 011 mum = 1, dsz = 001 mum = 1, dsz = 011 a[15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] eim_da [15:0] a[25:16] eim_a [25:16] eim_a [25:16] eim_a [25:16] eim_a [25:16] eim_a [25:16] eim_a [24:16] 1 1 for 32-bit mode, the address range is a[24:0], due to address space allocation in memory map. eim_a [25:16] nandf_d [8:0] 1 d[7:0], eim_eb 0 nandf_d [7:0] 2 ??nandf_d [7:0] 2 2 nandf_d[7:0] multiplexed on alt3 mode of pata_data[7:0] ?nandf_d [7:0] eim_da [7:0] eim_da [7:0] d[15:8], eim_eb 1 ?nandf_d [15:8] 3 ?nandf_d [15:8] 3 3 nandf_d[15:8] multiplexed on alt3 mode of pata_data[15:8] ?nandf_d [15:8] eim_da [15:8] eim_da [15:8] d[23:16] , eim_eb 2 ????eim_d [23:16] eim_d [23:16] ? nandf_d [7:0] d[31:24] , eim_eb 3 ??eim_d [31:24] ?eim_d [31:24] eim_d [31:24] ? nandf_d [15:8]
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 55 4.6.6.3 general eim timing-synchronous mode figure 16 , figure 17 , and table 39 specify the timings related to the eim module. all ei m output control signals may be asserted and deasserted by an inte rnal clock synchronized to the bclk rising edge according to corres ponding assertion/negation control fields. , figure 16. eim outputs timing diagram figure 17. eim inputs timing diagram table 39. eim bus timing parameters 1 id parameter bcd = 0 bcd = 1 bcd = 2 bcd = 3 min max min max min max min max we1 bclk cycle time 2 t2*t3*t4*t we2 bclk low level width 0.4*t 0.8*t 1.2*t 1.6*t we4 address csx_b we_b oe_b bclk bey_b adv_b output data ... we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we15 we16 we17 we3 we2 we1 input data wait_b bclk we19 we18 we21 we20
i.mx53xd applications processors for consumer products, rev. 2 56 freescale semiconductor electrical characteristics we3 bclk high level width 0.4*t 0.8*t 1.2*t 1.6*t we4 clock rise to address valid 3 -0.5*t-1.25 -0.5*t+1.75 -t -1.25 -t+1.75 -1.5*t-1.2 5 -1.5*t +1.75 -2*t-1.25 -2*t+1.75 we5 clock rise to address invalid 0.5*t-1.25 0.5*t+1.75 t- 1.25 t+1.75 1.5*t-1.2 5 1.5*t +1.75 2*t-1.25 2*t+1.75 we6 clock rise to csx_b valid -0.5*t-1.25 -0.5*t+1.75 -t -1.25 -t+1.75 -1.5*t-1.2 5 -1.5*t +1.75 -2*t-1.25 -2*t+1.75 we7 clock rise to csx_b invalid 0.5*t-1.25 0.5*t+1.75 t- 1.25 t+1.75 1.5*t-1.2 5 1.5*t +1.75 2*t-1.25 2*t+1.75 we8 clock rise to we_b valid -0.5*t-1.25 -0.5*t+1.75 -t -1.25 -t+1.75 -1.5*t-1.2 5 -1.5*t +1.75 -2*t-1.25 -2*t+1.75 we9 clock rise to we_b invalid 0.5*t-1.25 0.5*t+1.75 t- 1.25 t+1.75 1.5*t-1.2 5 1.5*t +1.75 2*t-1.25 2*t+1.75 we10 clock rise to oe_b valid -0.5*t-1.25 -0.5*t+1.75 -t -1.25 -t+1.75 -1.5*t-1.2 5 -1.5*t +1.75 -2*t-1.25 -2*t+1.75 we11 clock rise to oe_b invalid 0.5*t-1.25 0.5*t+1.75 t- 1.25 t+1.75 1.5*t-1.2 5 1.5*t +1.75 2*t-1.25 2*t+1.75 we12 clock rise to bey_b valid -0.5*t-1.25 -0.5*t+1.75 -t -1.25 -t+1.75 -1.5*t-1.2 5 -1.5*t +1.75 -2*t-1.25 -2*t+1.75 we13 clock rise to bey_b invalid 0.5*t-1.25 0.5*t+1.75 t- 1.25 t+1.75 1.5*t-1.2 5 1.5*t +1.75 2*t-1.25 2*t+1.75 we14 clock rise to adv_b valid -0.5*t-1.25 -0.5*t+1.75 -t -1.25 -t+1.75 -1.5*t-1.2 5 -1.5*t +1.75 -2*t-1.25 -2*t+1.75 we15 clock rise to adv_b invalid 0.5*t-1.25 0.5*t+1.75 t- 1.25 t+1.75 1.5*t-1.2 5 1.5*t +1.75 2*t-1.25 2*t+1.75 we16 clock rise to output data valid -0.5*t-1.25 -0.5*t+1.75 -t -1.25 -t+1.75 -1.5*t-1.2 5 -1.5*t +1.75 -2*t-1.25 -2*t+1.75 we17 clock rise to output data invalid 0.5*t-1.25 0.5*t+1.75 t- 1.25 t+1.75 1.5*t-1.2 5 1.5*t +1.75 2*t-1.25 2*t+1.75 we18 input data setup time to clock rise 2 ? 4????? we19 input data hold time from clock rise 2 ? 2????? we20 wait_b setup time to clock rise 2 ? 4????? we21 wait_b hold time from clock rise 2 ? 2????? table 39. eim bus timing parameters (continued) 1 id parameter bcd = 0 bcd = 1 bcd = 2 bcd = 3 min max min max min max min max
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 57 4.6.6.4 examples of eim synchronous accesses figure 18 to figure 21 provide few examples of basic eim accesses to external memory devices with the timing parameters mentioned previously fo r specific control parameters settings. figure 18. synchronous memory read access, wsc=1 1 t is the maximal eim logic (axi_clk) cycle time. the maximum allowed axi_clk frequency is 133 mhz, whereas the maximum allowed bclk frequency is 104 mhz. as a result, if bcd = 0, axi_clk must be 104 mhz. if bcd = 1, then 133 mhz is allowed for axi_clk, resulting in a bclk of 66.5 mhz. when t he clock branch to eim is decreased to 104 mhz, other busses are impacted which are clocked from this source. see the ccm chapter of the i.mx53 reference manual for a detailed clock tree description. 2 bclk parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined as 50% as signal value. 3 for signal measurements ?high? is defined as 80% of signal value and ?low? is defined as 20% of signal value. last valid address address v1 d(v1) bclk addr data we_b adv_b oe_b bey_b csx_b we4 we5 we6 we7 we10 we11 we13 we12 we14 we15 we18 we19
i.mx53xd applications processors for consumer products, rev. 2 58 freescale semiconductor electrical characteristics figure 19. synchronous memory, write access, wsc=1, wbea=0, and wadvn=0 figure 20. muxed address/data (a/d) mode, synchr onous write access, wsc=6, adva=0, advn=1, and adh=1 note in 32-bit muxed address/data (a/d) mode the 16 msbs are driven on the data bus. last valid address address v1 d(v1) bclk addr data we_b adv_b oe_b bey_b csx_b we4 we5 we6 we7 we8 we9 we12 we13 we14 we15 we16 we17 last bclk addr/ we_b adv_b oe_b bey_b csx_b address v1 write data valid addr m_data we4 we16 we6 we7 we9 we8 we10 we11 we14 we15 we17 we5
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 59 figure 21. 16-bit muxed a/d mode, synchronous read access, wsc=7, radvn= 1, adh=1, and oea=0 4.6.6.5 general eim timing-asynchronous mode figure 22 through figure 27 , and table 40 help to determine timing paramete rs relative to the chip select (cs) state for asynchronous and dt ack eim accesses with corresponding eim bit fi elds and the timing parameters mentioned above. asynchronous read and write ac cess length in cycles may vary from what is shown in figure 22 through figure 25 as rwsc, oen, and csn is configured differently. refer to i.mx53 xd rm for the eim programming model. last bclk addr/ we_b adv_b oe_b bey_b csx_b address v1 data valid addr m_data we5 we6 we7 we14 we15 we10 we11 we12 we13 we18 we19 we4
i.mx53xd applications processors for consumer products, rev. 2 60 freescale semiconductor electrical characteristics figure 22. asynchronous memory read access (rwsc = 5) figure 23. asynchronous a/d muxed read access (rwsc = 5) last valid address address v1 d(v1) addr/ data[7:0] we_b adv_b oe_b bey_b csx_b next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 int_clk start of access end of access maxdi maxcso maxco m_data addr. v1 d(v1) addr/ we_b adv_b oe_b bey_b csx_b we39 we35a we37 we36 we38 we40a we31 we44 int_clk start of access end of access maxdi maxcso maxco we32a m_data
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 61 figure 24. asynchronous memory write access figure 25. asynchronous a/d muxed write access last valid address address v1 d(v1) addr data we_b adv_b oe_b bey_b csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41 we_b oe_b bey_b csx_b we33 we45 we34 we46 we42 addr. v1 d(v1) addr/ we31 we42 we41 we32a m_data adv_b we39 we40a
i.mx53xd applications processors for consumer products, rev. 2 62 freescale semiconductor electrical characteristics figure 26. dtack read access (dap=0) figure 27. dtack write access (dap=0) last valid address address v1 d(v1) addr data[7:0] we_b adv_b oe_b bey_b csx_b next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 dtack we47 we48 last valid address address v1 d(v1) addr data we_b adv_b oe_b bey_b csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41 dtack we47 we48
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 63 table 40. eim asynchronous timing parameters table relative chip select ref no. parameter determination by synchronous measured parameters 12 min max (if 133 mhz is supported by soc) unit we31 csx_b valid to address valid we4 - we6 - csa 3 ? 3 - csa ns we32 address invalid to csx_b invalid we7 - we5 - csn 4 ?3 - csnns we32 a(mux ed a/d csx_b valid to address invalid t 5 + we4 - we7 + (advn + adva + 1 - csa 3 ) -3 + (advn + adva + 1 - csa) ?ns we33 csx_b valid to we_b valid we8 - we6 + (wea - csa) ? 3 + (wea - csa) ns we34 we_b invalid to csx_b invalid we7 - we9 + (wen - csn) ? 3 - (wen_csn) ns we35 csx_b valid to oe_b valid we10 - we6 + (oea - csa) ? 3 + (oea - csa) ns we35 a (muxe d a/d) csx_b valid to oe_b valid we10 - we6 + (oea + radvn + radva + adh + 1 - csa) -3 + (oea + radvn+radva +adh+1-csa) 3 + (oea + radvn+radva+a dh+1-csa) ns we36 oe_b invalid to csx_b invalid we7 - we11 + (oen - csn) ? 3 - (oen - csn) ns we37 csx_b valid to bey_b valid (read access) we12 - we6 + (rbea - csa) ? 3 + (rbea 6 - csa) ns we38 bey_b invalid to csx_b invalid (read access) we7 - we13 + (rben - csn) ? 3 - (rben 7 - csn) ns we39 csx_b valid to adv_b valid we14 - we6 + (adva - csa) ? 3 + (adva - csa) ns we40 adv_b invalid to csx_b invalid (advl is asserted) we7 - we15 - csn ? 3 - csn ns we40 a (muxe d a/d) csx_b valid to adv_b invalid we14 - we6 + (advn + adva + 1 - csa) -3 + (advn + adva + 1 - csa) 3 + (advn + adva + 1 - csa) ns we41 csx_b valid to output data valid we16 - we6 - wcsa ? 3 - wcsa ns we41 a (muxe d a/d) csx_b valid to output data valid we16 - we6 + (wadvn + wadva + adh + 1 - wcsa) ?3 + (wadvn + wadva + adh + 1 - wcsa) ns we42 output data invalid to csx_b invalid we17 - we7 - csn ? 3 - csn ns
i.mx53xd applications processors for consumer products, rev. 2 64 freescale semiconductor electrical characteristics maxc o output max. delay from internal driving addr/control ffs to chip outputs. 10 ? ? ns maxc so output max. delay from csx internal driving ffs to csx out. 10 ? ? maxdi data maximum delay from chip input data to its internal ff 5?? we43 input data valid to csx_b invalid maxco - maxcso + maxdi maxco - maxcso + maxdi ?ns we44 csx_b invalid to input data invalid 00?ns we45 csx_b valid to bey_b valid (write access) we12 - we6 + (wbea - csa) ? 3 + (wbea - csa) ns we46 bey_b invalid to csx_b invalid (write access) we7 - we13 + (wben - csn) ? -3 + (wben - csn) ns maxd ti dtack maximum delay from chip dtack input to its internal ff + 2 cycles for synchronization ??? we47 dtack active to csx_b invalid maxco - maxcso + maxdti maxco - maxcso + maxdti ?ns we48 csx_b invalid to dtack invalid 00?ns 1 parameters we4... we21 value see column bcd = 0 in table 39 2 all config. parameters (csa,csn,wbea,wben,adva, advn,oen,oea,rbea & rben) are in cycle units. 3 cs assertion. this bit field determines when cs signal is asserted during read/write cycles. 4 cs negation. this bit field determines when cs signal is negated during read/write cycles. 5 t is axi_clk cycle time . 6 be assertion. this bit field determines when be signal is asserted during read cycles. 7 be negation. this bit field determines when be signal is negated during read cycles. table 40. eim asynchronous timing parameters table relative chip select ref no. parameter determination by synchronous measured parameters 12 min max (if 133 mhz is supported by soc) unit
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 65 4.6.7 ddr sdram specific parame ters (ddr2/lvddr2, lpddr2, and ddr3) the ddr2/lvddr2 interface fully co mplies with jesd79-2e ? ddr2 jedec release april, 2008, supporting ddr2-800 and lvddr2-800. the ddr3 interface fully complies with jesd79- 3d ? ddr3 jedec release april 2008 supporting ddr3-800. the lpddr2 interface fully complies with jesd209-2b, supporting lpddr2-800. figure 28 and table 41 show the address and control timi ng parameters for ddr2 and ddr3. figure 28. ddr sdram address and control parameters for ddr2 and ddr3 table 41. ddr sdram timing parameter table 1 2 id parameter symbol sdclk = 400 mhz units min max ddr1 sdram clock high-level width t ch 0.48 0.52 t ck ddr2 sdram clock low-level width t cl 0.48 0.52 t ck sdclk we addr row/ba col/ba cs cas ras ddr1 ddr2 ddr4 ddr4 ddr4 ddr5 ddr5 ddr5 ddr5 ddr6 ddr7 sdclk odt/cke ddr4
i.mx53xd applications processors for consumer products, rev. 2 66 freescale semiconductor electrical characteristics figure 29 and table 42 show the address and contro l timing parameters for lpddr2. figure 29. ddr sdram address and c ontrol timing parameters for lpddr2 ddr4 cs, ras, cas, cke, we, odt setup time t is 0.6 ? ns ddr5 cs, ras, cas, cke, we, odt hold time t ih 0.6 ? ns ddr6 address output setup time t is 0.6 ? ns ddr7 address output hold time t ih 0.6 ? ns 1 all timings are refer to vref level cross point. 2 reference load model is 25 ohm resistor from each of the ddr outputs to vdd_ref. table 42. ddr sdram timing parameter table for lpddr2 1 2 1 all timings are refer to vref level cross point. 2 reference load model is 25 ohm resistor from each of the ddr outputs to vdd_ref. id parameter symbol sdclk = 400 mhz units min max lp1 sdram clock high-level width t ch 0.45 0.55 t ck lp2 sdram clock low-level width t cl 0.45 0.55 t ck lp3 cs, cke setup time t is 0.3 ? ns lp4 cs, cke hold time t ih 0.3 ? ns lp3 ca setup time t is 0.3 ? ns lp4 ca hold time t ih 0.3 ? ns table 41. ddr sdram timing parameter table 1 2 (continued) id parameter symbol sdclk = 400 mhz units min max ck cs cke ca lp4 lp4 lp3 lp4 lp3 lp2 lp3 lp3 lp1
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 67 figure 30 and table 43 show the data write timing parameters. figure 30. ddr sdram data write cycle figure 31 and table 44 show the data read timing parameters. table 43. ddr sdram write cycle 1 2 3 1 all timings are refer to vref level cross point. 2 reference load model is 25 ohm resistor from each of the ddr outputs to vdd_ref. 3 to receive the reported setup and hold values, write calibration should be performed in order to locate the dqs in the middle of dq window. id parameter symbol sdclk = 400 mhz unit min max ddr17 dq and dqm setup time to dqs (differential strobe) t ds 0.285 ? ns ddr18 dq and dqm hold time to dqs (differential strobe) t dh 0.285 ? ns ddr21 dqs latching rising transitions to associated clock edges t dqss -0.25 +0.25 tck ddr22 dqs high level width t dqsh 0.45 0.55 tck ddr23 dqs low level width t dqsl 0.45 0.55 tck sdclk sdclk_b dqs (output) dq (output) dqm (output) data data data data data data data data dm dm dm dm dm dm dm dm ddr17 ddr17 ddr17 ddr17 ddr18 ddr18 ddr18 ddr18 ddr21 ddr23 ddr22
i.mx53xd applications processors for consumer products, rev. 2 68 freescale semiconductor electrical characteristics figure 31. ddr sdram dq vs. dqs and sdclk read cycle 4.7 external peripheral interfaces parameters the following subsections provide inform ation on external peripheral interfaces. 4.7.1 audmux timing parameters the audmux provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (ssis) an d external serial interfaces (audio and voice codecs). the ac timing of audmux external pins is governed by the ssi m odule. for more informati on, see the respective ssi electrical specifications f ound within this document. 4.7.2 cspi and ecspi timing parameters this section describes the timing parameters of the cspi and ecspi blocks. th e cspi and ecspi have separate timing parameters for master and slave mo des. the nomenclature used with the cspi / ecspi modules and the respective routing of these signals is shown in table 45 . table 44. ddr sdram read cycle 1 1 to receive the reported setup and hold values, read calibration sh ould be performed in order to locate the dqs in the middle of dq window. id parameter symbol sdclk = 400 mhz unit min max ddr26 minimum required dq valid window width except from lpddr2 ?0.6 ?ns ddr26(lp ddr2) minimum required dq valid window width for lpddr2 ?0.425 ?ns ddr27 dqs to dq valid data ? 0.275 0.475 ns sdclk sdclk_b dqs (input) dq (input) data data data data data data data data ddr26 ddr27
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 69 4.7.2.1 cspi master mode timing figure 32 depicts the timing of cspi in master mode. table 46 lists the cspi master mode timing characteristics. figure 32. cspi/ecspi master mode timing diagram table 45. cspi nomenclature and routing block instance i/o access ecspi-1 gpio, kpp, disp0_dat, csi0 _dat and eim_d through iomuxc ecspi-2 disp0_dat, csi0_dat and eim through iomuxc cspi disp0_dat, eim_a/d, sd 1 and sd2 through iomuxc table 46. cspi master mode timing parameters id parameter symbol min max unit cs1 sclk cycle time t clk 60 ? ns cs2 sclk high or low time t sw 26 ? ns cs3 sclk rise or fall 1 t rise/fall ??ns cs4 ssx pulse width t cslh 26 ? ns cs5 ssx lead time (slave select setup time) t scs 26 ? ns cs6 ssx lag time (ss hold time) t hcs 26 ? ns cs7 mosi propagation delay (c load =20pf) t pdmosi ?1 21 ns cs8 miso setup time t smiso 5?ns cs1 cs7 cs2 cs2 cs4 cs6 cs5 cs8 cs9 sclk ssx mosi miso rdy cs10 cs3 cs3
i.mx53xd applications processors for consumer products, rev. 2 70 freescale semiconductor electrical characteristics 4.7.2.2 cspi slave mode timing figure 33 depicts the timing of cspi in slave mode. timing characteristics we re not available at the time of publication. figure 33. cspi/ecspi slave mode timing diagram 4.7.2.3 ecspi master mode timing figure 32 depicts the timing of ecspi in master mode. table 47 lists the ecspi master mode timing characteristics. cs9 miso hold time t hmiso 5?ns cs10 rdy to ssx time 2 t sdry 5?ns 1 see specific i/o ac parameters section 4.5, ?i/o ac parameters ? 2 spi_rdy is sampled internally by ipg_clk and is asynchronous to all other cspi signals. table 47. ecspi master mode timing parameters id parameter symbol min max unit cs1 sclk cycle time?read sclk cycle time?write t clk 30 15 ?ns cs2 sclk high or low time?read sclk high or low time?write t sw 14 7 ?ns cs3 sclk rise or fall 1 t rise/fall ??ns cs4 ssx pulse width t cslh half sclk period ? ns cs5 ssx lead time (cs setup time) t scs 5?ns cs6 ssx lag time (cs hold time) t hcs 5?ns cs7 mosi propagation delay (c load =20pf) t pdmosi -0.5 2.5 ns cs8 miso setup time t smiso 8.5 ? ns table 46. cspi master mode timing parameters (continued) id parameter symbol min max unit cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 sclk ssx miso mosi
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 71 4.7.2.4 ecspi slave mode timing figure 33 depicts the timing of ecspi in slave mode. table 48 lists the ecspi slave mode timing characteristics. 4.7.3 enhanced serial audio inte rface (esai) timing parameters the esai consists of independent transmitter and receive r sections, each secti on with its own clock generator. table 49 shows the interface timing values. the number field in the table refe rs to timing signals found in figure 34 and figure 35 . cs9 miso hold time t hmiso 0?ns cs10 rdy to ssx time 2 t sdry 5?ns 1 see specific i/o ac parameters section 4.5, ?i/o ac parameters ? 2 spi_rdy is sampled internally by ipg_clk and is asynchronous to all other cspi signals. table 48. ecspi slave mo de timing parameters id parameter symbol min max unit cs1 sclk cycle time?read sclk cycle time?write t clk 15 40 ?ns cs2 sclk high or low time?read sclk high or low time?write t sw 7 20 ?ns cs4 ssx pulse width t cslh half sclk period ? ns cs5 ssx lead time (cs setup time) t scs 5?ns cs6 ssx lag time (cs hold time) t hcs 5?ns cs7 mosi setup time t smosi 4?ns cs8 mosi hold time t hmosi 4?ns cs9 miso propagation delay (c load =20pf) t pdmiso 417ns table 49. enhanced serial audio interface (esai) timing no. characteristics 1 ? 2,3 symbol expression 3 min max condition 4 unit 62 clock cycle 5 t ssicc 4 t c 4 t c 30.0 30.0 ? ? i ck i ck ns 63 clock high period ? for internal clock ?2 t c ? 9.0 6 ? ? ns ? for external clock ? 2 t c 15 ? ? table 47. ecspi master mode timing parameters (continued) id parameter symbol min max unit
i.mx53xd applications processors for consumer products, rev. 2 72 freescale semiconductor electrical characteristics 64 clock low period ? for internal clock ?2 t c ? 9.0 6 ? ? ns ? for external clock ? 2 t c 15 ? ? 65 sckr rising edge to fsr out (bl) high ? ? ? ? ? ? 17.0 7.0 x ck i ck a ns 66 sckr rising edge to fsr out (bl) low ? ? ? ? ? ? 17.0 7.0 x ck i ck a ns 67 sckr rising edge to fsr out (wr) high 6 ? ? ? ? ? ? 19.0 9.0 x ck i ck a ns 68 sckr rising edge to fsr out (wr) low 6 ? ? ? ? ? ? 19.0 9.0 x ck i ck a ns 69 sckr rising edge to fsr out (wl) high ? ? ? ? ? ? 16.0 6.0 x ck i ck a ns 70 sckr rising edge to fsr out (wl) low ? ? ? ? ? ? 17.0 7.0 x ck i ck a ns 71 data in setup time before sckr (sck in synchronous mode) falling edge ? ? ? ? 12.0 19.0 ? ? x ck i ck ns 72 data in hold time after sckr falling edge ? ? ? ? 3.5 9.0 ? ? x ck i ck ns 73 fsr input (bl, wr) high before sckr falling edge 6 ? ? ? ? 2.0 12.0 ? ? x ck i ck a ns 74 fsr input (wl) high before sckr falling edge ? ? ? ? 2.0 12.0 ? ? x ck i ck a ns 75 fsr input hold time after sckr falling edge ? ? ? ? 2.5 8.5 ? ? x ck i ck a ns 78 sckt rising edge to fst out (bl) high ? ? ? ? ? ? 18.0 8.0 x ck i ck ns 79 sckt rising edge to fst out (bl) low ? ? ? ? ? ? 20.0 10.0 x ck i ck ns 80 sckt rising edge to fst out (wr) high 6 ? ? ? ? ? ? 20.0 10.0 x ck i ck ns 81 sckt rising edge to fst out (wr) low 6 ? ? ? ? ? ? 22.0 12.0 x ck i ck ns 82 sckt rising edge to fst out (wl) high ? ? ? ? ? ? 19.0 9.0 x ck i ck ns 83 sckt rising edge to fst out (wl) low ? ? ? ? ? ? 20.0 10.0 x ck i ck ns 84 sckt rising edge to data out enable from high impedance ? ? ? ? ? ? 22.0 17.0 x ck i ck ns table 49. enhanced serial audio interface (esai) timing (continued) no. characteristics 1 ? 2,3 symbol expression 3 min max condition 4 unit
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 73 86 sckt rising edge to data out valid ? ? ? ? ? ? 18.0 13.0 x ck i ck ns 87 sckt rising edge to data out high impedance 77 ? ? ? ? ? ? 21.0 16.0 x ck i ck ns 89 fst input (bl, wr) setup ti me before sckt falling edge 6 ? ? ? ? 2.0 18.0 ? ? x ck i ck ns 90 fst input (wl) setup time before sckt falling edge ? ? ? ? 2.0 18.0 ? ? x ck i ck ns 91 fst input hold time after sckt falling edge ? ? ? ? 4.0 5.0 ? ? x ck i ck ns 95 hckr/hckt clock cycle ? 2 x t c 15 ? ? ns 96 hckt input rising edge to sckt output ? ? ? 18.0 ? ns 97 hckr input rising edge to sckr output ? ? ? 18.0 ? ns 1 vcore_vdd= 1.00 +- 0.10v tj = -40c to 125c cl=50pf 2 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that sckt and sckr are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that sckt and sckr are the same clock) 3 bl = bit length wl = word length wr = word length relative 4 sckt(sckt pin) = transmit clock sckr(sckr pin) = receive clock fst(fst pin) = transmit frame sync fsr(fsr pin) = receive frame sync hckt(hckt pin) = transmit high frequency clock hckr(hckr pin) = receive high frequency clock 5 for the internal clock, the external clock cycle is defined by icyc and the esai control register. 6 the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the second-to-last bit clock of the first word in the frame. 7 periodically sampled and not 100% tested. table 49. enhanced serial audio interface (esai) timing (continued) no. characteristics 1 ? 2,3 symbol expression 3 min max condition 4 unit
i.mx53xd applications processors for consumer products, rev. 2 74 freescale semiconductor electrical characteristics figure 34. esai transmitter timing sckt (input/output) fst (bit) out fst (word) out data out fst (bit) in fst (word) in 62 64 78 79 82 83 87 86 86 84 91 89 90 91 63 last bit first bit
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 75 figure 35. esai receiver timing sckr (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in 62 64 65 69 70 72 71 75 73 74 75 63 66 first bit last bit
i.mx53xd applications processors for consumer products, rev. 2 76 freescale semiconductor electrical characteristics 4.7.4 enhanced secured digital host controller(esdhcv2/v3) ac timing this section describes the elec trical information of the es dhcv2/v3, which includes sd/emmc4.3 (single data rate) timing and emmc4.4 (dual date rate) timing. 4.7.4.1 sd/emmc4.3 (single data rate) ac timing figure 36 depicts the timing of sd/emmc4.3, and table 50 lists the sd/emmc4.3 timing characteristics. figure 36. sd/emmc4.3 timing table 50. sd/emmc4.3 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 0 400 khz clock frequency (sd/sdio full speed/high speed) f pp 2 0 25/50 mhz clock frequency (mmc full speed/high speed) f pp 3 0 20/52 mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns esdhc output/card inputs cmd, dat (reference to clk) sd6 esdhc output delay t od ?5 5 ns esdhc input/card outputs cm d, dat (reference to clk) sd1 sd3 sd5 sd4 sd7 cmd output from esdhcv2 to card dat1 ...... dat7 dat0 cmd input from card to esdhcv2 dat1 ...... dat7 dat0 sck sd2 sd8 sd6
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 77 4.7.4.2 emmc4.4 (dual data rate) esdhcv3 ac timing figure 37 depicts the timing of emmc4.4. table 51 lists the emmc4.4 timing ch aracteristics. be aware that only data is sampled on both edges of the clock (not applicable to cmd). figure 37. emmc4.4 timing sd7 esdhc input setup time t isu 2.5 ? ns sd8 esdhc input hold time 4 t ih 2.5 ? ns 1 in low speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 2 in normal (full) speed mode for sd/sdio card, clock frequency can be any value between 0 ? 25 mhz. in high-speed mode, clock frequency can be any value between 0 ? 50 mhz. 3 in normal (full) speed mode for mmc card, clock frequency can be any value between 0 ? 20 mhz. in high-speed mode, clock frequency can be any value between 0 ? 52 mhz. 4 to satisfy hold timing, the delay difference between cl ock input and cmd/data input must not exceed 2 ns. table 51. emmc4.4 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (mmc full speed/high speed) f pp 052mhz esdhc output / card inputs cm d, dat (reference to clk) sd2 esdhc output delay t od ?5 5 ns esdhc input / card outputs cmd, dat (reference to clk) table 50. sd/emmc4.3 interface timing specification (continued) id parameter symbols min max unit sd1 sd2 sd3 output from esdhcv3 to card dat1 ...... dat7 dat0 input from card to esdhcv3 dat1 ...... dat7 dat0 sck sd4 sd2 ...... ......
i.mx53xd applications processors for consumer products, rev. 2 78 freescale semiconductor electrical characteristics 4.7.5 fec ac timing parameters this section describes the el ectrical information of th e fast ethernet controll er (fec) module. the fec is designed to support both 10 and 100 mbps ethernet /ieee 802.3 networks. an external transceiver interface and transceiver function are required to comp lete the interface to the media. the fec supports the 10/100 mbps mii (18 pins in total) and the 10 mbps (only 7-wire interface, which uses 7 of the mii pins), for connection to an external ethernet transceiver. for the pin li st of mii and 7-wi re, see the i.mx53 reference manual. this section describes the ac timi ng specifications of the fec. the mii signals are compatible with transceivers operating at a voltage of 3.3 v. 4.7.5.1 mii receive signal timing the mii receive signal timing involves th e fec_rxd[3:0], fec_rx_ dv, fec_rx_er, and fec_rx_clk signals. the receiver functions correct ly up to a fec_rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency require ment but the processor clock frequency must exceed twice the fec_rx_clk frequency. table 52 lists the mii receive channel signal timing parameters and figure 38 shows mii receive signal timings. . sd3 esdhc input setup time t isu 2.5 ? ns sd4 esdhc input hold time t ih 2.5 ? ns table 52. mii receive signal timing no. characteristics 1 2 1 fec_rx_dv, fec_rx_clk, and fec_rxd0 have same timing in 10 mbps 7-wire interface mode. 2 test conditions: 25pf on each output signal. min max unit m1 fec_rxd[3:0], fec_rx_dv, fec_rx_er to fec_rx_clk setup 5 ? ns m2 fec_rx_clk to fec_rxd[3:0], fec_rx_dv, fec_rx_er hold 5 ? ns m3 fec_rx_clk pulse width high 35% 65% fec_rx_clk period m4 fec_rx_clk pulse width low 35% 65% fec_rx_clk period table 51. emmc4.4 interface timing specification (continued) id parameter symbols min max unit
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 79 figure 38. mii receive signal timing diagram 4.7.5.2 mii transmit signal timing the mii transmit signal timing affects the fec_txd[3:0], fec_tx_en, fec_tx_er, and fec_tx_clk signals. the transmitter functions co rrectly up to a fec_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency require ment. in addition, the processor clock frequency must exceed twice the fec_tx_clk frequency. table 53 lists mii transmit channel timing parameters. figure 39 shows mii transmit signal timing diagram for the values listed in table 53 . table 53. mii transmit signal timing num characteristic 1 2 1 fec_tx_en, fec_tx_clk, and fec_txd0 have the same timing in 10 mbps 7-wire interface mode. 2 test conditions: 25pf on each output signal. min max unit m5 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er invalid 5 ? ns m6 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er valid ? 20 ns m7 fec_tx_clk pulse width high 35% 65% fec_tx_clk period m8 fec_tx_clk pulse width low 35% 65% fec_tx_clk period fec_rx_clk (input) fec_rxd[3:0] (inputs) fec_rx_dv fec_rx_er m3 m4 m1 m2
i.mx53xd applications processors for consumer products, rev. 2 80 freescale semiconductor electrical characteristics . figure 39. mii transmit signal timing diagram 4.7.5.3 mii async inputs signal timing (fec_crs and fec_col) table 54 lists mii asynchronous inpu ts signal timing information. figure 40 shows mii asynchronous input timings listed in table 54 . . figure 40. mii async inputs timing diagram 4.7.5.4 mii serial management cha nnel timing (fec_m dio and fec_mdc) table 55 lists mii serial mana gement channel timings. figure 41 shows mii serial management channel timings listed in table 55 . the mdc frequency should be equal to or less than 2.5 mhz to be compliant with the ieee 802.3 mii specification. however, the fec can function correctly with a maximum mdc frequency of 15 mhz. table 54. mii async inputs signal timing num characteristic 1 1 test conditions: 25pf on each output signal. min max unit m9 2 2 fec_col has the same timing in 10 mbit 7-wire interface mode. fec_crs to fec_col minimum pulse width 1.5 ? fec_tx_clk period table 55. mii transmit signal timing id characteristics 1 min max unit m10 fec_mdc falling edge to fec_mdio output invalid (minimum propagation delay) 0 ? ns m11 fec_mdc falling edge to fec_mdio output valid (max propagation delay) ? 5 ns m12 fec_mdio (input) to fec_mdc rising edge setup 18 ? ns fec_tx_clk (input) fec_txd[3:0] (outputs) fec_tx_en fec_tx_er m7 m8 m5 m6 fec_crs, fec_col m9
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 81 figure 41. mii serial management channel timing diagram 4.7.5.5 rmii mode timing in rmii mode, fec_tx_clk is used as the ref_cl k which is a 50 mhz 50 ppm continuous reference clock. fec_rx_dv is used as the crs_dv in rmii , and other signals under rmii mode include fec_tx_en, fec_txd[1:0], fec_rxd [1:0] and optional fec_rx_er. the rmii mode timings are shown in table 56 and figure 42 . m13 fec_mdio (input) to fec_mdc rising edge hold 0 ? ns m14 fec_mdc pulse width high 40 % 60% fec_mdc period m15 fec_mdc pulse width low 40 % 60% fec_mdc period 1 test conditions: 25pf on each output signal. table 56. rmii signal timing no. characteristics 1 min max unit m16 ref_clk(fec_tx_clk) pulse width high 35% 65% ref_clk period m17 ref_clk(fec_tx_clk) pulse width low 35% 65% ref_clk period m18 ref_clk to fec_txd[1:0], fec_tx_en invalid 2 ? ns m19 ref_clk to fec_txd[1:0], fec_tx_en valid ? 16 ns table 55. mii transmit signal timing (continued) id characteristics 1 min max unit fec_mdc (output) fec_mdio (output) m14 m15 m10 m11 m12 m13 fec_mdio (input)
i.mx53xd applications processors for consumer products, rev. 2 82 freescale semiconductor electrical characteristics figure 42. rmii mode signal timing diagram 4.7.6 flexible controller area ne twork (flexcan) ac electrical specifications the electrical charac teristics are related to th e can transceiver external to i.mx53xd such as mc33902 from freescale.the i.mx53xd has two can modules av ailable for systems design. tx and rx ports for both modules are multiplexed with other i/o pi ns. see the iomuxc chapter of the i.mx53 reference manual to see which pins expose tx and rx pins; these ports are named txcan and rxcan, respectively. m20 fec_rxd[1:0], crs_dv(fe c_rx_dv), fec_rx_er to ref_clk setup 4?ns m21 ref_clk to fec_rxd[1:0], fec_rx_dv, fec_rx_er hold 2?ns 1 test conditions: 25pf on each output signal. table 56. rmii signal timing (continued) no. characteristics 1 min max unit ref_clk (input) fec_tx_en m16 m17 m18 m19 m20 m21 fec_rxd[1:0] fec_txd[1:0] (output) fec_rx_er crs_dv (input)
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 83 4.7.7 i 2 c module timing parameters this section describes the timing parameters of the i 2 c module. figure 43 depicts the timing of i 2 c module, and table 57 lists the i 2 c module timing characteristics. figure 43. i 2 c bus timing table 57. i 2 c module timing parameters id parameter standard mode supply voltage = 1.65 v?1.95 v, 2.7 v?3.3 v fast mode supply voltage = 2.7 v?3.3 v unit min max min max ic1 i2clk cycle time 10 ? 2.5 ? s ic2 hold time (repeated) start condition 4.0 ? 0.6 ? s ic3 set-up time for stop condition 4.0 ? 0.6 ? s ic4 data hold time 0 1 1 a device must internally provide a hold time of at least 300 ns for i2dat signal in order to bridge the undefined region of the falling edge of i2clk. 3.45 2 2 the maximum hold time has only to be met if the device does not stretch the low period (id no ic5) of the i2clk signal. 0 1 0.9 2 s ic5 high period of i2clk clock 4.0 ? 0.6 ? s ic6 low period of the i2clk clock 4.7 ? 1.3 ? s ic7 set-up time for a repeated start condition 4.7 ? 0.6 ? s ic8 data set-up time 250 ? 100 3 3 a fast-mode i2c-bus device can be used in a standard-mode i2 c-bus system, but the requirement of set-up time (id no ic7) of 250 ns must be met. this automatically is the case if t he device does not stretch the low period of the i2clk signal. if such a device does stretch the low period of the i2clk signal, it must output the next data bit to the i2dat line max_rise_time (ic9) + data_setup_time (ic7) = 1000 + 250 = 1250 ns (according to the standard -mode i2c-bus specification) before the i2clk line is released. ?ns ic9 bus free time between a stop and start condition 4.7 ? 1.3 ? s ic10 rise time of both i2dat and i2clk signals ? 1000 20 + 0.1c b 4 4 c b = total capacitance of one bus line in pf. 300 ns ic11 fall time of both i2dat and i2clk signals ? 300 20 + 0.1c b 4 300 ns ic12 capacitive load for each bus line (c b ) ? 400 ? 400 pf ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start i2dat i2clk ic1
i.mx53xd applications processors for consumer products, rev. 2 84 freescale semiconductor electrical characteristics 4.7.8 image processing unit (ipu) module parameters the purpose of the ipu is to provide comprehensive su pport for the flow of data from an image sensor and/or to a display device. this support covers all as pects of these activities: ? connectivity to relevant devices ? cameras, displays, graphics accel erators, and tv encoders. ? related image processing and manipulation: sensor image signa l processing, disp lay processing, image conversions, and other related functions. ? synchronization and control cap abilities, such as avoida nce of tearing artifacts. 4.7.8.1 ipu sensor interface signal mapping the ipu supports a number of sensor input formats. table 58 defines the mapping of the sensor interface pins used for various supported interface formats. table 58. camera input signal cross reference, format and bits per cycle signal name 1 1 csix stands for csi1 or csi2 rgb565 8 bits 2 cycles rgb565 2 8 bits 3 cycles rgb666 3 8 bits 3 cycles rgb888 8 bits 3 cycles ycbcr 8 bits 2 cycles rgb565 4 16 bits 2 cycles ycbcr 5 16 bits 1 cycle ycbcr 6 16 bits 1 cycle ycbcr 7 20 bits 1 cycle csix_dat0 ? ? ? ? ? ? ? 0 c[0] csix_dat1 ? ? ? ? ? ? ? 0 c[1] csix_dat2 ? ? ? ? ? ? ? c[0] c[2] csix_dat3 ? ? ? ? ? ? ? c[1] c[3] csix_dat4 ? ? ? ? ? b[0] c[0] c[2] c[4] csix_dat5 ? ? ? ? ? b[1] c[1] c[3] c[5] csix_dat6 ? ? ? ? ? b[2] c[2] c[4] c[6] csix_dat7 ? ? ? ? ? b[3] c[3] c[5] c[7] csix_dat8 ? ? ? ? ? b[4] c[4] c[6] c[8] csix_dat9 ? ? ? ? ? g[0] c[5] c[7] c[9] csix_dat10 ? ? ? ? ? g[1] c[6] 0 y[0] csix_dat11 ? ? ? ? ? g[2] c[7] 0 y[1] csix_dat12 b[0], g[3] r[2],g[4],b[2] r/ g/b[4] r/g/b[0] y/c[0] g[3] y[0] y[0] y[2] csix_dat13 b[1], g[4] r[3],g[5],b[3] r/ g/b[5] r/g/b[1] y/c[1] g[4] y[1] y[1] y[3] csix_dat14 b[2], g[5] r[4],g[0],b[4] r/ g/b[0] r/g/b[2] y/c[2] g[5] y[2] y[2] y[4] csix_dat15 b[3], r[0] r[0],g[1],b[0] r/ g/b[1] r/g/b[3] y/c[3] r[0] y[3] y[3] y[5] csix_dat16 b[4], r[1] r[1],g[2],b[1] r/ g/b[2] r/g/b[4] y/c[4] r[1] y[4] y[4] y[6] csix_dat17 g[0], r[2] r[2],g[3],b[2] r/ g/b[3] r/g/b[5] y/c[5] r[2] y[5] y[5] y[7] csix_dat18 g[1], r[3] r[3],g[4],b[3] r/ g/b[4] r/g/b[6] y/c[6] r[3] y[6] y[6] y[8] csix_dat19 g[2], r[4] r[4],g[5],b[4] r/ g/b[5] r/g/b[7] y/c[7] r[4] y[7] y[7] y[9]
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 85 4.7.8.2 sensor interface timings there are three camera timi ng modes supported by the ipu. 4.7.8.2.1 bt.656 and bt.1120 video mode smart camera sensors, which incl ude imaging processing, usually suppor t video mode transfer. they use an embedded timing syntax to replace the sen sb_vsync and sensb_hsync signals. the timing syntax is defined by the bt.656/bt.1120 standards. this operation mode follows the recommendations of itu bt.656/ itu bt.1120 specifications. the only control signal used is sensb_pix_clk . start-of-frame and active-line signals are embedded in the data stream. an active line starts with a sav code and ends with a eav c ode. in some cases, digital blanking is inserted in between eav and sav code. the csi d ecodes and filters out the ti ming-coding from the data stream, thus recovering sensb_vsy nc and sensb_hsync signals for internal use. on bt.656 one component per cycle is received over the sensb_da ta bus. on bt.1120 two co mponents per cycle are received over the sensb_data bus. 4.7.8.2.2 gated clock mode the sensb_vsync, sensb_hsync, and sensb_pix_clk signals are used in this mode. see figure 44 . figure 44. gated clock mode timing diagram a frame starts with a rising edge on sensb_vsync (all the timings corr espond to straight polarity of the corresponding signals). then sensb_ hsync goes to high and hold for the entire line. pixel clock is valid as long as sensb_hsync is high. data is latched at the rising edge of the valid pixel clocks. 2 the msb bits are duplicated on lsb bits implementing color extension 3 the two msb bits are duplicated on lsb bits implementing color extension 4 rgb 16 bits ? supported in two ways: (1) as a ?generic data ? input ? with no on-the-fly processing; (2) with on-the-fly processing, but only under some rest rictions on the control protocol. 5 ycbcr 16 bits - supported as a ?generic-d ata? input ? with no on-the-fly processing. 6 ycbcr 16 bits - supported as a sub-case of the ycbcr, 20 bits, under the same conditions (bt.1120 protocol). 7 ycbcr, 20 bits, supported only within the bt.11 20 protocol (syncs embedded within the data stream). sensb_vsync sensb_hsync sensb_pix_clk sensb_data[19:0] invalid 1st byte n+1th frame invalid 1st byte nth frame active line start of frame
i.mx53xd applications processors for consumer products, rev. 2 86 freescale semiconductor electrical characteristics sensb_hsync goes to low at the end of line. pixel clocks then become invalid and the csi stops receiving data from the stream. fo r next line the sensb_hsync timi ng repeats. for next frame the sensb_vsync timing repeats. 4.7.8.2.3 non-gated clock mode the timing is the same as the gated-clock mode (described in section 4.7.8.2.2, ?gated clock mode ,? ) except for the sensb_hsync signal , which is not used (see figure 45 ). all incoming pixel clocks are valid and cause data to be latched into the input fifo. the sensb_pix_clk si gnal is inactive (states low) until valid data is going to be transmitted over the bus. figure 45. non-gated clock mode timing diagram the timing described in figure 45 is that of a typical sensor. some other sensors may have a slightly different timing. the csi can be programmed to support rising/fal ling-edge triggere d sensb_vsync; active-high/low sensb_hsync ; and rising/falling-edge triggered sensb_pix_clk. 4.7.8.3 electrical characteristics figure 46 depicts the sensor interface timing. sensb_mclk signal described here is not generated by the ipu. table 59 lists the sensor interface timing characteristics. figure 46. sensor interface timing diagram sensb_vsync sensb_pix_clk sensb_data[19:0] invalid 1st byte n+1th frame invalid 1st byte nth frame start of frame ip3 sensb_data, sensb_vsync, ip2 1/ip1 sensb_pix_clk (sensor output) sensb_hsync
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 87 4.7.8.4 ipu display interface signal mapping the ipu supports a number of display output video formats. table 60 defines the mapping of the display interface pins used during various supported video interface formats. table 59. sensor interface timing characteristics id parameter symbol min max unit ip1 sensor output (pixel) clock frequency fpck 0.01 180 mhz ip2 data and control setup time tsu 2 ? ns ip3 data and control holdup time thd 1 ? ns
i.mx53xd applications processors for consumer products, rev. 2 88 freescale semiconductor electrical characteristics table 60. video signal cross-reference i.mx53xd lcd comment 1 port name (x=0, 1) rgb, signal name (general) rgb/tv signal allocation (example) smart 16-bit rgb 18-bit rgb 24 bit rgb 8-bit ycrcb 2 16-bit ycrcb 20-bit ycrcb signal name dispx_dat0 dat[0] b[0] b[0] b[0] y/c[0] c[0] c[0] dat[0] the restrictions are as follows: a) there are maximal three continuous groups of bits that could be independently mapped to the external bus. groups should not be overlapped. b) the bit order is expressed in each of the bit groups, for example b[0] = least significant blue pixel bit dispx_dat1 dat[1] b[1] b[1] b[1] y/c[1] c[1] c[1] dat[1] dispx_dat2 dat[2] b[2] b[2] b[2] y/c[2] c[2] c[2] dat[2] dispx_dat3 dat[3] b[3] b[3] b[3] y/c[3] c[3] c[3] dat[3] dispx_dat4 dat[4] b[4] b[4] b[4] y/c[4] c[4] c[4] dat[4] dispx_dat5 dat[5] g[0] b[5] b [5] y/c[5] c[5] c[5] dat[5] dispx_dat6 dat[6] g[1] g[0] b[6] y/c[6] c[6] c[6] dat[6] dispx_dat7 dat[7] g[2] g[1] b[7] y/c[7] c[7] c[7] dat[7] dispx_dat8 dat[8] g[3] g[2] g[0] ? y[0] c[8] dat[8] dispx_dat9 dat[9] g[4] g[3] g[1] ? y[1] c[9] dat[9] dispx_dat10 dat[10] g[5] g[4] g[2] ? y[2] y[0] dat[10] dispx_dat11 dat[11] r[0] g[5] g[3] ? y[3] y[1] dat[11] dispx_dat12 dat[12] r[1] r[0] g[4] ? y[4] y[2] dat[12] dispx_dat13 dat[13] r[2] r[1] g[5] ? y[5] y[3] dat[13] dispx_dat14 dat[14] r[3] r[2] g[6] ? y[6] y[4] dat[14] dispx_dat15 dat[15] r[4] r[3] g[7] ? y[7] y[5] dat[15] dispx_dat16 dat[16] ? r[4] r[0] ? ? y[6] ? dispx_dat17 dat[17] ? r[5] r[1] ? ? y[7] ? dispx_dat18 dat[18] ? ? r[2] ? ? y[8] ? dispx_dat19 dat[19] ? ? r[3] ? ? y[9] ? dispx_dat20 dat[20] ? ? r[4] ? ? ? ? dispx_dat21 dat[21] ? ? r[5] ? ? ? ?
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 89 dispx_dat22 dat[22] ? ? r[6] ? ? ? ? ? dispx_dat23 dat[23] ? ? r[7] ? ? ? ? ? dix_disp_clk pixclk ? ? dix_pin1 ? vsync_in may be required for anti-tearing dix_pin2 hsync ? ? dix_pin3 vsync ? vsync out dix_pin4 ? ? additional frame/row synchronous signals with programmable timing dix_pin5 ? ? dix_pin6 ? ? dix_pin7 ? ? dix_pin8 ? ? dix_d0_cs ? cs0 ? dix_d1_cs ? cs1 alternate mode of pwm output for contrast or brightness control dix_pin11 ? wr ? dix_pin12 ? rd ? dix_pin13 ? rs1 register select signal dix_pin14 ? rs2 optional rs2 dix_pin15 drdy/dv drdy data va lidation/blank, data enable dix_pin16 ? ? additional data synchronous signals with programmable features/timing dix_pin17 q ? 1 signal mapping (both data and control/synchronization) is flexible. the table provides examples. 2 this mode works in compliance with recommendation itu-r bt.656 . the timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. only vi deo data is supported, transmission of non-video related data during blanking intervals is not supported. table 60. video signal cross-reference (continued) i.mx53xd lcd comment 1 port name (x=0, 1) rgb, signal name (general) rgb/tv signal allocation (example) smart 16-bit rgb 18-bit rgb 24 bit rgb 8-bit ycrcb 2 16-bit ycrcb 20-bit ycrcb signal name
i.mx53xd applications processors for consumer products, rev. 2 90 freescale semiconductor electrical characteristics note table 60 provides information for both th e disp0 and disp1 ports. however, disp1 port has reduced pinout depe nding on iomuxc configuration and therefore may not support all the ab ove configurations. see the iomuxc table for details. 4.7.8.5 ipu display interface timing the ipu display interface supports two kinds of display accesses: synchronous and asynchronous. there are two groups of external interface pins to prov ide synchronous and asynchr onous controls accordantly. 4.7.8.5.1 synchronous controls the synchronous control changes its va lue as a function of a system or of an external clock. this control has a permanent period and a permanent wave form. there are special physical outputs to provide synchronous controls: ? the ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display (component, pixel) clock for a display. ? the ipp_pin_1? ipp_pin_7 are general purpose synchr onous pins, that can be used to provide hsync, vsync, drdy or any else independent signal to a display. the ipu has a system of internal binding counters fo r internal events (such as hsync/vsycn and so on) calculation. the internal ev ent (local start point) is synchronized with internal di_clk. a suitable control starts from the local start point with predefined up and down values to calculate control?s changing points with half di_clk resolution. a full description of the counters system can be found in the ipu chapter of the i.mx53 reference manual. 4.7.8.5.2 asynchronous controls the asynchronous control is a data-orient ed signal that changes its value wi th an output data according to additional internal flags coming with the data. there are special physical outputs to pr ovide asynchronous controls, as follows: ? the ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays. ? the ipp_pin_11? ipp_pin_17 are genera l purpose asynchronous pins, that can be used to provide wr. rd, rs or any other data oriented signal to display. note the ipu has independent signal ge nerators for asynchronous signals toggling. when a di decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. the signals generators calculate predefined up and down valu es to change pins states with half di_clk resolution.
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 91 4.7.8.6 synchronous interfaces to sta ndard active matrix tft lcd panels 4.7.8.6.1 ipu display operating signals the ipu uses four control signals and data to operate a standard synchronous interface: ? ipp_disp_clk?clock to display ? hsync?horizontal synchronization ? vsync?vertical synchronization ? drdy?active data all synchronous display controls are generated on the b ase of an internally generated ?local start point?. the synchronous display controls ca n be placed on time axis with di?s offset, up and down parameters. the display access can be whole numbe r of di clock (tdiclk) only. the ipp_data can not be moved relative to the local start point. the data bus of the synchronous interface is output direction only. 4.7.8.6.2 lcd interfac e functional description figure 47 depicts the lcd interface timi ng for a generic active matrix color tft panel. in this figure signals are shown with negative polarity. the sequence of events fo r active matrix interface timing is: ? di_clk internal di clock, used for calculation of other controls. ? ipp_disp_clk latches data into the panel on its ne gative edge (when positive polarity is selected). in active mode, ipp_disp _clk runs continuously. ? hsync causes the panel to start a new line . (usually ipp_pin_2 is used as hsync.) ? vsync causes the panel to start a new frame. it always encompasses at least one hsync pulse. (usually ipp_pin_3 is used as vsync.) ? drdy acts like an output enable signal to the cr t display. this output enables the data to be shifted onto the display. when disabled, the data is invalid and the trace is off. (drdy can be used either synchronous or asynchronous generic purpose pin as well.) figure 47. interface timing diagram for tft (active matrix) panels 123 m m?1 hsync vsync hsync line 1 line 2 line 3 line 4 line n-1 line n drdy ipp_disp_clk ipp_data
i.mx53xd applications processors for consumer products, rev. 2 92 freescale semiconductor electrical characteristics 4.7.8.6.3 tft panel sync pulse timing diagrams figure 48 depicts the horizontal timing (ti ming of one line), including bot h the horizontal sync pulse and the data. all the parameters shown in the figur e are programmable. all controls are started by corresponding internal events?local start points. the timing diagrams correspond to inverse polarity of the ipp_disp_clk signal and active-low polarity of the hsync, vsync, and drdy signals. figure 48. tft panels timing di agram?horizontal sync pulse figure 49 depicts the vertical timing (t iming of one frame). all parame ters shown in the figure are programmable. figure 49. tft panels timing diagram?vertical sync pulse di clock vsync hsync drdy d0 d1 ip5o ip13o ip9o ip8o ip8 ip9 dn ip10 ip7 ip5 ip6 local start point local start point local start point ipp_disp_clk ipp_data ip14 vsync hsync drdy start of frame end of frame ip12 ip15 ip13 ip11
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 93 table 61 shows timing characteristics of signals presented in figure 48 and figure 49 . table 61. synchronous display interface timing characteristics (pixel level) id parameter symbol value description unit ip5 display interface clock period tdicp ( 1 ) display interface clock. ipp_disp_clk ns ip6 display pixel clock period tdpcp disp_clk_per_pixel tdicp time of translation of one pixel to display, disp_clk_per_pixel?number of pixel components in one pixel (1.n). the disp_clk_per_pixel is virtual parameter to define display pixel clock period. the disp_clk_per_pixel is received by dc/di one access division to n components. ns ip7 screen width time tsw (screen_width) tdicp screen_width?screen width in, interface clocks. horizontal blanking included. the screen_width should be built by suitable di?s counter 2 . ns ip8 hsync width time thsw (hsync_width) hsync_width?hsync width in di_clk with 0.5 di_clk resolution. defined by di?s counter. ns ip9 horizontal blank interval 1 thbi1 bgxp tdicp bgxp?width of a horizontal blanking before a first active data in a line (in interface clocks). the bgxp should be built by suitable di?s counter. ns ip10 horizontal blank interval 2 thbi2 (screen_width ? bgxp ? fw) tdicp width a horizontal blanking after a last active data in a line (in interface clocks) fw?with of active line in interface clocks. the fw should be built by suitable di?s counter. ns ip12 screen height tsh (screen_height) tsw screen_height? screen height in lines with blanking. the screen_height is a distance between 2 vsyncs. the screen_height should be built by suitable di?s counter. ns ip13 vsync width tvsw vsync_width vsync_ width?vsync width in di_clk with 0.5 di_clk resolution. defined by di?s counter ns ip14 vertical blank interval 1 tvbi1 bgyp tsw bgyp?width of first vertical blanking interval in line.the bgyp should be built by suitable di?s counter. ns ip15 vertical blank interval 2 tvbi2 (screen_height ? bgyp ? fh) tsw width of second vertical blanking interval in line.the fh should be built by suitable di?s counter. ns
i.mx53xd applications processors for consumer products, rev. 2 94 freescale semiconductor electrical characteristics the maximal accuracy of up/down edge of controls is: ip5o offset of ipp_disp_cl k todicp disp_clk_offset tdiclk disp_clk_offset?offset of ipp_disp_clk edges from local start point, in di_clk 2 (0.5 di_clk resolution) defined by disp_clk counter ns ip13o offset of vsync tovs vsync_offset tdiclk vsync_offset?offset of vsync edges from a local start point, when a vsync should be active, in di_clk 2 (0.5 di_clk resolution).the vsync_offset should be built by suitable di?s counter. ns ip8o offset of hsync tohs hsync_offset tdiclk hsync_offset?offset of hsync edges from a local start point, when a hsync should be active, in di_clk 2 (0.5 di_clk resolution).the hsync_offset should be built by suitable di?s counter. ns ip9o offset of drdy todrdy drdy_offset tdiclk drdy_offset?offset of drdy edges from a suitable local start point, when a corresponding data has been set on the bus, in di_clk 2 (0.5 di_clk resolution) the drdy_offset should be built by suitable di?s counter. ns 1 display interface clock period immediate value. disp_clk_period?number of di_clk per on e tdicp. resolution 1/16 of di_clk. di_clk_period?relation of between programing clock frequency and current system clock frequency display interface clock period average value. 2 di?s counter can define offset, period an d up/down characteristic of output signal according to programed parameters of the counter. same of parameters in the table are not defined by di?s registers directly (by name), but can be generated by corresponding di?s counter. the screen_width is an input value for di?s hsync generation counter. the distance between hsyncs is a screen_width. table 61. synchronous display interface timing characteristics (pixel level) (continued) id parameter symbol value description unit tdicp t diclk disp_clk_period di_clk_period ---------------------------------------------------- for integer disp_clk_period di_clk_period ---------------------------------------------------- , t diclk floor disp_clk_period di_clk_period ---------------------------------------------------- 0.5 0.5 + ?? ?? for fractional disp_clk_period di_clk_period ---------------------------------------------------- , ? ? ? ? ? ? ? = tdicp t diclk disp_clk_period di_clk_period ---------------------------------------------------- = accuracy 0.5 t diclk () 0.62ns =
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 95 the maximal accuracy of up/down edge of ipp_data is: the disp_clk_period, di_clk_period parame ters are programmed through the registers. figure 50 depicts the synchronous display interface tim ing for access level. the disp_clk_down and disp_clk_up parameters are set through the register. table 62 lists the synchronous display interface timing characteristics. figure 50. synchronous display interface timing diagram?access level table 62. synchronous display interfa ce timing characteristics (access level) id parameter symbol min typ 1 1 the exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . these conditions may be chip specific. max unit ip16 display interface clock low time tckl tdicd-tdicu?1.24 tdicd 2 ?tdicu 3 tdicd?tdicu+1.24 ns ip17 display interface clock high time tckh tdicp?tdicd+tdicu?1.24 tdicp?tdicd+tdicu tdicp?tdicd+tdicu+1.2 ns ip18 data setup time tdsu tdicd?1.24 tdicu ? ns ip19 data holdup time tdhd tdicp?tdicd?1.24 tdicp?tdicu ? ns ip20o control signals offset times (defines for each pin) tocsu tocsu?1.24 tocsu tocsu+1.24 ns ip20 control signals setup time to display interface clock (defines for each pin) tcsu tdicd?1.24?tocsu%tdicp tdicu ? ns accuracy t diclk 0.62ns = ip19 ip18 ip20 vsync ip17 ip16 drdy hsync other controls ip20o local start point tdicd tdicu ipp_disp_clk ipp_data
i.mx53xd applications processors for consumer products, rev. 2 96 freescale semiconductor electrical characteristics 4.7.8.7 interface to a tv encoder (tvdac) the interface has an 8-bit data bus, transferring a si ngle 8-bit value (y/u/v) in each cycle. the timing of the interface is described in figure 51 . note ? the frequency of the clock disp_clk is 27 mhz (within 10%) ? the hsync, vsync signals are active low. ? the drdy signal is shown as active high. ? the transition to the next row is marked by the negative edge of the hsync signal. it remains low for a single clock cycle. ? the transition to the next field/frame is marked by the negative edge of the vsync signal. it remains low for at least one clock cycles. ? at a transition to an odd field (of th e next frame), the negative edges of vsync and hsync coincide. ? at a transition is to an even fi eld (of the same frame), they do not coincide. ? the active intervals?during which data is transferred?are marked by the hsync signal being high. 2 display interface clock down time 3 display interface clock up time where ceil(x) rounds the elements of x to the nearest integers towards infinity. tdicd 1 2 -- -t diclk ceil 2 disp_clk_down di_clk_period ----------------------------------------------------------- ?? ?? = tdicu 1 2 -- -t diclk ceil 2 disp_clk_up di_clk_period ------------------------------------------------ ?? ?? =
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 97 figure 51. tv encoder interface timing diagram hsync vsync cb y cr cb y cr y pixel data timing line and field timing - ntsc even field odd field odd field even field 624 621 311 308 line and field timing - pal hsync drdy vsync hsync drdy vsync even field odd field odd field even field 1 523 262 261 drdy hsync drdy vsync hsync vsync 524 525 2 3 4 10 263 264 265 266 267 268 269 273 622 623 625 1 2 23 309 310 312 313 314 336 56 34 316 315 drdy disp_clk ipp_data
i.mx53xd applications processors for consumer products, rev. 2 98 freescale semiconductor electrical characteristics 4.7.8.7.1 tvev2 tv encoder performance specifications the tv encoder output specifications are shown in table 63 . all the parameters in the table are defined under the following conditions: ?r set = 1.05 k 1%, resistor on tvdac_vref pin to gnd ?r load = 37.5 1%, output load to the gnd table 63. tv encoder video performance specifications parameter conditions min typ max unit dac static performance resolution 1 ??10?bits integral nonlinearity (inl) 2 ? ? 1 2 lsbs differential nonlinearity (dnl) 2 ? ? 0.6 1 lsbs channel-to-channel gain matching 2 ??2?% full scale output voltage 2 r set = 1.05 k 1% r load = 37.5 1% 1.24 1.306 1.37 v dac dynamic performance spurious free dynamic range (sfdr) f out = 3.38 mhz f samp = 216 mhz ?59? dbc spurious free dynamic range (sfdr) f out = 9.28 mhz f samp = 297 mhz ?54? dbc video performance in sd mode 2 short term jitter (line to line) ? ? 2.5 ? ns long term jitter (field to field) ? ? 3.5 ? ns frequency response 0-4.0 mhz ?0.1 ? 0.1 db 5.75 mhz ?0.7 ? 0 db luminance nonlinearity ? ? 0.5 ? % differential gain ? ? 0.35 ? % differential phase ? ? 0.6 ? degrees signal-to-noise ratio (snr) flat field full bandwidth ? 75 ? db hue accuracy ? ? 0.8 ? degrees color saturation accuracy ? ? 1.5 ? % chroma am noise ? ? ?70 ? db chroma pm noise ? ? ?47 ? db chroma nonlinear phase ? ? 0.5 ? degrees chroma nonlinear gain ? ? 2.5 ? % chroma/luma intermodulation ? ? 0.1 ? % chroma/luma gain inequality ? ? 1.0 ? %
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 99 4.7.8.8 asynchronous interfaces the following sections describes the types of asynchronous interfaces. 4.7.8.8.1 standard parallel interfaces the ipu has four signal generato r machines for asynchronous signal. each machine generates ipu?s internal control levels (0 or 1) by up and down that are defined in registers. each asynchronous pin has a dynamic connection w ith one of the signal generators. this c onnection is redefined again with a new display access (pixel/component). the ipu can gene rate control signals according to system 80/68 requirements. the burst length is received as a result from predefined behavior of the internal signal generator machines. the access to a display is realized by the following: ? cs (ipp_cs) chip select ? wr (ipp_pin_11) write strobe ? rd (ipp_pin_12) read strobe ? rs (ipp_pin_13) register select (a0) both system 80 and system 68k in terfaces are supported for all desc ribed modes as depicted in figure 52 , figure 53 , figure 54 , and figure 55 . the timing images correspond to ac tive-low ipp_cs, wr and rd signals. each asynchronous access is defined by an access size paramete r. this parameter can be different between different kinds of accesses. this parameter defines a length of windows, when suitable controls of the current access are valid. a pause be tween two different display accesses can be guaranteed by programing suitable access sizes. there are no minimal/maximal hold/setup times hard defined by di. each control signal can be switched at any time during access size. chroma/luma delay inequality ? ? 1.0 ? ns video performance in hd mode 2 luma frequency response 0-30 mhz ?0.2 ? 0.2 db chroma frequency response 0-15 mhz, ycbcr 422 mode ?0.2 ? 0.2 db luma nonlinearity ? ? 3.2 ? % chroma nonlinearity ? ? 3.4 ? % luma signal-to-noise ratio 0-30 mhz ? 62 ? db chroma signal-to-noise ratio 0-15 mhz ? 72 ? db 1 guaranteed by design. 2 guaranteed by characterization. table 63. tv encoder video performance specifications (continued) parameter conditions min typ max unit
i.mx53xd applications processors for consumer products, rev. 2 100 freescale semiconductor electrical characteristics figure 52. asynchronous parallel system 80 interface (type 1) timing diagram rs wr rd rs wr rd burst access mode with sampling by cs signal single access mode (all control signals are not active for one display interface clock after each display access) ipp_cs ipp_data ipp_cs ipp_data
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 101 figure 53. asynchronous parallel system 80 interface (type 2) timing diagram rs wr rd rs wr rd burst access mode with sampling by wr/rd signals single access mode (all control signals are not active for one display interface clock after each display access) ipp_cs ipp_cs ipp_data ipp_data
i.mx53xd applications processors for consumer products, rev. 2 102 freescale semiconductor electrical characteristics figure 54. asynchronous parallel system 68k interface (type 1) timing diagram wr rd wr rd (read/write) (enable) rs rs (read/write) (enable) burst access mode with sampling by cs signal single access mode (all control signals ar e not active for one display interface clock after each display access) ipp_cs ipp_cs ipp_data ipp_data
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 103 figure 55. asynchronous parallel system 68k interface (type 2) timing diagram display operation can be performed with ipp_wait si gnal. the di reacts to the incoming ipp_wait signal with 2 di_clk delay. the di finishes a cu rrent access and a next access is postponed until ipp_wait release. figure 56 shows timing of the parallel interface with ipp_wait control. rs wr rd rs wr rd (read/write) (enable) (read/write) (enable) burst access mode with sampling by enable signal single access mode (all control signals ar e not active for one display interface clock after each display access) ipp_cs ipp_data ipp_cs ipp_data
i.mx53xd applications processors for consumer products, rev. 2 104 freescale semiconductor electrical characteristics figure 56. parallel interface ti ming diagram?read wait states 4.7.8.8.2 asynchronous parallel interface timing parameters figure 57 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. table 65 shows timing characteristics at display access level. al l timing diagrams are based on active low control signals (si gnals polarity is cont rolled through the di_disp_sig_pol register). di clock ipp_data wr rd ipp_wait ipp_data_in waiting waiting ip39 ipp_cs
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 105 figure 57. asynchronous parallel interface timing diagram table 64. asynchronous display interface timing parameters (pixel level) id parameter symbol value description unit ip28a address write system cycle time tcycwa access_ size_# predefined value in di register ns ip28d data write system cycle time tcycwd access_ size_# predefined value in di register ns ip29 rs start tdcsrr up# rs strobe switch, predefined value in di register ns ip30 cs start tdcsc up# cs strobe switch, predefined value in di register ns ip31 cs hold tdchc down# cs strobe release, predefined value in di register ? ip32 rs hold tdchrr down# rs strobe release, predefined value in di register ? ip35 write start tdcsw up# write strobe switch, predefined value in di register ns ip36 controls hold time for write tdchw do wn# write strobe release, predefined value in di register ns di clock rs wr rd a0 d0 d1 pp_data_in d2 d3 local start point ip27 ip28d ip28a local start point local start point local start point local start point ip37 ip33 ip35 ip38 ip34 ip36 ip29 ip31 ip32 ip47 ip30 ipp_cs ipp_data
i.mx53xd applications processors for consumer products, rev. 2 106 freescale semiconductor electrical characteristics table 65. asynchronous parallel interf ace timing parameters (access level) id parameter symbol min typ 1 1 the exact conditions have not been finalized, but will likely match the current customer requirement for their specific display . these conditions may be chip specific. max unit ip28 write system cycle time tcycw tdicpw ? 1.24 tdicpw 2 2 display period value for write access_size is predefined in register. tdicpw+1.24 ns ip29 rs start tdcsrr tdicurs ? 1.24 tdicurs tdicurs+1.24 ns ip30 cs start tdcsc tdicucs ? 1.24 tdicur tdicucs+1.24 ns ip31 cs hold tdchc tdicdcs ? tdicucs ? 1.2 4 tdicdcs 3 ?tdicucs 4 3 display control down for cs disp_down is predefined in register. 4 display control up for cs disp_up is predefined in register. tdicdcs ? tdicucs+1.24 ns ip32 rs hold tdchrr tdicdrs ? tdicurs ? 1.24 tdicdrs 5 ?tdicurs 6 5 display control down for rs disp_down is predefined in register. 6 display control up for rs disp_up is predefined in register. tdicdrs ? tdicurs+1.24 ns ip35 controls setup time for write tdcsw tdicuw ? 1.24 tdicuw tdicuw+1.24 ns ip36 controls hold time for write tdchw tdicdw ? tdicuw ? 1.24 tdicpw 7 ?tdicuw 8 tdicdw?tdicuw+1.24 ns ip38 slave device data hold time 8 troh tdrp?tlbd?tdicdr+1. 24 ? tdicpr ? tdicdr ? 1.24 ns tdicpw t di_clk ceil di_access_size_# di_clk_period ----------------------------------------------------- = tdicdcs 1 2 -- -t di_clk ceil 2 disp_down_# di_clk_period -------------------------------------------------- ?? ?? = tdicucs 1 2 -- -t di_clk ceil 2 disp_up_# di_clk_period --------------------------------------------- - ?? ?? = tdicdrs 1 2 -- -t di_clk ceil 2 disp_down_# di_clk_period -------------------------------------------------- ?? ?? = tdicurs 1 2 -- -t di_clk ceil 2disp_up_# di_clk_period --------------------------------------------- - ?? ?? =
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 107 4.7.9 lvds display bridge (ldb) module parameters the lvds interface complies with tia/eia 644-a standard. for more details, see tia/eia standard 644-a, ?electrical ch aracteristics of low voltage differenti al signaling (lvds) in terface circuits?. 4.7.10 one-wire (owire) timing parameters figure 58 depicts the rpp timing, and table 66 lists the rpp timing parameters. figure 58. reset and presence pulses (rpp) timing diagram 7 display control down for read disp_down is predefined in register. 8 display control up for write disp_up is predefined in register. table 66. rpp sequence delay comparisons timing parameters id parameters symb ol min typ max unit ow1 reset time low t rstl 480 511 ? 1 1 in order not to mask signaling by other devices on the 1-wire bus, t rstl + t r should always be less than 960 s. s ow2 presence detect high t pdh 15 ? 60 s ow3 presence detect low t pdl 60 ? 240 s ow4 reset time high (includes recovery time) t rsth 480 512 ? s tdicdrw 1 2 -- -t di_clk ceil 2 disp_down_# di_clk_period -------------------------------------------------- ?? ?? = tdicuw 1 2 -- -t di_clk ceil 2disp_up_# di_clk_period --------------------------------------------- - ?? ?? = one-wire bus one wire device tx ?presence pulse? (batt_line) one-wire tx ?reset pulse? ow1 ow2 ow3 ow4 t r
i.mx53xd applications processors for consumer products, rev. 2 108 freescale semiconductor electrical characteristics figure 59 depicts write 0 sequence timing, and table 67 lists the timing parameters. figure 59. write 0 sequence timing diagram figure 60 depicts write 1 sequence timing, figure 61 depicts the read sequence timing, and table 68 lists the timing parameters. figure 60. write 1 sequence timing diagram figure 61. read sequence timing diagram table 67. wr0 sequence timing parameters id parameter symbol min typ max unit ow5 write 0 low time t low0 60 100 120 s ow6 transmission time slot t slot ow5 117 120 s recovery time t rec 1??s ow5 ow6 one-wire bus (batt_line) t rec ow7 ow8 one-wire bus (batt_line) t su ow8 ow10 one-wire bus (batt_line) ow9 ow11
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 109 4.7.11 pulse width modulator (pwm) timing parameters this section describes the electrical information of the pwm. the pwm can be programmed to select one of three clock signals as its source frequency. the sel ected clock signal is passed through a prescaler before being input to the counter. the output is available at the pulse-width modulator output (pwmo) external pin. figure 62 depicts the timing of the pwm, and table 69 lists the pwm timing parameters. figure 62. pwm timing table 68. wr1 /rd timing parameters id parameter symbol min typ max unit ow7 write 1 low time t low1 1515s ow8 transmission time slot t slot 60 117 120 s read data setup t su ??1s ow9 read low time t lowr 1515s ow10 read data valid t rdv ?15?s ow11 release time t release 0?45s table 69. pwm output timing parameter ref. no. parameter min max unit 1 system clk frequency 1 1 cl of pwmo = 30 pf 0 ipg_clk mhz 2a clock high time 12.29 ? ns 2b clock low time 9.91 ? ns 3a clock fall time ? 0.5 ns 3b clock rise time ? 0.5 ns 4a output delay time ? 9.37 ns 4b output setup time 8.71 ? ns system clock 2a 1 pwm output 3b 2b 3a 4b 4a
i.mx53xd applications processors for consumer products, rev. 2 110 freescale semiconductor electrical characteristics 4.7.12 pata timing parameters this section describes the timing parameters of th e parallel ata module which are compliant with ata/atapi-6 specification. parallel ata module can work on pio/multi-word dma/ ultra dma transfer modes. each transfer mode has different data transfer rate, ul tra dma mode 4 data tr ansfer rate is up to 100mb/s. parallel ata module interface consist of a total of 29 pins. some pins act on differen t function in different transfer mode. there are different requireme nts of timing relationships among the function pins conform with ata/atapi-6 specification and these requirements ar e configurable by the ata module registers. table 70 and figure 63 define the ac characteristics of all the pata interface si gnals in all data transfer modes. figure 63. pata interface signals timing diagram the user must use level shifters for 5.0 v comp atibility on the ata inte rface. the i.mx53xd pata interface is 3.3 v compatible. the use of bus buffers introduces delay on the bus a nd skew between signal lines. these factors make it difficult to operate the bus at the highest speed (udma-5) when bus buf fers are used. if fast udma mode operation is needed, this may not be compatible with bus buffers. another area of attention is the slew rate limit imposed by th e ata specification on the ata bus. according to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 v/ns with a 40 pf load. not many vendors of bus buffers specify slew rate of the outgoing signals. when bus buffers are used, the ata_data bus buffer is special. this is a bidirectional bus buffer, so a direction control signal is needed. this direction control signal is at a_buffer_en. when its high, the bus should drive from host to device. when its low, the bus should drive from device to host. steering of the signal is such that contention on the host and device tri-state busse s is always avoided. table 70. ac characteristics of all interface signals id parameter symbol min max unit si1 rising edge slew rate for any signal on ata interface 1 1 srise and sfall shall meet this requirement when measured at the sender?s connector from 10?90% of full signal amplitude with all capacitive loads from 15 ? 40 pf where all signals have the same capacitive load value. s rise ?1.25v/ns si2 falling edge slew rate for any signal on ata interface 1 s fall ?1.25v/ns si3 host interface signal capacitance at the host connector c host ?20pf ata interface signals si1 si2
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 111 in the timing equations, some timing paramete rs are used. these parameters depend on the implementation of the i.mx53xd pa ta interface on silicon, the bus buffer used, the cable delay and cable skew. table 71 shows ata timing parameters. table 71. pata timing parameters name description value/ contributing factor 1 1 values provided where applicable. t bus clock period (ahb_clk_root) peripheral clock frequency (7.5 ns for 133 mhz clock) ti_ds set-up time ata_data to ata_iordy edge (udma-in only) udma0 udma1 udma2, udma3 udma4 udma5 15 ns 10 ns 7 ns 5 ns 4 ns ti_dh hold time ata_iordy edge to ata_data (udma-in only) udma0, udma1, udma2, udma3, udma4 udma5 5.0 ns 4.6 ns tco propagation delay bus clock l-to-h to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en 12.0 ns tsu set-up time ata_data to bus clock l-to-h 8.5 ns tsui set-up time ata_iordy to bus clock h-to-l 8.5 ns thi hold time ata_iordy to bus clock h to l 2.5 ns tskew1 max difference in propagation delay bus clock l-to-h to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en 7ns tskew2 max difference in buffer propagation delay for any of following signals: ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en transceiver tskew3 max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) transceiver tbuf max buffer propagation delay transceiver tcable1 cable propagation delay for ata_data cable tcable2 cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack cable tskew4 max difference in cable propagation de lay between ata_iordy and ata_data (read) cable tskew5 max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da 2, ata_da1, ata_da0, ata_data(write) cable tskew6 max difference in cable propagation delay without accounting for ground bounce cable
i.mx53xd applications processors for consumer products, rev. 2 112 freescale semiconductor electrical characteristics 4.7.12.1 pio mode read timing figure 64 shows timing for pio read. table 72 lists the timing parameters for pio read. figure 64. pio read timing diagram table 72. pio read timing parameters ata parameter parameter from figure 64 value controlling variable t1 t1 t1(min) = time_1 * t ? (tskew1 + tskew2 + tskew5) time_1 t2 (read) t2r t2(min) = time_2r * t ? (tskew1 + tskew2 + tskew5) time_2r t9 t9 t9(min) = time_9 * t ? (tsk ew1 + tskew2 + tskew6) time_9 t5 t5 t5(min) = tco + tsu + tbuf + tbuf+ tcable1 + tcable2 time_2 (affects tsu and tco) t6 t6 0 ? ta ta ta(min) = (1.5 + time_ax) * t ? (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax trd trd1 trd1(max) = (?trd)+ (tskew3 + tskew4) trd1(min) = (time_pio_rdx ? 0.5)*t ? (tsu + thi) (time_pio_rdx ? 0.5) * t > tsu + thi + tskew3 + tskew4 time_pio_rdx t0 ? t0(min) = (time_1 + time_2r+ time_9) * t time_1, time_2r, time_9
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 113 figure 65 shows timing for pio write. table 73 lists the timing parameters for pio write. figure 65. multi-word dma (mdma) timing table 73. pio write timing parameters ata paramete r parameter from figure 65 value controlling variable t1 t1 t1(min) = time_1 * t ? (tskew1 + tskew2 + tskew5) time_1 t2 (write) t2w t2(min) = time_2w * t ? (tskew1 + tskew2 + tskew5) time_2w t9 t9 t9(min) = time_9 * t ? (tskew1 + tskew2 + tskew6) time_9 t3 ? t3(min) = (time_2w ? time_on)* t ? (tskew1 + tskew2 +tskew5) if not met, increase time_2w t4 t4 t4(min) = time_4 * t ? tskew1 time_4 ta ta ta = (1.5 + time_ax) * t ? (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax t0 ? t0(min) = (time_1 + time_2 + time_9) * t time_1, time_2r, time_9 ? ? avoid bus contention when switching buffer on by making ton long enough ? ? ? avoid bus contention when switching buffer off by making toff long enough ?
i.mx53xd applications processors for consumer products, rev. 2 114 freescale semiconductor electrical characteristics figure 66 shows timing for mdma read, figure 67 shows timing for mdma write, and table 74 lists the timing parameters for mdma read and write. figure 66. mdma read timing diagram figure 67. mdma write timing diagram table 74. mdma read and write timing parameters ata parameter parameter from figure 66 (read), figure 67 (write) value controlling variable tm, ti tm tm(min) = ti(min) = time_m * t ? (tskew1 + tskew2 + tskew5) time_m td td, td1 td1(min) = td(min) = time_d * t ? (tskew1 + tskew2 + tskew6) time_d tk tk 1 tk(min) = time_k * t ? (tskew1 + tskew2 + tskew6) time_k t0 ? t0(min) = (time_d + time_k) * t time_d, time_k tg(read) tgr tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr(min-drive) = td ? te(drive) time_d tf(read) tfr tfr(min) = 5 ns ? tg(write) ? tg(min-write) = time_d * t ? (tskew1 + tskew2 + tskew5) time_d tf(write) ? tf(min-write) = time_k * t ? (tskew1 + tskew2 + tskew6) time_k tl ? tl (max) = (time_d + time_k ? 2) t ? (tsu + tco + 2 tbuf + 2 tcable2) time_d, time_k 2
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 115 4.7.12.2 ultra dma (udma) input timing figure 68 shows timing when the udma in transfer starts, figure 69 shows timing when the udma in host terminates transfer, figure 70 shows timing when the udma in device terminates transfer, and table 75 lists the timing parameters for udma in burst. figure 68. udma in transfer starts timing diagram tn, tj tkjn tn= tj= tkjn = time_jn * t ? (tskew1 + tskew2 + tskew6) time_jn ?ton toff ton = time_on t ? tskew1 toff = time_off t ? tskew1 ? 1 tk1 in the mdma figures ( figure 66 and figure 67 ) equals (tk ? 2*t). 2 tk1 in the mdma figures equals (tk ? 2*t). table 74. mdma read and write timing parameters (continued) ata parameter parameter from figure 66 (read), figure 67 (write) value controlling variable
i.mx53xd applications processors for consumer products, rev. 2 116 freescale semiconductor electrical characteristics figure 69. udma in host terminates transfer timing diagram figure 70. udma in device terminates transfer timing diagram table 75. udma in burst timing parameters ata parameter parameter from figure 68 , figure 69 , figure 70 description controlling variable tack tack tack (min) = (time_ack t) ? (tskew1 + tskew2) time_ack tenv tenv tenv (min) = (time_env t) ? (tskew1 + tskew2) tenv (max) = (time_env t) + (tskew1 + tskew2) time_env tds tds1 tds ? (tskew3) ? ti_ds > 0 tskew3, ti_ds, ti_dh should be low enough tdh tdh1 tdh ? (tskew3) ? ti_dh > 0
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 117 4.7.12.3 udma output timing figure 71 shows timing when the udma out transfer starts, figure 72 shows timing when the udma out host terminates transfer, figure 73 shows timing when the udma out device terminates transfer, and table 76 lists the timing parameters for udma out burst. figure 71. udma out transfer starts timing diagram tcyc tc1 (tcyc ? tskew) > t t big enough trp trp trp (min) = time_rp t ? (tskew1 + tskew2 + tskew6) time_rp ?tx1 1 (time_rp t) ? (tco + tsu + 3t + 2 tbuf + 2 tcable2) > trfs (drive) time_rp tmli tmli1 tmli1 (min) = (time_mlix + 0.4) t time_mlix tzah tzah tzah (min) = (time_zah + 0.4) t time_zah tdzfs tdzfs tdzfs = (time_dzfs t) ? (tskew1 + tskew2) time_dzfs tcvh tcvh tcvh = (time_cvh t) ? (tskew1 + tskew2) time_cvh ?ton toff 2 ton = time_on t ? tskew1 toff = time_off t ? tskew1 ? 1 there is a special timing requirement in the ata host that require s the internal diow to go only high 3 clocks after the last active edge on the dstrobe signal. the equation given on this line tries to capture this constraint. 2 make ton and toff big enough to avoid bus contention. table 75. udma in burst timing parameters (continued) ata parameter parameter from figure 68 , figure 69 , figure 70 description controlling variable
i.mx53xd applications processors for consumer products, rev. 2 118 freescale semiconductor electrical characteristics figure 72. udma out host terminates transfer timing diagram figure 73. udma out device terminates transfer timing diagram table 76. udma out burst timing parameters ata parameter parameter from figure 71 , figure 72 , figure 73 value controlling variable tack tack tack (min) = (time_ack t) ? (tskew1 + tskew2) time_ack tenv tenv tenv (min) = (time_env t) ? (tskew1 + tskew2) tenv (max) = (time_env t) + (tskew1 + tskew2) time_env tdvs tdvs tdvs = (time_dvs t) ? (tskew1 + tskew2) time_dvs tdvh tdvh tdvs = (time_dvh t) ? (tskew1 + tskew2) time_dvh tcyc tcyc tcyc = time_cyc t ? (tskew1 + tskew2) time_cyc t2cyc ? t2cyc = time_cyc 2 t time_cyc
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 119 4.7.13 sata phy parameters this section describes sata phy electrical specifications. 4.7.13.1 reference clock elect rical and jitte r specifications the refclk signal is differential and supports frequencies of 25 mhz or 50-156.25 mhz (100 mhz and 125 mhz are common frequencies). the frequency is pin-selectable (fo r more information about the signal, see ?per-transceiver control and status signa ls? in the sata phy chapter in the reference manual). table 77 provides the sata phy refe rence clock specifications. trfs1 trfs trfs = 1.6 t + tsui + tco + tbuf + tbuf ? ? tdzfs tdzfs = time_dzfs t ? (tskew1) time_dzfs tss tss tss = time_ss t ? (tskew1 + tskew2) time_ss tmli tdzfs_mli tdzfs_mli =max (time_dzfs, time_mli) t ? (tskew1 + tskew2) ? tli tli1 tli1 > 0 ? tli tli2 tli2 > 0 ? tli tli3 tli3 > 0 ? tcvh tcvh tcvh = (time_cvh t) ? (tskew1 + tskew2) time_cvh ?ton toff ton = time_on t ? tskew1 toff = time_off t ? tskew1 ? table 77. reference clock specifications parameters test conditions min max unit differential peak voltage (typically 0.71 v) ? 350 850 mv common mode voltage (refclk_p + refclk_m) / 2 ? 175 2,000 mv total phase jitter for information about total phase jitter, see following section ?3ps rms minimum/maximum duty cycle ? 40 60 % ui frequency range ? 25 156.25 mhz table 76. udma out burst timi ng parameters (continued) ata parameter parameter from figure 71 , figure 72 , figure 73 value controlling variable
i.mx53xd applications processors for consumer products, rev. 2 120 freescale semiconductor electrical characteristics 4.7.13.1.1 reference cl ock jitter measurement the total phase jitter on the referen ce clock is specified at 3 ps rms. th ere are numerous ways to measure the reference clock jitter, one of which is as follows. using a high-speed sampling scope (2 0 gsamples/s), 1 million samples of the differential reference clock are taken, and the zero-crossing times of each rising edge ar e calculated. from the zero-crossing data, an average reference clock period is calc ulated. this average reference cloc k period is subtracted from each sequential, instantaneous period to find the differen ce between each reference clock rising edge and the ideal placement to produce the phase jitter sequence. the power spectral density (psd) of the phase jitter is calculated and integrated after being weighted with th e transfer function shown in figure 74 . the square root of the resultant integral is the rms total phase jitter. figure 74. weighting function for rms phase jitter calculation 4.7.13.2 transmitter and receiver characteristics the sata phy meets or exceeds the electrical compliance requirements defined in the sata specification. the following subsections provide values obtained from a combination of simulations and silicon characterization. note the tables in the following sections indicate any exceptions to the sata specification or aspects of the sata phy that exceed th e standard, as well as provide information about parame ters not defined in the standard. 4.7.13.2.1 sata phy tra nsmitter characteristics table 78 provides specifications for sata phy transm itter characteristics. table 78. sata2 phy transmitter characteristics parameters symbol min typ max unit transmit common mode voltage v ctm 0.4 ? 0.6 v transmitter pre-emphasis accuracy (measured change in de-emphasized bit) ??0.5?0.5 db
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 121 4.7.13.2.2 sata phy r eceiver characteristics table 79 provides specificati ons for sata phy receiver characteristics. 4.7.13.3 sata_rext reference resistor connection the impedance calibration process requires connection of reference resistor 191 . 1% precision resistor on sata_rext pad to ground. resistor calibration consists of learning which state of the internal resistor calibration register causes an internal, digitally trimmed calibrati on resistor to best match the im pedance applied to the sata_rext pin. the calibration register value is then suppl ied to all tx and rx termination resistors. during the calibration process (for a few tens of mi croseconds), up to 0.3 mw can be dissipated in the external sata_rext resistor. at other times, no power is dissipated by the sata_rext resistor. 4.7.13.4 sata connectivity when not in use note the temperature sensor is part of the sata module. if sata ip is disabled, the temperature sensor will not wo rk as well. temperature sensor functionality is importa nt in supporting high perf ormance applications without overheating the devi ce (at high ambient temp). when both sata and thermal sensor are not require d, connect vp and vph s upplies to ground. the rest of the ports, both inputs and outputs (sata_r efclkm, sata_refclkp, sata_rext, sata_rxm, sata_rxp, sata_txm) can be left floating. it is not recommended to turn off the vph while the vp is active. when sata is not in use but thermal sensor is st ill required, both vp and vph supplies must be powered on according to their nominal voltage levels. the refe rence clock input frequency must fall within the specified range of 25 mhz to 156.25 mhz. sata_rext does not need to be connected, as the termination impedance is not of consequence. table 79. sata phy receiver characteristics parameters symbol min typ max unit minimum rx eye height (differential peak-to-peak) v min_rx_eye_height ? ? 175 mv tolerance ppm ?400 ? 400 ppm
i.mx53xd applications processors for consumer products, rev. 2 122 freescale semiconductor electrical characteristics 4.7.14 scan jtag controller (sjc) timing parameters figure 75 depicts the sjc test clock input timing. figure 76 depicts the sjc boundary scan timing. figure 77 depicts the sjc test access port. signal parameters are listed in table 80 . figure 75. test clock input timing diagram figure 76. boundary scan (jtag) timing diagram tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3 tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 123 figure 77. test access port timing diagram figure 78. trst timing diagram table 80. jtag timing id parameter 1,2 all frequencies unit min max sj0 tck frequency of operation 1/(3?t dc ) 1 0.001 22 mhz sj1 tck cycle time in crystal mode 45 ? ns sj2 tck clock pulse width measured at v m 2 22.5 ? ns sj3 tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 5 ? ns sj5 boundary scan input data hold time 24 ? ns sj6 tck low to output data valid ? 40 ns sj7 tck low to output high impedance ? 40 ns sj8 tms, tdi data set-up time 5 ? ns tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms sj8 sj9 sj10 sj11 sj10 tck (input) trst (input) sj13 sj12
i.mx53xd applications processors for consumer products, rev. 2 124 freescale semiconductor electrical characteristics 4.7.15 spdif timing parameters the sony/philips digital interconnect format (spdif) da ta is sent using the bi- phase marking code. when encoding, the spdif data signal is modulated by a cloc k that is twice the bit ra te of the data signal. table 81 and figures , show spdif timing parameters for the sony/philips digi tal interconnect format (spdif), including the timing of th e modulating rx clock (srck) for spd if in rx mode and the timing of the modulating tx clock ( stclk) for spdif in tx mode. sj9 tms, tdi data hold time 25 ? ns sj10 tck low to tdo data valid ? 44 ns sj11 tck low to tdo high impedance ? 44 ns sj12 trst assert time 100 ? ns sj13 trst set-up time to tck low 40 ? ns 1 t dc = target frequency of sjc 2 v m = mid-point voltage table 81. spdif timing parameters characteristics symbol timing parameter range units min max spdifin skew: asynchronous inputs, no specs apply ? ? 0.7 ns spdifout output (load = 50pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 24.2 31.3 ns spdifout1 output (load = 30pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 13.6 18.0 ns modulating rx clock (srck) period srckp 40.0 ? ns srck high period srckph 16.0 ? ns srck low period srckpl 16.0 ? ns modulating tx clock (stclk) period stclkp 40.0 ? ns stclk high period stclkph 16.0 ? ns stclk low period stclkpl 16.0 ? ns table 80. jtag timing (continued) id parameter 1,2 all frequencies unit min max
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 125 figure 79. spdif timing diagram figure 80. stclk timing 4.7.16 ssi timing parameters this section describes the timing parameters of the ssi module. the connectivity of the serial synchronous interfaces are summarized in table 82 . note ? the terms wl and bl used in the timing diagrams and tables refer to word length (wl) and bit length (bl). ? the ssi timing diagrams use gene ric signal names wherein the names used in the i.mx53 reference ma nual are channel specific signal names. for example, a channel clock referenced in the iomuxc chapter as aud3_txc appears in the timing diagram as txc. table 82. audmux port allocation port signal nomenclature type and access audmux port 1 ssi 1 internal audmux port 2 ssi 2 internal audmux port 3 aud3 external ? aud3 i/o audmux port 4 aud4 external ? eim or cspi1 i/o through iomuxc audmux port 5 aud5 external ? eim or sd1 i/o through iomuxc audmux port 6 aud6 external ? eim or disp2 through iomuxc audmux port 7 ssi 3 internal srck (output) v m v m srckp srckph srckpl stclk (input) v m v m stclkp stclkph stclkpl
i.mx53xd applications processors for consumer products, rev. 2 126 freescale semiconductor electrical characteristics 4.7.16.1 ssi transmitter timing with internal clock figure 81 depicts the ssi transmitte r internal clock timing and table 83 lists the timing parameters for the ssi transmitter internal clock. . figure 81. ssi transmitter internal clock timing diagram table 83. ssi transmitter timing with internal clock id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6.0 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6.0 ns ss6 (tx) ck high to fs (bl) high ? 15.0 ns ss8 (tx) ck high to fs (bl) low ? 15.0 ns ss10 (tx) ck high to fs (wl) high ? 15.0 ns ss12 (tx) ck high to fs (wl) low ? 15.0 ns ss14 (tx/rx) internal fs rise time ? 6.0 ns ss15 (tx/rx) internal fs fall time ? 6.0 ns ss16 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss19 ss1 ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 note: srxd input in synchronous mode only txc txfs (wl) (output) txfs (bl) (output) rxd (input) txd (output) : srxd input in synchronous mode only
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 127 note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of th e clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? the terms wl and bl refer to wo rd length (wl) and bit length (bl). ? ?tx? and ?rx? refer to the transm it and receive sections of the ssi. ? for internal frame sync operation us ing external clock, the fs timing is same as that of tx data (for exam ple, during ac97 mode of operation). ss17 (tx) ck high to stxd high/low ? 15.0 ns ss18 (tx) ck high to stxd high impedance ? 15.0 ns ss19 stxd rise/fall time ? 6.0 ns synchronous internal clock operation ss42 srxd setup before (tx) ck falling 10.0 ? ns ss43 srxd hold after (tx) ck falling 0.0 ? ns ss52 loading ? 25.0 pf table 83. ssi transmitter timing with internal clock (continued) id parameter min max unit
i.mx53xd applications processors for consumer products, rev. 2 128 freescale semiconductor electrical characteristics 4.7.16.2 ssi receiver timing with internal clock figure 82 depicts the ssi receiver internal clock timing and table 84 lists the timing parameters for the receiver timing with the internal clock figure 82. ssi receiver internal clock timing diagram table 84. ssi receiver timing with internal clock id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6.0 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6.0 ns ss7 (rx) ck high to fs (bl) high ? 15.0 ns ss9 (rx) ck high to fs (bl) low ? 15.0 ns ss11 (rx) ck high to fs (wl) high ? 15.0 ns ss13 (rx) ck high to fs (wl) low ? 15.0 ns ss20 srxd setup time before (rx) ck low 10.0 ? ns ss21 srxd hold time after (rx) ck low 0.0 ? ns ss50 ss48 ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 ss3 ss5 txc (output) txfs (bl) (output) txfs (wl) (output) rxd (input) rxc (output)
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 129 note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of th e clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? ?tx? and ?rx? refer to the transm it and receive sections of the ssi. ? the terms wl and bl refer to wo rd length (wl) and bit length (bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of tx data (for exam ple, during ac97 mode of operation). oversampling cl ock operation ss47 oversampling clock period 15.04 ? ns ss48 oversampling clock high period 6.0 ? ns ss49 oversampling clock rise time ? 3.0 ns ss50 oversampling clock low period 6.0 ? ns ss51 oversampling clock fall time ? 3.0 ns table 84. ssi receiver timing with internal clock (continued) id parameter min max unit
i.mx53xd applications processors for consumer products, rev. 2 130 freescale semiconductor electrical characteristics 4.7.16.3 ssi transmitter ti ming with external clock figure 83 depicts the ssi transmitte r external clock timing and table 85 lists the timing parameters for the transmitter timing wi th the external clock figure 83. ssi transmitter exte rnal clock timing diagram table 85. ssi transmitter timing with external clock id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss27 (tx) ck high to fs (bl) high ?10.0 15.0 ns ss29 (tx) ck high to fs (bl) low 10.0 ? ns ss31 (tx) ck high to fs (wl) high ?10.0 15.0 ns ss33 (tx) ck high to fs (wl) low 10.0 ? ns ss37 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss38 (tx) ck high to stxd high/low ? 15.0 ns ss45 ss33 ss24 ss26 ss25 ss23 note: srxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 txc (input) txfs (bl) (input) txfs (wl) (input) txd (output) rxd (input)
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 131 note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of th e clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? ?tx? and ?rx? refer to the transm it and receive sections of the ssi. ? the terms wl and bl refer to wo rd length (wl) and bit length (bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of tx data (for exam ple, during ac97 mode of operation). ss39 (tx) ck high to stxd high impedance ? 15.0 ns synchronous external clock operation ss44 srxd setup before (tx) ck falling 10.0 ? ns ss45 srxd hold after (tx) ck falling 2.0 ? ns ss46 srxd rise/fall time ? 6.0 ns table 85. ssi transmitter timing with external clock (continued) id parameter min max unit
i.mx53xd applications processors for consumer products, rev. 2 132 freescale semiconductor electrical characteristics 4.7.16.4 ssi receiver ti ming with external clock figure 84 depicts the ssi receiver external clock timing and table 86 lists the timing parameters for the receiver timing with the external clock. figure 84. ssi receiver exte rnal clock timing diagram table 86. ssi receiver timing with external clock id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss28 (rx) ck high to fs (bl) high ?10 15.0 ns ss30 (rx) ck high to fs (bl) low 10 ? ns ss32 (rx) ck high to fs (wl) high ?10 15.0 ns ss34 (rx) ck high to fs (wl) low 10 ? ns ss35 (tx/rx) external fs rise time ? 6.0 ns ss36 (tx/rx) external fs fall time ? 6.0 ns ss40 srxd setup time before (rx) ck low 10 ? ns ss41 srxd hold time after (rx) ck low 2 ? ns ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 ss40 ss22 ss32 ss36 ss41 txc txfs (bl) txfs (wl) rxd (input)
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 133 note ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of th e clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? ?tx? and ?rx? refer to the transm it and receive sections of the ssi. ? the terms wl and bl refer to wo rd length (wl) and bit length (bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of tx data (for exam ple, during ac97 mode of operation). 4.7.17 uart i/o configurat ion and timing parameters 4.7.17.1 uart rs-232 i/o configuration in different modes the i.mx53xd uart interfaces can se rve both as dte or dce device. this can be configured by the dcedte control bit (default 0 ? dce mode). table 87 shows the uart i/o configuration based on the enabled mode. 4.7.17.2 uart rs-232 serial mode timing the following sections describe the electrical in formation of the uart module in the rs-232 mode. 4.7.17.2.1 uart transmitter figure 85 depicts the transmit timi ng of uart in the rs-232 serial mode, with 8 data bit/ 1 stop bit format. table 88 lists the uart rs-232 serial mode transmit timing characteristics. table 87. uart i/o configuration vs. mode port dte mode dce mode direction description direction description rts output rts from dte to dce input rts from dte to dce cts input cts from dce to dte output cts from dce to dte dtr output dtr from dte to dce input dtr from dte to dce dsr input dsr from dce to dte output dsr from dce to dte dcd input dcd from dce to dte output dcd from dce to dte ri input ring from dce to dte output ring from dce to dte txd_mux input serial data from dce to dte output serial data from dce to dte rxd_mux output serial data from dte to dce input serial data from dte to dce
i.mx53xd applications processors for consumer products, rev. 2 134 freescale semiconductor electrical characteristics figure 85. uart rs-232 serial mode transmit timing diagram 4.7.17.2.2 uart receiver figure 86 depicts the rs-232 serial m ode receive timing with 8 da ta bit/1 stop bit format. table 89 lists serial mode receive timing characteristics. figure 86. uart rs-232 serial mode receive timing diagram 4.7.17.3 uart irda mode timing the following subsections give the uart transmit and receive timings in irda mode. 4.7.17.3.3 uart irda mode transmitter figure 87 depicts the uart irda mode transmit timing, with 8 data bit/1 stop bit format. table 90 lists the transmit timin g characteristics. table 88. rs-232 serial mode transmit timing parameters id parameter symbol min max units ua1 transmit bit time t tbit 1/f baud_rate 1 ? t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk ? table 89. rs-232 serial mode receive timing parameters id parameter symbol min max units ua2 receive bit time 1 1 the uart receiver can tolerate 1/(16 *f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 *f baud_rate ). t rbit 1/f baud_rate 2 ? 1/(16*f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16*f baud_rate ) ? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 txd (output) bit 3 start bit stop bit next start bit possible parity bit par bit ua1 ua1 ua1 ua1 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd (input) bit 3 start bit stop bit next start bit possible parity bit par bit ua2 ua2 ua2 ua2
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 135 figure 87. uart irda mode transmit timing diagram 4.7.17.3.4 uart irda mode receiver figure 88 depicts the uart irda mode receive ti ming, with 8 data bit/1 stop bit format. table 91 lists the receive timing characteristics. figure 88. uart irda mode receive timing diagram table 90. irda mode transmit timing parameters id parameter symbol min max units ua3 transmit bit time in irda mode t tirbit 1/f baud_rate 1 ? t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk ? ua4 transmit ir pulse duration t tirpulse (3/16)*(1/f baud_rate ) ? t ref_clk (3/16)*(1/f baud_rate ) + t ref_clk ? table 91. irda mode receive timing parameters id parameter symbol min max units ua5 receive bit time 1 in irda mode 1 the uart receiver can tolerate 1/(16 *f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 *f baud_rate ). t rirbit 1/f baud_rate 2 ? 1/(16*f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16*f baud_rate ) ? ua6 receive ir pulse duration t rirpulse 1.41 us (5/16)*(1/f baud_rate )? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 txd (output) bit 3 start bit stop bit possible parity bit ua3 ua3 ua3 ua3 ua4 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd (input) bit 3 start bit stop bit possible parity bit ua5 ua5 ua5 ua5 ua6
i.mx53xd applications processors for consumer products, rev. 2 136 freescale semiconductor electrical characteristics 4.7.18 usb-oh-3 parameters this section describes th e electrical parameters of the usb ot g port and usb host ports. for on-chip usb phy parameters see section 4.7.19, ?usb phy parameters .? 4.7.18.1 serial interface in order to support four seri al different interfaces, the usb serial transceiver can be configured to operate in one of four modes: ? dat_se0 bidirectional, 3-wire mode ? dat_se0 unidirectional, 6-wire mode ? vp_vm bidirectional, 4-wire mode ? vp_vm unidirectional, 6-wire mode 4.7.18.1.1 dat_se0 bidirectional mode figure 89. usb transmit waveform in dat_se0 bidirectional mode table 92. signal definitions - dat_se0 bidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out in tx data when usb_txoe_b is low differential rx data when usb_txoe_b is high usb_se0_vm out in se0 drive when usb_txoe_b is low se0 rx indicator when usb_txoe_b is high usb_dat_vp usb_se0_vm us1 us2 transmit us4 usb_txoe_b us3
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 137 figure 90. usb receive waveform in dat_se0 bidirectional mode table 93. definitions of usb waveform in dat_se0 bi-directional mode no. parameter signal name direction min max unit conditions / reference signal us1 tx rise/fall time usb_dat_vp out -? 5.0 ns 50 pf us2 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us3 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us4 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us7 rx rise/fall time usb_dat_vp in ? 3.0 ns 35 pf us8 rx rise/fall time usb_se0_vm in ? 3.0 ns 35 pf us8 us7 usb_dat_vp usb_se0_vm usb_txoe_b receive usb_se0_vm
i.mx53xd applications processors for consumer products, rev. 2 138 freescale semiconductor electrical characteristics 4.7.18.1.2 dat_se0 unidirectional mode figure 91. usb transmit waveform in dat_se0 unidirectional mode table 94. signal definitions - dat_se0 unidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx data when usb_txoe_b is low usb_se0_vm out se0 drive when usb_txoe_b is low usb_vp1 in buffered data on dp when usb_txoe_b is high usb_vm1 in buffered data on dm when usb_txoe_b is high usb_dat_vp usb_se0_vm us9 us10 transmit us12 usb_txoe_b us11
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 139 figure 92. usb receive waveform in dat_se0 unidirectional mode table 95. usb port timing specification in dat_se0 unidirectional mode no. parameter signal name signal source min max unit condition / reference signal us9 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us10 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us11 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us12 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us15 rx rise/fall time usb_vp1 in ? 3.0 ns 35 pf us16 rx rise/fall time usb_vm1 in ? 3.0 ns 35 pf us16 us15 usb_dat_vp usb_txoe_b receive usb_se0_vm
i.mx53xd applications processors for consumer products, rev. 2 140 freescale semiconductor electrical characteristics 4.7.18.1.3 vp_vm bidirectional mode figure 93. usb transmit waveform in vp_vm bidirectional mode figure 94. usb receive waveform in vp_vm bidirectional mode table 96. signal definitions - vp_vm bidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out (tx) in (rx) tx vp data when usb_txoe_b is low rx vp data when usb_txoe_b is high usb_se0_vm out (tx) in (rx) tx vm data when usb_txoe_b low rx vm data when usb_txoe_b high usb_dat_vp usb_se0_vm us18 us19 transmit usb_txoe_b us20 us22 us21 us22 usb_dat_vp usb_se0_vm us26 us28 us27 receive
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 141 table 97. usb port timing specific ation in vp_vm bidirectional mode no. parameter signal name direction min max unit condition / reference signal us18 tx rise/fall time usb_dat_v p out ? 5.0 ns 50 pf us19 tx rise/fall time usb_se0_v m out ? 5.0 ns 50 pf us20 tx rise/fall time usb_txoe _b out ? 5.0 ns 50 pf us21 tx duty cycle usb_dat_v p out 49.0 51.0 % ? us22 tx overlap usb_se0_v m out -3.0 +3.0 ns usb_dat_vp us26 rx rise/fall time usb_dat_v p in ? 3.0 ns 35 pf us27 rx rise/fall time usb_se0_v m in ? 3.0 ns 35 pf us28 rx skew usb_dat_v p in -4.0 +4.0 ns usb_se0_vm
i.mx53xd applications processors for consumer products, rev. 2 142 freescale semiconductor electrical characteristics 4.7.18.1.4 vp_vm un idirectional mode figure 95. usb transmit waveform in vp_vm unidirectional mode table 98. signal definitions - vp_vm unidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx vp data when usb_txoe_b is low usb_se0_vm out tx vm data when usb_txoe_b is low usb_vp1 in rx vp data when usb_txoe_b is high usb_vm1 in rx vm data when usb_txoe_b is high usb_dat_vp usb_se0_vm us30 us31 transmit usb_txoe_b us32 us34 us33
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 143 figure 96. usb receive waveform in vp_vm unidirectional mode table 99. usb timing specification in vp_vm unidirectional mode no. parameter signal di rection min max unit conditions / reference signal us30 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us31 tx rise/fall time usb_se0_v m out ? 5.0 ns 50 pf us32 tx rise/fall time usb_txoe_ b out ? 5.0 ns 50 pf us33 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us34 tx overlap usb_se0_v m out -3.0 3.0 ns usb_dat_vp us38 rx rise/fall time usb_vp1 in ? 3.0 ns 35 pf us39 rx rise/fall time usb_vm1 in ? 3.0 ns 35 pf us40 rx skew usb_vp1 in -4.0 +4.0 ns usb_vm1 us38 usb_vm1 receive usb_txoe_b us40 us39 usb_vp1
i.mx53xd applications processors for consumer products, rev. 2 144 freescale semiconductor electrical characteristics 4.7.18.2 parallel interface (normal ulpi) timing electrical and timing specifications of parallel inte rface (normal ulpi) for host port2 and port3 are presented in the subsequent sections. figure 97. usb transmit/receive waveform in parallel mode 4.7.19 usb phy parameters this section describes the usb-otg phy and the usb host port phy parameters. 4.7.19.1 usb phy ac parameters table 102 lists the ac timing parameters for usb phy. table 100. signal definitions - parallel interface (normal ulpi) name direction signal description usb_clk in interface clock. all interface signals are synchronous to clock. usb_data[7:0] i/o bi-directional data bus, driven low by the link during idle. bus ownership is determined by dir. usb_dir in direction. control the direction of the data bus. usb_stp out stop. the link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. usb_nxt in next. the phy asserts this signal to throttle the data. table 101. usb timing specification for normal ulpi mode id parameter min max unit conditions / reference signal us15 setup time (dir&nxt in, data in) 6.0 ? ns 10 pf us16 hold time (dir&nxt in, data in) 0.0 ? ns 10 pf us17 output delay time (stp out, data out ? 9.0 ns 10 pf usb_stp usb_dir/nxt us17 us16 usb_data us15 us16 us15 us17 usb_clk
electrical characteristics i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 145 4.7.19.2 usb phy additional electrical parameters table 103 lists the parameters for additional electrical character istics for usb phy. 4.7.19.3 usb phy system clocking (sysclk) table 104 lists the usb phy syst em clocking parameters. table 102. usb phy ac timing parameters parameter conditions min typ max unit trise 1.5 mbps 12 mbps 480 mbps 75 4 0.5 ?300 20 ns tfall 1.5 mbps 12 mbps 480 mbps 75 4 0.5 ?300 20 ns jitter 1.5 mbps 12 mbps 480 mbps ??10 1 0.2 ns table 103. additional electrical characteristics for usb phy parameter conditions min typ max unit vcm dc (dc level measured at receiver connector) hs mode ls/fs mode ?0.05 0.8 ?0.5 2.5 v crossover voltage ls mode fs mode 1.3 1.3 ?2 2 v power supply ripple noise (analog 3.3 v) <160mhz ?50 0 50 mv power supply ripple noise (analog 2.5 v) <1.2mhz >1.2mhz ?10 ?50 0 0 10 50 mv power supply ripple noise (digital 1.2 v) all conditions ?50 0 50 mv table 104. usb phy system clocking parameters parameter conditions min typ max unit clock deviation reference clock frequency 24 mhz ?150 ? 150 ppm rise/fall time ? ? ? 200 ps jitter (peak-peak) < 1.2 mhz 0 ? 50 ps jitter (peak-peak) > 1.2 mhz 0 ? 100 ps duty-cycle reference clock frequency 24 mhz 40 ? 60 %
i.mx53xd applications processors for consumer products, rev. 2 146 freescale semiconductor electrical characteristics 4.7.19.4 usb phy voltage thresholds table 105 lists the usb phy voltage thresholds. 4.7.19.5 usb phy termination usb driver impedance in fs and hs modes is 45 10% (steady state). no ex ternal resistors required. 4.8 xtal electrical specifications table 106 shows the xtalosc el ectrical specifications. table 107 shows the xtalosc_32k electrical specifications. 4.9 integrated ldo voltage regulators parameters the pll supplies vdd_dig_pll and vdd_ana_pll can be powered on from internal ldo voltage regulator (default case). in this case vdd_reg is used as internal regulator?s power source. the regulator?s output can be used as a supply for other domains such as vdda and vddal1. table 108 shows the vdd_dig_pll and vdd_ana_pll inte grated voltage regulators parameters. table 105. vbus comparators thresholds parameter conditions min typ max unit a-device session valid ? 0.8 1.4 2.0 v b-device session valid ? 0.8 1.4 4.0 v b-device session end ? 0.2 0.45 0.8 v vbus valid comparator threshold 1 1 for vbus maximum rating, see ta b l e 4 on page 18 ?4.44.64.75v table 106. xtalosc electrical specifications parameter min typ max units frequency 22 24 27 mhz table 107. xtalosc_32k electrical specifications parameter min typ max units frequency -- 32.768/32.0 1 1 recommended nominal frequency 32.768 khz. -- khz
boot mode configuration i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 147 5 boot mode configuration this section provides information on boot mode configuration pins allo cation and boot devices interfaces allocation. 5.1 boot mode configuration pins table 109 provides boot options, functionality, fuse values, and asso ciated pins. several input pins are also sampled at reset and can be used to override fuse values, depending on the value of bt_fuse_sel fuse. the boot option pins are in effect when bt_fuse_sel fuse is ?0? (cleared, which is the case for an unblown fuse). for detailed boot m ode options configured by the boot mode pins, please refer to the i.mx53xd fuse map document and boot chapter in i.mx53 reference manual. table 108. ldo voltage regulators electrical specifications parameter symbol min typ max units vdd_dig_pll functional voltage range 1 1 vdd_dig_pll and vdd_ana_pll voltages are programmable, bu t should not be set outside the target functional range for proper pll operation. v vid_dig_pll 1.15 1.2 1.3 v vdd_ana_pll functional voltage range 1 v vdd_ana_pll 1.7 1.8 1.95 v vdd_dig_pll and vdd_ana_pll accuracy ???+/?3% vdd_dig_pll power-supply rejection ratio 2 2 the gain or attenuation from the input supply variation to the output of the ldo (by design). ???18?db vdd_ana_pll power-supply rejection ratio 2 ???15?db output current 3 3 the limitation is for sum of the vdd_dig_pll and vdd_ana_pll current. i vid_dig_pll + i vdd_ana_pll ? ? 125 ma table 109. fuses and associated pins used for boot pin direction at reset e-fuse name details boot_mode[1] input n/a boot mode selection boot_mode[0] input
i.mx53xd applications processors for consumer products, rev. 2 148 freescale semiconductor boot mode configuration 5.2 boot devices interfaces allocation table 110 lists the interfaces that can be used by th e boot process in accordance with the specific boot mode configuration. the table also describes the interface?s specific modes and iomuxc allocation, which are configured during boot when appropriate. eim_a22 input boot_cfg1[7]/test mode selection boot options, pin value overrides fuse settings for bt_fuse_sel = ?0? . signal configuration as fuse override input at power up. these are special i/o lines that control the boot up configuration during product development. in production, the boot configuration can be controlled by fuses. eim_a21 input boot_cfg1[6]/test mode selection eim_a20 input boot_cfg1[5]/test mode selection eim_a19 input boot_cfg1[4] eim_a18 input boot_cfg1[3] eim_a17 input boot_cfg1[2] eim_a16 input boot_cfg1[1] eim_lba input boot_cfg1[0] eim_eb0 input boot_cfg2[7] eim_eb1 input boot_cfg2[6] eim_da0 input boot_cfg2[5] eim_da1 input boot_cfg2[4] eim_da2 input boot_cfg2[3] eim_da3 input boot_cfg2[2] eim_da4 input boot_cfg3[7] eim_da5 input boot_cfg3[6] eim_da6 input boot_cfg3[5] eim_da7 input boot_cfg3[4] eim_da8 input boot_cfg3[3] eim_da9 input boot_cfg3[2] eim_da10 input boot_cfg3[1] table 110. interfaces allocation during boot interface ip instance allocate d pads during boot comment spi cspi eim_a25, eim_d21, eim_d22, eim_d28 only ss1 is supported spi ecspi-1 eim_d[19:16] only ss1 is supported spi ecspi-2 csi_dat[10:8], eim_lba only ss1 is supported table 109. fuses and associated pins used for boot (continued) pin direction at reset e-fuse name details
boot mode configuration i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 149 5.3 power setup during boot by default, vdd_dig_pll is driven from internal on-die 1.2 v linear regulator (ldo). in order to achieve the standard operating mode (see vdd_dig_pll on table 7 ), ldo output to vdd_dig_pll should be configured by software by boot code after power-up to 1.3 v output. this is done by programming the pll1p2_vreg bits. eim eim eim ? lower 16 bit data bus a/d multiplexed or upper 16 bit data bus non multiplexed ? only cs0 is supported. nand flash extmc nand ? 8/16 bit ? nand data can be muxed either over eim data or pata data ? only cs0 is supported sd/mmc esdhcv2-1 pata_data[11:8], sd1_data[3:0], sd1_cmd, sd1_clk 1, 4 or 8 bit sd/mmc esdhcv2-2 pata_data[15: 12], sd2_clk, sd2_cmd, sd2_data[3:0] 1, 4 or 8 bit sd/mmc esdhcv3-3 pata_reset_b, pata_iordy, pata_da_0, pata _ data [ 3 : 0 ] , pata _ data [ 1 1 : 8 ] 1, 4 or 8 bit sd/mmc esdhcv2-4 pata_da1, pata_da_2, pata_data[7:4], pata _ data [ 1 5 : 1 2 ] 1, 4 or 8 bit i2c i2c-1 eim_d21, eim_d28 ? i2c i2c-2 eim_d16, eim_eb2 ? i2c i2c-3 eim_d[18:17] ? pata pata pata _ d i ow, pata _ d m ac k , pata _ d m a r q , pata _ b u f f e r _ e n , pata _ i n t r q , pata _ d i o r , pata_reset_b, pata_iord y, pata_da_[2:0], pata _ c s _ [ 1 : 0 ] , pata _ data [ 1 5 : 0 ] ? sata sata_phy sata_txm, sata_txp, sata_rxp, sata_rxm, sata_rext, sata_refclkm, sata_refclkp ? uart uartv2-1 csi0_dat[11:10] rxd/txd only uart uartv2-2 pata_dmarq, pata_buffer_en rxd/txd only uart uartv2-3 eim_d24, eim_d25 rxd/txd only uart uartv2-4 csi0_dat[13:12] rxd/txd only uart uartv2-5 csi0_dat[15:14] rxd/txd only usb usb-otg phy usb_h1_gpanaio usb_h1_rrefext usb_h1_dp usb_h1_dn usb_h1_vbus ? table 110. interfaces allocation during boot (continued) interface ip instance allocate d pads during boot comment
i.mx53xd applications processors for consumer products, rev. 2 150 freescale semiconductor package information and contact assignments 6 package information and contact assignments this section includes the contact assignment in formation and mechanical package drawing. 6.1 19x19 mm package information this section contains the outline drawing, signal assignment map, ground/po wer reference id (by ball grid location) for the 19 19 mm, 0.8 mm pitch package. 6.1.1 case tepbga-2, 19 x 19 mm, 0.8 mm pitch, 23 x 23 ball matrix figure 98 shows the top view of the 19 19 mm package, figure 99 shows the bottom view and the ball location (529 solder balls) of the 19 19 mm package, and figure 100 shows the side view of the 19 19 mm package. figure 98. 19 x 19 mm package top view
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 151 figure 99. 19 x 19 mm package, 529 solder balls, bottom view figure 100. 19 x 19 mm package side view
i.mx53xd applications processors for consumer products, rev. 2 152 freescale semiconductor package information and contact assignments the following notes apply to figure 98 , figure 99 , and figure 100 . 1. all dimensions are in millimeters. 2. dimensions and tolera ncing per asme y14.5m1?994. 6.1.2 19 x 19 mm signal assignments, power rails, and i/o table 111 shows the device connection li st for ground, power, sense, and reference co ntact signals. table 112 displays an alpha-sorted list of the signal ass ignments including associated power supplies. the table also includes out of reset pad state. table 113 shows the package ball map. 6.1.2.1 19 x 19 mm ground, power, sense, and reference contact assignments table 111 shows the device connection list for ground, power, sense, and refe rence contact signals alpha-sorted by name. table 111. 19 x 19 mm ground, power, sense, and reference contact assignments contact name package contact assignment(s) ddr_vref l17 gnd a1, a11, a13, a18, a2, a22, a23, aa11, aa15, aa20, aa21, ab1, ab18, ab2, ab22, ab23, ac1, ac18, ac2, ac22, ac23, b1, b11, b13, b18, b23, c12, c20, c21, d19, e19, f19, f20, f21, f22, g19, g7, h10, h12, h8, j11, j13, j15, j17, j20, j9, k10, k 12, k14, k16, k21, k8, l11, l13, l15, l7, l9, m10, m12, m14, m16, m8, n11, n13, n15, n9, p10, p12, p14, p16, p21, p7, p8, r11, r13, r15, r17, r20, r9, t 10, t14, t16, t8, u15, u19, v15, v18, v19, v20, v21, v22, w1 9, y14, y15, y19 nvcc_ckih g17 nvcc_csi r7 nvcc_eim_main u10, u9 nvcc_eim_sec u7 nvcc_emi_dram h18, k17, n17, p17, t18 nvcc_fec f11 nvcc_gpio f8 nvcc_jtag g9 nvcc_keypad f7 nvcc_lcd j6, j7 nvcc_lvds u13 nvcc_lvds_bg u14 nvcc_nandf t12 nvcc_pata n7 nvcc_reset h16 nvcc_sd1 h15
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 153 table 112 displays an alpha-sorted list of the signal assi gnments including power rails. the table also includes out of reset pad state. nvcc_sd2 h14 nvcc_srtc_pow v11 nvcc_xtal v12 svcc b22 svddgp b2 tvdac_ahvddrgb u17, v16 tvdac_dhvdd u16 usb_h1_vdda25 f13 usb_h1_vdda33 g13 usb_otg_vdda25 f14 usb_otg_vdda33 g14 vcc h13, j14, j16, k13, k15, l14, l16, m11, m13, m15, m9, n10, n12, n14, n16, n8, p11, p13, p15, p9, r10, r12, r14, r16, r8, t11, t13, t15, t17, t7, t9, u18, u8 vdda g12, m17, m7, u12 vddal1 f9 vdd_ana_pll g16 vdd_dig_pll h17 vdd_fuse g15 vddgp g10, g11, g8, h11, h7, h9, j10, j12, j8, k11, k7, k9, l10, l12, l8 vdd_reg g18 vp a15, b15 vph a9, b9 table 111. 19 x 19 mm ground, power, sense, and reference contact assignments (continued) contact name package contact assignment(s)
i.mx53xd applications processors for consumer products, rev. 2 154 freescale semiconductor package information and contact assignments table 112. 19 x 19 mm signal assignments, power rails, and i/o contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value boot_mode 0 c18 nvcc_reset lvio alt0 src src_boot_mod e[0] input 100 k pd boot_mode 1 b20 nvcc_reset lvio alt0 src src_boot_mod e[1] input 100 k pd ckih1 b21 nvcc_ckih analog alt0 camp- 1 camp1_ckih input analog ckih2 d18 nvcc_ckih analog alt0 camp- 2 camp2_ckih input analog ckil ab10 nvcc_srtc_pow analog ? srct ckil ? ? csi0_dat10 r5 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[28] input 100 k pu csi0_dat11 t2 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[29] input 100 k pu csi0_dat12 t3 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[30] input 360 k pd csi0_dat13 t6 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[31] input 360 k pd csi0_dat14 u1 nvcc_csi uhvio alt1 gpio-6 gpio6_gpio[0] input 360 k pd csi0_dat15 u2 nvcc_csi uhvio alt1 gpio-6 gpio6_gpio[1] input 360 k pd csi0_dat16 t4 nvcc_csi uhvio alt1 gpio-6 gpio6_gpio[2] input 360 k pd csi0_dat17 t5 nvcc_csi uhvio alt1 gpio-6 gpio6_gpio[3] input 360 k pd csi0_dat18 u3 nvcc_csi uhvio alt1 gpio-6 gpio6_gpio[4] input 360 k pd csi0_dat19 u4 nvcc_csi uhvio alt1 gpio-6 gpio6_gpio[5] input 360 k pd csi0_dat4 r1 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[22] input 100 k pu csi0_dat5 r2 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[23] input 360 k pd csi0_dat6 r6 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[24] input 100 k pu csi0_dat7 r3 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[25] input 100 k pu csi0_dat8 t1 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[26] input 100 k pu csi0_dat9 r4 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[27] input 360 k pd csi0_data_e n p3 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[20] input 100 k pu csi0_mclk p2 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[19] input 100 k pu csi0_pixclk p1 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[18] input 100 k pu csi0_vsync p4 nvcc_csi uhvio alt1 gpio-5 gpio5_gpio[21] input 100 k pu
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 155 di0_disp_cl k h4 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[16] input 100 k pu di0_pin15 e4 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[17] input 100 k pu di0_pin2 d3 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[18] input 100 k pu di0_pin3 c2 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[19] input 100 k pu di0_pin4 d2 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[20] input 100 k pu disp0_dat0 j5 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[21] input 100 k pd disp0_dat1 j4 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[22] input 100 k pd disp0_dat10 g3 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[31] input 100 k pu disp0_dat11 h5 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[5] input 100 k pd disp0_dat12 h1 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[6] input 100 k pu disp0_dat13 e1 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[7] input 100 k pu disp0_dat14 f2 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[8] input 100 k pu disp0_dat15 f3 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[9] input 100 k pu disp0_dat16 d1 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[10] input 100 k pu disp0_dat17 f5 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[11] input 100 k pu disp0_dat18 g4 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[12] input 100 k pu disp0_dat19 g5 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[13] input 100 k pu disp0_dat2 h2 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[23] input 100 k pd disp0_dat20 f4 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[14] input 100 k pu disp0_dat21 c1 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[15] input 100 k pu disp0_dat22 e3 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[16] input 100 k pu disp0_dat23 c3 nvcc_lcd gpio alt1 gpio-5 gpio5_gpio[17] input 100 k pu disp0_dat3 f1 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[24] input 100 k pd disp0_dat4 g2 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[25] input 100 k pd disp0_dat5 h3 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[26] input 100 k pd disp0_dat6 g1 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[27] input 100 k pd disp0_dat7 h6 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[28] input 100 k pd disp0_dat8 g6 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[29] input 100 k pu table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
i.mx53xd applications processors for consumer products, rev. 2 156 freescale semiconductor package information and contact assignments disp0_dat9 e2 nvcc_lcd gpio alt1 gpio-4 gpio4_gpio[30] input 100 k pu dram_a0 m19 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[0] output low dram_a1 l21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[1] output low dram_a10 k19 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[10 ] output low dram_a11 l22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[11 ] output low dram_a12 l20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[12 ] output low dram_a13 l23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[13 ] output low dram_a14 n18 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[14 ] output low dram_a15 m18 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[15 ] output low dram_a2 m20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[2] output low dram_a3 n20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[3] output low dram_a4 k20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[4] output low dram_a5 n21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[5] output low dram_a6 m22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[6] output low dram_a7 n22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[7] output low dram_a8 n23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[8] output low dram_a9 m21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_a[9] output low dram_calib ration m23 nvcc_emi_dram special ? ? (used in dram driver calibration. see special signal considerations {add xref} above) input ? dram_cas l18 nvcc_emi_dram ddr3 alt0 extmc emi_dram_cas output high dram_cs0 k18 nvcc_emi_dram ddr3 alt0 extmc emi_dram_cs[ 0] output high dram_cs1 p19 nvcc_emi_dram ddr3 alt0 extmc emi_dram_cs[ 1] output high table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 157 dram_d0 h20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[0] output high dram_d1 g21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[1] output high dram_d10 e22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[10 ] output high dram_d11 d20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[11 ] output high dram_d12 e23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[12 ] output high dram_d13 c23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[13 ] output high dram_d14 f23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[14 ] output high dram_d15 c22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[15 ] output high dram_d16 u20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[16 ] output high dram_d17 t21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[17 ] output high dram_d18 u21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[18 ] output high dram_d19 r21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[19 ] output high dram_d2 j21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[2] output high dram_d20 u23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[20 ] output high dram_d21 r22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[21 ] output high dram_d22 u22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[22 ] output high dram_d23 r23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[23 ] output high dram_d24 y20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[24 ] output high dram_d25 w21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[25 ] output high table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
i.mx53xd applications processors for consumer products, rev. 2 158 freescale semiconductor package information and contact assignments dram_d26 y21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[26 ] output high dram_d27 w22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[27 ] output high dram_d28 aa23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[28 ] output high dram_d29 v23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[29 ] output high dram_d3 g20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[3] output high dram_d30 aa22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[30 ] output high dram_d31 w23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[31 ] output high dram_d4 j23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[4] output high dram_d5 g23 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[5] output high dram_d6 j22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[6] output high dram_d7 g22 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[7] output high dram_d8 e21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[8] output high dram_d9 d21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_d[9] output high dram_dqm0 h21 nvcc_emi_dram ddr3 alt0 extmc emi_dram_dq m[0] output low dram_dqm1 e20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_dq m[1] output low dram_dqm2 t20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_dq m[2] output low dram_dqm3 w20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_dq m[3] output low dram_ras j19 nvcc_emi_dram ddr3 alt0 extmc emi_dram_ras output high dram_rese t p18 nvcc_emi_dram ddr3 alt0 extmc emi_dram_res et output low dram_sdba 0 r19 nvcc_emi_dram ddr3 alt0 extmc emi_dram_sdb a[0] output low dram_sdba 1 p20 nvcc_emi_dram ddr3 alt0 extmc emi_dram_sdb a[1] output low table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 159 dram_sdba 2 n19 nvcc_emi_dram ddr3 alt0 extmc emi_dram_sdb a[2] output low dram_sdck e0 h19 nvcc_emi_dram ddr3 alt0 extmc emi_dram_sdc ke[0] output low dram_sdck e1 t19 nvcc_emi_dram ddr3 alt0 extmc emi_dram_sdc ke[1] output low dram_sdcl k_0 k23 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdc lk0 output floating dram_sdcl k_0_b k22 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdc lk0_b output floating dram_sdcl k_1 p22 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdc lk1 output floating dram_sdcl k_1_b p23 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdc lk1_b output floating dram_sdod t0 j18 nvcc_emi_dram ddr3 alt0 extmc emi_dram_odt [0] output low dram_sdod t1 r18 nvcc_emi_dram ddr3 alt0 extmc emi_dram_odt [1] output low dram_sdqs 0 h23 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdq s[0] input low dram_sdqs 0_b h22 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdq s_b[0] input high dram_sdqs 1 d23 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdq s[1] input low dram_sdqs 1_b d22 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdq s_b[1] input high dram_sdqs 2 t22 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdq s[2] input low dram_sdqs 2_b t23 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdq s_b[2] input high dram_sdqs 3 y22 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdq s[3] input low dram_sdqs 3_b y23 nvcc_emi_dram ddr3clk alt0 extmc emi_dram_sdq s_b[3] input high dram_sdwe l19 nvcc_emi_dram ddr3 alt0 extmc emi_dram_sd we output high table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
i.mx53xd applications processors for consumer products, rev. 2 160 freescale semiconductor package information and contact assignments eckil ac10 nvcc_srtc_pow analog ? srtc eckil {no block i/o by this name in rm} ?? eim_a16 aa5 nvcc_eim_main uhvio alt0 extmc emi_eim_a[16] output 2 ? eim_a17 v7 nvcc_eim_main uhvio alt0 extmc emi_eim_a[17] output 2 ? eim_a18 ab3 nvcc_eim_main uhvio alt0 extmc emi_eim_a[18] output 2 ? eim_a19 w7 nvcc_eim_main uhvio alt0 extmc emi_eim_a[19] output 2 ? eim_a20 y6 nvcc_eim_main uhvio alt0 extmc emi_eim_a[20] output 2 ? eim_a21 aa4 nvcc_eim_main uhvio alt0 extmc emi_eim_a[21] output 2 ? eim_a22 aa3 nvcc_eim_main uhvio alt0 extmc emi_eim_a[22] output 2 ? eim_a23 v6 nvcc_eim_main uhvio al t0 extmc emi_eim_a[23] output ? eim_a24 y5 nvcc_eim_main uhvio al t0 extmc emi_eim_a[24] output ? eim_a25 w6 nvcc_eim_main uhvio al t0 extmc emi_eim_a[25] output ? eim_bclk w11 nvcc_eim_main uhvio alt0 extmc emi_eim_bclk output ? eim_cs0 w8 nvcc_eim_main uhvio alt0 extmc emi_eim_cs[0] output ? eim_cs1 y7 nvcc_eim_main uhvio alt0 extmc emi_eim_cs[1] output ? eim_d16 u6 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[16] input 100 k pu eim_d17 u5 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[17] input 100 k pu eim_d18 v1 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[18] input 100 k pu eim_d19 v2 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[19] input 100 k pu eim_d20 w1 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[20] input 100 k pu eim_d21 v3 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[21] input 100 k pu eim_d22 w2 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[22] input 360 k pd eim_d23 y1 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[23] input 100 k pu eim_d24 y2 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[24] input 100 k pu eim_d25 w3 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[25] input 100 k pu eim_d26 v5 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[26] input 100 k pu eim_d27 v4 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[27] input 100 k pu eim_d28 aa1 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[28] input 100 k pu eim_d29 aa2 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[29] input 100 k pu table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 161 eim_d30 w4 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[30] input 100 k pu eim_d31 w5 nvcc_eim_sec uhvio alt1 gpio-3 gpio3_gpio[31] input 360 k pd eim_da0 y8 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[0] input 2 100 k pu eim_da1 ac4 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[1] input 2 100 k pu eim_da10 ab7 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[10] input 2 100 k pu eim_da11 ac6 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[11] input 100 k pu eim_da12 v10 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[12] input 100 k pu eim_da13 ac7 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[13] input 100 k pu eim_da14 y10 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[14] input 100 k pu eim_da15 aa9 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[15] input 100 k pu eim_da2 aa7 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[2] input 2 100 k pu eim_da3 w9 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[3] input 2 100 k pu eim_da4 ab6 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[4] input 2 100 k pu eim_da5 v9 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[5] input 2 100 k pu eim_da6 y9 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[6] input 2 100 k pu eim_da7 ac5 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[7] input 2 100 k pu eim_da8 aa8 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[8] input 2 100 k pu eim_da9 w10 nvcc_eim_main uhvio alt0 extmc emi_nand_eim _da[9] input 2 100 k pu eim_eb0 ac3 nvcc_eim_main uhvio alt0 extmc emi_eim_eb[0] output 2 ? table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
i.mx53xd applications processors for consumer products, rev. 2 162 freescale semiconductor package information and contact assignments eim_eb1 ab5 nvcc_eim_main uhvio al t0 extmc emi_eim_eb[1] output 2 ? eim_eb2 y3 nvcc_eim_main uhvio alt1 gpio-2 gpio2_gpio[30] input 100 k pu eim_eb3 y4 nvcc_eim_main uhvio alt1 gpio-2 gpio2_gpio[31] input 100 k pu eim_lba aa6 nvcc_eim_main uhvio alt0 extmc emi_eim_lba output 2 ? eim_oe v8 nvcc_eim_main uhvio al t0 extmc emi_eim_oe output ? eim_rw ab4 nvcc_eim_main uhvio alt0 extmc emi_eim_rw output ? eim_wait ab9 nvcc_eim_main uhvio al t0 extmc emi_eim_wait output ? extal ab11 nvcc_xtal analog ? extal osc extal ? ? fastr_ana e18 nvcc_ckih analog ? ? (reserved, tie to ground) ?? fastr_dig e17 nvcc_ckih analog ? ? (reserved, tie to ground) ?? fec_crs_dv d11 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[25] input 100 k pu fec_mdc e10 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[31] input 100 k pu fec_mdio d12 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[22] input 100 k pu fec_ref_cl k e12 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[23] input 100 k pu fec_rx_er f12 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[24] input 100 k pu fec_rxd0 c11 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[27] input 100 k pu fec_rxd1 e11 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[26] input 100 k pu fec_tx_en c10 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[28] input 360 k pd fec_txd0 f10 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[30] input 100 k pu fec_txd1 d10 nvcc_fec uhvio alt1 gpio-1 gpio1_gpio[29] input 100 k pu gpio_0 c8 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[0] input 360 k pd gpio_1 b7 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[1] input 360 k pd gpio_10 w16 tvdac_ahvddrg b gpio alt0 gpio-4 gpio4_gpio[0] input 100 k pu gpio_11 v17 tvdac_ahvddrg b gpio alt0 gpio-4 gpio4_gpio[1] input 100 k pu gpio_12 w17 tvdac_ahvddrg b gpio alt0 gpio-4 gpio4_gpio[2] input 100 k pu table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 163 gpio_13 aa18 tvdac_ahvddrg b gpio alt0 gpio-4 gpio4_gpio[3] input 100 k pu gpio_14 w18 tvdac_ahvddrg b gpio alt0 gpio-4 gpio4_gpio[4] input 100 k pu gpio_16 c6 nvcc_gpio uhvio alt1 gpio-7 gpio7_gpio[11] input 360 k pd gpio_17 a3 nvcc_gpio uhvio alt1 gpio-7 gpio7_gpio[12] input 360 k pd gpio_18 d7 nvcc_gpio uhvio alt1 gpio-7 gpio7_gpio[13] input 360 k pd gpio_19 b4 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[5] input 3 100 k pu gpio_2 c7 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[2] input 360 k pd gpio_3 a6 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[3] input 360 k pd gpio_4 d8 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[4] input 100 k pu gpio_5 a5 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[5] input 360 k pd gpio_6 b6 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[6] input 360 k pd gpio_7 a4 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[7] input 360 k pd gpio_8 b5 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[8] input 360 k pd gpio_9 e8 nvcc_gpio uhvio alt1 gpio-1 gpio1_gpio[9] input 100 k pu jtag_mod c9 nvcc_jtag gpio alt0 sjc sjc_mod input 100 k pu jtag_tck d9 nvcc_jtag gpio alt0 sjc sjc_tck input 100 k pd jtag_tdi b8 nvcc_jtag gpio alt0 sjc sjc_tdi input 47 k pu jtag_tdo a7 nvcc_jtag gpio alt0 sjc sjc_tdo input keeper jtag_tms a8 nvcc_jtag gpio alt0 sjc sjc_tms input 47 k pu jtag_trstb e9 nvcc_jtag gpio alt0 sjc sjc_trstb input 47 k pu key_col0 c5 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[6] input 4 100 k pu key_col1 e7 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[8] input 100 k pu key_col2 c4 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[10] input 100 k pu key_col3 f6 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[12] input 100 k pu key_col4 e5 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[14] input 100 k pu key_row0 b3 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[7] input 360 k pd key_row1 d6 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[9] input 100 k pu key_row2 d5 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[11] input 100 k pu table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
i.mx53xd applications processors for consumer products, rev. 2 164 freescale semiconductor package information and contact assignments key_row3 d4 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[13] input 100 k pu key_row4 e6 nvcc_keypad uhvio alt1 gpio-4 gpio4_gpio[15] input 360 k pd lvds_bg_re s aa14 nvcc_lvds_bg analog ? ldb lvds_bg_res ? ? lvds0_clk_ n ab16 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[25] input floating lvds0_clk_ p ac16 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[24] input floating lvds0_tx0_ n y17 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[31] input floating lvds0_tx0_p aa17 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[30] input floating lvds0_tx1_ n ab17 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[29] input floating lvds0_tx1_p ac17 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[28] input floating lvds0_tx2_ n y16 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[27] input floating lvds0_tx2_p aa16 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[26] input floating lvds0_tx3_ n ab15 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[23] input floating lvds0_tx3_p ac15 nvcc_lvds lvds alt0 gpio-7 gpio7_gpi[22] input floating lvds1_clk_ n aa13 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[27] input floating lvds1_clk_ p y13 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[26] input floating lvds1_tx0_ n ac14 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[31] input floating lvds1_tx0_p ab14 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[30] input floating lvds1_tx1_ n ac13 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[29] input floating lvds1_tx1_p ab13 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[28] input floating lvds1_tx2_ n ac12 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[25] input floating lvds1_tx2_p ab12 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[24] input floating table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 165 lvds1_tx3_ n aa12 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[23] input floating lvds1_tx3_p y12 nvcc_lvds lvds alt0 gpio-6 gpio6_gpi[22] input floating nandf_ale y11 nvcc_nandf uhvio alt1 gpio-6 gpio6_gpio[8] input 100 k pu nandf_cle aa10 nvcc_nandf uhvio alt1 gpio-6 gpio6_gpio[7] input 100 k pu nandf_cs0 w12 nvcc_nandf uhvio alt1 gpio-6 gpio6_gpio[11] input 100 k pu nandf_cs1 v13 nvcc_nandf uhvio alt1 gpio-6 gpio6_gpio[14] input 100 k pu nandf_cs2 v14 nvcc_nandf uhvio alt1 gpio-6 gpio6_gpio[15] input 100 k pu nandf_cs3 w13 nvcc_nandf uhvio alt1 gpio-6 gpio6_gpio[16] input 100 k pu nandf_rb0 u11 nvcc_nandf uhvio alt1 gpio-6 gpio6_gpio[10] input 100 k pu nandf_re_b ac8 nvcc_eim_main uhvio alt1 gpio-6 gpio6_gpio[13] input 100 k pu nandf_we_ b ab8 nvcc_eim_main uhvio alt1 gpio-6 gpio6_gpio[12] input 100 k pu nandf_wp_ b ac9 nvcc_nandf uhvio alt1 gpio-6 gpio6_gpio[9] input 100 k pu pata _ b u f f e r_en k4 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[1] input 100 k pu pata_cs_0 l5 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[9] input 100 k pu pata_cs_1 l2 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[10] input 100 k pu pata_da_0 k6 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[6] input 100 k pu pata_da_1 l3 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[7] input 100 k pu pata_da_2 l4 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[8] input 100 k pu pata_data0 l1 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[0] input 100 k pu pata_data1 m1 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[1] input 100 k pu pata_data10 n4 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[10] input 100 k pu pata_data11 m6 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[11] input 100 k pu pata_data12 n5 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[12] input 100 k pu pata_data13 n6 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[13] input 100 k pu pata_data14 p6 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[14] input 100 k pu pata_data15 p5 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[15] input 100 k pu table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
i.mx53xd applications processors for consumer products, rev. 2 166 freescale semiconductor package information and contact assignments pata_data2 l6 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[2] input 100 k pu pata_data3 m2 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[3] input 100 k pu pata_data4 m3 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[4] input 100 k pu pata_data5 m4 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[5] input 100 k pu pata_data6 n1 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[6] input 100 k pu pata_data7 m5 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[7] input 100 k pu pata_data8 n2 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[8] input 100 k pu pata_data9 n3 nvcc_pata uhvio alt1 gpio-2 gpio2_gpio[9] input 100 k pu pata_dior k3 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[3] input 100 k pu pata_diow j3 nvcc_pata uhvio alt1 gpio-6 gpio6_gpio[17] input 100 k pu pata_dmack j2 nvcc_pata uhvio alt1 gpio-6 gpio6_gpio[18] input 100 k pu pata_dmarq j1 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[0] input 100 k pu pata_intrq k5 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[2] input 100 k pu pata_iordy k1 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[5] input 100 k pu pata _ r e s e t _b k2 nvcc_pata uhvio alt1 gpio-7 gpio7_gpio[4] input 100 k pu pmic_on_re q w14 nvcc_srtc_pow gpio alt0 srtc srtc_srtcalar m output ? pmic_stby_ req w15 nvcc_srtc_pow gpio alt0 ccm ccm_pmic_vst by_req output ? por_b c19 nvcc_reset lvio alt0 src src_por_b input 100 k pu reset_in_b a21 nvcc_reset lvio alt0 src src_reset_b input 100 k pu sata_refcl km a14 vph analog ? sata sata_refclkm ? ? sata_refcl kp b14 vph analog ? sata sata_refclkp ? ? sata_rext c13 vph analog ? sata sata_rext ? ? sata_rxm a12 vph analog ? sata sata_rxm ? ? sata_rxp b12 vph analog ? sata sata_rxp ? ? sata_txm b10 vph analog ? sata sata_txm ? ? sata_txp a10 vph analog ? sata sata_txp ? ? table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 167 sd1_clk e16 nvcc_sd1 uhvio alt1 gpio-1 gpio1_gpio[20] input 100 k pu sd1_cmd f18 nvcc_sd1 uhvio alt1 gpio-1 gpio1_gpio[18] input 100 k pu sd1_data0 a20 nvcc_sd1 uhvio alt1 gpio-1 gpio1_gpio[16] input 100 k pu sd1_data1 c17 nvcc_sd1 uhvio alt1 gpio-1 gpio1_gpio[17] input 100 k pu sd1_data2 f17 nvcc_sd1 uhvio alt1 gpio-1 gpio1_gpio[19] input 100 k pu sd1_data3 f16 nvcc_sd1 uhvio alt1 gpio-1 gpio1_gpio[21] input 100 k pu sd2_clk e14 nvcc_sd2 uhvio alt1 gpio-1 gpio1_gpio[10] input 100 k pu sd2_cmd c15 nvcc_sd2 uhvio alt1 gpio-1 gpio1_gpio[11] input 100 k pu sd2_data0 d13 nvcc_sd2 uhvio alt1 gpio-1 gpio1_gpio[15] input 100 k pu sd2_data1 c14 nvcc_sd2 uhvio alt1 gpio-1 gpio1_gpio[14] input 100 k pu sd2_data2 d14 nvcc_sd2 uhvio alt1 gpio-1 gpio1_gpio[13] input 100 k pu sd2_data3 e13 nvcc_sd2 uhvio alt1 gpio-1 gpio1_gpio[12] input 100 k pu test_mode d17 nvcc_reset lvio alt0 tcu_test_mod e input 100 k pd tvcdc_iob_ back ab19 tvdac_ahvddrg b analog ? tve tvcdc_iob_ba ck ?? tvcdc_iog_ back ac20 tvdac_ahvddrg b analog ? tve tvcdc_iog_ba ck ?? tvcdc_ior_ back ab21 tvdac_ahvddrg b analog ? tve tvcdc_ior_ba ck ?? tvdac_com p aa19 tvdac_ahvddrg b analog ? tve tvdac_comp ? ? tvdac_iob ac19 tvdac_ahvddrg b analog ? tve tvdac_iob ? ? tvdac_iog ab20 tvdac_ahvddrg b analog ? tve tvdac_iog ? ? tvdac_ior ac21 tvdac_ahvddrg b analog ? tve tvdac_ior ? ? tvdac_vref y18 tvdac_ahvddrg b analog ? tve tvdac_vref ? ? usb_h1_dn b17 usb_h1_vdda25, usb_h1_vdda33 analog50 ? usb usb_h1_dn ? ? table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
i.mx53xd applications processors for consumer products, rev. 2 168 freescale semiconductor package information and contact assignments note key_col0 and gpio_19 act as output for diagnostic signals during power-on reset. usb_h1_dp a17 usb_h1_vdda25, usb_h1_vdda33 analog50 ? usb usb_h1_dp ? ? usb_h1_gpa naio a16 usb_h1_vdda25, usb_h1_vdda33 analog25 ? usb usb_h1_gpana io ?? usb_h1_rre fext b16 usb_h1_vdda25, usb_h1_vdda33 analog25 ? usb usb_h1_rrefe xt ?? usb_h1_vbu s d15 usb_h1_vdda25, usb_h1_vdda33 analog50 ? usb usb_h1_vbus ? ? usb_otg_d n a19 usb_otg_vdda25, usb_otg_vdda33 analog50 ? usb usb_otg_dn ? ? usb_otg_dp b19 usb_otg_vdda25, usb_otg_vdda33 analog50 ? usb usb_otg_dp ? ? usb_otg_g pa n a i o f15 usb_otg_vdda25, usb_otg_vdda33 analog25 ? usb usb_otg_gpa naio ?? usb_otg_id c16 usb_otg_vdda25, usb_otg_vdda33 analog25 ? usb usb_otg_id ? ? usb_otg_r refext d16 usb_otg_vdda25, usb_otg_vdda33 analog25 ? usb usb_otg_rre fext ?? usb_otg_vb us e15 usb_otg_vdda25, usb_otg_vdda33 analog50 ? usb usb_otg_vbu s ?? xtal ac11 nvcc_xtal analog ? xtalo sc xtal ? ? 1 the state immediately after reset and before rom firmware or software has executed. 2 during power-on reset, this port acts as input for fuse override. see section 5.1, ?boot mode configuration pins? for details. for appropriate resistor values, see chapter 1 of i.mx53 s ystem development user's guide, document number mx53ug. 3 during power-on reset this port acts as output for diagnostic signal int_boot 4 during power-on reset this port acts as output for diagnostic signal any_pu_rst table 112. 19 x 19 mm signal assignments, power rails, and i/o (continued) contact name package contact assign ment power rail i/o buffer type out of reset condition 1 alt. mode block instance block i/o direction config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 169 6.2 19 x 19 mm, 0.8 pitch ball map table 113 shows the 19 19 mm, 0.8 pitch ball map. table 113. 19 x 19 mm, 0.8 pitch ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a gnd gnd gpio_17 gpio_7 gpio_5 gpio_3 jtag_tdo jtag_tms vph sata_txp gnd sata_rxm gnd sata_refclkm vp usb_h1_gpanaio usb_h1_dp gnd usb_otg_dn sd1_data0 reset_in_b gnd gnd a b gnd svddgp key_row0 gpio_19 gpio_8 gpio_6 gpio_1 jtag_tdi vph sata_txm gnd sata_rxp gnd sata_refclkp vp usb_h1_rrefext usb_h1_dn gnd usb_otg_dp boot_mode1 ckih1 svcc gnd b c disp0_dat21 di0_pin3 disp0_dat23 key_col2 key_col0 gpio_16 gpio_2 gpio_0 jtag_mod fec_tx_en fec_rxd0 gnd sata_rext sd2_data1 sd2_cmd usb_otg_id sd1_data1 boot_mode0 por_b gnd gnd dram_d15 dram_d13 c d disp0_dat16 di0_pin4 di0_pin2 key_row3 key_row2 key_row1 gpio_18 gpio_4 jtag_tck fec_txd1 fec_crs_dv fec_mdio sd2_data0 sd2_data2 usb_h1_vbus usb_otg_rrefext test_mode ckih2 gnd dram_d11 dram_d9 dram_sdqs1_b dram_sdqs1 d e disp0_dat13 disp0_dat9 disp0_dat22 di0_pin15 key_col4 key_row4 key_col1 gpio_9 jtag_trstb fec_mdc fec_rxd1 fec_ref_clk sd2_data3 sd2_clk usb_otg_vbus sd1_clk fastr_dig fastr_ana gnd dram_dqm1 dram_d8 dram_d10 dram_d12 e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
i.mx53xd applications processors for consumer products, rev. 2 170 freescale semiconductor package information and contact assignments f disp0_dat3 disp0_dat14 disp0_dat15 disp0_dat20 disp0_dat17 key_col3 nvcc_keypad nvcc_gpio vddal1 fec_txd0 nvcc_fec fec_rx_er usb_h1_vdda25 usb_otg_vdda25 usb_otg_gpanaio sd1_data3 sd1_data2 sd1_cmd gnd gnd gnd gnd dram_d14 f g disp0_dat6 disp0_dat4 disp0_dat10 disp0_dat18 disp0_dat19 disp0_dat8 gnd vddgp nvcc_jtag vddgp vddgp vdda usb_h1_vdda33 usb_otg_vdda33 vdd_fuse vdd_ana_pll nvcc_ckih vdd_reg gnd dram_d3 dram_d1 dram_d7 dram_d5 g h disp0_dat12 disp0_dat2 disp0_dat5 di0_disp_clk disp0_dat11 disp0_dat7 vddgp gnd vddgp gnd vddgp gnd vcc nvcc_sd2 nvcc_sd1 nvcc_reset vdd_dig_pll nvcc_emi_dram dram_sdcke0 dram_d0 dram_dqm0 dram_sdqs0_b dram_sdqs0 h j pata_dmarq pata _ d m ac k pata _ d i ow disp0_dat1 disp0_dat0 nvcc_lcd nvcc_lcd vddgp gnd vddgp gnd vddgp gnd vcc gnd vcc gnd dram_sdodt0 dram_ras gnd dram_d2 dram_d6 dram_d4 j k pata _ i o r dy pata_reset_b pata _ d i o r pata _ b u f f e r _ e n pata_intrq pata _ da _ 0 vddgp gnd vddgp gnd vddgp gnd vcc gnd vcc gnd nvcc_emi_dram dram_cs0 dram_a10 dram_a4 gnd dram_sdclk_0_b dram_sdclk_0 k l pata _ data 0 pata _ c s _ 1 pata _ da _ 1 pata _ da _ 2 pata _ c s _ 0 pata _ data 2 gnd vddgp gnd vddgp gnd vddgp gnd vcc gnd vcc ddr_vref dram_cas dram_sdwe dram_a12 dram_a1 dram_a11 dram_a13 l table 113. 19 x 19 mm, 0.8 pitch ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 171 m pata _ data 1 pata _ data 3 pata _ data 4 pata _ data 5 pata _ data 7 pata _ data 1 1 vdda gnd vcc gnd vcc gnd vcc gnd vcc gnd vdda dram_a15 dram_a0 dram_a2 dram_a9 dram_a6 dram_calibration m n pata _ data 6 pata _ data 8 pata _ data 9 pata _ data 1 0 pata _ data 1 2 pata _ data 1 3 nvcc_pata vcc gnd vcc gnd vcc gnd vcc gnd vcc nvcc_emi_dram dram_a14 dram_sdba2 dram_a3 dram_a5 dram_a7 dram_a8 n p csi0_pixclk csi0_mclk csi0_data_en csi0_vsync pata _ data 1 5 pata _ data 1 4 gnd gnd vcc gnd vcc gnd vcc gnd vcc gnd nvcc_emi_dram dram_reset dram_cs1 dram_sdba1 gnd dram_sdclk_1 dram_sdclk_1_b p r csi0_dat4 csi0_dat5 csi0_dat7 csi0_dat9 csi0_dat10 csi0_dat6 nvcc_csi vcc gnd vcc gnd vcc gnd vcc gnd vcc gnd dram_sdodt1 dram_sdba0 gnd dram_d19 dram_d21 dram_d23 r t csi0_dat8 csi0_dat11 csi0_dat12 csi0_dat16 csi0_dat17 csi0_dat13 vcc gnd vcc gnd vcc nvcc_nandf vcc gnd vcc gnd vcc nvcc_emi_dram dram_sdcke1 dram_dqm2 dram_d17 dram_sdqs2 dram_sdqs2_b t u csi0_dat14 csi0_dat15 csi0_dat18 csi0_dat19 eim_d17 eim_d16 nvcc_eim_sec vcc nvcc_eim_main nvcc_eim_main nandf_rb0 vdda nvcc_lvds nvcc_lvds_bg gnd tvdac_dhvdd tvdac_ahvddrgb vcc gnd dram_d16 dram_d18 dram_d22 dram_d20 u table 113. 19 x 19 mm, 0.8 pitch ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
i.mx53xd applications processors for consumer products, rev. 2 172 freescale semiconductor package information and contact assignments v eim_d18 eim_d19 eim_d21 eim_d27 eim_d26 eim_a23 eim_a17 eim_oe eim_da5 eim_da12 nvcc_srtc_pow nvcc_xtal nandf_cs1 nandf_cs2 gnd tvdac_ahvddrgb gpio_11 gnd gnd gnd gnd gnd dram_d29 v w eim_d20 eim_d22 eim_d25 eim_d30 eim_d31 eim_a25 eim_a19 eim_cs0 eim_da3 eim_da9 eim_bclk nandf_cs0 nandf_cs3 pmic_on_req pmic_stby_req gpio_10 gpio_12 gpio_14 gnd dram_dqm3 dram_d25 dram_d27 dram_d31 w y eim_d23 eim_d24 eim_eb2 eim_eb3 eim_a24 eim_a20 eim_cs1 eim_da0 eim_da6 eim_da14 nandf_ale lvds1_tx3_p lvds1_clk_p gnd gnd lvds0_tx2_n lvds0_tx0_n tvdac_vref gnd dram_d24 dram_d26 dram_sdqs3 dram_sdqs3_b y aa eim_d28 eim_d29 eim_a22 eim_a21 eim_a16 eim_lba eim_da2 eim_da8 eim_da15 nandf_cle gnd lvds1_tx3_n lvds1_clk_n lvds_bg_res gnd lvds0_tx2_p lvds0_tx0_p gpio_13 tvdac_comp gnd gnd dram_d30 dram_d28 aa ab gnd gnd eim_a18 eim_rw eim_eb1 eim_da4 eim_da10 nandf_we_b eim_wait ckil extal lvds1_tx2_p lvds1_tx1_p lvds1_tx0_p lvds0_tx3_n lvds0_clk_n lvds0_tx1_n gnd tvcdc_iob_back tvdac_iog tvcdc_ior_back gnd gnd ab ac gnd gnd eim_eb0 eim_da1 eim_da7 eim_da11 eim_da13 nandf_re_b nandf_wp_b eckil xtal lvds1_tx2_n lvds1_tx1_n lvds1_tx0_n lvds0_tx3_p lvds0_clk_p lvds0_tx1_p gnd tvdac_iob tvcdc_iog_back tvdac_ior gnd gnd ac table 113. 19 x 19 mm, 0.8 pitch ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 173 6.3 pop 12 x 12 mm package on package (pop) information this section contains the outline drawing, signal assignment map, ground/po wer reference id (by ball grid location) for the 12 x 12 mm, 0.4 mm pitch pop package. 6.3.1 case pop, 0.4 mm pitch, 12 x 12 ball matrix figure 101. 12x12 mm pop top view
i.mx53xd applications processors for consumer products, rev. 2 174 freescale semiconductor package information and contact assignments figure 102. 12 x 12 mm pop, bottom view
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 175 figure 103. 12 x 12 mm pop, side view the following notes apply to figure 101 , figure 102 , and figure 103 . 1 all dimensions are in millimeters. 2 dimensions and tolerancing per asme y14.5m ? 1994. 3 terminal position designat ion per jesd 95-1, spp-010 4 compliant to jesd 95-1 design guide 4.22, no exac t variation, and with exception to dimension ?a? 5 raw solder ball size during assembly is 0.25mm 6.3.2 12x 12 pop signal assignments, power rails, and i/o table 114 and table 115 show the device connection list for gr ound, power, sense, and reference contact signals. table 118 displays an alpha-sorted list of the signal ass ignments including associated power supplies. the table also includes out of reset pad state. table 119 and table 120 show the package ball maps.
i.mx53xd applications processors for consumer products, rev. 2 176 freescale semiconductor package information and contact assignments 6.3.2.1 12 x 12 mm pop ground, power, sense, and reference contact assignments table 114 and table 115 show the device connecti on list for ground, power, sen se, and reference contact signals alpha-sorted by name. table 114. 12 x 12 mm pop bottom ground, power, sense, and reference contact assignments contact name contact assignment ddr_vref u23 gnd a1, a2, a28, a29, b1, b2, b28, b29, c17, l1 4, l15, l16, m14, m15, m16, n14, n15, n16, p11,p12, p13, p17, p18, p19, r11, r12, r13, r17, r18, r19, t11, t12, t13, t17, t18, t19, u14, u15, u16, v14, v15, v16, w14,w15, w16, ah 1, ah15, ah29, aj 1, aj2, aj15, aj28, aj29 nvcc_ckih ad22 nvcc_csi j6 nvcc_eim_main g9 nvcc_eim_sec g6 nvcc_emi_dram f24, g24, h24, k24, l24, n24, p24, r24, u24, v24, w24, ac24, ad24 nvcc_emi_dram_2p5 k23,y24 nvcc_fec ac14 nvcc_gpio ad9 nvcc_jtag ad11 nvcc_keypad ad6 nvcc_lcd w7, y7 nvcc_lvds f19 nvcc_lvds_bg f18 nvcc_nandf g12 nvcc_pata n6 nvcc_reset ad18 nvcc_sd1 ac20 nvcc_sd2 ac16 nvcc_srtc_pow f13 nvcc_xtal f14 pop_vacc ag14 pop_vccmm c8, l3 pop_vccqmm c11 pop_vccqmm1 h3 pop_vdd1 c3, c13, c26, t3, t27, ag6, ag26
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 177 pop_vdd2 c14, c27, d3, p27, w3, af3, ag12, ag27 pop_vddca aa3, ad3, ag10 pop_vddmm ag13 pop_vddq c16, c20, c24, e27, j27, n27, w27, ab27, af27, ag16, ag20, ag24 pop_zq u3 svcc ah28 svddgp ah2 tvdac_ahvddrgb g22, g23 tvdac_dhvdd f23 tvdac_vref a27 usb_h1_vdda25 ad19 usb_h1_vdda33 ac18 usb_otg_vdda25 ac19 usb_otg_vdda33 ad20 vcc l11, l12, l13, l17, l18, l19, m11, m12, m13, m17, m18, m19, n11, n12, n13, n17, n18, n19, u17, u18, u19, v17, v18,v19, w17, w18, w19 vdd_ana_pll ac22 vdd_dig_pll ac23 vdd_fuse ac21 vdd_reg ad23 vdda f16, m6, r6, t24, ad14 vddal1 ac8 vddgp u11, u12, u13, v11, v12, v13, w11, w12, w13 vp ah19, aj19 vph ah13, aj13 table 115. 12 x 12 mm pop top ground, power, sense, and reference contact assignments contact name contact assignment ddr_vref p2, m22 gnd a12, a15, a18, a21, b5, b8, b10, c1, c23, f2, f23, j2, j 23, m2, m23, p23, r1, u23, v1, y23,aa1, ab7, ab11, ac5, ac9, ac12, ac15, ac18, ac21 pop_vacc ac11 table 114. 12 x 12 mm pop bottom ground, power, sense, and reference contact assignments (continued) contact name contact assignment
i.mx53xd applications processors for consumer products, rev. 2 178 freescale semiconductor package information and contact assignments 6.3.2.2 pop memory support and signal cross reference support is provided for 8- and 16-bit mlc nand flash mounted on the top of the package. to ensure jesd209 compliance, dedicated p cb connections ar e required per table 116 . with nand flash selected as the boot source, nandf_cle a nd the eim signals are configured as outputs. the pata signals are configured as inputs with weak pul l-ups (default) which allows the nandf_cle and the eim signals to drive them. note that the 16-bit nand flash is on the eim bus only. eim_da[4:7] and eim_da[12:15] are assigned to top balls and require no pcb connections. pop_vccmm a6, j1 pop_vccqmm a9 pop_vccqmm1 f1 pop_vdd1 a11, a20, b3, n2, n22,ab5, ac20 pop_vdd2 b11, b21, c2, l22, r2, aa2, ab10, ab21 pop_vddca u2, w2, ac8 pop_vddmm ac10 pop_vddq b13, b16, b19, d22, g22, k22, r22, v22, aa22, ab13, ab16, ab19 pop_zq p1 table 116. additional pcb conne ctions for pop nand flash suggested pcb net name first i.mx53 i/o on net second i.mx53 i/o on net associated top ball required for 8-bit nand flash? required for 16-bit nand flash? nandf_cle nandf_cle pata _ da _ 0 pata _ da _ 0 ye s ye s nandf_d0 eim_da10 pata _ data 0 pata _ data 0 ye s ye s nandf_d1 eim_da2 pata _ data 1 pata _ data 1 ye s ye s nandf_d2 eim_da11 pata _ data 2 pata _ data 2 ye s ye s nandf_d3 eim_da3 pata _ data 3 pata _ data 3 ye s ye s nandf_d8 eim_da8 pata _ data 8 pata _ data 8 no ye s nandf_d9 eim_da0 pata _ data 9 pata _ data 9 no ye s nandf_d10 eim_da9 pata _ data 1 0 pata _ data 1 0 no ye s nandf_d11 eim_da1 pata _ data 1 1 pata _ data 1 1 no ye s table 115. 12 x 12 mm pop top ground, power, sense, and reference contact assignments (continued) contact name contact assignment
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 179 to support emmc per the jesd 209 option, top ball signals per table 117 are provided. iomux mode alt2 is invoked for these i/o. i.mx53 pop supports 16- and 32-bit lpddr2-800 per jesd209 with no additional pcb digital signal connections. no signal cross reference is needed. the designer must ensure that the pcb routes power to pop_vdd1, pop_vdd2, pop_vddq, pop_ vddca, pop_vacc, and pop_vccqmm, pop_vccmm, and pop_vddmm. appr opriate discrete components mu st be employed for pop_zq, dram_calibration, ddr_vref, and pop_vccqmm1. 6.3.2.3 pop 12 x 12 mm, signal assignments, power rails, and i/o table 118 displays an alpha-sorted list of the signal assi gnments including power rails. the table also includes out of reset pad state. table 117. additional top ball connections for pop emmc emmc signal on port esdhc3 associated top ball rst pata _ da 0 clk pata _ i o r dy cmd pata_resetb table 118. pop 12 x 12 mm signal assignments, power rails, and i/o contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value boot_mode0 aa28 ? nvcc_reset lvio alt0 src_boot_mode[0 ] input 100 k pd boot_mode1 ab29 ? nvcc_reset lvio alt0 src_boot_mode[1 ] input 100 k pd ckih1 ac29 ? nvcc_ckih analog alt0 camp1_ckih input analog ckih2 ac28 ? nvcc_ckih analog alt0 camp2_ckih input analog ckil g13 ? nvcc_srtc_pow analog ? ckil ? ? csi0_dat10 r2 ? nvcc_csi uhvio alt1 gpio5_gpio[28] input 100 k pu csi0_dat11 r7 ? nvcc_csi uhvio alt1 gpio5_gpio[29] input 100 k pu csi0_dat12 u1 ? nvcc_csi uhvio alt1 gpio5_gpio[30] input 360 k pd csi0_dat13 r1 ? nvcc_csi uhvio alt1 gpio5_gpio[31] input 360 k pd csi0_dat14 t1 ? nvcc_csi uhvio alt1 gpio6_gpio[0] input 360 k pd csi0_dat15 p1 ? nvcc_csi uhvio alt1 gpio6_gpio[1] input 360 k pd
i.mx53xd applications processors for consumer products, rev. 2 180 freescale semiconductor package information and contact assignments csi0_dat16 m1 ? nvcc_csi uhvio alt1 gpio6_gpio[2] input 360 k pd csi0_dat17 n1 ? nvcc_csi uhvio alt1 gpio6_gpio[3] input 360 k pd csi0_dat18 l2 ? nvcc_csi uhvio alt1 gpio6_gpio[4] input 360 k pd csi0_dat19 l1 ? nvcc_csi uhvio alt1 gpio6_gpio[5] input 360 k pd csi0_dat4 t7 ? nvcc_csi uhvio alt1 gpio5_gpio[22] input 100 k pu csi0_dat5 r3 ? nvcc_csi uhvio alt1 gpio5_gpio[23] input 360 k pd csi0_dat6 p7 ? nvcc_csi uhvio alt1 gpio5_gpio[24] input 100 k pu csi0_dat7 n7 ? nvcc_csi uhvio alt1 gpio5_gpio[25] input 100 k pu csi0_dat8 u2 ? nvcc_csi uhvio alt1 gpio5_gpio[26] input 100 k pu csi0_dat9 p3 ? nvcc_csi uhvio alt1 gpio5_gpio[27] input 360 k pd csi0_data_en p6 ? nvcc_csi uhvio alt1 gpio5_gpio[20] input 100 k pu csi0_mclk t6 ? nvcc_csi uhvio alt1 gpio5_gpio[19] input 100 k pu csi0_pixclk u6 ? nvcc_csi uhvio alt1 gpio5_gpio[18] input 100 k pu csi0_vsync u7 ? nvcc_csi uhvio alt1 gpio5_gpio[21] input 100 k pu di0_disp_clk af2 ? nvcc_lcd gpio alt1 gpio4_gpio[16] input 100 k pu di0_pin15 ah6 ? nvcc_lcd gpio alt1 gpio4_gpio[17] input 100 k pu di0_pin2 ad7 ? nvcc_lcd gpio alt1 gpio4_gpio[18] input 100 k pu di0_pin3 ac7 ? nvcc_lcd gpio alt1 gpio4_gpio[19] input 100 k pu di0_pin4 ac6 ? nvcc_lcd gpio alt1 gpio4_gpio[20] input 100 k pu disp0_dat0 ad1 ? nvcc_lcd gpio alt1 gpio4_gpio[21] input 100 k pd disp0_dat1 ac3 ? nvcc_lcd gpio alt1 gpio4_gpio[22] input 100 k pd disp0_dat10 ag2 ? nvcc_lcd gpio alt1 gpio4_gpio[31] input 100 k pu disp0_dat11 ae3 ? nvcc_lcd gpio alt1 gpio5_gpio[5] input 100 k pd disp0_dat12 ac1 ? nvcc_lcd gpio alt1 gpio5_gpio[6] input 100 k pu disp0_dat13 ah3 ? nvcc_lcd gpio alt1 gpio5_gpio[7] input 100 k pu disp0_dat14 ag3 ? nvcc_lcd gpio alt1 gpio5_gpio[8] input 100 k pu disp0_dat15 ah4 ? nvcc_lcd gpio alt1 gpio5_gpio[9] input 100 k pu disp0_dat16 ag5 ? nvcc_lcd gpio alt1 gpio5_gpio[10] input 100 k pu disp0_dat17 ab6 ? nvcc_lcd gpio alt1 gpio5_gpio[11] input 100 k pu disp0_dat18 aj4 ? nvcc_lcd gpio alt1 gpio5_gpio[12] input 100 k pu table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 181 disp0_dat19 aa7 ? nvcc_lcd gpio alt1 gpio5_gpio[13] input 100 k pu disp0_dat2 ac2 ? nvcc_lcd gpio alt1 gpio4_gpio[23] input 100 k pd disp0_dat20 aj5 ? nvcc_lcd gpio alt1 gpio5_gpio[14] input 100 k pu disp0_dat21 ab7 ? nvcc_lcd gpio alt1 gpio5_gpio[15] input 100 k pu disp0_dat22 ah5 ? nvcc_lcd gpio alt1 gpio5_gpio[16] input 100 k pu disp0_dat23 aj6 ? nvcc_lcd gpio alt1 gpio5_gpio[17] input 100 k pu disp0_dat3 ae2 ? nvcc_lcd gpio alt1 gpio4_gpio[24] input 100 k pd disp0_dat4 af1 ? nvcc_lcd gpio alt1 gpio4_gpio[25] input 100 k pd disp0_dat5 ae1 ? nvcc_lcd gpio alt1 gpio4_gpio[26] input 100 k pd disp0_dat6 ad2 ? nvcc_lcd gpio alt1 gpio4_gpio[27] input 100 k pd disp0_dat7 ag1 ? nvcc_lcd gpio alt1 gpio4_gpio[28] input 100 k pd disp0_dat8 ag4 ? nvcc_lcd gpio alt1 gpio4_gpio[29] input 100 k pu disp0_dat9 aj3 ? nvcc_lcd gpio alt1 gpio4_gpio[30] input 100 k pu dram_a0 w23 ac6 nvcc_emi_dram ddr3 alt0 emi_dram_a[0] output low dram_a1 y23 ab6 nvcc_emi_dram ddr3 alt0 emi_dram_a[1] output low dram_a10 m28 ? nvcc_emi_dram ddr3 alt0 emi_dram_a[10] output low dram_a11 j29 ? nvcc_emi_dram ddr3 alt0 emi_dram_a[11] output low dram_a12 l28 ? nvcc_emi_dram ddr3 alt0 emi_dram_a[12] output low dram_a13 m27 ? nvcc_emi_dram ddr3 alt0 emi_dram_a[13] output low dram_a14 l27 ? nvcc_emi_dram ddr3 alt0 emi_dram_a[14] output low dram_a15 d27 ? nvcc_emi_dram ddr3 alt0 emi_dram_a[15] output low dram_a2 v23 ac7 nvcc_emi_dram ddr3 alt0 emi_dram_a[2] output low dram_a3 l23 ab8 nvcc_emi_dram ddr3 alt0 emi_dram_a[3] output low dram_a4 aa24 ab9 nvcc_emi_dram ddr3 alt0 emi_dram_a[4] output low dram_a5 m23 w1 nvcc_emi_dram ddr3 alt0 emi_dram_a[5] output low dram_a6 p23 v2 nvcc_emi_dram ddr3 alt0 emi_dram_a[6] output low dram_a7 n23 u1 nvcc_emi_dram ddr3 alt0 emi_dram_a[7] output low dram_a8 m24 t2 nvcc_emi_dram ddr3 alt0 emi_dram_a[8] output low dram_a9 t23 t1 nvcc_emi_dram ddr3 alt0 emi_dram_a[9] output low table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
i.mx53xd applications processors for consumer products, rev. 2 182 freescale semiconductor package information and contact assignments dram_calibr at i o n r23 ? nvcc_emi_dram calibrati on dram_calibrati on input ? dram_cas aa23 ? nvcc_emi_dram ddr3 alt0 emi_dram_cas output high dram_cs0 ab23 ab3 nvcc_emi_dram ddr3 alt0 emi_dram_cs[0] output high dram_cs1 j24 ab4 nvcc_emi_dram ddr3 alt0 emi_dram_cs[1] output high dram_d0 t29 w22 nvcc_emi_dram ddr3 alt0 emi_dram_d[0] output high dram_d1 v27 aa23 nvcc_emi_dram ddr3 alt0 emi_dram_d[1] output high dram_d10 ag22 ac13 nvcc_emi_dram ddr3 alt0 emi_dram_d[10] output high dram_d11 ag29 ac17 nvcc_emi_dram ddr3 alt0 emi_dram_d[11] output high dram_d12 ag23 ab14 nvcc_emi_dram ddr3 alt0 emi_dram_d[12] output high dram_d13 af29 ab15 nvcc_emi_dram ddr3 alt0 emi_dram_d[13] output high dram_d14 ag28 ab12 nvcc_emi_dram ddr3 alt0 emi_dram_d[14] output high dram_d15 aj27 ac16 nvcc_emi_dram ddr3 alt0 emi_dram_d[15] output high dram_d16 d29 c22 nvcc_emi_dram ddr3 alt0 emi_dram_d[16] output high dram_d17 e29 e23 nvcc_emi_dram ddr3 alt0 emi_dram_d[17] output high dram_d18 d28 d23 nvcc_emi_dram ddr3 alt0 emi_dram_d[18] output high dram_d19 f28 g23 nvcc_emi_dram ddr3 alt0 emi_dram_d[19] output high dram_d2 r29 u22 nvcc_emi_dram ddr3 alt0 emi_dram_d[2] output high dram_d20 f27 f22 nvcc_emi_dram ddr3 alt0 emi_dram_d[20] output high dram_d21 g27 h22 nvcc_emi_dram ddr3 alt0 emi_dram_d[21] output high dram_d22 e28 e22 nvcc_emi_dram ddr3 alt0 emi_dram_d[22] output high dram_d23 f29 h23 nvcc_emi_dram ddr3 alt0 emi_dram_d[23] output high dram_d24 f21 a17 nvcc_emi_dram ddr3 alt0 emi_dram_d[24] output high dram_d25 c19 a14 nvcc_emi_dram ddr3 alt0 emi_dram_d[25] output high dram_d26 g21 b17 nvcc_emi_dram ddr3 alt0 emi_dram_d[26] output high dram_d27 g18 a13 nvcc_emi_dram ddr3 alt0 emi_dram_d[27] output high dram_d28 g20 b15 nvcc_emi_dram ddr3 alt0 emi_dram_d[28] output high dram_d29 f17 b12 nvcc_emi_dram ddr3 alt0 emi_dram_d[29] output high dram_d3 u27 y22 nvcc_emi_dram ddr3 alt0 emi_dram_d[3] output high dram_d30 f20 a16 nvcc_emi_dram ddr3 alt0 emi_dram_d[30] output high table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 183 dram_d31 g19 b14 nvcc_emi_dram ddr3 alt0 emi_dram_d[31] output high dram_d4 r27 t23 nvcc_emi_dram ddr3 alt0 emi_dram_d[4] output high dram_d5 r28 v23 nvcc_emi_dram ddr3 alt0 emi_dram_d[5] output high dram_d6 p29 t22 nvcc_emi_dram ddr3 alt0 emi_dram_d[6] output high dram_d7 t28 w23 nvcc_emi_dram ddr3 alt0 emi_dram_d[7] output high dram_d8 af28 ac14 nvcc_emi_dram ddr3 alt0 emi_dram_d[8] output high dram_d9 ae29 ab17 nvcc_emi_dram ddr3 alt0 emi_dram_d[9] output high dram_dqm0 n28 n23 nvcc_emi_dram ddr3 alt0 emi_dram_dqm[0 ] output low dram_dqm1 ad27 ab20 nvcc_emi_dram ddr3 alt0 emi_dram_dqm[1 ] output low dram_dqm2 h29 l23 nvcc_emi_dram ddr3 alt0 emi_dram_dqm[2 ] output low dram_dqm3 c23 b20 nvcc_emi_dram ddr3 alt0 emi_dram_dqm[3 ] output low dram_ras m29 ? nvcc_emi_dram ddr3 alt0 emi_dram_ras output high dram_reset j28 ? nvcc_emi_dram ddr3 alt0 emi_dram_reset output low dram_sdba0 h27 ? nvcc_emi_dram ddr3 alt0 emi_dram_sdba[ 0] output low dram_sdba1 k27 ? nvcc_emi_dram ddr3 alt0 emi_dram_sdba[ 1] output low dram_sdba2 k28 ? nvcc_emi_dram ddr3 alt0 emi_dram_sdba[ 2] output low dram_sdcke0 ab24 ac3 nvcc_emi_dram ddr3 alt0 emi_dram_sdck e[0] output low dram_sdcke1 f22 ac4 nvcc_emi_dram ddr3 alt0 emi_dram_sdck e[1] output low dram_sdclk_ 0 ? nvcc_emi_dram ddr3clk alt0 emi_dram_sdclk 0 output floating dram_sdclk_ 0_b ? nvcc_emi_dram ddr3clk alt0 emi_dram_sdclk 0_b output floating dram_sdclk_ 1 h23 y2 nvcc_emi_dram ddr3clk alt0 emi_dram_sdclk 1 output floating dram_sdclk_ 1_b j23 y1 nvcc_emi_dram ddr3clk alt0 emi_dram_sdclk 1_b output floating table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
i.mx53xd applications processors for consumer products, rev. 2 184 freescale semiconductor package information and contact assignments dram_sdodt 0 l29 ? nvcc_emi_dram ddr3 alt0 emi_dram_odt[0] output low dram_sdodt 1 h28 ? nvcc_emi_dram ddr3 alt0 emi_dram_odt[1] output low dram_sdqs0 n29 r23 nvcc_emi_dram ddr3clk alt0 emi_dram_sdqs[ 0] input low dram_sdqs0_ b p28 p22 nvcc_emi_dram ddr3clk alt0 emi_dram_sdqs_ b[0] input high dram_sdqs1 ae28 ab18 nvcc_emi_dram ddr3clk alt0 emi_dram_sdqs[ 1] input low dram_sdqs1_ b ae27 ac19 nvcc_emi_dram ddr3clk alt0 emi_dram_sdqs_ b[1] input high dram_sdqs2 g28 j22 nvcc_emi_dram ddr3clk alt0 emi_dram_sdqs[ 2] input low dram_sdqs2_ b g29 k23 nvcc_emi_dram ddr3clk alt0 emi_dram_sdqs_ b[2] input high dram_sdqs3 c22 b18 nvcc_emi_dram ddr3clk alt0 emi_dram_sdqs[ 3] input low dram_sdqs3_ b c21 a19 nvcc_emi_dram ddr3clk alt0 emi_dram_sdqs_ b[3] input high dram_sdwe k29 ? nvcc_emi_dram ddr3 alt0 emi_dram_sdwe output high eckil g14 ? nvcc_srtc_pow analog eckil ? ? eim_a16 a7 ? nvcc_eim_main uhvio alt0 emi_eim_a[16] output 2 ? eim_a17 g8 ? nvcc_eim_main uhvio alt0 emi_eim_a[17] output 2 ? eim_a18 f8 ? nvcc_eim_main uhvio alt0 emi_eim_a[18] output 2 ? eim_a19 a6 ? nvcc_eim_main uhvio alt0 emi_eim_a[19] output 2 ? eim_a20 b7 ? nvcc_eim_main uhvio alt0 emi_eim_a[20] output 2 ? eim_a21 c6 ? nvcc_eim_main uhvio alt0 emi_eim_a[21] output 2 ? eim_a22 c2 ? nvcc_eim_main uhvio alt0 emi_eim_a[22] output 2 ? table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 185 eim_a23 b3 ? nvcc_eim_main uhvio alt0 emi_eim_a[23] output ? eim_a24 a4 ? nvcc_eim_main uhvio alt0 emi_eim_a[24] output ? eim_a25 a3 ? nvcc_eim_main uhvio alt0 emi_eim_a[25] output ? eim_bclk f11 ? nvcc_eim_main uhvio alt0 emi_eim_bclk output ? eim_cs0 g10 ? nvcc_eim_main uhvio alt0 emi_eim_cs[0] output ? eim_cs1 c4 ? nvcc_eim_main uhvio alt0 emi_eim_cs[1] output ? eim_d16 h1 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[16] input 100 k pu eim_d17 g3 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[17] input 100 k pu eim_d18 h2 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[18] input 100 k pu eim_d19 g2 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[19] input 100 k pu eim_d20 m7 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[20] input 100 k pu eim_d21 h6 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[21] input 100 k pu eim_d22 g1 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[22] input 360 k pd eim_d23 f1 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[23] input 100 k pu eim_d24 f9 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[24] input 100 k pu eim_d25 e1 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[25] input 100 k pu eim_d26 d1 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[26] input 100 k pu eim_d27 c10 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[27] input 100 k pu eim_d28 d2 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[28] input 100 k pu eim_d29 c7 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[29] input 100 k pu eim_d30 c1 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[30] input 100 k pu eim_d31 f7 ? nvcc_eim_sec uhvio alt1 gpio3_gpio[31] input 360 k pd eim_da0 k1 ? nvcc_eim_main uhvio alt0 emi_nand_eim_d a[0] input 2 100 k pu eim_da1 g11 ? nvcc_eim_main uhvio alt0 emi_nand_eim_d a[1] input 2 100 k pu eim_da10 l7 ? nvcc_eim_main uhvio alt0 emi_nand_eim_d a[10] input 2 100 k pu eim_da11 k7 ? nvcc_eim_main uhvio alt0 emi_nand_eim_d a[11] input 100 k pu eim_da12 e2 d1 nvcc_eim_main uhvio alt0 emi_nand_eim_d a[12] input 100 k pu table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
i.mx53xd applications processors for consumer products, rev. 2 186 freescale semiconductor package information and contact assignments eim_da13 f2 e1 nvcc_eim_main uhvio alt0 emi_nand_eim_d a[13] input 100 k pu eim_da14 j2 g1 nvcc_eim_main uhvio alt0 emi_nand_eim_d a[14] input 100 k pu eim_da15 k2 h1 nvcc_eim_main uhvio alt0 emi_nand_eim_d a[15] input 100 k pu eim_da2 f10 ? nvcc_eim_main uhvio alt0 emi_nand_eim_d a[2] input 2 100 k pu eim_da3 a8 ? nvcc_eim_main uhvio alt0 emi_nand_eim_d a[3] input 2 100 k pu eim_da4 e3 d2 nvcc_eim_main uhvio alt0 emi_nand_eim_d a[4] input 2 100 k pu eim_da5 f3 e2 nvcc_eim_main uhvio alt0 emi_nand_eim_d a[5] input 2 100 k pu eim_da6 j3 g2 nvcc_eim_main uhvio alt0 emi_nand_eim_d a[6] input 2 100 k pu eim_da7 k3 h2 nvcc_eim_main uhvio alt0 emi_nand_eim_d a[7] input 2 100 k pu eim_da8 a10 ? nvcc_eim_main uhvio alt0 emi_nand_eim_d a[8] input 2 100 k pu eim_da9 k6 ? nvcc_eim_main uhvio alt0 emi_nand_eim_d a[9] input 2 100 k pu eim_eb0 j1 ? nvcc_eim_main uhvio alt0 emi_eim_eb[0] output 2 ? eim_eb1 g7 ? nvcc_eim_main uhvio alt0 emi_eim_eb[1] output 2 ? eim_eb2 j7 ? nvcc_eim_main uhvio alt1 gpio2_gpio[30] input 100 k pu eim_eb3 f6 ? nvcc_eim_main uhvio alt1 gpio2_gpio[31] input 100 k pu eim_lba a5 ? nvcc_eim_main uhvio alt0 emi_eim_lba output 2 ? eim_oe a9 ? nvcc_eim_main uhvio alt0 emi_eim_oe output ? eim_rw h7 ? nvcc_eim_main uhvio alt0 emi_eim_rw output ? eim_wait l6 ? nvcc_eim_main uhvio alt0 emi_eim_wait output ? extal g15 ? nvcc_xtal analog ? extal ? ? fastr_ana ad29 ? nvcc_ckih analog ? fastr_ana ? ? table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 187 fastr_dig ad28 ? nvcc_ckih analog ? fastr_dig ? ? fec_crs_dv y27 ? nvcc_fec uhvio alt1 gpio1_gpio[25] input 100 k pu fec_mdc u28 ? nvcc_fec uhvio alt1 gpio1_gpio[31] input 100 k pu fec_mdio aa29 ? nvcc_fec uhvio alt1 gpio1_gpio[22] input 100 k pu fec_ref_clk y29 ? nvcc_fec uhvio alt1 gpio1_gpio[23] input 100 k pu fec_rx_er y28 ? nvcc_fec uhvio alt1 gpio1_gpio[24] input 100 k pu fec_rxd0 w28 ? nvcc_fec uhvio alt1 gpio1_gpio[27] input 100 k pu fec_rxd1 w29 ? nvcc_fec uhvio alt1 gpio1_gpio[26] input 100 k pu fec_tx_en v29 ? nvcc_fec uhvio alt1 gpio1_gpio[28] input 360 k pd fec_txd0 u29 ? nvcc_fec uhvio alt1 gpio1_gpio[30] input 100 k pu fec_txd1 v28 ? nvcc_fec uhvio alt1 gpio1_gpio[29] input 100 k pu gpio_0 ad12 ? nvcc_gpio uhvio alt1 gpio1_gpio[0] input 360 k pd gpio_1 ah12 ? nvcc_gpio uhvio alt1 gpio1_gpio[1] input 360 k pd gpio_10 b25 ? tvdac_ahvddrg b gpio alt0 gpio4_gpio[0] input 100 k pu gpio_11 b26 ? tvdac_ahvddrg b gpio alt0 gpio4_gpio[1] input 100 k pu gpio_12 a26 ? tvdac_ahvddrg b gpio alt0 gpio4_gpio[2] input 100 k pu gpio_13 c25 ? tvdac_ahvddrg b gpio alt0 gpio4_gpio[3] input 100 k pu gpio_14 b27 ? tvdac_ahvddrg b gpio alt0 gpio4_gpio[4] input 100 k pu gpio_16 ah10 ? nvcc_gpio uhvio alt1 gpio7_gpio[11] input 360 k pd gpio_17 ac10 ? nvcc_gpio uhvio alt1 gpio7_gpio[12] input 360 k pd gpio_18 ac9 ? nvcc_gpio uhvio alt1 gpio7_gpio[13] input 360 k pd gpio_19 aj10 ? nvcc_keypad uhvio alt1 gpio4_gpio[5] input 3 100 k pu gpio_2 ag11 ? nvcc_gpio uhvio alt1 gpio1_gpio[2] input 360 k pd gpio_3 ac12 ? nvcc_gpio uhvio alt1 gpio1_gpio[3] input 360 k pd gpio_4 ah11 ? nvcc_gpio uhvio alt1 gpio1_gpio[4] input 100 k pu gpio_5 aj11 ? nvcc_gpio uhvio alt1 gpio1_gpio[5] input 360 k pd gpio_6 aj12 ? nvcc_gpio uhvio alt1 gpio1_gpio[6] input 360 k pd table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
i.mx53xd applications processors for consumer products, rev. 2 188 freescale semiconductor package information and contact assignments gpio_7 ac11 ? nvcc_gpio uhvio alt1 gpio1_gpio[7] input 360 k pd gpio_8 ad10 ? nvcc_gpio uhvio alt1 gpio1_gpio[8] input 360 k pd gpio_9 ac13 ? nvcc_gpio uhvio alt1 gpio1_gpio[9] input 100 k pu jtag_mod ad15 ? nvcc_jtag gpio alt0 sjc_mod input 100 k pu jtag_tck ad13 ? nvcc_jtag gpio alt0 sjc_tck input 100 k pd jtag_tdi ac15 ? nvcc_jtag gpio alt0 sjc_tdi input 47 k pu jtag_tdo ag15 ? nvcc_jtag gpio alt0 sjc_tdo input keeper jtag_tms ad16 ? nvcc_jtag gpio alt0 sjc_tms input 47 k pu jtag_trstb ac17 ? nvcc_jtag gpio alt0 sjc_trstb input 47 k pu key_col0 ag9 ? nvcc_keypad uhvio alt1 gpio4_gpio[6] input 4 100 k pu key_col1 aj9 ? nvcc_keypad uhvio alt1 gpio4_gpio[8] input 100 k pu key_col2 ag8 ? nvcc_keypad uhvio alt1 gpio4_gpio[10] input 100 k pu key_col3 aj8 ? nvcc_keypad uhvio alt1 gpio4_gpio[12] input 100 k pu key_col4 ah7 ? nvcc_keypad uhvio alt1 gpio4_gpio[14] input 100 k pu key_row0 ah9 ? nvcc_keypad uhvio alt1 gpio4_gpio[7] input 360 k pd key_row1 ah8 ? nvcc_keypad uhvio alt1 gpio4_gpio[9] input 100 k pu key_row2 aj7 ? nvcc_keypad uhvio alt1 gpio4_gpio[11] input 100 k pu key_row3 ag7 ? nvcc_keypad uhvio alt1 gpio4_gpio[13] input 100 k pu key_row4 ad8 ? nvcc_keypad uhvio alt1 gpio4_gpio[15] input 360 k pd lvds_bg_res c18 ? nvcc_lvds_bg analog ? lvds_bg_res ? ? lvds0_clk_n b19 ? nvcc_lvds lvds alt0 gpio7_gpi[25] input floating lvds0_clk_p a19 ? nvcc_lvds lvds alt0 gpio7_gpi[24] input floating lvds0_tx0_n b22 ? nvcc_lvds lvds alt0 gpio7_gpi[31] input floating lvds0_tx0_p a22 ? nvcc_lvds lvds alt0 gpio7_gpi[30] input floating lvds0_tx1_n a21 ? nvcc_lvds lvds alt0 gpio7_gpi[29] input floating lvds0_tx1_p b21 ? nvcc_lvds lvds alt0 gpio7_gpi[28] input floating lvds0_tx2_n b20 ? nvcc_lvds lvds alt0 gpio7_gpi[27] input floating lvds0_tx2_p a20 ? nvcc_lvds lvds alt0 gpio7_gpi[26] input floating lvds0_tx3_n b18 ? nvcc_lvds lvds alt0 gpio7_gpi[23] input floating lvds0_tx3_p a18 ? nvcc_lvds lvds alt0 gpio7_gpi[22] input floating table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 189 lvds1_clk_n a15 ? nvcc_lvds lvds alt0 gpio6_gpi[27] input floating lvds1_clk_p b15 ? nvcc_lvds lvds alt0 gpio6_gpi[26] input floating lvds1_tx0_n b17 ? nvcc_lvds lvds alt0 gpio6_gpi[31] input floating lvds1_tx0_p a17 ? nvcc_lvds lvds alt0 gpio6_gpi[30] input floating lvds1_tx1_n a16 ? nvcc_lvds lvds alt0 gpio6_gpi[29] input floating lvds1_tx1_p b16 ? nvcc_lvds lvds alt0 gpio6_gpi[28] input floating lvds1_tx2_n a14 ? nvcc_lvds lvds alt0 gpio6_gpi[25] input floating lvds1_tx2_p b14 ? nvcc_lvds lvds alt0 gpio6_gpi[24] input floating lvds1_tx3_n a13 ? nvcc_lvds lvds alt0 gpio6_gpi[23] input floating lvds1_tx3_p b13 ? nvcc_lvds lvds alt0 gpio6_gpi[22] input floating nandf_ale n3 l2 nvcc_nandf uhvio alt1 gpio6_gpio[8] input 100 k pu nandf_cle g16 ? nvcc_nandf uhvio alt1 gpio6_gpio[7] input 100 k pu nandf_cs0 p2 m1 nvcc_nandf uhvio alt1 gpio6_gpio[11] input 100 k pu nandf_cs1 a11 ? nvcc_nandf uhvio alt1 gpio6_gpio[14] input 100 k pu nandf_cs2 c12 ? nvcc_nandf uhvio alt1 gpio6_gpio[15] input 100 k pu nandf_cs3 a12 ? nvcc_nandf uhvio alt1 gpio6_gpio[16] input 100 k pu nandf_rb0 c15 ? nvcc_nandf uhvio alt1 gpio6_gpio[10] input 100 k pu nandf_re_b m3 k2 nvcc_eim_main uhvio alt1 gpio6_gpio[13] input 100 k pu nandf_we_b m2 k1 nvcc_eim_main uhvio alt1 gpio6_gpio[12] input 100 k pu nandf_wp_b t2 n1 nvcc_nandf uhvio alt1 gpio6_gpio[9] input 100 k pu pata_buffer_ en v6 ? nvcc_pata uhvio alt1 gpio7_gpio[1] input 100 k pu pata_cs_0 aa2 ? nvcc_pata uhvio alt1 gpio7_gpio[9] input 100 k pu pata_cs_1 ab1 ? nvcc_pata uhvio alt1 gpio7_gpio[10] input 100 k pu pata_da_0 n2 l1 nvcc_pata uhvio alt1 gpio7_gpio[6] input 100 k pu pata_da_1 ab2 ? nvcc_pata uhvio alt1 gpio7_gpio[7] input 100 k pu pata_da_2 y3 ? nvcc_pata uhvio alt1 gpio7_gpio[8] input 100 k pu pata_data0 b9 a7 nvcc_pata uhvio alt1 gpio2_gpio[0] input 100 k pu pata_data1 b8 b6 nvcc_pata uhvio alt1 gpio2_gpio[1] input 100 k pu pata_data10 b10 a8 nvcc_pata uhvio alt1 gpio2_gpio[10] input 100 k pu table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
i.mx53xd applications processors for consumer products, rev. 2 190 freescale semiconductor package information and contact assignments pata_data11 c9 b7 nvcc_pata uhvio alt1 gpio2_gpio[11] input 100 k pu pata_data12 y1 ? nvcc_pata uhvio alt1 gpio2_gpio[12] input 100 k pu pata_data13 aa1 ? nvcc_pata uhvio alt1 gpio2_gpio[13] input 100 k pu pata_data14 w1 ? nvcc_pata uhvio alt1 gpio2_gpio[14] input 100 k pu pata_data15 v1 ? nvcc_pata uhvio alt1 gpio2_gpio[15] input 100 k pu pata_data2 b6 a5 nvcc_pata uhvio alt1 gpio2_gpio[2] input 100 k pu pata_data3 c5 b4 nvcc_pata uhvio alt1 gpio2_gpio[3] input 100 k pu pata_data4 y2 ? nvcc_pata uhvio alt1 gpio2_gpio[4] input 100 k pu pata_data5 v3 ? nvcc_pata uhvio alt1 gpio2_gpio[5] input 100 k pu pata_data6 v2 ? nvcc_pata uhvio alt1 gpio2_gpio[6] input 100 k pu pata_data7 w2 ? nvcc_pata uhvio alt1 gpio2_gpio[7] input 100 k pu pata_data8 b12 a10 nvcc_pata uhvio alt1 gpio2_gpio[8] input 100 k pu pata_data9 b11 b9 nvcc_pata uhvio alt1 gpio2_gpio[9] input 100 k pu pata_dior ab3 ? nvcc_pata uhvio alt1 gpio7_gpio[3] input 100 k pu pata_diow aa6 ? nvcc_pata uhvio alt1 gpio6_gpio[17] input 100 k pu pata_dmack y6 ? nvcc_pata uhvio alt1 gpio6_gpio[18] input 100 k pu pata_dmarq w6 ? nvcc_pata uhvio alt1 gpio7_gpio[0] input 100 k pu pata_intrq v7 ? nvcc_pata uhvio alt1 gpio7_gpio[2] input 100 k pu pata_iordy b5 a4 nvcc_pata uhvio alt1 gpio7_gpio[5] input 100 k pu pata_reset_b b4 a3 nvcc_pata uhvio alt1 gpio7_gpio[4] input 100 k pu pmic_on_req f12 ? nvcc_srtc_pow gpio alt0 srtc_srtcalarm output ? pmic_stby_r eq g17 ? nvcc_srtc_pow gpio alt0 ccm_pmic_vstby _req output ? por_b ac27 ? nvcc_reset lvio alt0 src_por_b input 100 k pu reset_in_b ab28 ? nvcc_reset lvio alt0 src_reset_b input 100 k pu sata_refclk m aj18 ? vph analog ? sata_refclkm ? ? sata_refclk p ah18 ? vph analog ? sata_refclkp ? ? sata_rext aj17 ? vph analog ? sata_rext ? ? sata_rxm ah16 ? vph analog ? sata_rxm ? ? table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 191 sata_rxp aj16 ? vph analog ? sata_rxp ? ? sata_txm ah14 ? vph analog ? sata_txm ? ? sata_txp aj14 ? vph analog ? sata_txp ? ? sd1_clk aj26 ? nvcc_sd1 uhvio alt1 gpio1_gpio[20] input 100 k pu sd1_cmd ah26 ? nvcc_sd1 uhvio alt1 gpio1_gpio[18] input 100 k pu sd1_data0 ah27 ? nvcc_sd1 uhvio alt1 gpio1_gpio[16] input 100 k pu sd1_data1 ag25 ? nvcc_sd1 uhvio alt1 gpio1_gpio[17] input 100 k pu sd1_data2 ah25 ? nvcc_sd1 uhvio alt1 gpio1_gpio[19] input 100 k pu sd1_data3 aj25 ? nvcc_sd1 uhvio alt1 gpio1_gpio[21] input 100 k pu sd2_clk ag19 ? nvcc_sd2 uhvio alt1 gpio1_gpio[10] input 100 k pu sd2_cmd ad21 ? nvcc_sd2 uhvio alt1 gpio1_gpio[11] input 100 k pu sd2_data0 ah17 ? nvcc_sd2 uhvio alt1 gpio1_gpio[15] input 100 k pu sd2_data1 ag17 ? nvcc_sd2 uhvio alt1 gpio1_gpio[14] input 100 k pu sd2_data2 ad17 ? nvcc_sd2 uhvio alt1 gpio1_gpio[13] input 100 k pu sd2_data3 ag18 ? nvcc_sd2 uhvio alt1 gpio1_gpio[12] input 100 k pu test_mode aa27 ? nvcc_reset lvio alt0 tcu_test_mode input 100 k pd tvcdc_iob_b ack b23 ? tvdac_ahvddrg b analog ? tvcdc_iob_back ? ? tvcdc_iog_b ack a24 ? tvdac_ahvddrg b analog ? tvcdc_iog_bac k ?? tvcdc_ior_b ack c28 ? tvdac_ahvddrg b analog ? tvcdc_ior_back ? ? tvdac_comp a25 ? tvdac_ahvddrg b analog ? tvdac_comp ? ? tvdac_iob a23 ? tvdac_ahvddrg b analog ? tvdac_iob ? ? tvdac_iog b24 ? tvdac_ahvddrg b analog ? tvdac_iog ? ? tvdac_ior c29 ? tvdac_ahvddrg b analog ? tvdac_ior ? ? usb_h1_dn ah21 ? usb_h1_vdda25, usb_h1_vdda33 analog5 0 ? usb_h1_dn ? ? table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
i.mx53xd applications processors for consumer products, rev. 2 192 freescale semiconductor package information and contact assignments 6.3.3 12 x 12 mm pop, 0.4 pitch ball maps table 119 shows the 12 12 mm, 0.4 pitch top ball map. table 120 shows the 12 12 mm, 0.4 pitch bottom ball map. usb_h1_dp aj21 ? usb_h1_vdda25, usb_h1_vdda33 analog5 0 ? usb_h1_dp ? ? usb_h1_gpan aio aj20 ? usb_h1_vdda25, usb_h1_vdda33 analog2 5 ? usb_h1_gpanaio ? ? usb_h1_rref ext ah20 ? usb_h1_vdda25, usb_h1_vdda33 analog2 5 ? usb_h1_rrefex t ?? usb_h1_vbus aj22 ? usb_h1_vdda25, usb_h1_vdda33 analog5 0 ? usb_h1_vbus ? ? usb_otg_dn aj23 ? usb_otg_vdda25 , usb_otg_vdda33 analog5 0 ? usb_otg_dn ? ? usb_otg_dp ah23 ? usb_otg_vdda25 , usb_otg_vdda33 analog5 0 ? usb_otg_dp ? ? usb_otg_gpa naio ah24 ? usb_otg_vdda25 , usb_otg_vdda33 analog2 5 ? usb_otg_gpanai o ?? usb_otg_id ah22 ? usb_otg_vdda25 , usb_otg_vdda33 analog2 5 ? usb_otg_id ? ? usb_otg_rre fext aj24 ? usb_otg_vdda25 , usb_otg_vdda33 analog2 5 ? usb_otg_rrefe xt ?? usb_otg_vbu s ag21 ? usb_otg_vdda25 , usb_otg_vdda33 analog5 0 ? usb_otg_vbus ? ? xtal f15 ? nvcc_xtal analog ? xtal ? ? 1 the state immediately after reset and before rom firmware or software has executed. 2 during power-on reset this port acts as input for fuse override, ~33k pu/pd recommended to set the value. see section 5.1, ?boot mode configuration pins ? for details. 3 during power-on reset this port acts as output for diagnostic signal int_boot 4 during power-on reset this port acts as output for diagnostic signal any_pu_rst table 118. pop 12 x 12 mm signal assignments, power rails, and i/o (continued) contact name pop bottom package contact assignment pop top package contact assignment power rail i/o buffer type out of reset condition 1 alt. mode function direct ion config./ value
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 193 table 119. pop 12 12 mm, 0.4 pitch top ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a nc nc pata _ r e s e t _ b pata _ i o r dy pata _ data 2 pop_vccmm pata _ data 0 pata _ data 1 0 pop_vccqmm pata _ data 8 pop_vdd1 gnd dram_d27 dram_d25 gnd dram_d30 dram_d24 gnd dram_sdqs3_b pop_vdd1 gnd nc nc a b nc nc pop_vdd1 pata _ data 3 gnd pata _ data 1 pata _ data 1 1 gnd pata _ data 9 gnd pop_vdd2 dram_d29 pop_vddq dram_d31 dram_d28 pop_vddq dram_d26 dram_sdqs3 pop_vddq dram_dqm3 pop_vdd2 nc nc b c gnd pop_vdd2 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_d16 gnd c d eim_da12 eim_da4 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vddq dram_d18 d e eim_da13 eim_da5 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_d22 dram_d17 e f pop_vccqmm1 gnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_d20 gnd f g eim_da14 eim_da6 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vddq dram_d19 g h eim_da15 eim_da7 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_d21 dram_d23 h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
i.mx53xd applications processors for consumer products, rev. 2 194 freescale semiconductor package information and contact assignments j pop_vccmm gnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_sdqs2 gnd j k nandf_we_b nandf_re_b nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vddq dram_sdqs2_b k l pata _ da _ 0 nandf_ale nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vdd2 dram_dqm2 l m nandf_cs0 gnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc ddr_vref gnd m n nandf_wp_b pop_vdd1 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vdd1 dram_dqm0 n p pop_zq ddr_vref nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_sdqs0_b gnd p r gnd pop_vdd2 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vddq dram_sdqs0 r table 119. pop 12 12 mm, 0.4 pitch top ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 195 t dram_a9 dram_a8 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_d6 dram_d4 t u dram_a7 pop_vddca nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_d2 gnd u v gnd dram_a6 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vddq dram_d5 v w dram_a5 pop_vddca nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_d0 dram_d7 w y dram_sdclk_1_b dram_sdclk_1 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_d3 gnd y aa gnd pop_vdd2 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vddq dram_d1 aa ab nc nc dram_cs0 dram_cs1 pop_vdd1 dram_a1 gnd dram_a3 dram_a4 pop_vdd2 gnd dram_d14 pop_vddq dram_d12 dram_d13 pop_vddq dram_d9 dram_sdqs1 pop_vddq dram_dqm1 pop_vdd2 nc nc ab ac nc nc dram_sdcke0 dram_sdcke1 gnd dram_a0 dram_a2 pop_vddca gnd pop_vddmm pop_vacc gnd dram_d10 dram_d8 gnd dram_d15 dram_d11 gnd dram_sdqs1_b pop_vdd1 gnd nc nc ac table 119. pop 12 12 mm, 0.4 pitch top ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
i.mx53xd applications processors for consumer products, rev. 2 196 freescale semiconductor package information and contact assignments table 120. pop 12 12 mm, 0.4 pitch bottom ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 a gnd gnd eim_a25 eim_a24 eim_lba eim_a19 eim_a16 eim_da3 eim_oe eim_da8 nandf_cs1 nandf_cs3 lvds1_tx3_n lvds1_tx2_n lvds1_clk_n lvds1_tx1_n lvds1_tx0_p lvds0_tx3_p lvds0_clk_p lvds0_tx2_p lvds0_tx1_n lvds0_tx0_p tvdac_iob tvcdc_iog_back tvdac_comp gpio_12 tvdac_vref gnd gnd a b gnd gnd eim_a23 pata_reset_b pata _ i o r dy pata _ data 2 eim_a20 pata _ data 1 pata _ data 0 pata _ data 1 0 pata _ data 9 pata _ data 8 lvds1_tx3_p lvds1_tx2_p lvds1_clk_p lvds1_tx1_p lvds1_tx0_n lvds0_tx3_n lvds0_clk_n lvds0_tx2_n lvds0_tx1_p lvds0_tx0_n tvcdc_iob_back tvdac_iog gpio_10 gpio_11 gpio_14 gnd gnd b c eim_d30 eim_a22 pop_vdd1 eim_cs1 pata _ data 3 eim_a21 eim_d29 pop_vccmm pata _ data 1 1 eim_d27 pop_vccqmm nandf_cs2 pop_vdd1 pop_vdd2 nandf_rb0 pop_vddq gnd lvds_bg_res dram_d25 pop_vddq dram_sdqs3_b dram_sdqs3 dram_dqm3 pop_vddq gpio_13 pop_vdd1 pop_vdd2 tvcdc_ior_back tvdac_ior c d eim_d26 eim_d28 pop_vdd2 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_a15 dram_d18 dram_d16 d e eim_d25 eim_da12 eim_da4 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vddq dram_d22 dram_d17 e f eim_d23 eim_da13 eim_da5 nc nc eim_eb3 eim_d31 eim_a18 eim_d24 eim_da2 eim_bclk pmic_on_req nvcc_srtc_pow nvcc_xtal xtal vdda dram_d29 nvcc_lvds_bg nvcc_lvds dram_d30 dram_d24 dram_sdcke1 tvdac_dhvdd nvcc_emi_dram nc nc dram_d20 dram_d19 dram_d23 f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 197 g eim_d22 eim_d19 eim_d17 nc nc nvcc_eim_sec eim_eb1 eim_a17 nvcc_eim_main eim_cs0 eim_da1 nvcc_nandf ckil eckil extal nandf_cle pmic_stby_req dram_d27 dram_d31 dram_d28 dram_d26 tvdac_ahvddrgb tvdac_ahvddrgb nvcc_emi_dram nc nc dram_d21 dram_sdqs2 dram_sdqs2_b g h eim_d16 eim_d18 pop_vccqmm1 nc nc eim_d21 eim_rw nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_sdclk_1 nvcc_emi_dram nc nc dram_sdba0 dram_sdodt1 dram_dqm2 h j eim_eb0 eim_da14 eim_da6 nc nc nvcc_csi eim_eb2 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_sdclk_1_b dram_cs1 nc nc pop_vddq dram_reset dram_a11 j k eim_da0 eim_da15 eim_da7 nc nc eim_da9 eim_da11 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nvcc_emi_dram_2p5 nvcc_emi_dram nc nc dram_sdba1 dram_sdba2 dram_sdwe k l csi0_dat19 csi0_dat18 pop_vccmm nc nc eim_wait eim_da10 nc nc nc vcc vcc vcc gnd gnd gnd vcc vcc vcc nc nc nc dram_a3 nvcc_emi_dram nc nc dram_a14 dram_a12 dram_sdodt0 l m csi0_dat16 nandf_we_b nandf_re_b nc nc vdda eim_d20 nc nc nc vcc vcc vcc gnd gnd gnd vcc vcc vcc nc nc nc dram_a5 dram_a8 nc nc dram_a13 dram_a10 dram_ras m table 120. pop 12 12 mm, 0.4 pitch bottom ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
i.mx53xd applications processors for consumer products, rev. 2 198 freescale semiconductor package information and contact assignments n csi0_dat17 pata _ da _ 0 nandf_ale nc nc nvcc_pata csi0_dat7 nc nc nc vcc vcc vcc gnd gnd gnd vcc vcc vcc nc nc nc dram_a7 nvcc_emi_dram nc nc pop_vddq dram_dqm0 dram_sdqs0 n p csi0_dat15 nandf_cs0 csi0_dat9 nc nc csi0_data_en csi0_dat6 nc nc nc gnd gnd gnd nc nc nc gnd gnd gnd nc nc nc dram_a6 nvcc_emi_dram nc nc pop_vdd2 dram_sdqs0_b dram_d6 p r csi0_dat13 csi0_dat10 csi0_dat5 nc nc vdda csi0_dat11 nc nc nc gnd gnd gnd nc nc nc gnd gnd gnd nc nc nc dram_calibration nvcc_emi_dram nc nc dram_d4 dram_d5 dram_d2 r t csi0_dat14 nandf_wp_b pop_vdd1 nc nc csi0_mclk csi0_dat4 nc nc nc gnd gnd gnd nc nc nc gnd gnd gnd nc nc nc dram_a9 vdda nc nc pop_vdd1 dram_d7 dram_d0 t u csi0_dat12 csi0_dat8 pop_zq nc nc csi0_pixclk csi0_vsync nc nc nc vddgp vddgp vddgp gnd gnd gnd vcc vcc vcc nc nc nc ddr_vref nvcc_emi_dram nc nc dram_d3 fec_mdc fec_txd0 u v pata _ data 1 5 pata _ data 6 pata _ data 5 nc nc pata_buffer_en pata _ i n t r q nc nc nc vddgp vddgp vddgp gnd gnd gnd vcc vcc vcc nc nc nc dram_a2 nvcc_emi_dram nc nc dram_d1 fec_txd1 fec_tx_en v table 120. pop 12 12 mm, 0.4 pitch bottom ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
package information and contact assignments i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 199 w pata _ data 1 4 pata _ data 7 pop_vdd2 nc nc pata_dmarq nvcc_lcd nc nc nc vddgp vddgp vddgp gnd gnd gnd vcc vcc vcc nc nc nc dram_a0 nvcc_emi_dram nc nc pop_vddq fec_rxd0 fec_rxd1 w y pata _ data 1 2 pata _ data 4 pata _ da _ 2 nc nc pata _ d m ac k nvcc_lcd nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_a1 nvcc_emi_dram_2p5 nc nc fec_crs_dv fec_rx_er fec_ref_clk y aa pata _ data 1 3 pata _ c s _ 0 pop_vddca nc nc pata _ d i ow disp0_dat19 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_cas dram_a4 nc nc test_mode boot_mode0 fec_mdio aa ab pata _ c s _ 1 pata _ da _ 1 pata _ d i o r nc nc disp0_dat17 disp0_dat21 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_cs0 dram_sdcke0 nc nc pop_vddq reset_in_b boot_mode1 ab ac disp0_dat12 disp0_dat2 disp0_dat1 nc nc di0_pin4 di0_pin3 vddal1 gpio_18 gpio_17 gpio_7 gpio_3 gpio_9 nvcc_fec jtag_tdi nvcc_sd2 jtag_trstb usb_h1_vdda33 usb_otg_vdda25 nvcc_sd1 vdd_fuse vdd_ana_pll vdd_dig_pll nvcc_emi_dram nc nc por_b ckih2 ckih1 ac ad disp0_dat0 disp0_dat6 pop_vddca nc nc nvcc_keypad di0_pin2 key_row4 nvcc_gpio gpio_8 nvcc_jtag gpio_0 jtag_tck vdda jtag_mod jtag_tms sd2_data2 nvcc_reset usb_h1_vdda25 usb_otg_vdda33 sd2_cmd nvcc_ckih vdd_reg nvcc_emi_dram nc nc dram_dqm1 fastr_dig fastr_ana ad table 120. pop 12 12 mm, 0.4 pitch bottom ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
i.mx53xd applications processors for consumer products, rev. 2 200 freescale semiconductor package information and contact assignments ae disp0_dat5 disp0_dat3 disp0_dat11 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dram_sdqs1_b dram_sdqs1 dram_d9 ae af disp0_dat4 di0_disp_clk pop_vdd2 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pop_vddq dram_d8 dram_d13 af ag disp0_dat7 disp0_dat10 disp0_dat14 disp0_dat8 disp0_dat16 pop_vdd1 key_row3 key_col2 key_col0 pop_vddca gpio_2 pop_vdd2 pop_vddmm pop_vacc jtag_tdo pop_vddq sd2_data1 sd2_data3 sd2_clk pop_vddq usb_otg_vbus dram_d10 dram_d12 pop_vddq sd1_data1 pop_vdd1 pop_vdd2 dram_d14 dram_d11 ag ah gnd svddgp disp0_dat13 disp0_dat15 disp0_dat22 di0_pin15 key_col4 key_row1 key_row0 gpio_16 gpio_4 gpio_1 vph sata_txm gnd sata_rxm sd2_data0 sata_refclkp vp usb_h1_rrefext usb_h1_dn usb_otg_id usb_otg_dp usb_otg_gpanaio sd1_data2 sd1_cmd sd1_data0 svcc gnd ah aj gnd gnd disp0_dat9 disp0_dat18 disp0_dat20 disp0_dat23 key_row2 key_col3 key_col1 gpio_19 gpio_5 gpio_6 vph sata_txp gnd sata_rxp sata_rext sata_refclkm vp usb_h1_gpanaio usb_h1_dp usb_h1_vbus usb_otg_dn usb_otg_rrefext sd1_data3 sd1_clk dram_d15 gnd gnd aj table 120. pop 12 12 mm, 0.4 pitch bottom ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
revision history i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 201 7 revision history table 121 provides a revision history for this data sheet. table 121. i.mx53xd data sheet document revision history rev. number date substantiv e change(s) rev 2 05/2011 ? in table 1, "ordering information," on page 3 , deleted the row for part number pcimx535dvv1b, added a row for mcimx538dzk1c and updated the pcimx538dzk1c row. ? updated the note on page 6 in section 1.2, ?features .? ? added 167 mhz arm specification to table 7, "i.mx53xd operating ranges," on page 20 . ? modified vdd_fuse design best practice footnote on table 7, "i.mx53xd operating ranges," on page 20 . ? changed vdd_fuse max current to 120 ma in table 9, "maximal supply currents," on page 23 . ? deleted the last row of table 10, "usb interface current consumption," on page 25 . ? added section 4.1.2.2, ?pop package thermal resistance,? according to package design report. ? made changes related to text, tables, and figures in section 4.6.7, ?ddr sdram specific parameters (ddr2/lvddr2, lpddr2, and ddr3) . changes include adding lpddr2 waves, updating timings by accz test results, and changing note about ddr load model. ? removed the standard serial interfaces section. ?in table 11, "gpio i/o dc electrical characteristics," on page 29 , changed input current with no pull-up/down from 250/120 na to 2 a, all input currents with pull-up from 0.12 ? to 2 a when vin = ovdd, and input current with pull-down from 0.25 a to 2 a when vin = 0. ?in ta bl e 1 2 , ta b l e 1 3 , and ta bl e 1 4 , changed input current from the na range to 1 a. ?in table 15, "lvio dc electrical characteristics," on page 33 , changed input current with no pull-up/down from 250/120 na to 1 a, all input currents with pull-up from 0.12 ? to 1 a when vin = ovdd, and input current with pull-down from 0.25 a to 1 a when vin = 0. ?in table 16, "uhvio dc electrical characteristics," on page 34 , changed input current with no pull-up/down from 300/63 na to 1 a, all input currents with pull-up from 0.06 ? to 1 a when vin = ovdd, and input current with pull-down from 0.3 a to 1 a when vin = 0. ? updated keeper values in ta bl e 1 1 through ta bl e 1 6 . ? fixed titles of figure 18 through figure 26 , to fit original eim ac spec. ? updated figure 2, "power up detailed sequence," on page 27 . ? added figure 27, "dtack write access (dap=0)," on page 62 . ? added table 19, "ddr output driver average impedance," on page 38 . ? deleted the second footnote of table 33, "camp electrical parameters (ckih1, ckih2)," on page 47 . ? deleted the revision 1.0 eim internal module multiplexing table. ? deleted the ckil electrical specifications table. ? deleted the cspi slave mode timing parameters table . ? updated the last paragragh of section 4.7.8.6.1, ?ipu display operating signals.? ? changed the title of the section 4.4.2, ?ddr output driver average impedance ,? from ?lpddr2 i/o output buffer impedance.? ? added section 6.3.2.2, ?pop memory support and signal cross reference .? ? updated table 36, " nfc?timing characteristics," on page 52 . ? removed the ?differential pulse skew? row from table 30, "ac electrical characteristics of lvds pad," on page 45 . ? updated table 64, "asynchronous display interface timing parameters (pixel level)," on page 105 . ? updated table 65, "asynchronous parallel interface timing parameters (access level)," on page 106 . ? updated table 101, "usb timing specification for normal ulpi mode," on page 144 . ? updated the second footnote on table 112, "19 x 19 mm signal assignments, power rails, and i/o," on page 154 .
i.mx53xd applications processors for consumer products, rev. 2 202 freescale semiconductor revision history rev 1 03/2011 ? updated the first sentence of section 3.1, ?special signal considerations.? ? deleted two tables, ?special signal considerations? and ?jtag controller interface summary,? in section 3.1, ?special signal considerations.? ? updated table 7, "i.mx53xd operating ranges," on page 20 . ? changed vddgp voltages as follows: ? 400 mhz from 1.35 to 1.05 v maximum. ? 800 mhz from 1.0/1.05/ 1.1 to 1.05/1.1/1.15 v minimum/nominal/maximum. ? stop mode from 0.9/0.95/1.1 to 0.8/ 0.85/1.3 v minimum/nominal/maximum. ? added statements to footnotes 5 and 6. ? added footnote on voltage ramping. ?in section 1, ?introduction ,? the second bullet point changed from ?smartbooks? to ?smart mobile devices.? ?in table 1, "ordering information," on page 3 , added two new rows for part numbers PCIMX535DVV1C and mcimx535dvv1c. rev 0 02/2011 initial release. table 121. i.mx53xd data sheet document revision history (continued) rev. number date substantiv e change(s)
i.mx53xd applications processors for consumer products, rev. 2 freescale semiconductor 203 this page intentionally left blank
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