cloc k gener ator f or digital still camer a b u2382fv descr iption dimension (units : mm) f eatures applications 01w095a october , 2001 absolute maxim um ratings (t a=25 c) *der ating : 4.5mw/ c f or oper ation abo v e t a=25 c *this product is not designed f or protection against r adioactiv e r a ys . *p o w er dissipation is the r ate when the ic is mounted on the board. *ic destr uction is not occurred, ho w e v er , oper ation can not be guar anteed. unit v mw c v applied v oltage input v oltage stor age temper ature r ange p o w er dissipation p ar ameter symbol limits v dd vin pd tstg ? 0.5 +7.0 ~ ? 0.5 v dd +0.5 ~ ? 30 +125 ~ 450 digital still camer a ssop-b16 9 8 16 1 0.1 6.4 0.3 4.4 0.2 5.0 0.2 0.15 0.1 0.22 0.1 0.65 1.15 0.1 0.3min. 0.1 1) gener ate cloc ks f or cds , usb with standard cloc k input 2) no e xter nal elements required 3) standard cloc ks apply to tw o kinds of ntsc/p al 4) p o w er do wn control in each 2-channel pll 5) single po w er supply of 3.3v oper ating 6) ssop-b16 small pac kage b u2382fv is a high-perf or mance 2-channel pll ic . pll circuit gener ates necessar y cloc ks b y inputting standard cloc ks of cr ystal oscillator from outside . changing a connection of wire can gener ate an y cloc ks required f or an y applications of users . jitter and s/n char acter istic has achie v ed almost the same high-quality sound and vision as oscillating module because of optimization of pll. f requency can be changed b y the inter nal dividing control.
p o w er supply v oltage v dd ? ? ? 3.0 3.6 v recommended oper ating conditions (t a=25 c) p ar ameter min. max. unit t yp . symbol input l v oltage r ange vil 0 0.2v dd v oper ating temper ature t opr ? ? 5 70 c output load cl ? ? 15 pf input h v oltage r ange 0.8v dd v dd v vih note) output frequency is deter mined b y the oper ation e xpression (f requency divide) input to xt al in. output at 27mhz input is sho wn abo v e . jitter is v alue when using time inter v al analyz er with 10000 sampling. ?| 1 ?j lo w and high limit v oltage in the schmitt tr igger input pin ha ving h ysteresis f eatures sho wn in ?| 3 diag r am. ?| 2 ?j time that output tak es to stabiliz e in the specific frequency r ange after the po w er supply reaches to 3.0v . ?| 3 ?j mak e ref erence to the diag r am. output h v oltage v oh 2.4 ? 0.2v dd ? ? ? ? ? ? ? ? 0.4 30 48.626786 70.937900 48.461539 71.877274 ? 0.4 ? 0.8v dd ? 45 ? v v v v v ma mhz v ol vthl vthh vh ys idd clk1_ll clk1_lh clk1_hl clk1_hh output l v oltage input thl *3 input thh *3 hysteresis width *3 oper ating circuit current clk1 ioh= ? 4.0ma iol=4.0ma *1 *1 vh ys=vthh ? vthl no load xt al 170/31/2 (xt al=17.734475mhz) xt al 360/45/2 (xt al=17.734475mhz) xt al 176/26/2 (xt al=14.318182mhz) xt al 502/50/2 (xt al=14.318182mhz) ? 47.998742 mhz clk2_l xt al 249/46/2 (xt al=17.734475mhz) electr ical char acter istics ( unless otherwise noted; t a=25 c , vcc=3.3v , xtal frequency=14.318182mhz) clk2 clk2_h 45 ? ? ? ? ? 47.998451 50 30 180 2.5 2.5 ? ? 55 ? ? ? ? 1 % psec psec nsec nsec msec duty jssd jsabs tr tf tloc k duty jitter ?e jitter min.-max. rise time f all time output loc k time xt al 295/44/2 (xt al=14.38182mhz) 1/2v dd test 1 ?e shor t time jitter min. ? max. 20% ~ 80% time of v dd 20% ~ 80% time of v dd *2 symbol min. max. unit conditions t yp . p ar ameter 0.2vdd 1/2vdd vthh vh ys input(v) output (v) vthl 0.8vdd bloc k diag r am 1 2 3 4 5 6 7 8 16 oe_clk1 clk1 clk1 output clk2 output h or l h or l h or l h or l sel nt_p al d vdd d vss clk2 oe_clk2 vdd2 vss2 ref_clk n t :14.38182mhz p al:17.734475mhz test1 a vdd a vss xt alin xt alout 15 14 13 12 11 10 9 b u2382fv
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