first gigabit per second cmos transceiver cores in the industry overview lsi logic s gigablaze cores are the first multi-gigabit per second cmos transceiver cores in the industry. they provide a full-duplex, point-to-point communications channel for gigabit speed serial interfaces. protocol independence enables the cores to be used with standard high-speed communications protocols to create a high-speed serial interface. applications for the cores include storage subsystems, network switches and routers, system area network (san) and high-speed backplanes. the gigablaze cores are optimally designed for use as a physical layer for high- speed protocols including fibre channel, gigabit ethernet, and the emerging system area network (san) standard. multiple gigablaze cores can be integrated into a single asic. combined with other lsi logic standards-based cores, such as merlin fibre channel, the tinyrisc and minirisc processors, and pci, the gigablaze core enables a completely new approach to high-performance, single- chip solution for increased differentiation and reduced chip count, power and cost. the third generation gigablaze transceiver is now available in lsi logic s g11 process technology, along with the g10 and 500k process technologies. description the gigablaze core consists of deserializer and serializer pattern and alignment circuitry. the deserializer receives a serial gigabit speed input encoded data stream and converts it into parallel data. this parallel data acts as an input for any high-speed protocol handler. likewise, encoded parallel data from the pro- tocol handler can be transmitted at gigabit speeds after being converted into a ser- ial stream by the serializer. the core transmitter serializes the parallel data with clock information embedded in it. the serialized output is a low-swing differential signal in nrz format. the receiver recovers data and the embedded clock from the serial data stream, performs byte synchronization and presents parallel data with respect to the recovered clock. the lsi logic coreware design program provides the complex building blocks, proven design methodology, technology and application support necessary to build a system on a chip, optimized uniquely for the target application. this single-chip approach reduces overall system costs and accelerates time to market. gigablaze transceiver cores gigablaze g11 core the gigablaze g11 core is lsi logic s third generation cmos serial transceiver core.the gigablaze g11 core transmits data up to 2.5 gbits/sec. serial transfer rate: 1.0625, 1.25, 2.125 and 2.5 gbits/sec asic process technology: g11, 2.5 v, 0.25-micron, cell-based cmos process parallel data interface: transmitter and receiver set independently for either 10 to 20 bits wide
figure 1. gigablaze block diagram gigablaze block diagram gigablaze technology provides a point-to-point, full-duplex, differential, serial communications link that transfers data at up to 2.5 gbits/sec. it is a protocol- independent serial interface with a direct interface option to optics, twinax line or a pcb trace. clock recovery and synchronization are included. as illustrated in figure 1 above, this cmos implementation is ideal for applications con- strained by power and size, and offers a competitive solution to the gaas and bicmos standard parts available today. high-speed protocols gigablaze technology provides a physical layer for emerging standard, high-speed communications protocols, such as fibre channel, gigabit ethernet, and the emerging system area network (san) as well as proprietary board-to-board or box-to-box serial communications. gigablaze transceiver cores features a gigabit high-speed serial interface cmos core; can be integrated with other industry- standard cores and user-defined logic for a system-on-a-chip solution supports serial transfer rates of up to 2.5 gbits/sec multiple cores can be integrated on a single asic supports full duplex operation self testability via serial loop back mode available in lsi logic s leading-edge, cmos technologies core behavioral models with timing information and simulation verification environment models available with complete test vector sets complete evaluation platforms available worldwide design resource center support tx clock generator serializer transmit buffer data/clock recovery rx clock generator receive buffer rxdata bist rbc clock txp txn rxp rxn receiver refclk or tbc txdata transmitter transceiver deserializer and data alignment
benefits reduces cost, chip count, pin count and power consumption; increases reliability, time to market and product differentiation meets the specific high bandwidth requirements of high-performance i/o saves area, reduces noise and enables higher integration facility for simultaneous transmit/receive transfers which improve system performance ensures easy testability, reduces development time high-density process maximizes on-chip integration ac verification, fast and accurate simulations; reduces test cost, time to market speeds system design design assistance available serial data rates (gbps) 1.0625 1.25 2.125 2.5 3.125 4.25 gigablaze next generation gigablaze g11 gigablaze g10 gigablaze 500k fibre channel gigabit ethernet system area network (san) *future extensions (black) gigablaze features 500k core g10 core g11 core manufacturing lc8500k, 3.3-volt, 0.5-micron (drawn) g10, 3.3-volt, 0.35-micron (drawn) g11, 2.5-volt, 0.25-micron (drawn) process technology 2-layer metal, cell-based cmos 3-layer metal, cell-based cmos 3-layer metal, cell-based cmos parallel data interface transmitter: 20-bits wide only transmitter: either 10- or 20-bits wide transmitter: 20-bits wide only receiver: either 10- or 20-bits wide receiver: either 10- or 20-bits wide receiver: either 10- or 20-bits wide serial transfer rates 1.0625 gbit/s 1.0625, 1.25 gbit/s 1.0625, 1.25, 2.125, 2.5 gbit/s termination external external internal blas generator separate hardmacro separate hardmacro internal to the transceiver core external package pins 13-pins for each core 13-pins for each core 12 pins for each core plus 5 pins for bias generator. bias plus 5 pins for bias generator. bias generator will support up to 8 cores. generator will support up to 8 cores. figure 2. gigablaze core specification support figure 3. three generations of migrated transceiver experience
contact information lsi logic corporation north american headquarters milpitas, ca tel: 408.433.8000 lsi logic europe ltd european headquarters united kingdom tel: 44.1344.426544 fax: 44.1344.481039 lsi logic kk headquarters tokyo, japan tel: 81.3.5463.7821 fax: 81.3.5463.7820 gigablaze transceiver cores lsi logic logo design, coreware and gigablaze are registered trademarks, and g11, merlin, tinyrisc, and minirisc are trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intel- lectual property rights of lsi logic or of third parties. copyright ?999 by lsi logic corporation. all rights reserved. order no. c20021.a 1099.1k ?printed in usa iso 9000 certified gigablaze core 1 gigablaze core 2 four-chip solution single-chip solution disk for- matter logic = > fc- al protocol chip tx 1 rx 1 tx 2 rx 2 disk for- matter logic merlin dl fibre channel protocol figure 4. single-chip disk controller diagram figure 5. gigabit ethernet diagram single-chip disk controller lsi logic s gigablaze technology reduces the number of chips required to imple- ment a disk controller. the standard parts solution contains up to four chips. using two gigablaze cores, the merlin dl fibre channel protocol core and disk formatter logic, this four-chip implementation is reduced to one chip and is illus- trated in figure 4 above. gigabit ethernet gigabit ethernet can drastically improve lan backbone throughput by providing 10 times the bandwidth of fast ethernet. in the example illustrated in figure 5 below, gigabit ethernet improves server access by providing a 1 gbit/s link from a fast ethernet switch to the server. lsi logic s gigablaze technology can serve as a physical layer for gigabit ethernet connections. visit our web site at: www.lsilogic.com/products/interface_cores/incgigblz
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