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db15-000193-00 september 2001 1 of 24 copyright ? 2001 by lsi logic corporation. all rights reserved. DPS9245EB evaluation board users guide contents 1 introduction 3 2 product and applications overview 3 3 driving the analog inputs 4 3.1 differential drive from a differential source 5 3.2 single-ended to differential con?uration (using ampli?rs) 6 3.3 single-ended to differential con?uration (transformer coupled) 7 3.4 true single-ended operation of the dps9245 7 3.5 suggested external signal sources and signal conditioning techniques 7 4 programmable gain ampli?r (pga) gain control 8 5 clock 9 5.1 dc-coupling the clock 9 5.2 ac-coupling the clock 9 6 16-bit parallel adc outputs 10 7 various digital inputs/outputs 10 7.1 oe 10 7.2 ovr_rng 10 7.3 resetb 10 7.4 busyb 11 8 power supplies 11 9 references, bandgap and common-mode voltage 12 9.1 adc references 13 9.2 bandgap/external bias capacitor and resistor 13 9.3 the common-mode voltage rxcmin 13 10 initializing the DPS9245EB board 14 11 layout guidelines 15 11.1 layers 15
2 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. 11.2 power planes 15 11.3 routing the 16 ?d output lines 15 11.4 signal isolation issues 15 11.5 high speed clock line 15 11.6 matching differential signals 16 11.7 adc references 16 11.8 supply bypass 16 11.9 critical placement 16 figures 1 functional block diagram of the dps9245 3 2 various options to drive the pga inputs 5 3 circuit options to drive the dps9245 with a low jitter clock source 9 4 power supply hook up to the evaluation board 12 5 external passive connections for the bandgap, references and common mode pins 13 6 top layer silk 18 7 plot of the top layer [signal] 19 8 plot of the second layer [ground] 20 9 plot of the third layer [power] 21 10 plot of the bottom layer [signal] 22 11 top level schematic of the dps9245e 23 tables 1 pga gain control 8 2 quick reference to the header options available 14 3 bill of materials (DPS9245EB, rev a) 17
DPS9245EB evaluation board 3 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. 1 introduction the DPS9245EB evaluation board is a platform to verify the performance of the dps9245, 16-bit, 5 megasamples/s adc. the purpose of this document is to provide complete details of the functionality and operation of the DPS9245EB. the application note will also focus on the equipment requirements and the various circuit options available on-board. this is followed by suggested guidelines for board layout. the top-level schematic of the board is shown in figure 11 . the board consists of 4 layers; the top and bottom are predominantly signal, the 2nd layer ground and the third layer for power supply. the plot for each layer is shown in figures 7 10 . the silk for the top layer is shown in figure 6 . in addition to the basic hardware (clocks, supplies and input signal generators), the user must also have a logic analyzer or some equivalent means to acquire digital data, along with fft processing software to fully evaluate the adc. 2 product and applications overview the dps9245 is a 16-bit adc with a maximum sampling rate of 5 megasamples/s. the combination of an integrated, on-chip low noise programmable gain ampli?r (pga), sample and hold function and internal reference makes the dps9245 a self-contained data acquisition sub-system. a functional diagram of the chip is shown in figure 1 . figure 1 functional block diagram of the dps9245 s/h and adc differential analog in (inp, inm) resetb 16 ovr_rng data ad[15:0] oe refclk vref low-noise pga (7 settings) gain[2:0]
4 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. the pga has an input-referred noise of 8 nv/mhz and a typical dynamic range of 100 db at the maximum pga gain of 20 db. the high level of integration, greater than 1 k ? input impedance of the pga, simple initialization and 16-bit parallel output interface synchronized to the sampling clock makes the dps9245 very user friendly. this versatile cmos adc has low power dissipation of 465 mw at the highest sampling rate and is available in a 44-lead lqfp. possible applications for this adc are listed below: ? analog front end for high-end dsp processors ? data acquisition ? automatic test equipment ? instrumentation ? mri, imaging ? high performance scanners and copiers ? dsl/copper line test equipment applications ? ccd cameras and video imaging ? wireless base station receivers 3 driving the analog inputs figure 2 shows the various hardware con?urations available on the evaluation board to drive the analog inputs of the adc. note: the ampli?r u4a is connected in unity gain. tapping the output from the noninverting terminal gives the best perfor- mance. this is not an error. r/c1 or r/c2 should be stuffed with a capacitor if the inputs are ac-coupled or stuffed with a 0 ? resistor if the inputs are dc-coupled. the common-mode voltage rxcmin is generated inter- nally.
DPS9245EB evaluation board 5 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. figure 2 various options to drive the pga inputs 3.1 differential drive from a differential source the dps9245 performs best when driven with a fully balanced differential signal between inp and inm centered on common-mode voltage rxcmin. balanced differential inputs can directly be connected to the smbs j7 (inp) and j8 (inm) bypassing the on-board ampli?rs and transformer. the center pins of headers jp9 and jp12 can also be used to interface with the pga inputs. driving differentially helps reduce the even order harmonics. the maximum peak to peak differential voltage swing between inp and inm should be no more than 5 vppd. if a differential source is not available, the board has two ways to convert a single-ended input signal into a differential one, as described in sections 3.2 and 3.3 . amp_-5v inp inm am p xfr am p xfr xfr enabl e rxcm in r17 1.24k r19 1k j8 jp9 1 2 3 r18 49.9 ? r20 1k j7 jp8 1 2 r2 2 1k u4a clc5602 2 3 1 u4b clc5602 6 5 7 8 4 jp11 1 2 jp12 1 2 3 t1 100mhz 1 2 3 4 5 6 7 8 r/c2 39nf c24 1.0 f r/c1 39nf u1 dps9245 inp 41 rxcmin 39 inm 42 rxin j6 amp_+5 v amp_-5v amp_+5v 8 4
6 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. 3.2 single-ended to differential con?uration (using ampli?rs) note: there is gain of 2 from j6 to the inputs of the pga when using the on-board ampli?rs. hence the inputs should be attenuated to compensate for this gain. the single-ended to differential conversion is done using comlinears dual low-noise clc5602 ampli?rs. 3.2.1 ac-coupled inputs to enable the ampli?rs: 1. keep header jp8 open. 2. connect the center pins of headers jp9 and jp12 to the pin marked amp i.e. short pins 2 and 3. 3. to ac-couple the inputs stuff r/c1 and r/c2 with 39 nf, low esr caps. using these dc blocking caps between the ampli?r outputs and the converter inputs a simple level-shifting scheme is implemented. w arning: this evaluation board is not optimized for dc-coupled inputs. the dps9245 has no loss of performance when operated either in the ac or dc-coupled mode. to fully evaluate the performance in the dc-coupled mode, lsi logic, recommends using the ad8138 low distortion differential adc driver. the ad8138 converts single-ended signals into differential ones and permits reference to an external common mode voltage. 3.2.2 dc-coupled inputs without level shift if the analog input signal is biased around the common-mode voltage, then to dc-couple the inputs stuff r/c1 and r/c2 with 0 ? resistors. follow steps [ 1 2 ] as described in section 3.2.1, ?c-coupled inputs. 3.2.3 3.2.3 dc-coupled inputs with level shift this mode of operation is possible when using the ad8138 ampli?r.
DPS9245EB evaluation board 7 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. 3.3 single-ended to differential con?uration (transformer coupled) to be used only when the input frequency is > 100 khz (the transformer is a dc block). 1. close header jp8. 2. connect the center pins of headers jp9 and jp12 to the pins marked xfr i.e., short pins 2 and 1. to ac-couple the inputs stuff r/c1 and r/c2 with 39 nf, low esr caps. the common-mode voltage is set internally. 3.4 true single-ended operation of the dps9245 even though the adc performs best when driven differentially, it is possible to drive the device single-ended. in that case, all of the above con?urations still apply to one of the two analog inputs; the other analog input should be connected to the rxcmin reference voltage, or to an external common mode reference. the performance with a single-ended input will depend strongly on the amount of common mode signal present at the chip rxinp/rxinm inputs. the on-chip pga performs a single-ended to differential conversion. hence, the signal entering the adc is balanced. 3.5 suggested external signal sources and signal conditioning techniques 1. krohn-hite model 4402b ultra pure wave sine wave oscillator. the low noise speci?ation makes it good for snr measurements. a typical measured value is 82 db for ? 1.0 dbfs input. signal bandwidth of the instrument is limited to 200 khz. 2. stanford research model-ds335 function generator. allows good linearity measurements over its entire frequency range. the bandwidth is limited to 3.1 mhz and signals distort when the amplitude exceeds 1.5 vpp. lsi logic uses an in-house board to generate balanced differential single and two-tone inputs. typical sfdr measurements for a 70 khz sinewave sampled at 5 mhz is > 90 db.
8 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. to maximize performance select sources with the lowest noise and thd numbers. lsi logic also recommends using a combination of series inline bandpass/lowpass ?ters to further condition the input signal for lab testing e.g., tte ?ters (kc4-75k-3.75k-50-720b and le182-1m-50-720b). 4 programmable gain ampli?r (pga) gain control the seven gain steps of the pga are set using the switch s2. when the switch is in the ?ff position, the bit value is ? and when in the ?n position the bit value is ?? ta b l e 1 shows the various settings for the switch. the default setting for gain[2:0] is 0b000 or 0 db. the gain setting 0b111 is not permitted. note: the input impedance changes with pga gain. . table 1 pga gain control gain2 gain1 gain0 pga gain [db] input resistance [k ? ] comments 0 0 0 0 5.57 min. gain 0 0 1 2.9 4.65 0 1 0 5.8 3.97 0 1 1 11.8 2.23 1 0 0 14.8 1.66 1 0 1 17.5 1.25 1 1 0 19.5 1 max. gain 1 1 1 not allowed
DPS9245EB evaluation board 9 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. 5 clock the dps9245 requires a low jitter (less than 10 ps), 50% duty cycle clock. lack of a good source will degrade linearity performance. the maximum clock frequency is 5 mhz. input the clock at the smb marked j5 as shown in figure 3 .a50 ? resistor terminates the input. if the source impedance of the generator is different, change the value of r12 accordingly. the signal is buffered (using u3) to clean up the rising and falling edges of the clock. a 33 ? damping resistor is placed in series with the refclk pin to prevent signal undershoot at the pin. the clock can either be ac or dc-coupled into the chip. figure 3 circuit options to drive the dps9245 with a low jitter clock source 5.1 dc-coupling the clock connect pins 2 and 4 of header jp5 (that is, pins marked dc and rclk). this is the default setting. 5.2 ac-coupling the clock connect pins 4 and 6 of header jp5 (that is, pins marked ac and rclk). dig_+3v dig_+3v clk in dc ext clk ac very short la clk c12 0.1 f c10 1nf r12 49.9 ? j5 c1 c11 10nf c3 1.0 f r9 4.99k r11 4.99k jp6 1 2 u3 74lcx125 a1 2 oe1 1 a2 5 oe2 4 a3 9 oe3 10 a4 oe4 gnd 7 y1 3 y2 6 y3 8 y4 11 vcc 14 r10 33.2 ? jp5 1 2 3 4 5 6 u1 dps9245 vdd_adio 6 refclk 7 oe 8 12 13
10 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. lsi logic uses the hewlett packard hp33120a, a 15 mhz function gen./awg. 6 16-bit parallel adc outputs the 16 adc outputs are buffered using a 16 bit cmos line driver (u5) and are available at header jp10. the ad0 (lsb) and ad15 (msb) bits have been labeled. pin 2 (marked la clk) of header jp6 provides a sampling clock for the logic analyzer. the outputs are valid when oe is high, or 3-stated when oe is low. the 16-bit external buffer [u5] is used to decrease the loading on the adc output pins and help minimize the output switching noise. the outputs ad[15:0] change on the rising edge of the refclk and are valid after 40 ns max. (see the dps9245 high-resolution adc with pga datasheet for more details.) 7 various digital inputs/outputs 7.1 oe oe is the output enable signal. the 16 adc outputs are valid when oe is high or 3-stated when oe is low. oe is pin 8 on-chip and is high during normal operation. 7.2 ovr_rng this signal is available at test pin tp5 (marked ovr rng). a high on this output signal indicates the range of the adc has been exceeded. to correct the situation, either attenuate the input to the pga or decrease the pga gain. ovr_rng is pin 25 on-chip and is low during normal operation. 7.3 resetb the push button switch s1 initializes the adc. this must be done after the power supplies and reference clock are stable. this signal can be monitored at pin 4 (marked resetb_in) of header jp7. a buffered version of resetb_in is fed directly to the chip. calibration starts on the
DPS9245EB evaluation board 11 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. rising edge of this signal. when resetb is low, registers (excluding the ones in the calibration circuitry) are initialized. resetb is level sensitive and should be held low for at least three clock cycles. resetb is pin 30 on-chip and is high during normal operation. 7.4 busyb this output signal is available at test pin tp4. this signal goes low on the rising edge of resetb. a low on this pin indicates the adc is in calibration/initialization mode. once the calibration is complete, busyb turns high and adc is ready for operation. busyb is pin 33 on-chip and is high during normal operation. 8 power supplies the DPS9245EB requires the following power supplies: ? +5 v for the analog and digital sections of the adc ? +5 and ? 5 v for the on-board ampli?rs ? +3.3 v for the adc outputs and on board logic ics. the board has an option to power the adc outputs with either +3.3 v or +5 v, using the header jp4 (marked adio voltage selector). this way the entire adc can be powered from a single +5 v supply, if needed. powering the adc outputs off the +3.3 v supplies reduces power consumption and noise generation due to output switching. the +5 v supply is split into three planes (using on-board low pass lc ?ters) minimizing the coupling between the analog and digital sections, buffer amp, and the adio supplies. the supply banana plugs are labeled +3 v, +5 v, ? 5 v and gnd. when using a bias resistor r21 of 1.43 k ? , the nominal current drawn from the three supplies is +5 v (100 ma), ? 5v( ? 10 ma) and +3 v (2 ma). w arning: ensure that the supplies are correctly hooked up and a return path is provided to ground (see figure 4 ). failure to do so could destroy the dps9245, as there are no supply clamping diodes on-board. when the on-board leds are
12 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. lit, the power supplies are correctly hooked up. do not exceed the supply voltage for any of the input pins. figure 4 power supply hook up to the evaluation board if the proposed application has separate analog and digital power supplies, lsi logic recommends connecting the vdd_adc (pins 28 and 44) to the analog section, while connecting vdd_adio (pin 6) and vddd_adc (pin 3 and 4) to the digital section. if the proposed application has separate analog and digital ground planes, lsi logic recommends connecting the gnd_adc (pins 1, 29 and 38) to the analog section, while connecting gnd_adio (pin 5) and gndd_adc (pin 2) to the digital section. all ground pins of the dps9245 are shorted to one common ground on the DPS9245EB evaluation board. 9 references, bandgap and common-mode voltage this section details the reference voltages and bandgap/bias settings for the board. 3 v +? 5 v +? 5 v +? + 3 v + 5 v ? 5 v gnd DPS9245EB j1 j3 j2 j4 user power supplies
DPS9245EB evaluation board 13 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. figure 5 external passive connections for the bandgap, references and common mode pins 9.1 adc references the adc full-scale reference voltages are generated on-chip. the high and low reference voltages are available at pins adc_refp (pin 37) and adc_refm (pin 36) respectively. the references are decoupled by connecting a 10 f low-esr/esl capacitor between the two pins (see figure 5 ). the voltage difference across these pins is nominally 2.5 v. note: the internal references of the dps9245 cannot be disconnected or overdriven. 9.2 bandgap/external bias capacitor and resistor connecting a precision resistor r21 to pin 35 (rext_rx) sets the power dissipation of the adc. trade-off between power dissipation and linearity at higher sampling rates (> 5 mhz) and/or for high input frequencies (greater than nyquist) is done by changing r21. as a general guideline rext_rx should always be in the range of 800 and to 3.0 k ? . rxbgcap (pin 34) is a voltage associated with the bandgap. the external capacitor c27 is used for noise ?tering. a value of 1 fis recommended. the default value of r21 is 1.43 k ? . 9.3 the common-mode voltage rxcmin this voltage is generated internally and is typically 2.40 v. for best results all analog inputs should be centered on this value. the maximum rxcm in c24 1.0 f jp11 1 2 r21 1.43k c27 1.0uf rx refm refp c25 0.1 f c26 10 f bgap u1 dps9245 rxcmin 39 rext_rx 35 rxbgcap 34 adc_refp 37 adc_refm 36 gnd_adc 38
14 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. output drive capability of rxcmin (pin39) is 47 a (50 k ? to ground). output impedance is typically 1 k ? , and a 1 f decoupling capacitor is used. 10 initializing the DPS9245EB board below is a set of basic debugging checks. 1. set adio, the digital output supply to 3.3 v [header jp4]. 2. dc-coupled reference clock [header jp5 and smb j5]. check amplitude and dc offset of the source. 3. pga gain set to 0 db [switch s2]. 4. analog inputs, driving the adc differentially [check jp12 and jp9, smb j6 and r/c1, r/c2]. check the amplitude of the input. check common-mode (~2.4 v) if the inputs are dc-coupled. 5. is power supply and return path to ground provided? are the leds lit? are the current speci?ations being met? 6. provide a clean clock supply at smb j5. 7. once clock and supplies are settled, initialize the adc by using the resetb push-button switch. 8. verify the dc voltage at test points marked bgap (1.25 v), rx (1.26 v), refp (3.65 v), and refm (1.15 v) and rxcmin (2.4 v). typical values included for reference only. 9. using a scope check the 16 adc outputs before and after the buffer u5. table 2 quick reference to the header options available header function jp4 digital output power supply selector jp5 ac or dc coupling for refclk jp9 and jp12 selecting on board transformer or ampli?r option jp8 enable transformer
DPS9245EB evaluation board 15 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. 11 layout guidelines please refer to figure 7 through figure 10 in combination with the following suggestions. 11.1 layers multilayer boards are recommended as they offer the advantages of reducing ground impedance and separating the sensitive analog signal from the noisy digital ones. four layers were used on the board and the layer sequence is signal/ground/power/signal. 11.2 power planes multiple power planes of +5 v, ? 5 v, and +3 v are used. this helps to isolate the sensitive signals from the switching digital signals. low pass lc ?ters have been used to isolate sections powered by the same supply. the ? 5 v is used to power the external ampli?r u4. the +3 v is used to power the on-board cmos logic ics and the 16-bit adc outputs. the buses back to the main supply jacks should be at least 100 mils wide, wider is better. 11.3 routing the 16 ?d output lines the routing for these digital wires has been done on one layer (top layer). constant jumping between the two outside signal layers will degrade the return path of the circulating current. 11.4 signal isolation issues the most sensitive analog pins are pin 34 through pin 42. these pins are inm, inp, rxcmin, adc_refp and adc_refm, rext_rx and rxbgcap. it is very important to keep the digital routing (?d outputs? far from these analog signals. 11.5 high speed clock line it is also important to keep the clock line refclk [pin7] isolated. the trace carrying the clock signal should be as short as possible. also
16 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. prevent crossing this trace with any varying analog or switching digital signals. 11.6 matching differential signals inp and inm are differential analog input signals and should be matched and balanced as well as possible. the smb jacks j7 and j8 should be grouped as a pair. 11.7 adc references keep all traces routed from these pins 36 and 37 (adc_refm and adc_refp) balanced and as short as possible. failure to do so will degrade the linearity of the adc. the most critical components are the decoupling capacitors, especially the 10 f capacitor between the reference outputs: adc_refp and adc_refm. place the capacitor as close as possible to the pins. 11.8 supply bypass the 1000 pf 0805 capacitors should be placed as close as possible to the vdd pins. 11.9 critical placement the capacitor (c27) and resistor (r21) connected to rxbgcap and rext_rx should be as close as possible to the main chip. traces from these pins to the passive components should be kept as short as possible and isolated from any noisy signals on-board.
DPS9245EB evaluation board 17 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. table 3 bill of materials (DPS9245EB, rev a) item reference part tol type pwr footprint manufacturer manufacture # qty 1 c1,c3,c24,c27 1.0 f 10% x7r 10 v 805 murata grm40x7r105k010 al 4 2 c2,c12,c13,c15, c17,c19,c23,c25, c30,c32 0.1 f 10% x7r 25 v 805 murata grm40x7r104k025 al 10 3 c4,c5,c6,c7,c8, c9,c26 10 f 80/20 * 16 v 1210 murata grm235y5v106z01 6al 7 4 c10,c14,c16,c18, c20,c22,c29,c31 1 nf 5% cog 50 v 805 murata grm40cog102j050 ad 8 5 c21,c11 10 nf 5% * 50 v 1206 panasonic ech-u1h103jb5 2 6 d1,d2,d3 red * * 20 ma smdled panasonic ln1271r 3 7 jp4,jp9,jp12 1 x 3 * * * hdr1x3 regal 4070-sh-3 3 8 jp5 2 x 3 * * * hdr2x3 regal 4071-dh-6 1 9 jp6,jp8,jp11,jp15 1 x 2 * * * hdr1x2 regal 4070-sh-2 4 10 jp7 2 x 2 * * * hdr2x2 regal 4071-dh-4 1 11 jp10 2 x 16 * * * hdr2x16 regal 4071-dh-32 1 12 j1,j2,j3,j4 banana jack_am * * * banana jack_ am johnson 108-0740-001 4 13 j5,j6,j7,j8 smb_413990-1-00 * * * smb amp 413990-1-00 4 14 l1,l2,l3,l4,l5,l6 3.3 h 5% * * 1210 delevan 1210-332j 6 15 r/c1,r/c2 39 nf 5% * 50 v 1210 panasonic ech-u1h393jb5 2 16 rp1,rp2 33 * * * rp16w bourns 4816p-t01-330 2 17 r1,r19,r20,r22 1 k ? 1% * 1/8 w 1206 panasonic erj-8enf1001v 4 18 r2,r3,r4,r5,r9, r11,r13,r14,r15,r 16 4.99 k ? 1% * 1/8 w 1206 panasonic erj-8enf4991v 10 19 r6,r7,r8 499 ? 1% * 1/8 w 1206 panasonic erj-8enf4990v 3 20 r10 33.2 ? 1% * 1/8 w 1206 panasonic erj-6enf33r2v 1 21 r18,r12 49.9 ? 1% * 1/8 w 1206 panasonic erj-8enf49r9v 2 22 r17 1.24 k ? 1% * 1/8 w 1206 panasonic erj-8enf1241 1 23 r21 1.43 k ? 1% * 1/8 w 1206 panasonic erj-8enf1431v 1 24 s1 evq-11g05r * * * small- push panasonic evq-11g05r 1
18 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. figure 6 top layer silk 25 s2 tpst * * * swdip6 candk ckn3002-nd 1 26 tp1,tp2,tp3,tp4,t p5 1514-2 * * * st1514 keystone 1514-2 5 27 t1 100 mhz * * * xform mini-circuits ttm01-1 1 28 u1 dps9245 * * * 44qfp lsi logic dps9245 1 29 u2 74hc14 * * * so14 fairchild 74hc14m 1 30 u3 74lcx125 * * * so14 fairchild 74lcx125 1 31 u4 clc5602 * * * so8 comlinear clc5602m 1 32 u5 74lcx16244 * * * ssop48 fairchild 74lcx16244mea 1 table 3 bill of materials (DPS9245EB, rev a) (cont.) item reference part tol type pwr footprint manufacturer manufacture # qty
DPS9245EB evaluation board 19 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. figure 7 plot of the top layer [signal]
20 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. figure 8 plot of the second layer [ground]
DPS9245EB evaluation board 21 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. figure 9 plot of the third layer [power]
22 of 24 DPS9245EB evaluation board db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. figure 10 plot of the bottom layer [signal]
DPS9245EB evaluation board 23 of 24 db15-000193-00 september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. figure 11 top level schematic of the dps9245e vdd_adc pin28 vdd_adc pin44 vddd_adc pin3&4 adc bypass vdd_adio pin6 gnd +3v +5v -5v ovr rng gnd probe p oints +3v +5v la clk clk in resetb_in dc ac oe_in ext clk busyb gain 0 (lsb) gain 1 inp inm amp xfr amp xfr rxin xfr enable power adio voltage selector ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad11 ad10 ad13 ad15 ad12 ad14 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 lsb msb adc outputs rxcmin last updated: 04/18/00 @ 2:40pm gain 2 (msb) reset switch very short rxin bias/ref power supplies / bypass circuits reset clock adc ouputs ana_+5v adio_v ana_+5v adio_v ana_+5v dig_+3v amp_-5v ana_+5v dig_+3v dig_+3v ana_+5v ana_+5v dig_+5v adio_v amp_+5v dig_+5v dig_+5v dig_+3v dig_+3v amp_+5v amp_-5v dig_+3v dig_+3v dig_+3v c6 10uf c5 10uf c7 10uf c9 10uf l5 3.3uh l2 3.3uh l3 3.3uh l6 3.3uh l1 3.3uh c4 10uf c20 1nf c18 1nf c21 10nf c16 1nf jp10 12 34 56 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c31 1nf u5 16 bit line d rive 74lcx16244 o0 2 o1 3 o2 5 o3 6 o4 8 o5 9 o6 11 o7 12 o8 13 o9 14 o10 16 o11 17 o12 19 o13 20 o14 22 o15 23 gnd1 15 gnd2 21 gnd3 28 gnd4 34 gnd5 39 gnd6 45 gnd7 4 gnd8 10 i0 47 i1 46 i2 44 i3 43 i4 41 i5 40 i6 38 i7 37 i8 36 i9 35 i10 33 i11 32 i12 30 i13 29 i14 27 i15 26 oe1 1 oe2 48 oe3 25 oe4 24 vcc1 7 vcc2 18 31 vcc3 vcc4 42 r17 1.24k c24 1.0uf r19 1k j8 jp9 1 2 3 r18 49.9 jp11 1 2 r20 1k j6 r21 1.43k r12 49.9 jp5 1 2 3 4 5 6 c3 1.0uf c11 10nf r/c1 39nf c10 1nf j5 r/c2 39nf jp12 1 2 3 j7 c27 1.0uf jp8 1 2 u1 dps9245 gain0 43 gain1 40 gain2 27 nc 31 nc 32 busyb 33 resetb 30 refclk 7 oe 8 inp 41 rxcmin 39 inm 42 rext_rx 35 rxbgcap 34 adc_refp 37 adc_refm 36 vdd_adc 28 vdd_adc 44 vddd_adc 3 vddd_adc 4 vdd_adio 6 gndd_adc 2 gnd_adc 1 gnd_adc 29 gnd_adc 38 gnd_adio 5 nc 26 ad0 9 ad1 10 ad2 11 ad3 12 ad4 13 ad5 14 ad6 15 ad7 16 ad8 17 ad9 18 ad10 19 ad11 20 ad12 21 ad13 22 ad14 23 ad15 24 ovr_rng 25 bgap rx refm refp r13 4.99k r11 4.99k r9 4.99k r22 1k u4a clc5602 2 3 1 8 4 c22 1nf u4b clc5602 6 5 7 8 4 c29 1nf c17 0.1uf c15 0.1uf c13 0.1uf c19 0.1uf c32 0.1uf c12 0.1uf c23 0.1uf c30 0.1uf c8 10uf c14 1nf d2 red d3 red c25 0.1uf c26 10uf rp1 33 rp2 33 jp6 1 2 r10 33.2 u3 74lcx125 a1 2 oe1 1 a2 5 oe2 4 a3 9 oe3 10 a4 12 oe4 13 gnd 7 y1 3 y2 6 y3 8 y4 11 vcc 14 s1 evq-11g05r no-mom-push c2 0.1uf c1 1.0uf r1 1k u2 74hc14 hex inverter i0 1 i1 3 i2 5 i3 9 i4 11 i5 13 gnd 7 o0 2 o1 4 o2 6 o3 8 o4 10 o5 12 vcc 14 r8 499 r7 r6 499 499 d1 red jp4 1 2 3 l4 3.3uh t1 100mhz 1 2 3 4 5 6 7 8 j4 j2 j1 j3 jp7 1 2 3 4 r2 4.99k r3 4.99k r4 4.99k r5 4.99k s2 tpst 1 2 3 4 5 6 r16 4.99k r14 4.99k r15 4.99k jp15 1 2 tp5 tp4 tp1 tp2 tp3
to receive product literature, visit us at http://www.lsilogic.com. 24 of 24 DPS9245EB evaluation board september 2001 copyright ? 2001 by lsi logic corporation. all rights reserved. lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or of third parties. this document is preliminary. as such, it contains data derived from functional simulations and performance estimates. lsi logic has not veri?d the functional descriptions or electrical and mechanical speci?ations using production parts. the lsi logic logo design is a registered trademark of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. doc. no. db15-000193-00 headquarters lsi logic corporation north american headquarters milpitas ca tel: 408.433.8000 fax: 408.433.8989 lsi logic europe ltd european headquarters bracknell england tel: 44.1344.426544 fax: 44.1344.481039 lsi logic k.k. headquarters tokyo japan tel: 81.3.5463.7821 fax: 81.3.5463.7820 iso 9000 certified notes

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