? semiconductor components industries, llc, 2001 january, 2001 rev. 2 1 publication order number: mc74vhct00a/d mc74vhct00a quad 2-input nand gate the mc74vhct00a is an advanced high speed cmos 2input nand gate fabricated with silicon gate cmos technology. it achieves high speed operation while maintaining cmos low power dissipation. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. the device input is compatible with ttltype input thresholds and the output has a full 5 v cmos level output swing. the input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logiclevel translator from 3.0 v cmos logic to 5.0 v cmos logic or from 1.8 v cmos logic to 3.0 v cmos logic while operating at the highvoltage power supply. the mc74vhct00a input structure provides protection when voltages up to 7 v are applied, regardless of the supply voltage. this allows the mc74vhct00a to be used to interface 5 v circuits to 3 v circuits. the output structures also provide protection when v cc = 0 v. these input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. ? high speed: t pd = 5.0 ns (typ) at v cc = 5 v ? low power dissipation: i cc = 2 m a (max) at t a = 25 c ? ttlcompatible inputs: v il = 0.8 v; v ih = 2.0 v ? power down protection provided on inputs and outputs ? balanced propagation delays ? designed for 3.0 v to 5.5 v operating range ? low noise: v olp = 0.8 v (max) ? pin and function compatible with other standard logic families ? chip complexity: 48 fets or 12 equivalent gates tssop14 dt suffix case 948g 14 1 device package shipping mc74vhct00ad soic14 48 units/rail mc74vhct00adr2 soic14 2500 units/reel mc74vhct00adt tssop14 96 units/rail mc74vhct00adtel tssop14 2000 units/reel mc74vhct00am soic eiaj14 48 units/rail mc74vhct00amel soic eiaj14 2000 units/reel mc74vhct00adtr2 tssop14 2000 units/reel http://onsemi.com ordering information soic14 d suffix case 751a marking diagrams vhct00a awlyyww vhct 00a awlyww vhct00a alyw soic eiaj14 m suffix case 965 14 1 14 1 a = assembly location l, wl = wafer lot y, yy = year w, ww = work week
mc74vhct00a http://onsemi.com 2 figure 1. pin assignment (top view) 13 14 12 11 10 9 8 2 1 34567 v cc b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2 gnd figure 2. logic diagram 3 y1 1 a1 2 b1 6 y2 4 a2 5 b2 8 y3 9 a3 10 b3 11 y4 12 a4 13 b4 y = ab l l h h l h l h function table inputs output ab h h h l y figure 3. iec logic diagram 3 a1 b1 & 6 8 11 1 2 a2 b2 4 5 a3 b3 9 10 a4 b4 12 13 y1 y2 y3 y4 pin assignment 1 2 3 out y1 in a1 in b1 4 5 in b2 in a2 6 7 8 out y3 out y2 gnd 9 in b3 in a3 10 11 12 in a4 out y4 13 14 v cc in b4
mc74vhct00a http://onsemi.com 3 maximum ratings (note 1.) symbol characteristics value unit v cc dc supply voltage 0.5 to +7.0 v v in dc input voltage 0.5 to +7.0 v v out dc output voltage v cc = 0 high or low state 0.5 to 7.0 0.5 to v cc + 0.5 v i ik input diode current 20 ma i ok output diode current v out < gnd; v out > v cc +20 ma i out dc output current, per pin +25 ma i cc dc supply current, v cc and gnd +50 ma ???? ???? p d ????????????????? ????????????????? power dissipation in still air, soic packages (note 2.) tssop package (note 2.) ?????? ?????? 500 450 ??? ??? mw t l lead temperature, 1 mm from case for 10 s 260 c t stg storage temperature 65 to +150 c v esd esd withstand voltage human body model (note 3.) machine model (note 4.) charged device model (note 5.) > 2000 > 200 > 3000 v i latchup latchup performance above v cc and below gnd at 125 c (note 6.) 300 ma * absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolutemaximumrated co nditions is not implied. 1. maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolutemaximumrated conditions is not implied. functional operation should be restricted to the recommended operating conditions. 2. derating soic packages: 7 mw/ c from 65 to 125 c tssop package: 6.1 mw/ c from 65 to 125 c 3. tested to eia/jesd22a114a 4. tested to eia/jesd22a115a 5. tested to jesd22c101a 6. tested to eia/jesd78 recommended operating conditions symbol characteristics min max unit v cc dc supply voltage 3.0 5.5 v v in dc input voltage 0.0 5.5 v v out dc output voltage vcc = 0 high or low state 0.0 0.0 5.5 v cc v t a operating temperature range 55 +125 c t r , t f input rise and fall time v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v 0 0 100 20 ns/v this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, pre- cautions must be taken to avoid applications of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must al- ways be tied to an appropri- ate logic voltage level (e.g., either gnd or v cc ). un- used outputs must be left open.
mc74vhct00a http://onsemi.com 4 the ja of the package is equal to 1/derating. higher junction temperatures may affect the expected lifetime of the device per the ta ble and figure below. device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 1 1 10 100 1000 time, years normalized failure rate t j = 80 c t j = 90 c t j = 100 c t j = 110 c t j = 130 c t j = 120 c failure rate of plastic = ceramic until intermetallics occur figure 4. failure rate vs. time junction temperature dc electrical characteristics v cc t a = 25 c t a 85 c t a 125 c symbol parameter test conditions (v) min typ max min max min max unit v ih minimum highlevel input voltage 3.0 4.5 5.5 1.4 2.0 2.0 1.4 2.0 2.0 1.4 2.0 2.0 v v il maximum lowlevel input voltage 3.0 4.5 5.5 0.53 0.8 0.8 0.53 0.8 0.8 0.53 0.8 0.8 v v oh minimum highlevel output voltage v v v v in = v ih or v il i oh = 50 m a 3.0 4.5 2.9 4.4 3.0 4.5 2.9 4.4 2.9 4.4 v g v in = v ih or v il v in = v ih or v il i oh = 4 ma i oh = 8 ma 3.0 4.5 2.58 3.94 2.48 3.80 2.34 3.66 v v ol maximum lowlevel output voltage v v v v in = v ih or v il i ol = 50 m a 3.0 4.5 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 v g v in = v ih or v il v in = v ih or v il i ol = 4 ma i ol = 8 ma 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 v i in maximum input leakage current v in = 5.5 v or gnd 0 to 5.5 0.1 1.0 1.0 m a i cc maximum quiescent supply current v in = v cc or gnd 5.5 2.0 20 40 m a i cct quiescent supply current input: v in = 3.4 v 5.5 1.35 1.50 1.65 ma i opd output leakage current v out = 5.5 v 0.0 0.5 5.0 10 m a
mc74vhct00a http://onsemi.com 5 ????????????????????????????????? ????????????????????????????????? ac electrical characteristics c load = 50 pf, input t r = t f = 3.0 ns ???? ???? ?????? ?????? ??????????? ??????????? ?????? ?????? t a = 25 c ????? ????? t a 85 c ????? ????? t a 125 c ?? ?? ???? ???? symbol ?????? ?????? parameter ??????????? ??????????? test conditions ?? ?? min ??? ??? typ ??? ??? max ??? ??? min ??? ??? max ??? ??? min ??? ??? max ?? ?? unit ???? ? ?? ? ???? t plh , t phl ?????? ? ???? ? ?????? maximum propogation delay, itabty ??????????? ? ????????? ? ??????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ?? ?? ?? ??? ? ? ? ??? 4.1 5.5 ??? ? ? ? ??? 10.0 13.5 ??? ? ? ? ??? ??? ? ? ? ??? 11.0 15.0 ??? ? ? ? ??? ??? ? ? ? ??? 13.0 17.5 ?? ?? ?? ns ???? ???? ?????? ?????? gy input a or b to y ??????????? ??????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ?? ?? ??? ??? 3.1 3.6 ??? ??? 6.9 7.9 ??? ??? ??? ??? 8.0 9.0 ??? ??? ??? ??? 9.5 10.5 ?? ?? ???? ? ?? ? ???? c in ?????? ? ???? ? ?????? maximum input capacitance ??????????? ? ????????? ? ??????????? ?? ?? ?? ??? ? ? ? ??? 5.5 ??? ? ? ? ??? 10 ??? ? ? ? ??? ??? ? ? ? ??? 10 ??? ? ? ? ??? ??? ? ? ? ??? 10 ?? ?? ?? pf typical @ 25 c, v cc = 5.0 v c pd power dissipation capacitance (note 7.) 17 pf 7. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc . c pd is used to determine the noload dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc . noise characteristics (input t r = t f = 3.0ns, c l = 50pf, v cc = 5.0v, measured in so package) t a = 25 c symbol characteristic typ max unit v olp quiet output maximum dynamic v ol 0.4 0.8 v v olv quiet output minimum dynamic v ol 0.4 0.8 v v ihd minimum high level dynamic input voltage 2.0 v v ild maximum low level dynamic input voltage 0.8 v 3.0 v gnd 50% 50% v cc a or b y t phl t plh *includes all probe and jig capacitance c l * test point device under test output v oh v ol figure 5. switching waveforms figure 6. test circuit input figure 7. input equivalent circuit output figure 8. output equivalent circuit * *parastic diode
mc74vhct00a http://onsemi.com 6 package dimensions d suffix soic package case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 dt suffix tssop package case 948g01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ??? ??? ??? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 14x ref k n n
mc74vhct00a http://onsemi.com 7 m suffix soic eiaj package case 96501 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z
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