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features ? single power supply operation - low voltage range: 2.7 v - 3.6 v ? memory organization - pm39lv512: 64k x 8 (512 kbit) - PM39LV010: 128k x 8 (1 mbit) - pm39lv020: 256k x 8 (2 mbit) - pm39lv040: 512k x 8 (4 mbit) high performance read - 55/70 ns access time cost effective sector/block architecture - uniform 4 kbyte sectors - uniform 64 kbyte blocks (sector group - except pm39lv512) data# polling and toggle bit features hardware data protection automatic erase and byte program - build-in automatic program verification - typical 16 s/byte programming time - typical 55 ms sector/block/chip erase time low power consumption - typical 4 ma active read current - typical 8 ma program/erase current - typical 0.1 a cmos standby current high product endurance - guarantee 100,000 program/erase cycles per single sector (preliminary) - minimum 20 years data retention industrial standard pin-out and packaging - 32-pin (8 mm x 14 mm) vsop - 32-pin plcc - optional lead-free (pb-free) package general description the pm39lv512/010/020/040 are 512 kbit/1 mbit/2 mbit/4 mbit 3.0 volt-only flash memories. these devices are designed to use a single low voltage, range from 2.7 volt to 3.6 volt, power supply to perform read, erase and program operations. the 12.0 volt v pp power supply for program and erase operations are not required. the devices can be programmed in standard eprom programmers as well. the memory array of pm39lv512 is divided into uniform 4 kbyte sectors for data or code storage. the memory arrays of PM39LV010/020/040 are divided into uniform 4 kbyte sectors or uniform 64 kbyte blocks (sector group - consists of sixteen adjacent sectors). the sector or block erase feature allows users to flexibly erase a memory area as small as 4 kbyte or as large as 64 kbyte by one single erase operation without affecting the data in others. the chip erase feature allows the whole memory array to be erased in one single erase operation. the devices can be programmed on a byte-by-byte basis after performing the erase operation. the devices have a standard microprocessor interface as well as a jedec standard pin-out/command set. the program operation is executed by issuing the program command code into command register. the internal control logic automatically handles the programming voltage ramp-up and timing. the erase operation is executed by issuing the chip erase, block, or sector erase command code into command register. the internal control logic automatically handles the erase voltage ramp-up and timing. the preprogramming on the array which has not been programmed is not required before an erase operation. the devices offer data# polling and toggle bit functions, the progress or completion of program and erase operations can be detected by reading the data# polling on i/o7 or the toggle bit on i/o6. the pm39lv512/010/020/040 are manufactured on pmc?s advanced nonvolatile cmos technology, p-flash?. the devices are offered in 32-pin vsop and plcc packages with access time of 55 and 70 ns. pmc 512 kbit / 1mbit / 2mbit / 4mbit 3.0 volt-only cmos flash memory programmable microelectronics corp. issue date: december, 2003 rev:1.2 pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 1
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 2 connection diagrams 32-pin plcc 20 19 18 17 16 15 14 5 6 7 8 9 10 11 12 13 1 2 3 4323130 a12 a15 nc v cc we# nc i/o1 gnd i/o2 i/o3 i/o4 i/o5 i/o6 i/o0 a0 a1 a2 a3 a4 a5 a6 a7 29 28 27 26 25 24 23 22 21 a14 a13 a8 a9 a11 oe# a10 ce# i/o7 a14 a13 a8 a9 a11 oe# a10 ce# i/o7 a14 a13 a8 a9 a11 oe# a10 ce# i/o7 a14 a13 a8 a9 a11 oe# a10 ce# i/o7 i/o1 gnd i/o2 i/o3 i/o4 i/o5 i/o6 i/o1 gnd i/o2 i/o3 i/o4 i/o5 i/o6 i/o1 gnd i/o2 i/o3 i/o4 i/o5 i/o6 i/o0 a0 a1 a2 a3 a4 a5 a6 a7 i/o0 a0 a1 a2 a3 a4 a5 a6 a7 i/o0 a0 a1 a2 a3 a4 a5 a6 a7 a12 a15 v cc we# nc nc nc a12 a15 v cc we# a12 a15 v cc we# a16 a16 a16 a18 a17 a17 nc 39lv512 39lv010 39lv020 39lv040 39lv040 39lv020 39lv010 39lv512 39lv512 39lv010 39lv020 39lv040 39lv040 39lv020 39lv010 39lv512 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin vsop i/o4 oe# a10 ce# i/o7 i/o6 i/o5 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 39lv512 39lv512 a11 a9 a8 a13 a14 we# v cc nc a15 a12 a7 a6 a5 a4 nc nc 39lv040 a11 a9 a8 a13 a14 we# v cc a15 a12 a7 a6 a5 a4 a16 a18 a17 39lv020 a11 a9 a8 a13 a14 we# v cc nc a15 a12 a7 a6 a5 a4 a16 a17 39lv010 a11 a9 a8 a13 a14 we# v cc nc a15 a12 a7 a6 a5 a4 a16 nc i/o4 oe# a10 ce# i/o7 i/o6 i/o5 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 39lv040 i/o4 oe# a10 ce# i/o7 i/o6 i/o5 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 39lv020 i/o4 oe# a10 ce# i/o7 i/o6 i/o5 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 39lv010
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 3 product ordering information pm39l v0x0 -70 j c e temperature range c = commercial (0 c to +70 c) package type j = 32-pin plastic j-leaded chip carrier (32j) v = 32-pin thin small outline package (vsop - 8 mm x 14 mm)(32v) speed option pmc device number pm39lv512 (512 kbit) PM39LV010 (1 mbit) pm39lv020 (2 mbit) pm39lv040 (4 mbit) r e b m u n t r a p t c c a ) s n ( e g a k c a pe g n a r e r u t a r e p m e t e c j 0 7 - 2 1 5 v l 9 3 m p 0 7 j 2 3 l a i c r e m m o c ) c 0 7 + o t c 0 ( c j 0 7 - 2 1 5 v l 9 3 m p e c v 0 7 - 2 1 5 v l 9 3 m p v 2 3 c v 0 7 - 2 1 5 v l 9 3 m p e c j 0 7 - 0 1 0 v l 9 3 m p 0 7 j 2 3 c j 0 7 - 0 1 0 v l 9 3 m p e c v 0 7 - 0 1 0 v l 9 3 m p v 2 3 c v 0 7 - 0 1 0 v l 9 3 m p e c j 0 7 - 0 2 0 v l 9 3 m p 0 7 j 2 3 c j 0 7 - 0 2 0 v l 9 3 m p e c v 0 7 - 0 2 0 v l 9 3 m p v 2 3 c v 0 7 - 0 2 0 v l 9 3 m p e c j 0 7 - 0 4 0 v l 9 3 m p 0 7 j 2 3 c j 0 7 - 0 4 0 v l 9 3 m p e c v 0 7 - 0 4 0 v l 9 3 m p v 2 3 c v 0 7 - 0 4 0 v l 9 3 m p environmental attribute e = lead-free (pb-free) package blank = standard package
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 4 pin descriptions l o b m y se p y tn o i t p i r c s e d a - 0 a s m ) 1 ( t u p n i y l l a n r e t n i e r a s e s s e r d d a . t u p n i s e s s e r d d a y r o m e m r o f : s t u p n i s s e r d d a . e l c y c e t i r w a g n i r u d # e w f o e g d e g n i l l a f e h t n o d e h c t a l # e ct u p n i r o f s e i r t i u c r i c l a n r e t n i s ' e c i v e d e h t s e t a v i t c a w o l s e o g # e c : e l b a n e p i h c o t n i s e h c t i w s d n a e c i v e d e h t s t c e l e s e d h g i h s e o g # e c . n o i t a r e p o e c i v e d . n o i t p m u s n o c r e w o p e h t e c u d e r o t e d o m y b d n a t s # e wt u p n i . w o l e v i t c a s i # e w . n o i t a r e p o e t i r w r o f e c i v e d e h t e t a v i t c a : e l b a n e e t i r w # e ot u p n i # e o . e l c y c d a e r a g n i r u d s r e f f u b t u p t u o s ' e c i v e d e h t l o r t n o c : e l b a n e t u p t u o . w o l e v i t c a s i 7 o / i - 0 o / i / t u p n i t u p t u o a t a d t u p t u o r o e l c y c e t i r w a g n i r u d a t a d / d n a m m o c t u p n i : s t u p t u o / s t u p n i a t a d . d e l b a s i d e r a # e o n e h w e t a t s - i r t o t t a o l f s n i p o / i e h t . e l c y c d a e r a g n i r u d v c c y l p p u s r e w o p e c i v e d d n gd n u o r g c nn o i t c e n n o c o n note: 1. a ms is the most significant address where a ms = a15 for pm39lv512, a16 for PM39LV010, a17 for pm39lv020, and a18 for pm39lv040.
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 5 block diagram device operation read operation the access of pm39lv512/010/020/040 are similar to eprom. to read data, three control functions must be satisfied: ce# is the chip enable and should be pulled low ( v il ). oe# is the output enable and should be pulled low ( v il ). we# is the write enable and should remains high ( v ih ) . product identification the product identification mode can be used to identify the manufacturer and the device through hardware or software read id operation. see table 1 for pmc manu- facturer id and device id. the hardware id mode is acti- vated by applying a 12.0 volt on a9 pin, typically used by an external programmer for selecting the right pro- gramming algorithm for the devices. refer to table 2 for bus operation modes. the software id mode is acti- vated by a three-bus-cycle command. see table 3 for software command definition. we# ce# oe# command register ce,oe logic a0-a ms erase/program voltage generator high voltage switch i/o0-i/o7 i/o buffers data latch sense amp y-gating memory array address latch y-decoder x-decoder byte programming the programming is a four-bus-cycle operation and the data is programmed into the devices (to a logical ? 0 ? ) on a byte-by-byte basis. see table 3 for software com- mand definition. a program operation is activated by writ- ing the three-byte command sequence followed by pro- gram address and one byte of program data into the devices. the addresses are latched on the falling edge of we# or ce# whichever occurs later, and the data are latched on the rising edge of we# or ce# whichever occurs first. the internal control logic automatically handles the internal programming voltages and timing. a data ? 0 ? can not be programmed back to a ? 1 ? . only erase operation can convert the ? 0 ? s to ? 1 ? s. the data# polling on i/o7 or toggle bit on i/o6 can be used to detect the progress or completion of a program cycle.
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 6 device operation (continued) chip erase the entire memory array can be erased through a chip erase operation. pre-programs the devices are not required prior to a chip erase operation. chip erase starts immediately after a six-bus-cycle chip erase command sequence. all commands will be ignored once the chip erase operation has started. the devices will return to standby mode after the completion of chip erase. sector and block erase the memory array of pm39lv512/010/020/040 are or- ganized into uniform 4 kbyte sectors. a sector erase operation allows to erase any individual sector without affecting the data in others. the memory array of PM39LV010/020/040, excluding pm39lv512, are also organized into uniform 64 kbyte blocks (sector group - consists of sixteen adjacent sectors). a block erase operation allows to erase any individual block. the sec- tor or block erase operation is similar to chip erase. i/o7 data# polling the pm39lv512/010/020/040 provide a data# polling feature to indicate the progress or completion of a pro- gram and erase cycles. during a program cycle, an at- tempt to read the devices will result in the complement of the last loaded data on i/o7. once the program op- eration is completed, the true data of the last loaded data is valid on all outputs. during a sector, block, or chip erase cycle, an attempt to read the device will re- sult a ? 0 ? on i/o7. after the erase operation is completed, an attempt to read the device will result a ? 1 ? on i/o7. i/o6 toggle bit the pm39lv512/010/020/040 also provide a toggle bit feature to detect the progress or completion of a pro- gram and erase cycles. during a program or erase cycle, an attempt to read data from the device will result a toggling between ? 1 ? and ? 0 ? on i/o6. when the program or erase operation is complete, i/o6 will stop toggling and valid data will be read. toggle bit may be accessed at any time during a program or erase cycle. hardware data protection hardware data protection protects the devices from un- intentional erase or program operation. it is performed in the following ways: (a) v cc sense: if v cc is below 1.8 v (typical), the write operation is inhibited. (b) write in- hibit: holding any of the signal oe# low, ce# high, or we# high inhibits a write cycle. (c) noise filter: pulses of less than 5 ns (typical) on the we# or ce# input will not initiate a write operation. n o i t a c i f i t n e d i t c u d o r pa t a d d i r e r u t c a f u n a mh d 9 : d i e c i v e d 2 1 5 v l 9 3 m ph b 1 0 1 0 v l 9 3 m ph c 1 0 2 0 v l 9 3 m ph d 3 0 4 0 v l 9 3 m ph e 3 table 1. product identification
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 7 y t i s n e d y r o m e mk c o l b ) 1 ( e z i s k c o l b ) s e t y b k ( r o t c e s e z i s r o t c e s ) s e t y b k ( e g n a r s s e r d d a t i b k 2 1 5 t i b m 1 t i b m 2 t i b m 4 0 k c o l b ) 2 ( 4 6 0 r o t c e s4 h f f f 0 0 - h 0 0 0 0 0 1 r o t c e s4 h f f f 1 0 - h 0 0 0 1 0 :: : 5 1 r o t c e s4 h f f f f 0 - h 0 0 0 f 0 1 k c o l b4 6 6 1 r o t c e s4 h f f f 0 1 - h 0 0 0 0 1 7 1 r o t c e s4 h f f f 1 1 - h 0 0 0 1 1 :: : 1 3 r o t c e s4 h f f f f 1 - h 0 0 0 f 1 2 k c o l b4 6 "" h f f f f 2 - h 0 0 0 0 2 3 k c o l b4 6 "" h f f f f 3 - h 0 0 0 0 3 4 k c o l b4 6 "" h f f f f 4 - h 0 0 0 0 4 5 k c o l b4 6 "" h f f f f 5 - h 0 0 0 0 5 6 k c o l b4 6 "" h f f f f 6 - h 0 0 0 0 6 7 k c o l b4 6 "" h f f f f 7 - h 0 0 0 0 7 sect or/block address t able notes: 1. a block is a 64 kbyte sector group which consists of sixteen adjecent sectors of 4 kbyte each. 2. block erase feature is available for PM39LV010/020/040 only. the chip erase command should be used to erase the block 0 for the pm39lv512.
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 8 command definition table 3. software command definition d n a m m o c e c n e u q e s s u b e l c y c s u b t s 1 e l c y c a t a d r d d a s u b d n 2 e l c y c a t a d r d d a s u b d r 3 e l c y c a t a d r d d a s u b h t 4 e l c y c a t a d r d d a s u b h t 5 e c l y c a t a d r d d a s u b h t 6 e l c y c a t a d r d d a d a e r1d r d d a t u o e s a r e p i h c6h a a h 5 5 5h 5 5 h a a 2h 0 8 h 5 5 5h a a h 5 5 5h 5 5 h a a 2h 0 1 h 5 5 5 e s a r e r o t c e s6h a a h 5 5 5h 5 5 h a a 2h 0 8 h 5 5 5h a a h 5 5 5h 5 5 h a a 2a s ) 1 ( h 0 3 e s a r e k c o l b6h a a h 5 5 5h 5 5 h a a 2h 0 8 h 5 5 5h a a h 5 5 5h 5 5 h a a 2a b ) 2 ( h 0 5 m a r g o r p e t y b4h a a h 5 5 5h 5 5 h a a 2h 0 a h 5 5 5d r d d a n i y r t n e d i t c u d o r p3h a a h 5 5 5h 5 5 h a a 2h 0 9 h 5 5 5 t i x e d i t c u d o r p ) 3 ( 3h a a h 5 5 5h 5 5 h a a 2h 0 f h 5 5 5 t i x e d i t c u d o r p ) 3 ( 1h 0 f h x x x notes: 1. sa = sector address of the sector to be erased. 2. ba = block address of the block to be erased. 3. either one of the product id exit command can be used. operating modes notes: 1. x can be v il , v ih or addresses. 2. a ms = most significant address; a ms = a15 for pm39lv512, a16 for PM39LV010, a17 for pm39lv020, and a18 for pm39lv040. table 2. bus operation modes e d o m# e c# e o# e ws s e r d d ao / i d a e rv l i v l i v h i x ) 1 ( d t u o e t i r wv l i v h i v l i xd n i y b d n a t sv h i xx x z h g i h e l b a s i d t u p t u oxv h i xx z h g i h n o i t a c i f i t n e d i t c u d o r p e r a w d r a h v l i v l i v h i a - 2 a s m ) 2 ( == 9 a , x v h ) 3 ( , v = 1 a l i v = 0 a , l i d i r e r u t c a f u n a m a - 2 a s m ) 2 ( = 9 a , x = v h ) 3 ( , v = 1 a l i v = 0 a , h i d i e c i v e d 3. v h = 12.0 v 0.5 v.
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 9 device operations flowcharts automatic programming chart 1. automatic programming flowchart start load data aah to address 555h load data 55h to address 2aah load data a0h to address 555h load program data to program address i/o7 = data? or i/o6 stop toggle? last address? programming completed no no yes yes address increment
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 10 automatic erase chart 2. automatic erase flowchart device operations flowcharts (continued) start write sector, block, or chip erase command data = ffh? or i/o6 stop toggle? erasure completed yes no sector erase command load data aah to address 555h load data 55h to address 2aah load data 80h to address 555h load data aah to address 555h load data 55h to address 2aah load data 10h to address 555h load data aah to address 555h load data 55h to address 2aah load data 80h to address 555h load data aah to address 555h load data 55h to address 2aah load data 30h to sa chip erase command block erase command load data aah to address 555h load data 55h to address 2aah load data 80h to address 555h load data aah to address 555h load data 55h to address 2aah load data 50h to ba
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 11 software product identification exit load data aah to address 555h load data 55h to address 2aah load data 90h to address 555h enter product identification mode (1,2) load data aah to address 555h load data 55h to address 2aah load data f0h to address 555h exit product identification mode (3) load data f0h to address xxxh exit product identification mode (3) or chart 3. software product identification entry/exit flowchart software product identification entry device operations flowcharts (continued) notes: 1. the device will enter product identification mode after excuting the product id entry command. 2. under product identification mode, the manufacturer id and device id of devices can be read at address x0000h and x0001h where x = don ? t care. 3. the device returns to standby operation.
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 12 s a i b r e d n u e r u t a r e p m e t c 5 2 1 + o t c 5 6 - e r u t a r e p m e t e g a r o t s c 5 2 1 + o t c 5 6 - e r u t a r e p m e t g n i r e d l o s d a e l t n u o m e c a f r u s e g a k c a p d r a d n a t ss d n o c e s 3 c 0 4 2 e g a k c a p e e r f - d a e ls d n o c e s 3 c 0 6 2 n i p 9 a t p e c x e s n i p l l a n o d n u o r g o t t c e p s e r h t i w e g a t l o v t u p n i ) 2 ( v o t v 5 . 0 - c c v 5 . 0 + n i p 9 a n o d n u o r g o t t c e p s e r h t i w e g a t l o v t u p n i ) 3 ( v 0 . 3 1 + o t v 5 . 0 - d n u o r g o t t c e p s e r h t i w e g a t l o v t u p t u o l l a v o t v 5 . 0 - c c v 5 . 0 + v c c ) 2 ( v 0 . 6 + o t v 5 . 0 - dc and ac operating range r e b m u n t r a p 0 4 0 / 0 2 0 / 0 1 0 / 2 1 5 v l 9 3 m p e r u t a r e p m e t g n i t a r e p o c 0 7 o t c 0 y l p p u s r e w o p c c v v 6 . 3 - v 7 . 2 absolute maximum ratings (1) notes: 1. stresses under those listed in ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. the functional operation of the device or any other conditions under those indicated in the operational sections of this specifica- tion is not implied. exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. maximum dc voltage on input or i/o pins are v cc + 0.5 v. during voltage transitioning period, input or i/o pins may overshoot to v cc + 2.0 v for a period of time up to 20 ns. minimum dc voltage on input or i/o pins are -0.5 v. during voltage transitioning period, input or i/o pins may undershoot gnd to -2.0 v for a period of time up to 20 ns. 3. maximum dc voltage on a9 pin is +13.0 v. during voltage transitioning period, a9 pin may overshoot to +14.0 v for a period of time up to 20 ns. minimum dc voltage on a9 pin is -0.5 v. during voltage transitioning period, a9 pin may undershoot gnd to -2.0 v for a period of time up to 20 ns.
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 13 dc characteristics l o b m y sr e t e m a r a pn o i t i d n o cn i mp y tx a ms t i n u i i l t n e r r u c d a o l t u p n iv n i v o t v 0 = c c 1a i o l t n e r r u c e g a k a e l t u p t u ov o / i v o t v 0 = c c 1a i 1 b s v c c s o m c t n e r r u c y b d n a t sv = # e o , # e c c c v 3 . 0 1 . 05a i 2 b s v c c l t t t n e r r u c y b d n a t sv = # e c h i v o t c c 5 0 . 03a m i 1 c c v c c t n e r r u c d a e r e v i t c ai ; z h m 5 = f t u o a m 0 =45 1a m i 2 c c ) 1 ( v c c t n e r r u c e s a r e / m a r g o r p80 2a m v l i e g a t l o v w o l t u p n i5 . 0 -8 . 0v v h i e g a t l o v h g i h t u p n iv 7 . 0 c c v c c 3 . 0 +v v l o e g a t l o v w o l t u p t u o i l o v ; a m 1 . 2 = c c v = c c n i m 5 4 . 0v v h o e g a t l o v h g i h t u p t u o i h o 0 0 1 - = v ; a c c v = c c n i m v c c 2 . 0 -v read operations characteristics ac characteristics l o b m y sr e t e m a r a p 5 5 - 2 1 5 v l 9 3 m p 5 5 - 0 1 0 v l 9 3 m p 5 5 - 0 2 0 v l 9 3 m p 5 5 - 0 4 0 v l 9 3 m p 0 7 - 2 1 5 v l 9 3 m p 0 7 - 0 1 0 v l 9 3 m p 0 7 - 0 2 0 v l 9 3 m p 0 7 - 0 4 0 v l 9 3 m p s t i n u n i mx a mn i mx a m t c r e m i t e l c y c d a e r5 50 7s n t c c a y a l e d t u p t u o o t s s e r d d a5 50 7s n t e c y a l e d t u p t u o o t # e c5 50 7s n t e o y a l e d t u p t u o o t # e o0 35 3s n t f d z h g i h t u p t u o o t # e o r o # e c05 105 2s n t h o r o # e c , # e o m o r f d l o h t u p t u o t s r i f d e r u c c o r e v e h c i h w , s s e r d d a 00 s n t s c v v c c e m i t p u - t e s0 50 5s note: 1. characterized but not 100% tested.
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 14 read operations ac waveforms output test load input test waveforms and measurement level ac characteristics (continued) pin capacitance ( f = 1 mhz, t = 25 c ) p y tx a ms t i n us n o i t i d n o c c n i 46 f pv n i v 0 = c t u o 82 1f pv t u o v 0 = note: these parameters are characterized but not 100% tested. address valid t rc t acc t ce t oe t df t oh output valid high z address ce# oe# we# output v cc t vcs 3.3 v 1.8 k 1.3 k output pin c l = 30 p f 3.0 v 0.0 v 1.5 v ac measurement level input
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 15 write (program/erase) operations characteristics l o b m y sr e t e m a r a p 5 5 - 2 1 5 v l 9 3 m p 5 5 - 0 1 0 v l 9 3 m p 5 5 - 0 2 0 v l 9 3 m p 5 5 - 0 4 0 v l 9 3 m p 0 7 - 2 1 5 v l 9 3 m p 0 7 - 0 1 0 v l 9 3 m p 0 7 - 0 2 0 v l 9 3 m p 0 7 - 0 4 0 v l 9 3 m p s t i n u n i mx a mn i mx a m t c w e m i t e l c y c e t i r w5 50 7s n t s a e m i t p u - t e s s s e r d d a00s n t h a e m i t d l o h s s e r d d a0 30 3s n t s c e m i t p u - t e s # e w d n a # e c00s n t h c e m i t d l o h # e w d n a # e c00s n t h e o e m i t d l o h h g i h # e o0 10 1s n t s d e m i t p u - t e s a t a d0 40 4s n t h d e m i t d l o h a t a d00s n t p w h t d i w e s l u p e t i r w5 35 3s n t h p w h g i h h t d i w e s l u p e t i r w0 20 2s n t p b e m i t g n i m m a r g o r p e t y b0 30 3s t c e e m i t e s a r e k c o l b r o p i h c0 0 10 0 1s m t s c v v c c e m i t p u - t e s0 50 5s ac characteristics (continued) program operations ac waveforms - we# controlled t ch t cs t wp t wph t bp t dh t ds t ah t as 555 555 address 2aa aa 55 a0 input data valid data data in a0 - a ms oe# we# ce# program cycle t wc v cc t vcs
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 16 ac characteristics (continued) chip erase operations ac waveforms t ch t cs t wp t wph t bp t dh t ds t ah t as 555 555 address 2aa aa 55 a0 input data valid data data in a0 - a ms oe# we# ce# program cycle t wc v cc t vcs program operations ac waveforms - ce# controlled aa 55 55 10 80 aa 555 2aa 555 555 2aa t ec t wph t wp t as t ah t dh t ds ao - a ms we# ce# oe# data in t wc 555 v cc t vcs
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 17 sector or block erase operations ac waveforms aa 55 55 30 or 50 80 aa 555 2aa 555 555 2aa sector or block address t ec t wph t wp t as t ah t dh t ds ao - a ms we# ce# oe# data in t wc v cc t vcs toggle bit ac waveforms ac characteristics (continued) t oeh we# ce# oe# i/o6 toggle stop toggling valid data t oe toggle data t df t oh note: t oggling ce#, oe#, or both oe# and ce# will operate toggle bit.
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 18 data# polling ac waveforms ac characteristics (continued) note: t oggling ce#, oe#, or both oe# and ce# will operate data# polling. program/erase performance t ch t ce t oeh t oe t df t oh valid data i/o7# we# ce# oe# i/o7 r e t e m a r a pt i n up y tx a ms k r a m e r e m i t e s a r e r o t c e ss m5 50 0 1n o i t e l p m o c e s a r e o t d n a m m o c e s a r e g n i t i r w m o r f e m i t e s a r e k c o l bs m5 50 0 1n o i t e l p m o c e s a r e o t d n a m m o c e s a r e g n i t i r w m o r f e m i t e s a r e p i h cs m5 50 0 1n o i t e l p m o c e s a r e o t d n a m m o c e s a r e g n i t i r w m o r f e m i t g n i m m a r g o r p e t y b s 6 10 3 d n a m m o c m a r g o r p e l c y c - r u o f f o e m i t e h t s e d u l c x e n o i t u c e x e r e t e m a r a pn i mp y tt i n ud o h t e m t s e t e c n a r u d n e0 0 0 , 0 0 1 ) 2 ( s e l c y c7 1 1 a d r a d n a t s c e d e j n o i t n e t e r a t a d0 2s r a e y3 0 1 a d r a d n a t s c e d e j l e d o m y d o b n a m u h - d s e0 0 0 , 2s t l o v4 1 1 a d r a d n a t s c e d e j l e d o m e n i h c a m - d s e0 0 2s t l o v5 1 1 a d r a d n a t s c e d e j p u - h c t a l i + 0 0 1 1 c c a m8 7 d r a d n a t s c e d e j note: these parameters are characterized but not 100% tested. note: 1. these parameters are characterized but not 100% tested. 2. preliminary specification only and will be formalized after cycling qualification test. reliability characteristics (1)
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 19 package type information 32v 32-pin thin small outline package (vsop - 8 mm x 14 mm)( measure in millimeters) 32j 32-pin plastic leaded chip carrier dimensions in inches (millimeters) pin 1 i.d. 15.11 14.86 14.05 13.89 1.27 typ. 0.81 0.66 11.51 11.35 12.57 12.32 0.74x30 13.46 12.45 0.53 0.33 2.41 1.93 3.56 3.18 seating plane 0.50 bsc 1.05 0.95 0.27 0.17 0.15 0.05 pin 1 i.d. 12.50 12.30 14.20 13.80 8.10 7.90 1.20 max 0.25 0 5 0.20 0.10 0.70 0.50
programmable microelectronics corp. issue date: december, 2003 rev: 1.2 pmc pm39lv512 / PM39LV010 / pm39lv020 / pm39lv040 20 revision hist or y e t a d. o n n o i s i v e rs e g n a h c f o n o i t p i r c s e d. o n e g a p 3 0 0 2 , y a m0 . 1n o i t a m r o f n i y r a n i m i l e r pl l a 3 0 0 2 , r e b m e t p e s1 . 1e s a e l e r l a m r o f d n a n o i t p i r c s e d m a r g o r p d e t a d p u5 3 0 0 2 , r e b m e c e d2 . 1 n o i t p o e g a k c a p e e r f - d a e l d e d d a2 1 , 3 , 1 m o r f s e l c y c e s a r e / m a r g o r p d e e t n a r u g d e d a r g p u ) y r a n i m i l e r p ( 0 0 0 , 0 0 1 o t 0 0 0 , 0 5 8 1 , 1 d e e p s l l a r o f f p 0 3 s a d a o l t s e t t u p t u o d e s i v e r4 1 n o i t a m r o f n i n o i s n e m i d e g a k c a p d e s i v e r9 1

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