a0 to a15 we oe cs1 i/o1 to 8 v dd v ss address input write enable output enable chip select 1 cs2 chip select 2 data i/o power supply (2.7v to 3.6v) power supply (0v) n. c. no connection 1 a11 32 oe 2 a9 31 a10 3 a8 30 cs1 4 a13 29 i/08 5 we 28 i/07 6 cs2 27 i/06 7 a15 26 i/05 8 v dd 25 i/04 9 n.c. 24 v ss 10 n.c. 23 i/03 11 a14 22 i/02 12 a12 21 i/01 13 a7 20 a0 14 a6 19 a1 15 a5 18 a2 16 a4 17 a3 16 a4 17 a3 15 a5 18 a2 14 a6 19 a1 13 a7 20 a0 12 a12 21 i/01 11 a14 22 i/02 10 n.c. 23 i/03 9 n.c. 24 v ss 8 v dd 25 i/04 7 a15 26 i/05 6 cs2 27 i/06 5 we 28 i/07 4 a13 29 i/08 3 a8 30 cs1 2 a9 31 a10 1 a11 32 oe (sop6) (tsop/slim-tsop) 32 v dd srm20v512slmt n.c. 1 31 a15 n.c. 2 30 cs2 a14 3 29 we a12 4 28 a13 a7 5 27 a8 a6 6 26 a9 a5 7 25 a11 a4 8 24 oe a3 9 23 a10 a2 10 22 cs1 a1 11 21 i/08 a0 12 20 i/07 i/01 13 19 i/06 i/02 14 18 i/05 i/03 15 17 i/04 v ss 16 (tsop-r1/slim-tsop-r1) srm20v512sltt/kt srm20v512slrt/yt a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 cs1 oe we i/o buffer column gate memory cell array 512 128 8 128 8 8 9 512 7 128 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 cs2 address buffer x decoder y decoder cs1, cs2 control logic oe, we control logic n description the srm20v512slmt 7 is a 65,536 words 8-bit asynchronous, static, random access memory on a monolithic cmos chip. its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. and C40 to 85 c operating tempereture range wakes it idial for portable equipment. the asynchronous and static nature of the memory requires no external clock or refreshing circuit. both the input and output ports are ttl compatible and the 3-state output allows easy expansion of memory capacity. n features l wide tempereture range ................. C40 to 85 c l fast access time ............................. srm20v512slmt 7 70ns l low supply current .......................... standby : 0.3 m a (typ.) operation : 8ma/1mhz (typ.) l completely static ............................. no clock required l single power supply ........................ 2.7v to 3.6v l ttl compatible inputs and outputs l 3-state output with wired-or capability l non-volatile storage with back-up batteries l package ...... srm20v512slmt 7 sop6-32pin (plastic) srm20v512sltt 7 tsop ( i )-32pin (plastic) srm20v512slrt 7 tsop ( i )-32pin-r1 (plastic) srm20v512slkt 7 slim-tsop ( i )-32pin (plastic) srm20v512slyt 7 slim-tsop ( i )-32pin-r1 (plastic) 512k-bit static ram pf861-02 n pin description n block diagram l wide temperature range l low supply current l access time 70ns l 65,536 words 8 bit asynchronous n pin configuration low voltage operation products srm20v512slmt 7
srm20v512slmt 7 2 parameter supply voltage input voltage input/output voltage power dissipation operating temperature storage temperature soldering temperature and time v dd v i v i/o p d t opr t stg t sol ?.5 to 4.6 ?.5 [ to v dd +0.3 ?.5 [ to v dd +0.3 0.5 ?0 to 85 ?5 to 150 260 c, 10s (at lead) v v v w c c symbol ratings unit (v ss = 0v) [ ?.0v when pulse width is less or equal 50ns (ta = ?0 to 85 c) parameter input voltage supply voltage symbol v dd v ss v ih v il [ if pulse width is less than 50ns, it is ?.0v min. 2.7 0 2.2 ?.3 [ 3.0 0 3.6 0 v dd +0.3 0.4 v v v v typ. max. unit [ typical values are measured at ta = 25 c and v dd = 3.0v (f = 1mhz, ta = 25 c) parameter symbol address capacitance c add c i c i/o input capacitance i/o capacitance min. typ. max. unit conditions pf v add = 0v v i = 0v v i/o = 0v 8 8 10 pf pf parameter symbol conditions unit input leakage high level output voltage low level output voltage operating supply current average operating current note ?this parameter is made by the inspection data of sample, not of all products. i li v oh v ol i dds i ddo a ma v (v dd = 2.7 to 3.6v, v ss = 0v, ta = ?0 to 85 c) i dda v i = 0 to v dd cs1 = v ih or cs2 = v il v a ma standby supply current i dds1 i dda1 cs1 = cs2 3 v dd ?.2v or cs2 0.2v v i = v il , v ih i i/o = 0ma, t cyc = min. v i = v il , v ih i i/o = 0ma, t cyc = 1us v i = v il , v ih i i/o = 0ma ma ma ?.0 min. typ. [ max. 0.3 20 8 8 1.0 1.0 30 35 15 15 output teakage i lo a cs1 = v ih or cs2 = v il or we = v il or oe = v ih , v io = 0 to v dd ?.0 1.0 2.4 0.4 v dd ?.2 0.2 v dd 3 3v, i oh = ?.0ma i oh = ?00 a v dd 3 3v, i ol = ?.0ma i ol = 100 a srm20v512slmt 7 n absolute maximum ratings n dc recommended operating conditions l terminal capa citance n electrical characteristics l dc electrical characteristics
srm20v512slmt 7 3 [ 1 test conditions 1. input pulse level : 0.4v to 2.4v 2. t r = t f = 5ns 3. input and output timing reference levels : 1.5v 4. output load c l = 100pf l ac electrical characteristics m read cycle m write cycle unit parameter symbol conditions (v ss = 0v, v dd = 2.7v to 3.6v, ta = ?0 to 85 c) read cycle time address access time chip select 1 access time chip select 2 access time output enable access time chip select 1 output set time chip select 1 output floating chip select 2 output set time chip select 2 output floating output enable output set time output enable output floating output hold time write cycle time chip select time 1 chip select time 2 address enable time address setup time write pulse width address hold time input data setup time input data hold time we output floating we output setup time t wc t cw1 t cw2 t aw t as t wp t wr t dw t dh t whz t ow 1 1 1 1 1 1 1 1 1 2 2 70 60 60 60 0 55 0 30 0 5 30 ns ns ns ns ns ns ns ns ns ns ns t rc t acc t acs1 t acs2 t oe t clz1 t chz1 t clz2 t chz2 t olz t ohz t oh 1 1 1 1 1 2 2 2 2 2 2 1 70 5 5 0 10 70 70 70 40 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns unit parameter symbol conditions (v ss = 0v, v dd = 2.7v to 3.6v, ta = ?0 to 85 c) srm20v512slmt 7 min. max. srm20v512slmt 7 min. max. [ 2 test conditions 1. input pulse level : 0.4v to 2.4v 2. t r = t f = 5ns 3. input timing reference levels : 1.5v 4. output timing reference levels: 200mv (the level displaced from stable output voltage level) 5. output load c l = 5pf +3v 1.0k 920 100pf i/o +3v 1.0k 920 5pf i/o
srm20v512slmt 7 4 note) [ 1 during read cycle time, we is to be "h" level. [ 2 during write cycle time that is controlled by cs1 or cs2, input/output buffer is in high impedance state whether oe level i s "h"or "l". [ 3 during write cycle time that is controlled by we, input/output buffer is high impedance state if oe is "h" level. [ 4 when i/o terminals are output mode, be careful that do not give the epposite signals to the i/o terminals. l timing chart m read cycle [ 1 m write cycle 1 (cs1 control) [ 2 m write cycle 3 (we control) [ 3 ? [ 4 m write cycle 2 (cs2 control) [ 2 address cs1 cs2 we dout din t wc t aw t wp t dw t wr t as t whz t ow t dh address cs1 cs2 we dout din t wc t aw t wp t cw2 t clz2 t whz t dw t wr t as t dh address cs1 cs2 oe dout address cs1 cs2 we dout din t wc t aw t wp t cw1 t whz t clz1 t dw t wr t as t dh t oh t chz1 t acs2 t clz2 t chz2 t oe t ohz t olz t rc t acc t acs1 t clz1 l data retention characteristic with low voltage power supply parameter symbol conditions min. typ. [ max. unit data retention supply voltage data retention current chip select data hold time v ddr i ddr t cdr 2.0 3.6 25 v ns (v ss = 0v, ta = ?0 to 85 c) 0 5 operation recovery time t r ms v dd = 2.7v cs1 = cs2 3 v dd ?.2v or cs2 0.2v [ : ta = 25 c 0.25 a data retention timing 1 (cs1 control) v dd cs1 v ddr 3 2.0v cs1 3 v dd \ 0.2v data hold mode t cdr v ih 2.7v 2.7v 2.7v 2.7v v ih t r date retention timing 2 (cs2 control) v dd cs2 v ddr 3 2.0v cs2 0.2v data hold mode t cdr v il v il t r
srm20v512slmt 7 5 n functions l truth table x : "h" or "l" h x l l cs1 x l h h cs2 x x x h x oe x l h we data i/o i dd mode i dds , i dds1 hi z hi z input data hi z unselected unselected write output disable i dds , i dds1 i dda , i dda1 l h l h ouput data read i dda , i dda1 i dda , i dda1 l reading data data is able to be read when the address is setted while holding cs1 = "l", cs2 = "h", oe = "l" and we = "h". since data i/o terminals are in high impedance state when oe = "h", the data bus line can be used for any other objective, then access time apparently is able to be cut down. l writing data there are the following four ways of writing data into the memory. (1) hold cs2 = "h", we = "l", set addresses and give "l" pulse to cs1. (2) hold cs1 = "l", we = "l", set addresses and give "h" pulse to cs2. (3) hold cs1 = "l", cs2 = "h", set addresses and give "l" pulse to we. (4) after setting addresses, give "l" pulse to cs1, we and give "h" pulse to cs2. anyway, data on the data i/o terminals are latched up into the chip at the end of the period that cs1, we are "l" level, and cs2 is "h" level. as data i/o terminals are in high impedance state when any of cs1, oe = "h", or cs2 = "l", the contention on the data bus can be avoided. l standby mode when cs1 is "h" or cs2 is "l" level, the chip is in the standby mode which has retaning data operation. in this case data i/o terminals are hi-z, and all inputs of addresses, we and data can be any "h" or "l". when cs1 and cs2 level are in the range over v dd -0.2v, or cs2 level is in the range under 0.2v, in the chip there is almost no current flow except through the high resistance parts of the memory. l data retention at low voltage power supply during standby mode in which the data is retentive, the supply voltage ( v dd ) can be in low voltage until v dd = v ddr . at this mode data reading and writing are impossible.
srm20v512slmt 7 6 unit : mm (inch) plastic sop6-32pin plastic tsop( i )-32pin unit : mm(inch) unit : mm(inch) plastic tsop( i )-32pin-r1 plastic slim-tsop( i )-32pin unit : mm unit : mm plastic slim-tsop( i )-32pin-r1 17 32 16 1 1.27 ( 0.05 ) 20.45 0.1 ( 0.805 ) 11.295 0.1 ( 0.445 ) +0.003 ?.004 0.4 0.1 ( 0.016 ) +0.003 ?.004 3.1 max ( 0.122 max ) +0.004 ?.003 0.2 ( 0.008 ) 1.42 ( 0.056 ) 0 8 0.15 0.05 ( 0.006 ) +0.001 ?.002 20.85 max ( 0.82 max ) 14.135 0.3 ( 0.556 ) +0.012 ?.011 2.7 0.1 ( 0.106 ) +0.004 ?.003 0.8 0.2 ( 0.031 ) +0.008 ?.007 32 1 17 16 index 18.4 0.2 ( 0.724 ) +0.008 ?.007 0 10 8 0.2 ( 0.315 0.007 ) 20 0.2 ( 0.787 ) +0.008 ?.007 0.5 0.1 ( 0.02 ) +0.003 ?.004 0.15 ( 0.006 ) +0.002 ?.003 0.5 ( 0.02 ) 1.27 max ( 0.05 max ) 0.2 0.1 ( 0.008 ) +0.003 ?.004 1 ( 0.039 ) +0.07 ?.075 0.8 0.2 ( 0.031 ) +0.008 ?.007 17 16 32 1 18.4 0.2 ( 0.724 ) +0.008 ?.007 0 10 8 0.2 ( 0.315 0.007 ) 20 0.2 ( 0.787 ) +0.008 ?.007 0.5 0.1 ( 0.02 ) +0.003 ?.004 0.15 ( 0.006 ) +0.002 ?.003 0.5 ( 0.02 ) 1.27 max ( 0.05 max ) 0.2 0.1 ( 0.008 ) +0.003 ?.004 1 ( 0.039 ) +0.07 ?.075 0.8 0.2 ( 0.031 ) +0.008 ?.007 index 13.4 0.2 0.50 0.20 +0.07 ?.02 0.15 +0.03 1.2max 0.5 0.2 0.5 0.2 0.5 0.2 8.0 0.1 11.8 0.1 ? 0.15 +0.10 ?.05 0 7 13.4 0.2 0.50 0.20 +0.07 ?.02 0.15 +0.03 1.2max 0.5 0.2 0.5 0.2 0.5 0.2 8.0 0.1 11.8 0.1 ? 0.15 +0.10 ?.05 0 ? 1 17 16 32 1 16 17 32 n package dimensions
srm20v512slmt 7 7 n characteristics curves 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 C40 C20 0 20406080 write v dd = 3.0v read, write read ta ( c) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 20 18 16 14 12 10 8 6 4 2 0 frequency (mhz) 1/t rc , 1/t wc 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 2.4 2.7 3 3.3 3.6 3.9 v dd (v) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 0.5 1 1.5 2 2.5 3 3.5 v oh (v) normalized i dda ? ta normalized i dda ? v dd normalized i dda ? frequency normalized i dds1 ? v dd normalized i oh ? v oh 100 10 1 0.1 0.01 80 60 40 20 0 e20 e40 ta ( c) 100 1 0.1 3.9 3.6 3.3 3 2.7 2.4 v dd (v) normalized i dds1 ? ta v dd =3.0v ta = 25 c v dd = 3.0v write read ta = 25 c ta = 25 c read, write write read ta = 25 c v dd = 3.0v
srm20v512slmt 7 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0 0.2 0.4 0.6 0.8 1 v ol (v) normalized t acs1 ta t acc t acs2 normalized t acs1 v dd t acc t acs2 normalized t acs1 c l t acc t acs2 normalized i ddr ta normalized i ol v ol 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 ta ( c) 1.3 1.25 1.2 1.15 1.1 1.05 1 0.95 0.9 0.85 0.8 v dd (v) 3.9 3.6 3.3 3 2.7 2.4 80 60 40 20 0 e20 e40 v dd =3.0v ta=25 c ta=25 c v dd =3.0v 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 100 200 300 400 c l (pf) 100 10 1 0.1 0.01 e40 e20 020406080 ta ( c) ta=25 c v dd =3.0v v dd 2.7v
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