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74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) product specification ic23 data handbook 1998 jun 30 integrated circuits
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 2 1998 jun 30 853-2090-19651 features ? symmetrical (a and b bus functions are identical) ? selectable generate parity or ofeed-througho parity for a-to-b and b-to-a directions ? independent transparent latches for a-to-b and b-to-a directions ? selectable odd/even parity ? continuously checks parity of both a bus and b bus latches as erra and errb ? open-collector err output ? ability to simultaneously generate and check parity ? can simultaneously read/latch a and b bus data ? output capability: +64 ma/32ma ? latch-up protection exceeds 500ma per jedec std 17 ? esd protection exceeds 2000 v per mil std 883 method 3015 and 200 v per machine model ? power up 3-state ? power-up reset ? no bus current loading when output is tied to 5 v bus ? live insertion/extraction permitted ? bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs description the 74alvt16899 is a high-performance bicmos product designed for v cc operation at 2.5v or 3.3v with i/o compatibility up to 5v. the 74alvt16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the a bus and b bus. either bus can generate or check parity. the parity bit can be fed-through with no change or the generated parity can be substituted with the sel input. the 74alvt16899 features independent latch enables for the a and b bus latches, a select pin for odd/even parity, and separate error signal output pins for checking parity. functional description: the 74alvt16899 has three principal modes of operation which are outlined below. all modes apply to both the a-to-b and b-to-a directions. transparent latch, generate parity, check a and b bus parity: bus a (b) communicates to bus b (a), parity is generated and passed on to the b (a) bus as bpar (apar). if lea and leb are high and the mode select (sel ) is low, the parity generated from a0-a7 and b0-b7 can be checked and monitored by erra and errb . (fault detection on both input and output buses.) transparent latch, feed-through parity, check a and b bus parity: bus a (b) communicates to bus b (a) in a feed-through mode if sel is high. parity is still generated and checked as erra and errb and can be used as an interrupt to signal a data/parity bit error to the cpu. latched input, generate/feed-through parity, check a (and b) bus parity: independent latch enables (lea and leb) allow other permutations of: ? transparent latch / 1 bus latched / both buses latched ? feed-through parity / generate parity ? check in bus parity / check out bus parity / check in and out bus parity quick reference data symbol parameter conditions typical unit symbol parameter conditions t amb = 25 c; gnd = 0v 2.5 v 3.3 v unit t plh t phl propagation delay an to bn or bn to an c l = 50pf 2.0 2.2 1.5 1.7 ns t plh t phl propagation delay an to erra c l = 50pf 9.8 7.0 7.8 5.1 ns c in input capacitance v i = 0v or v cc 3 3 pf c i/o output capacitance outputs disabled; v o = 0v or v cc 9 9 pf i ccz quiescent supply current outputs disabled 40 70 m a ordering information packages temperature range outside north america north america dwg number 56-pin plastic ssop type iii 40 c to +85 c 74alvt16899 av16899 dl sot371-1 56-pin plastic tssop type ii 40 c to +85 c 74alvt16899 dgg av16899 dgg sot364-1
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 3 pin configuration sv01731 gnd 1b6 sel gnd oea odd/even 1a6 1a3 1b3 2a7 2b7 2a4 2b4 2b1 oeb 2a1 leb 2a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1a0 1a1 1a2 1a4 v cc 1a5 1a7 1apar 1erra gnd 2erra 2apar 2a6 2a5 v cc 2a3 2a2 gnd lea 1b0 1b2 1b1 1b4 v cc 1b5 1b7 1bpar 1errb gnd 2errb 2bpar 2b6 2b5 v cc 2b3 2b2 gnd 2b0 pin description symbol pin number name and function 1a0 - 1a7 2a0 - 2a7 3, 5, 6, 7, 8, 10, 11, 12 27, 25, 24, 23, 22, 20, 19, 18 latched a bus 3-state inputs/outputs 1b0 - 1b7 2b0 - 2b7 54, 52, 51, 50, 49, 47, 46, 45 30, 32, 33, 34, 35, 37, 38, 39 latched b bus 3-state inputs/outputs 1apar 2apar 13, 17 a bus parity 3-state input/output 1bpar 2bpar 44, 40 b bus parity 3-state input/output odd/even 1 parity select input (low for even parity) oea , oeb 2, 29 output enable inputs (gate a to b, b to a) sel 56 mode select input (low for generate) lea, leb 55, 28 latch enable inputs (transparent high) 1erra , 1errb 2erra , 2errb 14, 43, 16, 41 error signal outputs (active-low) gnd 4, 15, 26, 31, 42, 53 ground (0v) v cc 9, 21, 36, 48 positive supply voltage
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 4 logic symbol 3 5 6 7 8 10 11 12 1a0 1a1 1a2 1a3 1a4 1a5 1a6 1a7 1b0 1b1 1b2 1b3 1b4 1b5 1b6 1b7 54 52 51 50 49 47 46 45 14 43 55 56 28 1 lea sel leb odd/even 1erra 1errb 13 1apar 1bpar 44 2 29 oeb oea sh00083 27 25 24 23 22 20 19 18 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 2b0 2b1 2b2 2b3 2b4 2b5 2b6 2b7 30 32 33 34 35 37 38 39 16 41 55 56 28 1 lea sel leb odd/even 2erra 2errb 17 2apar 2bpar 40 2 29 oeb oea parity and error function table inputs outputs sel odd/even xpar (a or b) s of high inputs xpar (b or a) errt errr * parity modes h h h even odd h h h l h l odd h h l even odd l l l h l h mode feed-through/check parity h l h even odd h h l h l h even h l l even odd l l h l h l mode l h h even odd h l h l h h odd l h l even odd h l l h h h mode generate parity l l h even odd l h l h h h even l l l even odd l h h l h h mode h = high voltage level l = low voltage level t = transmitif the data path is from a b then errt is erra r = receiveif the data path is from a b then errr is errb * blocked if latch is not transparent
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 5 block diagram 1 0 mux 9bit output buffer oe 9bit output buffer 9bit transparent latch le parity generator parity generator 1 0 mux oe 9bit transparent latch le oeb lea a0 a1 a2 a3 a4 a5 a6 a7 apar oea sel odd/ even leb b7 bpar b6 b5 b4 b3 b2 b1 b0 erra errb sh00084 (1 of 2 parity blocks) function table inputs operating mode oeb oea sel lea leb h h x x x 3-state a bus and b bus (input a & b simultaneously) h l l l h b a, transparent b latch, generate parity from b0 - b7, check b bus parity h l l h h b a, transparent a & b latch, generate parity from b0 - b7, check a & b bus parity h l l x l b a, b bus latched, generate parity from latched b0 - b7 data, check b bus parity h l h x h b a, transparent b latch, parity feed-through, check b bus parity h l h h h b a, transparent a & b latch, parity feed-through, check a & b bus parity l h l h x a b, transparent a latch, generate parity from a0 - a7, check a bus parity l h l h h a b, transparent a & b latch, generate parity from a0 - a7, check a & b bus parity l h l l x a b, a bus latched, generate parity from latched a0 - a7 data, check a bus parity l h h h l a b, transparent a latch, parity feed-through, check a bus parity l h h h h a b, transparent a & b latch, parity feed-through, check a & b bus parity l l x x x output to a bus and b bus (not allowed) h = high voltage level l = low voltage level x = don't care
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 6 absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage -0.5 to +4.6 v i ik dc input diode current v i < 0 -50 ma v i dc input voltage 3 -0.5 to +7.0 v i ok dc output diode current v o < 0 -50 ma v out dc output voltage 3 output in off or high state -0.5 to +7.0 v i out dc out p ut current output in low state 128 ma i out dc out ut current output in high state -64 ma t stg storage temperature range -65 to +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. recommended operating conditions symbol parameter 2.5v range limits 3.3v range limits unit symbol parameter min max min max unit v cc dc supply voltage 2.3 2.7 3.0 3.6 v v i input voltage 0 5.5 0 5.5 v v ih high-level input voltage 1.7 2.0 v v il input voltage 0.7 0.8 v i oh high-level output current 8 32 ma i ol low-level output current 8 32 ma i ol low-level output current; current duty cycle 50%; f 1khz 24 64 ma d t/ d v input transition rise or fall rate; outputs enabled 10 10 ns/v t amb operating free-air temperature range 40 +85 40 +85 c
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 7 dc electrical characteristics (3.3v 0.3v range) limits symbol parameter test conditions temp = -40 c to +85 c unit min typ 1 max v ik input clamp voltage v cc = 3.0v; i ik = 18ma 0.85 1.2 v v oh high-level out p ut voltage v cc = 3.0 to 3.6v; i oh = 100 m a v cc 0.2 v cc v v oh high - level out ut voltage v cc = 3.0v; i oh = 32ma 2.0 2.3 v v cc = 3.0v; i ol = 100 m a 0.07 0.2 v ol lowlevel out p ut voltage v cc = 3.0v; i ol = 16ma 0.25 0.4 v v ol low level out ut voltage v cc = 3.0v; i ol = 32ma 0.3 0.5 v v cc = 3.0v; i ol = 64ma 0.4 0.55 v rst power-up output low voltage 6 v cc = 3.6v; i o = 1ma; v i = v cc or gnd 0.55 v v cc = 3.6v; v i = v cc or gnd control p ins 0.1 1 v cc = 0 or 3.6v; v i = 5.5v control ins 0.1 10 i i input leakage current v cc = 3.6v; v i = 5.5v 4 0.1 20 m a v cc = 3.6v; v i = v cc data pins 4 0.5 1 v cc = 3.6v; v i = 0v 0.1 -5 i off off current v cc = 0v; v i or v o = 0 to 4.5v 0.1 100 m a bus hold current v cc = 3v; v i = 0.8v 75 130 i hold bus hold current data in p uts v cc = 3v; v i = 2.0v 75 140 m a data inputs v i = 0v to 3.6v; v cc = 3.6v 7 500 i ex current into an output in the high state when v o > v cc v o = 5.5v; v cc = 3.0v 10 125 m a i pu/pd power up/down 3-state output current 3 v cc 1.2v; v o = 0.5v to v cc ; v i = gnd or v cc oe/oe = don't care 33 100 m a i ozh 3-state output high current v cc = 3.6v; v o = 3.0v; v i = v il or v ih 0.5 5 m a i ozl 3-state output low current v cc = 3.6v; v o = 0.5v; v i = v il or v ih 0.5 5 m a i cch v cc = 3.6v; outputs high, v i = gnd or v cc, i o = 0 0.05 0.1 i ccl quiescent supply current v cc = 3.6v; outputs low, v i = gnd or v cc, i o = 0 4.6 7.0 ma i ccz v cc = 3.6v; outputs disabled; v i = gnd or v cc, i o = 0 5 0.06 0.1 d i cc additional supply current per input pin 2 v cc = 3v to 3.6v; one input at v cc 0.6v, other inputs at v cc or gnd 0.04 0.4 ma notes: 1. all typical values are at v cc = 3.3v and t amb = 25 c. 2. this is the increase in supply current for each input at the specified voltage level other than v cc or gnd 3. this parameter is valid for any v cc between 0v and 1.2v with a transition time of up to 10msec. from v cc = 1.2v to v cc = 3.3v 0.3v a transition time of 100 m sec is permitted. this parameter is valid for t amb = 25 c only. 4. unused pins at v cc or gnd. 5. i ccz is measured with outputs pulled up to v cc or pulled down to ground. 6. for valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. this is the bus hold overdrive current required to force the input to the opposite logic state.
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 8 ac characteristics (3.3v 0.3v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 3.3v 0.3v unit min typ 1 max t plh t phl propagation delay an to bn or bn to an 1 0.5 0.5 1.5 1.7 2.7 2.8 ns t plh t phl propagation delay an to bpar or bn to apar 4 2.5 2.0 5.0 4.6 8.0 7.3 ns t plh t phl propagation delay an to erra or bn to errb 5 2.5 2.5 7.8 5.1 11.5 8.5 ns t plh t phl propagation delay apar to bpar or bpar to apar 3 1.0 1.0 2.9 3.0 6.9 6.4 ns t plh t phl propagation delay apar to erra or bpar to errb 8 2.5 1.0 5.1 2.5 8.0 3.6 ns t plh t phl propagation delay odd/even to apar or bpar 7 1.5 1.5 3.8 3.4 6.5 5.4 ns t plh t phl propagation delay odd/even to erra or errb 6 2.5 1.5 6.6 4.0 10.0 6.6 ns t plh t phl propagation delay sel to apar or bpar 10 1.0 1.0 2.6 2.4 4.0 3.4 ns t plh t phl propagation delay sel to erra or errb 5 2.5 1.5 7.8 4.8 10.8 7.1 ns t plh t phl propagation delay lea to bn or leb to an 11 1.0 1.0 2.2 2.2 3.8 3.8 ns t plh t phl propagation delay lea to bpar or leb to apar 11 2.5 2.0 5.3 4.9 8.5 7.6 ns t plh t phl propagation delay lea to erra or leb to errb 9 2.5 2.5 7.4 5.6 11.0 9.2 ns t pzh t pzl output enable time oea to an, apar or oeb to bn, bpar 13, 14 1.0 0.5 2.4 1.8 5.8 3.3 ns t phz t plz output disable time oea to an, apar or oeb to bn, bpar 13, 14 2.5 1.0 5.2 2.4 8.0 3.5 ns note: 1. all typical values are at v cc = 3.3v and t amb = 25 c. ac setup requirements (3.3v 0.3v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf, r l = 500 w limits symbol parameter waveform v cc = 3.3v 0.3v unit min typ t s (h) t s (l) setup time, high or low an, apar to lea or bn, bpar to leb 12 1.0 1.0 0.1 0.1 ns t h (h) t h (l) hold time, high or low an, apar to lea or bn, bpar to leb 12 1.0 1.0 0.1 0.1 ns t w (h) pulse width, high lea or leb 12 1.0 ns
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 9 dc electrical characteristics (2.5v 0.2v range) limits symbol parameter test conditions temp = -40 c to +85 c unit min typ 1 max v ik input clamp voltage v cc = 2.3v; i ik = 18ma 0.85 1.2 v v oh high-level out p ut voltage v cc = 2.3 to 3.6v; i oh = 100 m a v cc 0.2 v cc v v oh high - level out ut voltage v cc = 2.3v; i oh = 8ma 1.8 2.5 v v cc = 2.3v; i ol = 100 m a 0.07 0.2 v ol low-level output voltage v cc = 2.3v; i ol = 24ma 0.3 0.5 v v cc = 2.3v; i ol = 8ma 0.4 v rst power-up output low voltage 7 v cc = 2.7v; i o = 1ma; v i = v cc or gnd 0.55 v v cc = 2.7v; v i = v cc or gnd control p ins 0.1 1 v cc = 0 or 2.7v; v i = 5.5v control ins 0.1 10 i i input leakage current v cc = 2.7v; v i = 5.5v 4 0.1 20 m a v cc = 2.7v; v i = v cc data pins 4 0.1 10 v cc = 2.7v; v i = 0 0.1 -5 i off off current v cc = 0v; v i or v o = 0 to 4.5v 0.1 100 m a i hold 6 bus hold current v cc = 2.3v; v i = 0.7v 115 m a i hold 6 data inputs v cc = 2.3v; v i = 1.7v 10 m a i ex current into an output in the high state when v o > v cc v o = 5.5v; v cc = 2.3v 10 125 m a i pu/pd power up/down 3-state output current 3 v cc 1.2v; v o = 0.5v to v cc ; v i = gnd or v cc ; oe/oe = don't care 33 100 m a i ozh 3-state output high current v cc = 2.7v; v o = 2.3v; v i = v il or v ih 0.5 5 m a i ozl 3-state output low current v cc = 2.7v; v o = 0.5v; v i = v il or v ih 0.5 5 m a i cch v cc = 2.7v; outputs high, v i = gnd or v cc, i o = 0 0.04 0.1 i ccl quiescent supply current v cc = 2.7v; outputs low, v i = gnd or v cc, i o = 0 3.5 4.5 ma i ccz v cc = 2.7v; outputs disabled; v i = gnd or v cc, i o = 0 5 0.04 0.1 d i cc additional supply current per input pin 2 v cc = 2.3v to 2.7v; one input at v cc 0.6v, other inputs at v cc or gnd 0.04 0.4 ma notes: 1. all typical values are at v cc = 2.5v and t amb = 25 c. 2. this is the increase in supply current for each input at the specified voltage level other than v cc or gnd 3. this parameter is valid for any v cc between 0v and 1.2v with a transition time of up to 10msec. from v cc = 1.2v to v cc = 2.5v 0.2v a transition time of 100 m sec is permitted. this parameter is valid for t amb = 25 c only. 4. unused pins at v cc or gnd. 5. i ccz is measured with outputs pulled up to v cc or pulled down to ground. 6. not guaranteed. 7. for valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 10 ac characteristics (2.5v 0.2v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 2.5v 0.2v unit min typ 1 max t plh t phl propagation delay an to bn or bn to an 1 1.0 1.0 2.0 2.2 3.5 3.9 ns t plh t phl propagation delay an to bpar or bn to apar 4 3.0 3.0 7.0 6.5 10.5 10.2 ns t plh t phl propagation delay an to erra or bn to errb 5 4.5 3.5 9.8 7.0 14.5 11.5 ns t plh t phl propagation delay apar to bpar or bpar to apar 3 1.0 1.0 3.0 3.5 4.3 5.5 ns t plh t phl propagation delay apar to erra or bpar to errb 8 3.0 1.5 6.7 3.6 10.0 5.4 ns t plh t phl propagation delay odd/even to apar or bpar 7 2.5 2.5 5.2 5.0 7.8 7.8 ns t plh t phl propagation delay odd/even to erra or errb 6 4.0 4.0 8.6 8.1 12.0 10.6 ns t plh t phl propagation delay sel to apar or bpar 10 1.5 1.5 3.7 3.2 5.5 5.3 ns t plh t phl propagation delay sel to erra or errb 5 4.5 3.0 9.4 7.6 14.0 11.5 ns t plh t phl propagation delay lea to bn or leb to an 11 1.0 1.0 3.0 3.0 4.8 4.6 ns t plh t phl propagation delay lea to bpar or leb to apar 11 2.5 2.5 7.5 7.4 12.2 11.2 ns t plh t phl propagation delay lea to erra or leb to errb 9 4.5 3.5 9.7 8.5 15.0 13.4 ns t pzh t pzl output enable time oea to an, apar or oeb to bn, bpar 13, 14 1.5 1.0 4.0 2.6 6.0 4.6 ns t phz t plz output disable time oea to an, apar or oeb to bn, bpar 13, 14 1.5 1.0 4.5 3.7 6.5 5.0 ns note: 1. all typical values are at v cc = 2.5v and t amb = 25 c. ac setup requirements (2.5v 0.2v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf, r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 2.5v 0.2v unit min typ t s (h) t s (l) setup time, high or low an, apar to lea or bn, bpar to leb 12 1.0 1.2 0.4 0.4 ns t h (h) t h (l) hold time, high or low an, apar to lea or bn, bpar to leb 12 1.0 1.2 0.4 0.5 ns t w (h) pulse width, high lea or leb 12 1.0 ns
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 11 ac waveforms v m = 1.5v or v cc /2 whichever is less; v in = gnd to 3.0v sw00160 nax input v m ny x output t phl t plh v m v m v m 3.0v or v cc , whichever is less 0 v oh v ol waveform 1. input (nax) to output (nyx) propagation delays noe input v m v m t pzh t phz nyx output v oh v m v m nyx output v ol t pzl t plz 0v v x v y 3.0v or v cc whichever is less 0v sw00204 waveform 2. 3-state output enable and disable times an, apar (bn, bpar) v m t plh t phl v m v m v m bn, bpar (an, apar) sel 1 input output sa00293 waveform 3. propagation delay, an to bn, bn to an, apar to bpar, bpar to apar an (bn) t plh v m v m v m bpar (apar) lea (leb) 1 input output odd/even 0 sel 0 t phl v m odd parity even parity odd parity note: only even parity mode is shown, odd parity mode would be with odd/even = 1 sa00294 waveform 4. propagation delay, an to bpar or bn to apar
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 12 an (bn) t phl v m v m v m erra (errb ) lea (leb) 1 input output apar (bpar) 0 odd/even 0 t plh v m odd parity even parity odd parity note: only even parity mode is shown, odd parity mode would be with odd/even = 1 sa00295 sel waveform 5. propagation delay, an to erra or bn to errb apar (bpar) v m t plh t phl v m v m v m erra (errb ) input output 1 an (bn) even parity odd/even input note: only even parity mode is shown, odd parity mode would cause inverted output sa00296 waveform 6. propagation delay, odd/even to erra or odd/even to errb
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 13 t phl v m v m v m bpar (apar) input output apar (bpar) 0 sel 0 t plh v m even parity odd/even input note: only even parity mode is shown, odd parity mode would cause inverted output an (bn) sa00297 waveform 7. propagation delay, odd/even to apar or odd/even to bpar apar (bpar) t phl v m v m v m erra (errb ) input output 0 t plh v m even parity odd/even input an (bn) note: only even parity mode is shown with even parity. odd parity mode would cause inverted output and odd parity mode would be with odd/even = 1 sa00298 waveform 8. propagation delay, apar to erra or bpar to errb
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 14 an (bn) input apar (bpar) 0 odd/even even parity odd parity even parity 1 lea (leb) t phl v m erra (errb ) input output t plh v m v m v m note: only odd parity mode is shown. even parity mode would be with odd/even = o sa00299 waveform 9. propagation delay, lea to erra or leb to errb an (bn) t phl v m v m v m bpar (apar) input output apar (bpar) 0 odd/even 1 t plh v m even parity sel input note: only even parity mode is shown with even parity. odd parity mode would cause inverted output and odd parity mode would be with odd/even = 1 sa00300 waveform 10. propagation delay, sel to bpar or sel to apar
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 15 v m apar, an] (bpar, bn) input sel 1 lea (leb) t phl v m bn, bpar (an, apar) input output t plh v m v m sa00301 waveform 11. propagation delay, lea to bpar or leb to apar, lea to bn or leb to an v m apar, bpar, an, bn v m v m v m v m v m lea, leb t s (h) t h (h) t s (l) t h (l) t w (h) v m sa00302 the shaded areas indicate when the input is permitted to change for predictable output performance. waveform 12. data setup and hold times, pulse width high oea , oeb v m t pzh t phz 0v v oh 0.3v v m v m an, apar, bn, bpar sa00303 waveform 13. 3-state output enable time to high level and output disable time from high level oea , oeb t pzl t plz v ol +0.3v an, apar, bn, bpar v m v m v m sa00304 waveform 14. 3-state output enable time to low level and output disable time from low level
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) 1998 jun 30 16 test circuit and waveform t w 90% v m 10% 90% v m 10% 90% v m 10% 90% v m 10% negative pulse positive pulse t w amp (v) 0v 0v t thl ( t f ) input pulse requirements rep. rate t w t r t f 10mhz 500ns 2.5ns 2.5ns input pulse definition v cc family 74alvt16 d.u.t. pulse generator r l c l r t v in v out test circuit for open collector outputs t thl ( t f ) t tlh ( t r ) t tlh ( t r ) amp (v) amplitude 3.0v or v cc , which ever is less r x sv01732 t plz/ t pzl 6 v or v cc 2 t plh/ t phl open t phz /t pzh gnd switch position r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. definitions: v x output r x v x error 100 v cc all other 500 switch load values test switch
2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) philips semiconductors product specification 74alvt16899 1998 jun 30 17 ssop56: plastic shrink small outline package; 56 leads; body width 7.5 mm sot371-1
2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) philips semiconductors product specification 74alvt16899 1998 jun 30 18 tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1mm sot364-1
2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) philips semiconductors product specification 74alvt16899 1998 jun 30 19 notes
philips semiconductors product specification 74alvt16899 2.5v/3.3v 18-bit latched transceiver with 16-bit parity generator/checker (3-state) yyyy mmm dd 20 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. print code date of release: 05-96 document order number: 9397-750-04066
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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