hym5v72a804 a h -series buffered 8mx72 bit cmos dram module based on 8 mx 8 dram, edo, ecc, 3.3v, 4k /8k -refresh this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 3 / jun.9 8 ? 199 8 hyundai semiconductor description the hym5v72a804 a h -series is a 8mx72-bit edo mode cmos dram module consisting of nine 8mx8 tsop and 16-bit bicmos line driver in tssop on a 168 pin glass-epoxy printed circuit board. 0.1 m f and 0.01 m f decoupling capacitors are mounted for each dram. the hym5v72a804 ah g-series is gold plated socket type dual in-line memory module suitable for easy interchange and addition of 64m byte memory. features max. active power dissipation speed 8k 4k 50 3.60w 4.57w 60 2.95w 3.92w fast access time and cycle time speed trac tcac thpc 5 0 5 0ns 18 ns 25ns 6 0 6 0ns 20 ns 30ns 168-pin buffered dimm buffered inputs (except /ras and dq) parallel presence detect with pd/id pin matrix extended data out operation single power supply of 3.3v 10% read-modify-write capability lvttl compatible inputs and outputs /cas-before-/ras, /ras-only, hidden and self refresh capability refresh cycles part no. ref. hym5v72a804a h-series 4k hym5v72a834a h-series 8k a a /cas-before-/ras refresh, hidden refresh mode : 4k cycles / 64ms pin discription /ras0 , / ras 2 row address strobe /cas0, /cas4, column address strobe /we0, /we2 write enable /oe0, /oe2 output enable a0 , b0 , a1-a12 address input (8k product) a0 , b0 , a1-a11 address input (4k product) dq0 - dq71 data input / output pd1 - pd8 presence detect /pde presence detect enable id0, id1 id bit vcc power (+3.3v) vss ground
hym5v72a804a h-series 2 pin name # name # name # name # name 1 vss 43 vss 85 vss 127 vss 2 dq0 44 /oe2 86 dq36 128 nc 3 dq1 45 /ras2 87 dq37 129 nc 4 dq2 46 /cas4 88 dq38 130 nc 5 dq3 47 nc 89 dq39 131 nc 6 vcc 48 /we2 90 vcc 132 /pde 7 dq4 49 vcc 91 dq40 133 vcc 8 dq5 50 nc 92 dq41 134 nc 9 dq6 51 nc 93 dq42 135 nc 10 dq7 52 dq18 94 dq43 136 dq54 11 dq8 53 dq19 95 dq44 137 dq55 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq20 97 dq45 139 dq56 14 dq10 56 dq21 98 dq46 140 dq57 15 dq11 57 dq22 99 dq47 141 dq58 16 dq12 58 dq23 100 dq48 142 dq59 17 dq13 59 vcc 101 dq49 143 vcc 18 vcc 60 dq24 102 vcc 144 dq60 19 dq14 61 nc 103 dq50 145 nc 20 dq15 62 nc 104 dq51 146 nc 21 dq16 63 nc 105 dq52 147 nc 22 dq17 64 nc 106 dq53 148 nc 23 vss 65 dq25 107 vss 149 dq61 24 nc 66 dq26 108 nc 150 dq62 25 nc 67 dq27 109 nc 151 dq63 26 vcc 68 vss 110 vcc 152 vss 27 /we0 69 dq28 111 nc 153 dq64 28 /cas0 70 dq29 112 nc 154 dq65 29 nc 71 dq30 113 nc 155 dq66 30 /ras0 72 dq31 114 nc 156 dq67 31 /oe0 73 vcc 115 nc 157 vcc 32 vss 74 dq32 116 vss 158 dq68 33 a0 75 dq33 117 a1 159 dq69 34 a2 76 dq34 118 a3 160 dq70 35 a4 77 dq35 119 a5 161 dq71 36 a6 78 vss 120 a7 162 vss 37 a8 79 pd1 121 a9 163 pd2 38 a10 80 pd3 122 a11 164 pd4 39 *a12 81 pd5 123 nc 165 pd6 40 vcc 82 pd7 124 vcc 166 pd8 41 nc 83 id0 125 nc 167 id1 42 nc 84 vcc 126 b0 168 vcc note : 1.a12 is used for 8k-refresh product (hym5v72a834 a h-series)
hym5v72a804a h-series 3 presence detect pins pin pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 id0 id1 -50 nc vss nc nc nc vss vss vss vss vss/nc -60 nc vss nc nc nc nc nc vss vss vss/nc note : 1.pds are either open nc or driven to vss via on-board buffer circuit. 2.ids are connected directly to nc or vss without a buffer. 3.id1 will be either open nc for self-refresh or driven to vss for standard. block diagram note : 1.a12 is used for 8k-refresh product (hym5v72a834 a h-series) 2. all resistors are 25ohm 5%
hym5v72a804a h-series 4 absolute maximum ratings symbol parameter rating unit t a ambient temperature 0 to 70 c t stg storage temperature -55 to 150 c v in , v out voltage on any pin relative to v ss -0.5 to 4.6 v v cc voltage on v cc relative to v ss -0.5 to 4.6 v i os short circuit output current 50 ma p d power dissipation 11.4 w t solder soldering temperature time 260 10 c sec note: operation at or above absolute maximum ratings can adversely affect device reliability. recommended dc operating conditions (t a =0 c to 70 c ) symbol parameter min. typ. max. unit v cc power supply voltage 3.0 3.3 3.6 v v ih input high voltage 2.0 - v cc +0.3 v v il input low voltage -0.3 - 0.8 v note: all voltages are referenced to v ss .
hym5v72a804a h-series 5 dc characteristics (t a =0 c to 70 c , v cc =3.3v 10%, v ss =0v, unless otherwise noted.) symbol parameter test conditions speed max. current unit 8k product 4k product i cc1 operating current /ras, /cas cycling trc=trc (min.) 50 60 1 000 82 0 12 70 10 90 ma i cc2 lvttl standby current /ras = /cas 3 v ih other inputs 3 v ss 9.18 9.18 ma i cc3 /ras-only refresh current /ras cycling /cas = v ih trc = trc (min.) 50 60 1 000 82 0 127 0 10 90 ma i cc4 edo mode current /cas cycling /ras = v il thpc = thpc (min.) 50 60 10 90 9 10 11 80 10 00 ma i cc5 cmos standby current /ras = /cas 3 v cc - 0.2v sl-part 4.68 2.88 4.68 2.88 ma i cc6 /cas-before-/ras refresh current trc=trc (min.) 50 60 1 000 82 0 127 0 10 90 ma i cc7 battery back-up current (sl-part) v ih = v cc - 0.2v, v il = 0.2v /cas = cbr cycling or 0.2v /oe & /we = v ih = v cc - 0.2v address = don`t care dq0-dq71 = open 5.13 5.13 ma i cc8 self refresh current (sl-part) /ras & /cas = 0.2v other pins are same as i cc 7 4.23 4.23 ma symbol parameter test condition min. max unit i li input leakage current(any input) v ss v in v cc + 0.3, all other pins not under test=v ss all but /ras /ras -10 - 22.5 10 22 .5 m a i lo output leakage current(any input) v ss v out v cc /ras & /cas at v ih - 5 5 m a v ol output low voltage i ol = 2.0ma - 0.4 v v oh output high voltage i oh = -2.0ma 2.4 - v note 1. i cc1 , i cc3 , i cc4 and i cc6 dependent on output loading and cycle rates(trc and thpc). 2. specified values are obtained with outputs unloaded. 3. i cc is specified as an average current. in i cc 1, i cc 3, i cc 6, address can be changed only once while /ras=vil. in i cc 4, address can be changed maximum once while /cas=v ih within one edo mode cycle time thpc. 4. only /ras(max.) = 1 m s is applied to refresh of battery backup but tras(max.) = 10 m s is applied to normal functional operation. 5. i cc 5(max.) = 2.88ma, i cc 7 and i cc 8 are applied to sl-part only. 6. v oh = 2.0v, v ol = 0.8v at ac functional test.
hym5v72a 804a h-series 6 ac characteristics (t a =0 c to 70 c , vcc=3.3v 10%, vss=0v, unless otherwise noted.) # symbol parameter -50 -60 -70 unit note min . max . min . max . min . max. 1 trc random read or write cycle time 90 - 110 - ns 2 trwc read-modify-write cycle time 12 8 - 153 - ns 14 3 thpc edo mode cycle time 25 - 30 - ns 4 thprw c edo mode read-modify-write cycle time 70 - 77 - ns 14 5 trac access time from /ras - 50 - 60 ns 4,5,10,11 6 tcac access time from /cas - 1 8 - 20 ns 4,5,10,14 7 taa access time from column address - 30 - 3 5 ns 4,5,11,14 8 tcpa access time from /cas precharge - 3 5 - 4 0 ns 4,14 9 tclz /cas to output low impedance 8 - 8 - ns 3,14 1 0 tcez out buffer turn-off delay from /cas 8 1 8 8 18 ns 14 1 1 tt transition time (rise and fall) 2 50 2 50 ns 4 1 2 trp /ras precharge time 30 - 40 - ns 1 3 tras /ras pulse width 5 0 1 0k 60 10k ns 1 4 trasp /ras pulse width (edo mode) 50 100k 60 100k ns 1 5 trsh /ras hold time 1 8 - 20 - ns 14 1 6 tcsh /cas hold time 38 - 43 - ns 14 1 7 tcas /cas pulse width 8 10k 10 10k ns 1 8 trcd /ras to /cas delay 1 5 3 2 18 4 0 ns 10,14 1 9 trad /ras to column address delay time 1 1 2 0 1 3 25 ns 11,14 2 0 tcrp /cas to /ras precharge time 10 - 10 - ns 14 2 1 tcp /cas precharge time 8 - 10 - ns 2 2 tasr row address set-up time 5 - 5 - ns 14 2 3 trah row address hold time 6 - 8 - ns 14 2 4 tasc column address set-up time 0 - 0 - ns 2 5 tcah column address hold time 8 - 10 - ns 2 6 tar column address hold time from /ras 43 - 48 - ns 14 2 7 tral column address to /ras lead time 30 - 35 - ns 14 2 8 trcs read command set-up time 0 - 0 - ns 2 9 trch read command hold time referenced to /cas 0 - 0 - ns 7 3 0 trrh read command hold time referenced to /ras -2 - -2 - ns 14 3 1 twch write command hold time 10 - 10 - ns 3 2 twcr write command hold time from /ras 38 - 43 - ns 14 3 3 twp write command pulse width 8 - 10 - ns 3 4 trwl write command to /ras lead time 20 - 20 - ns 14 3 5 tcwl write command to /cas lead time 8 - 10 - ns
hym5v72a804a h-series 7 a c characteristics # symbol parameter -50 -60 -70 unit note min . max . min . max . min . max. 3 6 tds data-in set-up time - 2 - -2 - ns 8,14 3 7 tdh data-in hold time 15 - 15 - ns 8,14 3 8 tdhr data-in hold time referenced to /ras 40 - 45 - ns 3 9 tref refresh period (8192 cycles) - 64 - 64 ms 12,13 refresh period (4096 cycles) - 64 - 64 ms 12 refresh period (sl-part) - 128 - 128 ms 12,13 4 0 twcs write command set-up time 0 - 0 - ns 9 4 1 tcwd /cas to /we delay time 3 3 - 3 8 - ns 9 4 2 trwd /ras to /we delay time 68 - 82 - ns 9,14 4 3 tawd column address to /we delay time 45 - 5 3 - ns 9 4 4 tcsr /cas set-up time (cbr cycle) 10 - 10 - ns 14 4 5 tchr /cas hold time (cbr cycle) 8 - 8 - ns 14 4 6 trpc /ras to /cas precharge time 3 - 3 - ns 14 4 7 tcpt /cas precharge time (cbr counter test) 25 - 30 - ns 4 8 troh /ras hold time reference to /oe 10 - 10 - ns 14 4 9 toea /oe access time - 18 - 20 ns 14 5 0 toed /oe to data delay 18 - 20 - ns 14 5 1 toez output buffer turn off delay time from /oe 8 1 8 8 18 ns 6,14 5 2 toeh /oe command hold time 13 - 15 - ns 5 3 tcpwd /we delay time from /cas precharge 4 7 - 5 8 - ns 9 5 4 trhcp /ras hold time from /cas precharge 3 5 - 40 - ns 14 5 5 twrp /we to /ras precharge time(cbr cycle) 12 - 12 - ns 14 5 6 twrh /we to /ras hold time (cbr cycle) 8 - 8 - ns 14 5 7 twts write command set-up time (test mode in) 10 - 10 - ns 5 8 twth write command hold time (test mode in) 10 - 10 - ns 5 9 trass /ras pulse width (self refresh) 100k - 100k - us 6 0 trps /ras precharge time (self refresh) 100 - 1 1 0 - ns 6 1 tchs /cas hold time (self refresh) -50 - -50 - ns 6 2 tdoh output data hold time 10 - 10 - ns 14 6 3 trez output buffer turn- off delay from /ras 0 10 0 15 ns 6 6 4 twez output buffer turn- off delay from /we 0 15 0 20 ns 6,14 6 5 twed /we to data delay time 20 - 20 - ns 6 6 toep /oe precharge time 5 - 5 - ns 6 7 twpe /we pulse width (edo cycle) 5 - 5 - ns 6 8 toch /oe to /cas hold time 5 - 5 - ns 6 9 tcho /cas hold time to /oe 5 - 5 - ns 7 0 tpd /pde to valid presence detect data - 10 - 10 ns 7 1 tpdof f /pde inactive to presence detect inactive 2 7 2 7 ns
hym5v72a804 a h-series 8 note 1. an initial pause of 200 m s is required after power-up followed by 8 /ras cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 /cas-before-/ras initialization cycles instead of 8 /ras-only refresh cycles are required. the device should be carefully initialized to be prevented from being entered into multi bit test mode during initialization. 2. if /ras=vss during power-up, the hym5v72a804 a / hym5v72a834 a could begin an active cycle. this condition results in higher current than necessary current which is demanded from the power supply during power-up. 3. it is recommended that /ras and /cas track with vcc during power-up or be held at a valid v ih in order to minimize the power-up current. 4. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are measured between v ih (min.) and v il (max.), and are assumed to be 5ns for all inputs. 5. measured at v oh =2.0v and v ol =0.8v with a load equivalent to 1 ttl loads and 100pf. 6. twez, trez, tcez and toez define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. either trch or trrh must be satisfied for a read cycle. 8. these parameters are referenced to /cas leading edge in early write cycles and to /we leading edge in read-modify-write cycles and late write cycle. 9. twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs 3 twcs(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. if trwd 3 trwd(min.), tcwd 3 tcwd(min.), tawd 3 tawd(min.), and tcpwd 3 tcpwd(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 10. operation within the trcd(max.) limit ensures that trac(max.) can be met. trcd(max.) is specified as a reference point only. if trcd is greater than the specified trcd(max.) limit, then access time is controlled by tcac. 11. operation within the trad(max.) limit ensures that trac(max.) can be met. trad(max.) is specified as a reference point only. if trad is greater than the specified trad(max.) limit, then access time is controlled by taa. 12. tref(max.)=256ms is applied to sl-parts. 13. a burst of 8192 /cas-before-/ras refresh cycles must be executed within 64ms (256ms for sl-parts) after exiting self refresh. (cbr refresh & hidden refresh : 4k cycle/64ms) 14. the timing skew from the dram to the dimm resulted from the addition of buffers. capacitance (t a =0 c to 70 c , vcc=3.3v 10%, vss=0v, f = 1mhz, unless otherwise noted.) symbol parameter typ. max. unit c in1 input capacitance (a0 - a12) - 1 8 pf c in2 input capacitance (/we0, /we2, /oe0, /oe2) - 1 8 pf c in3 input capacitance (/ras0, /ras2) - 45 pf c in4 input capacitance (/cas0, /cas4) - 1 8 pf c dq data input /output capacitance (dq0 - dq71) - 14 pf
hym5v72a804a h-series 9 package information
hym5v72a804 a h-series 10 ordering information part number ref. power package hym5v72a804 a thg 4k normal tsop hym5v72a804 a slthg 4k sl-part tsop hym5v72a834 a thg 8k normal tsop hym5v72a834 a slthg 8k sl-part tsop
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