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1. general description this 11-bit bus switch is designed for 1.7 v to 1.9 v v dd operation and sstl_18 select input levels. each host port pin (hpn) is multiplexed to one of four dimm port pins (xdpn). the selection of the dimm port to be connected to the host port is controlled by a decoder driven by three hardware select pins s0, s1 and en. driving pin en high disconnects all dimm ports from their respective host ports. when en is driven low, pins s0 and s1 select one of four dimm ports to be connected to their respective host port. when disconnected, any dimm port is terminated to the externally supplied voltage v bias by means of an on-chip pull-down resistor of typically 400 w . the on-state connects the host port to the dimm port through a 12 w nominal series resistance. the design is intended to have only one dimm port active at any time. the cbtu4411 can also be con?gured to support a differential strobe signal on channel 10 (true) and channel 9 (complementary strobe). when its lvcmos con?guration input strobe enable (stren) is high, channel 10 is pulled up to 3 4 of v dd internally by a resistive divider when the dimm port is idle. when the cbtu4411 is disabled ( en = high in strobe mode), the pull-down on channel 10 is disabled for current savings, pulling channel 10 to v dd . when strobe enable (stren) is low, channel 10 behaves the same as all other channels. the select inputs (s0, s1) are pseudo-differential type sstl_18. a reference voltage should be provided to input pin vref at nominally 0.5v dd . this topology provides accurate control of switching times by reducing dependency on select signal slew rates. s0 and s1 are provided with selectable input termination to 0.5v dd (active when lvcmos input term is high). when the cbtu4411 is disabled ( en = high), both s0 and s1 inputs are pulled low. the part incorporates a very low crosstalk design. it has a very low skew between outputs (< 30 ps) and low skew (< 30 ps) for rising and falling edges. the part has optimal performance in ddr2 data bus applications. each switch has been optimized for connection to 1- or 2-rank dimms. the low internal rc time constant of the switch allows data transfer to be made with minimal propagation delay. the cbtu4411 is characterized for operation from 0 c to +85 c. cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance rev. 03 12 october 2009 product data sheet
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 2 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 2. features n enable ( en) and select signals (s0, s1) are sstl_18 compatible n optimized for use in double data rate 2 (ddr2) sdram applications n suitable to be used with 400 mbit/s to 800 mbit/s, 200 mhz to 400 mhz ddr2 data bus n switch on-resistance is designed to eliminate the need for series resistor to ddr2 sdram n 12 w on-resistance n controlled enable/disable times support fast bus turnaround n pseudo-differential select inputs support accurate and low-skew control of switching times n selectable built-in termination resistors on the sn inputs n internal 400 w pull-down resistors on xdpn port n vbias input for optimal dimm-port pull-down when disabled n con?gurable to support differential strobe with pull-up to 3 4 of v dd on channel 10 when idle n low differential skew n matched rise/fall slew rate n low crosstalk data-data/data-dqm n simpli?ed 1 : 4 switch position control by 2-bit encoded input n single input pin puts all bus switches in off (high-impedance) position n latch-up protection exceeds 500 ma per jesd78 n esd protection exceeds 1500 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 750 v cdm per jesd22-c101 3. ordering information table 1. ordering information t amb =0 c to +85 c. type number package name description version cbtu4411ee lfbga72 plastic low pro?le ?ne-pitch ball grid array package; 72 balls; body 7 7 1.05 mm sot856-1
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 3 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 4. functional diagram (1) selectable. fig 1. functional diagram (positive logic) fig 2. simpli?ed schematic, channel 0 to channel 9 fig 3. simpli?ed schematic, channel 10 002aae850 switch r t 2 (1) r t 2 (1) r t 2 (1) r t 2 (1) vref v dd s0 s1 term stren en switch control switch switch switch 0dp10 1dp10 2dp10 3dp10 hp10 switch switch switch switch 0dp0 1dp0 2dp0 3dp0 hp0 002aae848 switch hpn a from switch control vbias r pd 400 w xdpn b r on 002aae849 switch hp10 from switch control vbias r pd xdp10 r pu v dd from switch control
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 4 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 5. pinning information 5.1 pinning fig 4. pin con?guration blank cell indicates no ball at that location. fig 5. ball mapping (transparent top view) 002aae837 cbtu4411ee transparent top view l k j h f d g e c b a 246810 1357911 ball a1 index area 1 a s1 stren 0dp0 1dp0 2dp0 2dp1 3dp1 23456789 b term s0 gnd hp0 3dp0 hp1 gnd c en d vbias gnd e 2dp10 3dp10 f 1dp10 hp10 g gnd h 3dp9 2dp9 v dd j 1dp9 hp9 k 0dp9 gnd hp8 0dp8 hp7 0dp7 hp6 0dp6 l 3dp8 2dp8 3dp7 2dp7 1dp7 2dp6 1dp6 0dp2 10 hp2 11 002aae838 vref 0dp10 v dd 1dp8 1dp1 0dp1 gnd 3dp6 hp5 v dd 1dp2 0dp3 hp3 2dp3 gnd hp4 2dp4 1dp5 2dp2 2dp5 3dp5 3dp2 1dp3 3dp3 0dp4 1dp4 3dp4 0dp5
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 5 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 5.2 pin description table 2. pin description symbol pin description hp0 to hp10 b5, b8, b10, d10, g10, k10, k8, k5, k3, j2, f2 host ports en c2 lvcmos level enable input (active low). when connected high, all dimm ports will be disconnected (show a high-impedance path) from the host ports. stren a2 strobe enable. lvcmos level strobe enable input (active high). when tied low, channel 10 (hp10 and its dp ports) functions identically to all other channels. when tied high, channel 10 is designated as the strobe channel (see section 6.1 function selection , figure 2 and figure 3 ). s0 b2 select inputs; type sstl_18. see section 6.1 function selection . s1 a1 vref c1 reference voltage for the pseudo-differential sstl_18 select inputs (s0, s1). vbias d1 voltage bias for the dimm port pull-down resistor (r pd ). term b1 lvcmos level input pin activates termination resistance on sn inputs when high; high-impedance when low. 0dp0, 1dp0, 2dp0, 3dp0 a4, a5, a6, b6 dimm port 0 0dp1, 1dp1, 2dp1, 3dp1 b7, a7, a8, a9 dimm port 1 0dp2, 1dp2, 2dp2, 3dp2 a10, a11, b11, c11 dimm port 2 0dp3, 1dp3, 2dp3, 3dp3 c10, d11, e10, e11 dimm port 3 0dp4, 1dp4, 2dp4, 3dp4 f11, g11, h10, h11 dimm port 4 0dp5, 1dp5, 2dp5, 3dp5 j11, j10, k11, l11 dimm port 5 0dp6, 1dp6, 2dp6, 3dp6 k9, l9, l8, l7 dimm port 6 0dp7, 1dp7, 2dp7, 3dp7 k6, l6, l5, l4 dimm port 7 0dp8, 1dp8, 2dp8, 3dp8 k4, l3, l2, l1 dimm port 8 0dp9, 1dp9, 2dp9, 3dp9 k1, j1, h2, h1 dimm port 9 0dp10, 1dp10, 2dp10, 3dp10 g1, f1, e1, e2 dimm port 10 gnd b4, b9, d2, f10, g2, k2, k7 ground v dd a3, b3, l10 positive supply voltage
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 6 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 6. functional description refer to figure 1 functional diag r am (positiv e logic) . 6.1 function selection table 3. function selection, channel 0 to channel 9 h = high voltage level; l = low voltage level; high-z = high-impedance; x = dont care. inputs function 0dpn 1dpn 2dpn 3dpn en s1 s0 hpn vbias hpn vbias hpn vbias hpn vbias lll r on high-z high-z r pd high-z r pd high-z r pd l l h high-z r pd r on high-z high-z r pd high-z r pd l h l high-z r pd high-z r pd r on high-z high-z r pd l h h high-z r pd high-z r pd high-z r pd r on high-z h x x high-z r pd high-z r pd high-z r pd high-z r pd
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 7 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance table 4. function selection, channel 10 h = high voltage level; l = low voltage level; high-z = high-impedance; x = dont care. inputs function 0dp10 1dp10 2dp10 3dp10 en s1 s0 stren hp10 vbias v dd hp10 vbias v dd hp10 vbias v dd hp10 vbias v dd lll l r on high-z high-z high-z r pd high-z high-z r pd high-z high-z r pd high-z lll h r on high-z high-z high-z r pd r pu high-z r pd r pu high-z r pd r pu l l h l high-z r pd high-z r on high-z high-z high-z r pd high-z high-z r pd high-z l l h h high-z r pd r pu r on high-z high-z high-z r pd r pu high-z r pd r pu l h l l high-z r pd high-z high-z r pd high-z r on high-z high-z high-z r pd high-z l h l h high-z r pd r pu high-z r pd r pu r on high-z high-z high-z r pd r pu l h h l high-z r pd high-z high-z r pd high-z high-z r pd high-z r on high-z high-z l h h h high-z r pd r pu high-z r pd r pu high-z r pd r pu r on high-z high-z h x x l high-z r pd high-z high-z r pd high-z high-z r pd high-z high-z r pd high-z h x x h high-z high-z r pu high-z high-z r pu high-z high-z r pu high-z high-z r pu table 5. s0, s1 input termination h = high voltage level; l = low voltage level; x = dont care. en term sn input termination l l termination resistors on s0, s1 inputs disconnected (high-impedance). l h termination resistors on s0, s1 inputs active. h x pull-down to gnd via r t 2. also disables the s0, s1 input receivers for power savings.
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 8 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 7. limiting values [1] the input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed. 8. recommended operating conditions [1] v bias > 0.5 v dd is reserved for test purposes only. table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). the package thermal impedance is calculated in accordance with jesd 51. symbol parameter conditions min max unit v dd supply voltage - 0.5 +2.5 v i ik input clamping current v i/o <0v - - 50 ma v i input voltage s0, s1 pins only [1] -v dd + 0.3 v except s0, s1 pins [1] - 0.5 +2.5 v t stg storage temperature - 65 +150 c table 7. operating conditions all unused control inputs of the device must be held at v dd or gnd to ensure proper device operation. symbol parameter conditions min typ max unit v dd supply voltage 1.7 - 1.9 v v ref reference voltage 0.49 v dd 0.50 v dd 0.51 v dd v v bias bias voltage pull-down resistor input [1] 0 0.30 v dd 0.33 v dd v v t termination voltage v ref - 0.04 v ref v ref + 0.04 v v i input voltage 0 - v dd v v ih(ac) ac high-level input voltage s0, s1 inputs v ref + 0.250 - - v v il(ac) ac low-level input voltage s0, s1 inputs - - v ref - 0.250 v v ih(dc) dc high-level input voltage s0, s1 inputs v ref + 0.125 - - v v il(dc) dc low-level input voltage s0, s1 inputs - - v ref - 0.125 v v ih high-level input voltage en, stren, term pins 0.65 v dd --v v il low-level input voltage en, stren, term pins - - 0.35 v dd v t amb ambient temperature operating in free air 0 - +85 c
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 9 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 9. static characteristics [1] all typical values are at v dd = 1.8 v, t amb =25 c. [2] measured by the current between the host and the dimm terminals at the indicated voltages on each side of the switch. table 8. static characteristics t amb =0 c to +85 c symbol parameter conditions min typ [1] max unit v ik input clamping voltage v dd = 1.7 v; i i = - 18 ma - - - 1.2 v v t termination voltage on s0, s1 inputs when sn = open circuit and term = high 0.5v dd - 0.04 0.5v dd 0.5v dd + 0.04 v v pu pull-up voltage channel 10 dimm port; en = low; v bias = 0.54 v; v dd = 1.8 v; stren = high; unselected dimm port 0.5v dd + 0.25 0.75v dd 0.75v dd + 0.25 v i li input leakage current v dd = 1.8 v; v i =v dd or gnd; sn = v dd ; v bias =v dd ; term = low s0, s1 - - 100 m a host port - - 100 m a dimm port - - 100 m a i dd supply current v dd = 1.8 v; i o =0a; v i =v dd or gnd en=low - 6 9 ma en = high - 5 100 m a c in input capacitance s0, s1 pins; v i = 1.8 v or 0 v - 3 - pf c on switch on capacitance v i = 0.9 v - 4 6 pf r on on resistance v dd = 1.8 v; v hpn =v ref ; v xdpn =v ref 250 mv [2] 71217 w v dd = 1.8 v; v hpn =v ref ; v xdpn =v ref 500 mv [2] 71217 w d r on on resistance mismatch between channels variation over channel voltage; en = low; v bias = 0.54 v; v dd = 1.8 v; stren = low; selected dimm port v hpn = 0.5v dd + 250 mv and v xdpn = 0.5v dd - 250 mv - 1.8 2.5 w r pd pull-down resistance en = high; v bias = 0.54 v; v dd = 1.8 v 280 400 520 w channel 10; stren = low 280 400 520 w channel 10; stren = high 780 1120 1460 w r pu pull-up resistance en = high; v bias = 0.54 v; v dd = 1.8 v; channel 10; stren = high 430 622 810 w r t termination resistance sn input; thevenin equivalent (see figure 1 ); input voltage sweep 0 < v i (sn) < v dd ; term = high 55 80 105 w
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 10 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 10. dynamic characteristics [1] this parameter is not production tested. [2] skew is not production tested. [3] difference of rising edge propagation delay to falling edge propagation delay. fig 6. pull-down resistance versus voltage 350 425 400 375 450 r pd ( w ) v dimm - v bias (v) 0 0.8 0.6 0.2 0.4 002aae863 table 9. dynamic characteristics v dd = 1.8 v 0.1 v. symbol parameter conditions min typ max unit t pd propagation delay from hpn or xdpn to xdpn or hpn; figure 9 , figure 13 [1] - 50 100 ps t pzh driver enable delay to high level from sn to hpn or xdpn 0.75 - 1.75 ns t pzl driver enable delay to low level from sn to hpn or xdpn 0.75 - 1.75 ns t phz driver disable delay from high level from sn to hpn or xdpn 0.75 - 1.75 ns t plz driver disable delay from low level from sn to hpn or xdpn 0.75 - 1.75 ns t sk(o) output skew time from any output to any output; figure 12 [2] - 2530ps t sk(edge) edge skew time figure 11 [2] [3] - 2530ps
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 11 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 11. hpn to xdpn ac waveforms and test circuit fig 7. input to output propagation delays (1) see section 6.1 function selection . (2) waveform 1 is for an output with internal conditions such that the output is high except when disabled by the output control. fig 8. 3-state output enable and disable times all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; slew rate = 2.5 v/ns. the outputs are measured one at a time with one transition per measurement. fig 9. test circuit (hpn to xdpn) 002aae864 1.8 v 0 v v oh v ol t plh t phl 0.9 v 0.9 v 0.9 v 0.9 v input output 002aae865 1.8 v v ref v ref en, sn (1) 0 v v oh v bias 0.9 v v oh - 100 mv output waveform 1 (2) t pzh t phz z o = 40 w sstl_18 driver 10.16 cm (4") dut hpn xdpn z o = 40 w 2.54 cm (1") c l 6 pf 75 w v t = v ref 002aae866
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 12 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 12. xdpn to hpn ac waveforms and test circuit (1) see section 6.1 function selection . (2) waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. (3) waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. fig 10. 3-state output enable and disable times fig 11. rising and falling edge skew fig 12. skew between any two outputs 002aae867 1.8 v 1.8 v t plz v ref v ref en, sn (1) output waveform 1 (2) 0.9 v t pzl v ol 0 v v ol + 100 mv v oh v ol 0.9 v v oh - 100 mv output waveform 2 (3) t pzh t phz 002aae868 1.8 v 0 v v oh v ol rising t sk(edge) 0.9 v 0.9 v 0.9 v 0.9 v input output falling t sk(edge) 002aac820 t sk(o) any two outputs
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 13 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 13. test information all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o =50 w ; slew rate = 2.5 v/ns. the outputs are measured one at a time with one transition per measurement. fig 13. test circuit (xdpn to hpn) 10.16 cm (4") z o = 40 w sstl_18 driver dut hpn xdpn z o = 40 w 2.54 cm (1") c l 6 pf 75 w v t = v ref 002aae869 table 10. i dd test mode condition description v bias = v dd all dimm ports are disconnected (high-impedance) from their host ports, and disconnected (high-impedance) from vbias and r pu . used for production testing only. v bias < 0.5v dd normal operation. see section 6.1 function selection .
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 14 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 14. package outline fig 14. package outline sot856-1 (lfbga72) references outline version european projection issue date iec jedec jeita sot856-1 sot856-1 04-04-27 04-05-12 dimensions (mm are the original dimensions) lfbga72: plastic low profile fine-pitch ball grid array package; 72 balls; body 7 x 7 x 1.05 mm b ball a1 index area ball a1 index area c a b c d e f h k g l j 246810 1357911 d e b a a a 2 a 1 e 2 e 1 e e a c b ? v m c ? w m y c y 1 x 0 2.5 5 mm scale unit mm 0.3 0.2 1.20 0.95 0.35 0.25 7.2 6.8 a 1 a 2 b e 7.2 6.8 d ee 1 v 0.15 5 e 2 5 0.5 w 0.05 y 0.08 y 1 0.1 a max 1.5
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 15 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 15. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 15.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 15.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 16 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 15.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 15 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 11 and 12 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 15 . table 11. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 12. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 17 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 16. abbreviations msl: moisture sensitivity level fig 15. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 13. abbreviations acronym description cdm charged-device model ddr2 double data rate 2 dimm dual in-line memory module dqm data queue mask esd electrostatic discharge hbm human body model lvcmos low voltage complementary metal-oxide semiconductor mm machine model mux multiplexer prr pulse repetition rate rc resistor-capacitor network sdram synchronous dynamic random access memory sstl_18 stub series terminated logic for 1.8 v
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 18 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 17. revision history table 14. revision history document id release date data sheet status change notice supersedes cbtu4411_3 20091012 product data sheet - cbtu4411_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? section 2 f eatures : 3 rd bullet item changed from designed to be used with 400 mbit/s to 667 mbit/s, 200 mhz to 333 mhz ddr2 data bus to suitable to be used with 400 mbit/s to 800 mbit/s, 200 mhz to 400 mhz ddr2 data bus ? deleted quick reference data table ? t ab le 6 limiting v alues : symbol and parameter descriptions updated to comply with new presentation standards. ? t ab le 7 oper ating conditions : symbol and parameter descriptions updated to comply with new presentation standards. ? t ab le 8 static char acter istics : symbol and parameter descriptions updated to comply with new presentation standards. ? t ab le 9 dynamic char acter istics : symbol and parameter descriptions updated to comply with new presentation standards. ? added soldering information. ? added section 16 ab bre viations . cbtu4411_2 20060922 product data sheet - cbtu4411_1 cbtu4411_1 (9397 750 12977) 20050107 product data sheet - -
cbtu4411_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 12 october 2009 19 of 20 nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 18.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 18.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 18.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors cbtu4411 11-bit ddr2 sdram mux/bus switch with 12 w on resistance ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 12 october 2009 document identifier: cbtu4411_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 6 6.1 function selection. . . . . . . . . . . . . . . . . . . . . . . 6 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 recommended operating conditions. . . . . . . . 8 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 9 10 dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 hpn to xdpn ac waveforms and test circuit . 11 12 xdpn to hpn ac waveforms and test circuit . 12 13 test information . . . . . . . . . . . . . . . . . . . . . . . . 13 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 15 soldering of smd packages . . . . . . . . . . . . . . 15 15.1 introduction to soldering . . . . . . . . . . . . . . . . . 15 15.2 wave and re?ow soldering . . . . . . . . . . . . . . . 15 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 15.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 19 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 18.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 contact information. . . . . . . . . . . . . . . . . . . . . 19 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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