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cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 1 post office box 655303 ? dallas, texas 75265 phase-locked loop-based zero-delay buffer operating frequency: 10 mhz to 200 mhz low jitter (cycle-cycle): 100 ps over the range 66 mhz to 200 mhz distributes one clock input to two banks of four outputs auto frequency detection to disable device (power down mode) consumes less than 20 a in power down mode operates from single 3.3-v supply industrial temperature range ?40 c to 85 c 25- ? on-chip series damping resistors no external rc network required spread spectrum clock compatible (ssc) available in 16-pin tssop or 16-pin soic packages description the cdcvf25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. it uses a pll to precisely align, in both frequency and phase, the output clocks to the input clock signal. the cdcvf25081 operates from a nominal supply voltage of 3.3 v. the device also includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point loads. two banks of four outputs each provide low-skew, low-jitter copies of clkin. all outputs operate at the same frequency. output duty cycles are adjusted to 50%, independent of duty cycle at clkin. the device automatically goes into power-down mode when no input signal is applied to clkin and the outputs go into a low state. unlike many products containing plls, the cdcvf25081 does not require an external rc network. the loop filter for the pll is included on-chip, minimizing component count, space, and cost. because it is based on a pll circuitry, the cdcvf25081 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. this stabilization is required following power up and application of a fixed-frequency signal at clkin and any following changes to the pll reference. the cdcvf25081 is characterized for operation from -40 c to 85 c. function table s2 s1 1y0?1y3 2y0?2y3 output source pll shutdown 0 0 hi-z hi-z n/a. yes 0 1 active hi-z pll ? no 1 0 active active input clock (pll bypass) yes 1 1 active active pll ? no ? clk input frequency < 2 mhz switches the outputs to low level copyright ? 2001, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 clkin 1y0 1y1 v dd gnd 2y0 2y1 s2 fbin 1y3 1y2 v dd gnd 2y3 2y2 s1 d package (soic) pw package (tssop) (top view)
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 2 post office box 655303 ? dallas, texas 75265 terminal functions terminal type description name pin no. type description 1y[0:3] 2, 3, 14, 15 o bank 1yn clock outputs. these outputs are low-skew copies of clkin. each output has an integrated 25- ? series-damping resistor. 2y[0:3] 6, 7, 10, 11 o bank 2yn clock outputs. these outputs are low-skew copies of clkin. each output has an integrated 25- ? series-damping resistor. clkin 1 i clock input. clkin provides the clock signal to be distributed by the cdcvf25081 clock driver. clkin is used to provide the reference signal to the integrated pll that generates the output signal. clkin must have a fixed frequency and phase in order for the pll to acquire lock. once the circuit is powered up and a valid signal is applied, a stabilization time is required for the pll to phase lock the feedback signal to clkin. fbin 16 i feedback input. fbin provides the feedback signal to the internal pll. fbin must be wired to one of the outputs to complete the feedback loop of the internal pll. the integrated pll synchronizes the fbin and output signal so there is nominally zero-delay from input clock to output clock. gnd 5, 12 ground ground s1, s2 9, 8 i select pins to determine mode of operation. see the function table for mode selection options. v dd 4, 13 power supply voltage. the supply voltage range is 3 v to 3.6 v
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 3 post office box 655303 ? dallas, texas 75265 functional block diagram 2 1y0 pll 16 fbin 25 ? 3 1y1 25 ? 14 1y2 25 ? 15 1y3 25 ? m u x 1 clkin input select decoding 8 s2 9 s1 6 2y0 25 ? 7 2y1 25 ? 10 2y2 25 ? 11 2y3 25 ?
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? supply voltage range, v dd ? 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see notes 1 and 2) ? 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (see notes 1 and 2) ? 0.5 v to v dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) ? 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) ? 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total output current, i o (v o = 0 to v dd ) ? 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 3): pw package 147 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d package 112 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observe d. 2. this value is limited to 4.6 v maximum. 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions min nom max unit supply voltage, v dd 3 3.3 3.6 v low level input voltage, v il 0.8 v high level input voltage, v ih 2 v input voltage, v i 0 3.6 v high-level output current, i oh ? 12 ma low-level output current, i ol 12 ma operating free-air temperature, t a -40 85 c timing requirements over recommended ranges of supply voltage, load and operating free-air temperature min nom max unit clock frequency f c l = 25 pf 10 100 mhz clock frequency, f clk c l = 15 pf 66 200 mhz
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ ? max unit v ik input voltage v dd = 3 v, i i = -18 ma ? 1.2 v i i input current v i = 0 v or v dd 5 a i pd ? power down current f clkin = 0 mhz, v dd = 3.3 v 20 a i oz output 3-state v o = 0 v or v dd, v dd = 3.6 v 5 a c i input capacitance at fbin, clkin v i = 0 v or v dd 4 pf c i input capacitance at s1, s2 v i = 0 v or v dd 2.2 pf c o output capacitance v i = 0 v or v dd 3 pf v dd = min to max, i oh = -100 a v dd ? 0.2 v oh high-level output voltage v dd = 3 v, i oh = -12 ma 2.1 v v oh high level out ut voltage v dd = 3 v, i oh = -6 ma 2.4 v v dd = min to max, i ol = 100 a 0.2 v ol low-level output voltage v dd = 3 v, i ol = 12 ma 0.8 v v ol low level out ut voltage v dd = 3 v, i ol = 6 ma 0.55 v v dd = 3 v, v o = 1 v ? 24 i oh high-level output current v dd = 3.3 v, v o = 1.65 v ? 30 ma i oh high level out ut current v dd = 3.6 v, v o = 3.135 v -15 ma v dd = 3 v, v o = 1.95 v 26 i ol low-level output current v dd = 3.3 v, v o = 1.65 v 33 ma ol v dd = 3.6 v, v o = 0.4 v 14 ? all typical values are at respective nominal v dd . ? for i dd over frequency see figure 7.
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 6 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ ? max unit t (lock) pll lock time f = 100 mhz 10 s t phase offset (clkin to fbin) f = 10 mhz to 66 mhz, vth = v dd /2 (see note 5) ? 200 200 ps t (phoffset) phase offset (clkin to fbin) f = 66 mhz to 200 mhz, vth = v dd /2 (see note 5) ? 150 150 ps t plh low-to-high level output propagation delay s2 = hi g h, s1 = low (pll b y pass) 2.5 6 ns t phl high-to-low level output propagation delay s2 = high , s1 = low (pll by ass) f = 1 mhz, c l = 25 pf t sk(o) output skew (yn to yn) (see note 4) 150 ps t part to part skew s2 = high, s1 = high (pll mode) 600 ps t sk(pp) part-to-part skew s2 = high, s1 = low (pll bypass) 700 ps f = 66 mhz to 200 mhz, c l = 15 pf 100 t jit(cc) jitter (cycle-to-cycle) f = 66 mhz to 100 mhz, c l = 25 pf f = 10 mhz to 66 mhz (see figure 6) 150 ps odc output duty cycle f = 10 mhz to 200 mhz 43% 57% t sk(p) pulse skew s2 = high, s1 = low (pll bypass) f = 1 mhz, c l = 25 pf 0.7 ns t rise time rate c l = 15 pf, see figure 4 0.8 3.3 v/ns t r rise time rate c l = 25 pf, see figure 4 0.5 2 v/ns t fall time rate c l = 15 pf, see figure 4 0.8 3.3 v/ns t f fall time rate c l = 25 pf, see figure 4 0.5 2 v/ns ? all typical values are at respective nominal v dd . notes: 4. the t sk(o) specification is only valid for equal loading of all outputs. 5. similar waveform at clkin and fbin are required. for phase displacement between clkin and y-outputs see figure 5.
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 7 post office box 655303 ? dallas, texas 75265 parameter measurement information notes: a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: z o = 50 ? , t r < 1.2 ns, t f < 1.2 ns. c. the outputs are measured one at a time with one transition per measurement. 1000 ? from output under test v dd 1000 ? c l = 25 pf at f = 10 mhz to 100 mhz c l = 15 pf at f = 66 mhz to 200 mhz figure 1. test load circuit fbin 50% v dd v ol v oh clkin 0 v v dd 50% v dd t (phoffset) figure 2. voltage thresholds for measurements, phase offset (pll mode) note: odc = t 1 /(t 1 + t 2 ) x 100% 50% v dd any y any y t sk(0) 50% v dd t sk(0) 50% v dd t 1 t 2 figure 3. output skew and output duty cycle (pll mode)
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 8 post office box 655303 ? dallas, texas 75265 parameter measurement information note: t sk(p) =|t plh ? t phl | 80% any y 50% v dd 20% t f v ol v oh t r clkin 0 v v dd t phl 50% v dd t plh 80% 50% v dd 20% figure 4. propagation delay and pulse skew (non-pll mode) figure 5 cload difference between fbin and yn pins ? pf (c fb + 4 pf) ? c yn ? 150 ? 100 ? 50 0 50 100 ? 10 ? 8 ? 6 ? 4 ? 20246810 v dd = 3 v phase displacement ? ps phase displacement vs cload v dd = 3.6 v v dd = 3.3 v figure 6 f ? frequency ? mhz 0 50 100 150 200 250 300 350 400 450 500 10 20 30 40 50 60 70 80 90 100 v dd = 3.3 v all outputs switching c l (yn) = 25 pf || 500 ? cycle-to-cycle jitter ? ps cycle-to-cycle jitter vs frequency
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 9 post office box 655303 ? dallas, texas 75265 parameter measurement information f ? frequency ? mhz 0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180 200 v dd = 3 v to 3.6 v c l (yn) = 15 pf || 500 ? t a = ? 40 c to 85 c i dd ? supply current ? ma supply current vs frequency v dd = 3.6 v t a = ? 40 c v dd = 3.6 v t a = 85 c v dd = 3 v t a = ? 40 c v dd = 3 v t a = 85 c figure 7
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 10 post office box 655303 ? dallas, texas 75265 mechanical data pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 ? 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
cdcvf25081 3.3-v phased-lock loop clock driver scas671 ? october 2001 11 post office box 655303 ? dallas, texas 75265 mechanical data d (r-pdso-g**) plastic small-outline package 8 pins shown 8 0.197 (5,00) a max a min (4,80) 0.189 0.337 (8,55) (8,75) 0.344 14 0.386 (9,80) (10,00) 0.394 16 dim pins ** 4040047/e 09/01 0.069 (1,75) max seating plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) nom 0 ? 8 gage plane a 0.004 (0,10) 0.010 (0,25) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
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