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technical data quard uart with 256-byte fifo IN16C1054 1. functional description IN16C1054 is a quad uart(universal asynchronous receiver /transmitter) with 256-byte fifo supporting maximum communication speed of 5.3mbps. it offers flow control func tion by hardware or software and signal lines which can open or close the tx/rx input/output when co mmunicating by rs-422 or rs-485. it c an handle four interrupt signals (int0, int1, int2 and int3) with one global interrupt signal line (gint) and offers a new ?xoff re-tr ansmit? function in addition to xon any character. uart can convert 8-bit parallel data to asynchronous serial dat a and vice versa. it can transmit 5 to 8-bit letters, program i/o interrupt trigger level and has 256-byte i/o data fifo. uart can generate any baud rate using clock and programmable divisor, transmit data with even, odd or no parity and 1, 1.5, 2 stop bit, and detect break, idle, framing error, fifo overflow and parity error in input data. uart has a software interface for modem controlling. IN16C1054 offers tqfp80 and plcc68 packages. 2. features ? 4 channel uart ? 3.3v operation ? 5v tolerant inputs ? pin-to-pin compatible with industry standard sb16c554 with additional ? enhancements ? up to 5.3 mbps baud rate (up to 85 mhz oscillator input clock) ? 256-byte transmit fifo ? 256-byte receive fifo with error flags ? industrial temperature range (-20 to +85 ) ? programmable and selectable transmit and receive fifo trigger levels for dma ? and interrupt generation ? software (xon/xoff) / hardware (rts#/cts#) flow control - programmable xon/xoff characters - programmable auto-rts and auto-cts ? global interrupt mask/poll control ? optional data flow resume by xon any character control ? optional data flow additional halt by xoff re- transmit control ? rs-422 point to point/multi-drop control ? rs-485 echo/non echo control ? dma signaling capability for both received and transmitted data ? software selectable baud rate generator ? prescaler provides additional divide-by-4 function ? fast data bus access time ? programmable sleep mode ? programmable serial interface characteristics - 5, 6, 7, or 8-bit characters - even, odd, or no parity bit generation and detection - 1, 1.5, or 2 stop bit generation ? false start bit detection ? line break generation and detection ? fully prioritized interrupt system controls ? modem control functions (rts#, cts#, dtr#, dsr#, dcd#, and ri#) rev. 00
IN16C1054 3. ordering information table 1: ordering information part number package operating temperature range device status IN16C1054-tq 80-pin tqfp -20 to +85 active IN16C1054-pl 68-pin plcc -20 to +85 active 4. block diagram figure 1: block diagram signal cts0#/dsr0#/dcd0#/ri0# logic txrdy3#/rxrdy3# modem register receive flow register uart 1 intrrupt generator control interrupt rts0#/dtr0# logic clock and xtal2 txrdy1#/rxrdy1# cts1#/dsr1#/dcd1#/ri1# txrdy2#/rxrdy2# receive shift shift rxd2 transmit cts2#/dsr2#/dcd2#/ri2# txd2 txd0 xtal1 rxd0 logic control register txd1 txrdy0#/rxrdy0# uart 0 rxd1 fifo logic logic txrdy#/rxrdy# global rts2#/dtr2# rts3#/dtr3# fifo reset cs#[3:0] rts1#/dtr1# register d[7:0] flow cts3#/dsr3#/dcd3#/ri3# int[3:0] control transmit control clksel register uart 2 rxd3 logic control uart 3 baud rate sb16c1054 logic control control data and ior#/iow# a[2:0] txd3 rev. 00
IN16C1054 5. pin configuration 5.1 pin configuration for 80-pin tqfp package figure 2: 80-pin tqfp pin configuration 27 9 63 cs1# 80 74 ri1# xtal2 dsr3# 54 39 cts1# rxd0 vcc dcd0# nc - no internal connection 43 int2 45 3 37 31 xtal1 19 48 rxrdy1#/rxen1 cts3# 79 57 61 ri2# 50 int3 76 dtr0#/txen0 41 rxd1 1 21 a0 59 rxrdy3#/rxen3 13 60 64 nc dcd3# d2 cts2# 67 nc rxrdy# 75 22 78 dsr0# 30 15 68 txrdy3#/txen3 8 rxrdy2#/rxen2 rts3#/txen3 reset ior# rxd3 rts2#/txen2 29 56 cts0# txd0 55 rts0#/txen0 vcc txd1 d5 gnd 14 72 ri3# 18 53 44 txd3 cs2# txrdy2#/txen2 cs0# 52 10 36 txrdy0#/txen 0 a1 16 txd2 62 dtr2#/txen2 dcd2# 17 dsr2# 51 28 46 dsr1# nc rxd2 a2 d6 intsel int0/gint d7 gnd 34 rts1#/txen1 33 71 11 32 4 dcd1# nc 2 35 d0 73 38 40 dtr3#/txen3 49 txrdy# 42 d4 cs3# clksel 65 70 66 ri0# 76 nc 69 26 iow# 77 5 24 rxrdy0#/rxen0 25 gnd vcc 23 gnd int1 47 txrdy1#/txen 1 dtr1#/txen1 20 58 d3 12 d1 rev. 00
IN16C1054 5.2 pin configuration for 68-pin plcc package figure 3: 68-pin plcc pin configuration 58 dsr0# dtr1#/txen1 a0 42 int3 5 16 d0 gnd a1 43 29 rts3#/txen 3 dcd0# rxd0 6 17 d1 rts1#/txen1 a2 59 44 30 gnd dcd3# ri0# 76 1 18 d2 int1 nc 60 45 31 dtr3#/txen 3 dsr2# 86 2 48 cs1# clksel nc - no internal connection 46 32 cts3# cts2# 63 txd1 rxd1 dcd2# 47 33 19 dtr2#/txen 2 d3 64 9 iow# ri1# ri2# 49 34 20 vcc d4 65 txd0 dcd1# rxd2 50 35 21 rts2#/txen 2 d5 66 gnd 51 36 22 int2 d6 txrdy# 52 37 23 ri3# cs0# 10 67 dsr3# rxrdy# 53 38 24 rxd3 int0/gint 11 cs2# 68 reset 54 25 vcc rts0#/txen0 12 txd2 1 55 26 intsel vcc 39 13 ior# 2 56 27 d7 dtr0#/txen0 dsr1# xtal2 40 14 txd3 3 57 28 gnd cts0# cts1# xtal1 41 15 cs3# 4 rev. 00
IN16C1054 rev. 00 5.3 pin description table 2: pin description data bus interface name pin type description tqfp80 plcc68 a0 a1 a2 48 47 46 34 33 32 i i i address bus lines [2:0]. these 3 address lines select one of the internal registers in uart channel 0-3 during a data bus transaction. d0 d1 d2 d3 d4 d5 d6 d7 7 8 9 11 12 13 14 15 66 67 68 1 2 3 4 5 i/o i/o i/o i/o i/o i/o i/o i/o data bus lines [7:0]. these pins are tri-state data bus for data transfer to or from the controlling cpu. ior# 70 52 i read data (active low strobe). a valid low level on ior# will load the data of an internal register defined by address lines a [2:0] onto the uart data bus for access by an external cpu. iow# 31 18 i write data (active low strobe). a valid low level on iow# will transfer the data from external cpu to an internal register that is defined by address lines a [2:0]. cs0# cs1# cs2# cs3# 28 33 68 73 16 20 50 54 i i i i chip select 0, 1, 2, and 3 (active low). these pins enable data transfers between the exte rnal cpu and the uart for the respective channel. int0/gint int1 int2 int3 27 34 67 74 15 21 49 55 o o o o interrupt 0/global inte rrupt, interrupt 1, 2, and 3. these pins provide individual channel interrupts or global interrupt. int0-3 are enabled when mcr[3] is set to ?1? and afr[4] is cleared to ?0? (default state). but int0 operates as gint and int1-int3 are disabled when afr[4] is set to ?1?. int0-3?s asserted state is active high, but gint?s asserted state is determined by afr[5 ]. gint?s asserted state is active high when afr[5] is set to ?1?, and active low when afr[5] is cleared to ?0?. intsel 6 65 i interrupt select. when intsel is left open or low state, the tri-state interrupts available on int0-3 are enabled by mcr[3]. but, when intsel is in high state, int0-3 are always enabled.
IN16C1054 rev. 00 table 2: pin description? continued name pin type description tqfp80 plcc68 txrdy0#/txen0 txrdy1#/txen1 txrdy2#/txen2 txrdy3#/txen3 21 40 61 80 - - - - o o o o transmitter ready 0, 1, 2, and 3/tx enable 0, 1, 2, and 3. these pins provide individual channel transmitter ready or transmit enable. txrdy0-3# are enabled when atr[1:0] is cleared to ?00? (default state). if atr[1:0] are set to ?11?, txrdy0-3# operate as txen0-3. txrdy0-3# (active low) are asserted by tx fifo/thr status for transmit channels 0- 3. txen0-3?s asserted state is determined by atr[5:4]. if at r[4] is cleared to ?0?, the state holds the same value as at r[5]. if atr[4] is set to ?1?, it is the auto-toggling state based on atr[5]. if these pins are unused, leave them unconnected. rxrdy0#/rxen0 rxrdy1#/rxen1 rxrdy2#/rxen2 rxrdy3#/rxen3 20 41 60 1 - - - - o o o o receiver ready 0, 1, 2, and 3/rx enable 0, 1, 2, and 3. these pins provide individual channel receiver ready or receive enable. rxrdy0-3# are enabled when atr[1: 0] is cleared to ?00? (default state). if atr[1:0] is set to ?11?, rxrdy0-3# are changed to rxen0-3. rxrdy0-3# (active low) are asserted by rx fifo/rbr status for receive channels 0-3. rxen0-3?s asserted state is determined by atr[7:6]. if atr[6] is cleared to ?0?, the state holds the same value as atr[7]. if atr[6] is set to ?1?, it is the auto-toggling stat e based on atr[7]. if these pins are unused, leave them unconnected. txrdy# 55 39 o transmitter ready (active low). this is asserted by tx fifo/thr status for transmit channels 0-3. rxrdy# 54 38 o receiver ready (activ e low). this is asserted by rx fifo/rhr status for receive channels 0-3. modem and serial i/o interface name pin type description tqfp80 plcc68 txd0 txd1 txd2 txd3 29 32 69 72 17 19 51 53 o o o o transmit data. these pins are individual transmit data output. during the local loop-ba ck mode, the txd output pin is disabled and txd data is inte rnally connected to the rxd input. rxd0 rxd1 rxd2 rxd3 17 44 57 4 7 29 41 63 i i i i receive data. these pins are individual receive data input. during the local loop-back m ode, the rxd input pin is disabled and rxd data is inter nally connected to the txd output.
IN16C1054 rev. 00 table 2: pin description? continued name pin type description tqfp80 plcc68 rts0# rts1# rts2# rts3# 26 35 66 75 14 22 48 56 o o o o request to send (active low). these pins indicate that the uart is ready to send data to the modem, and affect transmit and receive operations only when auto-rts function is enabled. cts0# cts1# cts2# cts3# 23 38 63 78 11 25 45 59 i i i i clear to send (active low). these pins indicate the modem is ready to accept transmi tted data from the uart, and affect transmit and receive operations only when auto-cts function is enabled. dtr0# dtr1# dtr2# dtr3# 24 37 64 75 12 24 46 58 o o o o data terminal ready (active low). these pins indicate uart is ready to transmit or receive data. dsr0# dsr1# dsr2# dsr3# 22 39 62 79 10 26 44 60 i i i i data set ready (active low). these pins indicate modem is powered-on and is ready for data exchange with uart. dcd0# dcd1# dcd2# dcd3# 29 32 69 72 17 19 51 53 i i i i carrier detect (active low). thes e pins indicate that a carrier has been detected by modem. ri0# ri1# ri2# ri3# 17 44 57 4 7 29 41 63 i i i i ring indicator (active low). these pins indicate the modem has received a ringing signal from telephone line. a low to high transition on these input pins generates a modem status interrupt, if enabled. other interfaces name pin type description tqfp80 plcc68 xtal1 50 35 i crystal or external clock input. xtal2 51 36 o crystal or buffered clock output. clksel 45 30 i clock select. this pin selects the divide-by-1 or divide-by-4 prescalable clock. during the reset, the high on clksel selects the divide-by-1 prescaler. the low on clk selects the divide-by-4 prescaler. the inverting value of clksel is latched into mcr[7] at the trailing edge of reset. reset 53 37 i reset (active high). this pin will reset the internal registers and all the outputs. vcc 5, 25, 65 13, 47, 64 i power supply input. 3.3v (2.7v ~ 3.6v) gnd 16, 36, 56, 76 6, 23, 40, 57 i signal and power ground. nc 10, 30, 47, 52, 71 31 - no internal connection.
IN16C1054 rev. 00 6. functional description the IN16C1054 uart is pin-to-pin compatible with the tl16c554 and st16c654 uarts. IN16C1054 offers 16c450 and 16c650 modes. when fi fo is enabled, it has a register configuration compatible with 64-byte fifo and 16c654, so it becomes compatible with 16c654. if you enable 256-byte fifo, you use the unique suprem e function that IN16C1054 offers. it offers communication speed up to 5.3mbps and more enhanced functions that other uarts with 128-byte fifo do not. IN16C1054 can select hardware/software flow cont rol. hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the rts# output and cts# input signals. software flow control automatically controls data flow by using programmable xon/xoff characters. 6.1 fifo operation IN16C1054?s fifo has two modes, 64-byte fifo mode and 256-byte fifo mode. setting fcr[0] to ?1? enables fifo, and if afr[0] is set to ?0?, it operates in 64-byte fifo mode(default). in this mode, transmit data fi fo, receive data and receive status fifo are 64 bytes. 64-byte fifo mode allows you to select the transmit interrupt trigger level from 8, 16, 32, or 56. you can verify this in terrupt trigger level by ttr and rtr. in this mode ttr and rtr are read only. and by fcr[5:4], xoff trigger level can be se lected to either 8, 16, 56, or 60, and xon trigger level to either 0, 8, 16, or 56 by fcr[7:6]. you can verify xon and xoff trigger level by fur and flr. in 64-byte fifo mode ttr and rtr are read only. if you select 256-byte fifo mode, you c an experience more powerful features of IN16C1054. setting both fcr[0] and afr[0] to ?1? will enable this mode. in this mode, transmit data fifo, receive data and receiv e status fifo are 256 bytes. interrupt trigger level and xon, xoff trigger level are controlled by ttr, rtr, fur and flr, not by fcr[7:4]. that is, ttr, rtr, f ur and flr can both read and write. you can verify free space of transmit fifo and the number of characters received in receive fifo by tcr, rcr and isr[7:6]. while tx fifo is full, the value sent to thr by cpu disappears. and while rx fifo is full, the data coming from external devices di sappear as well, provided that flow control function is not used. for more informati on, refer to register description. 6.2 hardware flow control hardware flow control is executed by au to-rts and auto-cts. auto-rts and auto-cts can be enabled/disabled independently by progr amming efr[7:6]. if auto-rts is enabled, it reports that it c annot receive more data by a sserting rts# when the amount of received data in rx fifo exceeds the wri tten value in fur. then after the data stored in rx fifo is read by cpu, it reports t hat it can receive new data by deasseting rts# when the amount of existing data in rx fifo is less than the written value in flr. when auto-cts is enabled and cts# is cleared to ?0?, transmitting data to tx fifo has to be suspended because external device has repor ted that it cannot accept more data. when data transmission has been suspended and cts# is set to ?1?, data in tx fifo is retransmitted because external device has report ed that it can accept more data. these operations prevent overrun during communicati on and if hardware flow control is disabled and transmit data rate exceeds rx fifo se rvice latency, overrun error occurs.
IN16C1054 6.2.1 auto-rts to enable auto-rts, efr[6] should be set to ?1?. once enabled, rts# outputs ?0?. if the number of received data in rx fifo is larger than the value stored in fur, rts# will be changed to ?1? and if not, holds ?0?. this state indicates that rx fifo can accept more data. after rts# changed to ?1? and reported to the cpu that it cannot accept more data, the cpu reads the data in rx fifo and then the amount of data in rx fifo reduces. when the amount of data in rx fifo equals the value written in flr, rts# changes to ?0? and reports that it can acc ept more data. that is, if rts# is ?0? now, rts# is not changed to ?1? until the amount in rx fifo exceeds the value set in fur. but if rts# is ?1? now, rts# is not changed to ?0? until the amount in rx fifo equals the value written in flr. the value of fur and flr is determined by fifo mode. if fcr[7:6] holds ?00?, ?01?, ?10?, and ?11?, fur stores 8, 16, 56, and 60, respective ly. and if fcr[5:4] holds ?00?, ?01?, ?10?, and ?11?, flr stores 0, 8, 16, and 56, respec tively in 64-byte fifo. in 256-byte fifo mode, users can write fur and flr values as they want and use them. but the value of fur must be larger than that of flr. while auto-rts is enabled, you can verify if rts# is ?0? or ?1? by fsr[5]. if fsr[5] is ?0?, rt s# is ?0? and if ?1?, rts# is ?1?, too. when ier[6] is set to ?1? and rts# is changed from ?0? to ?1? by auto-rts function, interrupt occurs and it is displayed on isr[ 5:0]. interrupts by auto-rts function are removed if msr is read. rts# is changed from ?0? to ?1? after the first stop bit is received. figure 4 shows the rts# timing chart while auto-rts is enabled. in figure 4, data byte n-1 is received and rts# is deasserted w hen the amount of data in rx fifo is larger than the value wri tten in fur. uart completes transmitting new data (data byte n) which has started bei ng transmitted even though external uart recognizes rts# has been deasserted. after that, the device stops transmitting more data. if cpu reads data of rx fifo, the va lue of rcr decreases and then if that value equals that of flr, rts# is asserted fo r external uart to transmit new data. flr + 1 flr + 0 rcr[7:0] start fur + 1 fur + 0 rts# da ta by te n stop rxd da ta by te n start stop da ta by te n- 1 fur - 0 fur - 1 start fur -0 ior# da ta by te 2 da ta by te 1 figure 4: rts# functional timing rev. 00
IN16C1054 rev. 00 6.2.2 auto-cts setting efr[7] to ?1? enables auto-rts. if enabl ed, data in tx fifo are determined to be transmitted or suspended by the value of cts# . if ?0?, it means external uart can receive new data and data in tx fifo are tr ansmitted through txd pin. if ?1?, it means external uart can not accept more data and data in tx fifo are not transmitted. but data being transmitted by then complete tr ansmission. these procedures are performed irrespective of fifo modes. while auto-cts is enabled, you can verify the input value of cts# by fsr[1]. if ?0?, cts# is ?0? and it means external uart can accept new data, if ?1?, cts# is ?1? and it means external ua rt can not accept more data and data in tx fifo are not being transmitted. if ier[7] is se t to ?1?, interrupt is generated by auto-cts when the input of cts# is changed from ?0? to ?1?, and it is shown on isr[5:0]. interrupts generated by auto-cts are removed if msr is read.
IN16C1054 rev. 00 6.3 software flow control software flow control is performed by xon and xoff character transmitting/accepting. software flow control is enabled/disabl ed independently by programming efr[3:0] and mcr[6:5, 2]. if tx software flow control is enabled by efr[3:2], xoff character is transmitted to report that dat a can not be accepted when t he stored amount of data in rx fifo exceeds the value in fur. after t he cpu reads the data in rx fifo and if the read amount is less than the value in flr, x on character is transmitted to report that more data can be accepted. if tx software fl ow control is enabled by efr[1:0] and xoff character is inputted through rxd pin, it means no more data can be accepted, and data transmission is suspended ev en though data are in tx fifo. if xon character is received through rxd pin while data transmi ssion is suspended, it means more data can be accepted, and ther efore data in tx fifo are re -transmitted. these procedures prevent overruns during communication. if so ftware flow control is disabled, overrun occurs when the transmit data rate exceeds rx fifo service latency. different combinations of software flow control c an be enabled by setting different combinations of efr[3:0] . table 3 shows software flow control options. table 3: software flow control options (efr[3:0]) efr[3] efr[2] efr[1] efr[0] tx, rx software flow controls 0 0 x x no transmit control 1 0 x x transmit xon1/xoff1 0 1 x x transmit xon2/xoff2 1 1 x x transmit xon1, xon2/xoff1, xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1/xoff1 x x 0 1 receiver compares xon2/xoff2 x x 1 1 receiver compares xon1, xon2/xoff1, xoff2 0 0 0 0 no transmit control, no receive flow control 0 0 1 0 no transmit control, receiver compares xon1/xoff1 0 0 0 1 no transmit control, receiver compares xon2/xoff2 0 0 1 1 no transmit control, receiv er compares xon1, xon2/xoff1, xoff2 1 0 0 0 transmit xon1/xoff1, no receive flow control 1 0 1 0 transmit xon1/xoff1, re ceiver compares xon1/xoff1 1 0 0 1 transmit xon1/xoff1, re ceiver compares xon2/xoff2 1 0 1 1 transmit xon1/xoff1, receiver compares xon1, xon2/xoff1, xoff2 0 1 0 0 transmit xon2/xoff2, no receive flow control 0 1 1 0 transmit xon2/xoff2, re ceiver compares xon1/xoff1 0 1 0 1 transmit xon2/xoff2, re ceiver compares xon2/xoff2 0 1 1 1 transmit xon2/xoff2, receiver compares xon1, xon2/xoff1, xoff2 1 1 0 0 transmit xon2/xoff2, no receive flow control 1 1 1 0 transmit xon2/xoff2, xoff2 , receiver compares xon1/xoff1 1 1 0 1 transmit xon1, xon2/xoff1, xo ff2, receiver compares xon2/xoff2 1 1 1 1 transmit xon1, xon2/xoff1, xoff2, re ceiver compares x on1, xon2/xoff1, xoff2
IN16C1054 rev. 00 6.3.1 transmit software flow control to make transmit software flow control enabled, efr[3:2] must be set to ?01?, ?10? or ?11?. unlike auto-rts in which ?0? is outputted on rts# when tx software flow control function is enabled, xon character is not trans mitted at first. if the amount of data in rx fifo (written in isr[6] and rcr) is less than the value in fur, xon character is not transmitted because xon is in init ial state. but if the amount of data in rx fifo exceeds the value in fur, xoff character is transmi tted immediately. transmitting xoff character means no more data can be accepted and after cpu reads data in rx fifo, data in rx fifo decreases. when the amount of data in rx fifo is same as the value of flr, xon character is transmitted and it means reporting to external uart that it can accept more data. after transmitting xoff character, xon c haracter is not transmi tted until the amount of data in rx fifo is same as the value of flr. the value of flr is determined by fifo mode. if fcr[7:6] is ?00?, ?01?, ?10?, and ?11?, fur is 8, 16, 56, and 60, respectively. and if f cr[5:4] is ?00?, ?01?, ?10?, and ?11?, flr is 0, 8, 16, and 56, respectively in 64-byte fif o. in 256-byte fifo mode, users can input values in fur and flr as they want and use them. but the value in fur must be larger than that of flr. while tx software flow contro l is active, its status (if xon or xoff) can be verified by fsr[4]. if fsr[4] is ?0?, the status is xon and if ?1?, the status is xoff. it can be verified by fsr[4] only. and for there is no condition to generate interrupt, interrupt doesn?t occur. it is different from that inte rrupt is generated by ier[5] when rx software flow control is enabled. 6.3.2 receive software flow control to make receive software flow control enabled, efr[1:0] must be set to ?01?, ?10? or ?11?. when enabled, data in tx fifo are determined to be transmitted or suspended by incoming xon/xoff characters. if xon character is received, it means external uart can accept new data, and data in tx fifo are transmitted through txd pin. if xoff character is received, it means external uart can not accept more data, and data in tx fifo are not transmitted. but data being transmitted by t hat time are completely transmitted. these procedures are performed irrespective of fifo modes. while receive software flow control is enabled, you can verify if the rx software flow control status is xon or xoff by fsr[0]. if it is ?0?, rx software flow control status is xon and it means external uart can accept new data. if ?1?, rx softwar e flow control status is xoff and it means external uart can not accept more data and data in tx fifo are not being transmitted. if ier[5] is set to ?1?, interrupt is generated when xoff character is received and it is shown on isr[5:0]. interrupts generated by rx software flow control are removed if isr is read or xon character is received. general problems in using xo n/xoff function and tips for using xon/xoff character as one character are as follows. when rx software flow control and auto-cts are enabled, lsr?s transmit empty bit and transmit holding empty bit are not affected even though rx flow control status is xoff or ?1? is inputted on cts# pin, so data in tx fifo are suspended. that is, these two bits are set to ?1? if there is space available in tx fifo. xon/xoff character which generated parity error are tr eated as normal xon/xoff character. if xon and xoff character are set to same , both characters are treated as xon character. tips for using xon/xoff character as two characters are as follows.
IN16C1054 rev. 00 if received characters are xon1, xon1 and x on2, rx flow control status becomes xon and previous xon1 is ignored. if received characters are xoff1, xoff1 and xoff2, rx flow control status becomes xoff and previous xoff1 is ignored. if received characters are repeated as xon1 xoff1, xon1 and xoff1, there is no effect in rx flow control status and these characters are not tr eated as data. but if received characters are xon1 xoff1, xon1, xoff1, xon1 and xon2, rx flow control status becomes xon. if received characters are xon1 xoff1, xon1, xoff1 and xoff2, rx flow control status becomes xoff. if xon1 and xoff1 characters do not pr ecede xon2 and xoff2, xon2 and xoff2 are treated as data and stored in rx fifo. if xon1 is not accompanied with xon2 or xo ff1 character, it is treated as data and stored in rx fifo. if xoff1 is not accompanied with xoff2 or xon1 character, it is treated as data and stored in rx fifo. as seen before, if received characters ar e xon1, xoff2, xon2 or xoff1, xon2, xoff2, these characters are all treated as data and stored in rx fifo. if characters are arrived continuously like x on1, xon2 or xoff1, xoff2, descriptions are as follows. if xon1, xon2 characters and xoff1, xoff2 c haracters are same with each other, all characters are treated as no rmal xon and xoff characters. if xon1, xoff1 characters and xon2, xoff2 characters are same with each other, these are treated as no rmal xon characters. if xon1, xon2, xoff1 characte rs are same and xoff2 is different, these are treated as normal xon, xoff characters. if xon1, xon2, xoff2 characte rs are same and xoff1 is different, these are treated as normal xon, xoff characters. if xon2, xoff1, xoff2 characte rs are same and xon1 is different, these are treated as normal xon, xoff characters. if xon1, xoff1, xoff2 characte rs are same and xon2 is different, these are treated as normal xon, xoff characters. if xon2, xoff1 characters are same and x on1, xoff2 are different, these are treated as normal xon, xoff characters. if xon1, xon2, xoff1, xoff2 are all same, these are treated only as normal xon characters. in all these cases no xon/xoff c haracters are treated as data. refer to table 4 below. table 4: xon/xoff character recognition logic table
IN16C1054 rev. 00 xon1 char. xon2 char. xoff1 char. xoff2 char. recognition of xon char. recognition of xoff char. 11h 11h 13h 13h yes yes 11h 13h 11h 13h yes no 11h 11h 11h 13h yes yes 11h 11h 13h 11h yes yes 11h 13h 13h 13h yes yes 11h 13h 11h 11h yes yes 11h 13h 13h 14h yes yes 11h 11h 11h 11h yes no in case xon/xoff software flow contro l function and xon any function is enabled, descriptions are as follows. if xon, xoff characters are used as one character, if xoff character arrives during xon status, status changes to xoff. if xon character arrives during xoff status, status changes to xon. if xoff character arrives during xoff st atus, status changes to xon but xoff character is not treated as data. if xon, xoff characters are used as two characters, if only xon1 or xon1 + xon2 character arrive s during xoff status, status changes to xon and all characters ar e not treated as data. if only xon2 character arrives during xoff status, status changes to xon and xon2 character is treated as data and stored in rx fifo. if xoff1 + xoff2 character arrives duri ng xon status, status changes to xon. if xoff1 + xoff2 character arrives during xoff status, status is changed to xon by xoff1 and changed to xoff again by xoff2. in case software flow control function and special character function is enabled, descriptions are as follows. if xoff1 character is used as software flow control character, character in xoff2 register is recognized as special character. if xoff2 character is used as software flow c ontrol character, it is not recognized as special character but as xoff character because both are same. if xoff1, xoff2 character is sequential and xoff1 + xoff2 character is used as software flow control character, it is not recognized as special character but as xoff2 character because both are same. if xoff1 + xoff2 character is used as so ftware flow control character and xoff2 character which does not follow after xoff1 c haracter arrives, it is not recognized as xoff2 character but as special character even though both are same.
IN16C1054 rev. 00 6.3.3 xon any function while rx software flow control function is enabled, data in tx fifo are transmitted when received xon character and transmission is suspended when xoff character is received. this status is called ?xoff status?. transmission is re-s tarted when status changes to ?xon status? by incoming xon character or xon any function that changes status when any data arrives. xon any function is enabled if mcr[5] is set to ?1?. while it is enabled, xoff status changes to xon status though xoff character arrives. details about it are described in 6.3. 2 receive software flow control. 6.3.4 xoff re-transmit function while tx software flow control function is active, xoff character is transmitted when the amount of data in rx fifo exceeds the val ue of fur. though it received xoff character, external uart may not recognize this char acter for some reason and continue to transmit data. under tx software flow control, because xoff character had been transmitted once before, it is not transmitted agai n though more data arrive. in this situation, overflow may occur in rx fifo. conventional uarts c an not deal this situation but sb16c1054 does with xoff re-transmit function. xoff re-transmit function transmits xoff c haracter again when more data arrives from external uart though it transmitted xoff charac ter before. by this function the external uart can recognize xoff character and stop transmitting data though it didn?t recognize the xoff character before. there are four xoff re-transmitting settings by xrcr[1:0]. xoff character can be re- transmitted when every 1, 4, 8 or 16 data arrives in xoff status. if xrcr[1:0] is ?00?, xoff character is re -transmitted whenever 1 more data arrives in xoff status. if xrcr[1:0] is ?01?, xoff charac ter is re-transmitted whenever 4 more data arrives in xoff status. if ?10?, 8 more data and if ?11?, 16 more data. if the value of fur is approaching the fifo size, 256-byte, it is good to write xrcr[1:0] ?00?. if the 256-fur value is small, it is good to select ?00? of xrcr and if large, it is good to select ?11?. xoff re-transmit function is enabled by m cr[6] and mcr[2]. change mcr[2] from op1# function to xoff re-transmit function by setting mcr[6] to ?1? and set mcr[2] to ?1? again. then xoff re-transmit function is enabled. when disabling it, first set mcr[6] to ?1? and then clear mcr[2] to ?0?.
IN16C1054 rev. 00 6.4 interrupts as there are four independent 1-channel uarts in sb16c1054, so there are four interrupts. interrupts are assigned int0, in t1, int2, and int3 for each channel. each interrupt has six prioritized level?s interr upt generation capability. the ier enables each of the six types of interrupts and int signal in response to an interrupt generation. when an interrupt is generated, the isr indicates that an interrupt is pending and provides the type of interrupt. and sb16c1054 can handle for four interrupts with one global interrupt. global interrupt treats four of each interrupt as one interrupt, so it is useful when external system has few interrupt resource. global inte rrupt line is also used as int0, and it is determined by afr[4] that whic h one is used. if afr[4] is cleared to ?0?, int0/gint pin is selected as int0 and if set to ?1?, gint. w hen you treat four interrupts as one interrupt, you should use several additional functions. gicr determines whether global interrupt occurs or not. while gicr[0] is set to ?1 ?, an interrupt that is generated in four one- channel uarts and treated as unmask is transmitt ed to gint. but if gicr[0] is cleared to ?0?, an interrupt is not transmitted to gint though interrupts ar e generated in four one- channel uarts and treated as mask. so this in terrupt is not transmitted to external cpu. the status of global interrupt and generation of inte rrupts in one-channel uart can be verified by gisr. the value set in gicr[0] is reflected in gisr[7], so the status of mask of global interrupt can be verified. gisr[0] shows the status of interrupt of uart that is connected to cs0#. if gisr[0] is clear ed to ?0?, it means that interrupt is not generated in the uart of cs0# and if set to ?1?, it means that inte rrupt is generated. the value of gisr[0] shows the status of interrupt generat ed in the uart of cs0#, irrespective of the value set in gicr[0 ]. gicr[0] determines w hether the interrupts generated in four one-channel ua rts that is connected to cs0#, cs1#, cs2#, and cs3# are transmitted to external devices or not, but does not determine w hether the interrupts are generated or not in uarts. the value of output signal when an interrupt is generated in gint pin is selected by afr[5]. that is , gint can determine the polarity of asserted status. if afr[5] is cleared to ?0?, gint out puts ?0? when global inte rrupt is generated. and if set to ?1?, outputs ?1? w hen global interrupt is generated.
IN16C1054 6.5 dma operation transmitter and receiver dma operation is available through txrdy#, rxrdy#, txrdy[3:0]#, and rxrdy[3:0]#. there are tw o modes of dma operation, dma mode 0 or dma mode 1, selected by fcr[3]. in dma mode 0 or fifo disable (fcr[3] = 0), dma occurs in single character transfer. in dma mode 1, multi-character dma transfers are managed to relieve the cpu for longer periods of time. 6.5.1 single dma transfer (dma mode 0/fifo disable) transmitter: there are no character in tx fifo or thr. and the txrdy# and txrdy[3:0]# signals will be in assert state. txrdy#, txrdy[3:0]# will switch to deassert state after one character is loaded into tx fifo or thr. receiver: there is at least one characte r in rx fifo or rhr. and the rxrdy# and rxrdy[3:0]# signals will be in assert state. once rxrdy# is a sserted, rxrdy[3:0]# signal will switch to deassert state when ther e are no more characters in rx fifo or rbr. figure 5 shows txrdy#, txrdy[3:0]#, rxrdy#, and rxrdy[3:0]# in dma mode 0/fifo disable. figure 5: txrdy#/txrdy[3:0]# and rxrdy#/ rxrdy[3:0]# in dma mode 0/fifo disable. tcr tx fifo empty tcr isr[6] 01h rxrdy#, rxrdy[3:0]# 0 empty space tx fifo 00h rcr 0 isr[7] character #1 empty space 01h txrdy#, txrdy[3:0]# isr[6] at least one location fille d isr[7] 0 rcr txrdy#, txrdy[3:0]# rx fifo empty rxrdy#, rxrdy[3:0]# 1 00h at least one location filled rx fifo character #1 rev. 00
IN16C1054 6.5.2 block dma transfer (dma mode 1) transmitter: when the characters in tx fifo ar e less than the trigger level that is set in ttr, txrdy# or txrdy[3:0] signal is asserted. when tx fifo is full, txrdy# or txrdy[3:0]# signal is deasserted. receiver: when the characters in rx fifo are more than the trigger level that is set in rtr, rxrdy# or rxrdy[3:0] signal is assert ed. when rx fifo is empty, rxrdy# or rxrdy[3:0]# signal is deasserted. the figure 6 below shows txrdy#, txrdy[3:0]# and rxrdy#, rx rdy[3:0]# in dma mode 1. figure 6: txrdy#/txrdy[3:0]# and rxrdy#/rxrdy[3:0]# in dma mode 1. 6.6 sleep mode with auto wake-up the sb16c1054 provides sleep mode operation to reduce its power consumption when sleep mode is activated. sleep mode is enabled when efr[4] and ier[4] are set to ?1?. sleep mode is activated when: rxd input is in idle state. cts#, dsr#, dcd#, and ri# are not toggling. the tx fifo and tsr are in empty state. no interrupt is pending except thr and time-out interrupts. in sleep mode, the sb16c1054 clock and baud rate clock are stopped. since most registers are clocked using these clocks, the power consumption is greatly reduced. normal operation is resumed when: rxd input receives the dat a start bit transition. data byte is loaded to the tx fifo or thr. cts#, dsr#, dcd#, and ri# inputs are changed. 80h rtr isr[6] ttr character #1 rx fifo rcr tcr txrdy#, txrdy[3:0]# 80h 0 txrdy#, txrdy[3:0]# character #1 character #2 character #2 tx fifo rxrdy#, rxrdy[3:0]# character #127 00h character #1 rxrdy#, rxrdy[3:0]# tx fifo full empty space 80h 0 ttr isr[7] isr[6] 0 tcr character #127 character #256 80h 00h character #128 empty space 0 isr[7] rcr character #2 80h rx fifo empty character #255 80h character #127 character #128 character #128 rtr rev. 00
IN16C1054 6.7 programmable baud rate generator the sb16c1054 has a programmable baud rate generator with a prescaler. the prescaler is controlled by mcr[7], as shown in figure 7. the mcr[7] sets the prescaler to divide the clock frequency by 1 or 4. and the baud rate generator further divides this clock frequency by a programmable divisor (dll and dlm) between 1 and (2 16 ? 1) to obtain a 16x sampling rate clock of the serial data rate. the sampling rate clock is used by transmitter for data bit shifting and receiver for data sampling. the divisor of the baud rate generator is: xtal1 crystal input frequency ( prescaler ) divisor = (desired baud rate x 16) mcr[7] is cleared to ?0? (prescaler = 1), w hen clksel input is in low state after reset. mcr[7] is set to ?1? (prescaler = 4), when clksel input is in high state after reset. figure 7: prescaler and baud rate generator block diagram dll and dlm must be written to in order to program the baud rate. dll and dlm are the least and most significant byte of the baud ra te divisor, respectively. if dll and dlm are both zero, the sb16c1054 is effectively di sabled, as no baud clock will be generated. table 5 shows the baud rate and divisor value for prescaler with divide by 1 as well as crystal with frequency 1.8432mhz, 3.6864mhz, 7.3728mhz, and 14.7456mhz, respectively. figure 8 shows the crystal clock circuit reference. table 5: baud rates progammable clock oscillator logic logic divisor (divide by 4) mcr[7] = 0 baud rate xtal2 reference logic internal (divide by 1) logic internal baud rate clock for transmitte r and receiver prescaler xtal1 mcr[7] = 1 prescaler generator rev. 00
IN16C1054 desired baud rate 16x digit divisor for prescaler with divide by 1 1.8432mhz 3.6864mhz 7.3728mhz 14.7456mhz 50 0900h 1200h 2400h 4800h 75 0600h 0c00h 1800h 3000h 150 0300h 0600h 0c00h 1800h 300 0180h 0300h 0600h 0c00h 600 00c0h 0180h 0300h 0600h 1200 0060h 00c0h 0180h 0300h 1800 0040h 0080h 0100h 0200h 2000 003ah 0074h 00e8h 01d0h 2400 0030h 0060h 00c0h 0180h 3600 0020h 0040h 0080h 0100h 4800 0018h 0030h 0060h 00c0h 7200 0010h 0020h 0040h 0080h 9600 000ch 0018h 0030h 0060h 19.2k 0006h 000ch 0018h 0030h 38.4k 0003h 0006h 000ch 0018h 57.6k 0002h 0004h 0008h 0010h 115.2k 0001h 0002h 0004h 0008h 230.4k D 0001h 0002h 0004h 460.8k D D 0001h 0002h 921.6k D D D 0001h figure 8: prescaler and baud rate generator block diagram table 6: component values frequency range (mhz) c1 (pf) c2 (pf) r1 ( ? ) r2( ? ) 1.8~8 22 68 220k 470 ~ 1.5k 8~16 33~68 33 ~ 68 220k ~ 2.2m 470 ~ 1.5k output sb16c1054 clock xta l 1 clock c2 optional xta l 2 sb16c1054 r2 crystal c1 r1 external xta l 1 xta l 2 6.8 break and time-out conditions rev. 00
IN16C1054 break condition: break condition is occurred when txd signal outputs ?0? and sustains for more than one character. it is occurred if lcr[6] is set to ?1? and del eted if ?0?. if break condition is occurred when normal data are transmitted on txd, break signal is transmitted and internal serial data are also transmitted, but they are not out putted to external txd pin. when break condition is deleted, then they are transmitted to txd pin. figure 9 below shows the break condition block diagram. time-out condition: when serial data is received from external uart, characters are stored in rx fifo. when the number of characters in rx fifo reaches the trigger level, interrupt is generated for the cpu to treat characters in rx fifo. but when the number of characters in rx fifo does not reach the trigger le vel and no more data arrives from external device, interrupt is not generated and therefore cpu c annot recognize it. sb16c1054 offers time-out function for this situati on. time-out function generates an interrupt and reports to cpu when the number of rx fifo is less than trigger level and no more data receives for four character time. time-out interrupt is enabled when ier[2] is set to ?1? and can be verified by isr. figure 9: break condition block diagram m character #1 r mcr[6] = 0 mcr[6] = 1 s r r mcr[6] = 1 transmitter shift register(tsr) r s tx fifo txd pin s mcr[6] = 0 character #2 tsr out put r mcr[6] = 0 brake condition output s l l s s m m r l 16x clock rev. 00
IN16C1054 rev. 00 7. register descriptions each uart channel in the sb16c1054 has its own set of registers selected by address lines a2, a1, and a0 with a specific channel selected. the complete register set is shown on table 7 and table 8. table 7: internal registers map page 0 page 1 page 2 page 3 page 4 address a[2:0] lcr[7] = 0 mcr[6] = 0 lcr[7] = 1 lcr[7:0] bfh lcr[7] = 0 mcr[6] = 1 lcr = bfh psr[0] = 0 lcr = bfh psr[0] = 1 0h thr/rbr dll ? psr psr 1h ier dlm gicr atr afr 2h fcr/isr gisr efr xrcr 3h lcr 4h mcr xon1 ttr 5h lsr tcr xon2 rtr 6h msr rcr xoff1 fur 7h spr fsr xoff2 flr
IN16C1054 rev. 00 table 7: internal registers map? continued address a[2:0] register read/write comments page 0 registers 0h thr : transmit holding register rbr : receive buffer register write-only read-only lcr[7] = 0, mcr[6] = 0 1h ier : interrupt enable register r ead/write lcr[7] = 0, mcr[6] = 0 2h fcr : fifo control register isr : interrupt status register write-only read-only lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh 3h lcr : line control register read/write ? 4h mcr : modem control register read/ write lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh, lcr[7] = 0, mcr[6] = 1 5h lsr : line status register read- only lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh 6h msr : modem status register r ead-only lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh 7h spr : scratch pad register read/ write lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh page 1 registers 0h dll : divisor latch lsb read/write lcr[7] = 1, lcr bfh 1h dlm : divisor latch msb read/write lcr[7] = 1, lcr bfh 2h fcr : fifo control register isr : interrupt status register write-only read-only lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh 3h lcr : line control register read/write ? 4h mcr : modem control register read/ write lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh, lcr[7] = 0, mcr[6] = 1 5h lsr : line status register read- only lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh 6h msr : modem status register r ead-only lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh 7h spr : scratch pad register read/ write lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh
IN16C1054 rev. 00 table 7: internal registers map? continued address a[2:0] register read/write comments page 2 registers 0h none ? ? 1h gicr : global interrupt control register write-only lcr[7] = 0, mcr[6] = 1 2h gisr : global interrupt status regist er read-only lcr[7] = 0, mcr[6] = 1 3h lcr : line control register read/write ? 4h mcr : modem control register read/ write lcr[7] = 0, mcr[6] = 0, lcr[7] = 1, lcr bfh, lcr[7] = 0, mcr[6] = 1 5h tcr : transmit fifo count register read-only lcr[7] = 0, mcr[6] = 1 6h rcr : receive fifo count register read-only lcr[7] = 0, mcr[6] = 1 7h fsr : flow control status register read-only lcr[7] = 0, mcr[6] = 1 page 3 registers 0h psr : page select register r ead/write lcr = bfh, psr[0] = 0, lcr = bfh, psr[0] = 1 1h atr : auto toggle control register read/write lcr = bfh, psr[0] = 0 2h efr : enhanced feature register read/write lcr = bfh, psr[0] = 0 3h lcr : line control register read/write ? 4h xon1 : xon1 character register read/write lcr = bfh, psr[0] = 0 5h xon2 : xon2 character register read/write lcr = bfh, psr[0] = 0 6h xoff1 : xoff1 character register read/write lcr = bfh, psr[0] = 0 7h xoff2 : xoff2 character register read/write lcr = bfh, psr[0] = 0 page 4 registers 0h psr : page select register read/write lcr = bfh, psr[0] = 0, lcr = bfh, psr[0] = 1 1h afr : additional feature register read/write lcr = bfh, psr[0] = 1 2h xrcr : xoff re-transmit count regist er read/write lcr = bfh, psr[0] = 1 3h lcr : line control register read/write ? 4h ttr : transmit fifo trigger level register read/write lcr = bfh, psr[0] = 1 5h rtr : receive fifo trigger level register read/write lcr = bfh, psr[0] = 1 6h fur : flow control upper threshold r egister read/write lcr = bfh, psr[0] = 1 7h flr : flow control lower threshold r egister read/write lcr = bfh, psr[0] = 1
IN16C1054 rev. 00 table 8: internal registers description addr. a[2:0] reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0 registers 0h thr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0h rbr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1h ier 0/cts# interrupt enable 0/rts# interrupt enable 0/xoff interrupt enable 0/sleep mode enable modem status interrupt enable receive line status interrupt enable thr empty interrupt enable receive data available interrupt enable 2h isr fcr[0]/ 256-tx fifo empty fcr[0]/ 256-rx fifo full interrupt priority bit 5 interrupt priority bit 4 interrupt priority bit 3 interrupt priority bit 2 interrupt priority bit 1 interrupt priority bit 0 2h fcr rx trigger level (msb) rx trigger level (lsb) 0/tx trigger level (msb) 0/tx trigger level (lsb) dma mode select tx fifo reset rx fifo reset fifo enable 3h lcr divisor enable set tx brake set parity parity type select parity enable stop bits word length bit 1 word length bit 0 4h mcr clock select page 2 select/xoff re-transmit access enable 0/xon any 0/loop back out2/ intx enable out1/ xoff re- transmit enable rts# dtr# 5h lsr rx fifo data error thr & tsr empty thr empty receive break framing error parity error overrun error receive data ready 6h msr dcd# ri# dsr# cts# ? dcd# ? ri# ? dsr# ? cts# 7h scr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 1 registers 0h dll bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1h dlm bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 page 2 registers 1h gicr 0 0 0 0 0 0 0 global interrupt mask 2h gisr global interrupt mask status 0 0 0 ch 3 interrupt status ch 2 interrupt status ch 1 interrupt status ch 0 interrupt status 5h tcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6h rcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7h fsr 0 0 tx hw flow control status tx sw flow control status 0 0 rx hw flow control status rx sw flow control status table 8: internal registers description? continued
IN16C1054 rev. 00 addr. a[2:0] reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 3 registers 0h psr 1 0 1 0 0 1 0 page select 1h atr rxen polarity select rxen enable txen polarity select txen enable 0 0 auto toggle mode bit 1 auto toggle mode bit 0 2h efr auto-cts# enable auto-rts# enable special character detect enable enhanced feature enable software flow control bit 3 software flow control bit 2 software flow control bit 1 software flow control bit 0 4h xon1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5h xon2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6h xoff1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7h xoff2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 4 registers 1h afr 0 0 global interrupt polarity select global interrupt enable 0 0 0 256-fifo enable 2h xrcr 0 0 0 0 0 0 bit 1 bit 0 4h ttr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5h rtr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6h fur bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7h flr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7.1 transmit holding register (thr, page 0) the transmitter section consists of the tr ansmit holding register (thr) and transmit shift register (tsr). the thr is actually a 64-byte fifo or a 256-byte fifo. the thr receives data and shifts it into the tsr, where it is converted to serial dat a and moved out on the tx terminal. if the fifo is disabled, location zero of the fifo is used to store the byte. characters are lost if overflow occurs. 7.2 receive buffer register (rbr, page 0) the receiver section consists of the re ceive buffer register (rbr) and receive shift register (rsr). the rbr is actually a 64-byte fifo or a 256-byte fifo. the rsr receives serial data from exte rnal terminal. the serial data is converted to parallel data and is transferred to the rbr. this receiver secti on is controlled by the line control register. if the fifo is disabled, location zero of the fifo is used to store the characters. if overflow occurs, characters are lost. the rbr also stores the error status bits associated with each character. 7.3 interrupt enable register (ier, page 0) ier enables each of the seven types of interrupt, namely receive data ready, transmit
IN16C1054 rev. 00 empty, line status, modem status, xoff received, rts# state transition from low to high, and cts# state transition from low to high. all interrupts are disabled if bit[7:0] are cleared. interrupt is enabled by setting appropriate bits. table 9 shows ier bit settings. table 9: interrupt enable register description bit symbol description 7 ier[7] cts# interrupt enable (requires efr[4] = 1). 0 : disable the cts# interrupt (default). 1 : enable the cts# interrupt. 6 ier[6] rts# interrupt enable (requires efr[4] = 1). 0 : disable the rts# interrupt (default). 1 : enable the rts# interrupt. 5 ier[5] xoff interrupt enable (requires efr[4] = 1). 0 : disable the xoff interrupt (default). 1 : enable the xoff interrupt. 4 ier[4] sleep mode enable (requires efr[4] = 1). 0 : disable sleep mode (default). 1 : enable sleep mode. 3 ier[3] modem status interrupt enable 0 : disable the modem status register interrupt (default). 1: enable the modem status register interrupt. 2 ier[2] receive line st atus interrupt enable 0 : disable the receive line status interrupt (default). 1: enable the receive line status interrupt. 1 ier[1] transmit holding register interrupt enable 0 : disable the thr interrupt (default). 1 : enable the thr interrupt. 0 ier[0] receive buffer register interrupt enable 0 : disable the rbr interrupt (default). 1 : enable the rbr interrupt. 7.4 interrupt status register (isr, page 0) the uart provides multiple levels of priori tized interrupts to minimize software work load. isr provides the source of interrupt in a prioritized manner.
IN16C1054 rev. 00 table 10 shows isr[7:0] bit settings. table 10: interrupt status register description bit symbol description 7 isr[7] fcr[0]/256 tx fifo empty. when 256-byte fifo mode is disabled (default). mirror the content of fcr[0]. when 256-byte fifo mode is enabled. 0 : 256-byte tx fifo is full. 1 : 256-byte tx fifo is not full. when tcr is ?00h?, there are two situations of tx fifo full and tx fifo empty. if 256 tx empty bit is ?1?, it means tx fifo is empty and if ?0?, it means 256 bytes character is fully stored in tx fifo. 6 isr[6] fcr[0]/256 rx fifo full. when 256-byte fifo mode is disabled (default). mirror the content of fcr[0]. when 256-byte fifo mode is enabled. 0 : 256-byte rx fifo is not full. 1 : 256-byte rx fifo is full. when rcr is ?00h?, there are two situations of rx fifo full and rx fifo empty. if 256 rx empty bit is ?1?, it means 256 bytes character is fully stored in rx fifo and if ?0?, it means rx fifo is empty. table 10: interrupt status register description? continued bit interrupt priority li st and reset functions 5:0 priority interrupt type interrupt source interrupt reset control 00 _ 0001 D none none D 00 _ 0110 1 receiver line status oe, pe, fe, bi reading the lsr. 00 _ 1100 2 receive data available receiver data available, reaches trigger level. reading the rbr or fifo falls below trigger level. 00 _ 0100 2 character timeout indi- cation at least one data is in rx fifo and there are no more data in fifo during four character time. reading the rbr. 00 _ 0010 3 transmit holding register empty when thr is empty or tx fifo passes above trigger level (fifo enable). reading the isr or write data on thr. 00 _ 0000 4 modem status cts#, dsr# , dcd#, ri# reading the msr. 01 _ 0000 5 receive xoff or special character detection of a xoff or special character. reading the isr. 10 _ 0000 6 rts#, cts# status during auto rts/cts flow control rts# pin or cts# pin change state from ?0? to ?1?. reading the isr. 7.5 fifo control register (fcr, page 0) fcr is used for enabling the fifos, cleari ng the fifos, setting transmit/receive fifo trigger level, and selecting the dma modes. table 11 shows fcr bit settings.
IN16C1054 rev. 00 table 11: fifo control register description bit symbol description 7:6 fcr[7:6] rx fifo trigger level select 00 : 8 characters (default) 01 : 16 characters 10 : 56 characters 11 : 60 characters 5:4 fcr[5:4] tx fifo trigger level select 00 : 8 characters (default) 01 : 16 characters 10 : 32 characters 11 : 56 characters fcr[5:4] can only be modified and enabled when efr[4] is set. 3 fcr[3] dma mode select 0 : set dma mode 0 (default) 1 : set dma mode 1 2 fcr[2] tx fifo reset 0 : no tx fifo reset (default) 1 : reset tx fifo pointers and tx fifo level counter logic. this bit will return to ?0? after resetting fifo. 1 fcr[1] rx fifo reset 0 : no rx fifo reset (default) 1 : reset rx fifo pointers and rx fifo level counter logic. this bit will return to ?0? after resetting fifo. 0 fcr[0] fifo enable 0 : disable the tx and rx fifo (default). 1 : enable the tx and rx fifo
IN16C1054 rev. 00 7.6 line control register (lcr, page 0) lcr controls the asynchronous data communi cation format. the word length, the number of stop bits, and the parity type are selected by writing the appr opriate bits to the lcr. table 12 shows lcr bit settings. table 12: line control register description bit symbol description 7 lcr[7] divisor latch enable. 0 : disable the divisor latch (default). 1 : enable the divisor latch. 6 lcr[6] break enable. 0 : no tx break condition output (default). 1 : forces txd output to ?0?, for alerting the communication terminal to a line break condition. 5 lcr[5] set stick parity. lcr[5:3] = xx0 : no parity is selected. lcr[5:3] = 0x1 : stick par ity disabled. (default) lcr[5:3] = 101 : stick parity is forced to ?1?. lcr[5:3] = 111 : stick parity is forced to ?0?. 4 lcr[4] parity type select. lcr[5:3] =001 : o dd parity is selected. lcr[5:3] =011 : ev en parity is selected. 3 lcr[3] parity enabled. 0 : no parity (default). 1 : a parity bit is generated during the transmission and the receiver checks for receive parity. 2 lcr[2] number of stop bits. lcr[2:0] = 0xx : 1 stop bit (word length = 5, 6, 7, 8). lcr[2:0] = 100 : 1.5 st op bits (word length = 5). lcr[2:0] = 11x or 1x1 : 2 stop bits (word length = 6, 7. 8). 1:0 lcr[1:0] word length bits. 00 : 5 bits (default). 01 : 6 bits. 10 : 7 bits. 11 : 8 bits.
IN16C1054 rev. 00 7.7 modem control register (mcr, page 0) mcr controls the interface with the modem, data set, or peripheral device that is emulating the modem. table 13 shows mcr bit settings. table 13: modem control register description bit symbol description 7 mcr[7] clock prescaler select. 0 : divide by 1 clock input (default). 1 : divide by 4 clock input. 6 mcr[6] page 2 select/xoff re-transmit access enable 0 : enable access to page 0 register when lcr[7] is ?0? (default). 1 : enable access to page 2 register and xoff re-transmit bit when lcr[7] is ?0?. 5 mcr[5] xon any enable. 0 : disable xon any (default). 1 : enable xon any. 4 mcr[4] internal loop back enable. 0 : disable loop back mode (default). 1 : enable internal loop back m ode. in this mode the mcr[3:0] signals are looped back into msr[7:4] and txd output is looped back to rxd input internally. 3 mcr[3] out2/interrupt output enable. 0 : intx outputs disabled (default). during loop back mode, out2 output ?0? and it controls msr[7] to ?1?. 1 : intx outputs enabled. during loop back mode, out2 output ?1? and it controls msr[7] to ?0?. out2 is not available as an output pin on the sb16c1054. 2 mcr[2] out1/xoff re-transmit enable. 0 : xoff re-transmit disable when mcr[6] is ?0?. during loop back mode, out1 output to ?0 ? and it controls msr[6] to ?1?. 1 : xoff re-transmit enable when mcr[6] is ?1?. during loop back mode, out1 output to ?1? and it controls msr[6] to ?0?. out1 is not available as an output pin on the sb16c1054. xoff re-transmit is operated wi th xrcr, refer to xrcr. 1 mcr[1] rts# output. 0 : force rts# output to ?1?. during loop back mode, controls msr[4] to ?1?. 1 : force rts# output to ?0?. during loop back mode, controls msr[4] to ?0?. 0 mcr[0] dtr# output. 0 : force dtr# output to ?1?. during loop back mode, controls msr[5] to ?1?. 1 : force dtr# output to ?0?. during loop back mode, controls msr[5] to ?0?.
IN16C1054 rev. 00 7.8 line status register (lsr, page 0) lsr provides the status of data transfers between the ua rt and the cpu. when lsr is read, lsr[4:2] reflect the error bits (bi, fe, pe) of the character at the top of the rx fifo. the errors in a character are i dentified by reading ls r and then reading rbr. reading lsr does not cause an in crement of the rx fifo read pointer. the rx fifo read pointer is incremented by reading t he rbr. table 14 shows lsr bit settings. table 14: line status register description bit symbol description 7 lsr[7] rx fifo data error indicator. 0 : no rx fifo error (default). 1 : at least one parity error, framing error, or break indication is in the rx fifo. this bit is cleared when there is no more error in any of characters in the rx fifo. 6 lsr[6] thr and tsr empty indicator. 0 : thr or tsr is not empty. 1 : thr and tsr are empty. 5 lsr[5] thr empty indicator. 0 : thr is not empty. 1 : thr is empty. it indicates that the uart is ready to accept a new character for transmission. in addition, it uses the uart to gener- ate an interrupt to the cpu w hen the thr empty interrupt enable is set to ?1?. 4 lsr[4] break interrupt indicator. 0 : no break condition (default). 1 : the receiver received a break signal (rxd was ?0? for at least one character frame time). in fifo mode, only one character is loaded into the rx fifo. 3 lsr[3] framing error indicator. 0 : no framing error (default). 1 : framing error. it indicates that the received character did not have a valid stop bit. 2 lsr[2] parity error indicator. 0 : no parity error (default). 1 : parity error. it indicates that the receive character did not have the correct even or odd parity, as selected by the lcr[4] 1 lsr[1] overrun error indicator. 0 : no overrun error (default). 1 : overrun error. it indicates that the character in the rbr or rx fifo was not read by the cpu, t hereby ignored the receiving character. 0 lsr[0] receive data ready indicator. 0 : no character in the rbr or rx fifo. 1 : at least one character in the rbr or rx fifo.
IN16C1054 rev. 00 7.9 modem status register (msr, page 0) msr provides the current status of control signals from modem or auxiliary devices. msr[3:0] are set to ?1? when input from modem changes and cleared to ?0? as soon as cpu reads msr. table 15 shows msr bit settings. table 15: modem status register description bit symbol description 7 msr[7] dcd input status. complement of data ca rrier detect (dcd#) input. in loop back mode this bit is equivalent to out2 in the mcr. 6 msr[6] ri input status. complement of ring indicator (ri#) input. in loop back mode this bit is equivalent to out1 in the mcr. 5 msr[5] dsr input status. complement of data set ready (dsr#) input. in loop back mode this bit is equivalent to dtr in the mcr. 4 msr[4] cts input status. complement of clear to send (cts#) input. in loop back mode this bit is equivalent to rts in the mcr. 3 msr[3] ? dcd input status. 0 : no change on cd# input (default). 1 : indicates that the dcd# input has changed state. 2 msr[2] ? ri input status. 0 : no change on ri# input (default). 1 : indicates that the ri# input has changed state from ?0? to ?1?. 1 msr[1] ? dsr input status. 0 : no change on dsr# input (deault). 1 : indicates that the dsr# input has changed state. 0 msr[0] ? cts input status. 0 : no change on cts# input (deault). 1 : indicates that the cts# input has changed state. 7.10 scratch pad register (spr, page 0) this 8-bit read/write register does not cont rol the uart in anyway. it is intended as a scratch pad register to be used by t he programmer to hold data temporarily. 7.11 divisor latches (dll, dlh, page 1) two 8-bit registers which store the 16-bit divisor for generation of the clock in baud rate generator. dlh stores the most significant part of the diviso r, and dll stores the least significant part of the divisor. div isor of zero is not recommended. note that dll and dlh can only be written to before sleep mode is enabled, i.e., before ier[4] is set. chapter 6.7 describes the details of divisor latches.
IN16C1054 rev. 00 7.12 global interrupt control register (gicr, page 2) gicr is a register that internal four 16c1050 uarts share to use. it is used when determining whether each interrupt generated at four 16c1050 uarts are transmitted to global interrupts or not. table 16 shows the gicr bit settings. table 16: global interrupt control register description bit symbol description 7:1 gicr[7:1] not used, always ?000 _ 0000? 0 gicr[0] global interrupt mask. 0 : deasserted, irrespective of occurring interrupts of four 16c1050 uarts displayed on gisr[3:0]. ?1? is outputted if global interrupt polarity, afr[5] is ?0? and outputted ?0? if ?1?. 1 : generates interrupt when a ll the values of gisr[3:0] are not ?0?. if all the values of gisr[3:0] are ?0?, interrupt is not outputted on gint pin. ?1 ? is outputted if afr[5] is ?0? and ?0? is outputted if ?1?. 7.13 global interrupt status register (gisr, page 2) gisr is a register that internal four 16c1050 ua rts share to use. it is used to verify the generation status of each interrupt of four 16c1050 uarts w hen global interrupt function is enabled. table 17 shows gisr bit settings. table 17: global interrupt status register description bit symbol description 7 gisr[7] mirror the content of gicr[0]. 6:4 gisr[6:4] not used, always ?00?. 3 gisr[3] uart of cs3# interrupt status. 0 : uart of cs3# interrupt was not generated. 1 : uart of cs3# interrupt was generated. 2 gisr[2] uart of cs2# interrupt status. 0 : uart of cs2# interrupt was not generated. 1 : uart of cs2# interrupt was generated. 1 gisr[1] uart of cs1# interrupt status. 0 : uart of cs1# interrupt was not generated. 1 : uart of cs1# interrupt was generated. 0 gisr[0] uart of cs0# interrupt status. 0 : uart of cs0# interrupt was not generated. 1 : uart of cs0# interrupt was generated. 7.14 transmit fifo count register (tcr, page 2)
IN16C1054 rev. 00 tcr shows the number of characters that c an be stored in tx fifo. in 64-byte fifo mode, it consists of only tcr[6:0]. if the num ber of characters that can be stored in tx fifo is 0, it is shown as ?0000_0000? and if 64, it is shown as ?0100_0000?. in 256-byte fifo mode, it consists of isr[7] + tcr[7: 0]. if the number of characters that can be stored in tx fifo is 0, it is show n as ?0_0000_0000? and if 255, it is shown as ?0_1111_1111?. and in case of the maximum number 256, it is shown as ?1_0000_0000?. 7.15 receive fifo count register (rcr, page 2) rcr shows the number of characters that is st ored in rx fifo. in 64-byte fifo mode, it consists of only rcr[6:0]. if the number of characte rs that is stored in rx fifo is 0, it is shown as ?0000_0000? and if 64, it is shown as ?0100_0000?. in 256-byte fifo mode, it consists of isr[6] + rcr[7:0]. if the number of characters that is stored in rx fifo is 0, it is shown as ?0_0000_0000? and if 255, it is shown as ?0_1111_1111?. and in case of the maximum number 256, it is shown as ?1_0000_0000?. 7.16 flow control status register (fsr, page 2) fsr show the status of operat ion of tx hardware flow control, rx hardware flow control, tx software flow control, and rx software flow control. table 18: flow control status register description bit symbol description 7:6 fsr[7:6] not used, always ?00?. 5 fsr[5] tx hardware flow control status. 0 : when fifo or auto-rts flow control is disabled. if fifo and auto-rts flow control is enabled, it means the number of data received in rx fifo at the first time is less than the value of fur, or it means the number of data in rx fifo was more than the value of fur and after the cpu read them, the number of data that remains unread is less than or equal to the value of flr. that is, uart reports external device that it can receive more characters. 1 : it shows that the number of data received in rx fifo exceeds the value of fur and uart reports external device that it cannot receive more data. if rx fifo has space to store more data, new data are stored in rx fifo but after it gets full, they are lost. for more details, refer to ?6 .2 hardware flow control?. 4 fsr[4] tx software flow control status. 0 : when fifo or software flow control is disabled. if fifo and software flow control is enabled, it means the number of data received in rx fifo at the first time is less than the value of fur, or it means the number of data in rx fifo was more than the value of fur and after the cpu read them, the number of data that remains unread after the cpu read the data received in rx fifo is less than or equal to the value of flr. that
IN16C1054 rev. 00 is, uart transmits xon character to report external device that it can receive more data. 1 : it shows that the number of data received in rx fifo exceeds the value of fur and transmitting xoff character to report external device that it cannot receive more data. if rx fifo has space to st ore more data, new data are stored in rx fifo but after it gets full, they are lost. for more details, refer to ?6 .3 software flow control?. 3:2 fsr[3:2] not used, always ?00?. 1 fsr[1] rx hardware flow control status. 0 : when fifo or auto-cts flow control is disabled. if fifo and auto-cts flow control is enabled, ?0? is inputted in cts# pin and it means external device can receive more data. this time data in tx fifo are transmitted. 1 : if fifo and auto-cts flow control is enabled, ?1? is inputted in cts# pin and it means exte rnal device can not receive more data. this time data in tx fifo are not transmitted. for more details, refer to ?6 .2 hardware flow control?. 0 fsr[0] rx software flow control status. 0 : when fifo or rx software flow control is disabled. if fifo and rx software flow control is enabled, it means xoff character has never arrived or xon character arrived after xoff character had arrived(it means external device can receive more data). this time data in tx fifo are transmitted. 1 : if fifo and rx software flow control is enabled, it means xoff character has arrived and external device can not receive data any more. this time characters in tx fifo are not transmitted. for more details, refer to ?6 .3 software flow control?. 7.17 page select register (psr, page 3) if bfh is written in lcr, registers in page3 and page4 can be accessed. psr is used to determine which page to use. table 19 shows psr bit settings.
IN16C1054 rev. 00 table 19: page select register description bit symbol description 7:1 psr[7:1] access key. when writing data on psr to change page, access key must be correspondent. if the value of psr[7:1] is ?1010_010?, data is written on psr[0] and page can be sele cted. if psr[7:1] is read, it reads ?0000_000? which is irrespective of access key. 0 psr[0] page select. 0 : page 3 is selected (default). 1 : page 4 is selected. 7.18 auto toggle control register (atr, page 3) atr controls the signals for controlling input/output signals when using line interface as rs422 or rs485, so eliminates additional gl ue logic outside. table 20 shows atr bit settings.
IN16C1054 rev. 00 table 20: auto toggle control register description bit symbol description 7 atr[7] rxen polarity select. 0 : asserted output of rxen is ?0?. (default) 1 : asserted output of rxen is ?1?. 6 atr[6] rxen control mode select. 0 : rxen is outputted as same as atr[7], irrespective of txd signal. (default) 1 : rxen is outputted after maki ng complement of atr[7] when txd signal is transmitting. and outputted as same as atr[7] when txd is not transmitting. 5 atr[5] txen polarity select. 0 : asserted output of txen is ?0?. (default) 1 : asserted output of txen is ?1?. 4 atr[4] txen control mode select. only when atr[1:0] is ?11?; 0 : txen is outputted as same as atr[5], irrespective of txd signal. (default) 1 : rxen is outputted after maki ng complement of atr[5] when txd signal is transmitting, and outputted after making complement of atr[7] when txd is not transmitting.. 3:2 atr[3:2] not used, always ?00?. 1:0 atr[1:0] auto toggle enable. 00 : auto toggle is disabled (default). rts#/txen, dtr#txen pin operate as rts#, dtr#. if 80- pin, each of txrdy/txen, rxrdy/rxen operates as txrdy, rxrdy. 01 : rts#/txen pin operates as txen. dtr#/txen pin operates as dtr#. if 80-pin, each of txrdy/txen, rxrdy/rxen operates as txrdy, rxrdy. 10 : dtr#/txen pin operates as txen. rts#/txen operates as rts#. if 80-pin, each of txrdy/txen, rxrdy/rxen operates as txrdy, rxrdy. 11 : only in 80-pin. txrdy/txe n, rxrdy/rxen pin operates as txen, rxen. rts#/txen, dtr#/txen operates as rts#, dtr#. 7.19 enhanced feature register (efr, page 3) efr enables or disables t he enhanced features of the ua rt. table 21 shows efr bit settings. table 21: enhanced feature register description
IN16C1054 rev. 00 bit symbol description 7 efr[7] auto-cts flow control enable. 0 : auto-cts flow control is disabled (default). 1 : auto-cts flow control is enabled. transmission stops when cts# pin is inputted ?1?. transmission resumes when cts# pin is inputted ?0?. 6 efr[6] auto-rts flow control enable. 0 : auto-rts flow control is disabled (default). 1 : auto-rts flow control is enabled. the rts# pin outputs ?1? when data in rx fifo fill above the fur. rts# pin outputs ?0? when data in rx fifo fall below the flr. 5 efr[5] special character detect. 0 : special character detect disabled (default). 1 : special character detect enabl ed. the uart compares each incoming character with data in xoff2 register. if a match occurs, the received data is transferred to rx fifo and isr[4] is set to ?1? to indicate that a special character has been detected. 4 efr[4] enhanced function bits enable. 0 : disables enhanced functions and writing to ier[7:4], fcr[5:4], mcr[7:5]. 1 : enables enhanced function ie r[7:4], fcr[5:4], and mcr[7:5] can be modified, i.e., this bit is therefore a write enable. 3:0 efr[3:0] software flow control select. single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. see table 3 ?software flow control options (efr[3:0])? on page 11. 7.23 additional feature register (afr, page 4) afr enables or disables the 256-byte fifo mode and controls the global interrupt. table 22 shows afr bit settings. table 22: additional feature register description
IN16C1054 rev. 00 bit symbol description 7:6 afr[7:6] not used, always ?00?. 5 afr[5] global interrupt polarity select 0 : gint pin outputs ?0? when interrupt is generated (default). 1 : gint pin outputs ?1? when interrupt is generated. 4 afr[4] global interrupt enable 0 : int0/gint pin is selected to int0 (default). 1 : int0/gint pin is selected to gint. 3:1 afr[3:1] not used, always ?000?. 0 afr[0] 256-byte fifo enable. 0 : 256-byte fifo mode is disabled and this means sb16c1054 operates as non fifo mode or 64-byte fifo mode (default). 1 : 256-byte fifo mode is enabl ed and isr[7:6] operates as 256-tx fifo empty and 256-rx fifo full. 7.24 xoff re-transmit count register (xrcr, page 4) xrcr operates only when software flow cont rol is enabled by efr[3:0] and xoff re- transmit function of mcr[2] is also enabled. and it determi nes the period of retransmission of xoff character. table 23 shows xrcr bit settings. table 23: xoff re-transmit count register description bit symbol description 7:2 xrcr[7:2] not used, always ?0000_00?. 1:0 xrcr[1:0] xoff re-tr ansmit count select 00 : transmits xoff character whenever the number of received data is 1 during xoff status. (default) 01 : transmits xoff character whenever the number of received data is 4 during xoff status. 10 : transmits xoff character whenever the number of received data is 8 during xoff status. 11 : transmits xoff character whenever the number of received data is 16 during xoff status. 7.25 transmit fifo trigger level register (ttr, page 4) operates only when 256-byte fifo mode is enabl ed. it sets the trigger level of 256-byte tx fifo for generating transmit interrupt. in terrupt is generated w hen the number of data remained in tx fifo after transmitting through txd pin is less than the value of ttr. initial value is 128h, ?1000_0000? and ?0000_0000? must not be written. if written, unexpected operation may occur.
IN16C1054 rev. 00 7.26 receive fifo trigger level register (rtr, page 4) operates only when 256-byte fifo mode is enabl ed. it sets the trigger level of 256-byte rx fifo for generating receive interrupt. interrupt is generated w hen the number of data remained in rx fifo exceeds the value of rtr( this time, timeout or interrupt is valid). initial value is 128h, ?1000_0000? and ?0000_0000? must not be written. if written, unexpected operation may occur. 7.27 flow control upper threshold register (fur, page 4) it can be written only when 256-byte fifo mode is enabled and one of tx software flow control or auto-rts is enabled (in 64-byte mode, it cannot be wr itten but can be read only, and follows the value of trigger level set in fcr[5:4]). while tx software flow control is enabled, xoff character is transmitted when the number of data in rx fifo exceeds the value of fur. if auto-rts is enabled, ?1? is outputted on rts# pin to report that it cannot receive data any more. if both tx softw are flow control and auto-rts is enabled, xoff character is transmitted and ?1? is outputt ed on rts# pin. the value of fur must be larger than that of flr. 7.28 flow control lower threshold register (flr, page 4) it can be written only when 256-byte fifo mode is enabled and one of tx software flow control, or auto-rts is enabled (in 64-byte mode, it cannot be wr itten but can be read only, and follows the value of trigger level set in fcr[7:6]). while tx software flow control is enabled, xon character is transmitted when the number of data in rx fifo is less than the value of fur only if xoff character is tr ansmitted before. if auto-rts is enabled, ?0? is outputted on rts# pin to report that it can receive more data. if both tx software flow control and auto-rts is enabled, xon characte r is transmitted only if xoff character is transmitted before and ?0? is out putted on rts# pin. the value of flr must be less than that of fur. table 24: sb16c1054 reset conditions registers reset state page 0 rbr [7:0] = ?xxxx_xxxx? ier [7:0] = ?0000_0000? fcr [7:0] = ?0000_0000? isr [7:0] = ?0000_0001?
IN16C1054 rev. 00 lcr [7:0] = ?0000_0000? mcr [7:0] = ?0000_0000? lsr [7:0] = ?0110_0000? msr [7:4] = ?0000? [3:0] = logic levels of the inputs inverted spr [7:0] = ?0000_0000? page 1 dll [7:0] = ?1111_1111? dlm [7:0] = ?1111_1111? page 2 gicr [7:0] = ?0000_0000? gisr [7:0] = ?0000_0000? tcr [7:0] = ?0000_0000? rcr [7:0] = ?0000_0000? fsr [7:0] = ?0000_0000? page 3 psr [7:0] = ?0000_0000? atr [7:0] = ?0000_0000? efr [7:0] = ?0000_0000? xon1 [7:0] = ?0000_0000? xon2 [7:0] = ?0000_0000? xoff1 [7:0] = ?0000_0000? xoff2 [7:0] = ?0000_0000? page 4 afr [7:0] = ?0000_0000? xrcr [7:0] = ?0000_0000? ttr [7:0] = ?1000_0000? rtr [7:0] = ?1000_0000? fur [7:0] = ?0000_0000? flr [7:0] = ?0000_0000? output signals reset state txd, rts#, dtr# logic 1 txrdy# logic 0 rxrdy# logic 1 int tri-state condition = intsel is open or low state logic 0 = intsel is high state 8. programmer?s guide the base set of registers that is used during high-speed data transfer has a straightforward access method. the extended function registers require special access bits to be decoded along with the address lines. the following guide will help with programming these registers. no te that the descriptions below are for individual register access. some streamlining through interl eaving can be obtained when programming all the registers.
IN16C1054 rev. 00 table 25: register programming guide command action set baud rate to value1, value 2 read lcr, save in temp set lcr to 80h set dll to value1 set dlm to value2 set lcr to temp set xon1, xoff1 to value1, value 2 read lcr, save in temp set lcr to bfh set xon1 to value1 set xoff1 to value2 set lcr to temp set xon2, xoff2 to value1, val ue2 read lcr, save in temp set lcr to bfh set xon2 to value1 set xoff2 to value2 set lcr to temp set software flow control mode to value read lcr, save in temp set lcr to bfh set efr to value set lcr to temp set flow control threshold for 64-byte fifo mode 1) set fcr to ?0000_xxx1? ? set fur to 8, set flr to 0 2) set fcr to ?0101_xxx1? ? set fur to 16, set flr to 8 3) set fcr to ?1010_xxx1? ? set fur to 56, set flr to 16 4) set fcr to ?1111_xxx1? ? set fur to 60, set flr to 56 set flow control threshold for 256-byte fifo mode set fcr to ?xxxx_xxx1? read lcr, save in temp set lcr to bfh set psr to a5h set afr to 01h table 25: register programming guide? continued command action set fur to upper threshold value set flr to lower threshold value set psr to a4h set lcr to temp set tx fifo / rx fifo interrupt trigger level for 64-byte fifo mode 1) set fcr to ?0000_xxx1? ? set rtr to 8, set ttr to 8 2) set fcr to ?0101_xxx1?
IN16C1054 rev. 00 ? set rtr to 16, set ttr to 16 3) set fcr to ?1010_xxx1? ? set rtr to 56, set ttr to 32 4) set fcr to ?1111_xxx1? ? set rtr to 60, set ttr to 56 set tx fifo / rx fifo interrupt trigger level for 256-byte fifo mode set fcr to ?xxxx_xxx1? read lcr, save in temp set lcr to bfh set psr to a5h set afr to 01h set ttr to tx fifo trigger level value set rtr to rx fifo trigger level value set psr to a4h set lcr to temp read flow control status read lcr, save in temp1 read mcr, save in temp2 set lcr to (?0111_1111? and temp1) set mcr to (?0100_0000? or temp2) read fsr, save in temp3 pass temp3 back to host set mcr to temp2 set lcr to temp1 read tx fifo / rx fifo count value read lcr, save in temp1 read mcr, save in temp2 set lcr to (?0111_1111? and temp1) set mcr to (?0100_0000? or temp2) read tcr, save in temp3 read rcr, save in temp4 pass temp3 back to host pass temp4 back to host set mcr to temp2 set lcr to temp1 table 25: register programming guide? continued command action read 256-byte tx fifo empty status / rx fifo full status set fcr to ?xxxx_xxx1? read lcr, save in temp1 set lcr to bfh set psr to a5h set afr to 01h set psr to a4h set lcr to temp1 read isr, save in temp2
IN16C1054 rev. 00 pass temp2 back to host enable xoff re-transmit read lcr, save in temp1 set lcr to not bfh read mcr, save in temp2 set mcr to (?0100_0000? or temp2) set mcr to (?0100_0100? or temp2) set mcr to (?1011_1111? and temp2) set mcr to temp2 set lcr to temp1 disable xoff re-transmit read lcr, save in temp1 set lcr to not bfh read mcr, save in temp2 set mcr to (?0100_0000? or temp2) set mcr to (?1011_1011? and temp2) set mcr to temp2 set lcr to temp1 set prescaler value to divide-by-1 or 4 read lcr, save in temp1 set lcr to bfh read efr, save in temp2 set efr to (?0001_0000? or temp2) set lcr to 00h read mcr, save in temp3 if divide-by-1 = ok then set mcr to (?0111_1111? and temp3) else set mcr to (?1000_0000? or temp3) set lcr to bfh set efr to temp2 set lcr to temp1 9. electrical characteristics absolute maximum ratings symbol parameter conditions min max unit v cc supply voltage 3.6 v v i input voltage 0.5 5.5 v v o output voltage gnd + 0.1 v cc ? 0.1 v t amb operating ambient temperature in free-air 40 +85 t stg storage temperature 60 +150
IN16C1054 rev. 00 dc electrical characteristics symbol parameter conditions 3.3v unit min nom max v cc supply voltage 2.7 3.3 3.6 v v i input voltage 0 v cc v v ih high-level input voltage v cc 0.7 5.5 v v il low-level input voltage 0 v cc 0.3 v v o output voltage 0 v cc v v oh high-level output voltage ioh = 8ma 2.4 v v ol low-level output voltage iol = 8ma 0.4 v c i input capacitance 9 pf oscillator/clock speed 85 mhz clock duty cycle 50 % i cc supply current ma i ccsleep sleep current ma symbol parameter min max unit t rd pulse duration, ior# low 24 ns t csr set up time, csx# valid before ior# low ? 10 ns t ar set up time, a2~a0 valid before ior# low ? 10 ns t ra hold time, a2~a0 valid after ior# high ? 2 ns t rcs hold time, csx# valid after ior# high ? 0 ns t frc delay time, t ar +t rd +t rc ? 54 ns t rc delay time, ior# high to ior# or iow# low 20 ns t wr pulse duration, iow# 24 ns t csw setup time, csx# valid before iow# 10 ns t aw setup time, a2~a0 valid before iow# 10 ns
IN16C1054 rev. 00 t ds setup time, d7~d0 valid before iow# 15 ns t wa hold time, a2~a0 valid after iow# 2 ns t wcs hold time, csx# valid after iow# 2 ns t dh hold time, d7~d0 valid after iow# 5 ns t fwc delay time, t aw +t wr +t wc 54 ns t wc delay time, iow# to iow# or ior# 20 ns t rvd enable time, ior# to d7~d0 valid 24 ns t hz disable time, ior# to d7~d0 released 4 ns t irs delay time, intx to txdx at start 8 24 rclk t sti delay time, txdx at start to intx 8 8 rclk t si delay time, iow# high or low (wr thr) to intx 16 32 rclk t sxa delay time, txdx at start to txrdy# 8 rclk t hr propagation delay time, iow#(wr thr) to intx 12 ns t ir propagation delay time, ior#(rd iir) to intx 12 ns t wxi propagation delay time, iow#(wr thr) to txrdy# 10 ns t sint delay time, stop bit to intx or stop bit to rxrdy# or read rbr to set interrupt 1 rclk t rint propagation delay time, read rbr/lsr to intx /lsr interrupt 12 ns t rint propagation delay time, ior# rclk to rxrdy# 12 ns t mdo propagation delay time, iow#(wr mcr) to rtsx#, dtrx# 12 ns t sim propagation delay time, modem i nput ctsx#, dsrx#, and dcdx# to intx 12 ns t rim propagation delay time, ior#(rd msr) to interrupt 3 ns t sim propagation delay time, rix# to intx# 12 ns ? the internal address strobe is always in active state. ? in the fifo mode, td1= xxns (min) between reads of the fifo and the status register.
IN16C1054 t t ra t ior# t csx# t t t a[2:0] valid data hz valid address d[7:0] rvd rc iow# rd rcs ar t csr t active frc figure 10: read cycle timing fwc wr t dh active t t wa t t d[7:0] t wc t a[2:0] t valid data t valid address csx# aw wcs csw ds iow# ior# figure 11: write cycle timing rev. 00
IN16C1054 hr t irs t t sti si hr txdx t parity t intx ir iow# start ior# start (wr thr) (rd iir) stop(1-2) data(5-8) t figure 12: transmitter timing start stop (wr thr) iow# parity txdx data txrdy# sxa t wxi t by te #1 figure 13: transmitter ready mode 0 timing sxa t txdx txrdy# t stop iow# fifo full start parity wxi data by te #16 (wr thr) figure 14: transmitter ready mode 1 timing rev. 00
IN16C1054 (fifo at or above t (rd lsr) sint rint ior# (rd rbr) lsi interrupt (fcr6, 7 = 0, 0) data(5-8) start intx(trigger ior# level interrupt clock sample rint t rxdx t trigger level) stop (fifo below parity trigger level) figure 15: receiver fifo first byte (sets rbr) timing trigger level clock stop trigger level) sint (rd lsr) t sint t ior# rint (rd rbr) t rint trigger level) t rxdx (fifo at or above sample interrupt top byte of fifo (fifo below read from fifo lsi interrupt previous byte ior# timeout or figure 16: receiver fifo after first byte (after rbr set) timing rev. 00
IN16C1054 rxdx t rxrdy# rint (rd rbr) ior# clock sample sint t stop (first byte) figure 17: receiver ready mode 0 timing sample sint reaches the rxdx t trigger level) t ior# rint rxrdy# clock (first byte that stop (rd rbr) figure 18: receiver ready mode 1 timing sim rtsx#, dtrx# (wr mcr) t t rim t t sim rim t sim t iow# mdo (rd msr) mdo ior# t intx ctsx#, dsrx#, dcdx# rix# figure 19: modem control timing rev. 00
IN16C1054 10. package outline 80-pin tqfp: thin plastic quad flat package; body 12 12 1.0 mm 0,17 0,27 14,00 12,00 9,50 1,20 max 1,05 0,95 0,50 0,10 1.00 0 - 7 0,75 0,45 note : 1. all dimensions are in millimeters. 2. falls within ansi y14.5-1982 68-pin plcc: plastic leaded chip carrier rev. 00
IN16C1054 0.956 (24,282) 0.956 (24,282) 0.02 (0,51) min 0.18 (4,57) max 0.120 (3,05) 0.090 (2,29) 0.469 (11,913) 0.469 (11,913) 0.021 (0,53) 0.013 (0,33) 0.032 (0.081) 0.050 (1,27) 0.026 (0,66) 0.985 (25,019) 0.950 (24,130) 0.985 (25,019) 0.950 (24,130) 0.441 (11,201) 0.441 (11,201) 0.995 (25,273) 0.995 (25,273) note : 1. all dimensions are in inches (millimeters). 2. falls within ansi y14.5-1982 rev. 00

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