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1 high speed, dual channel, 6a, mosfet driver with programmable rising and falling edge delay timers isl89367 the isl89367 is a high-speed, 6a, 2 channel mosfet driver optimized for synchronous rectifier applications. internal timers can be programmed with resistor s to delay the rising and/or falling edges of the outputs. logi cally anded dual inputs are also provided. one input is for the pwm signal and the second can be used as an enable. a third control input is used to optionally invert the logical polarity of the driver outputs. comparator like logical inputs allows this driver to be configured for any logic level from 3.3v to 10 vdc. the precision logic thresholds provided by the comparators allow the use of external rc circuits to generate longer time delays than are possible with the internal timers. the comparator s also allow the driver to be configured with a low output voltage that is negative relative to the logic ground if desired. this is useful for applications that require a negative turn-off gate drive voltage for driving fets with logic thresholds. at high switching frequencies, these mosfet drivers use very little bias current. separate, non-overlapping drive circuits are used to drive each cmos output fet to prevent shoot-thru currents in the output stage. an under voltage lockout (uv) in sures that the driver outputs remain off (low) during turn-on until v dd is sufficiently high for correct logic control. this prevents unexpected behavior when vdd bias is being applied or removed. features ? 2 outputs with 6a peak drive currents (sink and source) with output voltage range of 4.5v to 16v. ?typical on-resistance ~1 . ? specified miller plateau drive currents. ? epad provides very low thermal impedance ( jc = 3c/w). ? dual logic inputs with hysteresis for high noise immunity. ? rising and/or falling output edge delays programmed with resistors. ? ~ 20ns rise and fall time driving a 10nf load. ? low operating bias currents applications ? synchronous rectifier (sr) driver ? switch mode power supplies ? motor drives, class d amplifiers, ups, inverters ? pulse transformer driver ? clock/line driver 3.3v enable inva invb pwm outb /outa vref+ vref- rdela rdelb fdelb fdela gnd 12v figure 1. typical application 0 50 100 150 200 250 300 350 0 5 10 15 20 rising or falling edge delay (ns) rdt (2k to 20k) figure 2. programmable time delays -40c (worst case) +25c (typical) +125c (worst case) january 31, 2011 fn7727.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl89367 2 fn7727.0 january 31, 2011 block diagram the positive threshold is 63% of ((vref+)-(vref-)). the negative threshold is 37% of ((vref+)-(vref-)). delay timer outx vdd in1x invx vref+ vss vref- rdelx fdelx in2x for clarity, only one channel is shown delay timer rising edge is delayed falling edge is delayed epad separated gate drives prevent shoot-thru currents in the output cmos fets. 10k for proper thermal and electrical performance, the epad must be connected to the pcb signal ground plane.
isl89367 3 fn7727.0 january 31, 2011 pin configurations isl89367 (16 ld tdfn, epsoic) top view epad inva in1a invb in2b in1b in2a fdelb rdelb vss outb outa vdd rdela fdela 1 2 3 4 5 6 7 8 12 9 10 11 13 14 15 16 vref+ vref- invx in1x in2x outx 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 outx in1x in2x invx truth table pin descriptions pin number symbol description 1, 8 vref+ vref- vref+ and vref- are the reference voltages for the in1a, in1b, in2a, an d in2b logic inputs. vref+ is normally connected to the positive bias voltage of the input logi c. vref- is normally connected to the ground reference of the input logic. 2, 7 inva or invb connect these pins to vdd to invert the corresponding output. connect to vss to not invert the corresponding output. 3, 4, 5, 6 in1a, in2a, in1b, in2b anded logical inputs. one input to each channel can be used as an enable . logic high threshold is 63% of [(vref+) - (vref-)]. logic low threshold is 37% of [(vref+) - (vref-)]. 9, 16 fdelb, fdela connect a resistor between these pins and vss to program the duration of the falling edge propagation delay of the corresponding output relative to the logic inputs. 10, 15 rdelb, rdela connect a resistor between these pins and vss to program the duration of the rising edge propagation delay of the corresponding output relative to the logic inputs. 11, 14 vss, vdd output bias voltage. (vdd to vss) range is 4.5v to 16v. vss may be negative relative to vref-. 12, 13 outb, outa 6a peak outputs. output voltage swing is between vdd and vss. epad must be connected to logic ground (vref-). ordering information part number (notes 1, 2, 3) part marking temp range (c) input configuration package (pb-free) pkg. dwg. # ISL89367FRTAZ 367a -40 to +125 non-inverting 16 ld 3x5 tdfn l16.5x3 notes: 1. add ?-t?, suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl89367. for more information on msl, please see technical brief tb363 .
isl89367 4 fn7727.0 january 31, 2011 absolute maximum rating s thermal information supply voltage, v dd relative to v ss . . . . . . . . . . . . . . . . . . . . -0.3v to 18v v ref+ relative to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v v ref- relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0v to v ss - 0.3v invx (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v ss - 0.3v to v dd + 0.3v innx (note 5) relative to v ref- . . . . . . . . . (v ref- ) - 0.3v to (v ref+ ) + 0.3v v ref+ relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 18v v ref+ relative to v ref- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 18v average output current (note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ma esd ratings human body model class 2 (tested per jesd22-a114e) . . . . . . . . 2000v machine model class b (tes ted per jesd22-a115-a) . . . . . . . . . . . . 200v charged device model class iv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000v latch-up (tested per jesd-78b; class 2, level a) output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500 ma thermal resistance (typical) ja (c/w) jc (c/w) 16 ld tdfn package (notes 6, 7) . . . . . . . 36 3 max power dissipation at +25c in free air . . . . . . . . . . . . . . . . . . . . . . 2.8w max power dissipation at +25c with copper plane . . . . . . . . . . . . . 33.3w storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temp range . . . . . . . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp maximum recommended operating conditions junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c supply voltage, v dd relative to v ss . . . . . . . . . . . . . . . . . . . . . . . 0v to 16v v ref- relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0v to v ss invx (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss or v dd innx (note 5) relative to v ref- . . . . . . . . . . . . . . . . . . . . . . . . v ref- to v ref+ v ref+ relative to v ss , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0v to 10v v ref+ relative to v ref- , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0v to 10v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. substitute inva or invb for invx. 5. substitute in1a, in2a, in1b, or in2b for innx 6. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 8. the average output current, when driving a power mosf et or similar capacitive load, is the average of the rectified output current (sinking and sourcing). the peak output currents of this driv er are self limiting by transconductance or r ds(on) and do not required any external components to minimize the peaks. if the output is driving a non-capacitive load, such as an led, maximum output current must be limited by e xternal means to less than the specified absolute average output current. dc electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, rdela = rdelb = fdela = fdelb = 0k unless otherwise specified. boldface limits apply over the operating junc tion temperature range, -40c to +125c. parameters symbol test conditions t j = +25c t j = -40c to +125c units min (note 9) typ max (note 9) min (note 9) max (note 9) power supply voltage range (v dd relative to v ss) v dd --- 4.5 16 v v dd quiescent current i dd inx = gnd - 5 - - - ma ina = inb = 1mhz, square wave - 25 - - ma v ref+ and v ref- bias v ref+ relative to v ss v p-s 3-10 3 10 v v ref- relative to v ss v n-s 0-4 0 4 v v ref+ relative to v ref- v p-n 3-10 3 10 v v ref+ quiescent current i pp v p-n = 12v - 200 - 100 300 a undervoltage vdd undervoltage lock-out (note 11) v uv innx = true (note 12) -3.3- - - v hysteresis - ~25 - - - mv
isl89367 5 fn7727.0 january 31, 2011 inputs input range for in1a, in2a, in1b, in2b v in v in is referenced to v ref- --- vref-vref+v input range for inva, invb v inv v inv is referenced to v ss --- v ss v dd v logic 0 threshold for in1a, in2a, in1b, in2b v il nominally 37% x ((v ref+ ) - (v ref- )) - 37 - 34 40 % logic 1 threshold for in1a, in2a, in1b, in2b v ih nominally 63% x ((v ref+ ) - (v ref- )) - 63 - 60 66 % logic 0 threshold for inva, invb v ilv v ilv is referenced to v ss -0.9- 1 1.2 v logic 1 threshold for inva, invb v ihv v ihv is referenced to v ss - 1.5 - 1.5 1.7 v input capacitance of in1a, in2a, in1b, 1n2b,inva, invb c in -2- - - pf input bias current for in1a, in2a, in1b, in2b i in v ref- < v in < v ref+ - - - -10 +10 a input bias current for inva, invb i inv v ss < v inv < v dd - - - -40 +40 a outputs high level output voltage v oha v ohb --- v dd - 0.1 v dd v low level output voltage v ola v olb --- gnd gnd + 0.1 v peak output source current i o v o (initial) = 0v, c load = 10nf - -6 - - - a peak output sink current i o v o (initial) =12v, c load = 10nf - +6 - - - a notes: 9. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 10. this parameter is taken from the simulation models for the inpu t fet. the actual capacitance on this input will be dominated by the pcb parasitic capacitance. 11. a 200s delay further inhibits the release of the output state when the uv positive going threshold is crossed. 12. the true state of a specific part numb er is defined by the input logic symbol. dc electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, rdela = rdelb = fdela = fdelb = 0k unless otherwise specified. boldface limits apply over the operating junc tion temperature range, -40c to +125c. (continued) parameters symbol test conditions t j = +25c t j = -40c to +125c units min (note 9) typ max (note 9) min (note 9) max (note 9) ac electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, rdela = rdelb = fdela = fdelb = 0k unless otherwise specified. boldface limits apply over the operating ju nction temperature range, -40c to +125c. parameters symbol test conditions /notes t j = +25c t j = -40c to +125c units min (note 9) typ max (note 9) min (note 9) max (note 9) output rise time (see figure 4) t r c load = 10 nf, 10% to 90% -20- - 40 ns output fall time (see figure 4) t f c load = 10 nf, 90% to 10% -20- - 40 ns output rising edge propagation delay (see figure 3) t rdlya, t rdlyb -25- - 50 ns
isl89367 6 fn7727.0 january 31, 2011 output falling edge propagation delay (see figure 3) t fdlya, t fdlyb -25- - 50 ns rising propagation matching (see figure 3) t rm - <1ns - - - ns falling propagation matching (see figure 3) t fm - <1ns - - - ns rising edge timer delay (note 13) t rtdly rdelx = 20k , no load - 270 - 237 297 ns rdelx = 2.0k , no load - 45 - 29 58 ns falling edge timer delay (note 13) t tdly fdelx = 20k , no load - 270 - 237 297 ns fdelx = 2.0k , no load - 45 - 29 58 ns miller plateau sink current (see test circuit figure 5) -i mp v dd = 10v, v miller = 5v -6---a -i mp v dd = 10v, v miller = 3v -4.7---a -i mp v dd = 10v, v miller = 2v -3.7---a miller plateau source current (see test circuit figure 6) i mp v dd = 10v, v miller = 5v -5.2---a i mp v dd = 10v, v miller = 3v -5.8---a i mp v dd = 10v, v miller = 2v -6.9---a note: 13. delays for timing resistors < 2.0k or > 20k are not specified and are not recommended. the resi stors tolerances (includi ng the boundary values of 2.0k and 20.0k ) are recommended to be 1% or better. ac electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, rdela = rdelb = fdela = fdelb = 0k unless otherwise specified. boldface limits apply over the operating ju nction temperature range, -40c to +125c. (continued) parameters symbol test conditions /notes t j = +25c t j = -40c to +125c units min (note 9) typ max (note 9) min (note 9) max (note 9)
isl89367 7 fn7727.0 january 31, 2011 test waveforms and circuits figure 3. prop delays and matching figure 4. rise/fall times figure 5. miller plateau sink current test circuit fig ure 6. miller plateau source current test circuit figure 7. miller plateau sink current fi gure 8. miller plateau source current innx outa outb 0v 3.3v t rdlya t rdlyb 63% 37% t fdlya t fdlyb t rm t fm 50% 50% 50% 50% outa or outb t r t f 90% 10% v miller 10v +i sense -i sense 10f 0.1f 0.1 200ns 10k isl8916x 10nf v miller 10v +i sense -i sense 10f 0.1f 0.1 200ns 10k isl8916x 10nf 200ns v miller -i mp v out current through 0.1 resistor 10v 0a 0v 200ns v miller i mp v out current through 0.1 resistor 0
isl89367 8 fn7727.0 january 31, 2011 typical performance curves figure 9. i dd vs v dd (static) figure 10. i dd vs v dd (1 mhz) figure 11. i dd vs frequency (+25c) figure 12. r ds(on) vs temperature figure 13. output rise/fall times figure 14. propagation delay vs v dd 2.0 2.5 3.0 3.5 4 8 12 16 static bias current (ma) v dd +125c +25c -40c 20 25 30 35 15 10 5 4 8 12 16 1mhz bias current (ma) v dd +125c +25c -40c 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 2.0 frequency (mhz) i dd (ma) no load 5v 10v 16v 12v 1.8 1.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -45 -20 5 30 55 80 105 130 r ds(on) (w) temperature (c) v out low v out high 15 20 25 -45 -20 5 30 55 80 105 130 rise/fall time (ns) temperature (c) fall time, c load = 10nf rise time, c load = 10nf 15 20 25 30 5 7 9 11 13 15 propagation delay (ns) v dd output falling prop delay output rising prop delay
isl89367 9 fn7727.0 january 31, 2011 functional description note: in the following discussion, when a lower case ?n? or ?x? is used in a pin name, the ?n? can be replaced by ?1? or ?2? and ?x? can be replaced by ?a? or ?b?. the isl89367 drivers are designed specifically for synchronous rectifier (sr) applications but can also be used for any mosfet driver application especially wh en a precision propagation time delay is required for the output rising for falling edge (or both). to prevent unexpected glitches on the output of the isl89367 during the application or removal of bias voltage, the undervoltage (uv) lock-out holds the outputs of the driver low when vdd < ~3.3 vdc regardless of the input logic level. the fast rising (or fa lling) output drive cu rrent of the isl89367 minimizes the turn-on (o r off) delay due to the input capacitance of the driven fet. the switching transition period at the miller plateau is also minimized by the high amplitude drive currents. (see the specified miller plateau currents in the ac electrical specifications on page 6). input logic voltage levels the input logic (innx) has threshol ds of 37% (falling input) and 63% (rising input). the maximum v ref+ relative to v ref- is 10vdc. for typical 5v logic applications v ref+ = 5v, v ref- = 0v. in a similar manner, applications with 3.3v logic v ref+ = 3.3v and v ref- = 0v. note that the invx inputs have ttl compatible thresholds, are v dd tolerant, and do not have precision thresholds. programmable delays the propagation time delays are programmed by resistors connected between rdelx or fdelx and vss. a resistor connected to rdelx delays the ri sing edge of outx. likewise, a resistor connected to fdelx delays the falling edge of outx. the resistors should be connected as close as possible to the pins to prevent noise coupling into thes e connections. in extremely noisy applications, it may be necessary to bypass the resistors with a 0.01f or smaller decoupling capacitor. the time delay varies linearly between ~40ns and ~265ns for values from 2k to 20k . if no time delay is required, short rdelx and fdelx to vss. programmed delays for resistor values < 2k are not specified or recommended. resistor values > 20k are also not recommended. delays greater than 270ns for application requiring delay du rations longer than 270ns, the isl89367 also offers a solution. the input logic pins have precision thresholds which are designed for precision time delays of either the rising of falling edge of outx by using the time constant of a resistor and capacito r. the logic inputs pins of the driver, innx, are connected to the positive inputs of the input comparators. the positive and negative transition threshold voltages are established on the negative inputs of these comparator by a resistor di vider that is biased by v ref+ and v ref- . if v ref+ is connected to the bias voltage of the input logic and if v ref- is connected to the ground of the input logic, then the threshold transitions are propor tional to the bias voltage of the input logic. consequently, the time delays are independent of the accuracy of the input logic bias voltage. figure 16 illustrates a circuit that is used to delay the rising edge of outa relative to the rising edge of the signal source. the value of c should also be substant ially larger than the input capacitance of the input pin of the isl89367, the parasitic capacitance associated with the traces, and the output capacitance, c ds of the signal fet q1. if the signal source is ttl or open drain, r a is required but not for cmos. the calculation of the rising delay is simply shown by equation 1: this is a consequence of the 37%/63% thresholds. figure 15. programmable delay vs rdel and fdel typical performance curves (continued) 0 50 100 150 200 250 300 350 0 5 10 15 20 rising or falling edge delay (ns) rdt (2k to 20k) -40c (worst case) +25c (typical) +125c (worst case) t delay r b c = (eq. 1)
isl89367 10 fn7727.0 january 31, 2011 figure 17 is used to delay the falling edge of outx. in this case the rising time constant is r b x c. logic states the combinational control logic of the isl89367 is very flexible. the state of outx is the anded logic of both inputs, in1x and in2x. the invx input to the exclusiv e-or gate is used to invert the logic state of outx. frequently, for sr applications, it is desirable to have a logic control that can force outa = 0 for the purpose of diode emulation. this ?enable? control input can be either of the in1x or in2x inputs of one channel. in figure 1 on page 1, in1a is used as the enabled input for channel a. when this input is tied to v ref+ , outa follows the state of in2x. if ina1 is connected to v ref- , with inva = 0, outa remains low no matter what state in2a is in. power dissipation and die temp the following is an example of how to calculate the power dissipated by the isl89367 driver. these calculations are intended to give an approximat e temperature rise of the die junction. because operating conditions such as air flow can influence the actual temperatures, it is absolutely necessary to confirm the operating temperatures in a specific application by measuring the isl89367 temper atures with an infra-red temperature sensor or camera . using a thermal couple to measure the temperature of small devices is not recommended because the thermal couple wire w ill act as a heat sink reducing the temperature of the measured de vice to values less than what will actually occur. see tech brief tb379 for more information. figure 18 illustrates how the ga te charge varies with gate voltage, v gs , and the v ds of the driven mosfet. because an sr is switched on and off when v ds = 0 and if we use v gs = 12v, from the graph, q g = 13.5nc. in this example the dissipation of the driver with frequency = 1mhz is shown by equation 2: notice that the dissipation of the driver is not a function of the peak drive rating of the driver. also if an external gate resistor is used to limit the peak curren t output, the dissipation is proportionally shared between the value of the gate resistor and the r ds(on) of the isl89367 output. another parameter that must be considered is the dissipation resulting from the bias current at the frequency of operation. for the isl89367 the bias current @ v dd = 12v and 1mhz is 24ma. the thermal impedances of the isl89367 are: jc = 3c/w ja = 36c/w the temperature rise is: t risejc is the temperature rise referenced to the temperature of the pcb ground plane under the part. in this example the temperature rise is relatively small for jc and ja . obviously the isl89367 could drive significantly larger fets than what is used in this example. output current rating while the isl89367 has a very high peak output current rating of 6a sourcing and sinking, there are limitations to the average output current. with the high peak output current of the isl89367, it is tempting to use the driver as a general purpose switch to drive loads that are not capacitive as are the gates of mosfets. it is important to note that the maximum average vref+ vref- inva in1a in2a outa vdd vss fdela rdela c signal source isl89368 only section a is shown r a r b signal source in2a outa q1 figure 16. rising outa time delay vref+ vref- inva in1a in2a outa vdd vss fdela rdela c signal source isl89368 only section a is shown r a r b signal source in2a outa q1 figure 17. falling outa time delay 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 22 24 qg, total gate charge (nc) v gs gate-to-source voltage (v) v ds = 40v i d = 12a v ds = 0v v ds = 64v figure 18. charge of a typical mosfet p gate 2qg freq v gs = (eq. 2) 217nc1mhz12 = 0.408w = p bias v ds i bias 12v 24ma 0.288w == = (eq. 3) p total p gate p bias 0.408w 0.288w ++ + 0.696w == (eq. 4) t risejc jc p total 2.09 c = = (eq. 5) t riseja ja p total 25 c = = (eq. 6)
isl89367 11 fn7727.0 january 31, 2011 output current rating of the isl89367 of 150ma must not be overlooked. while this value seems low, it is more than adequate to drive very high gate charge values at high frequencies. the average output current (sinking or sourcing) into a capacitive load is: i avg = qg x freq or qg = i avg /freq for a frequency of 1mhz and for the maximum average current of 150ma: this charge is approximately 10x the value of the gate charge as in the example of figure 2 on page 1. obviously, with lower frequencies, this margin is even greater. it is likely that the greater limitation of driving a larg e capacitive load could be the power dissipation. if the driver dissipation is recalculated with a value of 150nc, then: pcb layout guidelines the ac performance of the isl89367 depends significantly on the design of the pc board. the following layout design guidelines are recommended to achieve optimum performance: ? place the driver as close as possible to the driven power fet. ? understand where the switching power currents flow. the high amplitude di/dt currents of the driven power fet will induce significant voltage transients on the associated traces. ? keep power loops as short as possible by paralleling the source and return traces. ? use planes where practical; they are usually more effective than parallel traces. ? avoid paralleling high amplitud e di/dt traces with low level signal lines. high di/dt will induce currents and consequently, noise voltages in the low level signal lines. ? when practical, minimize impedances in low level signal circuits. the noise, magnetically induced on a 10k resistor, is 10x larger than the noise on a 1k resistor. ? be aware of magnetic fields emanating from transformers and inductors. gaps in these structures are especially bad for emitting flux. ? if you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to minimize coupling. ? the use of low inductance comp onents such as chip resistors and chip capacitors is highly recommended. ? use decoupling capacitors to reduce the influence of parasitic inductance in the vdd and gnd leads. to be effective, these caps must also have the shortest possible conduction paths. if vias are used, connect several paralleled vias to reduce the inductance of the vias. ? it may be necessary to add resi stance to dampen resonating parasitic circuits especially on outa and outb. if an external gate resistor is unacceptable, then the layout must be improved to minimize lead inductance. ? keep high dv/dt nodes away from low level circuits. guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. this is especially true for control circuits that source the input signals to the isl89367. ? avoid having a signal ground plane under a high amplitude dv/dt circuit. this will inject di/dt currents into the signal ground paths. ? do power dissipation and voltage drop calculations of the power traces. many pcb/cad programs have built in tools for calculation of trace resistance. ? large power components (power fets, electrolytic caps, power resistors, etc.) will have internal parasitic inductance which cannot be eliminated. this must be accounted for in the pcb layout and circuit design. ? if you simulate your circuits, consider including parasitic components especially parasitic inductance. epad heatsinking considerations the thermal pad is electrically connected to the gnd supply through the ic substrate. the epad of the isl89367 has two main functions: to provide a quiet gnd for the input threshold comparators and to provide heat sinking for the ic. the epad must be connected to a ground plane and no switching currents from the driven fet should pass through the ground plane under the ic. figure 19 is a pcb layout example of how to use vias to remove heat from the ic through the epad. for maximum heatsinking, it is recommended that a ground plane, connected to the epad, be added to both sides of the pcb. a via array, within the area of the epad, will conduct heat from the epad to the gnd plane on the bottom layer. the number of vias and the size of the gnd planes required for adequate heatsinking is determined by the power dissipated by the isl89367, the air flow and the maximum temperature of the air around the ic. q g 150ma 1mhz 150nc = ? = (eq. 7) p gate 2 150nc 1mhz 12v 3.6w == (eq. 8) t riseja 33 3.6w 119 c = = (eq. 9) epad gnd plane component layer epad gnd plane bottom layer figure 19. typical pcb pattern for thermal vias
isl89367 12 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7727.0 january 31, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl89367 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 1/31/11 fn7727.0 initial release
isl89367 13 fn7727.0 january 31, 2011 package outline drawing l16.5x3 16 lead thin dual flat no-lead plastic package rev 0, 05/07 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 6 a b 5.00 3.00 b 0.10 ma c 1 16 8 9 0.50 4.40 3.50 0.25 b 0.40 0.1 1.65 2.20 index area pin 1 index area pin 1 6 6 4 0.10 c 0.08 c c seating plane base plane see detail "x" 0.75 0.05 max c 5 0.05 max 0.20 ref (16x 0.25) (14x 0.50) 4.40 1.65 2.20 (16x 0.60)

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