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product preview this is preliminary information on a new product now in development. details are subject to change without notice. march 2005 1/49 rev. 1 STV0684 digital camera processor features supports the vc6700 cmos sensor (uxga, 1600 x 1200 pixels) from stmicroelectronics high quality video processor ram based firmware pixel defect correction nora (noise reduction algorithm anti-vignetting algorithm advanced statistics processor two general purpose scalers dual video interface for concurrent viewfinder and movie capture st20 32-bit core instruction, data cache and embedded memory for fast code execution embedded rom bootloader for code storage in cost effective nand flash memory code executed in sdram, no code-size limitation avi (audio video interleave) clips directly recorded into the mass storage media long clip length low power consumption flexible tft, d-tfd digital interface for preview (while recording) and review direct support for casio, epson and au optronics displays flexible digital interface designed to support future digital panels pal and ntsc encoder with on-chip digital to analog converter tv display of pictures and movie clips on-chip 16-bit sigma-delta analog to digital converter for audio record audio digital to analog converter for audio playback versatile mass storage interface support compact-flash, nand-on-board, smartmedia, secure digital and multi-media usb 2.0 full speed device usb audio and video class compliant usb mass storage class compliant, bulk only transfer protocol jpeg and mjpeg codec description the STV0684 processor is targeted for use in cmos digital still cameras. st supplies complete camera reference designs which include sensor, co-processor, firmware and software drivers. the STV0684 uses a small bga package (12 mm x 12 mm) ideal for the design of very small digital cameras. the STV0684 incorporates st?s unique and highly performing video processor algorithms including newly improved and patented algorithms (e.g. nora and anti-vignetting). the cmos sensors from stmicroelectronics use pinned photodiodes manufactured in a high performance process resulting in improved low light performance, reducing the gap with ccd sensors. applications digital still cameras solid state video camera recorders embedded cameras ordering information part number temperature package STV0684 [0; +70 ] c bga196 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
STV0684 2/49 technical specifications system overview resolution uxga - vc6700v048 sample rate up to 48 m sample/s (msps) power supply 3.3v and 1.8v power requirements ma typical package bga196, 12x12 mm figure 1: STV0684 system overview dram interface nand interface boot hw ecc lcd controller vp scaler 1 scaler 2 codec usb interface STV0684 STV0684 audio interface nand sdram tv interface st20 core dram interface nand interface boot hw ecc lcd controller vp scaler 1 scaler 2 codec usb interface STV0684 STV0684 audio interface nand sdram tv interface st20 core www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
3/49 STV0684 table of contents chapter 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 chapter 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 chapter 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.1 video processor (vp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 st20-c103 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 sfp module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6.1 audio record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6.2 audio playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 tv interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 lcd controller - display interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 jpeg codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.10 other interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10.1 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10.2 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10.3 comparator for low battery detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 chapter 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.1 sfp ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.2 audio adc electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.3 ac electrical characteristics of usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.5.4 sdram timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.5.5 i2c timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5.6 spi timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5.7 nand timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
STV0684 4/49 4.5.8 ac characteristics for nand flash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5.9 compact flash timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5.10 tft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.11 tv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.12 sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6 esd handling characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.7 external circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.7.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.7.2 audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.7.3 recommended power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 chapter 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.1 STV0684 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.2 STV0684 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
5/49 STV0684 functional block diagram 1 functional block diagram figure 2: STV0684 functional block diagram sensor boot pwm nand sdram (external) vp vdfif dot selector jpeg jpeg decode dma fifo dma ram audio adc usbifo iso iso blkout blkin cf st20 t2 tvc cf flash spi i2c dma dma t1 lcdc tv lcd audio audi o ilc i2c spi core rom fifo fifo fifo ram encode usb www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
signal description STV0684 6/49 2 signal description figure 3: signals identified by functional group power inputs: core i/o master pll audio audio pll tv grounds: common master pll audio audio pll tv 5 15 10 ap sensor interface vddi vddc vddp vdda vss vssp vssa spclk sscl ssda sclk pll and clock: vc xtlo xtli audio an cbs interrupt/ control reset wakeup special function pins (sfp) usb interface dp 133 STV0684 vddap tv_vdda vssap tv_vssa low battery low_batt vref tv interface tv_rext cvbs tv_gnda_rext sensor interface vsync sdata[9:0] hsync 10 dn usb_det sdram sdram 38 st micro connect debug st micro connect 5 st micro connect debug st micro connect 2 graphics display graphics display 17 e-warp debug e-warp debugger 4 cf/nand/smc interface cf/ nand/ smc 28 spi spi 5 pwm output audio output/ piezo other user interface/power management 20 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
7/49 STV0684 signal description table 1: STV0684 signal description 1 pin name location type sfp number description power supplies: total 38 pins vddi1 l12 s vdd io supply 3.3v vddi2 g13 s vdd io supply 3.3v vddi3 f10 s vdd io supply 3.3v vddi4 f7 s vdd io supply 3.3v vddi5 f4 s vdd io supply 3.3v vddi6 k3 s vdd io supply 3.3v vddi7 n3 s vdd io supply 3.3v vddi8 p5 s vdd io supply 3.3v vddi9 n6 s vdd io supply 3.3v vddi10 k8 s vdd io supply 3.3v vddc1 g8 s vdd core supply 1.8v vddc2 c7 s vdd core supply 1.8v vddc3 f2 s vdd core supply 1.8v vddc4 m5 s vdd core supply 1.8v vddc5 m11 s vdd core supply 1.8v vss l13 s ground vss h8 s ground vss f14 s ground vss e13 ground vss b7 s ground vss a7 s ground vss f6 s ground vss g6 s ground vss k4 s ground vss p2 s ground vss p4 s ground vss m6 s ground vss m7 s ground vss p8 s ground vss n11 s ground vddp d8 s pll core supply 3.3v vssp e8 s pll core gnd tv_vdda a12 s tv core supply 3.3v www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
signal description STV0684 8/49 tv_vssa b12 s tv core gnd vdda c10 s audio analog power supply 3.3v vssa b11 s audio analog ground vddap b14 s audio pll supply 1.8v vssap c13 s audio pll ground sensor interface: total 16 pins of which 12 are sfps sdata0 n8 i sfp80 sensor interface bit0 sdata1 m9 i sfp81 sensor interface bit1 sdata2 j8 i sfp82 sensor interface bit2 sdata3 l9 i sfp83 sensor interface bit3 sdata4 p9 i sfp84 sensor interface bit4 sdata5 n9 i spf85 sensor interface bit5 sdata6 k9 i sfp86 sensor interface bit6 sdata7 p10 i sfp87 sensor interface bit7 sdata8 l10 i sfp88 sensor interface bit8 sdata9 n10 i sfp89 sensor interface bit9 hsync m10 i sfp90 horizontal synchronization vsync p11 i sfp91 vertical synchronization sclk n12 o clock supplied to the sensor spclk p14 i data qualifying clock from the sensor ssda p12 i/o i 2 c data line sscl p13 i/o i 2 c clock line sdram interface: total 38 pins all of which are sfps dq0 l14 i/o sfp101 sdram dq1 n13 i/o sfp92 sdram dq2 j9 i/o sfp102 sdram dq3 n14 i/o sfp93 sdram dq4 j10 i/o sfp103 sdram dq5 m12 i/o sfp94 sdram dq6 k13 i/o sfp104 sdram dq7 l11 i/o sfp95 sdram dq8 k10 i/o sfp96 sdram dq9 j11 i/o sfp105 sdram dq10 m13 i/o sfp97 sdram table 1: STV0684 signal description 1 pin name location type sfp number description www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
9/49 STV0684 signal description dq11 j12 i/o sfp106 sdram dq12 m14 i/o sfp98 sdram dq13 j13 i/o sfp107 sdram dq14 k11 i/o sfp99 sdram dq15 k14 i/o sfp108 sdram dqml k12 i/o sfp100 sdram a0 h10 i/o sfp109 sdram a1 j14 i/o sfp110 sdram a2 h11 i/o sfp111 sdram a3 h12 i/o sfp112 sdram a4 h9 i/o sfp113 sdram a5 h14 i/o sfp114 sdram a6 h13 i/o sfp115 sdram a7 g10 i/o sfp116 sdram a8 g14 i/o sfp117 sdram a9 g11 i/o sfp118 sdram a10 g12 i/o sfp119 sdram a11 g9 i/o sfp120 sdram a12 f13 i/o sfp121 sdram ba0 e14 i/o sfp122 sdram ba1 f12 i/o sfp123 sdram clk f11 i/o sfp124 sdram cke d14 i/o sfp125 sdram dqmh e12 i/o sfp126 sdram ras d13 i/o sfp127 sdram cas e11 i/o sfp128 sdram we d12 i/o sfp129 sdram table 1: STV0684 signal description 1 pin name location type sfp number description www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
signal description STV0684 10/49 graphics lcd interface: total 18 pins of which all are sfps l_lp l5 i/o sfp63 lcd interface l_res m4 i/o sfp64 lcd interface l_xinh n4 i/o sfp65 lcd interface l_xscl p3 i/o sfp66 lcd interface l_fryp n5 i/o sfp67 lcd interface l_frys l6 i/o sfp68 lcd interface l_dy / pnl_clk k6 i/o sfp69 lcd interface l_yscl / hsync j6 i/o sfp70 lcd interface l_yscld / vsync p6 i/o sfp71 lcd interface l_dout0 h7 i/o sfp72 lcd interface l_dout1 p7 i/o sfp73 lcd interface l_dout2 k7 i/o sfp74 lcd interface l_dout3 j7 i/o sfp75 lcd interface l_dout4 l7 i/o sfp76 lcd interface l_dout5 n7 i/o sfp77 lcd interface l_frx / data6 m8 i/o sfp78 lcd interface l_gcp / data7 l8 i/o sfp79 lcd interface backlight b6 i/o sfp13 lcd interface / gpio tv interface: total 3 pins cvbs c12 ana cvbs out tv_rext b13 ana tv reference voltage tv_gnda_rext a13 ana tv reference voltage spi (used for mmc, sd): total 5 pins all of which are sfps spi_miso b10 i/o sfp1 master in slave out spi_mosi f9 i/o sfp2 master out slave in spi_slk d9 i/o sfp3 spi clock spi_ss b9 i/o sfp4 spi slave/host selection spi cs e9 i/o sfp5 spi chip select table 1: STV0684 signal description 1 pin name location type sfp number description www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
11/49 STV0684 signal description audio interface: total 6 pins of which 2 are sfps cbs c11 ana audio vbias ap a11 ana audio adc differential input an d10 ana audio adc differential input vc c14 ana audio pll filter pwm out e10 i/o sfp0 dac: pulse width modulator output enable c6 i/o sfp17 enable external audio amplifier nand (smartmedia) & compact-flash interface: total 29 pins all of which are sfps io0 e4 i/o sfp35 smc d0 - cf d00 io1 e3 i/o sfp36 smc d1 - cf d01 io2 d1 i/o sfp37 smc d2 - cf d02 io3 e2 i/o sfp38 smc d3 - cf d03 io4 e1 i/o sfp39 smc d4 - cf d04 io5 f5 i/o sfp40 smc d5 - cf do5 io6 f3 i/o sfp41 smc d6 - cf do6 io7 g3 i/o sfp42 smc d7 - cf do7 nand cs f1 i/o sfp43 nand chip select we g7 i/o sfp44 smc we - cf we ale oe g2 i/o sfp45 smc ale - cf oe cle rdy j1 i/o sfp46 smc cle - cf ready rb wait j4 i/o sfp47 smc r/-b - cf wait re reg j2 i/o sfp48 smc re - cf reg cs card en j5 i/o sfp49 smc cs - cf ce1 writ_prot card det1 k1 i/o sfp50 smc wp - cf wp card_det card det2 k5 i/o sfp51 smc cd - cf cd1 cfa0 k2 i/o sfp52 cf a00 cfa1 l1 i/o sfp53 cf a01 cfa2 l2 i/o sfp54 cf a02 cfa3 l3 i/o sfp55 cf a03 cfa4 m1 i/o sfp56 cf ao4 cfa5 m2 i/o sfp57 cf a05 cfa6 n1 i/o sfp58 cf a06 cfa7 n2 i/o sfp59 cf a07 table 1: STV0684 signal description 1 pin name location type sfp number description www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
signal description STV0684 12/49 cfa8 m3 i/o sfp60 cf a08 cfa9 p1 i/o sfp61 cf ao9 cfa10 l4 i/o sfp62 cf a10 user interface - (application specific sfp): total 16 pins all of which are sfps mode up f8 i/o sfp6 see firmware manual mode down a10 i/o sfp7 see firmware manual select c9 i/o sfp8 see firmware manual cancel a9 i/o sfp9 see firmware manual shutter d7 i/o sfp12 see firmware manual led0 a5 i/o sfp18 see firmware manual led1 b5 i/o sfp19 see firmware manual flash rdy b8 i/o sfp10 see firmware manual flash trigger e5 i/o sfp20 see firmware manual power off e7 i/o sfp11 see firmware manual power down a6 i/o sfp14 see firmware manual snap b4 i/o sfp24 sensor interface shutter_cntl1 d5 i/o sfp21 mechanical shutter interface shutter_cntl2 a4 i/o sfp22 mechanical shutter interface shutter_cntl3 c5 i/o sfp23 mechanical shutter interface suspend e6 i/o sfp15 sensor suspend pin general purpose input/output: total 11 pins all of which are sfps gpio0 b3 i/o sfp28 general purpose io gpio1 a2 i/o sfp29 general purpose io gpio2 c3 i/o sfp30 general purpose io / jtag trig ewarp gpio3 b2 i/o sfp31 general purpose io / jtag tdi ewarp gpio4 a1 i/o sfp32 general purpose io / jtag tdo ewarp gpio5 b1 i/o sfp33 general purpose io / jtag tms ewarp gpio6 c2 i/o sfp34 general purpose io / jtag tck ewarp gpio7 d3 i/o sfp130 general purpose io gpio8 c4 i/o sfp25 general purpose io gpio9 a3 i/o sfp26 general purpose io gpio10 d4 i/o sfp27 general purpose io table 1: STV0684 signal description 1 pin name location type sfp number description www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
13/49 STV0684 signal description usb interface: total 4 pins of which 1 is a sfp dp g4 i/o usb datap dn g5 i/o usb datan detect g1 i/o high when usb vcc present usb tx_en d6 i/o sfp16 battery level detector: total 2 pins low_batt a14 ana battery level input vref d11 ana reference for the battery voltage clock, reset, system signals: total 4 pins xtal in c8 ana 27 mhz crystal input xtal out a8 ana 27 mhz crystal output reset c1 i reset input wake_up d2 i/o debug and test interface: total 7 pins of which 2 are sfps up_trigi h5 i/o sfp131 st20 microconnect debug interface up_trigo h4 i/o sfp132 st20 microconnect debug interface up_tdi h1 i st20 microconnect debug interface up_tdo h2 o st20 microconnect debug interface up_tms j3 i st20 microconnect debug interface up_tck h6 i st20 microconnect debug interface up_rst h3 i st20 microconnect debug interface 1. this is preliminary information that may be subject to change table 1: STV0684 signal description 1 pin name location type sfp number description www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
functional description STV0684 14/49 3 functional description 3.1 video processor (vp) the vp is the result of stmicroelectronics extensive know-how and hard work around the colour science for cmos sensor. the vp block fulfills many functions related to colour reconstruction from a bayer filter, colour matrixing and sharpening, real-time and programmable defect pixel correction, agc, awb, anti flicker and gamma correction, scaling from the sensor to the required video and lcd panel resolution. this new video processor benefits from stmicroelectronics latest algorithms development such as the patented noise reducti on algorithm and anti-vignetting that ensures the highest quality standard. the vp combines hardware and firmware. the main block controller is powered by a 8051 e warp microcontroller, with ram based firmware for the highest level of flexibility. feature list system features ram based firmware dual video interface for simultaneous viewfinder and movie capture bayer or ycbcr input from supported memory 48mpixel/s capable processing pipe flashgun and shutter support rgb/yuv 4:2:2 output formats image reconstruction functions x2, x2.5 horizontal downscaling colour channel gains and offsets anti-vignetting defect correction nora - active noise reduction demosaic (bayer->rgb conv) yuv matrix (rgb -> yuv) image crop general purpose rgb downscaler rgb matrix peaking gamma correction statistics processor 4 accumulators - programmable on the fly programmable zones www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
15/49 STV0684 functional description image control functions (tasks handled by the ewarp processor) sensor detection, initialisation and configuration vp mode management: stills, streaming etc. automatic exposure control, automatic white balance flicker correction dampening/promotion tasks scaler management dark calibration flashgun control shutter control 3.2 st20-c103 core the st20 core is the heart of the STV0684 system-on-chip. the processor can execute its code from either the 64kb of private sram or directly from the external sdram. instruction/data cache ensure a fast code execution. a boot loader residing in a rom of the device provides capability to boot the system by copying the application firmware image from non volatile memory (spi flash or standard nand flash) to the program sram or sdram memory. this mechanism ensures the lowest system cost by storing the application firmware on a cheap mass storage memory and thus avoiding the extra cost of a nor type memory. the boot loader also provides the useful possibility to upgrade the application firmware and therefore program cameras on the factory line. the st20-c103 core includes the following: st20c1 processor running at 48 mhz frequency diagnostic control unit dcu3 (4 compare, 4 capture, trace) for debug and code development pwm4 timer, intc2 interrupt controller (16 inputs) 64k local ram (sram) 4k d-cache & 4k i-cache instruction and data caches memory arbiter www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
functional description STV0684 16/49 core architecture and block diagram 3.3 sfp module the sfp module is based on reconfigurable device pins combined with some local logic to maximize in-system flexibility of the device in any given application an sfp can be configured either to be driven as a gpio or by the local logic block within the STV0684 (detailed in figure 3 ). the functionality and configuration of each sfp is determined and managed under control of the st20. control registers local to each module are mapped into the processors address space, this leaves the processor to support more demanding, computational intensive tasks. figure 4: st20dc3 architecture and block diagram st20-c103 st20-c103 sdram st20-c103 icache dcache peripheral controller port peripheral 1 st bus type 2 domain st bus type 1 domain st20-c103 interconnect reg_dec_0 node reg_dec_1 reg_dec_2 peripheral 2 peripheral 10 peripheral 11 peripheral 10 peripheral 20 boot rom www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
17/49 STV0684 functional description 3.4 usb interface the usb interface fulfills the three following functions: the first function is to download from the camera to the pc all the various objects stored on the mass storage media. the STV0684 uses mass storage class, bulk only transfer to ensure seamless connection with most of the operating system on the market, including pc and mac platforms. the second function is to stream concurrent audio and video through isochronous endpoints. once again, the STV0684 follow established and newly developed standards to ensure the lowest burden of driver development. the STV0684 is usb audio class and usb video class compliant. the third function allows the download of the system program code, necessary to run the application, to either serial flash or nand flash soldered on the main camera pcb. this function is extremely convenient when programming the cameras on the manufacturing lines and is not open to final users. features usb 2.0 compliant (full speed device) full speed (12 mbps) signalling bit rate usb audio class compliant usb video class compliant usb mass storage compliant, bulk only transfer protocol simultaneously accessible endpoints: ? isochronous endpoint (in) for video ? isochronous endpoint (in) for audio ? bulk endpoint (in) for download ? bulk endpoint (out) for download ? interrupt endpoint (in) ? control pipe www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
functional description STV0684 18/49 3.5 memory interface description the memory control block provides dedicated support for embedded sram, external sdram, nand, smartmedia and compact flash (via sfp pins). embedded sram full-speed random read/write access from the st20 to embedded sram full-speed embedded sram address generation for real-time data writes from the compression engine, the video processor block, spi, the audio block and the usb module full-speed embedded sram address generation for data reads to the dma out fifo selection of the source/destination modules is managed by firmware. external sdram st20 memory mapped accesses to external sdram full-speed embedded sdram address generation for real-time data writes from vdfif (for vc and vp modules) or dma out fifo full-speed external sdram address generation/control to dma out fifo, tv fifo, lcd fifo or vp fifo?s operation with pc100 (or better e.g. pc133) and jedec standard no. 21-c compliant devices and supports 64mb, 128mb, 256mb and 512mb parts with a 16-bit bus width mass storage media support compact-flash support smartmedia card support nand flash memory with a 512b+16 page org anization, ecc done by hardware, 32mbit to 1gbit devices support for multi-media card and secure digital with the spi interface www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
19/49 STV0684 functional description 3.6 audio interface the STV0684 includes every step of the processing chain required to record, compress, decompress and playback audio. the STV0684 featur es a high quality 16 bi t sigma delta analog to digital converter including automatic level control and noise gating, as well as volume control. it also features an adpcm codec to maximize the length of audio and avi clips on a given mass storage media. finally, the product features a digital to analog converter (pwm followed by rc filters) to directly address a speaker or buzzer for audio playback. 3.6.1 audio record the audio record block consists two main blocks the analogue front end and a 16bit delta-sigma adc. the front end includes the functions of automatic level control and noise gate, and volume control, the adc uses sampling frequencies of 8khz, 11.025khz, 16khz, 22.05khz, 32khz, 44.1khz and 48khz, with either differential or single ended inputs. the sampled output can be 8 or 16 bit. the output of the acd is then available to the adpcm module giving an audio compression ratio of 4 to 1. 3.6.2 audio playback audio playback is achieved by an internal pulse width modulator with a sample rates of 8khz, 11.025khz, 16khz, 22.05khz, 32khz or 44.1khz, connected to either an external amplifier chip and loudspeaker/ head phone socket, or to a simple piezo buzzer. 3.7 tv interface the tv block is composed of a digital encoder that supports pal and ntsc and a video digital to analog converter (dac). this interface supports still and video encoding for display on a tv set. features supports pal/ntsc analog tv standards interlaced input data, ycrcb 4:2:2 format 16bits x 16words fifo for buffering incoming display data interrupt generation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
functional description STV0684 20/49 3.8 lcd controller - display interface the STV0684 lcd controller has been specifically designed to ensure the two following important characteristics: support of low cost panels with a direct interface to digital lcd panels removing the need for an external timing controller ic flexibility with a high-level of programmability on all the signals shapes, polarities and frequencies the display interface fully supports lcd panel dot selection modes such as delta, delta transverse, delta longitudinal and mosaic and many more by incorporating a dot selector which converts 3dot/pixel input rgb frame data, to 1dot/pixel rgb data. basic functionality of the system includes still picture review, viewfinder mode as well as viewfinder mode while recording a video clip. features support thin film transistor (tft) color displays 64 or 256 grey level, 256k(18bit)or 16.7million(24bit) color tft support 6 bit or 8 bit display interfaces 16-deep, 16bit deep fifo for buffering incoming display data resolution programmable up to 1024x1024 pixels programmable timing for different display panels support casio, epson, and au optronics panels horizontal, vertical sync and pixel clock signals supports little-endian data formats interrupt generation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
21/49 STV0684 functional description 3.9 jpeg codec description the STV0684 features a compression and a decompression engine that is used for both still pictures and video clips. the hardware codec ensures a fast reaction time of the system to encode and decode data. this is particularly important to minimize the shutter to shutter time and the ability to rapidly display images on a local display or the tv set. compression engine the compression engine uses baseline sequential jpeg techniques to compress a digital 656 video stream (at up to 12mpixels/s), down to bandwidth that can be transmitted over the usb interface or to a mass st orage media, typically 500-900kbytes/s. it outputs a jpeg data stream with the headers required by standard decoders. decompression engine the jpeg decoder block reads the compressed data from the dma fifo, parses the header and writes back decompressed data back to dma fifo. this data is organized in 8x8 blocks of the different color components. this data can be converted to raster scan format to be read by the display controller for display on a lcd or tv. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
functional description STV0684 22/49 3.10 other interfaces 3.10.1 spi the spi interface is a generic serial interface that can be used to perform the following functions: support for multi-media and secure digital cards support for serial flash where code can be located the spi supports: full duplex, three-wire synchronous transfers single, master/slave operation selectable either through firmware or hardware programmable clock polarity and phase end of transfer interrupt flag write collision flag busy flag indication 3.10.2 i2c the STV0684 features a hardware i2c master interface and supports the following features: i2c protocol standard i2c mode (100 khz)/fast i2c mode (400 khz) single master mode transmitter/receiver performance 7/10 bit addressing dma mode data transfer clock stretching 3.10.3 comparator for low battery detection the comparator circuit was designed to compare the battery voltage (after an external resistor divider) with an external reference voltage and generate a low_batt (high when battery voltage is lower than the present threshold) signal for the cpu core. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
23/49 STV0684 electrical characteristics 4 electrical characteristics 4.1 absolute maximum ratings caution: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2: absolute maximum ratings symbol parameter value unit v ddc supply voltage (core) 2.5 v v ddi supply voltage (io) 4.0 v v ddp supply voltage (pll) 4.0 v v dda supply voltage (audio) 4.0 v v ddap supply voltage (audio_pll) 2.5 v v tv_vdda supply voltage (tv) 2.5 v current on any signal pin 2 ma t sto storage temperature -50 to 150 c t op operating temperature 0 to 70 c t lead lead temperature (soldering, 10 s) +260 c www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 24/49 4.2 operating conditions 4.3 thermal data note: 1 typical, measured with the component mounted on an evaluation pc board in free air. table 3: operating conditions symbol parameter typ. unit v ddc supply voltage (core) 1.8 v v ddi supply voltage (io) 3.3 v v ddp supply voltage (pll) 3.3 v v dda supply voltage (audio) 3.3 v v ddap supply voltage (audio_pll) 1.8 v v tv_vdda supply voltage (tv) 3.3 v t a ambient temperature 25 c table 4: thermal data symbol parameter value unit rth(j-a) junction-ambient thermal resistance - lfbga196 ( note 1 )50c/w www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
25/49 STV0684 electrical characteristics 4.4 dc electrical characteristics over operating conditions unless otherwise specified. values from ta b l e 5 and ta b l e 6 are estimates. table 5: dc electrical characteristics symbol parameter min typ max unit v il input low voltage (xtal_in) 0 0.631 v v ih input high voltage (xtal_in) 1.123 v ddc v v hys hysteresis (xtal_in) 0.492 v v il input low voltage (sfp pin) 1 1. these figures apply to sfp, spclk, sscl, and ssda, they do not apply to the xtal_in pad 0 0.8 v v ih input high voltage (sfp pin) 1 2 v ddi v v hys schmitt trigger hysteresis (sfp pin) 1 0.4 v v t+ schmitt input low to high threshold voltage (sfp pin) 1 2.15 v v t- schmitt input high to low threshold voltage (sfp pin) 1 1.05 v v t threshold point (sfp pin) 1 1.65 v v ol output low voltage(sfp pin) 0.4 v v oh output high voltage(sfp pin) 2.4 v i il input leakage current input pins i/o pins 1 a v ilu usb differential pad d+/d- input low 0.8 v v ihu usb differential pad d+/d- input high (driven) 2.0 v v ihuz usb differential pad d+/d- input high (floating) 2.7 3.6 v v tdi usb differential pad d+/d- input sensitivity 2 2. v di = |(d+)- (d-)| 0.2 v v cm usb differential pad d+/d- common mode voltage 3 3. v cm includes v di range 0.8 2.5 v v olu usb differential pad d+/d- output low voltage 0.0 0.3 v v ohu usb differential pad d+/d- output high voltage 2.8 3.6 v v crs usb differential pad d+/d- output signal cross over voltage 1.3 2.0 v z drv driver output resistance 28 44 ? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 26/49 table 6: power supply specifications symbol parameter min typ max unit v ddc supply voltage (core) 1.65 1.8 1.95 v v ddi supply voltage (io) 3.0 3.3 3.6 v v ddp supply voltage (pll) 3.0 3.3 3.6 v v dda supply voltage (audio) 3.0 3.3 3.6 v v ddap supply voltage (audio_pll) 1.65 1.8 1.95 v v tv_vdda supply voltage (tv) 3.0 3.3 3.6 v i suspend core suspend current 0.2 ma io suspend current 1.166 ma pll suspend current 1 a audio suspend current 1 a audio_pll suspend current 1 a tv suspend current 1 a i low power core low power current 54.3 ma io low power current 6.3 ma pll low power current 3.8 ma audio low power current 5.9 a audio_pll low power current 12 a tv low power current 1 a i highpower core high power current 130 ma io high power current 17.8 ma pll high power current 7.74 ma audio high power current 5.3 ma audio_pll high power current 0.23 ma tv high power current 11.63 ma www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
27/49 STV0684 electrical characteristics 4.5 ac electrical characteristics 4.5.1 sfp ac parameters each sfp is a ttl schmitt trigger bidirectional pad buffer, 3v3 capable with 2ma drive capability and slew-rate control. the 3.3v ios comply to the eia/jedec standard jesd8-b. 4.5.2 audio adc electrical parameters table 7: audio/adc electrical characteristics symbol parameter test conditions min. typ. max. unit fclk clock frequency 12 mhz dutymclk clk duty cycle 40 60 % fs sample frequency 8 48 khz vbias bias reference voltage vbias / v dda = 3v 1.5 v rbias vbias impedance vbias 5 k ? rin input impedance in+ / in- 50 k ? cin input capacitance in+ / in- 10 pf dyn in input dynamic range adc out full scale in+ / in- gain 0db (agc off) 1.5 vpp snr* signal / noise ratio sinewave @fs - 3db gain 0db 82 db offset offset error after automatic calibration 100 lsb harm 1 1. input sine wave 1khz, fmclk 11.289 mhz, bw = 10hz-20 khz, a-weighting filters, output 16 bits raw pcm signal to peak harmonics sinewave @fs - 3db gain 0db 75 db sinewave @fs - 3db gain 24db 50 db www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 28/49 4.5.3 ac electrical characteristics of usb transceiver all measurements are fully electrically compliant to chapter 7 (electrical requirements) of revision 2 of the usb specification for full-speed devices (v1.1). the transceiver has been tested with external impedance-matching series resistors (27 ? +/-5%) between the pads and the usb cable. the operation of the usb transceiver is guaranteed through design and application testing. table 8: ac characteristics of usb transceiver symbol description min. typ. max unit transmit /output stage tlr fall time 4.45 5.82 7.31 ns tlf rise time 4.55 5.77 6.81 ns tlrfm rise and fall time matching 90 111 % system rpu usb differential pad dp, dn pullup resistor 1.425 1.575 k ? rpd usb differential pad dp, dn pulldown resistor 14.25 15.75 k ? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
29/49 STV0684 electrical characteristics 4.5.4 sdram timing description 4.5.4.1 read/write timing diagrams for external synchronous dram figure 5: sdram read timing figure 6: sdram write timing dclk command dqm a0-9, ba, a10 active read nop precharge nop row column row dout m dout m + 1 dout m + 2 dout m + 3 dq cas latency t ck t rcd t rc cke t ras dq sample dq sample dq sample dq sample t rp t cms t cmh t as t ah t cl t ch t cms t cmh t ac t oh (ras, cas, we) a11-12 dclk command dqm a0-9, a10 sdram write timing active write nop precharge nop row column row din m din m + 1 din m + 2 din m + 3 dq t ck t rcd t rc cke t ras t rp t cms t cmh t as t ah t cl t ch t cms t cmh t ds t dh (ras, cas, we) a11-12 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 30/49 note: 1 the sdram interface is designed to operate with sdram devices which are compliant with the intel sdram specification revision 1.7 november 1999. speed grades 66, 100 and 133mhz are compatible. 2 above timing assumes 20pf load per pad. table 9: sdram timing symbol min typ max units t ck 41.67 ns t ch t ck /2 - (t ck *0.0345) t ck /2 t ck /2 + (t ck *0.0345) ns t cl t ck /2 - (t ck *0.0345) t ck /2 t ck /2 + (t ck *0.0345) ns t ac 24.8 ns t oh 0 ns t cms 20.3 ns t cmh 20 ns t as 20.7 ns t ds 20.1 ns t dh 21.8 ns t rcd 1 t ck t ras 2 t ck t rc 4 t ck t rp 2 t ck t rrd 1 2 t ck tah 19.8 ns 1. t rrd = row active to row active delay www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
31/49 STV0684 electrical characteristics 4.5.5 i 2 c timing description figure 7: start and stop conditions figure 8: sda data valid table 10: i 2 c timing spec symbol parameter std mode fast mode unit minmaxminmax f scl scl clock frequency 10 100 10 400 khz tlow low period of scl 4.8 - 1.4 - s thigh high period of scl 4.8 - 0.9 - s thd;sta hold time for a repeated start 4.8 - 1.4 - s tsu;sta setup time for repeated start 4.8 - 0.9 - s tstu;sto setup time for a stop 4.8 - 0.9 - s thd;dat data hold time 350 - 350 - ns tsu;dat data setup time 2.4 - 045 - s tbuf bus free time between stop and start 4.8 - 1.4 - s start stop sda scl thd;sta tsu;sta tsu;sto scl sda data valid data allowed to change data valid data allowed to change thigh tlow tsu;dat thd;dat www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 32/49 4.5.6 spi timing description it is able to support master and slave mode. the timing given is needed for slave mode and in master mode is able to provide t r , t f = 5ns with output load 30pf figure 9: message format figure 10: spi timing diagram table 11: spi timing table symbol parameter min max units f sck sck frequency= 1/t sck 24 (master) 48 (slave) mhz t dsu data in setup time 18(master) 5(slave) ns t dh data in hold time 0(master) 5(slave) ns scl sda s sr 7 bit device add r/w a8 bit data a (a) p 123 8 91 2 789 msb lsb msb lsb t dsu t dh spi_miso spi_slk spi_slk spi_mosi t v t css t chsh t cs spi_slk spi_slk spi_ss spi_ss t sck www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
33/49 STV0684 electrical characteristics in slave mode for resynchronization purpose the need for idle phase between byte transfer is needed for the transmit mode. t css ss active setup time, relative to sck 210(master/ slave) ns t chsh ss active hold time, relative to sck 50(master/ slave) ns t v clock low to output valid 20 (master/slave) ns t cs minimum ss high time 120(slave) ns t idle idle phase between byte transfer in transmit mode for resynchronisation 120(slave) ns figure 11: idle phase timing in slave mode table 11: spi timing table symbol parameter min max units t idle sck www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 34/49 4.5.7 nand timing description figure 12: command latch cycle for nand flash interface figure 13: address latch cycle for nand flash interface t cls t wp t clh t ds t dh command cle we_n ale io[7:0] ce_n t als t alh t cls t wp t wc t ds t dh a0-a7 cle we_n ale io[0:7] ce_n a9-a16 a17-a21 t wh t alh www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
35/49 STV0684 electrical characteristics figure 14: input data latch cycles for nand flash interface figure 15: sequential output cycle after read for nand flash interface figure 16: status read cycle for nand flash interface t als t wp t clh t ds t dh din0 cle we_n io[0:7] ce_n din1 din511 t wh ale t wc dout re_n io[0:7] rb_n dout dout ce_n t rc t rp t reh t rea t rr t ds 70h cle re_n io[0:7] ce_n status we_n t cls t clh t cls t wp t whr t dh t rsto www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 36/49 figure 17: read operation for nand flash interface figure 18: reset operation for nand flash interface t wb cle re_n io[0:7] ce_n ale a0-7 00h a9-16 a17-21 rb_n dout0 dout1 dout2 we_n t r t rr cle io[0:7] ce_n ffh rb_n we_n t rst www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
37/49 STV0684 electrical characteristics 4.5.8 ac characteristics for nand flash operation note: 1 all parameters relating to the ce_n signal are omitted as it is not enabled/disabled during execution of any nand flash operation i.e. it is permanently tied low. 2 all timings are worst case 3 conforms to both samsung and toshiba specifications as outlined in datasheets. 4 the nand flash timings detailed here are guaranteed by design. 5 the loading factor used for the characterization is equivalent to 40pf. 4.5.9 compact flash timing there are two types of bus cycles and timing sequen ces that occur in the pcmcia type interface, direct mapped i/o transfer and memory access. the STV0684 will only support the memory mapped mode. table 12: ac characteristics for nand flash operation symbol parameter min typical max units t cls cle set-up time 61.4 62.4 ns t clh cle hold time 83.2 ns t wp we-n pulse width 83.2 ns t als ale set-up time 82.6 83.2 ns t alh ale hold time 82.4 83.2 ns t ds data set-up time 82.6 83.2 ns t dh data hold time 61.8 62.4 ns t wc write cycle time 145.1 145.6 ns t wh we_n high hold time 61.9 62.4 ns t rr ready to re_n low 81 83 ns t rp re_n pulse width 83.2 ns t rc read cycle time 187.2 ns t rea re_n access time 35 43.2 ns t reh re_n high hold time 103.5 104 ns t whr we_n high to re_n low 124.2 124.8 ns t r data transfer from cell to register 25.015 s t wb we_n high to busy 41.6 215.3 ns t rst device resetting (read) 5.015 s www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 38/49 4.5.9.1 compact flash pin description the following table lists the pins of the cf card which are connected to the STV0684.output refers to pins that are driven by STV0684. input is those pins that are driven by the cf card. 4.5.9.2 compact flash timings the timings achieved for accessing the attribute and common memory are listed below.there are registers in the cf controller of the STV0684 in which all these timings can be programmed in terms of number of clocks of 48mhz. all the timings below assume a 48mhz operating clock frequency. table 13: pin description symbol pin description direction sfp used cfa0 ~cfa10 address output 52~62 card_det card_det2 card detect input 50 cs card en card enable. output 49 io0~io7 data. only 8 bits of the data bus d[7:0] are used. input 35~42 ale oe output enable output 45 cle rdy ready/busy input 46 re reg register(attribute) memory select output 48 rst reset note 1 1. the reset may come from the global reset of the system or be driven by a user definable sfp this function is application specific. rb wait wait input 47 we write enable output 44 table 14: cf attribute memory read timing symbol parameter min. typ. max. units tc(r) read cycle time 340 - ns ta(a) address access time - 300 ns ta(ce) card enable access time - 300 ns ta(oe) output enable access time - 300 ns tdis(ce) output disable time from ce - 100 ns tdis(oe) output disable time from oe - 100 ns tsu (a) address setup time 40 - ns ten(ce) output enable time from ce 5 - ns ten(oe) output enable time from oe 5 - ns tv(a) data valid from address change 0 - ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
39/49 STV0684 electrical characteristics figure 19: attribute memory read timing diagram table 15: attribute memory write timing symbol parameter min. max. units tc(w) write cycle time 280 ns tw(we) write pulse width 200 ns tsu(a) address setup time 40 ns trec(we) write recovery time 40 ns we tsu(d-weh) data setup time for we 160 ns th(d) data hold time 40 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 40/49 figure 20: attribute memory write timing diagram table 16: common memory read timing symbol item min. max. units ta(oe) output enable access time 140 ns tdis(oe) output disable time from oe 100 ns tsu(a) address setup time 40 ns th(a) address hold time 40 ns tsu(ce) ce setup before oe 0 ns th(ce) ce hold following oe 40 ns tv(wt-oe) wait delay falling from oe 40 ns tv(wt) data setup for wait release 0 ns tw(wt) wait width time 350 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
41/49 STV0684 electrical characteristics figure 21: common memory read timing diagram table 17: common memory write timing symbol parameter min. max. units tsu(d-weh) data setup before we 80 ns th(d) data hold following we 40 ns tw(we) we pulse width 200 ns tsu(a) address setup time 40 ns tsu(ce) ce setup before we 0 ns trec(we) write recovery time 40 ns th(a) address hold time 40 ns th(ce) ce hold following we 20 ns tv(wt-we) wait delay falling from we 40 ns tv(wt) we high from wait release 0 ns tw (wt) wait width time 350 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 42/49 4.5.10 tft 4.5.11 tv tv timing description tv external components an external 10000 ohm precision resistor typical 1% placed between the tv_rext pin and gndas_rext sets the full scale dac current. table 18: tft timing symbol parameter min. max. units pnl_clk panel clock 1.56 27 mhz hsync 1 1. hsync & vsync are active low (default, but programmable) and the falling edge of both hs & vs are always synchronous. horizontal sync 2 1822 pnl_clk periods vsync 1 vertical sync 2 1598 horizontal sync periods table 19: tv timing description symbol parameter min. typ. max. unit resolution 10 bits recommended load impedance 175 ? analog output dynamic current 1 1. the output current of 8ma = typ: tv_rext - tv_gnda_rext =1.4v, rref=10000 ? 6.64 8 9.36 ma output voltage 1 1.6 v dc dynamic performance snr, bw=10mhz, fclk=80mhz 50 db thd, bw=10mhz, fclk=80mhz 50 db voltage reference v_rext - tv_gnda_rext -7% 1.4 +7% v www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
43/49 STV0684 electrical characteristics 4.5.12 sensor interface 4.6 esd handling characteristics figure 22: timing for sensor input table 20: timing for sensor input symbol parameter min max unit t clk spclk 20 (50mhz) 1000 (1mhz) ns t setup data valid before clock rising 1.5 ns t hold data hold time t clk /2 t rmax max transition time (20% to 80%) 1 ns t skew data / clock skew 440 ps clock duty cycle 45 55 table 21: esd handling characteristics test criteria unit esd machine model 150 v esd human body 2 kv spclk sdata[9:0] sensor_hsync sensor_vsync t rmax t skew t clk t setup t hold www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
electrical characteristics STV0684 44/49 4.7 external circuits 4.7.1 crystal oscillator there are 2 crystal oscillator pins xtal_in, xtal_out, as shown in figure 23. the oscillator cell architecture is a single stage oscillator with an inverter working as an amplifier. the oscillator stage is biased by an internal resistor (>1m ? ). it also requires an external pi network consisting of a crystal and two capacitors. note: the tv standards requests that the clock accuracy of the oscillator circuit must be 30ppm or less to achieve a 500hz accuracy for 4.5mhz chroma. 4.7.2 audio if the record audio section of the STV0684 is not required, ap, cbs, vc and an can be left unconnected. power must still be supplied to vdda and vddap. 4.7.3 recommended power supply decoupling a 0.1 f bypass capacitor located as close as possible to the chip package connecting between all vdd pins and gnd and at least one bulk decoupling capacitor on each of the supply rails vdda, vddc, vddi and vddp. figure 23: oscillator support circuit figure 24: audio pll filter and cbs xtali xtalo crystal 22pf 22pf + _ 10f 680pf cbs vc 10k 10nf www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
45/49 STV0684 package information 5 package information 5.1 STV0684 pin assignment figure 25: STV0684 pin assignment 7 13 12 11 10 9 8 14 654321 g h k l m e f d j n p c b a vddap tv_ rext tv_ vssa vssa sfp1 sfp4 sfp10 vss_5 sfp13 sfp19 sfp24 sfp28 sfp31 sfp33 vc vssa p cvbs cbs vdda sfp8 xtali vddc _2 sfp17 sfp23 sfp25 sfp30 sfp34 reset low_ bat tv_gnda _rext tv_vdda ap sfp7 sfp9 xtalo vss_6 sfp14 sfp18 sfp22 sfp26 sfp29 sfp32 sfp125 sfp127 sfp129 vref an sfp3 vddp sfp12 sfp16 sfp21 sfp27 sfp130 wakeup sfp37 sfp122 vss_4 sfp126 sfp128 sfp0 sfp5 vssp sfp11 sfp15 sfp20 sfp35 sfp36 sfp38 sfp39 vss_3 sfp121 sfp123 sfp124 vddi_3 sfp2 sfp6 vddi_4 vss_7 sfp40 vddi_5 sfp41 vddc_3 sfp43 sfp117 vddi_2 sfp119 sfp118 sfp116 sfp120 vddc_1 sfp44 vss_8 dn dp sfp42 sfp45 usb_ detect sfp114 sfp115 sfp112 sfp111 sfp109 sfp113 vss_2 sfp72 up_ tck sfp132 sfp131 up_ rst up_ tdo up_ tdi sfp110 sfp107 sfp106 sfp105 sfp103 sfp102 sfp82 sfp75 sfp70 sfp49 sfp47 up_ tms sfp48 sfp46 sfp108 sfp104 sfp100 sfp99 sfp96 sfp86 vddi_ 10 sfp74 sfp69 sfp51 vss_9 vddi_6 sfp52 sfp50 sfp101 vss_1 vddi_1 sfp95 sfp88 sfp83 sfp79 sfp76 sfp68 sfp63 sfp62 sfp55 sfp54 sfp53 sfp98 sfp97 sfp94 vddc_5 sfp90 sfp81 sfp78 sfp13 sfp12 vddc_4 sfp64 sfp60 sfp57 sfp56 sfp93 sfp92 sclk vss_ 15 sfp89 sfp85 sfp80 sfp77 vddi_9 sfp67 sfp65 vddi_7 sfp59 sfp58 spclk sscl ssda sfp91 sfp87 sfp84 vss_ 14 sfp73 sfp71 vddi_8 vss_ 11 sfp66 vss_ 10 sfp61 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
package information STV0684 46/49 5.2 STV0684 package mechanical data note: 1 the maximum mounted height is 1.57 mm based on a 0.37 mm ball pad diameter. solder paste is 0.15 mm thick with 0.37 mm ball pad diameter. 2 lfbga stands for l ow profile f ine pitch b all g rid a rray. low profile: the total profile height (dim a) is measured from the seating plane to the top of the component. a = [1.21 to 1.70] mm fine pitch: e<1.00 mm pitch. 3 the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings or other features of package body or integral heatslug. a distinguishing feature can be added on the bottom su rface of the package to identify the terminal a1 corner. exact shape of each corner is optional. reference dimensions (mm) min. typ. max. a 1.210 1.700 a1 0.270 a2 1.120 b 0.450 0.500 0.550 d 11.850 12.000 12.150 d1 10.400 e 11.850 12.000 12.150 e1 10.400 e 0.720 0.800 0.880 f 0.650 0.800 0.950 ddd 0.120 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
47/49 STV0684 package information figure 26: lfbga 12x12x1.70 196 (80% scale versus original drawing) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
revision history STV0684 48/49 revision history table 22: revision history version date comments 1 22-mar-05 first publication for this revision 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
STV0684 49/49 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized fo r use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics. all rights reserved. stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states http://www.st.com www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com

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