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features ? one of a family of devices with user memories from 1-kbit to 8-kbits ? 2-kbit (256-byte) eeprom user memory ? four 512-bit (64-byte) zones ? self-timed write cycle ? single byte or 16-byte page write mode ? programmable access rights for each zone ? 2-kbit configuration zone ? 37-byte otp area for user-defined codes ? 160-byte area for user-defined keys and passwords ? high security features ? 64-bit mutual authentication protocol (under license of elva) ? cryptographic message authentication codes (mac) ? stream encryption ? four key sets for authentication and encryption ? eight sets of two 24-bit passwords ? anti-tearing function ? voltage and frequency monitors ? smart card features ? iso 7816 class b (3v) operation ? iso 7816-3 asynchronous t=0 protocol (gemplus? patent) * ? multiple zones, key sets and passwords for multi-application use ? synchronous 2-wire serial interface for faster device initialization * ? programmable 8-byte answer-to-reset register ? iso 7816-2 compliant modules ? embedded application features ? low voltage supply: 2.7v ? 3.6v ? secure nonvolatile storage for sensitive system or user information ? 2-wire serial interface (twi, 5v compatible) ? 1.0 mhz compatibility for fast operation ? standard 8-lead plastic packages, green compliant (exceeds rohs) ? same pin configuration as at24cxxx serial eeprom in soic and pdip packages ? high reliability ? endurance: 100, 000 cycles ? data retention: 10 years ? esd protection: 2,000v min * note : modules available with either t = 0 / 2-wire modes or 2-wire mode only. cryptomemory ? at88sc0204ca summary 5202es?crypt?08/09
2 at88sc0204ca 5202es?crypt?08/09 table 1. pin assignments figure 1. pin configuration 1 2 3 4 8 7 6 5 8-lead soic, pdi p nc nc nc gnd v cc nc scl sd a 8-lead tssop nc v cc 8 1 nc c n 7 2 nc k l c 6 3 gnd 5 4 sda 1 2 3 4 8 7 6 5 sda gnd clk v cc 8-lead ultra thin mini-map (mlp 2x3) bo t t o m vi ew nc nc nc nc 1. description the at88sc0204ca member of the cryptomemory ? family is a high-performance secure memory providing 2 kbit of user memory with advanced security and cryptograph ic features built in. the user memory is divided into four 64-byte zones, each of which may be individually set with different security access rights or effectively combined together to provide space for 1 to 4 data files. the at88sc0204ca f eatures an enhanced command set that allows direct communication with microcontroller hardware 2-wire interface thereby allowing for faster firm ware development with reduced code space requirements. pad description iso module twi module ?soic, pdip? tssop mini-map v cc supply voltage c1 c1 8 8 4 gnd ground c5 c5 4 1 5 scl/clk serial clock input c3 c3 6 6 2 sda/io serial da ta input/output c7 c7 5 3 7 rst reset input c2 nc nc nc nc twi smart card module v cc =c1 nc =c2 scl/clk=c3 nc=c4 c5=gnd c6=nc c7=s d a /io c8=nc iso smart card module v cc =c1 rst=c2 scl/clk=c3 nc=c4 c5=gnd c6=nc c7=s d a /io c8=nc
at88sc0204ca 3 5202es?crypt?08/09 2. smart card applications the at88sc0204ca provides high security, low cost, and ease of implementation without the need for a microprocessor operating system. the embedded cryptograp hic engine provides for dynamic, symmetric-mutual authentication between the device and host, as well as per forming stream encryption for all data and passwords exchanged between the device and host. up to four unique key sets may be used for these operations. the at88sc0204ca offers the ability to communicate with virtual ly any smart card reader using the asynchronous t = 0 protocol (gemplus patent) defined in iso 7816-3. 3. embedded applications through dynamic, symmetric-mutual authentication, data encryption, and the use of cryptographic message authentication codes (mac), the at88sc02 04ca provides a secure place for storage of sensitive information within a system. with its tamper detection circuits, this information remains safe even under attack. a 2-wire serial interface running at speeds up to 1.0 mhz provides fast and effici ent communications with up to 15 individually addressable devices. the at88sc0204ca is available in industry standard 8-lead packages with the same familiar pin configuration as at24cxxx serial eeprom devices. note : does not apply to either the tsso p or the ultra thin mini-map pinouts. figure 2. block diagram random generator authentication, encryption and certification unit eeprom answer to reset data transfer password verification reset block asynchronous iso interface synchronous interface power management v cc gnd scl/clk sda/io rst
4 at88sc0204ca 5202es?crypt?08/09 4. connection diagram figure 3. connection diagram 2.7v - 5.5v 2.7v - 3.6v sda scl microprocessor cryptomemory 5. pin descriptions 5.1. supply voltage (v cc ) the v cc input is a 2.7v to 3.6v posit ive voltage supplied by the host. 5.2. clock (scl/clk) when using the asynchronous t = 0 protocol, the clk (scl) input provides the device with a carrier frequency f . the nominal length of one bit emitted on i/o is defined as an ?elementary time unit ? (etu) and is equal to 372/ f . when using the synchronous protocol, data clocking is done on the positive edge of the clock when writing to the device and on the negative edge of the cl ock when reading from the device. 5.3. reset (rst) the at88sc0204ca provides an iso 7816-3 compliant asynchronous answer-to-reset (atr) sequence. upon activation of the reset sequence, the device outputs bytes cont ained in the 64-bit answer-to-reset register. an internal pull-up on the rst input pad allows the device to oper ate in synchronous mode without bonding rst. the at88sc0204ca does not support an answer-to-reset s equence in the synchronous mode of operation. 5.4. serial data (sda/io) the sda/io pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wired with any number of other open-drain or open-collector devices. an exter nal pull-up resistor should be connected between sda/io and v cc . the value of this resistor and t he system capacitance loading the sda/io bus will determine the rise time of sda/io. this rise time will determine the maximum frequ ency during read operat ions. low value pull- up resistors will allow higher frequenc y operations while drawing higher average powe r supply current. sda/io information applies to both asynchronous and synchronous protocols.
at88sc0204ca 5 5202es?crypt?08/09 6. *absolute maximum ratings operating temperature............................. ? 40c to +85c storage temperature ............................ ? 65c to + 150c voltage on any pin with respect to ground ....................... ? 0.7 to v cc +0.7v maximum operating voltage.......................................4.0v dc output current ..................................................5.0 ma * notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other c ondition beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. table 2. dc characteristics applicable over recommended operating range from v cc = +2.7 to 3.6v, t ac = -40 c to +85 c (unless otherwise noted) symbol parameter test conditions min typ max units v cc (1) supply voltage 2.7 3.6 v i cc supply current async read at 3.57mhz 5 ma i cc supply current async write at 3.57mhz 5 ma i cc supply current synch read at 1mhz 5 ma i cc supply current synch write at 1mhz 5 ma i sb standby current v in = v cc or gnd 100 a v il sda/io input low voltage 0 v cc x 0.2 v v il clk input low voltage 0 v cc x 0.2 v v il rst input low voltage 0 v cc x 0.2 v v ih (1) sda/io input high voltage v cc x 0.7 5.5 v v ih (1) scl/clk input high voltage v cc x 0.7 5.5 v v ih (1) rst input high voltage v cc x 0.7 5.5 v i il sda/io input low current 0 < v il < v cc x 0.15 15 a i il scl/clk input low current 0 < v il < v cc x 0.15 15 a i il rst input low current 0 < v il < v cc x 0.15 50 a i ih sda/io input high current v cc x 0.7 < v ih < v cc 20 a i ih scl/clk input high current v cc x 0.7 < v ih < v cc 100 a i ih rst input high current v cc x 0.7 < v ih < v cc 150 a v oh sda/io output high voltage 20k ohm external pull-up v cc x 0.7 v cc v v ol sda/io output low voltage i ol = 1ma 0 v cc x 0.15 v i oh sda/io output high current v oh 20 a i ol sda/io output low current v ol 10 ma
6 at88sc0204ca 5202es?crypt?08/09 note : 1. to prevent latch up conditions from o ccurring during power up of the at88sc0204ca, v cc must be turned on before applying v ih . for powering down, v ih must be removed before turning v cc off. table 3. ac characteristics applicable over recommended operating range from v cc = +2.7 to 3.6v, t ac = -40 c to +85 c, cl = 30pf (unless otherwise noted) symbol parameter min max units f clk async clock frequency 1 4 mhz f clk synch clock frequency 0 1 mhz clock duty cycle 40 60 % t r ?rise time - sda/io, rst? 1 s t f ?fall time - sda/io, rst? 1 s t r rise time - scl/clk 9% x period s t f fall time - scl/clk 9% x period s t aa clock low to data out valid 250 ns t hd.sta start hold time 200 ns t su.sta start set-up time 200 ns t hd.dat data in hold time 10 ns t su.dat data in set-up time 100 ns t su.sto stop set-up time 200 ns t dh data out hold time 20 ns t wr write cycle time 5 ms
at88sc0204ca 7 5202es?crypt?08/09 7. device operations fo r synchronous protocols 7.1. clock and data transitions the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 6 on page 8 ). data changes during scl high periods wi ll indicate a start or stop condition as defined below. 7.1.1. start condition a high-to-low transition of sda with scl high defines a start condition which must precede all commands (see figure 7 on page 8 ). 7.1.2. stop condition a low-to-high transition of sda with scl high defines a st op condition. after a read sequence, the stop condition will place the eeprom in a standby power mode (see figure 7 on page 8 ). 7.1.3. acknowledge all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknowledge that it has received each wo rd. this happens during the ninth clock cycle (see figure 8 on page 9 ). 7.2. memory reset after an interruption in communication due protocol errors, power loss or any reason, perform "acknowledge polling" to properly recover from the condition. acknowledge polling c onsists of sending a start condition followed by a valid cryptomemory command byte and determining if the device responded with an acknowledge. figure 4. bus time for 2-wire se rial communications. scl: serial clock, sda: serial data i/o scl sda in s da out t f t high t low t low t r t aa t dh t buf t su.sto t su.dat t hd.dat t hd.sta t su.sta
8 at88sc0204ca 5202es?crypt?08/09 figure 5. write cycle timing. scl: se rial clock, sda: serial data i/o t wr (1) stop condition start condition wordn ack 8th bit scl sda note : the write cycle time twr is the time from a valid stop condition of a write sequenc e to the end of the internal clear/write cycle. figure 6. data validity data change allowed data stable data stable sda scl figure 7. start and stop definitions sda scl start stop
at88sc0204ca 9 5202es?crypt?08/09 figure 8. output acknowledge start acknowledge scl data in data out 189
10 at88sc0204ca 5202es?crypt?08/09 8. device architecture 8.1. user zones the eeprom user memory is divided into 4 zones of 512 bits each. multiple zones allow for storage of different types of data or files in different zones. access to user zones is permitted only after meeting proper security requirements. these security requirements are user definable in the co nfiguration memory during devic e personalization. if the same security requirements are selected for multiple zones, th en these zones may effectively be accessed as one larger zone. figure 9. user zones zone $0 $1 $2 $3 $4 $5 $6 $7 $00 - 64 bytes - user 0 $38 $00 - 64 bytes - user 1 $38 $00 - 64 bytes - user 2 $38 $00 - 64 bytes - user 3 $38 9. control logic access to the user zones occur only through the control logic built into the device. this logic is configurable through access registers, key registers and keys programmed into the configuration memory dur ing device personalization. also implemented in the control logic is a cryptographic engine for performing the various higher-level security functions of the device.
at88sc0204ca 11 5202es?crypt?08/09 10. configuration memory the configuration memory cons ists of 2048 bits of eeprom memory used for storage of passwords, keys, codes, and also used for definition of security access rights for the us er zones. access rights to t he configuration memory are defined in the control logic and are not alterable by the user after completion of personalization. figure 10. configuration memory $0 $1 $2 $3 $4 $5 $6 $7 $00 answer to reset $08 fab code mtz card manufacturer code identifitcation $10 lot history code read only $18 dcr identification number nc $20 ar0 pr0 ar1 pr1 ar2 pr2 ar3 pr3 $28 $30 $38 reserved $40 $48 issuer code access control $50 $58 $60 $68 $70 $78 $80 $88 for authentication and encryption use cryptography $90 $98 $a0 $a8 for authentication and encryption use secret $b0 pac write 0 pac read 0 $b8 pac write 1 pac read 1 $c0 pac write 2 pac read 2 $c8 pac write 3 pac read 3 $d0 pac write 4 pac read 4 $d8 pac write 5 pac read 5 $e0 pac write 6 pac read 6 $e8 pac write 7 pac read 7 password $f0 $f8 reserved forbidden 10.1. security fuses there are three fuses on the device that must be blown du ring the device personalization process. each fuse locks certain portions of the c onfiguration zone as otp (one-time progra mmable) memory. fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuse s may be performed at one final step.
12 at88sc0204ca 5202es?crypt?08/09 11. communication security modes communications between the device and host operate in th ree basic modes. standard mode is the default mode for the device after power-up. authentication mode is activated by a successful aut hentication sequence. encryption mode is activated by a successful encryption acti vation following a successful authentication. table 4. communication security modes (1) mode configuration data user data passwords data integrity check standard clear clear clear mdc (1) authentication clear clear encrypted mac (1) encryption clear encrypted encrypted mac (1) note : 1. configuration data include viewable areas of the configuration z one except the passwords: mdc: modification detection code. mac: message authentication code. 12. security options 12.1. anti-tearing in the event of a power loss during a write cycle, the integrit y of the device?s stored data is recoverable. this function is optional: the host may choose to activate the anti-tearing f unction, depending on application requirements. when anti- tearing is active, write commands take longer to execute, si nce more write cycles are required to complete them, and data is limited to a maximum of ei ght bytes for each write request. data is written first into a buffer z one in eeprom instead of the intended de stination address, but with the same access conditions. the data is then written in the required location. if this second write cycle is interrupted due to a power loss, the device will automaticall y recover the data from the system buffer zone at the next power-up. non- volatile buffering of the data is done automatically by the device. during power-up in applications using anti-tearing, the host is required to perform ack polling in the event that the device needs to carry out the data recovery process. 12.2. write lock if a user zone is configured in the writ e lock mode, the lowest address byte of an 8-byte page constitutes a write access byte for the bytes of that page. for example, the write lock byte at $080 controls the bytes from $081 to $087. figure 11. write lock example address $0 $1 $2 $3 $4 $5 $6 $7 $080 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx locked locked locked the write-lock byte itself may be locked by writing its least significant (rightmost) bit to ?0?. moreover, when write lock mode is activated, the write lock byte can only be programm ed ? that is, bits written to ?0? cannot return to ?1?. in the write lock configurati on, write operations are limited to writing only one byte at a time. attempts to write more than one byte will result in writing of just the first byte into the device.
at88sc0204ca 13 5202es?crypt?08/09 12.3. password verification passwords may be used to protect read and/or write access of any user zone. when a valid password is presented, it is memorized and active until power is turned off, unless a new password is presented or rst becomes active. there are eight password sets that may be used to pr otect any user zone. only one password is active at a time. presenting the correct write password also grants read access privileges. 12.4. authentication protocol the access to a user zone may be protected by an authentica tion protocol. any one of four keys may be selected to use with a user zone. authentication success is memorized and active as long as the chip is powered, un less a new authentication is initialized or rst becomes active. if the new authentication request is not validated, the card loses its previous authentication which must be presented again to gain access. only the latest request is memorized. figure 12. password and aut hentication operations device (card) card number verify a compute challenge b challenge b verify rpw data checksum (cs) verify wpw verify cs write data host (reader) compute challenge a challenge a verify b read password (rpw) verify cs write password (wpw) data cs authentication read access write access note : authentication and password verification may be a ttempted at any time and in any order. exceeding corresponding authentication or password attempts tria l limit renders subsequent aut hentication or password verification atte mpts futile.
14 at88sc0204ca 5202es?crypt?08/09 12.5. cryptographic message authentication codes at88sc0204ca implements a data validity check function in the standard, authentication or encryption modes of operation. in the standard mode, data validity che ck is done through a modification detection code (mdc), in which the host may read an mdc from the device in order to veri fy that the data sent was received correctly. in authentication and encryption modes, the data validity check becomes more powerf ul since it provides a bidirectional data integrity check and data origin authentication capability in the form of a message authentication codes (mac). only the host/device that carried out a vali d authentication is capable of computing a valid mac. while operating in the authentication or encryption modes, the use of mac is requi red. for an ingoing command, if the device calculates a mac different from the mac transmitted by the host, not only is the command abandoned but the security privilege is revoked. a new authentication and/or encryption ac tivation will be required to reactivate the mac. 12.6. encryption the data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure data confidentiality. the issuer may choose to require encryption for a user zo ne by settings made in the configuration memory. any one of four keys may be selected for use with a user zone. in this case, activation of the encryption mode is required in order to read/write data in the zone and only encrypted data will be transmitted. even if not requi red, the host may still elect to activate encryption provided the proper keys are known. 12.7. supervisor mode enabling this feature allows the holder of one specific password to gain full access to all eight password sets, including the ability to change passwords. 12.8. modify forbidden no write access is allowed in a user zone protected with th is feature at any time. the user zone must be written during device personalization prior to blowing the security fuses. 12.9. program only for a user zones protected by this f eature, data can only be programmed (bits c hange from a ?1? to a ?0?), but not erased (bits change from a ?0? to a ?1?).
at88sc0204ca 15 5202es?crypt?08/09 13. protocol selection the at88sc0204ca supports two di fferent communication protocols. smartcard applications: smartcard applications use iso 7816-b protocol in asynchronous t = 0 mode for compatibility and interoperability with industry standard smartcard readers. embedded applications: a 2-wire serial interface provides fast and efficient co nnectivity with other logic devices or microcontrollers. the power-up sequence determines establishes the communication protocol for use within t hat power cycle. protocol selection is allowed only during power-up. 13.2. synchronous 2-wire serial interface the synchronous mode is the default mode after power up. this is due to the presence of an internal pull-up on rst. for embedded applications using cryptomemory in standard plas tic packages, this is the only available communication protocol. power-up v cc , rst goes high also. after stable v cc , scl(clk) and sda(i/o) may be driven. once synchronous mode has been selected, it is not possible to switch to asynchronous mode without first powering off the device figure 13. synchronous 2-wire protocol v cc i/o-sda rst clk-scl 1 2 3 45 note : five clock pulses must be sent before the first command is issued.
16 at88sc0204ca 5202es?crypt?08/09 13.3. asynchronous t = 0 protocol this power-up sequence complies to iso 7816-3 for a cold reset in smart card applications. v cc goes high; rst, i/o (sda) and clk (scl) are low. set i/o (sda) in receive mode. provide a clock signal to clk (scl). rst goes high after 400 clock cycles. the device will respo nd with a 64-bit atr code, including historical byte s to indicate the memory density within the cryptomemory family. once asynchronous mode has been selected, it is not possible to switch to synchronous mode without first powering off the device. figure 14. asynchronous t = 0 protocol (gemplus patent) v cc i/o-sda rst clk-scl at r 14. initial device programming enabling the security features of cryptomemory requires prior personalization. personalization entails setting up of desired access rights by zones, passwords and key values, programming these values into the configuration memory with verification using simple write and read commands, and then blowing fuses to lock this information in place. gaining access to the configuration memory requires successf ul presentation of a secure (or transport) code. the initial signature of the secure (transport) code for the at88sc0204ca device is $e5 47 47. this is the same as the write 7 password. the user may elect to change the signature of the secure code anytime after successful presentation. after writing and verifying data in the configuration memory, the security fuses must be blown to lock this information in the device. for additional information on personalizing cryptomemory, please see the application notes programming cryptomemory for embedded applications and in itializing cryptomemory for smart card applications from the product page at www.atmel.com/products/securemem .
at88sc0204ca 17 5202es?crypt?08/09 15. ordering information table 5. ordering information ordering code package voltage range temperature range at88sc0204ca-mj at88sc0204ca-mp AT88SC0204CA-MJTG at88sc0204ca-mptg m2 ? j module - iso m2 ? p module - iso m2 ? j module -twi m2 ? p module -twi 2.7v?3.6v commercial (0c to 70c) at88sc0204ca-pu at88sc0204ca-su at88sc0204ca-th at88sc0204ca-y6h-t 8p3 8s1 8a2 8y6 2.7v?3.6v green compliant (exceeds rohs)/industrial ( ? 40c to 85c) at88sc0204ca-wi 7 mil wafer 2.7v?3.6v industrial ( ? 40c to 85c) table 6. ordering information package type (1) (2) description m2 ? j module : iso or twi m2 iso 7816 smart card module m2 ? p module: iso or twi m2 iso 7816 smart card module with atmel ? logo 8p3 8-lead, 0.300? wide, plas tic dual inline package (pdip) 8s1 8-lead, 0.150? wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 4.4mm body, plastic thin shrink small outline package (tssop) 8y6 8-lead, 2.0 x 3.0mm body, 0.50mm pitch, ult ra thin mini-map, dual no lead package (dfn), (mlp 2x3) note : 1. formal drawings may be obtained from an atmel sales office. 2 . both the j and p module packages are used for either iso (t=0 / 2-wire mode) or twi (2-wire mode only).
18 at88sc0204ca 5202es?crypt?08/09 16. package information ordering code: mj or mjtg ordering code: mp or mptg module size: m2 dimension*: 12.6 x 11.4 [mm] glob top: round - ? 8.5 [mm] thickness: 0.58 [mm] pitch: 14.25 mm module size: m2 dimension*: 12.6 x 11.4 [mm] glob top: square - 8.8 x 8.8 [mm] thickness: 0.58 [mm] pitch: 14.25 mm * note : the module dimensions listed refer to the dimensi ons of the exposed metal c ontact area. the actual dimensions of the module after excise or punching fr om the carrier tape are generally 0.4 mm greater in both directions (i.e., a punched m2 module will yield 13.0 x 11.8 mm).
at88sc0204ca 19 5202es?crypt?08/09 17. ordering code: su 17.1. 8-lead soic note: common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0 ? ?8 ? top view end view side view e d a a1 n e 1 c e1 l drawing no. 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 rev. 8s1 c 3/17/05 title 8s1, 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) b
20 at88sc0204ca 5202es?crypt?08/09 18. ordering code: pu 18.1. 8-lead pdip common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view drawing no. 2325 orchard parkway san jose, ca 95131 r rev. 8p3 b 01/09/02 title 8p3, 8-lead, 0.300" wide body, plastic dual in-line package (pdip) a a2 b b2 b3 c d d1 e e1 e ea l ? 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.115 ? 0.130 0.018 0.060 0.039 0.010 0.365 ? 0.310 0.250 0.130 0.210 0.195 0.022 0.070 0.045 0.014 0.400 ? 0.325 0.280 0.150 2 5 6 6 3 3 4 3 4 2 0.100 bsc 0.300 bsc notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba, for additional information. 2. dimensions a and l are measured with the pa ckage seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or prot rusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads const rained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar prot rusions. dambar protrusions shall not exceed 0.010 (0.25 mm).
at88sc0204ca 21 5202es?crypt?08/09 19. ordering code: th 19.1. 8-lead tssop common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a??1.20 a2 0.80 1.00 1.05 b0.19?0.304 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 re3 side view a2 a d b end view top view l l1 1 2 3 e1 n pin 1 indicator this corner e e drawing no. rev. 8a2 c 10/29/08 title notes: 1. this drawing is for general information only. refer to jedec d rawing mo-153, variation aa, for proper dimension s, tolerances, datums, etc. 2. dimension d does not include mold flash, prot rusions or gate burrs. mold flash, prot rusions and gate burrs shall not exceed 0.15 mm (0.006 in) per sid e. 3. dimension e1 does not include inter-lead flash or prot rusions. inter-lead flash and prot rusions shall not exceed 0.25 mm (0.010 in) per sid e. 4. dimension b does not include dambar prot rusion. allowable dambar prot rusion shall be 0.08 mm total in excess of the b dimension at maxi mum mate rial condition . dambar cannot be located on the l ower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm . 5. dimension d and e1 to be dete rmined at datum plane h . package drawing contact: 8a2, 8-lead, 4.4mm body, plastic thin shrink small outline package (tssop) tnr gpc packagedrawings@atmel.com
22 at88sc0204ca 5202es?crypt?08/09 20. ordering code: y6h-t 20.1. 8-lead ultra thin mini-map drawing no. rev. 8y6 e 11/21/08 title package drawing contact: 8y6, 8-lead , 2.0x3.0 mm body, 0.50 mm pitch, ultrathin mini-map, dual no lead package (sawn)(udfn) ynz gpc a2 pin 1 index area a3 d e b (8x) pin 1 id a1 a l (8x) e (6x) 1.50 ref. d2 e2 common dimensions (unit of measure = mm) symbol min nom max note d 2.00 bsc e 3.00 bsc d2 1.40 1.50 1.60 e2 - - 1.40 a - - 0.60 a1 0.0 0.02 0.05 a2 - - 0.55 a3 0.20 ref l 0.20 0.30 0.40 e 0.50 bsc b 0.20 0.25 0.30 2 notes: 1. this drawing is for general information only. refer to jedec drawing mo-229, for proper dimensions, tolerances, datums, etc. 2. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 3. soldering the large thermal pad is optional, but not recommended. no electrical connection is accomplished to the device through this pad, so if soldered it should be tied to ground packagedrawings@atmel.com
at88sc0204ca 23 5202es?crypt?08/09 appendix a. revision history doc. rev. date comments 5202ds 08/2009 minor edits and twi module updates 5202ds 07/2009 minor updates to package drawing information and ordering information. 5202cs 05/2009 added mini-map column to table 1-1 and mini-map pin-out drawing. 5202bs 02/2009 connection diagram inserted; dc characteristics table updated. 5202as 07/2008 initial document release.
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