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1. general description the lpc1110/11/12/13/14 are a arm cortex-m0 based, low-cost 32-bit mcu family, designed for 8/16-bit microcontroller applications , offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. the lpc1110/11/12/13/14 operate at cpu frequencies of up to 50 mhz. the peripheral complement of the lpc1110/11/12/13/14 includes up to 32 kb of flash memory, up to 8 kb of data memory, one fast-mode plus i 2 c-bus interface, one rs-485/eia-485 uart, up to two spi interfac es with ssp features, fo ur general purpose counter/timers, a 10-bit adc, and up to 42 general purpose i/o pins. remark: the lpc1110/11/12/13/14 series consis ts of the lpc1100 series (parts lpc111x/101/201/301) and the lpc1100l seri es (parts lpc111x/002/102/202/302). the lpc1100l series includes the power profiles, a windowed watchdog timer, and a configurable open-drain mode. 2. features and benefits ? system: ? arm cortex-m0 processor, running at frequencies of up to 50 mhz. ? arm cortex-m0 built-in nested vectored interrupt controller (nvic). ? serial wire debug. ? system tick timer. ? memory: ? 32 kb (lpc1114), 24 kb (lpc1113), 16 kb (lpc1112), 8 kb (lpc1111),or 4 kb (lpc1110) on-chip flash programming memory. ? 8 kb, 4 kb, 2 kb, or 1 kb sram. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? digital peripherals: ? up to 42 general purpose i/o (gpio) pi ns with configurable pull-up/pull-down resistors. in addition, a configurable open-drain mode is supported on the lpc111x/002/102/202/302. ? gpio pins can be used as edge and level sensitive interrupt sources. ? high-current output driver (20 ma) on one pin. ? high-current sink drivers (20 ma) on two i 2 c-bus pins in fast-mode plus (not on lpc1112fdh20/102). lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontrol ler; up to 32 kb flash and 8 kb sram rev. 6 ? 2 november 2011 product data sheet
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 2 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller ? four general purpose counter/timers with up to four capture inputs and up to 13 match outputs. ? programmable watchdog timer (wdt). ? programmable windowed wdt on lpc111x/002/102/202/302 only. ? analog peripherals: ? 10-bit adc with input multip lexing among 5, 6, or 8 pins depending on package size. ? serial interfaces: ? uart with fractional baud rate generation, internal fifo, and rs-485 support. ? two spi controllers with ssp features and with fifo and multi-protocol capabilities (second spi on lqfp48 package only). ? i 2 c-bus interface supporting full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s with multiple address recognition and monitor mode (not on lpc1112fdh20/102). ? clock generation: ? 12 mhz internal rc oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? programmable watchdog oscillator with a frequency range of 7.8 khz to 1.8 mhz. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from th e system oscillator or the internal rc oscillator. ? clock output function with divider that ca n reflect the system oscillator clock, irc clock, cpu clock, and the watchdog clock. ? power control: ? integrated pmu (power management unit) to minimize power consumption during sleep, deep-sleep, and deep power-down modes. ? power profiles residing in boot rom allowing to optimize performance and minimize power consumption for any given application through one simple function call. (lpc1100l series, on lpc111x/002/102/202/302 only.) ? three reduced power modes: sleep, deep-sleep, and deep power-down. ? processor wake-up from deep-sleep mode via a dedicated start logic using up to 13 of the functional pins. ? power-on reset (por). ? brownout detect with four separate thre sholds for interrup t and forced reset. ? unique device serial number for identification. ? single power supply (1.8 v to 3.6 v). ? available as lqfp48 package and hvqfn33 package (lpc1100 and lpc1100l series). ? lpc1100l series available as tssop28 package, dip28 package, tssop20 package, and so20 package. 3. applications ? emetering ? lighting ? alarm systems ? white goods
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 3 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 4. ordering information table 1. ordering information type number package name description version so20, tssop20, tssop2 8, and dip28 packages LPC1110FD20 so20 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 lpc1111fdh20/002 tssop20 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 lpc1112fd20/102 so20 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 lpc1112fdh20/102 tssop20 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 lpc1112fdh28/102 tssop28 tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 lpc1114fdh28/102 tssop28 tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 lpc1114fn28/102 dip28 dip28: plastic dual in-line package; 28 leads (600 mil) sot117-1 hvqfn33 and lqfp48 packages lpc1111fhn33/101 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1111fhn33/102 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1111fhn33/201 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1111fhn33/202 hvqfn33 hvqfn: plastic thermal en hanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn33/101 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn33/102 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn33/201 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhn33/202 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1112fhi33/202 hvqfn33 hvqfn: plastic therma l enhanced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc1113fhn33/201 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1113fhn33/202 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a l pc1113fhn33/301 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1113fhn33/302 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhn33/201 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhn33/202 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 4 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 4.1 ordering options lpc1114fhn33/301 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhn33/302 hvqfn33 hvqfn: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1114fhi33/302 hvqfn33 hvqfn: plastic therma l enhanced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc1113fbd48/301 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1113fbd48/302 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1114fbd48/301 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1114fbd48/302 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 table 1. ordering information ?continued type number package name description version table 2. ordering options type number series flash total sram power profiles uart rs-485 i 2 c/ fast+ spi adc channels gpio package lpc1110 LPC1110FD20 lpc1100l 4 kb 1 kb yes 1 1 1 5 16 so20 lpc1111 lpc1111fdh20/002 lpc1100l 8 kb 2 kb yes 1 1 1 5 16 tssop20 lpc1111fhn33/101 lpc1100 8 kb 2 kb no 1 1 1 8 28 hvqfn33 lpc1111fhn33/102 lpc1100l 8 kb 2 kb yes 1 1 1 8 28 hvqfn33 lpc1111fhn33/201 lpc1100 8 kb 4 kb no 1 1 1 8 28 hvqfn33 lpc1111fhn33/202 lpc1100l 8 kb 4 kb yes 1 1 1 8 28 hvqfn33 lpc1112 lpc1112fd20/102 lpc1100l 16 kb 4 kb yes 1 1 1 5 16 so20 lpc1112fdh20/102 lpc1100l 16 kb 4 kb yes 1 - 1 5 14 tssop20 lpc1112fdh28/102 lpc1100l 16 kb 4 kb yes 1 1 1 6 22 tssop28 lpc1112fhn33/101 lpc1100 16 kb 2 kb no 1 1 1 8 28 hvqfn33 lpc1112fhn33/102 lpc1100l 16 kb 2 kb yes 1 1 1 8 28 hvqfn33 lpc1112fhn33/201 lpc1100 16 kb 4 kb no 1 1 1 8 28 hvqfn33 lpc1112fhn33/202 lpc1100l 16 kb 4 kb yes 1 1 1 8 28 hvqfn33 lpc1112fhi33/202 lpc1100l 16 kb 4 kb yes 1 1 1 8 28 hvqfn33 lpc1113 lpc1113fhn33/201 lpc1100 24 kb 4 kb no 1 1 1 8 28 hvqfn33 lpc1113fhn33/202 lpc1100l 24 kb 4 kb yes 1 1 1 8 28 hvqfn33 lpc1113fhn33/301 lpc1100 24 kb 8 kb no 1 1 1 8 28 hvqfn33 lpc1113fhn33/302 lpc1100l 24 kb 8 kb yes 1 1 1 8 28 hvqfn33
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 5 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller lpc1113fbd48/301 lpc1100 24 kb 8 kb no 1 1 2 8 42 lqfp48 lpc1113fbd48/302 lpc1100l 24 kb 8 kb yes 1 1 2 8 42 lqfp48 lpc1114 lpc1114fdh28/102 lpc1100l 32 kb 4 kb yes 1 1 1 6 22 tssop28 lpc1114fn28/102 lpc1100l 32 kb 4 kb yes 1 1 1 6 22 dip28 lpc1114fhn33/201 lpc1100 32 kb 4 kb no 1 1 1 8 28 hvqfn33 lpc1114fhn33/202 lpc1100l 32 kb 4 kb yes 1 1 1 8 28 hvqfn33 lpc1114fhn33/301 lpc1100 32 kb 8 kb no 1 1 1 8 28 hvqfn33 lpc1114fhn33/302 lpc1100l 32 kb 8 kb yes 1 1 1 8 28 hvqfn33 lpc1114fhi33/302 lpc1100l 32 kb 8 kb yes 1 1 1 8 28 hvqfn33 lpc1114fbd48/301 lpc1100 32 kb 8 kb no 1 1 2 8 42 lqfp48 lpc1114fbd48/302 lpc1100l 32 kb 8 kb yes 1 1 2 8 42 lqfp48 table 2. ordering options type number series flash total sram power profiles uart rs-485 i 2 c/ fast+ spi adc channels gpio package
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 6 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 5. block diagram (1) lqfp48 packages only. (2) not on lpc1112fdh20/102. (3) all pins available on lqfp48 and hvqfn33 packages. ct16b1_mat1 not av ailable on tssop28/dip28 packages. ct32b1_mat3, ct16b1_cap0, ct16b1_mat[1:0], ct32b 0_cap0 not available on tssop20/so20 packages. (4) ad[7:0] available on lqfp48 and hvqfn33 packages. ad[5:0] available on tssop 28/dip28 packages. ad[4:0] available on tssop20/so20 packages. (5) all pins available on lq fp48 packages. rxd, txd, dtr , cts , rts available on hvqfn 33 packages. rxd, txd, cts , rts available on tssop28/dip28 packages. rxd, txd available on t ssop20/so20 packages. fig 1. lpc1110/11/12/13/14 block diagram sram 1/2/4/8 kb arm cortex-m0 test/debug interface flash 4/8/16/24/32 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions xtalin xtalout reset clocks and controls swd lpc1110/11/12/13/14 002aae696 slave slave slave slave rom slave ahb-lite bus gpio ports pio0/1/2/3 clkout irc por spi0 10-bit adc uart 32-bit counter/timer 0 i 2 c-bus (2) wdt ioconfig ct32b0_mat[3:0] (3) ad[7:0] (4) ct32b0_cap0 (3) sda scl rxd txd dtr, dsr, cts (5) , dcd, ri, rts (5) system control pmu 32-bit counter/timer 1 ct32b1_mat[3:0] (3) ct32b1_cap0 (3) 16-bit counter/timer 1 ct16b1_mat[1:0] (3) ct16b1_cap0 (3) 16-bit counter/timer 0 ct16b0_mat[2:0] (3) ct16b0_cap0 (3) sck0, ssel0 miso0, mosi0 sck1, ssel1 miso1, mosi1 spi1 (1) system bus
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 7 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 6. pinning information 6.1 pinning table 3. pin description overview part pin description table pinning diagram LPC1110FD20 ta b l e 4 figure 4 lpc1111fdh20/002 ta b l e 4 figure 5 lpc1112fd20/102 ta b l e 4 figure 6 lpc1112fdh20/102 ta b l e 5 figure 5 lpc1112fdh28/102 ta b l e 6 figure 7 lpc1114fdh28/102 ta b l e 6 figure 8 lpc1114fn28/102 ta b l e 6 figure 8 lpc1111fhn33/101 ta b l e 8 figure 3 lpc1111fhn33/102 ta b l e 8 figure 3 lpc1111fhn33/201 ta b l e 8 figure 3 lpc1111fhn33/202 ta b l e 8 figure 3 lpc1112fhn33/101 ta b l e 8 figure 3 lpc1112fhn33/102 ta b l e 8 figure 3 lpc1112fhn33/201 ta b l e 8 figure 3 lpc1112fhn33/202 ta b l e 8 figure 3 lpc1112fhi33/202 ta b l e 8 figure 3 lpc1113fhn33/201 ta b l e 8 figure 3 lpc1113fhn33/202 ta b l e 8 figure 3 lpc1113fhn33/301 ta b l e 8 figure 3 lpc1113fhn33/302 ta b l e 8 figure 3 lpc1114fhn33/201 ta b l e 8 figure 3 lpc1114fhn33/202 ta b l e 8 figure 3 lpc1114fhn33/301 ta b l e 8 figure 3 lpc1114fhn33/302 ta b l e 8 figure 3 lpc1114fhi33/302 ta b l e 8 figure 3 lpc1113fbd48/301 ta b l e 7 figure 2 lpc1113fbd48/302 ta b l e 7 figure 2 lpc1114fbd48/301 ta b l e 7 figure 2 lpc1114fbd48/302 ta b l e 7 figure 2
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 8 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 2. pin configuration lqfp48 package lpc1113fbd48/301 lpc1113fbd48/302 lpc1114fbd48/301 lpc1114fbd48/302 pio2_6 pio3_0/dtr pio2_0/dtr/ssel1 r/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 v ss r/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck0 xtalout pio1_10/ad6/ct16b1_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio2_7 pio2_2/dcd/miso1 pio2_8 pio2_10 pio2_1/dsr/sck1 pio3_3/ri pio0_3 pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 pio1_9/ct16b1_mat0 v dd pio3_4 pio3_2/dcd pio2_4 pio1_11/ad7 pio2_5 v ss pio3_5 pio1_4/ad5/ct32b1_mat3/wakeup pio0_6/sck0 swdio/pio1_3/ad4/ct32b1_mat2 pio0_7/cts pio2_9 pio2_3/ri/mosi1 pio3_1/dsr 002aae697 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 9 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 3. pin configuration hvqfn33 7x7 and 5x5 packages 002aae698 transparent top view pio0_8/miso0/ct16b0_mat0 pio1_8/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio1_10/ad6/ct16b1_mat1 xtalin r/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio2_0/dtr r/pio1_2/ad3/ct32b1_mat1 pio0_3 pio0_4/scl pio0_5/sda pio1_9/ct16b1_mat0 pio3_4 pio3_5 pio0_6/sck0 pio0_7/cts pio1_7/txd/ct32b0_mat1 pio1_6/rxd/ct32b0_mat0 pio1_5/rts/ct32b0_cap0 v dd pio3_2 pio1_11/ad7 pio1_4/ad5/ct32b1_mat3/wakeup swdio/pio1_3/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss fig 4. pin configuration so20 package LPC1110FD20 lpc1112fd20/ 102 pio0_8/miso0/ct16b0_mat0 pio0_4/scl pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 swclk/pio0_10/sck0/ct16b0_mat2 pio0_1/clkout/ct32b0_mat2 r/pio0_11/ad0/ct32b0_mat3 reset/pio0_0 pio0_5/sda v ss pio0_6/sck0 v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_7/txd/ct32b0_mat1 swdio/pio1_3/ad4/ct32b1_mat2 pio1_6/rxd/ct32b0_mat0 002aag595 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 10 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 5. pin configuration tssop20 package with i 2 c-bus pins lpc1111fdh20/002 pio0_8/miso0/ct16b0_mat0 pio0_4/scl pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 swclk/pio0_10/sck0/ct16b0_mat2 pio0_1/clkout/ct32b0_mat2 r/pio0_11/ad0/ct32b0_mat3 reset/pio0_0 pio0_5/sda v ss pio0_6/sck0 v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_7/txd/ct32b0_mat1 swdio/pio1_3/ad4/ct32b1_mat2 pio1_6/rxd/ct32b0_mat0 002aag596 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 fig 6. pin configuration tssop20 package with v dda and v ssa pins lpc1112fdh20/102 pio0_8/miso0/ct16b0_mat0 pio0_3 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 swclk/pio0_10/sck0/ct16b0_mat2 pio0_1/clkout/ct32b0_mat2 r/pio0_11/ad0/ct32b0_mat3 reset/pio0_0 v dda v ss v ssa v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_7/txd/ct32b0_mat1 swdio/pio1_3/ad4/ct32b1_mat2 pio1_6/rxd/ct32b0_mat0 002aag597 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 fig 7. pin configuration tssop28 package lpc1112fdh28/102 lpc1114fdh28/102 pio0_8/miso0/ct16b0_mat0 pio0_7/cts pio0_9/mosi0/ct16b0_mat1 pio0_4/scl swclk/pio0_10/sck0/ct16b0_mat2 pio0_3 r/pio0_11/ad0/ct32b0_mat3 pio0_2/ssel0/ct16b0_cap0 pio0_5/sda pio0_1/clkout/ct32b0_mat2 pio0_6/sck0 reset/pio0_0 v dda v ss v ssa v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_9/ct16b1_mat0 swdio/pio1_3/ad4/ct32b1_mat2 pio1_8/ct16b1_cap0 pio1_4/ad5/ct32b1_mat3/wakeup pio1_7/txd/ct32b0_mat1 pio1_5/rts/ct32b0_cap0 pio1_6/rxd/ct32b0_mat0 002aag598 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 11 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 8. pin configuration dip28 package lpc1114fn28/ 102 pio0_8/miso0/ct16b0_mat0 pio0_7/cts pio0_9/mosi0/ct16b0_mat1 pio0_4/scl swclk/pio0_10/sck0/ct16b0_mat2 pio0_3 r/pio0_11/ad0/ct32b0_mat3 pio0_2/ssel0/ct16b0_cap0 pio0_5/sda pio0_1/clkout/ct32b0_mat2 pio0_6/sck0 reset/pio0_0 v dda v ss v ssa v dd r/pio1_0/ad1/ct32b1_cap0 xtalin r/pio1_1/ad2/ct32b1_mat0 xtalout r/pio1_2/ad3/ct32b1_mat1 pio1_9/ct16b1_mat0 swdio/pio1_3/ad4/ct32b1_mat2 pio1_8/ct16b1_cap0 pio1_4/ad5/ct32b1_mat3/wakeup pio1_7/txd/ct32b0_mat1 pio1_5/rts/ct32b0_cap0 pio1_6/rxd/ct32b0_mat0 002aag599 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 12 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 6.2 pin description table 4. lpc1110/11/12 pin description ta ble (so20 and tssop20 package with i 2 c-bus pins) symbol pin so20/ tssop20 start logic input type reset state [1] description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected throug h the ioconfig register block. reset /pio0_0 17 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/o utput pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 18 [3] yes i/o i; pu pio0_1 ? general purpose digital inpu t/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 19 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_4/scl 20 [4] yes i/o i; ia pio0_4 ? general purpose digital inpu t/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 5 [4] yes i/o i; ia pio0_5 ? general purpose digital inpu t/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 6 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_8/miso0/ ct16b0_mat0 1 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 2 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 3 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 13 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled (pins pulled up to full v dd level ); ia = inactive, no pull-up/down enabled. r/pio0_11/ ad0/ct32b0_mat3 4 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_7 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected throug h the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 7 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 8 [5] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 9 [5] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 10 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_6/rxd/ ct32b0_mat0 11 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 12 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. v dd 15 - - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 14 [6] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 13 [6] - o - output from the oscillator amplifier. v ss 16 - - ground. table 4. lpc1110/11/12 pin description ta ble (so20 and tssop20 package with i 2 c-bus pins) ?continued symbol pin so20/ tssop20 start logic input type reset state [1] description
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 14 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [2] see figure 37 for the reset pad configuration. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an extern al pull-up resistor is required on this pin for the deep power-d own mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 36 ). [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 36 ). [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. table 5. lpc1112 pin description table (tssop20 with v dda and v ssa pins) symbol pin tssop20 start logic input type reset state [1] description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 17 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor ex ecution to begin at address 0. i/o - pio0_0 ? general purpose digital in put/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 18 [3] yes i/o i; pu pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 19 [3] yes i/o i; pu pio0_2 ? general purpose digi tal input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 20 [3] yes i/o i; pu pio0_3 ? general purpose digita l input/output pin. pio0_8/miso0/ ct16b0_mat0 1 [3] yes i/o i; pu pio0_8 ? general purpose digi tal input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 2 [3] yes i/o i; pu pio0_9 ? general purpose digi tal input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 3 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 15 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller r/pio0_11/ ad0/ct32b0_mat3 4 [4] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_7 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 7 [4] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digi tal input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 8 [4] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digi tal input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 9 [4] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digi tal input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 10 [4] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digi tal input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_6/rxd/ ct32b0_mat0 11 [3] no i/o i; pu pio1_6 ? general purpose digi tal input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 12 [3] no i/o i; pu pio1_7 ? general purpose digi tal input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. v dd 15 - i - 3.3 v supply voltage to the internal regulator and the external rail. v dda 5 - i - 3.3 v supply voltage to the adc. also used as the adc reference voltage. xtalin 14 [5] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. table 5. lpc1112 pin description table (tssop20 with v dda and v ssa pins) ?continued symbol pin tssop20 start logic input type reset state [1] description
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 16 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled (pins pulled up to full v dd level ); ia = inactive, no pull-up/down enabled. [2] see figure 37 for the reset pad configuration. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an extern al pull-up resistor is required on this pin for the deep power-d own mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 36 ). [4] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 36 ). [5] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. xtalout 13 [5] - o - output from the oscillator amplifier. v ss 16 - i - ground. v ssa 6 - i - analog ground. table 5. lpc1112 pin description table (tssop20 with v dda and v ssa pins) ?continued symbol pin tssop20 start logic input type reset state [1] description table 6. lpc1112/14 pin descriptio n table (tssop28 and dip28 packages) symbol pin tssop28/ dip28 start logic input type reset state [1] description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. th e operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 23 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 24 [3] yes i/o i; pu pio0_1 ? general purpose digital inpu t/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 25 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 26 [3] yes i/o i; pu pio0_3 ? general purpose digital input/output pin. pio0_4/scl 27 [4] yes i/o i; ia pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 17 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller pio0_5/sda 5 [4] yes i/o i; ia pio0_5 ? general purpose digital inpu t/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 6 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 28 [3] yes i/o i; pu pio0_7 ? general purpose digital inpu t/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 1 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 2 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 3 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 4 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_9 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. th e operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 9 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 10 [5] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. table 6. lpc1112/14 pin descriptio n table (tssop28 and dip28 packages) ?continued symbol pin tssop28/ dip28 start logic input type reset state [1] description
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 18 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller r/pio1_2/ ad3/ct32b1_mat1 11 [5] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 12 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 13 [5] no i/o i; pu pio1_4 ? general purpose digital input/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pul led high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 14 [3] no i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 15 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 16 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 17 [3] no i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0 18 [3] no i/o i; pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. v dd 21 - - 3.3 v supply voltage to the internal regulator and the external rail. v dda 7 - - - 3.3 v supply voltage to the adc. also used as the adc reference voltage. xtalin 20 [6] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 19 [6] - o - output from the oscillator amplifier. v ss 22 - - ground. v ssa 8 - - - analog ground. table 6. lpc1112/14 pin descriptio n table (tssop28 and dip28 packages) ?continued symbol pin tssop28/ dip28 start logic input type reset state [1] description
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 19 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled (pins pulled up to full v dd level ); ia = inactive, no pull-up/down enabled. [2] see figure 37 for the reset pad configuration. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an extern al pull-up resistor is required on this pin for the deep power-d own mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 36 ). [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 36 ). [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. table 7. lpc1113/14 pin description table (lqfp48 package) symbol pin start logic input type reset state [1] description pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function select ed through the ioconfig register block. reset /pio0_0 3 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peri pherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 4 [3] yes i/o i; pu pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 10 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 14 [3] yes i/o i; pu pio0_3 ? general purpose digital input/output pin. pio0_4/scl 15 [4] yes i/o i; ia pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 16 [4] yes i/o i; ia pio0_5 ? general purpose digital input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/ output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 22 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 23 [3] yes i/o i; pu pio0_7 ? general purpose digital input/output pin (high-current output driver). i- cts ? clear to send input for uart.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 20 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller pio0_8/miso0/ ct16b0_mat0 27 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 28 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 29 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 32 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_11 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function select ed through the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 33 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 34 [5] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 35 [5] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 39 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. table 7. lpc1113/14 pin description table (lqfp48 package) ?continued symbol pin start logic input type reset state [1] description
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 21 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller pio1_4/ad5/ ct32b1_mat3/ wakeup 40 [5] no i/o i; pu pio1_4 ? general purpose digital input/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 45 [3] no i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 46 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 47 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 9 [3] no i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0 17 [3] no i/o i; pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 30 [5] no i/o i; pu pio1_10 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 42 [5] no i/o i; pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. pio2_0 to pio2_11 i/o port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function select ed through the ioconfig register block. pio2_0/dtr /ssel1 2 [3] no i/o i; pu pio2_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. i/o - ssel1 ? slave select for spi1. pio2_1/dsr /sck1 13 [3] no i/o i; pu pio2_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. i/o - sck1 ? serial clock for spi1. pio2_2/dcd /miso1 26 [3] no i/o i; pu pio2_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart. i/o - miso1 ? master in slave out for spi1. table 7. lpc1113/14 pin description table (lqfp48 package) ?continued symbol pin start logic input type reset state [1] description
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 22 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to 2.6 v for lpc111x/101/201/301, pins pulled up to full v dd level on lpc111x/002/102/202/302 (v dd = 3.3 v)); ia = inactive, no pull-up/down enabled. [2] see figure 37 for the reset pad configuration. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an extern al pull-up resistor is required on this pin for the deep power-d own mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 36 ). [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 36 ). pio2_3/ri /mosi1 38 [3] no i/o i; pu pio2_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. i/o - mosi1 ? master out slave in for spi1. pio2_4 19 [3] no i/o i; pu pio2_4 ? general purpose digital input/output pin. pio2_5 20 [3] no i/o i; pu pio2_5 ? general purpose digital input/output pin. pio2_6 1 [3] no i/o i; pu pio2_6 ? general purpose digital input/output pin. pio2_7 11 [3] no i/o i; pu pio2_7 ? general purpose digital input/output pin. pio2_8 12 [3] no i/o i; pu pio2_8 ? general purpose digital input/output pin. pio2_9 24 [3] no i/o i; pu pio2_9 ? general purpose digital input/output pin. pio2_10 25 [3] no i/o i; pu pio2_10 ? general purpose digital input/output pin. pio2_11/sck0 31 [3] no i/o i; pu pio2_11 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio3_0 to pio3_5 i/o port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function select ed through the ioconfig register block. pins pio3_6 to pio3_11 are not available. pio3_0/dtr 36 [3] no i/o i; pu pio3_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. pio3_1/dsr 37 [3] no i/o i; pu pio3_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. pio3_2/dcd 43 [3] no i/o i; pu pio3_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart. pio3_3/ri 48 [3] no i/o i; pu pio3_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. pio3_4 18 [3] no i/o i; pu pio3_4 ? general purpose digital input/output pin. pio3_5 21 [3] no i/o i; pu pio3_5 ? general purpose digital input/output pin. v dd 8; 44 - i - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 6 [6] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 7 [6] - o - output from the oscillator amplifier. v ss 5; 41 - i - ground. table 7. lpc1113/14 pin description table (lqfp48 package) ?continued symbol pin start logic input type reset state [1] description
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 23 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. table 8. lpc1111/12/13/14 pin description table (hvqfn33 package) symbol pin start logic input type reset state [1] description pio0_0 to pio0_11 port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 2 [2] yes i i;pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 3 [3] yes i/o i;pu pio0_1 ? general purpose digital input/ output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clock out pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 8 [3] yes i/o i;pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 9 [3] yes i/o i;pu pio0_3 ? general purpose digital input/output pin. pio0_4/scl 10 [4] yes i/o i;pu pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 11 [4] yes i/o i;pu pio0_5 ? general purpose digital input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/out put. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 15 [3] yes i/o i;pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 16 [3] yes i/o i;pu pio0_7 ? general purpose digital inpu t/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 17 [3] yes i/o i;pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 18 [3] yes i/o i;pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 19 [3] yes i i;pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 24 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller r/pio0_11/ad0/ ct32b0_mat3 21 [5] yes - i;pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_11 port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ad1/ ct32b1_cap0 22 [5] yes - i;pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ad2/ ct32b1_mat0 23 [5] no - i;pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ad3/ ct32b1_mat1 24 [5] no - i;pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 25 [5] no i/o i;pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 26 [5] no i/o i;pu pio1_4 ? general purpose digital input/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 30 [3] no i/o i;pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 31 [3] no i/o i;pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. table 8. lpc1111/12/13/14 pin description table (hvqfn33 package) ?continued symbol pin start logic input type reset state [1] description
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 25 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to 2.6 v for lpc111x/101/201/301, pins pulled up to full v dd level on lpc111x/002/102/202/302 (v dd = 3.3 v)); ia = inactive, no pull-up/down enabled. [2] see figure 37 for the reset pad configuration. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an extern al pull-up resistor is required on this pin for the deep power-d own mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 36 ). [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled, and the pin is not 5 v tolerant (see figure 36 ). [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. pio1_7/txd/ ct32b0_mat1 32 [3] no i/o i;pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 7 [3] no i/o i;pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0 12 [3] no i/o i;pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 20 [5] no i/o i;pu pio1_10 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 27 [5] no i/o i;pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. pio2_0 port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. pins pio2_1 to pio2_11 are not available. pio2_0/dtr 1 [3] no i/o i;pu pio2_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. pio3_0 to pio3_5 port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function selected through the ioconfig register block. pins pio3_0, pio3_1, pio3_3 and pio3_6 to pio3_11 are not available. pio3_2 28 [3] no i/o i;pu pio3_2 ? general purpose digital input/output pin. pio3_4 13 [3] no i/o i;pu pio3_4 ? general purpose digital input/output pin. pio3_5 14 [3] no i/o i;pu pio3_5 ? general purpose digital input/output pin. v dd 6; 29 - i - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 4 [6] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 5 [6] - o - output from the oscillator amplifier. v ss 33 - - - thermal pad. connect to ground. table 8. lpc1111/12/13/14 pin description table (hvqfn33 package) ?continued symbol pin start logic input type reset state [1] description
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 26 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 7. functional description 7.1 arm cortex-m0 processor the arm cortex-m0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 on-chip flash program memory the lpc1110/11/12/13/14 contain 32 kb (lpc11 14), 24 kb (lpc1113), 16 kb (lpc1112), 8 kb (lpc1111), or 4 kb (lpc1110) of on-chip flash memory. 7.3 on-chip sram the lpc1110/11/12/13/14 contain a total of 8 kb, 4 kb, 2 kb, or 1 kb on-chip static ram memory. 7.4 memory map the lpc1110/11/12/13/14 incorporates several distinct memory regions, shown in the following figures. figure 9 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 megabyte in si ze, and is divided to allow for up to 128 peripherals. the apb peripheral ar ea is 512 kb in size and is divided to allow for up to 32 peripherals. each peripheral of either type is allocated 16 kilobytes of space. this allows simplifying the address decoding for each peripheral.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 27 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 7.5 nested vectored inte rrupt controller (nvic) the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m0. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. 7.5.1 features ? controls system exceptions and peripheral interrupts. (1) lqfp48 package only. (1) not on part lpc1112fdh20/102. fig 9. lpc1110/11/12/13/14 memory map 0x5000 0000 0x5001 0000 0x5002 0000 0x5020 0000 ahb peripherals 127-16 reserved gpio pio1 4-7 0x5003 0000 0x5004 0000 gpio pio2 gpio pio3 8-11 12-15 gpio pio0 0-3 apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 8000 0x4005 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wdt 32-bit counter/timer 0 32-bit counter/timer 1 adc uart pmu i 2 c-bus (2) 13-10 reserved reserved reserved 21-19 reserved 31-23 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x0000 2000 0x1000 2000 0x1000 1000 0x1000 0800 0x1fff 0000 0x1fff 4000 0x2000 0000 0x4000 0000 0x4008 0000 0x5000 0000 0x5020 0000 0xffff ffff reserved reserved reserved apb peripherals ahb peripherals 8 kb sram (lpc1113/14/301/302) 0x1000 0400 4 kb sram (lpc1111/12/13/14/201/102/202) 2 kb sram (lpc1111/12/101/002/102) 1 kb sram (lpc1110) 0x1000 0000 lpc1110/11/12/13/14 8 kb on-chip flash (lpc1111) 0x0000 1000 4 kb on-chip flash (lpc1110) 0x0000 4000 0x0000 6000 16 kb on-chip flash (lpc1112) 0x0000 8000 32 kb on-chip flash (lpc1114) 24 kb on-chip flash (lpc1113) 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors 002aae699 reserved spi0 16-bit counter/timer 1 16-bit counter/timer 0 ioconfig system control 22 spi1 (1) flash controller 0xe000 0000 0xe010 0000 private peripheral bus
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 28 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller ? in the lpc1110/11/12/13/14, th e nvic supports 32 vectored interrupts including up to 13 inputs to the start logic from individual gpio pins. ? four programmable interrupt priority levels with hardware prio rity level masking. ? software interr upt generation. 7.5.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. any gpio pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.6 ioconfig block the ioconfig block allows sele cted pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc1110/11/12/13/14 use accelerated gpio functions: ? gpio registers are a dedicated ahb peripheral so that the fastest possible i/o timing can be achieved. ? entire port value can be written in one instruction. additionally, any gpio pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 features ? bit level port registers allow a single instruct ion to set or clear any number of bits in one write operation. ? direction control of individual bits. ? all i/o default to inputs with pull-ups enabled after reset with the exception of the i 2 c-bus pins pio0_4 and pio0_5. ? pull-up/pull-down resistor configuration can be programmed through the ioconfig block for each gpio pin (except for pins pio0_4 and pio0_5). ? on the lpc111x/101/201/301, all gpio pins (except pio0_4 and pio0_5) are pulled up to 2.6 v (v dd = 3.3 v) if their pull-up resistor is enabled in the ioconfig block.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 29 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller ? on the lpc111x/002/102/202/302, all gpio pins (except pio0_4 and pio0_5) are pulled up to 3.3 v (v dd = 3.3 v) if their pull-up resistor is enabled in the ioconfig block. ? programmable open-drain mode for parts lpc111x/002/102/202/302. 7.8 uart the lpc1110/11/12/13/14 contain one uart. support for rs-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. the uart includes a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.8.1 features ? maximum uart data bit rate of 3.125 mbit/s. ? 16 byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode. ? support for modem control. 7.9 spi serial i/o controller the lpc1110/11/12/13/14 contain two spi co ntrollers on the lqfp48 package and one spi controller on the hvqfn33/tssop2 8/dip28/tssop20/so 20 packages (spi0). both spi controllers support ssp features. the spi controller is capable of operation on a ssp, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the spi supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.9.1 features ? maximum spi speed of 25 mbit/s (master) or 4.17 mbit/s (slave) (in ssp mode) ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 30 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 7.10 i 2 c-bus serial i/o controller the lpc1110/11/12/13/14 contain one i 2 c-bus controller. remark: part lpc1112fdh20/102 does not contain the i 2 c-bus controller. the i 2 c-bus is bidirectional for inter-ic control using only two wires: a serial clock line (scl) and a serial data line (sda). each de vice is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.10.1 features ? the i 2 c-interface is a standard i 2 c-bus compliant interface with open-drain pins. the i 2 c-bus interface also supports fast-mod e plus with bit rates up to 1 mbit/s. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 7.11 10-bit adc the lpc1110/11/12/13/14 contain one adc. it is a single 10-bit successive approximation adc with eight channels. 7.11.1 features ? 10-bit successive approximation adc. ? input multiplexing among 8 pins. ? power-down mode. ? measurement range 0 v to v dd . ? 10-bit conversion time ? 2.44 ? s (up to 400 ksamples/s). ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 31 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 7.12 general purpose externa l event counter/timers the lpc1110/11/12/13/14 include two 32-bit counter/timers and two 16-bit counter/timers. the counter/timer is designed to count cycles of the system derived clock. it can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. each counter/timer also incl udes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.12.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? one capture channel per timer, that can ta ke a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. 7.13 system tick timer the arm cortex-m0 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fi xed time interval (typically 10 ms). 7.14 watchdog timer (lpc1100 series, lpc111x/101/201/301) remark: the watchdog timer without windowed features is available on parts lpc111x/101/201/301. the purpose of the watchdog is to reset t he microcontroller within a selectable time period. 7.14.1 features ? internally resets chip if not period ically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 32 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the in ternal rc oscillator (irc), the watchdog oscillator, or the main cl ock. this gives a wid e range of potential timing choices of watchdog operation unde r different power reduction conditions. it also provides the ability to run the wdt from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. 7.15 windowed watchdog ti mer (lpc1100l series, lpc111x/002/102/202/302) remark: the windowed watchdog timer is availa ble on parts lpc111x/002/102/202/302. the purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.15.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the irc or the dedicated watchdog oscillator (wdo). this gives a wide range of potential timing choices of watchdog operation under different power conditions. 7.16 clocking and power control 7.16.1 crystal oscillators the lpc1110/11/12/13/14 incl ude three ind ependent oscillators. these are the system oscillator, the internal rc oscillator (irc), and the watchdog os cillator. each oscillator can be used for more than one purpose as required in a particular application. following reset, the lpc1110/11/1 2/13/14 will operate from the internal rc oscillator until switched by software. this a llows systems to operate without any external crystal and the bootloader code to operate at a known frequency. see figure 10 for an overview of the lpc1 110/11/12/13/14 clock generation.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 33 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 7.16.1.1 internal rc oscillator the irc may be used as the clock source for th e wdt, and/or as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. upon power-up or any chip reset, the lpc1110/11/12/13/14 use the irc as the clock source. software may later switch to one of the other available clock sources. 7.16.1.2 system oscillator the system oscillator can be used as the clock source for the cpu, with or without using the pll. the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. fig 10. lpc1110/11/12/13/14 cloc k generation block diagram system pll irc oscillator system oscillator watchdog oscillator irc oscillator watchdog oscillator mainclksel (main clock select) syspllclksel (system pll clock select) system clock divider ahb clock 0 (system) sysahbclkctrl[1:18] (ahb clock enable) ahb clocks 1 to 18 (memories and peripherals) spi0 peripheral clock divider spi0 spi1 peripheral clock divider spi1 uart peripheral clock divider uart wdt clock divider wdt wdtuen (wdt clock update enable) watchdog oscillator irc oscillator system oscillator clkout pin clock divider clkout pin clkoutuen (clkout update enable) 002aae514 main clock system clock irc oscillator 18
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 34 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 7.16.1.3 watchdog oscillator the watchdog oscillator can be used as a clock source that directly drives the cpu, the watchdog timer, or the clkout pin. the watchdog oscillator nominal frequency is programmable between 7.8 khz and 1.7 mhz. th e frequency spread over processing and temperature is ? 40 %. 7.16.2 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is prov iding the desired output frequency. the pll output frequency must be lower than 100 mhz. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. si nce the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.16.3 clock output the lpc1110/11/12/13 /14 features a cloc k output function that routes th e irc oscillator, the system oscillator, the watchdog oscillator , or the main clock to an output pin. 7.16.4 wake-up process the lpc1110/11/12/13/14 begin operation at power-up and when awakened from deep power-down mode by using the 12 mhz irc o scillator as the clock source. this allows chip operation to resume quickly. if the syst em oscillator or the pll is needed by the application, software will need to enable these features an d wait for them to stabilize before they are used as a clock source. 7.16.5 power control the lpc1110/11/12/13/14 support a variety of power control features. there are three special modes of processor power reduction: sleep mode, deep-sleep mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, a register is pr ovided for shutting down the cl ocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required fo r the application. selected peripherals have their own clock divider which prov ides even better power control. 7.16.5.1 power profiles (lpc1100l se ries, lpc111x/002/ 102/202/302 only) the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile. the power configuration routine configures the lpc1110/11/12/13/14 for one of the following power modes: ? default mode corresponding to power configuration after reset. ? cpu performance mode co rresponding to optimize d processing capability.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 35 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller ? efficiency mode corresponding to optimize d balance of current consumption and cpu performance. ? low-current mode corresponding to lowest power consumption. in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock. 7.16.5.2 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.16.5.3 deep-sleep mode in deep-sleep mode, the chip is in sleep mode, and in addition all analog blocks are shut down. as an exception, the user has the opt ion to keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. deep-sleep mode allows for additional power savings. up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip from deep-sleep mode. unless the watchdog oscillator is selected to run in deep-s leep mode, the clock source should be switched to irc before entering deep-sleep mode, because the irc can be switched on and off glitch-free. 7.16.5.4 deep power-down mode in deep power-down mode, power is shut off to the entire chip with the exception of the wakeup pin. the lpc1110/11/ 12/13/14 can wake up from deep power-down mode via the wakeup pin. a low-going pulse as short as 50 ns wakes up the part from deep power-down mode. when entering deep power-down mode, an external pull-up resistor is required on the wakeup pin to hold it high. the reset pin must also be held high to prevent it from floating while in deep power-down mode. 7.17 system control 7.17.1 start logic the start logic connects external pins to corresponding interrupts in the nvic. each pin shown in ta b l e 7 to table 8 as input to the start logic has an individual interrupt in the nvic interrupt vector table. the start logic pi ns can serve as external interrupt pins when the chip is running. in addition, an input signal on the start logic pins can wake up the chip from deep-sleep mode when all clocks are shut down. the start logic must be configured in the system configuration block and in the nvic before being used.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 36 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 7.17.2 reset reset has four sources on the lpc1110/11/12/13/14: the reset pin, the watchdog reset, power-on reset (por), and the browno ut detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip re set by any source, once the operating voltage attains a usable level, starts the irc and initializes the flash controller. a low-going pulse as short as 50 ns resets the part. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. an external pull-up resistor is required on the reset pin if deep power-down mode is used. 7.17.3 brownout detection the lpc1110/11/12/13/14 includes four le vels for monitoring the voltage on the v dd pin. if this voltage falls below one of the four select ed levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for inte rrupt in the interrupt enable register in the nvic in order to cause a cpu in terrupt; if not, software can monitor the signal by reading a dedicated status register. four additional threshold levels can be selected to cause a forced reset of the chip. 7.17.4 code security (code read protection - crp) this feature of the lpc1110/11/12/13/14 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. when needed, crp is invoked by programming a specific pattern into a dedicated flash location. iap commands are not affected by the crp. in addition, isp entry via the pio0_1 pin can be disabled without enabling crp. for details see the lpc111x user manual . there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors can not be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 select ed fully disables any access to the chip via the swd pins and the isp. this mode effectively disables isp override using pio0_1 pin, too. it is up to the user?s application to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via the uart.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 37 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller in addition to the three crp levels, sampli ng of pin pio0_1 for valid user code can be disabled. for details see the lpc111x user manual . 7.17.5 apb interface the apb peripherals are located on one apb bus. 7.17.6 ahblite the ahblite connects the cpu bus of the arm cortex-m0 to the flash memory, the main static ram, and the boot rom. 7.17.7 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. in addition, start logic inputs serve as external interrupts (see section 7.17.1 ). 7.18 emulation and debugging debug functions are integrated into the arm cortex-m0. serial wire debug with four breakpoints and two watchpoints is supported. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 38 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] the peak current is limited to 25 times the corresponding maximum current. [4] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on required shelf lifetime. please refer to t he jedec spec (j-std-033b.1) for further details. [5] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 9. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) 1.8 3.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd supply voltage is present [2] ? 0.5 +5.5 v i dd supply current per supply pin [3] - 100 ma i ss ground current per ground pin [3] - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ?c - 100 ma t stg storage temperature non-operating [4] ? 65 +150 ?c t j(max) maximum junction temperature - 150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [5] ? 6500 +6500 v
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 39 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 9. static characteristics table 10. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) 1.8 3.3 3.6 v lpc1100 series (lpc111x/101/201/301) power consumption i dd supply current active mode; code while(1){} executed from flash system clock = 12 mhz v dd = 3.3 v [2] [3] [4] [5] [6] -3-m a system clock = 50 mhz v dd = 3.3 v [2] [3] [5] [6] [7] -9-m a sleep mode; system clock = 12 mhz v dd = 3.3 v [2] [3] [4] [5] [6] -2-m a deep-sleep mode; v dd = 3.3 v [2] [3] [8] -6- ? a deep power-down mode; v dd = 3.3 v [2] [9] -2 2 0-n a lpc1100l series (lpc111x/002/ 102/202/302) power consumption in low-current mode [10] i dd supply current active mode; code while(1){} executed from flash system clock = 12 mhz v dd = 3.3 v [2] [3] [4] [5] [6] -2-m a system clock = 50 mhz v dd = 3.3 v [2] [3] [5] [6] [7] -7-m a sleep mode; system clock = 12 mhz v dd = 3.3 v [2] [3] [4] [5] [6] -1-m a deep-sleep mode; v dd = 3.3 v [2] [3] [8] -2- ? a deep power-down mode; v dd = 3.3 v [2] [9] -2 2 0-n a standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled - 0.5 10 na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled - 0.5 10 na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled - 0.5 10 na
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 40 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller v i input voltage pin configured to provide a digital function [11] [12] [13] 0- 5 . 0v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage 2.0 v ? v dd ? 3.6 v; i oh = ? 4 ma v dd ? 0.4 - - v 1.8 v ? v dd < 2.0 v; i oh = ? 3 ma v dd ? 0.4 - - v v ol low-level output voltage 2.0 v ? v dd ? 3.6 v; i ol =4 ma --0.4v 1.8 v ? v dd < 2.0 v; i ol =3 ma --0 . 4v i oh high-level output current v oh =v dd ? 0.4 v; 2.0 v ? v dd ? 3.6 v ? 4- - ma 1.8 v ? v dd < 2.0 v ? 3- - ma i ol low-level output current v ol =0.4v 2.0 v ? v dd ? 3.6 v 4- - ma 1.8 v ? v dd < 2.0 v 3 - - ma i ohs high-level short-circuit output current v oh =0v [14] -- ? 45 ma i ols low-level short-circuit output current v ol =v dd [14] --5 0m a i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v; 2.0 v ? v dd ? 3.6 v ? 15 ? 50 ? 85 ? a 1.8 v ? v dd < 2.0 v ? 10 ? 50 ? 85 ? a v dd lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 41 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage 2.5 v ?? v dd ?? 3.6 v; i oh = ? 20 ma v dd ? 0.4 - - v 1.8 v ?? v dd < 2.5 v; i oh = ? 12 ma v dd ? 0.4 - - v v ol low-level output voltage 2.0 v ?? v dd ?? 3.6 v; i ol =4 ma --0 . 4v 1.8 v ?? v dd < 2.0 v; i ol =3 ma --0.4v i oh high-level output current v oh =v dd ? 0.4 v; 2.5 v ? v dd ? 3.6 v 20 - - ma 1.8 v ? v dd < 2.5 v 12 - - ma i ol low-level output current v ol =0.4v 2.0 v ? v dd ? 3.6 v 4- - ma 1.8 v ? v dd < 2.0 v 3 - - ma i ols low-level short-circuit output current v ol =v dd [14] --5 0m a i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v 2.0 v ? v dd ? 3.6 v ? 15 ? 50 ? 85 ? a 1.8 v ? v dd < 2.0 v ? 10 ? 50 ? 85 ? a v dd lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 42 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] t amb =25 ? c. [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [4] irc enabled; system oscillator disabled; system pll disabled. [5] bod disabled. [6] all peripherals disabled in the sysahbclkctrl register. peri pheral clocks to uart and spi0/1 disabled in system configuratio n block. [7] irc disabled; system oscill ator enabled; system pll enabled. [8] all oscillators and analog blocks turned off in the pdsleepcfg register; pdsleepcfg = 0x0000 18ff. [9] wakeup pin pulled high externally. [10] low-current mode pwr_low_current selected when runni ng the set_power routine in the power profiles. [11] including voltage on outputs in 3-state mode. [12] v dd supply voltage must be present. [13] 3-state outputs go into 3-state mode in deep power-down mode. [14] allowed as long as the current limit does not exceed the maximum current allowed by the device. [15] to v ss . [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 11 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 11 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 11 . [5] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 11 . [6] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 11 . [7] t amb = 25 ? c; maximum sampling frequency f s = 400 ksamples/s and analog input capacitance c ia = 1 pf. [8] input resistance r i depends on the sampling frequency f s : r i = 1 / (f s ? c ia ). table 11. adc static characteristics t amb = ? 40 ? c to +85 ? c unless otherwise specified; adc frequency 4.5 mhz, v dd = 2.5 v to 3.6 v. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dd v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] --? 1lsb e l(adj) integral non-linearity [3] --? 1.5 lsb e o offset error [4] --? 3.5 lsb e g gain error [5] --0 . 6% e t absolute error [6] --? 4lsb r vsi voltage source interface resistance --40k ? r i input resistance [7] [8] --2 . 5m ?
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 43 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 11. adc characteristics 002aaf426 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd ? v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 44 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 9.1 bod static characteristics [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see lpc111x user manual . 9.2 power consumpt ion lpc111x/101/201/301 power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see lpc111x user manual ): ? configure all pins as gpio with pull-up resistor disabled in the ioconfig block. ? configure gpio pins as outputs using the gpiondir registers. ? write 0 to all gpiondata registers to drive the outputs low. table 12. bod static characteristics [1] t amb =25 ?c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 0 assertion - 1.65 - v de-assertion - 1.80 - v interrupt level 1 assertion - 2.22 - v de-assertion - 2.35 - v interrupt level 2 assertion - 2.52 - v de-assertion - 2.66 - v interrupt level 3 assertion - 2.80 - v de-assertion - 2.90 - v reset level 0 assertion - 1.46 - v de-assertion - 1.63 - v reset level 1 assertion - 2.06 - v de-assertion - 2.15 - v reset level 2 assertion - 2.35 - v de-assertion - 2.43 - v reset level 3 assertion - 2.63 - v de-assertion - 2.71 - v
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 45 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register (sysah bclkctrl = 0x1f); a ll peripheral clocks disabled; internal pull-up resi stors disabled; bod disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 12. active mode: typical supply current i dd versus supply voltage v dd for different system clock frequencies (for lpc111x/101/201/301) conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register (sysah bclkctrl = 0x1f); a ll peripheral clocks disabled; internal pull-up resi stors disabled; bod disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 13. active mode: typical supply current i dd versus temperature for different system clock frequencies (fo r lpc111x/101/201/301) v dd (v) 1.8 3.6 3.0 2.4 002aaf390 4 8 12 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) temperature ( c) ?40 85 35 10 60 ?15 002aaf391 4 8 12 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2)
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 46 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; sleep mode entered from fl ash; all peripheral s disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors dis abled; bod disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 14. sleep mode: typical supply current i dd versus temperature for different system clock frequencies (fo r lpc111x/101/201/301) conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 15. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd (for lpc111x/101/201/301) 002aaf392 temperature ( c) ?40 85 35 10 60 ?15 2 6 4 8 i dd (ma) 0 12 mhz (1) 36 mhz (2) 48 mhz (2) 24 mhz (2) 002aaf394 temperature ( c) ?40 85 35 10 60 ?15 10 30 20 40 i dd (a) 0 3.6 v 3.3 v 2.0 v 1.8 v
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 47 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 9.3 power consumpti on lpc111x/002/102/202/302 power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see lpc111x user manual ): ? configure all pins as gpio with pull-up resistor disabled in the ioconfig block. ? configure gpio pins as outputs using the gpiondir registers. ? write 0 to all gpiondata registers to drive the outputs low. fig 16. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd (for lpc111x/101/201/301) 002aaf457 0.2 0.6 0.4 0.8 i dd (a) 0 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 2.0 v 1.8 v
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 48 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register (sysah bclkctrl = 0x1f); a ll peripheral clocks disabled; internal pull-up resistors di sabled; bod disabled; low-current mode. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 17. active mode: typical supply current i dd versus supply voltage v dd for different system clock frequencies (for lpc111x/002/102/202/302) conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register (sysah bclkctrl = 0x1f); a ll peripheral clocks disabled; internal pull-up resistors di sabled; bod disabled; low-current mode. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 18. active mode: typical supply current i dd versus temperature for different system clock frequencies (for lpc111x/002/102/202/302) v dd (v) 1.8 3.6 3.0 2.4 002aaf980 4 6 2 8 10 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) 002aaf981 temperature ( c) ?40 85 35 10 60 ?15 2 8 6 4 10 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2)
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 49 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; sleep mode entered from fl ash; all peripheral s disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors disabled; bo d disabled; low-current mode. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 19. sleep mode: typical supply current i dd versus temperature for different system clock frequencies (for lpc111x/002/102/202/302) temperature ( c) ?40 85 35 10 60 ?15 002aaf982 2 4 6 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2)
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 50 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 20. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd (for lpc111x/002/102/202/302) fig 21. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd (for lpc111x/002/102/202/302) 002aaf977 temperature ( c) ?40 85 35 10 60 ?15 2.5 4.5 3.5 5.5 i dd (a) 1.5 v dd = 3.3 v, 3.6 v 1.8 v 002aaf978 0.2 0.6 0.4 0.8 i dd (a) 0 temperature ( c) ?40 85 35 10 60 ?15 v dd = 3.6 v 3.3 v 1.8 v
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 51 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 9.4 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c. unless noted otherwise, the system oscillator an d pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz and 48 mhz. table 13. power consumption for individual analog and digital blocks peripheral typical supply current in ma notes n/a 12 mhz 48 mhz irc 0.27 - - system oscillator running; pll off; independent of main clock frequency. system oscillator at 12 mhz 0.22 - - irc running; pll off; independent of main clock frequency. watchdog oscillator at 500 khz/2 0.004 - - system oscillator running; pll off; independent of main clock frequency. bod 0.051 - - independent of main clock frequency. main pll - 0.21 - adc - 0.08 0.29 clkout - 0.12 0.47 main clock divided by 4 in the clkoutdiv register. ct16b0 - 0.02 0.06 ct16b1 - 0.02 0.06 ct32b0 - 0.02 0.07 ct32b1 - 0.02 0.06 gpio - 0.23 0.88 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabled in the sysahbclkcfg register. ioconfig - 0.03 0.10 i2c - 0.04 0.13 rom - 0.04 0.15 spi0 - 0.12 0.45 spi1 - 0.12 0.45 uart - 0.22 0.82 wdt - 0.02 0.06 main clock selected as clock source for the wdt.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 52 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 9.5 electrical pi n characteristics conditions: v dd = 3.3 v; on pin pio0_7. fig 22. high-drive output: typical high-level output voltage v oh versus high-level output current i oh . conditions: v dd = 3.3 v; on pins pio0_4 and pio0_5. fig 23. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c ?40 c
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 53 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; standard port pins and pio0_7. fig 24. typical low-l evel output current i ol versus low-level output voltage v ol conditions: v dd = 3.3 v; standard port pins. fig 25. typical high-level output voltage v oh versus high-level output source current i oh v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 54 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 26. typical pull-up current i pu versus input voltage v i conditions: v dd = 3.3 v; standard port pins. fig 27. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aae988 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd (a) 0 t = 85 c 25 c ?40 c
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 55 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 10. dynamic characteristics 10.1 power-up ramp conditions [1] see figure 28 . [2] the wait time specifies the time the power supply must be at levels below 400 mv before ramping up. 10.2 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to the flash. data must be written to the flash in blocks of 256 bytes. table 14. power-up characteristics t amb = ? 40 ? c to +85 ?c. symbol parameter conditions min typ max unit t r rise time at t = t 1 : 0 < v i ?? 400 mv [1] 0- 500 ms t wait wait time [1] [2] 12 - - ? s v i input voltage at t = t 1 on pin v dd 0 - 400 mv condition: 0 < v i ?? 400 mv at start of power-up (t = t 1 ) fig 28. power-up ramp v dd 0 400 mv t r t wait t = t 1 002aag001 table 15. flash characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 - - years unpowered 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 56 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 10.3 external clock [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 16. dynamic characteristic: external clock t amb = ? 40 ? c to +85 ?c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4--ns t clcx clock low time t cy(clk) ? 0.4--ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 29. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 57 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 10.4 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40 %. [3] see the lpc111x user manual . table 17. dynamic characteristic: internal oscillators t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. 12 mhz ? 1 % accuracy is guaranteed for 2.7 v ? v dd ? 3.6 v and t amb = ?40 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 12 mhz ? 1 % accuracy specification for voltages below 2.7 v. fig 30. internal rc oscillator frequency versus temperature table 18. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -7.8 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 1700 - khz 002aaf403 11.95 12.05 12.15 f (mhz) 11.85 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v 2.0 v
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 58 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 10.5 i/o pins [1] applies to standard port pins and reset pin. 10.6 i 2 c-bus [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the falling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. table 19. dynamic characteristic: i/o pins [1] t amb = ? 40 ? c to +85 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 20. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ?c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 59 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with respect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low per iod of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. 10.7 spi interfaces fig 31. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat table 21. dynamic characteristics of spi pins in spi mode symbol parameter conditions min typ max unit spi master (in spi mode) t cy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] 40 ns t ds data set-up time in spi mode 2.4 v ? v dd ? 3.6 v [2] 15 - - ns 2.0 v ? v dd < 2.4 v [2] 20 ns 1.8 v ? v dd < 2.0 v [2] 24 - - ns t dh data hold time in spi mode [2] 0-- n s t v(q) data output valid time in spi mode [2] -- 1 0 n s t h(q) data output hold time in spi mode [2] 0-- n s
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 60 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the spi peripheral clock divider (sspclkdiv), the spi scr parameter (specified in the ssp0cr0 register), and the spi cpsdvsr parameter (specified in the spi clock prescale register). [2] t amb = ?40 ? c to 85 ? c. [3] t cy(clk) = 12 ? t cy(pclk) . [4] t amb = 25 ? c; for normal voltage supply range: v dd = 3.3 v. spi slave (in spi mode) t cy(pclk) pclk cycle time 20 - - ns t ds data set-up time in spi mode [3] [4] 0-- n s t dh data hold time in spi mode [3] [4] 3 ? t cy(pclk) + 4 - - ns t v(q) data output valid time in spi mode [3] [4] -- 3 ? t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -- 2 ? t cy(pclk) + 5 ns table 21. dynamic characteristics of spi pins in spi mode symbol parameter conditions min typ max unit pin names sck, miso, and mosi refer to pins for both spi peripherals, spi0 and spi1. fig 32. spi master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 61 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller pin names sck, miso, and mosi refer to pins for both spi peripherals, spi0 and spi1. fig 33. spi slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 62 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 11. application information 11.1 adc usage notes the following guidelines show how to increase the performance of the adc in a noisy environment beyond the adc specifications listed in ta b l e 11 : ? the adc input trace must be short and as close as possible to the lpc1110/11/12/13/14 chip. ? the adc input traces must be shielded from fast switching digital signals and noisy power supply lines. ? because the adc and the digital core share the same power supply, the power supply line must be adequately filtered. ? to improve the adc performance in a very no isy environment, put the device in sleep mode during the adc conversion. 11.2 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv (rms) is needed. in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 34 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 35 and in ta b l e 2 2 and ta b l e 2 3 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 35 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer (see ta b l e 2 2 ). fig 34. slave mode operation of the on-chip oscillator lpc1xxx xtalin c i 100 pf c g 002aae788
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 63 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 11.3 xtal printed circuit bo ard (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in fig 35. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 22. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz - 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz - 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 23. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 64 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. 11.4 standard i/o pad configuration figure 36 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? analog input fig 36. standard i/o pad configuration pin v dd esd v ss esd v dd weak pull-up weak pull-down output enable repeater mode enable output pull-up enable pull-down enable data input analog input select analog input 002aaf304 pin configured as digital output driver pin configured as digital input pin configured as analog input
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 65 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 11.5 reset pad configuration 11.6 electromagnetic co mpatibility (emc) radiated emission measurements according to the iec61967-2 standard using the tem-cell method are shown for the lpc1114fbd48/302 in ta b l e 2 4 . [1] iec levels refer to appendix d in the iec61967-2 specification. fig 37. reset pad configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin table 24. electromagnetic compatibility (e mc) for part lpc1114fbd48/302 (tem-cell method) v dd = 3.3 v; t amb = 25 ? c. parameter frequency band system clock = unit 12 mhz 24 mhz 48 mhz input clock: irc (12 mhz) maximum peak level 150 khz - 30 mhz ? 7 ? 5 ? 7db ? v 30 mhz - 150 mhz ? 21 1 0d b ? v 150 mhz - 1 ghz 4 8 16 db ? v iec level [1] -onm- input clock: crystal oscillator (12 mhz) maximum peak level 150 khz - 30 mhz ? 7 ? 7 ? 7db ? v 30 mhz - 150 mhz ? 218db ? v 150 mhz - 1 ghz 4 7 14 db ? v iec level [1] -onm-
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 66 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 12. package outline fig 38. package outline sot163-1 (so20) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z ywv references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 67 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 39. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 11 0 20 11 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 68 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 40. package outline sot361-1 (tssop28) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot361-1 mo-153 99-12-27 03-02-19 0.25 w m b p z e 11 4 28 15 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 a max. 1.1
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 69 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 41. package outline sot117-1 (dip28) unit a max. 1 2 b 1 (1) (1) (1) cd e w em h l references outline version european projection issue date iec jedec jeita mm inches dimensions (mm dimensions are derived from the original inch dimensions) sot117-1 99-12-27 03-02-13 a min. a max. b z max. m e e 1 1.7 1.3 0.53 0.38 0.32 0.23 36 35 14.1 13.7 3.9 3.4 0.25 2.54 15.24 15.80 15.24 17.15 15.90 1.7 5.1 0.51 4 0.066 0.051 0.020 0.014 0.013 0.009 1.41 1.34 0.56 0.54 0.15 0.13 0.01 0.1 0.6 0.62 0.60 0.68 0.63 0.067 0.2 0.02 0.16 051g05 mo-015 sc-510-28 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 28 1 15 14 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. dip28: plastic dual in-line package; 28 leads (600 mil) sot117-1
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 70 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 42. package outline (hvqfn33 5x5) references outline version european projection issue date iec jedec jeita mo-220 hvqfn33f_po 11-10-11 11-10-17 unit (1) mm max nom min 0.85 0.05 0.00 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 a 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm bc 0.30 0.18 d (1) a (1) d h e (1) e h ee 1 e 2 l 3.5 vw 0.1 0.1 y 0.05 0.5 0.3 y 1 0.05 0 2.5 5 mm scale 1/2 e ac b v c w terminal 1 index area a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area 1/2 e
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 71 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 43. package outline (hvqfn33 7x7) references outline version european projection issue date iec jedec jeita - - - hvqfn33_po 09-03-17 09-03-23 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm a 1 b 0.35 0.28 0.23 cd (1) d h e (1) e h 4.85 4.70 4.55 ee 1 e 2 4.55 lv 0.1 w 0.05 y 0.08 y 1 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a 1 a c b e 2 e 1 e e ac b v c w terminal 1 index area d h e h l 9 16 32 33 25 17 24 8 1
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 72 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 44. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 73 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 13. soldering fig 45. reflow soldering of the so20 package sot163-1_fr occupied area solder lands dimensions in mm placement accuracy 0.25 1.50 0.60 (20) 1.27 (18) 8.00 11.00 13.40 11.40
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 74 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 46. reflow soldering of the tssop20 package dimensions in mm ay by d1 d2 gy hy p1 c gx sot360-1_fr hx sot360-1 solder land occupied area footprint information for reflow soldering of tssop20 package ay by gy c hy hx gx p1 generic footprint pattern refer to the package outline drawing for actual layout p2 (0.125) (0.125) d1 d2 (4x) p2 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.450 7.300 0.650 0.750
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 75 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 47. reflow soldering of the tssop28 package dimensions in mm ay by d1 d2 gy hy p1 c gx sot361-1_fr hx sot361-1 solder land occupied area footprint information for reflow soldering of tssop28 package ay by gy c hy hx gx p1 generic footprint pattern refer to the package outline drawing for actual layout p2 (0.125) (0.125) d1 d2 (4x) p2 7.200 4.500 1.350 0.400 0.600 9.500 5.300 7.450 11.800 0.650 0.750
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 76 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 48. reflow soldering of the hvqfn33 package footprint information for reflow soldering of hvqfn33 package 001aao134 occupied area solder land solder resist solder land plus solder paste solder paste deposit dimensions in mm remark: stencil thickness: 0.125 mm e = 0.65 evia = 4.25 owdtot = 5.10 oa pid = 7.25 pa+oa oid = 8.20 oa 0.20 sr chamfer (4) 0.45 dm evia = 1.05 w = 0.30 cu evia = 4.25 evia = 2.40 lbe = 5.80 cu lbd = 5.80 cu pie = 7.25 pa+oa lae = 7.95 cu lad = 7.95 cu oie = 8.20 oa owetot = 5.10 oa ehs = 4.85 cu dhs = 4.85 cu 4.55 sr 4.55 sr b-side (a-side fully covered) number of vias: 20 solder resist covered via 0.30 ph 0.60 sr cover 0.60 cu sehtot = 2.70 sp sdhtot = 2.70 sp gape = 0.70 sp spe = 1.00 sp 0.45 dm spd = 1.00 sp gapd = 0.70 sp
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 77 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller fig 49. reflow soldering of the lqfp48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ayby p1 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 78 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 14. abbreviations table 25. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus apb advanced peripheral bus bod brownout detection gpio general purpose input/output pll phase-locked loop rc resistor-capacitor spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port tem transverse electromagnetic uart universal asynchronous receiver/transmitter
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 79 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 15. revision history table 26. revision history document id release date data sheet status change notice supersedes lpc1110_11_12_13_14 v.6 20111102 product data sheet - lpc1111_12_13_14 v.5 modifications: ? parts lpc1112fhi33/202 and lpc1114fhi33/302 added. ? parts lpc1112fdh28/102, lpc111 4fdh28/102, lpc1114fn28/102, lpc1112fdh20/102, LPC1110FD20, lpc1 111fdh20/002, lpc1112fd20/102 added. lpc1111_12 _13_14 v.5 20110622 product data sheet - lpc1111_12_13_14 v.4 modifications: ? adc sampling frequency corrected in table 7 (table note 7). ? pull-up level specified in table 3 to table 4 and section 7.7.1. ? parameter t cy(clk) corrected on table 17. ? wwdt for parts lpc111x/102/202/302 added in section 2 and section 7.15. ? programmable open-drain mode for parts lpc111x/102/202/302 added in section 2 and section 7.12. ? condition for parameter t stg in table 5 updated. ? table note 4 of table 5 updated. ? section 13 added. ? removed plcc44 package information. lpc1111_12 _13_14 v.4 20110210 product data sheet - lpc1111_12_13_14 v.3 modifications: ? power consumption graphs added for parts lpc111x/102/202/302 (figure 13 to figure 17). ? parameter v hys for i 2 c bus pins: typical value corrected v hys = 0.05v dd in table 7. ? typical value for parameter n endu added in table 12 ?flash characteristics?. ? i 2 c-bus pins configured as standard mode pins, parameter i ol changed to 3.5 ma (minimum) for 2.0 v ? v dd ? 3.6 v. ? section 11.6 ?electromagnetic compatibility (emc)? added. ? power-up characterization added (section 10.1 ?power-up ramp conditions?). lpc1111_12 _13_14 v.3 20101110 product data sheet - lpc1111_12_13_14 v.2 modifications: ? parts lpc111x/102/202/302 added (lpc1100l series). ? power consumption data for parts lpc111x/102/202/302 added in table 7. ? pll output frequency limited to 100 mhz in section 7.15.2. ? description of reset and wakeup functions updated in section 6. ? wdt description updated in section 7.14. the wdt is a 24-bit timer. ? power profiles added to section 2 and section 7 for parts lpc111x/102/202/302. lpc1111_12 _13_14 v.2 20100818 product data sheet - lpc1111_12_13_14 v.1 modifications: ? v esd limit changed to ? 6500 v (min) /+6500 v (max) in table 6. ? t ds updated for spi in master mode (table 17). ? deep-sleep mode functionality changed to allow bod and watchdog oscillator as the only analog blocks allowed to remain running in deep-sleep mode (section 7.15.5.3). ? v dd range changed to 3.0 v ? v dd ? 3.6 v in table 15. ? reset state of pins and start logic functionality added in table 3 to table 5. ? section 7.16.1 added. ? section ?memory mapping control? removed. ? v oh and i oh specifications updated for high-drive pins in table 7. ? section 9.4 added.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 80 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller lpc1111_12 _13_14 v.1 20100416 product data sheet - - table 26. revision history ?continued document id release date data sheet status change notice supersedes
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 81 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 82 of 84 nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc1110_11_12_13_14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserv ed. product data sheet rev. 6 ? 2 november 2011 83 of 84 continued >> nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 12 7 functional description . . . . . . . . . . . . . . . . . . 26 7.1 arm cortex-m0 processor . . . . . . . . . . . . . . . 26 7.2 on-chip flash program memo ry . . . . . . . . . . . 26 7.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 nested vectored interrupt controller (nvic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.5.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 28 7.6 ioconfig block . . . . . . . . . . . . . . . . . . . . . . 28 7.7 fast general purpose parallel i/o . . . . . . . . . . 28 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.8 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.9 spi serial i/o controller. . . . . . . . . . . . . . . . . . 29 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.10 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 30 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.11 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.12 general purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.13 system tick timer . . . . . . . . . . . . . . . . . . . . . . 31 7.14 watchdog timer (lpc1100 series, lpc111x/101/201/301) . . . . . . . . . . . . . . . . . . 31 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.15 windowed watchdog timer (lpc1100l series, lpc111x/002/102/202/302) . . . . . . . . . . . . . . 32 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.16 clocking and power control . . . . . . . . . . . . . . 32 7.16.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 32 7.16.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 33 7.16.1.2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 33 7.16.1.3 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 34 7.16.2 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.16.3 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.16.4 wake-up process . . . . . . . . . . . . . . . . . . . . . . 34 7.16.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.16.5.1 power profiles (lpc1100l series, lpc111x/002/102/202/302 only) . . . . . . . . . . 34 7.16.5.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.16.5.3 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 35 7.16.5.4 deep power-down mode . . . . . . . . . . . . . . . . 35 7.17 system control . . . . . . . . . . . . . . . . . . . . . . . . 35 7.17.1 start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.17.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.17.3 brownout detection . . . . . . . . . . . . . . . . . . . . 36 7.17.4 code security (code read protection - crp) . . . . . . . . . . . 36 7.17.5 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.17.6 ahblite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.17.7 external interr upt inputs . . . . . . . . . . . . . . . . . 37 7.18 emulation and debugging . . . . . . . . . . . . . . . 37 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38 9 static characteristics . . . . . . . . . . . . . . . . . . . 39 9.1 bod static characteristics . . . . . . . . . . . . . . . 44 9.2 power consumption lpc111x/101/201/301 . . . . . . . . . . . . . . . . . . 44 9.3 power consumption lpc111x/002/102/202/302. . . . . . . . . . . . . . . 47 9.4 peripheral power consumption . . . . . . . . . . . 51 9.5 electrical pin characteristics. . . . . . . . . . . . . . 52 10 dynamic characteristics. . . . . . . . . . . . . . . . . 55 10.1 power-up ramp conditions . . . . . . . . . . . . . . . 55 10.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 55 10.3 external clock. . . . . . . . . . . . . . . . . . . . . . . . . 56 10.4 internal oscillators . . . . . . . . . . . . . . . . . . . . . 57 10.5 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.6 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.7 spi interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 59 11 application information . . . . . . . . . . . . . . . . . 62 11.1 adc usage notes. . . . . . . . . . . . . . . . . . . . . . 62 11.2 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.3 xtal printed circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . 63 11.4 standard i/o pad configuration . . . . . . . . . . . 64 11.5 reset pad configuration . . . . . . . . . . . . . . . . . 65 11.6 electromagnetic compatibility (emc) . . . . . . 65 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 66 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 78 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 79
nxp semiconductors lpc1110/11/12/13/14 32-bit arm cortex-m0 microcontroller ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 2 november 2011 document identifier: lpc1110_11_12_13_14 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 81 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 81 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17 contact information. . . . . . . . . . . . . . . . . . . . . 82 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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