View MB15F02SLPV1_2777562.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds04-21356-3e fujitsu semiconductor data sheet assp dual serial input pll frequency synthesizer mb15f02sl n description the fujitsu mb15f02sl is a serial input phase locked loop (pll) frequency synthesizer with a 1200 mhz and a 500 mhz prescalers. the 1200 mhz and 500 mhz prescalers have a dual modulus division ratio of 128/129 or 64/65, and a 8/9 or a 16/17 enabling pulse swallowing operation. the supply voltage range is between 2.4 v and 3.6 v. the mb15f02sl uses the latest bicmos process. as a result, the supply current is typically 3 ma at 2.7 v. a refined charge pump supplies a well-balanced output current of 1.5 ma or 6 ma. the charge pump current is selectable by serial data. mb15f02sl is ideally suited for wireless mobile communications, such as gsm and pdc. n features ? high frequency operation: rf synthesizer: 1200 mhz max if synthesizer: 500 mhz max ? low power supply voltage: v cc = 2.4 to 3.6 v ? ultra low power supply current: i cc = 3.0 ma typ. (v cc = 2.7 v, ta = +25 c, in if, rf locking state) i cc = 3.5 ma typ. (v cc = 3.0 v, ta = +25 c, in if, rf locking state) ? direct power saving function: power supply current in power saving mode typ. 0.1 m a (v cc = 3.0 v, ta = +25 c), max. 10 m a (v cc = 3.0 v) ? dual modulus prescaler: 1200 mhz prescaler (64/65, 128/129)/500 mhz prescaler (8/9 or 16/17) ? serial input 14-bit programmable reference divider: r = 3 to 16,383 ? serial input programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 3 to 2,047 ? software selectable charge pump current ? on-chip phase control for phase comparator ? operating temperature: ta = C40 to +85 c ? pin compatible with mb15f02, mb15f02l n packages 16-pad plastic bcc (lcc-16p-m04) (fpt-16p-m05) 16-pin plastic ssop
2 mb15f02sl n pin assignments gnd rf osc in gnd if fin if v ccif ld/fout ps if d oif clock data le fin rf v ccrf xfin rf ps rf d orf 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 top view top view gnd rf clock d oif d orf 1 2 3 4 5 6 78 9 10 11 12 13 14 15 16 osc in gnd if fin if v ccif ps if ld/fout data le fin rf v ccrf ps rf xfin rf (fpt-16p-m05) (lcc-16p-m04) 16-pin ssop 16-pad bcc
3 mb15f02sl n pin descriptions pin no. pin name i/o descriptions ssop-16 bcc-16 116gnd rf C ground for rf-pll section. 21osc in i the programmable reference divider input. tcxo should be connected with a ac coupling capacitor. 32gnd if C ground for the if-pll section. 43fin if i prescaler input pin for the if-pll. connection to an external vco should be via ac coupling. 54v ccif C power supply voltage input pin for the if-pll section. 6 5 ld/fout o lock detect signal output (ld)/phase comparator monitoring output (fout). the output signal is selected by lds bit in a serial data. lds bit = h ; outputs fout signal lds bit = l ; outputs ld signal 76ps if i power saving mode control for the if-pll section. this pin must be set at l during power-on. (open is prohibited.) ps if = h ; normal mode ps if = l ; power saving mode 87do if o charge pump output for the if-pll section. phase characteristics of the phase detector can be selected via programming of the fc-bit. 98do rf o charge pump output for the rf-pll section. phase characteristics of the phase detector can be selected via programming of the fc-bit. 10 9 ps rf i power saving mode control for the rf-pll section. this pin must be set at l during power-on. (open is prohibited.) ps rf = h ; normal mode ps rf = l ; power saving mode 11 10 xfin rf i prescaler complementary input for the rf-pll section. this pin should be grounded via a capacitor. 12 11 v ccrf C power supply voltage input pin for the rf-pll section, the shift register and the oscillator input buffer. when power is off, latched data of rf-pll is lost. 13 12 fin rf i prescaler input pin for the rf-pll. connection to an external vco should be via ac coupling. 14 13 le i load enable signal inpunt (with a schmitt trigger input buffer.) when the le bit is set h, data in the shift register is transferred to the corresponding latch according to the control bit in the serial data. 15 14 data i serial data input (with a schmitt trigger input buffer.) data is transferred to the corresponding latch (if-ref counter, if-prog. counter, rf-ref. counter, rf-prog. counter) according to the control bit in the serial data. 16 15 clock i clock input for the 23-bit shift register (with a schmitt trigger input buffer.) one bit of data is shifted into the shift register on a rising edge of the clock.
4 mb15f02sl n block diagram 16 clock 15 data 14 le 10 ps rf 11 xfin rf 13 fin rf osc in fin if ps if 3-bit latch 7-bit latch 11-bit latch 3-bit latch latch selector 23-bit shift register 7-bit latch 11-bit latch phase comp. (if-pll) lock det. (if-pll) lock det. (rf-pll) charge pump (if-pll) current switch phase comp. (rf-pll) charge pump (rf-pll) current switch 2-bit latch 14-bit latch 1-bit latch 2-bit latch 14-bit latch 1-bit latch intermittent mode control (if-pll) intermittent mode control (rf-pll) schmitt circuit schmitt circuit schmitt circuit binary 7-bit swallow counter (if-pll) binary 14-bit programmable ref. counter (if-pll) c/p setting current cp binary 11-bit programmable counter (if-pll) binary 7-bit swallow counter (rf-pll) binary 11-bit programmable counter (rf-pll) prescaler (if-pll) 8/9, 16/17 prescaler (rf-pll) 64/65, 128/129 fc if sw if lds fc rf sw rf lds v ccif gnd if 5 3 fp if 8 do if ld if selector t1 t2 t1 t2 9 do rf or 6 ld / fout fr rf fp rf fr if c n 1 c n 2 and ld fr if fr rf fp if fp rf v ccrf gnd rf 7 (6) (3) (1) (12) (10) (9) (13) (14) (15) 4 2 (8) (5) (7) (2) (4) binary 14-bit programmable ref. counter (rf-pll) c/p setting current cp 1-bit latch 12 (11) 1 (16) o : ssop ( ) : bcc
5 mb15f02sl n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit remark min. max. power supply voltage v cc C0.5 +4.0 v input voltage v i C0.5 v cc +0.5 v output voltage v o gnd v cc v storage temperature tstg C55 +125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.4 3.0 3.6 v input voltage v i gnd C v cc v operating temperature ta C40 C +85 c
6 mb15f02sl n electrical characteristics (v cc = 2.4 v to 3.6 v, ta = C40 to +85 c) (continued) parameter symbol condition value unit min. typ. max. power supply current* 1 i ccif *1 fin if = 500 mhz, v ccif = 2.7 v (v ccif = 3.0 v) C 1.2 (1.5) Cma i ccrf *1 fin rf = 1200 mhz, v ccrf = 2.7 v (v ccrf = 3.0 v) C 1.8 (2.0) Cma power saving current i psif ps if = ps rf = l C 0.1* 2 10 m a i psrf ps if = ps rf = l C 0.1* 2 10 m a operating frequency fin if *3 fin if if pll 50 C 500 mhz fin rf *3 fin rf rf pll 100 C 1200 mhz osc in fosc C 3 C 40 mhz input sensitivity fin if *8 pfin if if pll, 50 w system C15 C +2 dbm fin rf pfin rf rf pll, 50 w system C15 C +2 dbm osc in v osc C0.5v cc vp-p h level input voltage data, clock, le v ih schmitt trigger input v cc 0.7 + 0.4 CC v l level input voltage v il schmitt trigger input C C v cc 0.3 C 0.4 h level input voltage ps if ,ps rf v ih Cv cc 0.7 C C v l level input voltage v il CCCv cc 0.3 h level input current data, clock, le, ps if , ps rf i ih *4 C C1.0 C +1.0 m a l level input current i il *4 C C1.0 C +1.0 h level input current osc in i ih C0C+100 m a l level input current i il *4 C C100 C 0 h level output voltage ld/fout v oh v cc = 3.0 v, i oh = C1 ma v cc C 0.4 C C v l level output voltage v ol v cc = 3.0 v, i ol = 1 ma C C 0.4 h level output voltage do if do rf v doh v cc = 3.0 v, i doh = C0.5 ma v cc C 0.4 C C v l level output voltage v dol v cc = 3.0 v, i dol = 0.5 ma C C 0.4 high impedance cutoff current do if do rf i off v cc = 3.0 v, v off = 0.5 v to v cc C 0.5 v CC2.5na h level output current ld/fout i oh *4 v cc = 3.0 v C C C1.0 ma l level output current i ol *4 v cc = 3.0 v 1.0 C C
7 mb15f02sl (continued) (v cc = 2.4 to 3.6 v, ta = C40 to +85 c) *1: conditions; fosc = 12 mhz, ta = +25 c, in locking state. *2: v ccif = v ccrf = 3.0 v, fosc = 12.8 mhz, ta = +25 c, in power saving mode. *3: ac coupling. 1000pf capacitor is connected under the condition of min. operating frequency. *4: the symbol C (minus) means direction of current flow. *5: v cc = 3.0 v, ta = +25 c (|i 3 | C |i 4 |)/[(|i 3 | + |i 4 |)/2] 100(%) *6: v cc = 3.0 v, ta = +25 c [(|i 2 | C |i 1 |)/2]/[(|i 1 | + |i 2 |)/2] 100(%) (applied to each i dol , i doh ) *7: v cc = 3.0 v, [|i do(+85 c) C i do(C40 c) |/2]/[|i do(+85 c) + i do(C40 c) |/2] 100(%) (applied to each i dol , i doh ) *8: prescaler divided ratio charge pump current fin if vfin if (min) 16/17 1.5 ma mode 50 mhz fin 500 mhz C15 dbm 6.0 ma mode 50 mhz fin 300 mhz C15 dbm 300 mhz < fin 500 mhz C10 dbm 8/9 1.5 ma mode 50 mhz fin 300 mhz* C15 dbm 300 mhz < fin 500 mhz C15 dbm 6.0 ma mode 50 mhz fin 300 mhz* C15 dbm 300 mhz < fin 500 mhz C10 dbm * : v cc = 2.7 v to 3.6 v at 500 mhz, v cc = 2.4 v to 3.6 v, ta = C40 c to +85 c at fin < 500 mhz parameter symbol condition value unit min. typ. max. h level output current do if do rf i doh *4 v cc = 3.0 v, v doh = v cc /2, ta = + 2 5 c cs bit = h C C6.0 C ma cs bit = l C C1.5 C l level output current i dol v cc = 3.0 v, v dol = v cc /2, ta = + 2 5 c cs bit = h C 6.0 C cs bit = l C 1.5 C charge pump current rate i dol /i doh i domt *5 v do = v cc /2 C 3 C % vs v do i dovd *6 0.5 v v do v cc C 0.5 v C 10 C % vs ta i dota *7 C40 c ta + 85 c, v do = v cc /2 C10C% i 1 i 1 i 3 i 2 i 2 i 4 i dol i doh 0.5 vcc/2 vcc vcc - 0.5 charge pump output voltage (v)
8 mb15f02sl n functional description the divide ratio can be calculated using the following equation: f vco = {(m n) + a} f osc ? r (a < n) f vco : output frequency of external voltage controlled oscillator (vco) m : preset divide ratio of dual modulus prescaler (8 or 16 for if-pll, 64 or 128 for rf-pll) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : reference oscillation frequency r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of if/rf-pll sections, programmable reference dividers of if/rf-pll sections are controlled individually. serial data of binary data is entered through data pin. on rising edge of clock, one bit of serial data is transferred into the shift register. when the le signal is taken high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. table 1. control bit shift register configuration control bit destination of serial data cn1 cn2 l l the programmable reference counter for the if-pll h l the programmable reference counter for the rf-pll l h the programmable counter and the swallow counter for the if-pll h h the programmable counter and the swallow counter for the rf-pll programmable reference counter msb data flow cn1,2 : control bit [table 1] r1 to r14 : divide ratio setting bits for the programmable reference counter (3 to 16,383)[table 2] t1, 2 : test purpose bit [table 3] cs : charge pump currnet select bit [table 9] x : dummy bits (set 0 or 1) note: data input with msb first. 1234567891011121314151617181920212223 c n 1 c n 2 t 1 t 2 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 c s xxxx lsb
9 mb15f02sl table 2. binary 14-bit programmable reference counter data setting note: divide ratio less than 3 is prohibited. table 3. test purpose bit setting divide ratio (r) r14r13r12r11r10r9r8r7r6r5r4r3r2r1 3 0 0 0 0 0000000011 4 0 0 0 0 0000000100 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 t1 t2 ld/fout pin state l l outputs fr if . h l outputs fr rf . l h outputs fp if . h h outputs fp rf . programmable counter lsb msb data flow cn1, cn2 : control bit [table 1] n1 to n11 : divide ratio setting bits for the programmable counter (3 to 2,047) [table 4] a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) [table 5] sw if /sw rf : divide ratio setting bit for the prescaler [table 6] (8/9 or 16/17 for the sw if , 64/65 or 128/129 for the sw rf ) fc if /fc rf : phase control bit for the phase detector (if: fc if , rf: fc rf ) [table 7] lds : ld/fout signal select bit [table 8] note: data input with msb first. 1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23 cn1 cn2 lds sw if / sw rf fc if / fc rf a1 a2 a3 a4 a5 a6 a7 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11
10 mb15f02sl table 4. binary 11-bit programmable counter data setting note: divide ratio less than 3 is prohibited. table 5. binary 7-bit swallow counter data setting note: divide ratio (a) range = 0 to 127 table 6. prescaler data setting table 7. phase comparator phase switching data setting note: z = high-impedance depending upon the vco and lpf polarity, fc bit should be set. table 8. ld/fout output select data setting divide ratio (n) n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 3 00000000011 4 00000000100 2047 1 1 1 1 1 1 1 1 1 1 1 divide ratio (a) a7 a6 a5 a4 a3 a2 a1 0 0000000 1 0000001 127 1111111 sw = h sw = l prescaler divide ratio if-pll 8/9 16/17 rf-pll 64/65 128/129 fc if, fc rf = h fc if, fc rf = l do if, do rf fr > fp h l fr = fp z z fr < fp l h vco polarity (1) (2) lds ld/fout output signal hfout (fr if /fr rf , fp if /fp rf ) signals l ld signal (1) (2) lpf output voltage vco output frequency
11 mb15f02sl table 9. charge pump current setting power saving mode (intermittent mode control circuit) table 10. ps pin setting the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pin high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. note: when power (v cc ) is first applied, the device must be in standby mode, ps = low, for at least 1 m s. ps pin must be set at l for power-on . cs current value h 6.0 ma l 1.5 ma ps pin status h normal mode l power saving mode (1) (2) (3) v cc clock data le ps on tv 3 1 m s tps 3 100 ns off (1) ps = l (power saving mode) at power-on (2) set serial data 1 m s later after power supply remains stable (v cc > 2.2 v). (3) release power saving mode (ps: l ? h ) 100 ns later after setting serial data.
12 mb15f02sl n serial data input timing lsb msb 1st data 2nd data control bit invalid data clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 on rising edge of the clock, one bit of the data is transfered into the shift register. note: le should be l when the data is transferred into the shift register. parameter min. typ. max. unit t 1 20 C C ns t 2 20 C C ns t 3 30 C C ns t 4 30 C C ns parameter min. typ. max. unit t 5 100 C C ns t 6 20 C C ns t 7 100 C C ns
13 mb15f02sl n phase comparator output waveform n otes: phase error detection range = C2 p to +2 p pulses on do if/rf signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu > 2/fosc: i. e. t wu > 156.3 ns when fosc = 12.8 mhz t wu < 4/fosc: i. e. t wl < 312.5 ns when fosc = 12.8 mhz fr if /fr rf fp if /fp rf ld (fc bit = high) (fc bit = low) d oif / d orf t wu t wl d oif / d orf ld output logic table if-pll section rf-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l
14 mb15f02sl n measurment circuit (for measuring input sensitivity fin/osc in ) s.g. s.g. 50 w 1000 pf 0.1 m f 50 w 1000 pf v ccif fout 50 w 1000 pf 1000 pf s.g. 0.1 m f v ccrf 1 2 3 controller (divide ratio setting) oscilloscope 4 5 6 7 8 16 15 14 13 12 11 10 9 d oif ps if ld/fout v ccif fin if gnd if osc in gnd rf d orf ps rf xfin rf v ccrf fin rf le data clock note: ssop-16
15 mb15f02sl n typical characteristics 1. fin input impedance 10 5 0 - 5 - 10 - 15 - 20 - 25 - 30 - 35 - 40 0 500 1000 1500 2000 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = +25 c spec rf-pll input sensitivity - input frequency input frequency fin rf (mhz) input sensitivity pfin rf (dbm) 10 5 0 - 5 - 10 - 15 - 20 - 25 - 30 0 100 200 300 400 500 600 700 800 900 1000 v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = +25 c spec if-pll input sensitivity - input frequency input sensitivity pfin if (dbm) input frequency fin if (mhz)
16 mb15f02sl 2. osc in input sensitivity 10 0 - 10 - 20 - 30 - 40 - 50 0 20 40 60 80 100 120 140 160 180 200 220 240 v cc = 2.7 v v cc = 2.4 v v cc = 3.0 v v cc = 3.6 v ta = + 25 c input sensitivity - input frequency input frequency f osc (mhz) input sensitivity v osc (dbm) spec
17 mb15f02sl 3. do output current (rf-pll) 10.00 v do - i do v do - i do - 10.00 0 .6000/div change pump output voltage v do (v) change pump output current i do (ma) change pump output voltage v do (v) change pump output current i do (ma) 4.800 2.000 /div 0 ta = +25 c v cc = 3.0 v i doh i dol 10.00 - 10.00 0 .6000/div 4.800 2.000 /div 0 ta = +25 c v cc = 3.0 v i doh i dol 1.5 ma mode 6.0 ma mode
18 mb15f02sl 4. do output current (if-pll) v do - i do v do - i do change pump output voltage v do (v) change pump output current i do (ma) change pump output voltage v do (v) change pump output current i do (ma) 10.00 - 10.00 0 .6000/div 4.800 2.000 /div 0 ta = +25 c v cc = 3.0 v i doh i dol 10.00 - 10.00 0 .6000/div 4.800 2.000 /div 0 ta = +25 c v cc = 3.0 v i doh i dol 1.5 ma mode 6.0 ma mode
19 mb15f02sl 5. fin input impedance 351.03 w - 699.34 w 100 mhz 33.18 w - 208.83 w 400 mhz 12.895 w - 94.023 w 800 mhz 1 : 2 : 3 : 4 : 10.543 w - 48.268 w 1200 mhz 1 3 2 start 100.000 000 mhz fin rf input impedance fin if input impedance stop 1 200.000 000 mhz 4 859.06 w - 1.0314 k w 50 mhz 92.656 w - 413.59 w 200 mhz 28.531 w - 204.21 w 400 mhz 1 : 2 : 3 : 4 : 20.859 w - 159.23 w 500 mhz start 50.000 000 mhz stop 500.000 000 mhz 4 1 2 3
20 mb15f02sl 6. osc in input impedance osc in input impedance 9.0005 k w - 3.281 k w 3 mhz 3.9238 k w - 4.8648 k w 10 mhz 1.4543 k w - 3.45 k w 20 mhz 1 : 2 : 3 : 4 : 395.5 w - 1.8983 k w 40 mhz 1 2 3 4 start 3.000 000 mhz stop 40.000 000 mhz
21 mb15f02sl n application example n usage precautions (1) v ccrf must equal vcc if . even if either rf-pll or if-pll is not used, power must be supplied to both v ccrf and v ccif to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. 1000 pf 0.1 m f 12345678 16 15 14 13 12 11 10 9 1000 pf output from controller 3 v mb15f02sl 1000 pf 1000 pf 3 v 0.1 m f output lockdet vco vco tcxo do rf ps rf xfin rf v ccrf fin rf le data clock do if ps if ld / fout v ccif fin if gnd if osc in gnd rf lpf lpf note: ssop-16
22 mb15f02sl n ordering information part number package remarks mb15f02slpfv1 16-pin, plastic ssop (fpt-16p-m05) MB15F02SLPV1 16-pad, plastic bcc (lcc-16p-m04)
23 mb15f02sl n package dimensions (continued) c 1999 fujitsu limited f16013s-3c-5 5.00?.10(.197?004) * 4.40?.10 6.40?.20 (.252?008) (.173?004) * .049 ?004 +.008 ?.10 +0.20 1.25 (mounting height) 0.10(.004) 0.65(.026) 0.24?.08 (.009?003) 1 8 16 9 "a" 0.10?.10 (stand off) 0.17?.03 (.007?001) m 0.13(.005) (.004?004) details of "a" part 0~8 (.018/.030) 0.45/0.75 (.020?008) 0.50?.20 0.25(.010) lead no. index dimensions in mm (inches) 16-pin, plastic ssop (fpt-16p-m05) note 1 ) * : these dimensions do not include resin protrusion. note 2 ) pins width and pins thickness include plating thickness.
24 mb15f02sl (continued) c 1999 fujitsu limited c16015s-1c-1 0.325?.10 (.013?004) 3.40(.134)typ "a" 0.40?.10 (.016?004) 3.25(.128) 0.80(.031) ref typ 4.20?.10 (.165?004) 4.55?.10 (.179?004) 0.80(.031)max mounting height 0.075?.025 (.003?001) (stand off) 0.05(.002) 6 9 1 14 9 14 1 6 0.40?.10 (.016?004) 0.75?.10 (.030?004) details of "a" part 1.725(.068) ref 1.55(.061) ref "b" details of "b" part (.024?004) 0.60?.10 (.024?004) 0.60?.10 0.65(.026) typ index area dimensions in mm (inches) 16-pad, plastic bcc (lcc-16p-m04)
mb15f02sl fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, usa tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ f0001 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB15F02SLPV1

	To Download MB15F02SLPV1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .