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semiconductor technical data dualband gsm 3.6 v ipa plastic package case 873e (tqfp32ep) order this document by MRFIC1859/d 1 32 device operating temperature range package ordering information MRFIC1859r2 t c = 35 to 100 c tqfp32ep (scale 2:1) 1 motorola wireless semiconductor solutions rf and if device data

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! the MRFIC1859 is a dualband, single supply rf power amplifier for gsm900/dcs1800 hand held radios. the onchip spur free voltage generator reduces the number of external components by eliminating the need for a negative voltage supply. the device output power can be controlled open loop without the use of directional coupler and detection diode. the MRFIC1859 is general packet radio service (gprs) compatible. the device is packaged in a tqfp32ep with exposed backside pad allowing excellent electrical and thermal performance through a solderable contact. ? single positive supply solution ? input/output external matching ? high power and efficiency ? typical 3.6 v characteristics: p out = 36.2 dbm, pae = 53% for gsm p out = 34 dbm, pae = 43% for dcs ? crosstalk harmonic leakage of 27 dbm typical (gsm) ? triple band capability simplified block diagram ing ind d2g d1g b1g b23g outg outd v ss v p v sc b23d d2d g2d b1d d1d d2b negative and positive voltage generator d1b b2b this device contains 21 active transistors. this document contains information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 2000 rev 2
MRFIC1859 2 motorola wireless semiconductor solutions rf and if device data 32 31 30 29 28 27 26 25 9 10111213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v ss d2b b2b outd outd out d outd outd m2g d2g d2g d2g d1d d1b b1d ind b23g v p gnd outg outg outg outg outg b23d d2d d2d v sc g2d d1g b1g ing pin connections exposed pad (gndon bottom) maximum ratings rating symbol value unit supply voltage v d1b,d2b v d1g,d2g, d3g,d1d, d2d,d3d 6.0 v rf input power ing, ind 12 dbm rf output power dbm gsm section outg 38 dcs section outd 36 operating case temperature range t c 35 to 100 c storage temperature range t stg 55 to 150 c thermal resistance, junction to case r q jc 15 c/w notes: 1. maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the recommended operating contitions or electrical characteristics tables. 2. meets human body model (hbm) 100 v and machine model (mm) 60 v. 3. esd data available upon request. recommended operating conditions characteristic symbol min typ max unit supply v d1b,d2b v d1g,d2g, d3g,d1d, d2d,d3d 2.8 5.5 v input power gsm ing 3.0 10 dbm input power dcs ind 5.0 12 dbm
MRFIC1859 3 motorola wireless semiconductor solutions rf and if device data electrical characteristics (v d1b, d2b = 3.6 v, v d1g,d2g,d3g = 3.6 v or v d1d,d2d,d3d = 36 v, peak measurement at 12.5% duty cycle, 4.6 ms period, t a = 25 c, unless otherwise noted.) characteristic symbol min typ max unit gsm section (p in = 3.0 dbm) frequency range bw 880 915 mhz output power p out 35 36.2 dbm power added efficiency pae 45 53 % output power @ low voltage (v d1g,d2g,d3g = 3.0 v) p out 33.5 34.7 dbm harmonic output dbc 2f o 35 30 3f o 60 45 second harmonic leakage at dcs output (crosstalk isolation) 25 20 dbm input return loss |s 11 | 12 db output power isolation with buffer on (p in = 3.0 dbm, v d1b,d2b = 3.6 v, v d1g,d2g,d3g = 0 v) p on 8.0 3.0 dbm output power isolation (p in = 3.0 dbm, v d1b,d2b = 0 v, v d1g,d2g,d3g = 0 v) p off 42 dbm noise power in rx band 925 to 960 mhz (100 khz measurement band- width) np dbm 925 to 935 mhz 90 67 935 to 960 mhz -90 79 negative voltage (p in = 2.0 dbm, v d1b, d2b = 3.0 v) v ss 4.85 v negative voltage settling time (p in = 3.0 dbm, v d1b,d2b stepped from 0 to 3.0 v) t s 0.7 2.0 m s stabilityspurious output (p out = 5.0 to 35 dbm, load vswr = 6:1 all phase angle, source vswr = 3:1, at any phase angle adjust v d1g,d2g,d3g for specified power) p spur 60 dbc load mismatch stress (p out = 5.0 to 35 dbm, load vswr = 10:1 all phase angles, 5 seconds, adjust v d1g,d2g,d3g for specified power) no degradation in output power before and after test positive voltage (p in = 3.0 dbm, v d1b = v d2b = 3.0 v) v p 6 10 v dcs section (p in = 5.0 dbm) frequency range bw 1710 1785 mhz output power p out 33 34 dbm power added efficiency pae 35 43 % output power @ low voltage (v d1d,d2d,d3d = 3.0 v) p out 31.5 32.4 dbm harmonic output dbc 2f o 40 35 3f o 35 30 input return loss |s 11 | 12 db output power isolation with buffer on (p in = 5.0 dbm, v d1b,d2b = 3.6 v, v d1d,d2d,d3d = 0 v) p on 8.0 2.0 dbm output power isolation (p in = 5.0 dbm, v d1b,d2b = 0 v, v d1d,d2d,d3d = 0 v) p off 36 dbm noise power in rx band 1805 to 1880 mhz (100 khz measurement bandwidth) np 85 71 dbm negative voltage (p in = 5.0 dbm, v d1b,d2b = 3.0 v) v ss 4.85 v negative voltage settling time (p in = 5.0 dbm, v d1b,d2b stepped from 0 to 3.0 v) t s 0.7 2.0 m s stabilityspurious output (p out = 3.0 to 33 dbm, load vswr = 6:1 all phase angle, source vswr = 3:1, at any phase angle adjust v d1d,d2d,d3d for specified power) p spur 60 dbc
MRFIC1859 4 motorola wireless semiconductor solutions rf and if device data electrical characteristics (continued) (v d1b, d2b = 3.6 v, v d1g,d2g,d3g = 3.6 v or v d1d,d2d,d3d = 36 v, peak measurement at 12.5% duty cycle, 4.6 ms period, t a = 25 c, unless otherwise noted.) characteristic unit max typ min symbol dcs section (continued) (p in = 5.0 dbm) load mismatch stress (p out = 3.0 to 33 dbm, load vswr = 10:1 all phase angles, 5 seconds, adjust v d1d,d2d,d3d for specified power) no degradation in output power before and after test positive voltage (p in = 5.0 dbm, v d1b = v d2b = 3.0 v) v p 6 10 v
MRFIC1859 5 motorola wireless semiconductor solutions rf and if device data figure 1. application schematic v bat v ramp ce band select tx en c23 100 nf r8 10k r6 10k r7 10k c19 100 nf c16 1.0 nf mc33170* mtsf3n02* s s s g d d d d bs txen bgsm bdcs v db gnd v bat ce v ss out v p inv ninv ldo c11 3.3 pf c18 47 pf t5 1.5 mm t2 47 mm t1 6.0 mm c7 22 pf c5 47 pf c6 1.0 pf c9 47 pf r2 6.8 k c10 22 pf c2 3.9 pf l3 56 nh r3 5.6k r9 1.5 k c15 12 pf c17 47 pf in gsm in dcs t9 11 mm r5 12 k l1 15 nh r4 8.2 k t10 4.0 mm l2 2.7 nh c1 47 pf c13 12 pf c12 10 nf t7 5.5 mm t8 12 mm n.c. c3 12 pf c4 4.7 pf 1 2 3 4 5 6 7 8 9 10111213141516 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 c8 6.8 pf MRFIC1859 out dcs out gsm t1, t2, t3, t4 zc = 50 w t5, t6 zc = 30 w t7, t8, t9, t10 zc = 80 w substrate fr4 er = 4.5 c2, c3, c4 are high q capacitors * products of on semiconductor t3 22 mm c21 5.6 pf c20 n.c. r1 2.2 k 1 2 3 4 5 6 78 9 10 11 12 13 14 2.5 mm 1.5 mm c14 47 pf c22 47 pf t6 t4 n.c. exposed pad (gnd on bottom)
MRFIC1859 6 motorola wireless semiconductor solutions rf and if device data gsm typical characteristics 880 880 58 880 37 880 55 880 38 35.5 38 880 f, frequency (mhz) f, frequency (mhz) pae (%) f, frequencey (mhz) f, frequency (mhz) f, frequency (mhz) figure 2. output power versus frequency f, frequency (mhz) figure 3. power added efficiency versus frequency t a = 25 c p in = 3.0 dbm figure 4. output power versus frequency figure 5. output power versus frequency figure 6. output power versus frequency figure 7. power added efficiency versus frequency p out (d b m) 3.0 v 3.6 v v bat = 4.2 v t a = 25 c p in = 3.0 dbm 3.6 v v bat = 3.0 v p in = 3.0 dbm p out (d b m) 25 c t a = 35 c 85 c v bat = 3.6 v p in = 3.0 dbm p out (dbm) 85 c p out (d b m) v bat = 4.2 v p in = 3.0 dbm 85 c pae (%) v bat = 3.6 v p in = 3.0 dbm 85 c 885 890 895 900 905 910 915 37.5 37 36.5 36 35.5 35 34.5 34 33.5 33 885 890 895 900 905 910 915 54 53 52 51 50 49 48 47 46 885 890 895 900 905 910 915 35 34.5 34 33.5 33 885 890 895 900 905 910 915 36.5 36 35.5 35 34.5 885 890 895 900 905 910 915 37.5 37 36.5 36 35.5 885 890 895 900 905 910 915 56 54 52 50 48 46 v bat = 4.2 v 3.0 v 25 c t a = 35 c 25 c t a = 35 c 25 c t a = 35 c
MRFIC1859 7 motorola wireless semiconductor solutions rf and if device data gsm typical characteristics 880 880 22 67 880 13 46 880 f, frequency (mhz) h3 (dbc) f, frequencey (mhz) f, frequency (mhz) figure 8. second harmonics versus frequency f, frequency (mhz) figure 9. third harmonics versus frequency v bat = 3.6 v p in = 3.0 dbm figure 10. positive voltage generator output versus frequency figure 11. crosstalk versus frequency h 2 (d b c) v bat = 3.6 v p in = 3.0 dbm v pos ( v ) t a = 35 c 25 c 85 c v bat = 3.6 v p in = 3.0 dbm xtalk (dbm) t a = 35 c 25 c 85 c t a = 25 c 35 c 85 c v bat = 3.6 v p in = 3.0 dbm 25 c 85 c 885 890 895 900 905 910 915 44 42 40 38 36 34 32 30 885 890 895 900 905 910 915 t a = 35 c 66 65 64 63 62 61 60 59 58 885 890 895 900 905 910 915 12 11 10 9.0 8.0 885 890 895 900 905 910 915 23 24 25 26 27 28 29 30 0 0 3.0 40 v r a m p (v) v r a m p (v) figure 12. output power versus v ramp figure 13. total current versus v ramp f = 897.5 mhz v bat = 3.6 v p in = 3.0 dbm p out , o ut p ut po w e r (d b m) t a = 35 c 25 c 85 c total current (a) t a = 35 c 25 c 85 c 10 0.5 1.0 1.5 2.0 2.5 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 35 30 25 20 15 10 5.0 0 5.0 f = 897.5 mhz v bat = 3.6 v p in = 3.0 dbm
MRFIC1859 8 motorola wireless semiconductor solutions rf and if device data dcs typical characteristics 47 1710 36 1710 f, frequency (mhz) f, frequency (mhz) 3.0 v 3.6 v v bat = 4.2 v t a = 25 c p in = 5.0 dbm 3.0 v 3.6 v p out (d b m) t a = 25 c p in = 5.0 dbm pae (%) v bat = 4.2 v 1725 1740 1755 1770 1785 35 34 33 32 31 30 1725 1740 1755 1770 178 5 46 45 44 43 42 41 40 1710 1710 48 1710 35 1710 36 33.5 f, frequency (mhz) f, frequency (mhz) f, frequency (mhz) f, frequency (mhz) figure 14. output power versus frequency figure 15. power added efficiency versus frequency figure 16. output power versus frequency figure 17. output power versus frequency figure 18. output power versus frequency figure 19. power added efficiency versus frequency v bat = 3.0 v p in = 5.0 dbm p out (d b m) 25 c t a = 35 c 85 c v bat = 3.6 v p in = 5.0 dbm p out (dbm) 85 c p out (d b m) v bat = 4.2 v p in = 5.0 dbm 85 c pae (%) v bat = 3.6 v p in = 5.0 dbm 85 c 33 32.5 32 31.5 30 34 33.5 33 32.5 32 35.5 35 34.5 34 33.5 46 44 42 40 38 36 25 c t a = 35 c 25 c t a = 35 c 25 c t a = 35 c 31 30.5 1725 1740 1755 1770 1785 1725 1740 1755 1770 178 5 34.5 1725 1740 1755 1770 1785 1725 1740 1755 1770 178 5
MRFIC1859 9 motorola wireless semiconductor solutions rf and if device data dcs typical characteristics 46 1710 49 1710 h3 (dbc) f, frequencey (mhz) f, frequency (mhz) v bat = 3.6 v p in = 5.0 dbm h 2 (d b c) t a = 25 c 35 c 85 c v bat = 3.6 v p in = 5.0 dbm 25 c 85 c 1725 1740 1755 1770 1785 47 45 43 41 39 37 35 t a = 35 c 43 40 37 34 31 28 25 1725 1740 1755 1770 1785 figure 20. second harmonics versus frequency figure 21. third harmonics versus frequency 1710 12 f, frequency (mhz) figure 22. positive voltage generator output versus frequency v bat = 3.6 v p in = 5.0 dbm v pos (v) t a = 35 c 25 c 85 c 11 10 9.0 8.0 7.0 1725 1740 1755 1770 1785 0 40 v ramp (v) figure 23. output power versus v ramp f = 1747.5 mhz v bat = 3.6 v p in = 5.0 dbm p out , output power (dbm) t a = 35 c 25 c 85 c 5.0 0.5 1.0 1.5 2.0 2.5 0 2.0 v r a m p (v) figure 24. total current versus v ramp total current (a) t a = 35 c 25 c 85 c 0.5 1.0 1.5 2.0 2.5 1.8 1.4 1.0 0.6 0.2 0 35 30 25 20 15 10 5.0 0 0.4 0.8 1.2 1.6 f = 1747.5 mhz v bat = 3.6 v p in = 5.0 dbm
MRFIC1859 10 motorola wireless semiconductor solutions rf and if device data applications information design philosophy the MRFIC1859 is a dualband single supply rf integrated power amplifier designed for use in gsm900/dcs1800 handheld radios under 3.6 v operation. with matching circuit modifications, it is also applicable for use in triple band gsm900/dcs1800/pcs1900 equipment. typical performances in gsm/dcs at 3.6 v are: gsm: 35.8 dbm with 53% pae and, dcs: 34 dbm with 43% pae. it features a large band (900 to 1800 mhz) internal negative voltage generator based on rf rectification of the input carrier after its amplification by two dedicated buffer stages (see simplified block diagram). this method eliminates spurs found on the output signal when using dc/dc converter type negative voltage generators, either on or off chip. the buffer generates also a stepup positive voltage, which can be used to drive a nmos drain switch. external circuit considerations the MRFIC1859 can be tuned by changing the values and/or positions of the appropriate external components (see figure 1: application schematic). while tuning the rf lineup, it is recommended to apply external negative supply in order to prevent any damage to the power amplifier stages. poor tuning on the input may not provide enough rf power to operate the negative voltage generator properly. input matching is a shuntc, seriesl, low pass structure for gsm and a shuntl, seriesl high pass structure for dcs. it should be optimized at the rated input power (e.g. 3.0 dbm in gsm, 5.0 dbm in dcs). since the input lines feed both 1st stages and 1st stage buffers, input matching should be iterated with buffer and q1 drain matching. note that dc blocking capacitors are included on chip. first stage buffer amplifier is tuned with a short 80 w microstrip line which may be replaced by a chip inductor. second stage buffer amplifier is supplied and matched through a discrete chip inductor. those two elements are tuned to get the maximum output from voltage generator. the overall typical buffer current (db1 + db2) is about 60 ma in gsm and 100 ma in dcs. however, the negative generator needs a settling time of 1.0 m s (see burst mode paragraph). during this transient period of time, both stages are biased to idss, which is about 200 ma each. the stepup positive voltage available at pin 2, which is approximately 10 v in each band, can be used to drive a nmos drain switch for best performances. q1 drains are supplied and matched through 80 w printed microstrip lines that could be replaced by discrete chip inductors as well. their lengths (or equivalent inductor values) are tuned by sliding the rf decoupling capacitors along to get the maximum gain on the first stages. q2 drains are supplied through 60 w printed microstrip lines that contribute also to the interstage matching in order to optimum drive to the final stages. the line length for q2g and q2d is small, so replacing it with discrete inductors is not practical. q3 stages are fed via 50 w printed microstrip lines that must handle the high supply current of that stages (2.0 amp peak) without significant voltage drop. this line can be buried in an inner layer to save pcb space or be a discrete rf choke. output matching is accomplished in both bands with two stages low pass networks. easy implementation is achieved with shunt capacitors mounted along a 50 w microstrip transmission line. value and position are chosen to reach a load line of 2.0 w while conjugating the device output parasitics. the networks must also properly terminate the second and third harmonic level. use of highq capacitors for the first output matching capacitor circuits is recommended in order to get the best output power and efficiency performances. note: the choice of output matching capacitor type and supplier will affect h2 and h3 level and efficiency, because of series resonant frequency.
MRFIC1859 11 motorola wireless semiconductor solutions rf and if device data pin function description pin no. symbol i/o description functionality 1 b23g i gsm bias for 2nd and 3rd stage bias pin of gsm second and third stages. biasing circuit is made of an internal resistor connected to rf transistor gate, and in series with a current source, connected to v ss (pin 32). an external resistor allows to tune biasing point for best gain (class ab). to switch off gsm lineup, setting this pin (and pin 18) to high impedance, which will apply v ss (5.0 v) to the gates, i.e., a voltage two times lower than fet threshold voltage. 2 v p o positive voltage a buffer amplifier is designed to produce the required negative voltage, based on rf signal amplification and rectification. also a positive voltage is generated in the same way, with rectification and a voltage doubler. this voltage supplies an op amp in order to drive a nmos as drain switch. refer to application schematic, with mc33170 and mtsf3n02 (products of on semiconductor). 3 gnd ground 4,5,6,7,8 outg o gsm output rf output and power supply for output gsm stage. supply voltage is provided through those five pins. an external matching network is required to provide optimum load impedance. 9 n.c. 10,11,12 d2g i gsm 2nd stage drain power supply for gsm second stage, and interstage matching. wire bonds and pins form the required inductor for optimum intermatching tuning. make note that decoupling capacitor on those pins needs to be placed as close as possible to the pins. refer to application schematic for component value. 13 d1d i dcs 1st stage drain power supply for dcs first stage, and interstaging matching. this pin associated with a printed line (80 w ) forms the required inductor for a proper match. 14 d1b i buffer 1st stage drain power supply for buffer amplifier first stage, and interstaging matching. this pin, associated with a printed line (80 w ) forms the required inductor for a proper match. 15 b1d i dcs 1st stage bias same function as pin 18 for dcs amplifier. 16 ind i dcs rf input rf input for dcs amplifier. a series inductor or line and a parallel inductor are required for a proper matching to 50 w and maximum gain. see application circuit. 17 ing i gsm rf input rf input for gsm amplifier. an inductor and a capacitor are required for a proper matching to 50 w and maximum gain. see application circuit. 18 b1g i gsm 1st stage bias bias pin of gsm first stage and associated buffer stage. biasing circuit is made of an internal resistor connected to rf transistor gate, and in series with a current source, connected to v ss (pin 32). an external resistor allows to tune biasing point for best gain (class ab). see comments on pin 1. 19 d1g i gsm 1st stage drain power supply for gsm first stage, and interstage matching. this pin, associated with a printed line (80 w ) form the required inductor for a proper match. 20 g2d i dcs 2nd stage gate access to dcs 2nd stage gate. a shunt capacitor connected to this pin contributes to the interstage matching between 1st and 2nd dcs stages. 21 v sc o check for negative voltage an opened drain transistor connected to this pin, with v ss as gate voltage, gives a checking signal for negative voltage generation. used in application circuit to forbid on state to the nmos drain switch when v ss is not working. prevents ic degradation when bias is not present. this pin is not used with mc33170 which has its own protection circuit. 22,23 d2d i dcs 2nd stage drain power supply for dcs driver stage, and interstaging matching. these pins form the required inductor for a proper match. 24 b23d i dcs bias for 2nd and 3rd stage same as pin 1 for dcs amplifier. 25,26,27, 28,29 outd o dcs rf output rf output and power supply for output dcs stage. supply voltage is provided through those five pins. an external matching network is required to provide optimum load impedance. 30 b2b i buffer 2nd state bias like pins 1, 15, and 18, this is a bias pin. pin 30 is used to bias 2nd stage of buffer amplifier. 31 d2b i buffer 2nd stage drain drain supply and matching of buffer amplifier to maximize v ss and v p voltages.
MRFIC1859 12 motorola wireless semiconductor solutions rf and if device data pin function description (continued) pin no. functionality description i/o symbol 32 v ss o negative voltage a buffer amplifier is designed to produce the required negative voltage, based on rf signal amplification with a two stages wide band amplifier and rectification of the resulting signal. an external zener diode is used to regulate this voltage and provide to the gates a stabilized biasing voltage. v ss is also used to switch off the unused amplifier. refer to bias pins 1, 18 and 15, 24. exposed pad gnd i main gnd the bottom pad of the tqfp32ep package is used for electrical/rf grounding and thermal dissipation. the pcb pattern where it fits has to be tailored for good ground and thermal continuity (with many ground via holes). tuning methodology the following section gives the user some guidelines and hints to tune and optimize the MRFIC1859 operation inside their own radio pcb. first of all, one must keep in mind that negative and positive voltage generation is based on rf carrier rectification. this means that rf input signal must always be present when running the part as a standalone solution. therefore, in order to ease the tuning phase, it is recommended to apply the negative voltage externally in order to avoid any damage to the large rf mesfet transistors. this is particularly true if one uses the complete application with mc33170 (product of on semiconductor) as control ic to do the optimization. in that case, both negative and positive voltage should be provided externally. the rf decoupling capacitors have been selected as 47 pf for gsm band (c17, c14, c22, c9. c1, and c8) and 22 pf or 12 pf for dcs band (c10, c15, and c13). but those can be optimized depending on their size and source, for example 12 pf were used at some places for dcs to provide better decoupling of the harmonics too, thus providing some extra performance. the recommended tuning procedure consists of several steps that need to be performed in sequential order. several interations can be performed if appropriate. due to low interaction between lineups, each band can be tuned independently. ? optimize the buffer operation using d1b (t8 line) and d2b matching (l3 inductor). simultaneously, tune gsm or dcs input matching using l1, c21 or l2, t10, respectively. check the margin on p in to generate v ss and v p (those voltages should still meet their specification with a 5.0 db reduction in p in ). a small shunt capacitor can be placed on v p to maximize that voltage. ? optimize rf line up linear gain using d1g, d2g matching (t9 line) or d1d, d2d, g2d matching (t7 line, c8) for gsm or dcs lineup, respectively. the goal is to maximize and center small signal gain. p in has to be reduced for this exercise, hence the negative voltage needs to be applied externally. a broad band measurement is helpful to visualize the frequency response. linear gain should peak at around 40 db for gsm and 32 db for dcs. the input matching has to be checked again and eventually refined during this step. ? optimize output matching using t4, c3, t1, c4 and t2 for gsm or t6, c2, t5, c6, t3 for dcs, respectively. those elements set the p out /pae tradeoff and harmonics rejection performance. ? finally, one can iterate some of the above steps to fine tune rf behavior and also to find the best configuration for crosstalk and harmonics content reduction. for example, d2b inductor l3 and v ss decoupling capacitor c11 have a small influence on the gsm second harmonic leaking through the dcs output. the nominal impedance seen from the ipa package pins have been measured on the demoboard (after removing the MRFIC1859) and are listed in the following table. they can be taken as a starting point for the optimization. also this gives the equivalent lumped element if one uses a lumped element instead of microstrip line. impedance on the different gsm i/os: (expressed in w at 900 mhz) ing = 16.2 + j83.5 outg = 1.9 j2.3 d2g = close to 0 since decoupled as short as possible d1g = 1 + j19.8 (3.5 nh) d1b = 1.2 + j28.7 (5.0 nh) d2b = infinite since 56 nh behaves as choke impedance on the different dcs i/os: (expressed in w at 1750 mhz) ind = 12.5 + j36.5 outd = 3.6 j4.4 d2d = close to 0 since decoupled as short as possible g2d = 0.9 + j6.8 (0.64 nh) d1d = 1.1 + j20.8 (1.9 nh) d1b = 8.8 + j84.7 (7.6 nh) d2b = infinite since 56 nh behaves as choke one should note that except for rf in /rf out impedance, all others should be oin theoryo pure reactive shunt elements. the fact that their resistive part is not zero is linked to the finite quality factor of the equivalent inductor and also to the limited accuracy of the measurement (when close to the smith chart border). control considerations the MRFIC1859 application uses drain control technique developed for our generations of gaas ipas. this method relies on the fact that for an rf power amplifier operating in saturation mode, the rf output power is proportional to the square of the amplifier drain voltage: p out (watt) = k * v d (v) * v d (v). a dedicated control ic mc33170 has been designed to manage all those control, biasing and band selection functions. when the emitting order is sent (txen = high), the mc33170 activates the power supply v dbuf of the negative voltage generator nvg (v dbuf = v bat ), involving the presence of v neg as well as a positive v p of about 9.0 v. once v neg
MRFIC1859 13 motorola wireless semiconductor solutions rf and if device data detected and regulated at 5.0 v, the mc33170 enables a nchannel mosfet to be driven. the nmos is used as a ballast transistor whose drainsource resistance is controlled by v ramp . this allows to supply the pa with a voltage from 0 v (v ramp = 0 v) to v bat (v ramp = 2.0 v) and hence to control the output power. such a way of control provides an excellent predictability of the rf output power (since the output voltage is proportional to the drain voltage) and eliminates the need for a power or current detection loop. the band selection is achieved by setting the bs pin of the mc33170 to 0 v (gsm) or 1.0 v (dcs), hence biasing the gsm or dcs transistors through biasgsm and biasdcs pins. burst mode in order to perform burst mode measurements, the following time can be used as a guideline. ce txen (& p in ) v ramp 2.0 v 0 v 2.0 v 0 v 2.0 v 0 v 10 m s 1.0 m s figure 25. first the mc33170 must be awaken through ce to activate its low drop out regulator. the bs pin has also to be set according to the selected frequency band. then txen is set high which supply the buffer stages and activates the negative and positive voltage generation. txen signal can be used to switch the input power (using a driver or attenuator) in order to provide higher isolation for on/off burst dynamic. v ramp (pin 1) can be applied soon after txen since the internal negative voltage generator settles in less than 1.0 m s. references (motorola application notes) an1599 power control with the mrfic0913 gaas integrated power amplifier and mc33169 support ic. an1697 gsm900/dcs1800 dualband 3.6 v power amplifier solution with open loop control scheme.
MRFIC1859 14 motorola wireless semiconductor solutions rf and if device data plastic package case 873e02 (tqfp32ep) issue a outline dimensions e1 d e ???? ???? dim min max millimeters a 1.13 a1 0.039 0.089 a2 0.95 1.05 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.2 c1 0.09 0.16 d 7 bsc d1 5 bsc e 0.5 bsc e e1 l 0.45 0.75 l1 r1 0.08 r2 0.08 0.2 s 0.2 07 0 11 13 11 13 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b and d to be determined at datum plane h. 4. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar cannot be located on the lower radius or the foot. minimum space between a protrusion and adjacent lead is 0.07mm 6. exact shape of corners is optional. ab 0.2 d c 0.25 d gg a 6 32 1 4x b ab 0.2 d h 4x c seating plane 28x e f 32x b ab m 0.08 d c 0.08 c h a a2 a1 2 r1 r2 gage plane s l (l1) c1 c (b) b1 base metal plating 1 2 3 1 ref 4x e/2 section gg detail f 1 3 7 bsc 5 bsc m n exposed flag view jj m 2.09 2.19 n 2.09 2.19 e/2 25 24 d/2 e1/2 d1/2 d1 8 9 16 j j
MRFIC1859 15 motorola wireless semiconductor solutions rf and if device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo para meters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all ope rating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motoro la, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : motorola japan ltd.; sps, technical information center, 3201, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 minamiaz abu. minatoku, tokyo 1068573 japan. 8 1334403569 technical information center: 18005216274 asia / pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, 2, dai king street, tai po industrial estate, tai po, n.t., hong kong. 85226668334 home page : http://www.motorola.com/semiconductors/ MRFIC1859/d ?

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