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preliminary technical data blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin embedded processor adsp-bf512/bf514/bf516/bf518(f) rev. pre information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 analog devices, inc. all rights reserved. features up to 400 mhz high-performance blackfin ? processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of programming and comp iler-friendly support advanced debug, trace, an d performance monitoring wide range of operating voltages. see operating conditions on page 23 168-ball csp_bga 176-lead lqfp with exposed pad memory 116k bytes of on-chip memory external memory controller wi th glueless support for sdram and asynchronous 8-bit and 16-bit memories optional 4 mbit on-chip spi flash with boot option flexible booting options from internal spi flash, otp mem- ory, external spi/parallel memories, or from spi/uart host devices code security with lockbox tm secure technology one-time-programmable (otp) memory memory management unit providing memory protection peripherals ieee 802.3-compliant 10/100 ethernet mac with ieee 1588 support (ADSP-BF518 only) parallel peripheral interface (ppi), supporting itu-r 656 video data formats 2 dual-channel, fu ll-duplex synchronous serial ports (sports), supporting 8 stereo i 2 s channels 12 peripheral dmas, 2 mastered by the ethernet mac 2 memory-to-memory dmas with external request lines event handler with 56 interrupt inputs 2 serial peripheral interfaces (spi) removable storage interface (rsi) controller for mmc, sd, sdio, and ce-ata 2 uarts with irda ? support two-wire interface (twi) controller eight 32-bit timers/counters with pwm support three-phase 16-bit center-based pwm unit 32-bit general-purpose counter real-time clock (rtc) and watchdog timer 32-bit core timer 40 general-purpose i/os (gpios) debug/jtag interface on-chip pll capable of 0.5 to 64 frequency multiplication jtag test and emulation peripheral access bus otp 3-phase pwm watchdog timer rtc twi sport1-0 rsi (sdio) ppi uart1C0 spi0 4 mbit spi flash (see table 1) spi1 timer7C0 counter emac boot rom dma external bus interrupt controller dma controller l1 data memory l1 instruction memory 16 dma core bus external access bus external port flash, sdram control ports b
rev. pre | page 2 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data table of contents general description ................................................. 3 portable low-power architecture ............................. 3 system integration ................................................ 3 processor peripherals ............................................. 3 blackfin processor core .......................................... 3 memory architecture ............................................ 5 dma controllers .................................................. 9 real-time clock ................................................... 9 watchdog timer ................................................ 10 timers ............................................................. 10 3-phase pwm .................................................... 10 general-purpose (gp) counter .............................. 11 serial ports ........................................................ 11 serial peripheral interface (spi) ports ...................... 11 uart ports ...................................................... 11 twi controller interface ...................................... 12 rsi interface ...................................................... 12 10/100 ethernet mac .......................................... 12 ieee 1588 support .............................................. 13 ports ................................................................ 13 parallel peripheral interface (ppi) ........................... 14 code security with lockbox secure technology ......... 14 dynamic power management ................................ 14 voltage regulation interface .................................. 16 clock signals ..................................................... 16 booting modes ................................................... 17 instruction set description .................................... 18 development tools .............................................. 18 designing an emulator-compatible processor board (target) ................................... 19 related documents .............................................. 19 lockbox secure technology disclaimer .................... 19 signal descriptions ................................................. 20 specifications ........................................................ 23 operating conditions ........................................... 23 electrical characteristics ....................................... 25 absolute maximum ratings ................................... 26 package information ............................................ 26 esd sensitivity ................................................... 26 timing specifications ........................................... 27 output drive currents ......................................... 49 power dissipation ............................................... 51 test conditions .................................................. 51 thermal characteristics ........................................ 54 176-lead lqfp lead assignment . .............................. 55 168-ball csp_bga ball assignment ... ......................... 57 outline dimensions ................................................ 60 surface mount design .......................................... 61 ordering guide ..................................................... 62 revision history 03/09revision pre: numerous small clarifications and corrections throughout document. updated 176-lead lqfp package outl ine, clarifying location of exposed pad on bottom of package........................ page 60
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 3 of 62 | march 2009 general description the adsp-bf512/bf514/bf516/ bf518(f) processors are members of the blackfin family of products, incorporating the analog devices/intel micro si gnal architecture (msa). blackfin processors combine a dual-mac state-of-the-art signal processing engine, the advantages of a clean, orthogonal risc- like microprocessor instruction se t, and single-instruction, mul- tiple-data (simd) multimedia capabilities into a single instruction-set architecture. the processors are completely code compatible with other blackfin processors. by integrating a rich set of indu stry-leading system peripherals and memory, blackfin processors are the platform of choice for next-generation applications that require risc-like program- mability, multimedia support , and leading- edge signal processing in one integrated package. portable low-power architecture blackfin processors provide world-class power management and performance. they are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of oper ation to significantly lower overall power consumption. this capability can result in a substantial reduc- tion in power consum ption, compared with just varying the frequency of operation. this a llows longer battery life for portable appliances. system integration the adsp-bf512/bf514/bf516/ bf518(f) processors are highly integrated system-on-a-chip solutions for the next gener- ation of embedded network connected applications. by combining industry-standard interfaces with a high perfor- mance signal processing core, co st-effective applications can be developed quickly, without the ne ed for costly external compo- nents. the system peripherals include an ieee-compliant 802.3 10/100 ethernet mac with ieee-1588 support (adsp- bf518/ADSP-BF518f only), an rs i controller, a twi control- ler, two uart ports, two spi po rts, two serial ports (sports), nine general purpose 32-bit timers (eight with pwm capability), three-phase pwm for motor control, a real-time clock, a watch- dog timer, and a parallel peripheral interface (ppi). processor peripherals the adsp-bf512/bf514/bf516/bf518 (f) processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overa ll system performance (see figure 1 on page 4 ). the processors contain dedicated network communica- tion modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or extern al sources, and power manage- ment control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. all of the peripherals, except fo r the general-purpose i/o, rotary counter, twi, three-phase pwm, real-time clock, and timers, are supported by a flexible dma structure. there are also sepa- rate memory dma channels dedicated to data transfers between the processor's variou s memory spaces, including external sdram and asynchronous memory. multiple on-chip buses provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. blackfin processor core as shown in figure 1 on page 4 , the blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, an d a 40-bit shifter. the compu- tation units process 8-, 16-, or 32-b it data from the register file. table 1. processor comparison feature adsp-bf512 adsp-bf512f adsp-bf514 adsp-bf514f adsp-bf516 adsp-bf516f ADSP-BF518 ADSP-BF518f ieee-1588 CCCCCC11 ethernet mac CCCC1111 rsi CC111111 twi 11111111 sports 22222222 uarts 22222222 spis 22222222 gp timers 88888888 watchdog timers 11111111 rtc 11111111 ppi 11111111 internal 4mbit spi flash C1C1C1C1 rotary counter 11111111 3-phase pwm pairs 33333333 gpios 40 40 40 40 40 40 40 40 memory (bytes) l1 instruction sram 32k l1 instruction sram/cache 16k l1 data sram 32k l1 data sram/cache 32k l1 scratchpad 4k l3 boot rom 32k maximum speed grade 400 mhz package options 176-lead lqfp 168-ball csp_bga
rev. pre | page 4 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data the compute register file contains eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compar e/select and vector search instructions. for certain instructions, two 16- bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). if the second alu is used, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). figure 1. blackfin processor core sequencer align decode loop buffer 16 16 8 88 8 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 5 of 62 | march 2009 blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram and cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and co re resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the adsp-bf512/bf514/bf516/bf 518(f) processors view memory as a single unified 4g byte address space, using 32-bit addresses. all resources, includ ing internal memory, external memory, and i/o control registers, occupy separate sections of this common address space. th e memory portions of this address space are arranged in a hi erarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or sram, and larger, lower-cost and performance off-chip memory systems. see figure 2 . the on-chip l1 memory system is the highest-performance memory available to the blackfin processor. the off-chip mem- ory system, accessed through the external bus interface unit (ebiu), provides expansion wi th sdram, flash memory, and sram, optionally accessing up to 132m bytes of physical memory. the memory dma controller prov ides high-bandwidth data- movement capability. it can perform block transfers of code or data between the internal memory and the external memory spaces. internal (on-chip) memory the adsp-bf512/bf514/bf516/bf 518(f) processors have three blocks of on-chip memory providing high-bandwidth access to the core. the first block is the l1 instruction memory, consisting of 48k bytes sram, of which 16k bytes can be configured as a four-way set-associative cache. this memory is accessed at full processor speed. the second on-chip memory block is the l1 data memory, con- sisting of up to two banks of up to 32k bytes each. each memory bank is configurable, offering both cache and sram functional- ity. this memory block is accessed at full processor speed. the third memory block is a 4k byte scratchpad sram which runs at the same speed as the l1 memories, but is only accessible as data sram and cannot be configured as cache memory. external (off-chip) memory external memory is accessed via the ebiu. this 16-bit interface provides a glueless connection to a bank of synchronous dram (sdram) as well as up to four banks of asynchronous memory devices including flash, epro m, rom, sram, and memory mapped i/o devices. the sdram controller can be prog rammed to interface to up to 128m bytes of sdram. a separa te row can be open for each sdram internal bank and the sdram controller supports up to four internal sdram banks, improving overall performance. figure 2. adsp-bf512/bf514/bf516/bf518(f) internal/external memory map re s s s s s s s s s s s s s s s s s s s s s s s s s 3 s s s s s s s s s 8 s s s s 8 8 8 8 3 s s 8 s s 8 s s s s 3 s 8 s 8
rev. pre | page 6 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data the asynchronous memory cont roller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. each bank occupies a 1m byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1m byte of memory. flash memory the adsp-bf512f/adsp-bf514f/adsp-bf516f/ ADSP-BF518f processors contai n a spi flash memory within the package of the processo r and connected to spi0. the spi flash memory has a 4m bi t capacity and 1.8v (nominal) operating voltage. the prog ram/erase endurance is 100,000 cycles per block, and this me mory has greater than 100 years data retention capability. also in cluded are support for software write protection and support fo r fast erase and byte-program. the processors internally connec t to the flash memory die with the mosi, miso, spissel, and spi_clk signals similar to an external spi flash. to further provide a secure processing envi- ronment, these internally connected signals are not exposed outside of the package. for this reason, programming the adsp-bf51xf flash memory is performed by running code on the processor. it cannot be programmed from external signals and data transfers between the spi flash and the processor can- not be probed externally. one-time programmable memory the processors have 64k bits of one-time programmable non- volatile memory that can be pr ogrammed by the developer only one time. it includes the array and logic to support read access and programming. additiona lly, its pages can be write protected. otp enables developers to store both public and private data on-chip. in addition to storing public and private key data for applications requiring security, it also allows developers to store completely user-defin able data such as customer id, product id, and mac address. hence generic parts can be shipped which are then programmed and protected by the developer within this non-volatile memory. i/o memory space the processors do not define a se parate i/o space. all resources are mapped through the flat 32-bit address space. on-chip i/o devices have their control re gisters mapped into memory- mapped registers (mmrs) at ad dresses near the top of the 4g byte address space. these ar e separated into two smaller blocks, one which contains the control mmrs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. booting the processors contain a small on-chip boot kernel, which con- figures the appropriate peripheral for booting. if the processors are configured to boot from boot rom memory space, the pro- cessor starts executing from th e on-chip boot rom. for more information, see booting modes on page 17 . event handling the event controller handles all asynchronous and synchronous events to the processor. the pr ocessors provide event handling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. pri- oritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. the con- troller provides support for fi ve different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor through the jtag interface. ? reset C this event resets the processor. ? nonmaskable interrupt (nmi ) C the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. ? exceptions C events that occur synchronously to program flow; that is, the exception is taken before the instruction is allowed to complete. conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return -from-event inst ruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the event controller consists of two stages, the core event con- troller (cec) and the system in terrupt controller (sic). the core event controller works with the system interrupt controller to prioritize and control all sy stem events. conceptually, inter- rupts from the peripherals ente r into the sic, and are then routed directly into the general-purpose interrupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest-priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peri pherals of the processors. table 2 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities.
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 7 of 62 | march 2009 system interrupt controller (sic) the system interrupt controller provides the mapping and rout- ing of events from the many peri pheral interrupt sources to the prioritized general-purpose interrupt inputs of the cec. although the processors provid e a default mapping, the user can alter the mappings and prioriti es of interrupt events by writ- ing the appropriate values in to the interrupt assignment registers (sic_iarx). table 3 describes the inputs into the sic and the default mappings into the cec. event control the adsp-bf512/bf514/bf516/bf518( f) processors provide a very flexible mechanism to contro l the processing of events. in the cec, three registers are us ed to coordinate and control events. each register is 16 bits wide. ? cec interrupt latch register (ilat) C indicates when events have been latched. the appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. this register is updated automatically by the co ntroller, but it may be writ- ten only when its corresponding imask bit is cleared. ? cec interrupt mask register (imask) C controls the masking and unmasking of individual events. when a bit is set in the imask register, that event is unmasked and is processed by the cec when a sserted. a cleared bit in the imask register masks the even t, preventing the processor from servicing the event even though the event may be latched in the ilat register. th is register ma y be read or written while in supervisor mode. (note that general-pur- pose interrupts can be globally enabled and disabled with the sti and cli instructions, respectively.) ? cec interrupt pending register (ipend) C the ipend register keeps track of all ne sted events. a set bit in the ipend register indicates the event is currently active or nested at some level. this re gister is updated automatically by the controller but may be read while in supervisor mode. table 2. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test controlemu 1 reset rst 2 nonmaskable interrupt nmi 3exception evx 4 reserved 5 hardware error ivhw 6 core timer ivtmr 7 general-purpose interrupt 7 ivg7 8 general-purpose interrupt 8 ivg8 9 general-purpose interrupt 9 ivg9 10 general-purpose interrupt 10 ivg10 11 general-purpose interrupt 11 ivg11 12 general-purpose interrupt 12 ivg12 13 general-purpose interrupt 13 ivg13 14 general-purpose interrupt 14 ivg14 15 general-purpose interrupt 15 ivg15 table 3. peripheral interrupt assignment peripheral interrupt event general purpose interrupt (at reset) peripheral interrupt id default core interrupt id sic registers pll wakeup interrupt ivg7 0 0 iar0 imask0 and isr0 dma error 0 (generic) ivg7 1 0 iar0 imask0 and isr0 dmar0 block interrupt ivg7 2 0 iar0 imask0 and isr0 dmar1 block interrupt ivg7 3 0 iar0 imask0 and isr0 dmar0 overflow error ivg7 4 0 iar0 imask0 and isr0 dmar1 overflow error ivg7 5 0 iar0 imask0 and isr0 ppi error ivg7 6 0 iar0 imask0 and isr0 mac status ivg7 7 0 iar0 imask0 and isr0 sport0 status ivg7 8 0 iar1 imask0 and isr0 sport1 status ivg7 9 0 iar1 imask0 and isr0 ptp error interrupt ivg7 10 0 iar1 imask0 and isr0 reserved ivg7 11 0 iar1 imask0 and isr0 uart0 status ivg7 12 0 iar1 imask0 and isr0 uart1 status ivg7 13 0 iar1 imask0 and isr0 rtc ivg8 14 1 iar1 imask0 and isr0 dma 0 channel (ppi) ivg8 15 1 iar1 imask0 and isr0 dma 3 channel (sport0 rx) ivg9 16 2 iar2 imask0 and isr0
rev. pre | page 8 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data dma 4 channel (sport0 tx/rsi) ivg9 17 2 iar2 imask0 and isr0 dma 5 channel (sport1 rx/spi1) ivg9 18 2 iar2 imask0 and isr0 dma 6 channel (sport1 tx) ivg9 19 2 iar2 imask0 and isr0 twi ivg10 20 3 iar2 imask0 and isr0 dma 7 channel (spi0) ivg10 21 3 iar2 imask0 and isr0 dma8 channel (uart0 rx) ivg10 22 3 iar2 imask0 and isr0 dma9 channel (uart0 tx) ivg10 23 3 iar2 imask0 and isr0 dma10 channel (uart1 rx) ivg10 24 3 iar3 imask0 and isr0 dma11 channel (uart1 tx) ivg10 25 3 iar3 imask0 and isr0 otp memory interrupt ivg11 26 4 iar3 imask0 and isr0 gp counter ivg11 27 4 iar3 imask0 and isr0 dma1 channel (mac rx) ivg11 28 4 iar3 imask0 and isr0 port h interrupt a ivg11 29 4 iar3 imask0 and isr0 dma2 channel (mac tx) ivg11 30 4 iar3 imask0 and isr0 port h interrupt b ivg11 31 4 iar3 imask0 and isr0 timer 0 ivg12 32 5 iar4 imask1 and isr1 timer 1 ivg12 33 5 iar4 imask1 and isr1 timer 2 ivg12 34 5 iar4 imask1 and isr1 timer 3 ivg12 35 5 iar4 imask1 and isr1 timer 4 ivg12 36 5 iar4 imask1 and isr1 timer 5 ivg12 37 5 iar4 imask1 and isr1 timer 6 ivg12 38 5 iar4 imask1 and isr1 timer 7 ivg12 39 5 iar4 imask1 and isr1 port g interrupt a ivg12 40 5 iar5 imask1 and isr1 port g interrupt b ivg12 41 5 iar5 imask1 and isr1 mdma stream 0 ivg13 42 6 iar5 imask1 and isr1 mdma stream 1 ivg13 43 6 iar5 imask1 and isr1 software watchdog timer ivg13 44 6 iar5 imask1 and isr1 port f interrupt a ivg13 45 6 iar5 imask1 and isr1 port f interrupt b ivg13 46 6 iar5 imask1 and isr1 spi0 status ivg7 47 0 iar5 imask1 and isr1 spi1 status ivg7 48 0 iar6 imask1 and isr1 reserved ivg7 49 0 iar6 imask1 and isr1 reserved ivg7 50 0 iar6 imask1 and isr1 rsi interrupt0 ivg10 51 3 iar6 imask1 and isr1 rsi interrupt1 ivg10 52 3 iar6 imask1 and isr1 pwm trip interrupt ivg10 53 3 iar6 imask1 and isr1 pwm sync interrupt ivg10 54 3 iar6 imask1 and isr1 ptp status interrupt ivg10 55 3 iar6 imask1 and isr1 table 3. peripheral interrupt assignment (continued) peripheral interrupt event general purpose interrupt (at reset) peripheral interrupt id default core interrupt id sic registers
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 9 of 62 | march 2009 the sic allows further control of event processing by providing three pairs of 32-bit interrupt cont rol and status re gisters. each register contains a bit correspond ing to each of the peripheral interrupt events shown in table 3 on page 7 . ? sic interrupt mask registers (sic_imaskx) C control the masking and unmasking of each peripheral interrupt event. when a bit is set in these regist ers, that peripheral event is unmasked and is processed by the system when asserted. a cleared bit in the register masks the peripheral event, pre- venting the processor from servicing the event. ? sic interrupt status registers (sic_isrx) C as multiple peripherals can be ma pped to a single event, these registers allow the software to determ ine which peripheral event source triggered the interrupt. a set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. ? sic interrupt wakeup enable registers (sic_iwrx) C by enabling the correspo nding bit in these registers, a periph- eral can be configured to wake up the processor, should the core be idled when the event is generated. for more infor- mation see dynamic power management on page 14 . because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requ ires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec recogn izes and queues the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general- purpose interrupt to the ipend ou tput asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the state of the processor. dma controllers the adsp-bf512/bf514/bf516/bf 518(f) processors have multiple, independent dma chan nels that support automated data transfers with minimal ov erhead for the processor core. dma transfers can occur between the processor's internal memories and any of its dma-ca pable peripherals. addition- ally, dma transfers can be acco mplished between any of the dma-capable peripherals and exte rnal devices connected to the external memory interfaces, including the sdram controller and the asynchronous memory controller. dma-capable peripherals include the ethernet mac, rsi, sports, spis, uarts, and ppi. each individual dma-capable peripheral has at least one dedicated dma channel. the processors dma controlle r supports both one-dimen- sional (1-d) and two-dimensio nal (2-d) dma transfers. dma transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. the 2-d dma capability support s arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 32k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video appl ications where data can be de- interleaved on the fly. examples of dma types suppo rted by the dma controller include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a linked list of descriptors ? 2-d dma using an array of descriptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, there are two memory dma channels that transfer data between the vari- ous memories of the processor sy stem. this enables transfers of blocks of data between any of the memoriesincluding external sdram, rom, sram, and flash memorywith minimal pro- cessor intervention. memory dm a transfers can be controlled by a very flexible descriptor-b ased methodology or by a stan- dard register-based autobuffer mechanism. the processors also have an external dma controller capability via dual external dma request signals when used in conjunc- tion with the external bus interface unit (ebiu). this functionality can be used when a high speed interface is required for external fifos and high bandwidth communica- tions peripherals. it allows co ntrol of the number of data transfers for memory dma. the nu mber of transfers per edge is programmable. this feature can be programmed to allow mem- ory dma to have an increased priority on the external bus relative to the core. real-time clock the real-time clock (rtc) provides a robust set of digital watch features, including current time , stopwatch, and alarm. the rtc is clocked by a 32.768 khz crystal external to the proces- sors. the rtc peripheral has a de dicated power suppl y so that it can remain powered up and clocke d even when the rest of the processor is in a low-power st ate. the rtc provides several programmable interrupt options, including interrupt per sec- ond, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a pro- grammed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second co unter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day. the second alarm is for a day and time of that day.
rev. pre | page 10 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data the stopwatch function counts down from a programmed value, with one-second resolu tion. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like the other peripherals, the rtc can wake up the processor from sleep mode upon generati on of any rtc wakeup event. additionally, an rtc wakeup ev ent can wake up the processor from deep sleep mode or cause a transition from the hibernate state. connect rtc signals rtxi and rtxo with external compo- nents as shown in figure 3 . watchdog timer the adsp-bf512/bf514/bf516/bf518 (f) processors include a 32-bit timer that can be used to implement a software watchdog function. a software watchdog ca n improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (nmi), or general- purpose interrupt, if the timer ex pires before bein g reset by soft- ware. the programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the progra mmed value. this protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a hardware reset, the watchdog timer resets both the core and the proc essor peripherals. after a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the system clock (sclk), at a maximum frequency of f sclk . timers there are nine general-purpose programmable timer units in the adsp-bf512/bf514/bf516/bf 518(f) processors. eight timers have an external signal th at can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events . these timers can be synchro- nized to an external clock input to the several other associated pf signals, an external clock in put to the ppi_clk input signal, or to the internal sclk. the timer units can be used in conjunction with the two uarts to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timers can generate interrupt s to the processor core provid- ing periodic events for synchron ization, either to the system clock or to a count of external signals. in addition to the eight genera l-purpose progra mmable timers, a ninth timer is also provided. th is extra timer is clocked by the internal processor clock and is ty pically used as a system tick clock for generation of operatin g system periodic interrupts. 3-phase pwm features of the 3-phase pwm generation unit are: ? 16-bit center-based pwm generation unit ? programmable pwm pulse width ? single/double update modes ? programmable dead time and switching frequency ? twos-complement implementa tion which permits smooth transition to full on and full off states ? possibility to sync hronize the pwm generation to an exter- nal synchronization ? special provisions for bdcm operation (crossover and output enable functions) ? wide variety of special switched reluctance (sr) operating modes ? output polarity and clock gating control ? dedicated asynchronous pwm shutdown signal the processors integrate a flexible and programmable 3-phase pwm waveform generator that ca n be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac inductio n (acim) or permanent magnet synchronous (pmsm) motor cont rol. in addition, the pwm block contains special functions that considerably simplify the generation of the required pw m switching patterns for control of the electronically commutated motor (ecm) or brushless dc motor (bdcm). software can enable a special mode for switched reluctan ce motors (srm). the six pwm output signals consis t of three high-side drive sig- nals (pwm_ah, pwm_bh, and pwm_ch) and three low-side drive signals (pwm_al, pwm_bl, and pwm_cl). the polarity of the generated pwm signal be set with software, so that either active hi or active lo pwm patterns can be produced. the switching frequency of the generated pwm pattern is pro- grammable using the 16-bit pwmtm register. the pwm generator can operate in single update mode or double update figure 3. external components for rtct rtxo c1 c2 x1 s ugge s ted component s : x1 ecl iptek e c 38 j (through-hole package) or ep s onmc40512pfload( s urface-mount package) c1 22 p f c2 22 p f r1 10 m
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 11 of 62 | march 2009 mode. in single update mode the duty cycle values are program- mable only once per pwm period , so that the resultant pwm patterns are symmetrical about the midpoint of the pwm period. in the double update mode, a second updating of the pwm registers is implemented at the midpoint of the pwm period. in this mode, it is po ssible to produce asymmetrical pwm patterns that produce lowe r harmonic distortion in 3-phase pwm inverters. general-purpose (gp) counter a 32-bit gp counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or man- ual thumb wheels. the counter can also operate in general- purpose up/down count modes. then, count direction is either controlled by a level-sensitive input signal or by two edge detectors. a third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three signals have a programmable debouncing circuit. an internal signal forwarded to the gp timer unit enables one timer to measure the intervals between count events. boundary registers enable auto-zero operation or simple system warning by interrupts when programmabl e count values are exceeded. serial ports the adsp-bf512/bf514/bf516/bf 518(f) processors incorpo- rate two dual-channel synchron ous serial ports (sport0 and sport1) for serial and multip rocessor communications. the sports support the following features: ?i 2 s capable operation. ? bidirectional operation C each sport has two sets of inde- pendent transmit and receiv e signals, enabling eight channels of i 2 s stereo audio. ? buffered (8-deep) transmit an d receive ports C each port has a data register for transfe rring data words to and from other processor components and shift registers for shifting data in and out of the data registers. ? clocking C each transmit and re ceive port can either use an external serial clock or generate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word length C each sport supports serial data words from 3 to 32 bits in length, tr ansferred most-significant-bit first or least-significant-bit first. ? framing C each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. ? companding in hardware C each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. ? dma operations with single-cycle overhead C each sport can automatically receive and tr ansmit multiple buffers of memory data. the processor can link or chain sequences of dma transfers between a sport and memory. ? interrupts C each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer, or buffers, through dma. ? multichannel capability C each sport supports 128 chan- nels out of a 1024-channel wind ow and is compatible with the h.100, h.110, mvip-90, and hmvip standards. serial peripheral interface (spi) ports the processors have two spi-co mpatible ports (spi0 and spi1) that enable the processor to communicate with multiple spi- compatible devices. the spi interface uses three sign als for transferring data: two data signals (master output-slave inputCmosi, and master input-slave outputCmiso) and a clock signal (serial clockCsck). an spi chip select input signal (spixss ) lets other spi devices select the processor, and multiple spi chip select output signals let the processor select other spi devices. the spi select signals are reconfigured general-purpose i/o signals. using these signals, the spi port provides a full-duplex, syn- chronous serial interface, wh ich supports both master/slave modes and multimaster environments. the spi port baud rate and cloc k phase/polarities are program- mable, and it has an integrated dma channel, configurable to support transmit or receive data streams. the spis dma chan- nel can only service unidirection al accesses at any given time. the spi port clock rate is calculated as: where the 16-bit spi_baud register contains a value of 2 to 65,535. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. uart ports the adsp-bf512/bf514/bf516/bf 518(f) processors provide two full-duplex universal asynchronous receiver/transmitter (uart) ports, which are fully compatible with pc-standard uarts. each uart port provides a simplified uart interface to other peripherals or hosts, supporting full-duplex, dma-sup- ported, asynchronous transfers of serial data. a uart port spi clock rate f sclk 2 spi_baud ----------------------------------- - =
rev. pre | page 12 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data includes support for five to eight data bits, one or two stop bits, and none, even, or od d parity. each uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interr upts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower default priority than most dma channels because of their re latively low service rates. each uart port's baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk /1,048,576) to (f sclk /16) bits per second. ? supporting data formats from seven to 12 bits per frame. ? both transmit and receive oper ations can be configured to generate maskable interrupts to the processor. the uart ports clock rate is calculated as: where the 16-bit uart_divisor comes from the uart_dlh (most significant 8 bits) and uart_dll (least significant 8 bits) registers. in conjunction with the general-purpose timer functions, auto- baud detection is supported. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda?) serial infrared physical layer link specification (sir) protocol. twi controller interface the processors include a two wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi is co mpatible with the widely used i 2 c ? bus standard. the twi module offers the capa bilities of simultaneous master and slave op eration, support for both 7-bit addressing and multimedia data arbitration. the twi interface utilizes two signals for transfe rring clock (scl) and data (sda) and supports the protocol at sp eeds up to 400k bits/sec. the twi interface signals are compat ible with 5 v logic levels. additionally, the processors tw i module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. rsi interface the removable storage interface (r si) controller acts as the host interface for multi-media cards (mmc), secure digital memory cards (sd card), secure digital input/output cards (sdio), and ce-ata hard disk drives. the following list describes the main features of the rsi controller. ? support for a single mmc, sd memory, sdio card or ce- ata hard disk drive ? support for 1-bit and 4-bit sd modes ? support for 1-bit, 4-bit and 8-bit mmc modes ? support for 4-bit and 8-bi t ce-ata hard disk drives ? a ten-signal external interface with clock, command, and up to eight data lines ? card detection using one of the data signals ? card interface clock generation from sclk ? sdio interrupt and read wait features ? ce-ata command completion signal recognition and disable 10/100 ethernet mac the adsp-bf516/bf518 processors offer the capability to directly connect to a network by way of an embedded fast ether- net media access controller (mac ) that supports both 10-baset (10m bits/sec) and 100-baset (100m bits/sec) operation. the 10/100 ethernet mac peripheral on the processor is fully com- pliant to the ieee 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. some standard features are: ? support of mii and rmii pr otocols for external phys ? full duplex and half duplex modes ? data framing and encapsulation: generation and detection of preamble, length padding, and fcs ? media access management (in half-duplex operation): col- lision and contention handling, including control of retransmission of collision frames and of back-off timing ? flow control (in full-duplex operation): generation and detection of pause frames ? station management: generation of mdc/mdio frames for read-write access to phy registers ? sclk operating range down to 25 mhz (active and sleep operating modes) ? internal loopback from transmit to receive some advanced features are: ? buffered crystal output to external phy for support of a single crystal system ? automatic checksum computat ion of ip header and ip payload fields of rx frames ? independent 32-bit descriptor-driven receive and transmit dma channels uart clock rate f sclk 16 uart_divisor ----------------------------------------------- =
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 13 of 62 | march 2009 ? frame status delivery to me mory through dma, including frame completion semaphores for efficient buffer queue management in software ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations ? convenient frame alignment modes support even 32-bit alignment of encapsulated rece ive or transmit ip packet data in memory after the 14-byte mac header ? programmable ethernet event interrupt supports any com- bination of: ? selected receive or transmit frame status conditions ? phy interrupt condition ? wakeup frame detected ? selected mac management counter(s) at half-full ? dma descriptor error ? 47 mac management statistics counters with selectable clear-on-read behavi or and programmable interrupts on half maximum value ? programmable receive address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes fo r broadcast, multicast, uni- cast, control, and damaged frames ? advanced power management supporting unattended transfer of receive and transm it frames and status to/from external memory via dma during low-power sleep mode ? system wakeup from sleep operating mode upon magic packet or any of four user-d efinable wakeup frame filters ? support for 802.3q tagged vlan frames ? programmable mdc clock rate and preamble suppression ? in rmii operation, seven unused signals may be config- ured as gpio signals for other purposes ieee 1588 support the ieee 1588 standard is a precision clock synchronization protocol for networked measurem ent and control systems. the ADSP-BF518/ADSP-BF518f proce ssors include hardware sup- port for ieee 1588 with an integrated precision time protocol synchronization engine (ptp_tsync). this engine provides hardware assisted time stamping to improve the accuracy of clock synchronization between ptp nodes. the main features of the ptp_sync engine are: ? support for both ieee 1588-2002 and ieee 1588-2008 pro- tocol standards ? hardware assisted time st amping capable of 12.5 ns resolution ?lock adjustment ? programmable ptm message support ?dedicated interrupts ? programmable alarm ? multiple input clock sources (sclk, mii clock, external clock up to 50 mhz) ? programmable pulse per second (pps) output ? auxiliary snapshot to time stamp external events ports because of the rich set of periph erals, the processors group the many peripheral signals to four portsport f, port g, port h, and port j. most of the associated pins/balls are shared by multi- ple signals. the ports functi on as multiplexer controls. general-purpose i/o (gpio) the adsp-bf512/bf514/bf516/bf 518(f) processors have 40 bidirectional, general-purpose i/o (gpio) signals allocated across three separate gpio modulesportfio, portgio, and porthio, associated with po rt f, port g, and port h, respectively. each gpio-capable signal shares functionality with other peripherals via a multiplexing scheme; however, the gpio functionality is the defa ult state of the device upon power-up. neither gpio output nor input drivers are active by default. each general-purpose po rt signal can be individually controlled by manipula tion of the port control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio signal as input or output. ? gpio control and status regi sters C the processor employs a write one to modify mechanism that allows any combi- nation of individual gpio signals to be modified in a single instruction, without affecting the level of any other gpio signals. four control registers are provided. one register is written in order to set signal values, one register is written in order to clear signal values , one register is written in order to toggle signal values, and one register is written in order to specify a signal value. reading the gpio status register allows software to interrogate the sense of the signals. ? gpio interrupt mask register s C the two gpio interrupt mask registers allow each indi vidual gpio signal to func- tion as an interrupt to the processor. similar to the two gpio control registers that ar e used to set and clear indi- vidual signal values, one gpio interrupt mask register sets bits to enable interrupt function, and the other gpio inter- rupt mask register clears bits to disable interrupt function. gpio signals defined as inputs can be configured to gener- ate hardware interrupts, while output signals can be triggered by software interrupts. ? gpio interrupt sensitivity registers C the two gpio inter- rupt sensitivity registers spec ify whether individual signals are level- or edge-sensitive and specifyif edge-sensitive whether just the rising edge or both the rising and falling edges of the signal are signific ant. one register selects the type of sensitivity, and one re gister selects which edges are significant for edge-sensitivity.
rev. pre | page 14 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data parallel peripheral interface (ppi) the adsp-bf512/bf514/bf516/bf518 (f) processors provide a parallel peripheral interface (ppi ) that can connect directly to parallel a/d and d/a converte rs, itu-r-601/656 video encod- ers and decoders, and other gene ral-purpose peripherals. the ppi consists of a dedicated input clock signal, up to three frame synchronization signals, an d up to 16 data signals. in itu-r-656 modes, the ppi receiv es and parses a data stream of 8-bit or 10-bit data elements. on-chip decode of embedded preamble control and synchronization information is supported. three distinct itu-r- 656 modes are supported: ? active video only mode C the ppi does not read in any data between the end of active video (eav) and start of active video (sav) preamble sy mbols, or any data present during the vertical blanking intervals. in this mode, the control byte sequence s are not stored to memory; they are filtered by the ppi. ? vertical blanking only mode C the ppi only transfers verti- cal blanking interval (vbi) data, as well as horizontal blanking information and control byte sequences on vbi lines. ? entire field mode C the entire incoming bitstream is read in through the ppi. this includ es active video, control pre- amble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. though not explicitly supported, itu-r-656 output functional- ity can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data ou t the ppi in a frame sync-less mode. the processors 2-d dma features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. the general-purpose modes of th e ppi are intended to suit a wide variety of data capture an d transmission applications. the modes are divided into four main categories, each allowing up to 16 bits of data transfer per ppi_clk cycle: ? data receive with internally generated frame syncs ? data receive with externally generated frame syncs ? data transmit with internally generated frame syncs ? data transmit with externally generated frame syncs these modes support adc/dac connections, as well as video communication with hardware signalling. many of the modes support more than one level of frame synchronization. if desired, a programmable delay can be inserted between asser- tion of a frame sync and reception/transmission of data. code security with lockbox secure technology a security system consisting of a blend of hardware and soft- ware provides customers with a flexible and rich set of code security features with lockbox secure tech nology. key features include: ? otp memory ? unique chip id ? code authentication ? secure mode of operation the security scheme is based up on the concept of authentica- tion of digital signatures usin g standards-based algorithms and provides a secure processing environment in which to execute code and protect assets. dynamic power management the adsp-bf512/bf514/bf516/bf 518(f) processors provide four operating modes, each with a different performance/power profile. in addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. when configured for a 0 volt core supply voltage, the processor enters the hiber- nate state. control of clocki ng to each of the processor peripherals also reduces power consumption. see table 4 for a summary of the power se ttings for each mode. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed. active operating modemoderate power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. in this mode, the clkin to cclk multiplier ratio can be changed, although the changes are not real ized until the full-on mode is entered. dma access is available to appropriately configured l1 memories. table 4. power settings mode/state pll pll bypassed core clock (cclk) system clock (sclk) core power full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 15 of 62 | march 2009 in the active mode, it is possible to disable the pll through the pll control register (pll_ctl). if disabled, the pll must be re-enabled before transitioning to the full-on or sleep modes. sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally an external event or rtc ac tivity wakes up the processor. when in the sleep mo de, asserting wakeup causes the processor to sense the value of the bypass bit in the pll control register (pll_ctl). if bypass is disabled, the processor transitions to the full on mode. if bypass is enabled, the processor transi- tions to the active mode. system dma access to l1 me mory is not supported in sleep mode. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the processor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals, such as the rtc, may still be ru nning but cannot access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchronous interrupt generated by the rtc. when in deep sleep mode, an rtc asynchronous interrupt causes the proces- sor to transition to the acti ve mode. assertion of reset while in deep sleep mode causes the pr ocessor to transition to the full on mode. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the processor core (cclk) and system blocks (sclk). any critical information stored internally (memory contents, regist er contents, etc.) must be written to a non-volatile storage device prio r to removing power if the pro- cessor state is to be preserved. writing b#00 to th e freq bits in the vr_ctl register also causes ext_wake to transition low, which can be used to signal an external voltage regulator to shut down. since v ddext is still supplied in this mode, all of the external sig- nals three-state, unless otherwis e specified. this allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. the ethernet module can signal an external regulator to wake up using ext_wake. if pf15 does not connect as a phyint signal to an external phy devi ce, it can be pulled low by any other device to wake the processo r up. the processor can also be woken up by a real-time clock wakeup event or by asserting the reset pin. all hibernate wakeup events initiate the hardware reset sequence. individual sour ces are enabled by the vr_ctl register. the ext_wake signal is provided to indicate the occurrence of wakeup events. with the exception of the vr_c tl and the rtc registers, all internal registers and memories lose their content in the hiber- nate state. state variables may be held in external sram or sdram. the sckelow bit in the vr_ctl register controls whether or not sdram operates in self-refresh mode, which allows it to retain its content while the processor is in hiberna- tion and through the subsequent reset sequence. power savings as shown in table 5 , the processors support up to six different power domains, which maximizes flexibility while maintaining compliance with industry standa rds and conventions. by isolat- ing the internal logic of the processor into its own power domain, separate from the rt c and other i/o, the processor can take advantage of dynamic power management without affecting the rtc or other i/o de vices. there are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate specifications table for processor operating conditions; even if the fea- ture/peripheral is not used. the dynamic power management feature of the processor allows both the processors input voltage (v ddint ) and clock fre- quency (f cclk ) to be dynamically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. further, these power sa vings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations. where the variables in the equations are: f cclknom is the nominal core clock frequency f cclkred is the reduced core clock frequency v ddintnom is the nominal internal supply voltage v ddintred is the reduced internal supply voltage table 5. power domains power domain v dd range all internal logic, except rtc, memory, otp v ddint rtc internal logic and crystal i/o v ddrtc memory logic v ddmem otp logic v ddotp optional internal flash v ddflash all other i/o v ddext power savings factor f cclkred f cclknom -------------------------- v ddintred v ddintnom ------------------------------- - ?? ?? 2 t red t nom -------------- - ? ? ? ? = % power savings 1 po wer savings factor ? () 100% =
rev. pre | page 16 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data t nom is the duration running at f cclknom t red is the duration running at f cclkred voltage regulation interface the adsp-bf512/bf514/bf516/bf 518(f) processors require an external voltage regulator to power the v ddint domain. to reduce standby power consumption in the hibernate state, the external voltage regulator can be signaled through ext_wake to remove power from the processor core. ext_wake is high- true for power-up and may be connected directly to the low- true shut down input of many common regulators. the power good (pg ) input signal allows the processor to start only after the internal voltage has reached a chosen level. in this way, the startup time of the external regulator is detected after hibernation. for a complete description of the pg functionality, refer to the adsp-bf51x blackfin proc essor hardware reference . clock signals the adsp-bf512/bf514/bf516/bf 518(f) processors can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processor clkin signal. when an external clock is used, the xtal pin/ba ll must be left unconnected. alternatively, because the proce ssor includes an on-chip oscilla- tor circuit, an external crysta l may be used. for fundamental frequency operation, us e the circuit shown in figure 4 . a paral- lel-resonant, fundamental freq uency, microprocessor-grade crystal is connected across the clkin and xtal pins/balls. the on-chip resistance between th e clkin pin/ball and the xtal pin/ball is in the 500 k range. further parallel resistors are typ- ically not recommended. the two capacitors and the series resistor shown in figure 4 fine tune phase and amplitude of the sine frequency. the capacitor and resist or values shown in figure 4 are typical values only. the capaci tor values are dependent upon the crystal manufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufactur er. the user should verify the customized values based on care ful investigations on multiple devices over temperature range. a third-overtone crystal can be used for frequencies above 25 mhz. the circuit is then modifi ed to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in figure 4 . a design procedure fo r third-overtone oper- ation is discussed in detail in application note (ee-168) using third overtone crystals with the adsp-218x dsp on the analog devices website ( www.analog.com )use site search on ee-168. the clkbuf signal is an output signal, which is a buffered ver- sion of the input clock. this signal is particularly useful in ethernet applications to limit the number of required clock sources in the system. in this type of application, a single 25 mhz or 50 mhz crystal may be applied directly to the pro- cessor. the 25 mhz or 50 mhz output of clkbuf can then be connected to an external ethe rnet mii or rmii phy device. the blackfin core runs at a different clock rate than the on-chip peripherals. as shown in figure 5 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a programmable 0.5 to 64 multiplication factor (bounded by specified minimum and maximum vco frequencies). the default multiplier is 5 , but it can be modified by a software instruction sequence. on-the-fly frequency changes can be effected by simply writing to the pll_div register. th e maximum allowed cclk and sclk rates depend on the applied voltages v ddint , v ddext , and v ddmem , the vco is always permitted to run up to the frequency specified by the parts speed grad e. the clkout signal reflects the sclk frequency to the off-chip world. it belongs to the sdram interface, but it functions as reference signal in other timing specifications as well. whil e active by default, it can be disabled using the ebiu_sdgctl and ebiu_amgctl registers. figure 4. external crystal connections figure 5. frequency mo dification methods clkin clkout xtal en clkbuf to pll circuitry for overtone operation only: note: value s marked with * mu s tbecu s tomized depending on the cry s tal and layout. plea s e analyze carefully. 1 8 pf* en 1 8 pf* 33 0 * blackfin pll 0.5 to 64 1to 15 1,2,4, 8 vco clkin fine adju s tment require s pll s eq uencing c o ar s e adju s tment on-the -fly cc l k s clk s clk cclk s clk 8 0mhz
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 17 of 62 | march 2009 all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 6 illustrates typical system clock ratios. note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lock latencies by writing the appropriate values to the pll divisor register (pll_div). the core clock (cclk) frequency can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 7 . this programmable core cloc k capability is useful for fast core frequency modifications. the maximum cclk frequency not only depends on the part's speed grade (see page 62), it also depends on the applied v ddint voltage. see table 11 for details. the maxi mal system clock rate (sclk) depends on the chip package and the applied v ddint , v ddext , and v ddmem voltages (see table 14 on page 24). booting modes the processor has several mechanisms (listed in table 8 ) for automatically loading internal and external memory after a reset. the boot mode is defined by three bmode input bits dedicated to this purpose. ther e are two catego ries of boot modes. in master boot modes the processor actively loads data from parallel or serial memories . in slave boot modes the pro- cessor receives data from external host devices. the boot modes listed in table 8 provide a number of mecha- nisms for automatically loading the processors internal and external memories after a reset. by default, all boot modes use the slowest meaningful configuration settings. default settings can be altered via the initialization code feature at boot time or by proper otp programming at pre-boot time. the bmode bits of the reset configuration register, sampled during power- on resets and software-initiat ed resets, implement the modes shown in table 8 . ? idle/no boot mode (bmode = 0x0) in this mode, the processor goes into idle. the idle boot mode helps recover from illegal operating modes, such as when the user has mis configured the otp memory. ? boot from 8-bit or 16-bit external flash memory (bmode = 0x1) in this mode, the boot kernel loads the first block header from address 0x2000 0000 anddepend- ing on instructions containing in the headerthe boot kernel performs 8-bit or 16-bit boot or starts program exe- cution at the address provided by the header. by default, all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle r/w access times, 4-cycle setup). the ardy is not enabled by default, but it can be enabled by otp programming. similarly, all interface behavior and timings can be customized by otp programming. this includes activation of burst-mode or page-mode operation. in this mode, all signals be longing to the asynchronous interface are enabled at the port muxing level. ? boot from internal spi me mory (bmode = 0x2) the processor uses spi0 to load fr om code previously loaded to the 4 mbit internal spi flash. only available on the adsp- bf512f/adsp-bf514f/adsp-bf516f/ADSP-BF518f. ? boot from external spi eeprom or flash (bmode = 0x3) 8-bit, 16-bit, 24-bit or 32- bit addressable devices are supported. the processor uses the pg15 gpio signal (at spi0ssel2 ) to select a single spi eeprom/flash device connected to the spi0 interface; then submits a read com- mand and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. pull-up resistors are required on th e ssel and miso signals. by default, a value of 0x85 is written to the spi0_baud register. ? boot from spi0 host device (bmode = 0x4) the pro- cessor operates in spi slave mode and is configured to receive the bytes of the ldr file from an spi host (master) agent. in the host, the hwait signal must be interrogated table 6. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0001 1:1 50 50 0110 6:1 300 50 1010 10:1 400 40 table 7. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios (mhz) vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 400 100 11 8:1 200 25 table 8. booting modes bmode2C0 description 000 idle - no boot 001 boot from 8- or 16-bit external flash memory 010 boot from internal spi memory 011 boot from external spi memory (eeprom or flash) 100 boot from spi0 host 101 boot from otp memory 110 boot from sdram 111 boot from uart0 host
rev. pre | page 18 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data by the host before every transmitted byte. a pull-up resistor is required on the spi0ss input. a pull-down on the serial clock may improve signal quality and booting robustness. ? boot from otp memory (bmode = 0x5) this provides a stand-alone booting method. the boot stream is loaded from on-chip otp memory. by default the boot stream is expected to start from otp pa ge 0x40 on and can occupy all public otp memory up to page 0xdf. this is 2560 bytes. since the start page is programmable the maximum size of the boot stream ca n be extended to 3072 bytes. ? boot from sdram (bmode = 0x6) this is a warm boot scenario, where the bo ot kernel starts booting from address 0x0000 0010. the sdram is expe cted to contain a valid boot stream and the sdram cont roller must be configured by the otp settings. ? boot from uart0 host (bmode = 0x7) using an auto- baud handshake sequence, a boot-stream formatted program is downloaded by the host. the host selects a bit rate within the uart clocking capabilities. when performing the autoba ud, the uart expects a @ (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the rx0 sign al to determine the bit rate. the uart then replies with an acknowledgement com- posed of 4 bytes (0xbfthe value of uart0_dll and 0x00the value of uart0_dl h). the host can then download the boot stream. to hold off the host the blackfin processor signals the host with the boot host wait (hwait) signal. therefore, the host must monitor hwait before every transmitted byte. for each of the boot modes, a 16- byte header is first read from an external memory device. the header specifies the number of bytes to be transferred and th e memory destination address. multiple memory blocks may be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the address stored in the evt1 register. prior to booting, the pre-boot routine interrogates the otp memory. individual boot modes can be customized or even dis- abled based on otp programming. external hardware, especially booting hosts may watch the hwait signal to deter- mine when the pre-boot has finished and the boot kernel starts the boot process. by programm ing otp memory, the user can instruct the preboot routine to also customize the pll, the sdram controller, and the asynchronous interface. the boot kernel differentiates between a regular hardware reset and a wakeup-from-hibernate even t to speed up booting in the later case. bits 6-4 in the syst em reset configuration (syscr) register can be used to bypass pre-boot ro utine and/or boot ker- nel in case of a software reset. they can also be used to simulate a wakeup-from-hibernate boot in the software reset case. the boot process can be further customized by initialization code. this is a piece of code that is loaded and executed prior to the regular application boot. typically, this is used to configure the sdram controller or to sp eed up booting by managing pll, clock frequencies, wait states, or serial bit rates. the boot rom also features c-ca llable function entries that can be called by the user application at run time. this enables sec- ond-stage boot or boot management schemes to be implemented with ease. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax designed for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction in structions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple le vels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mc u features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit macs or four 8-bit alus plus two load/store plus two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, which include intermixing of 16-bit and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools the adsp-bf512/bf514/bf516/bf 518(f) processors are sup- ported with a complete set of crosscore ? software and hardware development tools, in cluding analog devices emula- tors and visualdsp++? development environment. the same emulator hardware that supports other blackfin processors also fully emulates the adsp -bf512/bf514/bf516/bf518(f) processors. ez-kit lite evaluation board for evaluation of the processors, use the ez-kit lite ? board being developed by analog devices. the board comes with on- chip emulation capabilities and is equipped to enable software development. multiple daug hter cards are available.
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 19 of 62 | march 2009 designing an emulator-compatible processor board (target) the analog devices family of em ulators are tools that every sys- tem developer needs in order to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag processor. the emulator uses the tap to access th e internal features of the pro- cessor, allowing the developer to load code, set breakpoints, observe variables, observe memo ry, and examine registers. the processor must be halted to se nd data and commands, but once an operation has been completed by the emulator, the processor system is set running at fu ll speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conn ections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see (ee-68) analog devices jt ag emulation technical reference on the analog devices website ( www.analog.com ) use site search on ee-68. this document is updated regularly to keep pace with improvem ents to emulator support. related documents the following publications th at describe the adsp-bf512/ adsp-bf514/adsp-bf516/adsp -bf518 processors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf512/bf514/bf516/bf518(f) blackfin processor hardware reference ? adsp-bf53x/bf56x blackfin processor programming reference ? adsp-bf512/bf514/bf516/bf518(f) blackfin processor anomaly list lockbox secure technology disclaimer analog devices products containing lockbox secure technol- ogy are warranted by analog devices as detailed in the analog devices standard terms and conditions of sale. to our knowl- edge, the lockbox secure technolo gy, when used in accordance with the data sheet and hardware reference manual specifica- tions, provides a secure method of implementing code and data safeguards. however, analog devices does not guarantee that this technology provides absolu te security. accordingly, analog devices hereby disclaims any and all express and implied warranties that the lock- box secure technology cannot be breached, compromised or otherwise circumvented and in no event shall analog devices be liable for any loss, damage, destruction or release of data, information, physical property or intel- lectual property.
rev. pre | page 20 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data signal descriptions the processors signal de finitions are listed in table 9 . in order to maintain maximum function and reduce package size and signal count, some signals have dual, multiplexed functions. in cases where signal function is re configurable, the default state is shown in plain text, while the al ternate function is shown in italics. all pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchro- nous and synchronous memory control, and the buffered xtal output pin (clkbuf). on the external memory interface, the control and address lines are driv en high, with the exception of clkout, which toggles at the system clock rate. all i/o signals have their input buffers disabled with the excep- tion of the signals noted in the data sheet that need pull-ups or pull downs if unused. the sda (serial data) and scl (ser ial clock) pins/balls are open drain and therefore require a pu llup resistor. consult version 2.1 of the i 2 c specification for the proper resistor value. it is strongly advised to use the available ibis models to ensure that a given board design meet s overshoot/undershoot and sig- nal integrity requirements. if no ib is simulation is performed, it is strongly recommended to add se ries resistor terminations for all driver types a, c and d. th e termination re sistors should be placed near the processor to reduce transients and improve signal integrity. the resi stance value, typically 33 or 47 , should be chosen to match the average board trace impedance. additionally, adding a paralle l termination to clkout may prove useful in further enhancing signal integrity. be sure to verify overshoot/undershoot and si gnal integrity specifications on actual hardware. table 9. signal descriptions signal name type function driver type 1 ebiu addr19C1 o address bus a data15C0 i/o data bus a abe1C0 / sdqm1C0 o byte enable or data mask a ams1C0 obank select a are o asynchronous memory read enable a awe o write enable for async a sras o sdram row address strobe a scas o sdram column address strobe a swe o sdram write enable a scke o sdram clock enable a clkout o sdram clock output b sa10 o sdram a10 signal a sms o sdram bank select a port f: gpio and multiplexed peripherals pf0/ etxd2 / ppi d0 / spi1sel2 / taclk6 i/o gpio/ ethernet mii transmit d2 / ppi data 0 / spi1 slave select 2 / timer6 alternate clock c pf1/ erxd2 / ppi d1 / pwm ah / taclk7 i/o gpio/ ethernet mii receive d2 / ppi data 1 / pwm ah output / timer7 alternate clock c pf2/ etxd3 / ppi d2 / pwm al i/o gpio/ ethernet transmit d3 / ppi data 2 / pwm al output c pf3/ erxd3 / ppi d3 / pwm bh / taclk0 i/o gpio/ ethernet mii data receive d3 / ppi data 3 / pwm bh output / timer0 alternate clock c pf4/ erxclk / ppi d4 / pwm bl / taclk1 i/o gpio/ ethernet mii receive clock / ppi data 4 / pwm bl out / timer1 alternate clk c pf5/ erxdv / ppi d5 / pwm ch / taci0 i/o gpio/ ethernet mii or rmii receive data valid / ppi data 5 / pwm ch out / timer0 alternate capture input c pf6/ col / ppi d6 / pwm cl / ta ci1 i/o gpio/ ethernet mii collision / ppi data 6 / pwm cl out / timer1 alternate capture input c pf7/ spi0sel1 / ppi d7 / pwmsync i/o gpio/ spi0 slave select 1 / ppi data 7 / pwm sync c pf8/ mdc /ppi d8/ spi1sel4 i/o gpio/ ethernet management channel clock / ppi data 8 / spi1 slave select 4 c pf9/ mdio / ppi d9 / tmr2 i/o gpio/ ethernet management channel serial data / ppi data 9 / timer 2 c
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 21 of 62 | march 2009 pf10/ etxd0 / ppi d10 / tmr3 i/o gpio/ ethernet mii or rmii transmit d0/ppi data 10 / timer 3 c pf11/ erxd0 / ppi d11 / pwm ah / taci3 i/o gpio/ ethernet mii receive d0/ppi data 11 / pwm ah output / timer3 alternate capture input c pf12/ etxd1 / ppi d12 / pwm al i/o gpio/ ethernet mii transmit d1 / ppi data 12 / pwm al output c pf13/ erxd1 / ppi d13 / pwm bh i/o gpio/ ethernet mii or rmii receive d1 / ppi data 13 / pwm bh output c pf14/ etxen / ppi d14 / pwm bl i/o gpio/ ethernet mii transmit enable / ppi data 14 / pwm bl out c pf15 2 / rmii phyint / ppi d15 / pwm_synca i/o gpio/ ethernet mii phy interrupt / ppi data 15 / alternate pwm sync c port g: gpio and multiplexed peripherals pg0/ miicrs / rmiicrs / hwait 3 / spi1sel3 i/o gpio/ ethernet mii or rmii carrier sense / hwait / spi1 slave select3 c pg1/ erxer/ dmar1 / pwm ch i/o gpio/ ethernet mii or rmii receive error / dma req 1 / pwm ch out c pg2/ miitxclk / rmiiref_clk / dmar0 / pwm cl i/o gpio/ ethernet mii or rmii reference clock / dma req 0 / pwm cl out c pg3/ dr0pri / rsi_data0 / spi0sel5 / taclk3 i/o gpio/ sport0 primary rx data / rsi data 0 / spi0 slave select 5 / timer3 alternate clk c pg4/ rsclk0 / rsi_data1 / tmr5 / taci5 i/o gpio/ sport0 rx clock / rsi data 1 / timer 5 / timer5 alternate capture input d pg5/ rfs0 / rsi_data2 / ppiclk / tmrclk i/o gpio/ sport0 rx frame sync / rsi data 2 / ppi clock / external timer reference c pg6/ tfs0 / rsi_data3 / tmr0 / ppifs1 i/o gpio/ sport0 tx frame sync / rsi data 3 / timer0 / ppi frame sync1 c pg7/ dt0pri / rsi_cmd / tmr1 / ppifs2 i/o gpio/ sport0 tx primary data / rsi command / timer 1 / ppi frame sync2 c pg8/ tsclk0 / rsi_clk / tmr6 / taci6 i/o gpio/ sport0 tx clock / rsi clock / timer 6 / timer6 alternate capture input d pg9/ dt0sec / uart0tx / tmr4 i/o g pio/ sport0 secondary tx data / uart0 transmit / timer 4 c pg10/ dr0sec / uart0rx / taci4 i/o gpio/ sport0 secondary rx data / uart0 receive / timer4 alternate capture input c pg11/ spi0ss / ams2 / spi1sel5 / taclk2 i/o gpio/ spi0 slave device select / asynchronous memory bank select 2 / spi1 slave select 5 / timer2 alternate clk c pg12/ spi0sck / ppiclk / tmrclk / ptp_pps i/o gpio/ spi0 clock/ppi clock / external timer reference / ptp pulse per second out d pg13/ spi0miso 4 / tmr0 / ppifs1 / ptp_clkout i/o gpio/ spi0 master in slave out/timer0 / ppi frame sync1 / ptp clock out c pg14/ spi0mosi / tmr1 / ppifs2 / pwm trip / ptp_auxin i/o gpio/ spi0 master out slave in / timer 1 / ppi frame sync2/pwm trip / ptp auxiliary snapshot trigger input c pg15/ spi0sel2 / ppifs3 / ams3 i/o gpio/ spi0 slave select 2 / ppi frame sync3 / asynchronous memory bank select 3 c port h: gpio and multiplexed peripherals ph0/ dr1pri / spi1ss / rsi_data4 i/o gpio/ sport1 primary rx data / spi1 device select / rsi data 4 c ph1/ rfs1 / spi1miso / rsi_data5 i/o gpio/ sport1 rx frame sync / spi1 master in slave out / rsi data 5 c ph2/ rsclk1 / spi1sck / rsi data6 i/o gpio/ sport1 rx clock / spi1 clock / rsi data 6 d ph3/ dt1pri / spi1mosi / rsi data7 i/o gpio/ sport1 primary tx data / spi1 master out slave in / rsi data 7 c ph4/ tfs1 / aoe / spi0sel3 / cud i/o gpio/ sport1 tx frame sync / asynchronous memory output enable / spi0 slave select 3 / counter up direction c ph5/ tsclk1 / ardy / ptp_ext_clkin / cdg i/o gpio/ sport1 tx clock / asynchronous memory hardware ready control / external clock for ptp tsync / counter down gate d ph6/ dt1sec / uart1tx / spi1sel1 / czm i/o gpio/ sport1 secondary tx data / uart1 transmit / spi1 slave select 1 / counter zero marker c ph7/ dr1sec / uart1rx / tmr7 / taci2 i/o gpio/ sport1 secondary rx data / uart1 receive / timer 7 / timer2 alternate clock input c table 9. signal descriptions signal name type function driver type 1
rev. pre | page 22 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data port j pj0:scl i/o 5v twi serial clock (this signal is an open-drain output and requires a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value.) e pj1:sda i/o 5v twi serial data (this signal is an open-drain output and requires a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value.) e real time clock rtxi i rtc crystal input (this ball should be pulled low when not used.) rtxo o rtc crystal output jtag port tck i jtag clock tdo o jtag serial data out c tdi i jtag serial data in tms i jtag mode select trst i jtag reset (this signal should be pulled low if the jtag port is not used.) emu o emulation output c clock clkin i clock/crystal input xtal o crystal output clkbuf o buffered xtal output c mode controls reset ireset nmi i non-maskable interrupt (this signal sh ould be pulled high when not used.) bmode2-0 i boot mode strap 2-0 voltage regulation interface pg i power good ext_wake o wake up indication f power supplies all supplies must be powered see operating conditions on page 23 . v ddext p i/o power supply v ddint p internal power supply v ddrtc p real time clock power supply v ddflash p internal spi flash power supply v ddmem pmem power supply v ppotp p otp programming voltage v ddotp potp power supply v ss g ground for all supplies 1 see output drive currents on page 49 for more information about each driver type. 2 when driven low, the pf15 signal can be us ed to wake up the processor from the hiberna te state, either in normal gpio mode or i n ethernet mode as phyint . if the pin/ball is used for wake up, enable the feature with the phywe bit in the vr_ctl register, and pull-up the signal with a resistor. 3 boot host wait is a gpio s ignal toggled by the boot kernel. the mandatory external pull-up/pull-down resistor defines the signa l polarity. 4 a pull-up resistor is required for the boot from external sp i eeprom or flash (bmode = 0x3). table 9. signal descriptions signal name type function driver type 1
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 23 of 62 | march 2009 specifications note that component specificat ions are subject to change without notice. operating conditions parameter conditions min nominal max unit v ddint internal supply voltage 1 1 the expected nominal value is 1.4v 5% and initial customer designs should des ign with a programmable regulator that can be adjusted from 0.95v to 1.5v in 50mv st eps. tbd tbd tbd v v ddext 2 2 must remain powered (even if the as sociated function is not used). external supply voltage 3 3 v ddext is the supply to the gpio. 1.70 1.8, 2.5 or 3.3 3.6 v v ddrtc 4 4 if not used, power with v ddext . rtc power supply voltage 2.25 3.6 v v ddmem 5 5 pins/balls that use v ddmem are data15C0, addr19C1, abe1C0 , are , awe , ams1C0 , sa10, swe , scas , clkout, sras , sms , scke. these pins/balls are not tolerant to voltages higher than v ddmem . when using any of the asynchronous memory signals ams3C2 , ardy, or aoe v ddmem and v ddext must be shorted externally because these signals are multiplexed with gpio. mem supply voltage 1.70 1.8, 2.5 or 3.3 3.6 v v ddflash 4 internal spi flash supply voltage 1.7 1.8 1.9 v v ddotp otp supply voltage 2.25 2.5 2.75 v v ppotp otp programming voltage for reads 2 2.25 2.5 2.75 v for writes 6 6 the v ddotp voltage for writes must only be applied when programming otp memory. there is a finite amount of cumulative time that this vol tage may be applied (dependent on voltage and junction temperature) over the lifetime of the part. please see table 17 on page 26 for details. 6.9 7.0 7.1 v v ih high level input voltage 7, 8 7 bidirectional pins/balls (pf15C0, pg15C0, ph7C0) and input pins/balls (rtxi, tck, tdi, tms, trst , clkin, reset , nmi , and bmode2C0) of the adsp- bf512/bf514/bf516/bf518(f) are 3.3 v tolerant (always accept up to 3.6 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. 8 parameter value applies to all input and bi directional pins/balls except sda and scl. v ddext /v ddmem = 1.90 v 1.1 3.6 v v ih high level input voltage 7, 8 v ddext /v ddmem = 2.75 v 1.7 3.6 v v ih high level input voltage 7, 8 v ddext /v ddmem = 3.6 v 2.0 3.6 v v ihtwi high level input voltage v ddext = 1.90 v/2.75 v/3.6 v 0.7 x v bustwi v bustwi 9 9 the v ihtwi min and max value vary with the selection in the twi_dt field of the nongpio_drive register. see v bustwi min and max values in table 11 . v v il low level input voltage 7, 8 v ddext /v ddmem = 1.7 v C0.3 0.6 v v il low level input voltage 7, 8 v ddext /v ddmem = 2.25 v C0.3 0.7 v v il low level input voltage 7, 8 v ddext /v ddmem = 3.0 v C0.3 0.8 v v iltwi low level input voltage v ddext = minimum C0.3 0.3 x v bustwi 10 10 sda and scl are pulled up to v bustwi . see table 10 . v t j junction temperature 168-ball csp_bga @ t ambient = 0c to +70c 0 +105 c t j junction temperature 176-lead lqfp @ t ambient = 0c to +70c 0 +105 c t j junction temperature 176-lead lqfp @ t ambient = C40c to +85c C40 +105 c
rev. pre | page 24 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data table 10 shows settings for twi_dt in the nongpio_drive register. set this register prior to using the twi port. table 11 describes the timing requirements for the processor clocks. take care in selecting msel, ssel, and csel ratios so as not to exceed the maximum co re clock and system clock. table 13 describes phase-locked loop operating conditions. table 10. twi_dt field selections and v ddext /v bustwi twi_dt v ddext nominal v bustwi minimum v bustwi nominal v bustwi maximum unit 000 (default) 3.3 2.97 3.3 3.63 v 001 1.8 1.27 1.8 2.35 v 010 2.5 2.97 3.3 3.63 v 011 1.8 2.97 3.3 3.63 v 100 3.3 4.5 5 5.5 v 101 1.8 2.25 2.5 2.75 v 110 2.5 2.25 2.5 2.75 v 111 (reserved)CCCCC table 11. core clock (cclk) re quirements400 mhz speed grade 1 parameter min max unit f cclk core clock frequency (v ddint =tbd v minimum) 400 mhz f cclk core clock frequency (v ddint =tbd v minimum) tbd mhz f cclk core clock frequency (v ddint = tbd v minimum) tbd mhz f cclk core clock frequency (v ddint = tbd v minimum) tbd mhz f cclk core clock frequency (v ddint = tbd v minimum) tbd mhz 1 the speed grade of a given part is printed on the ch ips package as shown in figure 6 on page 26 and can also be seen on the ordering guide on page 62 . it stands for the maximum allowed cclk frequency at v ddint = tbd v and the maximum allowed vco frequency at any supply voltage. table 12. core clock (cclk) re quirements300 mhz speed grade 1 parameter min max unit f cclk core clock frequency (v ddint =tbd v minimum) 300 mhz f cclk core clock frequency (v ddint =tbd v minimum) tbd mhz f cclk core clock frequency (v ddint = tbd v minimum) tbd mhz f cclk core clock frequency (v ddint = tbd v minimum) tbd mhz f cclk core clock frequency (v ddint = tbd v minimum) tbd mhz 1 the speed grade of a given part is printed on the ch ips package as shown in figure 6 on page 26 and can also be seen on the ordering guide on page 62 . it stands for the maximum allowed cclk frequency at v ddint = tbd v and the maximum allowed vco frequency at any supply voltage. table 13. phase-locked loop operating conditions parameter min max unit f vco voltage controlled oscillator (vco) frequency 50 speed grade 1 mhz 1 the speed grade of a given part is printed on the ch ips package as shown in figure 6 on page 26 and can also be seen on the ordering guide on page 62 . it stands for the maximum allowed cclk frequency at v ddint = tbd v and the maximum allowed vco frequency at any supply voltage. table 14. maximum sclk conditions parameter 1 v ddext = 3.3 v, 2.5 v, or 1.8 v unit f sclk clkout/sclk frequency (v ddint tbd v) 80 mhz f sclk clkout/sclk frequency (v ddint tbd v) tbd mhz 1 f sclk must be less than or equal to f cclk and is subject to additional restrict ions for sdram interface operation. see table 22 on page 30 .
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 25 of 62 | march 2009 electrical characteristics parameter test conditions min typical max unit v oh high level output voltage v ddext /v ddmem = 1.7 v, i oh = C0.5 ma 1.35 v v oh high level output voltage v ddext /v ddmem = 2.25 v, i oh = C0.5 ma 2.0 v v oh high level output voltage v ddext /v ddmem = 3.0 v, i oh = C0.5 ma 2.4 v v ol low level output voltage v ddext /v ddmem = 1.7 v/2.25 v/3.0 v, i ol = 2.0 ma 0.4 v v oltwi low level output voltage v ddext /v ddmem = 1.7 v/2.25 v/3.0 v, i ol =2.0 ma tbd v v i ih high level input current 1 1 applies to input balls. v ddext /v ddmem =3.6 v, v in = 3.6 v 10.0 a i il low level input current 1 v ddext /v ddmem =3.6 v, v in = 0 v 10.0 a i ihp high level input current jtag 2 2 applies to jtag input balls (tck, tdi, tms, trst) . v ddext = 3.6 v, v in = 3.6 v 75.0 a i ozh three-state leakage current 3 3 applies to three-statable balls. v ddext /v ddmem = 3.6 v, v in = 3.6 v 10.0 a i ozhtwi three-state leakage current 4 4 applies to bidirection al balls scl and sda. v ddext =3.0 v, v in = 5.5 v 10.0 a i ozl three-state leakage current 3 v ddext /v ddmem = 3.6 v, v in = 0 v 10.0 a c in input capacitance 5 5 applies to all signal balls. f in = 1 mhz, t ambient = 25c, v in = 2.5 v tbd tbd 6 6 guaranteed, but not tested. pf i ddhibernate total current for all domains in hibernate state v ddext =v ddmem =v ddrtc = 3.3 v, v ddotp =v ppotp = 2.5 v, v ddint = 0 v, clkin=0 mhz, @t j = 25c tbd a i ddrtc total current for v ddrtc in hibernate state v ddrtc = 3.3 v, @t j = 25c tbd a
rev. pre | page 26 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data absolute maximum ratings stresses greater than those listed in table 15 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. when programming otp memory on the adsp- bf512/bf514/bf516/bf518(f) processor, the v ppotp pin/ball must be set to the write value specified in the operating condi- tions on page 23 . there is a finite amou nt of cumulative time that the write voltage may be a pplied (dependent on voltage and junction temperature) to v ppotp over the lifetime of the part. therefore, maximum otp memory programming time for the processor is shown in table 17 . package information the information presented in figure 6 and table 18 provides details about the package branding for the processor. for a com- plete listing of prod uct availability, see ordering guide on page 62 . esd sensitivity table 15. absolute maximum ratings parameter rating internal supply voltage (v ddint ) tbd v to +tbd v external (i/o) supply voltage (v ddext )C0.3 v to +3.8 v input voltage 1, 2 1 applies to 100% transient duty cycle. for other duty cycles see table 16 . 2 applies only when v ddext is within specifications. when v ddext is outside speci- fications, the range is v ddext 0.2 volts. C0.5 v to +3.6 v input voltage 1, 3 3 applies to signals scl, sda. C0.5 v to +5.5 v output voltage swing C0.5 v to v ddext +0.5 v load capacitance 4 4 for proper sdram controller operation, the maximum load capacitance is 50 pf (at 3.3 v) or 30 pf (at 2.5 v) for addr19C1, data15C0, abe1C0 /sdqm1C0, clkout, scke, sa10, sras , scas , swe , and sms . 200 pf storage temperature range C65 c to +150 c junction temperature underbias +110oc table 16. maximum duty cycle for input transient voltage 1 1 applies to all signal pins/balls with the exception of clkin, xtal, vrout. v in min (v) v in max (v) maximum duty cycle tbd tbd 100 % tbd tbd 40% tbd tbd 25% tbd tbd 15% tbd tbd 10% table 17. maximum otp memory programming time temperature vppotp voltage (v) 25 c85 c110 c 125 c 6.9 tbd sec tbd sec tbd sec tbd sec 7.0 2400 sec tbd sec tbd sec tbd sec 7.1 1000 sec tbd sec tbd sec tbd sec figure 6. product information on package table 18. package brand information brand key field description adsp-bf51x product name t temperature range pp package type z lead free option ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliance designator yyww date code vvvvvv.x n.n tppzccc b ads p-bf51x a #yyww country_of_origin esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality.
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 27 of 62 | march 2009 timing specifications clock and reset timing table 19 and figure 7 describe clock and reset operations. per absolute maximum ratings on page 26 , combinations of clkin and clock multipliers must not select core/peripheral clocks in excess of 400 mhz/80 mhz. table 19. clock and reset timing parameter min max unit timing requirement s t ckin clkin period 1 20.0 100.0 ns t ckinl clkin low pulse 2 10.0 ns t ckinh clkin high pulse 2 10.0 ns t bufdlay clkin to clkbuf delay 10 ns t wrst reset asserted pulse width low 3 11 t ckin ns 1 combinations of the clkin frequency and the pl l clock multiplier must no t exceed the allowed f vco , f cclk , and f sclk settings discussed in table 11 through table 14 . 2 applies to bypass mode and non-bypass mode. 3 applies after power-up sequence is complete . at power-up, the processor s internal phase-locked loop requires no more than 2000 clkin cycles, while reset is asserted, assuming stable power supplies and clkin (not incl uding start-up time of external clock oscillator). figure 7. clock and reset timing reset c c c c wr s
rev. pre | page 28 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data asynchronous memory read cycle timing table 20. asynchronous memory read cycle timing parameter min max unit timing requirements t sdat data15C0 setup before clkout 2.1 ns t hdat data15C0 hold after clkout 0.8 ns t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristic s t do output delay after clkout 1 1 output pins/balls include ams3C0 , abe1C0 , addr19C1, aoe , are . 6.0 ns t ho output hold after clkout 1 0.8 ns figure 8. asynchronous memory read cycle timing t do t s dat clkout amsx abe1C0 t ho abe, addre ss read t hdat data15C0 aoe t do t s ardy t hardy acce ss extended 3 cycle s hold 1cycle are t hardy ardy addr19C1 s etup 2cycle s programmed read acce ss 4cycle s t ho t s ardy
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 29 of 62 | march 2009 asynchronous memory write cycle timing table 21. asynchronous memory write cycle timing parameter min max unit timing requirements t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristic s t ddat data15C0 disable after clkout 6.0 ns t endat data15C0 enable after clkout 1.0 ns t do output delay after clkout 1 1 output pins/balls include ams3C0 , abe1C0 , addr19C1, data15C0, aoe, awe . 6.0 ns t ho output hold after clkout 1 0.8 ns figure 9. asynchronous memory write cycle timing t do t endat clkout am s x abe1C0 t ho write data t ddat data15C0 awe t s ardy t hardy s etup 2cycle s programmed write acce ss 2cycle s acce ss extended 1cycle hold 1cycle ardy addr19C1 t ho t s ardy t do abe, addre ss
rev. pre | page 30 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data sdram interface timing table 22. sdram interface timing v ddmem = 1.8 v v ddmem = 2.5/3.3 v parameter min max min max unit timing requirement s t ssdat data setup before clkout 1.5 1.5 ns t hsdat data hold after clkout 0.8 0.8 ns switching characteristics t sclk clkout period 1 1 the t sclk value is the inverse of the f sclk specification discussed in table 14 . package type and reduced supply voltages affect the best-case value listed here. 12.5 12.5 ns t sclkh clkout width high 2.5 2.5 ns t sclkl clkout width low 2.5 2.5 ns t dcad command, address, data delay after clkout 2 2 command pins/balls include: sras , scas , swe , sdqm, sms , sa10, scke. 4.4 4.4 ns t hcad command, address, data hold after clkout 2 1.0 1.0 ns t dsdat data disable after clkout 4.4 4.4 ns t ensdat data enable after clkout 1.0 1.0 ns figure 10. sdram interface timing t hcad t hcad t d s dat t dcad t ss dat t dcad t en s dat t h s dat t s clkl t s clkh t s clk clkout data (in) data (out) command, addre ss (out) note: command = sras , scas , swe , s dqm, sms , s a10, s cke.
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 31 of 62 | march 2009 external dma request timing table 23 and figure 11 describe the external dma request operations. table 23. external dma request timing parameter min max unit timing parameters t dr dmarx asserted to clkout high setup 6.0 ns t dh clkout high to dmarx deasserted hold time 0.0 ns t dmaract dmarx active pulse width 1.0 t sclk ns t dmarinact dmarx inactive pulse width 1.75 t sclk ns figure 11. external dma request timing clkout t dr dmar0/1 a d dmar0/1 a dmaract dmaract dmaract dmaract
rev. pre | page 32 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data parallel peripheral interface timing table 24 and figure 12 on page 32 , figure 18 on page 38 , and figure 19 on page 39 describe parallel peripheral interface operations. table 24. parallel peripheral interface timing parameter min max unit timing requirements t pclkw ppi_clk width 1 6.4 ns t pclk ppi_clk period 1 16.0 ns timing requirements - gp input and frame capture modes t sfspe external frame sync setup before ppi_clk (nonsampling edge for rx, sampling edge for tx) 6.7 ns t hfspe external frame sync hold after ppi_clk 1.0 ns t sdrpe receive data setup before ppi_clk 3.5 ns t hdrpe receive data hold after ppi_clk 1.5 ns switching characteristics - gp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 8.8 ns t hofspe internal frame sync hold after ppi_clk 1.7 ns t ddtpe transmit data delay after ppi_clk 9.0 ns t hdtpe transmit data hold after ppi_clk 1.8 ns 1 ppi_clk frequency cannot exceed f sclk /2 figure 12. ppi gp rx mode with external frame sync timing pols = 0 pols = 0 polc = 0 pols = 1 pols = 1 polc = 1 t hfspe t sfspe ppi_data ppi_clk ppi_clk ppi_fs1 ppi_fs2 t sdrpe t hdrpe data0 is sampled data1 is sampled
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 33 of 62 | march 2009 figure 13. ppi gp tx mode with external frame sync timing figure 14. ppi gp rx mode with internal frame sync timing t hdtpe t ddtpe pols = 0 pols = 0 polc = 0 pols = 1 pols = 1 data driving/ frame sync sampling edge data driving/ frame sync sampling edge polc = 1 t hfspe t sfspe ppi_data ppi_clk ppi_clk ppi_fs1 ppi_fs2 t sdrpe t hdrpe pols = 0 pols = 0 polc = 0 pols = 1 pols = 1 frame sync is driven out data0 is sampled polc = 1 t dfspe t hofspe ppi_clk ppi_clk ppi_fs1 ppi_fs2 ppi_data
rev. pre | page 34 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data figure 15. ppi gp tx mode with internal frame sync timing t hdtpe t ddtpe pols = 0 pols = 0 polc = 0 pols = 1 pols = 1 frame sync is driven out data0 is driven out polc = 1 t dfspe t hofspe ppi_data ppi_clk ppi_clk ppi_fs1 ppi_fs2 data0
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 35 of 62 | march 2009 sd/sdio controller timing table 25 and figure 16 describe sd/sdio controller timing. table 26 and figure 17 describe sd/sdio controller (high speed) timing. table 25. sd/sdio controller timing parameter min max unit timing requirements t isu input setup time 7.2 ns t ih input hold time 2 ns switching characteristics f pp clock frequency data transfer mode 0 20 mhz f od clock frequency identification mode 0 1 /100 400 khz t wl clock low time 15 ns t wh clock high time 15 ns t tlh clock rise time 10 ns t thl clock fall time 10 ns t odly output delay time during data transfer mode C1 14 ns t odly output delay time during identification mode C1 50 ns 1 0 khz means to stop the clock. the given minimum frequency range is for cases where a co ntinuous clock is required. figure 16. sd/sdio controller timing input sd_clk t odly(max) t pp t wl t wh t thl t tlh t isu t ih t odly(min) voh (min) vol (max) output 1 2 1 input includes sd_dx and sd_cmd 2 output includes sd_dx and sd_cmd
rev. pre | page 36 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data table 26. sd/sdio controller timing (high speed mode) parameter min max unit timing requirements t isu input setup time 7.2 ns t ih input hold time 2ns switching characteristics f pp clock frequency data transfer mode 0 40 mhz t wl clock low time 9.5 ns t wh clock high time 9.5 ns t tlh clock rise time 3ns t thl clock fall time 3ns t odly output delay time during data transfer mode 2 ns t oh output hold time 2.5 ns figure 17. sd/sdio controller timing (high-speed mode) t odly t pp t wl t wh t thl t tlh t isu t ih t oh 1.5 v sd_clk input output 1 2 1 input includes sd_dx and sd_cmd 2 output includes sd_dx and sd_cmd
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 37 of 62 | march 2009 serial ports table 27 through table 30 on page 38 and figure 18 on page 38 through figure 19 on page 39 describe serial port operations. table 27. serial portsexternal clock parameter min max unit timing requirements t sfse tfsx/rfsx setup before tsclkx/rsclkx 1 3.0 ns t hfse tfsx/rfsx hold after tsclkx/rsclkx 1 3.0 ns t sdre receive data setup before rsclkx 1 3.0 ns t hdre receive data hold after rsclkx 1 3.6 ns t sclkew tsclkx/rsclkx width 5.4 ns t sclke tsclkx/rsclkx period 8.0 ns switching characteristics t dfse tfsx/rfsx delay after tsclkx/rsclk x (internally generated tfsx/rfsx) 2 12.0 ns t hofse tfsx/rfsx hold after tsclkx/rsclk x (internally generated tfsx/rfsx) 1 0.0 ns t ddte transmit data delay after tsclkx 1 12.0 ns t hdte transmit data hold after tsclkx 1 0.0 ns 1 referenced to sample edge. 2 referenced to drive edge. table 28. serial portsinternal clock parameter min max unit timing requirements t sfsi tfsx/rfsx setup before tsclkx/rsclkx 1 11.3 ns t hfsi tfsx/rfsx hold after tsclkx/rsclkx 1 C1.5 ns t sdri receive data setup before rsclkx 1 11.3 ns t hdri receive data hold after rsclkx 1 C1.5 ns t sclkew tsclkx/rsclkx width 5.4 ns t sclke tsclkx/rsclkx period 18.0 ns switching characteristics t dfsi tfsx/rfsx delay after tsclkx/rsclk x (internally generated tfsx/rfsx) 2 3.0 ns t hofsi tfsx/rfsx hold after tsclkx/rsclk x (internally generated tfsx/rfsx) 1 ? 4.0 ns t ddti transmit data delay after tsclkx 1 3.0 ns t hdti transmit data hold after tsclkx 1 ? 1.8 ns t sclkiw tsclkx/rsclkx width 5.4 ns 1 referenced to sample edge. 2 referenced to drive edge. table 29. serial portsenable and three-state parameter min max unit switching characteristics t dtene data enable delay from external tsclkx 1 0.0 ns t ddtte data disable delay from external tsclkx 1 10.0 ns t dteni data enable delay from internal tsclkx 1 C2.0 ns t ddtti data disable delay from internal tsclkx 1 3.0 ns 1 referenced to drive edge.
rev. pre | page 38 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data table 30. external late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external tfsx or external rfsx with mce = 1, mfd = 0 1, 2 10.0 ns t dtenlfse data enable from late fs or mce = 1, mfd = 0 1, 2 0.0 ns 1 mce = 1, tfsx enable and tfsx valid follow t ddtenfs and t ddtlfse . 2 if external rfsx/tfsx setu p to rsclkx/tsclkx t sclke /2 then t ddtte/i and t dtene/i apply, otherwise t ddtlfse and t dtenlfs apply. figure 18. serial ports t s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 39 of 62 | march 2009 figure 19. external late frame sync t ddtlf s e t s f s e/i t dtene/i r s clkx drive drive s ample rfs x dtx 2nd bit 1 s tbit t dtenlf s t ddtte/i t hof s e/i t dtenlf s t s f s e/i t dtene/i drive drive s ample dtx t s clkx tf s x 2nd bit 1 s tbit t ddtlf s e t ddtte/i t hof s e/i external rf s xwithmce=1,mfd=0 late external tf s x
rev. pre | page 40 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data serial peripheral interface (spi) portmaster timing table 31 and figure 20 describe spi port master operations. table 31. serial peripheral interface (spi) portmaster timing parameter min max unit timing requirements t sspidm data input valid to sck edge (data input setup) 11.6 ns t hspidm sck sampling edge to data input invalid C1.5 ns switching characteristics t sdscim spiselx low to first sck edge 2 t sclk C1.5 ns t spichm serial clock high period 2 t sclk C1.5 ns t spiclm serial clock low period 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk ns t hdsm last sck edge to spiselx high 2 t sclk C1.5 ns t spitdm sequential transfer delay 2 t sclk ns t ddspidm sck edge to data out valid (data out delay) 0 6 ns t hdspidm sck edge to data out invalid (data out hold) C1.0 4.0 ns figure 20. serial peripheral interface (spi) portmaster timing t sspidm t hspidm t ddspidm lsb msb t hdspidm mosix (output) misox (input) spixsely p sx pl p sx pl p spi spil spil spil spi s spi ls s spi spi six p isx ip sspi p p s ssi li spi ls li s li li ls
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 41 of 62 | march 2009 serial peripheral interface (spi) portslave timing table 32 and figure 21 describe spi port slave operations. table 32. serial peripheral interface (spi) portslave timing parameter min max unit timing requirements t spichs serial clock high period 2 t sclk C1.5 ns t spicls serial clock low period 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk C1.5 ns t hds last sck edge to spiss not asserted 2 t sclk C1.5 ns t spitds sequential transfer delay 2 t sclk C1.5 ns t sdsci spiss assertion to first sck edge 2 t sclk ns t sspid data input valid to sck edge (data input setup) 1.6 ns t hspid sck sampling edge to data input invalid 1.6 ns switching characteristics t dsoe spiss assertion to data out active 0 8.5 ns t dsdhi spiss deassertion to data high impedance 0 8.5 ns t ddspid sck edge to data out valid (data out delay) 10 ns t hdspid sck edge to data out invalid (data out hold) 0 ns figure 21. serial peripheral interface (spi) portslave timing t hdspid t ddspid t dsdhi lsb msb msb t hspid t dsoe t ddspid t hdspid misox (output) mosix (input) t sspid spixss ip sx pl ip sx pl ip ssi spis spils spils spil s spis sspi spi si ls s s se spi isx p six ip ls ls p p spis spi li li li li spi
rev. pre | page 42 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data general-purpose port timing table 33 and figure 22 describe general-purpose port operations. timer clock timing table 34 and figure 23 describe timer clock timing. table 33. general-purpose port timing parameter min max unit timing requirement t wfi general-purpose port signal input pulse width t sclk + 1 ns switching characteristics t gpod general-purpose port signal output delay from clkout low 0 9.66 ns figure 22. general-purpose port timing gpp input gpp output clkout t gpod t wfi table 34. timer clock timing parameter min max unit switching characteristic t todp timer output update delay after ppiclk high 12.64 ns figure 23. timer clock timing timer output ppi clock t todp
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 43 of 62 | march 2009 timer cycle timing table 35 and figure 24 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk /2) mhz. table 35. timer cycle timing parameter min max unit timing characteristics t wl timer pulse width input low (measured in sclk cycles) 1 1 t sclk ns t wh timer pulse width input high (measured in sclk cycles) 1 1 t sclk ns t tis timer input setup time before clkout low 2 5n s t tih timer input hold time after clkout low 2 C2 ns switching characteristics t hto timer pulse width output (measured in sclk cycles) 1 t sclk (2 32 C1)t sclk ns t tod timer output update delay after clkout high 8.1 ns 1 the minimum pulse widths apply for tmrx sign als in width capture and external clock modes. they also apply to the pf15 or ppi_c lk signals in pwm output mode. 2 either a valid setup and hold time or a valid pulse width is suff icient. there is no need to re synchronize programmable flag in puts. figure 24. timer cycle timing timer input timer output clkout t ti s
rev. pre | page 44 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data up/down counter/rotary encoder timing 10/100 ethernet mac controller timing table 37 through table 42 and figure 26 through figure 31 describe the 10/100 ethernet mac cont roller operations. table 36. up/down counter/rotary encoder timing parameter v ddext 1.8 v v ddext 2.5/3.3 v min max min max unit timing requirements t wcount up/down counter/rotary encoder input pulse width t sclk + 1 t sclk + 1 ns t cis counter input setup time before clkout low 1 1 either a valid setup and hold time or a valid pulse width is su fficient. there is no need to resynchronize counter inputs. 4.0 4.0 ns t cih counter input hold time after clkout low1 4.0 4.0 ns figure 25. up/down counter/rotary encoder timing cud/cdg/czm clk out t cis t cih t wcount table 37. 10/100 ethernet mac controll er timing: mii receive signal parameter 1 min max unit t erxclkf erxclk frequency (f sclk = sclk frequency) none 25 mhz + 1% f sclk + 1% ns t erxclkw erxclk width (t erxclk = erxclk period) t erxclk x 35% t erxclk x 65% ns t erxclkis rx input valid to erxclk rising edge (data in setup) 7.5 ns t erxclkih erxclk rising edge to rx input invalid (data in hold) 7.5 ns 1 mii inputs synchronous to erxclk are erxd3C0, erxdv, and erxer. table 38. 10/100 ethernet mac controll er timing: mii transmit signal parameter 1 min max unit t etf etxclk frequency (f sclk = sclk frequency) none 25 mhz + 1% f sclk + 1% ns t etxclkw etxclk width (t etxclk = etxclk period) t etxclk x 35% t etxclk x 65% ns t etxclkov etxclk rising edge to tx output valid (data out valid) 20 ns t etxclkoh etxclk rising edge to tx output invalid (data out hold) 0 ns 1 mii outputs synchronous to etxclk are etxd3C0.
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 45 of 62 | march 2009 table 39. 10/100 ethernet mac controll er timing: rmii receive signal parameter 1 min max unit t erefclkf ref_clk frequency (f sclk = sclk frequency) none 50 mhz + 1% 2 x f sclk + 1% ns t erefclkw eref_clk width (t erefclk = erefclk period) t erefclk x 35% t erefclk x 65% ns t erefclkis rx input valid to rmii ref_clk rising edge (data in setup) 4 ns t erefclkih rmii ref_clk rising edge to rx input invalid (data in hold) 2 ns 1 rmii inputs synchronous to rmii ref_clk are erxd1C0, rmii crs_dv, and erxer. table 40. 10/100 ethernet mac controller timing: rmii transmit signal parameter 1 min max unit t erefclkov rmii ref_clk rising edge to tx output valid (data out valid) 8.1 ns t erefclkoh rmii ref_clk rising edge to tx output invalid (data out hold) 2 ns 1 rmii outputs synchronous to rmii ref_clk are etxd1C0. table 41. 10/100 ethernet mac controller timing: mii/rmii asynchronous signal parameter 1, 2 min max unit t ecolh col pulse width high t etxclk x 1.5 t erxclk x 1.5 ns t ecoll col pulse width low t etxclk x 1.5 t erxclk x 1.5 ns t ecrsh crs pulse width high t etxclk x 1.5 ns t ecrsl crs pulse width low t etxclk x 1.5 ns 1 mii/rmii asynchronous signals are col, crs. these signals are applicable in both mii and rmii modes. the asynchronous col input is synchronized se parately to both the etxclk and the erxclk, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the t wo clocks. 2 the asynchronous crs input is synchronized to the etxclk, and mus t have a minimum pulse width high or low at least 1.5 times th e period of etxclk. table 42. 10/100 ethernet mac controller timing: mii station management parameter 1 min max unit t mdios mdio input valid to mdc rising edge (setup) 11.5 ns t mdcih mdc rising edge to mdio input invalid (hold) 11.5 ns t mdcov mdc falling edge to mdio output valid 25 ns t mdcoh mdc falling edge to mdio output invalid (hold) C1 ns 1 mdc/mdio is a 2-wire serial bidirectional port for controlling one or more external phys. mdc is an output clock whose minimum period is programmable as a multiple of the system clock sclk. mdio is a bidirectional data line. figure 26. 10/100 ethernet mac controller timing: mii receive signal erxd 3 s
rev. pre | page 46 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data figure 27. 10/100 ethernet mac controller timing: mii transmit signal figure 28. 10/100 ethernet mac controller timing: rmii receive signal figure 29. 10/100 ethernet mac controller timing: rmii transmit signal figure 30. 10/100 ethernet mac controller timing: asynchronous signal etxd 3 -0 etxen mii txclk t etxclk t etxclkoh t etxclkov t etxclkw erxd1-0 erxdv erxer erxclk t refclk t erxclki s t erxclkih t refclkw etxd1-0 etxen rmii ref_clk t refclk t erefclkoh t erefclkov mii cr s ,col t ecr s h t ecr s l t ecolh t ecoll
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 47 of 62 | march 2009 figure 31. 10/100 ethernet mac contro ller timing: mii station management mdio (output) mdc (output) t mdcoh t mdio s t mdcih mdio (input) t mdcov
rev. pre | page 48 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data jtag test and emulation port timing table 43 and figure 32 describe jtag port operations. table 43. jtag port timing parameter min max unit timing parameters t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setup before tck high 1 4n s t hsys system inputs hold after tck high 1 5n s t trstw trst pulse width 2 (measured in tck cycles) 4 tck switching characteristics t dtdo tdo delay from tck low 10 ns t dsys system outputs delay after tck low 3 01 2n s 1 system inputs = data15C0, scl, sda, tfs0, tsclk0, rsclk0, rfs0, dr0pri, dr0sec, pf15C0, pg15C0, ph7C0, mdio, tck, td1, tms, trs t , reset , nmi , bmode2C0. 2 50 mhz maximum 3 system outputs = data15C0, addr19C1, abe1C0 , are , awe , ams1C0 , sras , scas , swe , scke, clkout, sa10, sms , scl, sda, tsclk0, tfs0, rfs0, rsclk0, dt0pri, dt0sec, pf15C0, pg15C0, ph7C0, mdc, mdio, td0, emu . figure 32. jtag port timing tm s tdi tdo s y s tem input s s y s tem output s tck t tck t htap t s tap t dtdo t ss y s t h s y s t d s y s
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 49 of 62 | march 2009 output drive currents figure 33 through figure 44 show typical current-voltage char- acteristics for the output drivers of the processors. the curves represent the current drive capability of the output drivers as a function of output voltage. see table 9 on page 20 for informa- tion about which driver type corresponds to a particular pin/ball. figure 33. drive current a (low v ddext ) figure 34. drive current a (high v ddext ) source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd t t tbd figure 35. drive current b (low v ddext ) figure 36. drive current b (high v ddext ) figure 37. drive current c (low v ddext ) source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd t t tbd t t tbd
rev. pre | page 50 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data figure 38. drive current c (high v ddext ) figure 39. drive current d (low v ddext ) figure 40. drive current d (high v ddext ) source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd figure 41. drive current e (low v ddext ) figure 42. drive current e (high v ddext ) figure 43. drive current f (low v ddext ) source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 51 of 62 | march 2009 power dissipation total power dissipation has two components: one due to inter- nal circuitry (p int ) and one due to the switching of external output drivers (p ext ). see the adsp-bf51x blackfin proc essor hardware reference manual for definitions of the vari ous operating modes and for instructions on how to minimize system power. many operating conditions can a ffect power dissipation. system designers should refer to (ee-tbd) estimating power for adsp-bf512/bf514/bf516/bf518(f) blackfin processors on the analog devices website ( www.analog.com )use site search on ee-tbd. that document provides detailed information for optimizing your design for lowest power. test conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. figure 45 shows the measurement point fo r ac measurements (except output enable/disable). the measurement point v meas is v ddext /2 or v ddmem /2 for v ddext /v ddmem (nominal) = 2.5 v/3.3 v. output enable time measurement output signals are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of figure 46 . the time t ena _ measured is the interval, from when the reference sig- nal switches, to when the output voltage reaches v trip (high) or v trip (low). v trip (high) is 2.0 v and v trip (low) is 1.0 v for v ddext /v ddmem (nominal) = 2.5 v/3.3 v. time t trip is the interval from when the output starts driv ing to when the output reaches the v trip (high) or v trip (low) trip voltage. time t ena is calculated as shown in the equation: if multiple signals (such as the data bus) are enabled, the mea- surement value is that of the first signal to start driving. output disable time measurement output signals are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltag e. the output disable time t dis is the difference between t dis _ measured and t decay as shown on the left side of figure 46 . the time for the voltage on the bus to decay by v is dependent on the capacitive load c l and the load current i l . this decay time can be approximated by the equation: the time t decay is calculated with test loads c l and i l , and with v equal to 0.5 v for v ddext /v ddmem (nominal) = 2.5 v/3.3 v. the time t dis _ measured is the interval from when the reference sig- nal switches, to when the output voltage decays v from the measured output high or output low voltage. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the adsp- figure 44. drive current f (high v ddext ) figure 45. voltage reference levels for ac measurements (except output enable/disable) source current (ma) source voltage (v) 150 100 50 0 C50 C100 C150 0 0.5 1.0 1.5 2.0 2.5 3.0 tbd t tt s s figure 46. output enable/disable reference s s s s s s s s s s s s s s s s t ena t ena_measured t trip ? = t dis t dis_measured t decay ? = t decay c l v () i l ? =
rev. pre | page 52 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data bf512/bf514/bf516/bf518(f) proces sors output voltage and the input threshold for the device requiring the hold time. c l is the total bus capacitance (per data line), and i l is the total leak- age or three-state current (per data line). the hold time will be t decay plus the various output disa ble times as specified in the timing specifications on page 27 (for example t dsdat for an sdram write cycle as shown in sdram interface timing on page 30 ). capacitive loading output delays and holds are based on standard capa citive loads: 30 pf on all pins/balls (see figure 47 ). v load is 1.5 v for v ddext (nominal) = 2.5 v/3.3 v. figure 48 on page 52 through figure 55 on page 53 show how output rise time varies with capacitance. the delay and hold specifications given should be derated by a factor derived from these figures. the graphs in these figures may not be linear outside the ranges shown. figure 47. equivalent device loading for ac measurements (includes all fixtures) t1 zo 50:(impedance) td = 4.04 r 1.18 ns 2pf tester pin electronics 50 : 0.5pf 70 : 400 : 45 : 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td), is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 : figure 48. typical rise and fall times (10%C90%) versus load capacitance for driver a at evdd min figure 49. typical rise and fall times (10%C90%) versus load capacitance for driver a at evdd max figure 50. typical rise and fall times (10%C90%) versus load capacitance for driver b at evdd min tbd tbd tbd
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 53 of 62 | march 2009 figure 51. typical rise and fall times (10%C90%) versus load capacitance for driver b at evdd max figure 52. typical rise and fall times (10%C90%) versus load capacitance for driver c at evdd min figure 53. typical rise and fall times (10%C90%) versus load capacitance for driver c at evdd max tbd tbd tbd figure 54. typical rise and fall times (10%C90%) versus load capacitance for driver d at evdd min figure 55. typical rise and fall times (10%C90%) versus load capacitance for driver d at evdd max tbd tbd
rev. pre | page 54 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data thermal characteristics to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature ( c) t case = case temperature ( c) measured by customer at top center of package. jt = from table 45 p d = power dissipation (see power dissipation on page 51 for the method to calculate p d ) values of ja are provided for packag e comparison and printed circuit board design considerations. ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature ( c) values of jc are provided for package comparison and printed circuit board design considerations when an external heat sink is required. values of jb are provided for packag e comparison and printed circuit board design considerations. in table 45 , airflow measurements comply with jedec stan- dards jesd51-2 and jesd51-6, and the junction-to-board measurement complies with je sd51-8. the junction-to-case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. the lqfp-ep package requires th ermal trace squares and ther- mal vias, to an embedded ground plane, in the pcb. the paddle must be connected to ground for proper operation to data sheet specifications. refer to jedec standard jesd51-5 for more information. t j t case jt p d () += t j t a ja p d () += table 44. thermal characteristics for sq-176-2 package parameter condition typical unit ja 0 linear m/s airflow tbd c/w jma 1 linear m/s airflow tbd c/w jma 2 linear m/s airflow tbd c/w jc not applicable tbd c/w jt 0 linear m/s airflow tbd c/w jt 1 linear m/s airflow tbd c/w jt 2 linear m/s airflow tbd c/w table 45. thermal characteri stics for bc-168-1 package parameter condition typical unit ja 0 linear m/s airflow tbd c/w jma 1 linear m/s airflow tbd c/w jma 2 linear m/s airflow tbd c/w jc not applicable tbd c/w jt 0 linear m/s airflow tbd c/w jt 1 linear m/s airflow tbd c/w jt 2 linear m/s airflow tbd c/w
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 55 of 62 | march 2009 176-lead lqfp lead assignment table 46 lists the lqfp leads by lead number. table 47 on page 56 lists the lqfp by signal mnemonic. table 46. 176-lead lqfp pi n assignment (numerically by lead number) lead no. signal lead no. signal lead no. signal lead no. signal 1 gnd 45 gnd 89 gnd 133 gnd 2 gnd 46 gnd 90 gnd 134 gnd 3 pf9 47 pg1 91 a12 135 pg 4 pf8 48 pg0 92 a11 136 v ddext 5p f 74 9v ddext 93 a10 137 gnd 6p f 65 0t d o9 4a 91 3 8v ddint 7v ddext 51 emu 95 v ddmem 139 gnd 8v ppotp 52 tdi 96 a8 140 rtxo 9v ddotp 53 tck 97 a7 141 rtxi 10 pf5 54 trst 98 v ddint 142 v ddrtc 11 pf4 55 tms 99 gnd 143 clkin 12 pf3 56 d15 100 v ddint 144 xtal 13 pf2 57 d14 101 a6 145 v ddext 14 v ddint 58 d13 102 a5 146 reset 15 gnd 59 v ddmem 103 a4 147 nmi 16 v ddflash 60 d12 104 v ddmem 148 v ddext 17 v ddflash 61 d11 105 a3 149 gnd 18 pf1 62 d10 106 a2 150 clkbuf 19 pf0 63 v ddint 107 a1 151 gnd 20 pg15 64 d9 108 abe 11 5 2 v ddint 21 pg14 65 d8 109 abe 01 5 3 p h 7 22 gnd 66 d7 110 sa10 154 ph6 23 v ddint 67 gnd 111 gnd 155 ph5 24 v ddext 68 v ddmem 112 v ddmem 156 ph4 25 pg13 69 d6 113 swe 157 gnd 26 pg12 70 d5 114 scas 158 v ddext 27 pg11 71 d4 115 sras 159 ph3 28 pg10 72 d3 116 v ddint 160 ph2 29 v ddflash 73 d2 117 gnd 161 ph1 30 v ddint 74 d1 118 sms 162 ph0 31 pg9 75 v ddmem 119 scke 163 gnd 32 pg8 76 d0 120 ams 1164 v ddint 33 pg7 77 a19 121 are 165 pf15 34 pg6 78 a18 122 awe 166 pf14 35 v ddext 79 v ddint 123 ams 0167 pf13 36 pg5 80 a17 124 v ddmem 168 pf12 37 pg4 81 a16 125 clkout 169 gnd 38 pg3 82 v ddmem 126 v ddflash 170 v ddext 39 pg2 83 gnd 127 nc 1 171 pf11 40 bmode2 84 a15 128 v ddext 172 sda 41 bmode1 85 a14 129 v ddext 173 scl 42 bmode0 86 a13 130 ext_wake 174 pf10 43 gnd 87 gnd 131 gnd 175 gnd 44 gnd 88 gnd 132 gnd 176 gnd 1 this pin must not be connected.
rev. pre | page 56 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data table 47. 176-lead lqfp pin assignment (alphabetically by signal mnemonic) lead no. signal lead no. signal lead no. signal lead no. signal 107 a1 58 d13 4 pf8 53 tck 106 a2 57 d14 3 pf9 52 tdi 105 a3 56 d15 174 pf10 50 tdo 103 a4 51 emu 171 pf11 117 gnd 102 a5 130 ext_wake 168 pf12 55 tms 101 a6 1 gnd 167 pf13 54 trst 97 a7 2 gnd 166 pf14 7 v ddext 96 a8 15 gnd 165 pf15 24 v ddext 94 a9 22 gnd 135 pg 35 v ddext 93 a10 43 gnd 48 pg0 49 v ddext 92 a11 44 gnd 47 pg1 128 v ddext 91 a12 45 gnd 39 pg2 129 v ddext 86 a13 46 gnd 38 pg3 136 v ddext 85 a14 67 gnd 37 pg4 145 v ddext 84 a15 83 gnd 36 pg5 148 v ddext 81 a16 87 gnd 34 pg6 158 v ddext 80 a17 88 gnd 33 pg7 170 v ddext 78 a18 89 gnd 32 pg8 16 v ddflash 77 a19 90 gnd 31 pg9 17 v ddflash 109 abe 0 99 gnd 28 pg10 29 v ddflash 108 abe 1 111 gnd 27 pg11 126 v ddflash 123 ams 0 131 gnd 26 pg12 14 v ddint 120 ams 1 132 gnd 25 pg13 23 v ddint 121 are 133 gnd 21 pg14 30 v ddint 122 awe 134 gnd 20 pg15 63 v ddint 42 bmode0 137 gnd 162 ph0 79 v ddint 41 bmode1 139 gnd 161 ph1 98 v ddint 40 bmode2 149 gnd 160 ph2 100 v ddint 150 clkbuf 151 gnd 159 ph3 116 v ddint 143 clkin 157 gnd 156 ph4 138 v ddint 125 clkout 163 gnd 155 ph5 152 v ddint 76 d0 169 gnd 154 ph6 164 v ddint 74 d1 175 gnd 153 ph7 59 v ddmem 73 d2 176 gnd 146 reset 68 v ddmem 72 d3 127 nc 1 141 rtxi 75 v ddmem 71 d4 147 nmi 140 rtxo 82 v ddmem 70 d5 19 pf0 110 sa10 95 v ddmem 69 d6 18 pf1 114 scas 104 v ddmem 66 d7 13 pf2 119 scke 112 v ddmem 65 d8 12 pf3 173 scl 124 v ddmem 64 d9 11 pf4 172 sda 9 v ddotp 62 d10 10 pf5 118 sms 142 v ddrtc 61 d11 6 pf6 115 sras 8v ppotp 60 d12 5 pf7 113 swe 144 xtal 1 this pin must not be connected.
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 57 of 62 | march 2009 168-ball csp_bga ball assignment table 48 lists the csp_bga by ball number. table 49 on page 58 lists the csp_bga balls by signal mnemonic. table 48. 168-ball csp_bga ball assignme nt (numerically by ball number) ball no. signal name ball no. signal name ball no. signal name ball no. signal name ball no. signal name ball no. signal name a1 gnd c1 pf4 e10 v ddint h1 pg12 k6 v ddmem n1 bmode1 a2 scl c2 pf7 e12 v ddmem h2 pg13 k7 v ddmem n2 pg1 a3 sda c3 pf8 e13 are h3 pg11 k8 v ddmem n3 tdo a4 pf13 c4 pf10 e14 awe h5 v ddext k9 v ddmem n4 trst a5 pf15 c5 v ddext f1 pf0 h6 gnd k10 v ddmem n5 tms a6 ph2 c6 v ddext f2 pf1 h7 gnd k12 a8 n6 d13 a7 ph1 c7 pf11 f3 v ddint h8 gnd k13 a2 n7 d9 a8 ph5 c8 v ddext f5 v ddext h9 gnd k14 a1 n8 d5 a9 ph6 c9 v ddint f6 gnd h10 v ddint l1 pg5 n9 d1 a10 ph7 c10 v ddext f7 gnd h12 a3 l2 pg3 n10 a18 a11 clkbuf c11 rtxi f8 gnd h13 abe 0l3pg2 n11a16 a12 xtal c12 rtxo f9 gnd h14 scas l12 a9 n12 a14 a13 clkin c13 pg f10 v ddint j1 pg10 l13 a6 n13 a11 a14 gnd c14 nc 1 f12 sms j2 v ddflash l14 a4 n14 a7 b1 v ddotp d1 pf3 f13 scke j3 pg9 m1 pg4 p1 gnd b2 gnd d2 pf5 f14 ams 1j5v ddmem m2 bmode2 p2 tdi b3 pf9 d3 vppotp g1 pg15 j6 gnd m3 bmode0 p3 tck b4 pf12 d12 v ddflash g2 pg14 j7 gnd m4 pg0 p4 d15 b5 pf14 d13 clkout g3 v ddint j8 gnd m5 emu p5 d14 b6 ph0 d14 ams 0g5v ddext j9 gnd m6 d12 p6 d11 b7 ph3 e1 v ddflash g6 gnd j10 v ddint m7 d10 p7 d8 b8 ph4 e2 pf2 g7 gnd j12 a15 m8 d2 p8 d7 b9 v ddext e3 pf6 g8 gnd j13 abe 1m9d0 p9d6 b10 reset e5 v ddext g9 gnd j14 sa10 m10 a17 p10 d4 b11 nmi e6 v ddext g10 v ddint k1 pg6 m11 a13 p11 d3 b12 v ddrtc e7 v ddint g12 swe k2 pg8 m12 a12 p12 a19 b13 v ddext e8 v ddint g13 sras k3 pg7 m13 a10 p13 gnd b14 ext_wake e9 v ddint g14 gnd k5 v ddmem m14 a5 p14 gnd 1 this pin must not be connected.
rev. pre | page 58 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data table 49. 168-ball csp_bga ball assignment (alphabetically by signal mnemonic) ball no. signal name ball no. signal name ball no. signal name ball no. signal name ball no. signal name ball no. signal name k14 a1 a11 clkbuf g6 gnd c7 pf11 a9 ph6 g5 v ddext k13 a2 a13 clkin g7 gnd b4 pf12 a10 ph7 h5 v ddext h12 a3 d13 clkout g8 gnd a4 pf13 b10 reset d12 v ddflash l14 a4 m9 d0 g9 gnd b5 pf14 c11 rtxi e1 v ddflash m14 a5 n9 d1 h6 gnd a5 pf15 c12 rtxo j2 v ddflash l13 a6 m8 d2 h7 gnd c13 pg j14 sa10 c9 v ddint n14 a7 p11 d3 h8 gnd m4 pg0 h14 scas e7 v ddint k12 a8 p10 d4 h9 gnd n2 pg1 f13 scke e8 v ddint l12 a9 n8 d5 j6 gnd l3 pg2 a2 scl e9 v ddint m13 a10 p9 d6 j7 gnd l2 pg3 a3 sda e10 v ddint n13 a11 p8 d7 j8 gnd m1 pg4 f12 sms f3 v ddint m12 a12 p7 d8 j9 gnd l1 pg5 g13 sras f10 v ddint m11 a13 n7 d9 p1 gnd k1 pg6 g12 swe g3 v ddint n12 a14 m7 d10 p13 gnd k3 pg7 p3 tck g10 v ddint j12 a15 p6 d11 p14 gnd k2 pg8 p2 tdi h10 v ddint n11 a16 m6 d12 c14 nc 1 j3 pg9 n3 tdo j10 v ddint m10 a17 n6 d13 b11 nmi j1 pg10 g14 gnd e12 v ddmem n10 a18 p5 d14 f1 pf0 h3 pg11 n5 tms j5 v ddmem p12 a19 p4 d15 f2 pf1 h1 pg12 n4 trst k5 v ddmem h13 abe 0m5emu e2pf2 h2pg13b9v ddext k6 v ddmem j13 abe 1 b14 ext_wake d1 pf3 g2 pg14 b13 v ddext k7 v ddmem d14 ams 0a1gnd c1pf4 g1pg15 c5v ddext k8 v ddmem f14 ams 1 a14 gnd d2 pf5 b6 ph0 c6 v ddext k9 v ddmem e13 are b2 gnd e3 pf6 a7 ph1 c8 v ddext k10 v ddmem e14 awe f6 gnd c2 pf7 a6 ph2 c10 v ddext b1 v ddotp m3 bmode0 f7 gnd c3 pf8 b7 ph3 e5 v ddext b12 v ddrtc n1 bmode1 f8 gnd b3 pf9 b8 ph4 e6 v ddext d3 vppotp m2 bmode2 f9 gnd c4 pf10 a8 ph5 f5 v ddext a12 xtal 1 this pin must not be connected.
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 59 of 62 | march 2009 figure 56 shows the top view of the csp_bga ball configura- tion. figure 57 shows the bottom view of the csp_bga ball configuration. figure 56. 168-ball csp_bga ba ll configuration (top view) figure 57. 168-ball csp_bga ball configuration (bottom view) a1 ball pad corner top view a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11121314 v ddint v ddext gnd i/o key v ddrtc v ddmem v ddflash nc a1 ball pad corner bottom view a b c d e f g h j k l m n p 1413121110987654321 v ddint v ddext gnd i/o key v ddrtc v ddmem v ddflash nc
rev. pre | page 60 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data outline dimensions dimensions in figure 58 are shown in millimeters. figure 58. 176-lead low profile quad flat package [lqfp_ep] (sq-176-2) dimensions shown in millimeters compliant to jedec standards ms-026-bga-hd 1.45 1.40 1.35 0.15 0.10 0.05 top view (pins down) 133 1 132 45 44 88 89 176 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 26.20 26.00 sq 25.80 24.10 24.00 sq 23.90 view a pin 1 0.08 max coplanarity view a rotated 90 ccw seating plane 12 7 0 0.20 0.15 0.09 0.75 0.60 0.45 1.00 ref bottom view (pins up) 133 1 132 45 44 88 89 176 exposed pad exposed pad is centered on the package. 5.80 ref sq note: the exposed pad is required to be electrically and thermally connected to vss. implement this by soldering the exposed pad to a vss pcb land that is the same size as the exposed pad. the vss pcb land should be robustly connected to the vss plane in the pcb with an array of thermal vias for best performance.
adsp-bf512/bf514/bf516/bf518(f) preliminary technical data rev. pre | page 61 of 62 | march 2009 surface mount design table 50 is provided as an aide to pcb design. for industry- standard design recommendations, refer to ipc-7351, generic requirements for surface mount design and land pattern standard . figure 59. 168-ball chip scale package ball grid array csp_bga (bc-168-1) dimensions shown in millimeters compliant to jedec standards mo-275-ggab-1. 0.80 bsc 0.56 0.70 a b c d e f g 98 11 1013 12 7 6 5 4 2 31 bottom view 10.40 bsc sq h j k l m n p 0.34 nom 0.29 min detail a top view detail a coplanarity 0.20 0.50 0.45 0.40 ball diameter seating plane 12.10 12.00 sq 11.90 a1 ball corner a1 ball corner 1.70 1.60 1.45 1.36 1.26 1.16 14 table 50. bga data for use with surface-mount design package ball attach type solder mask opening ball pad size 168-ball csp_bga solder mask defined tbd mm diameter tbd mm diameter
rev. pre | page 62 of 62 | march 2009 adsp-bf512/bf514/bf516/bf518(f) preliminary technical data ? 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr08155-0-3/09(pre) ordering guide model 1 1 z = rohs compliant part. temperature range 2 2 referenced temperature is ambient temperature. speed grade (max) flash memory package description package option ADSP-BF518kswz-eng 0 c to +70 c 400 mhz n/a 176-lead lqfp_ep sq-176-2

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