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a t dsp microcomputer information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringeme nts of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. rev. 0 tigersharc and the tigersharc logo are registered trademarks of analog devices, inc. adsp-ts101s key features 250 mhz, 4.0 ns inst ruction cycle rate 6m bits of internal?on-chip?sram memory 19 19 mm (484-ball) or 27 27 mm (625-ball) pbga package dual computation blocks?each containing an alu, a multiplier, a shifter, and a register file dual integer alus, providing data addressing and pointer manipulation integrated i/o includes 14 channel dma controller, external port, four link ports, sdram controller, programmable flag pins, two timers, and timer expired pin for system integration 1149.1 ieee compliant jtag test access port for on-chip emulation on-chip arbitration for gluel ess multiprocessing with up to eight tigersharc ? dsps on a common bus key benefits provides high performance static superscalar dsp operations, optimized for telecommunications infrastructure and other large, demanding multiprocessor dsp applications performs exceptionally well on dsp algorithm and i/o benchmarks (see benchmarks in table 1 and table 2 ) supports low overhead dma transfers between internal memory, external memory, memory-mapped peripherals, link ports, host processors, and other (multiprocessor) dsps eases dsp programming through extremely flexible instruction set and high level language friendly dsp architecture enables scalable multipro cessing systems with low communications overhead functional block diagram l1 3 8 l2 8 3 l3 3 8 input fifo output buffer output fifo host interface multiprocessor interface cluster bus arbiter data 64 link ports jtag port sdram controller l0 external port 3 8 addr 32 cntrl 6 m0 data m1 addr m1 data m2 addr m2 data memory m2 64kx32 ad memory m1 64kx32 ad memory m0 64kx32 ad integer kalu integer jalu 32 data address generation iab pc btb irq addr fetch program sequencer y register file 32x32 multiplier alu shifter dab 128 128 x register file 32x32 multiplier alu shifter dab 128 128 i/o address internal memory computational blocks i/o processor link port controller control/ status/ buffers dma controller control/ status/ tcbs 256 32 256 dma data link data dma address 32 128 32 128 32 128 32 32 32x32 32x32 m0 addr one technology way, p.o.box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 www.analog.com fax:781/326-8703 ? analog devices, inc., 2002
adsp-ts101s ?2? rev. 0 table of contents general description . . . . . . . . . . . . . . . . . . . . 2 dual compute blocks . . . . . . . . . . . . . . . . . . . . . . . . 3 data alignment buffer (dab) . . . . . . . . . . . . . . . . . . 4 dual integer alus (ialus) . . . . . . . . . . . . . . . . . . . 4 program sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . 4 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . 4 flexible instruction set . . . . . . . . . . . . . . . . . . . . . 4 on-chip sram memory . . . . . . . . . . . . . . . . . . . . . 5 external port (off-chip memory/peripherals interface) . . . . . . 5 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 multiprocessor interface . . . . . . . . . . . . . . . . . . . . . 5 sdram controller . . . . . . . . . . . . . . . . . . . . . . . . 6 eprom interface . . . . . . . . . . . . . . . . . . . . . . . . . 6 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 link ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 timer and general-purpose i/o . . . . . . . . . . . . . . . . 8 reset and booting . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 low power operation . . . . . . . . . . . . . . . . . . . . . . . . 9 clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 filtering reference voltage and clocks . . . . . . . . . . . 9 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9 designing an emulator-compatible dsp board (target) . . . . . . . . . . . . . . . . . . . . . . . 10 additional information . . . . . . . . . . . . . . . . . . . . . . 11 pin function descriptions . . . . . . . . . . . . . . . . . . . . . 11 strap pin function descriptions . . . . . . . . . . . . . . . . . 19 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 20 absolute maximum ratings . . . . . . . . . . 21 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 21 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 22 general ac timing . . . . . . . . . . . . . . . . . . . . . . . 22 link ports data transfer and token switch timing . . . . . . . . . . . . . . . 25 output drive currents . . . . . . . . . . . . . . . . . . . . . . 28 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 28 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 output disable time . . . . . . . . . . . . . . . . . . . . . . 29 output enable time . . . . . . . . . . . . . . . . . . . . . . 29 capacitive loading . . . . . . . . . . . . . . . . . . . . . . . 30 environmental conditions . . . . . . . . . . . . . . . . . . . . 32 thermal characteristics . . . . . . . . . . . . . . . . . . . . 32 484-ball pbga pin conf igurations . . . . . . . . . . . . . . . 33 625-ball pbga pin conf igurations . . . . . . . . . . . . . . . 36 outline dimensions . . . . . . . . . . . . . . . . . . . . 39 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . 40 general description the adsp-ts101s tigersharc dsp is an ultra high perfor- mance, static superscalar proce ssor optimized for large signal processing tasks and communications infrastructure. the dsp combines very wide memory widths with dual computation blocks?supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing?to set a new standard of performance for digital signal processors. the tigersharc dsp?s static superscalar architecture lets the processor execute up to four instructions each cy cle, performing twenty-four 16-bit fixed-point operations or six floating-point operations. three independent 128-bit wide internal data buses, each connecting to one of the three 2m bit memory banks, enable quad word data, instruction, and i/o accesses and provide 12g bytes per second of internal memory bandwidth. operating at 250 mhz, the adsp-ts101s dsp?s core has a 4.0 ns instruc- tion cycle time. using its single-instruction, multiple-data (simd) features, the adsp-ts101s can perform 2 billion 40-bit macs or 500 million 80-bit macs per second. table 1 and table 2 show the dsp?s performance benchmarks. the adsp-ts101s is code compatible with the other tiger- sharc processors. table 1. general-purpose algorithm benchmarks at 250 mhz benchmark speed clock cycles 32-bit algorithm, 500 million macs/s peak performance 1024 point complex fft (radix 2) 39.34 s 9,835 50-tap fir on 1024 input 110 s 27,500 single fir mac 2.2 ns 0.55 16-bit algorithm, 2 billion macs/s peak performance 256 point complex fft (radix 2) 4.4 s 1,100 50-tap fir on 1024 input 28.8 s 7,200 single fir mac 0.56 ns 0.14 single complex fir mac 2.28 ns 0.57 i/o dma transfer rate external port 800m bytes/s n/a link ports (each) 250m bytes/s n/a table 2. 3g wireless algorithm benchmarks benchmark execution (mips) 1 1 the execution speed is in instruction cycles per second. turbo decode 384 kbps data channel 51 mips viterbi decode 12.2 kbps amr 2 voice channel 2 adaptive multi rate (amr) 0.86 mips complex correlation 3.84 mcps 3 with a spreading factor of 256 3 megachips per second (mcps) 0.27 mips
?3? rev. 0 adsp-ts101s the functional block diagram on page 1 shows the adsp- ts101s dsp?s architectural blocks. these blocks include: ? dual compute blocks, each co nsisting of an alu, multi- plier, 64-bit shifter, and 32-word register file and associated data alignm ent buffers (dabs) ? dual integer alus (ialus), each with its own 31-word register file for data addressing ? a program sequencer with in struction alignment buffer (iab), branch target buffer (btb), and interrupt controller ? three 128-bit internal data bu ses, each connecting to one of three 2m bit memory banks ? on-chip sram (6m bit) ? an external port that provid es the interface to host pro- cessors, multiprocessing spa ce (dsps), off-chip memory mapped peripherals, and external sram and sdram ? a 14-channel dma controller ? four link ports ? two 32-bit interval timers and timer expired pin ? a 1149.1 ieee compliant jtag test access port for on-chip emulation figure 1 shows a typical single proc essor system with external sdram. figure 3 on page 7 shows a typical multiprocessor system. the tigersharc dsp uses a stat ic superscalar? architecture. this architecture is superscalar in that the adsp-ts101s dsp?s core can execute simultaneously from one to four 32-bit instruc- tions encoded in a very large instruction word (vliw) instruction line using the dsp?s dual compute blocks. because the dsp does not perform instruction reordering at runtime? the programmer selects which oper ations will execute in parallel prior to runtime?the order of instructions is static. with few exceptions, an instruction line, whether it contains one, two, three, or four 32-bit instructions, executes with a throughput of one cycle in an eight- deep processor pipeline. for optimal dsp program execution, programmers must follow the dsp?s set of instruction parallelism rules when encoding an instruction line. in general, the selection of instructions that the dsp can execute in parallel each cycle depends on the instruction line resources each instruction requires and on the source and destination registers used in the instructions. the programmer has direct control of three co re components?the ialus, the compute blocks, and the program sequencer. the adsp-ts101s, in most cases, has a two-cycle arithmetic execution pipeline that is fully interlocked, so whenever a com- putation result is unavailable fo r another operation dependent on it, the dsp automatically inserts one or more stall cycles as needed. efficient programming with dependency-free instruc- tions can eliminate most computational and memory transfer data dependencies. in addition, the adsp-ts101s supports simd operations two ways?simd compute blocks and simd computations.the programmer can direct both comp ute blocks to operate on the same data (broadcast distribution) or on different data (merged distribution). in addition, each compute block can execute four 16-bit or eight 8-bit simd computations in parallel. dual compute blocks the adsp-ts101s has compute blocks that can execute com- putations either independently or together as a simd engine. the dsp can issue up to two compute instructions per compute block each cycle, instructing the alu, multiplier, or shifter to perform independent, simultaneous operations. the compute blocks are referred to as x and y in assembly syntax, and each block contains three computational units?an alu, a multiplier, a 64-bit shifter?and a 32-word register file. ? register file?each compute block has a multiported 32-word, fully orthogonal regist er file used for transfer- ring data between the computation units and data buses and for storing intermediate results. instructions can access the registers in the regi ster file individually (word aligned), or in sets of two (dual aligned) or four (quad aligned). ? alu?the alu performs a standard set of arithmetic operations in both fixed- and floating-point formats. it also performs logic operations. ? multiplier?the multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and accumulate. figure 1. single processor system with external sdram controlimp2?0 dmar3C0 dma device (optional) data flag3?0 id2?0 flyby ioen ras cas ldqm hdqm sdwe sdcke sda10 irq3C0 lclk_p sclk_p lxclkin lxdat7?0 lxclkout lxdir lclkrat2?0 sclkfreq tmr0e bm s/lclk_n v ref mssd buslock sdram memory (optional) cs ras cas dqm we cke a10 addr data clk reset jtag adsp-ts101s bms clock link devices (4 max) (optional) boot eprom (optional) addr memory (optional) oe data addr data host processor interface (optional) ack br7C0 cpa hbg hbr ms1C0 data63?0 data addr cs ack we addr31?0 d a t a c o n t r o l a d d r e s s brst reference rd wrh/wrl msh dpa boff ds2?0 cs static superscalar is a trademark of analog devices, inc.
adsp-ts101s ?4? rev. 0 ? shifter?the 64-bit shifter performs logical and arith- metic shifts, bit and bit stream manipulation, and field deposit and extraction operations. ? accelerator?128-bit unit fo r trellis decoding (for example, viterbi and turbo decoders ) and complex cor- relations for communication applications. using these features, the compute blocks can: ? provide 8 macs per cycle peak and 7.1 macs per cycle sustained 16-bit performance and provide 2 macs per cycle peak and 1.8 macs per cycle sustained 32-bit per- formance (based on fir) ? execute six single precision floating-point or execute twenty-four 16-bit fixed-point operations per cycle, providing 1500 mflops or 6.0 gops performance ? perform two complex 16-bit macs per cycle ? execute eight trellis butterflies in one cycle data alignment buffer (dab) the dab is a two quad word fifo that enables loading of quad word data from non-aligned addresses. normally, load instruc- tions must be aligned to their da ta size so that quad words are loaded from a quad aligned address. using the dab significantly improves the efficiency of some applications, such as fir filters. dual integer alus (ialus) the adsp-ts101s has two ialus that provide powerful address generation capabilities and perform many general- purpose integer operations. each of the ialus: ? provides memory addresses for data and update pointers ? supports circular buffering and bit-reverse addressing ? performs general-purpose inte ger operations, increasing programming flexibility ? includes a 31-word regist er file for each ialu as address generators, the ialus perform immediate or indirect (pre- and post-modify) addressing. they perform modulus and bit-reverse operations with no constraints placed on memory addresses for the modulus data buffer placement. each ialu can specify either a single , dual , or quad word access from memory. the ialus have hardware support for circular buffers, bit reverse, and zero-overhead looping. circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, and they are commonly used in digital filters and fourier tr ansforms. each ialu provides registers for four circular buffers, so applications can set up a total of eight circular buffers. the ialus handle address pointer wraparound automatically, reducing overhead, increasing perfor- mance, and simplifying implementation. circular buffers can start and end at any memory location. because the ialu?s computational pipeline is one cycle deep, in most cases integer results are available in the next cycle. hardware (register dependency check) causes a stall if a result is unavailable in a given cycle. program sequencer the adsp-ts101s dsp?s program sequencer supports: ? a fully interruptible programming model with flexible programming in assembly and c/c++ languages; handles hardware interrupts with high throughput and no aborted instruction cycles. ? an eight-cycle in struction pipeline?three-cycle fetch pipe and five-cycle execution pipe?with computation results available two cycles after operands are available. ? the supply of instruction fetch memory addresses; the sequencer?s instruction alig nment buffer (iab) caches up to five fetched instructio n lines waiting to execute; the program sequencer extracts an instruction line from the iab and distributes it to th e appropriate core component for execution. ? the management of program structures and determina- tion of program flow according to jump, call, rti, rts instructions, loop structures, conditions, interrupts, and software exceptions. ? branch prediction and a 128- entry branch target buffer (btb) to reduce branch delays for efficient execution of conditional and unconditional branch instructions and zero-overhead looping; correct ly predicted branches that are taken occur with zero-to- two overhead cycles, over- coming the three-to-six stage branch penalty. ? compact code without the requ irement to align code in memory; the iab handles alignment. interrupt controller the dsp supports nested and non-nested interrupts. each interrupt type has a register in the interrupt vector table. also, each has a bit in both the interrupt latch register and the interrupt mask register. all interrupts are fixed as either level sensitive or edge sensitive, except the irq3C0 hardware interrupts, which are programmable. the dsp distinguishes between hardware interrupts and software exceptions, handling them differently. when a software exception occurs, the dsp aborts all other instructions in the instruction pipe. when a hardwa re interrupt occurs, the dsp continues to execute instructions already in the instruction pipe. flexible instruction set the 128-bit instruction line, which can contain up to four 32-bit instructions, accommodates a variety of parallel operations for concise programming. for example, one instruction line can direct the dsp to conditionally execute a multiply, an add, and a subtract in both computation bl ocks while it also branches to another location in the program. some key features of the instruc- tion set include: ? enhanced instructions for communications infrastruc- ture to govern trellis deco ding (for example, viterbi and turbo decoders) and despreading via complex correlations ? algebraic assembly language syntax ? direct support for all dsp, imaging, and video arith- metic types, eliminating hardware modes
?5? rev. 0 adsp-ts101s ? branch prediction encoded in instruct ion, enables zero- overhead loops ? parallelism encoded in instruction line ? conditional execution optional for all instructions ? user-defined partitioni ng between program and data memory on-chip sram memory the adsp-ts101s has 6m bits of on-chip sram memory, divided into three blocks of 2m bits (64k words 32 bits). each block?m0, m1, and m2?can store program, data, or both, so applications can configure memory to suit specific needs. placing program instructions and data in different memory blocks, however, enables the dsp to acce ss data while performing an instruction fetch. the dsp?s internal and external memory ( figure 2 ) is organized into a unified memory map, whic h defines the location (address) of all elements in the system. the memory map is divided into four memory areas?host space, external memory, multiprocessor space, and internal memory? and each memory space, except ho st memory, is subdivided into smaller memory spaces. each internal memory block connects to one of the 128-bit wide internal buses?block m0 to bus md0, block m1 to bus md1, and block m2 to bus md2?enabling the dsp to perform three memory transfers in the same cycle. the dsp?s internal bus architecture provides a total memory bandwidth of 12g bytes per second, enabling the core and i/o to access eight 32-bit data words (256 bits) and four 32-bit instructions each cycle. the dsp?s flexible memory structure enables: ? dsp core and i/o access of different memory blocks in the same cycle ? dsp core access of all three memory blocks in parallel? one instruction and two data accesses ? programmable partitioning of program and data memory ? program access of all memory as 32-, 64-, or 128-bit words?16-bit words with the dab ? complete context switch in less than 20 cycles (80 ns) external port (off-chip memory/peripherals interface) the adsp-ts101s dsp?s external port provides the processor?s interface to off-chip memory and peripherals. the 4g word address space is included in th e dsp?s unified address space. the separate on-chip buses?three 128-bit data buses and three 32-bit address buses?are multiplexed at the external port to create an external system bus wi th a single 64-bit data bus and a single 32-bit address bus. the external port supports data transfer rates of 800m bytes per second over external bus. the external bus can be configured for 32- or 64-bit operation. when the system bus is configured for 64-bit operation, the lower 32 bits of the external data bus connect to even addresses, and the upper 32 bits connect to odd addresses. the external port supports pipelined, slow, and sdram proto- cols. addressing of external memory devices and memory mapped peripherals is facilitated by on-chip decoding of high order address lines to generate memory bank select signals. the adsp-ts101s provides programmable memory, pipeline depth, and idle cycle for synchronous accesses, and external acknowledge controls to support interfacing to pipelined or slow devices, host processors, and other memory-mapped peripherals with variable access, hold, and disable time requirements. host interface the adsp-ts101s provides an easy and configurable interface between its external bus and host processors through the external port. to accommodate a variety of host processors, the host interface supports pipelined or slow protocols for accesses of the host as slave. each protocol has programmable transmission parameters, such as idle cycles, pipe depth, and internal wait cycles. the host interface supports burst transactions initiated by a host processor. after the host issues the starting address of the burst and asserts the brst signal, the dsp increments the address internally while the host continues to assert brst . the host interface provides a deadlock recovery mechanism that enables a host to recover from de adlock situations involving the dsp. the boff signal provides the deadlock recovery mecha- nism. when the host asserts boff , the dsp backs off the current transaction and asserts hbg and relinquishes the external bus. the host can directly read or write the internal memory of the adsp-ts101s, and it can access most of the dsp registers, including dma control (tcb) registers. vector interrupts support efficient execution of host commands. multiprocessor interface the adsp-ts101s offers powerful features tailored to multi- processing dsp systems through th e external port and link ports. this multiprocessing capability provides highest bandwidth for interprocessor communication, including: ? up to eight dsps on a common bus ? on-chip arbitration for glueless multiprocessing ? link ports for point-to-point communication the external port and link ports provide integrated, glueless mul- tiprocessing support. the external port supports a unified address space (see figure 2 ) that enables direct interprocessor accesses of each adsp- ts101s dsp?s internal memory and registers. the dsp?s on-chip distributed bus arbitration logic provides simple, glueless connection for systems containing up to eight adsp-ts101s dsps and a host processor. bus arbitration has a rotating priority. bus lock supports indivisible read-modify-write sequences for semaphores. a bus fairness feature prevents one dsp from holding the external bus too long. the dsp?s four link ports provid e a second path for interproces- sor communications with throug hput of 1g bytes per second. the cluster bus provides 800m bytes per second throughput? with a total of 1.8g bytes per second interprocessor bandwidth.
adsp-ts101s ?6? rev. 0 sdram controller the sdram controller controls the adsp-ts101s dsp?s transfers of data to and from synchronous dram (sdram). the throughput is 32 or 64 bits pe r sclk cycle using the external port and sdram control pins. the sdram interface provides a glueless interface with standard sdrams?16m bit, 64m bit, 128m bit, and 256m bit. the dsp directly supports a maximum of 64m words 32 bit of sdram. the sdram interface is mapped in external memory in the dsp?s unified memory map. eprom interface the adsp-ts101s can be configured to boot from external 8-bit eprom at reset through the external port. an automatic process (which follows reset) loads a program from the eprom into internal memory. this proces s uses 16 wait cycles for each read access. during booting, the bms pin functions as the eprom chip select signal. the eprom boot procedure uses dma channel 0, which packs the bytes into 32-bit instructions. applications can also access the eprom (write flash memories) during normal operation through dma. the eprom or flash memory interface is not mapped in the dsp?s unified memory map. it is a byte address sp ace limited to a maximum of 16m bytes (24 address bits). the eprom or flash memory interface can be used after boot via a dma. dma controller the adsp-ts101s dsp?s on-chip dma controller, with 14 dma channels, provides zero-ove rhead data transfers without processor intervention. the dma controller operates indepen- dently and invisibly to the dsp?s core, enabling dma operations figure 2. memory map re ser ve d re ser ve d re ser ve d reserved internal registers (uregs) internal memory 2 internal memory 1 internal memory 0 0x 003 fffff 0x00300000 0x00280000 0x00200000 0x 001 80 7ff 0x00180000 0x0010ffff 0x00100000 0x0008ffff 0x00080000 0x0000ffff 0x00000000 internal space proces sor i d 7 proces sor i d 6 proces sor i d 5 proces sor i d 4 proces sor i d 3 proces sor i d 2 proces sor i d 1 proces sor i d 0 broadcast host ( msh ) bank 1 ( ms1 ) bank 0 ( ms0 ) sdram ( mssd ) internal me mory 0 x1 00 000 00 0 x0 c00 00 00 0 x0 80 000 00 0 x0 40 000 00 0 x0 3c0 00 00 0 x0 38 000 00 0 x0 34 000 00 0 x0 30 000 00 0 x0 2c0 00 00 0 x0 28 000 00 0 x0 24 000 00 0 x0 20 000 00 0 x0 1c0 00 00 0x003fffff 0 x0 00 000 00 global space 0xffffffff m u l t i p r o c e s s o r m e m o r y s p a c e e x t e r n a l m e m o r y s p a c e each is a copy of internal space re ser ve d
?7? rev. 0 adsp-ts101s to occur while the dsp?s core continues to execute program instructions. the dma contro ller performs dma transfers between: ? internal memory and external memory and memory- mapped peripherals ? inter nal memor y of other dsps on a common bus, a host processor, or link port i/o ? external memory and external peripherals or link port i/o ? external bus master and internal memory or link port i/o the dma controller provides a number of additional features. the dma controller supports flyby transfers. flyby operations only occur through the external port (dma channel 0) and do not involve the dsp?s core. the dma controller acts as a conduit to transfer data from one external device to another through external memory. during a transaction, the dsp: ? relinquishes the external data bus ? outputs addresses, memory selects ( ms1C0 , mssd , ras , cas , and sdwe ) and the flyby , ioen , and rd / wr strobes ? responds to ack dma chaining is also supporte d by the dma controller. dma chaining operations enable applic ations to automatically link one dma transfer sequence to anothe r for continuous transmission. the sequences can occur over different dma channels and have different transmission attributes. figure 3. shared memory multiprocessing system clks/refs addr31?0 data63?0 br1 br7C2,0 addr31?0 data63?0 br0 br7C1 bms control adsp-ts101 #0 control adsp-ts101 #1 adsp-ts101 #7 adsp-ts101 #6 adsp-ts101 #5 adsp-ts101 #4 adsp-ts101 #3 adsp-ts101 #2 reset reset id2?0 clks/refs lclk_p s/lclk_n v ref sclk_p lclkrat2?0 sclkfreq 000 clock reference voltage addr data host processor interface (optional) ack global memory and peripherals (optional) oe addr data cs addr data boot eprom (optional) rd ms1C0 ack id2?0 001 hbg hbr cs we wrh/l c o n t r o l a d d r e s s d a t a c o n t r o l a d d r e s s d a t a sdram memory (optional) mssd flyby ioen ras cas ldqm hdqm sdwe sdcke sda10 cs ras cas dqm we cke a10 addr data clk msh dmar3C0 dpa boff cpa brst link devices (4 max) (optional) lxclkin lxdir lxdat7?0 lxclkout tmr0e bm controlimp2?0 link irq3C0 flag3?0 link reset buslock clock ds2?0
adsp-ts101s ?8? rev. 0 the dma controller also supports two-dimensional transfers. the dma controller can access and transfer two-dimensional memory arrays on any dma transmit or receive channel. these transfers are implemented with index, count, and modify registers for both the x and y dimensions. the dma controller performs th e following dma operations: ? external port block transfers. four dedicated bidirec- tional dma channels transfer blocks of data between the dsp?s internal memory and any external memory or memory-mapped peripheral on the external bus. these transfers support master mode and handshake mode protocols. ? link port transfers. eight dedicated dma channels (four transmit and four receive) tran sfer quad word data only between link ports and between a link port and internal or external memory. these tr ansfers only use handshake mode protocol. dma priority rotates between the four receive channels. ? autodma transfers. two de dicated unidirectional dma channels transfer data received from an external bus master to internal memory or to link port i/o. these transfers only use slave mode protocol, and an external bus master must initiate the transfer. link ports the dsp?s four link ports provide additional 8-bit bidirectional i/o capability. with the ability to operate at a double data rate? latching data on both the rising and falling edges of the clock? running at 125 mhz, each link port can support up to 250m bytes per second, for a combined maximum throughput of 1g bytes per second. the link ports provide an optional communications channel that is useful in multiprocessor systems for implementing point to point interprocessor communications. applications can also use the link ports for booting. each link port has its own doub le-buffered input and output registers. the dsp?s core can write directly to a link port?s transmit register and read from a receive register, or the dma controller can perform dma tr ansfers through eight (four transmit and four receive) dedicated link port dma channels. each link port has three signal s that control its operation. lxclkout and lxclkin implement clock/acknowledge handshaking. lxdir indicates the direction of transfer and is used only when buffering the lxdat signals. an example appli- cation would be using differential low-swing buffers for long twisted-pair wires. lxdat provides the 8-bit data bus input/output. applications can program separa te error detection mechanisms for transmit and receive operations (applications can use the checksum mechanism to implement consecutive link port trans- fers), the size of data packets, and the speed at which bytes are transmitted. under certain conditions, the link port receiver can initiate a token switch to reverse the direction of transfer; the transmitter becomes the receiver and vice versa. timer and general-purpose i/o the adsp-ts101s has a timer pin (tmr0e) that generates output when a programmed timer counter has expired. also, the dsp has four programmable general-purpose i/o pins (flag3?0) that can function as either single bit input or output. as outputs, these pins can signal peripheral devices; as inputs, they can provide the test for conditional branching. reset and booting the adsp-ts101s has three levels of reset: ? power-up reset?after power-up of the system, and strap options are stable, the reset pin must be asserted (low) for a minimum of 2 ms followed by a deasserted (high) pulse of a minimum of 50 sclk cycles and asserted (low) for a minimum of 100 sclk cycles. trst must also be asserted (low) during power-up to ensure proper operation of the device. see figure 4 . ? normal reset?for any resets following the power-up reset sequence, the reset pin must be asserted for at least 100 sclk cycles. ? core reset?when setting th e sqrst bit in sqctl, the core is reset, but not the external port or i/o. after reset, the adsp-ts101s has four boot options for beginning operation: ? boot from eprom. the dsp defaults to eprom booting when the bms pin strap option is set low. see strap pin function descriptions on page 19 . ? boot by an external master (host or another adsp- ts101s). any master on the cluster bus can boot the adsp-ts101s through writes to its internal memory or through auto dma. ? boot by link port. all four r eceive link dma channels are initialized after reset to tr ansfer a 256-word block to internal memory address 0 to 255, and to issue an interrupt at the end of the block (similar to ep dma). the corresponding dma interrupts are set to address zero (0). ? no boot?start running from an external memory. using the ?no boot? option, the adsp-ts101s must start running from an external me mory, caused by asserting one of the irq3C0 interrupt signals. figure 4. power-up reset waveform reset notes: t start_lo = 2ms minimum after power supplies are stable t pulse1_hi =50 t sclk minimum to 100 t sclk maximum t pulse2_lo =100 t sclk minimum t start_lo t pulse1_hi t pulse2_lo
?9? rev. 0 adsp-ts101s the adsp-ts101s core always exits from reset in the idle state and waits for an interrupt. some of the interrupts in the interrupt vector table are initialized and enabled after reset. low power operation the adsp-ts101s can enter a low power sleep mode in which its core does not execute instructions, reducing power consump- tion to a minimum. the adsp-t s101s exits sleep mode when it senses a falling edge on any of its irq3C0 interrupt inputs. the interrupt, if enabled, causes the adsp-ts101s to execute the corresponding interrupt service routine. this feature is useful for systems that require a low power standby mode. clock domains the adsp-ts101s has two clock inputs that drive its two major clock domains: ? sclk (system clock). prov ides clock input for the external bus interface and defines the ac specification reference for the external bus signals. the external bus interface runs at 1 the sclk frequency. a dll locks internal sclk to sclk input. the maximum sclk frequency is the minimum of either 100 mhz or cclk/2, where cclk is the internal dsp clock fre- quency. sclk must be conn ected to the same clock source as lclk. ? lclk (local clock). provides clock input to the internal clock driver, cclk, which is the internal clock for the core, internal buses, memory, and link ports. the instruc- tion execution rate is equa l to cclk. a pll from lclk generates cclk which is phase-locked. the lclkrat pins define the clock multiplication of lclk to cclk (see table 4 on page 12 ). the link port clock is generated from cclk via a software programmable divisor. reset m u s t b e a s s e r t e d u n t i l l c l k i s s t a b l e a n d w i t h i n specification for at least 2 ms. this applies to power-up as well as any dynamic modification of lclk after power- up. dynamic modification ma y include lclk going out of specification as long as reset is asserted. connecting sclk and lclk to the same clock source is a requirement for the device. using an integer clock multipli- cation value provides predictabl e cycle-by-cycle operation, a requirement of fault-tolerant systems and some multi- processing systems. power supplies the adsp-ts101s has separate power supply connections for internal logic (v dd ), analog circuits (v dd_a ), and i/o buffer (v dd_io ) power supply. the internal (v dd ) and analog (v dd_a ) supplies must meet the 1.2 v requirement. the i/o buffer (v dd_io ) supply must meet the 3.3 v requirement. the analog supply (v dd_a ) powers the clock generator plls. to produce a stable clock, systems must provide a clean power supply to power input v dd_a . designs must pay critical attention to bypassing the v dd_a supply. the ideal power-on sequence for the dsp is to provide power- up of all supplies simultaneously. if there is going to be some delay between power-up of the supplies, provide v dd (and v dd_a ) first, then v dd_io . filtering reference voltage and clocks figure 5 shows a possible circuit for filtering v ref , sclk_n, and lclk_n. this circuit provides the reference voltage for the switching voltage, system clock, and local clock references. development tools the adsp-ts101s is supported with a complete set of crosscore? software and hardware development tools, including analog devices emulators and visualdsp++? devel- opment environment. the same emulator hardware that supports other tigersharc dsps also fully emulates the adsp-ts101s. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/lib rary builder), a linker, a loader, a cycle-accurate instruction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathemat- ical functions. a key point for these tools is c/c++ code efficiency. the compiler has been developed for efficient transla- tion of c/c++ code to dsp asse mbly. the dsp has architectural features that improve the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important features. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representation of user data enables the programmer to quickly determine the per- formance of an algorithm. as algorithms grow in complexity, this capability can have increasing significance on the designer?s development schedule, increasing productivity. statistical profiling enables the programmer to nonintrusively poll the processor as it is running the pr ogram. this feature, unique to visualdsp++, enables the software developer to passively gather important code execution metrics without interrupting the realtime characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and efficiently. by using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. figure 5. v ref , sclk_n, and lclk_n filter v dd_io v ss v ref sclk_n lclk_n r1 r2 c1 c2 r1: 2k series resistor r2: 1.67k series resistor c1: 1 f capacitor (smd) c2: 1nf capacitor (hf smd) placed close to dsp?s pins crosscore is a trademark of analog devices, inc. visualdsp++ is a trademark of analog devices, inc.
adsp-ts101s ?10? rev. 0 debugging both c/c++ and as sembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? perform linear or statistical profiling of program execution ? fill, dump, and graphically pl ot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ ide lets programmers define and manage dsp software development. its dialog boxes and property pages let programmers configure and ma nage all of the tigersharc development tools, including the color syntax highlighting in the visualdsp++ editor. this capability permit programmers to: ? control how the development tools process inputs and generate outputs ? maintain a one-to-one corr espondence with the tool?s command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored speci fically to address the memory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unscheduled regions, semaphores, events, and device flags. the vdk also supports priori ty-based, preemptive, coopera- tive, and time-sliced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ devel- opment environment, but can also be used via standard command line tools. when the vdk is used, the development environment assists the develope r with many error-prone tasks and assists in managing system resources, automating the gener- ation of various vdk based objects, and visualizing the system state, when debugging an application that uses the vdk. vcse is analog devices techno logy for creating, using, and reusing software components (independent modules of substan- tial functionality) to quickly and reliably assemble software applications. download components from the web and drop them into the application. pu blish component archives from within visualdsp++. vcse su pports component implementa- tion in c/c++ or assembly language. use the expert linker to visually manipulate the placement of code and data on the embedded system. view memory utilization in a color-coded graphical form, easily move code and data to different areas of the dsp or external memory with the drag of the mouse, examine run time stac k and heap usage. the expert linker is fully compatible with existing linker definition file (ldf), allowing the developer to move between the graphical and textual environments. analog devices dsp emulators use the ieee 1149.1 jtag test access port of the adsp-ts101s processor to monitor and control the target board pro cessor during emulation. the emulator provides full speed em ulation, allowing inspection and modification of memory, registers, and processor stacks. nonin- trusive in-circuit emulation is assu red by the use of the processor?s jtag interface?the emulator does not affect target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the tigersha rc processor family. hardware tools include tigersharc dsp pc plug-in cards. third party software tools include dsp libraries, real time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the dsp must be halted to send data and commands, but once an operation has been completed by the emulator, the ds p system is set running at full speed with no impact on system timing. to use these emulators, the targ et?s design must include the interface between an analog devices jtag dsp and the emulation header on a custom dsp target board. target board header the emulator interface to an analog devices jtag dsp is a 14-pin header, as shown in figure 6 . the customer must supply this header on the target board in order to communicate with the emulator. the interface consists of a standard dual row 0.025" square post header, set on 0.1" 0.1" spacing, with a minimum post length of 0.235". pin 3 is the key position used to prevent the pod from being inserted backwa rds. this pin must be clipped on the target board. also, the clearance (length, width, and height) around the header must be considered. leave a clearance of at least 0.15" and 0.10" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector. as can be seen in figure 6 , there are two sets of signals on the header. there are the standard jtag signals tms, tck, tdi, tdo, trst , and emu used for emulation purposes (via an emulator). there are also secondary jtag signals btms, btck, btdi, and btrst that are optionally used for board- level (boundary scan) testing.
?11? rev. 0 adsp-ts101s when the emulator is not connected to this header, place jumpers across btms, btck, btrst , and btdi as shown in figure 7 . these jumpers hold the jtag signals in the correct state to allow the dsp to run free. remove all the jumpers when connecting the emulator to the jtag header. jtag emulator pod connector figure 8 details the dimensions of the jtag pod connector at the 14-pin target end. figure 9 displays the keep-out area for a target board header. the keep-out area allows the pod connector to properly seat onto the target board header. this board area should contain no components (c hips, resistors, capacitors, and so on). the dimensions are referenced to the center of the 0.25" square post pin. design for emulation circuit information for details on target board design issues including single processor connections, multiproce ssor scan chains, signal buff- ering, signal termination, and emulator pod logic, see the ee-68: analog devices j tag emulation technical reference on the analog devices website ( www.analog.com )?use site search on ?ee-68?. this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a gene ral overview of the adsp-ts101s dsp?s architecture and functionality. for detailed information on the adsp-ts101s dsp?s core architecture and instruction set, see the tigersharc dsp hardware specification and the tigersharc dsp instruction set specification . for detailed infor- mation on the development tools for this processor, see the visualdsp++ user?s guide for tigersharc dsp . pin function descriptions while most of the adsp-ts101s dsp?s input pins are normally synchronous?tied to a specific clock?a few are asynchronous. for these asynchronous signals, an on-chip synchronization circuit prevents metastability problems. the ac specification for asynchronous signals is used on ly when predictable cycle-by- cycle behavior is required. figure 6. jtag target board connector for jtag equipped analog devices dsp (jumpers in place) figure 7. jtag ta rget board connector with no local boundary scan 4 3 top view 9 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd 12 56 78 9 10 11 12 13 14 top view 13 14 11 12 910 9 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd figure 8. jtag pod connector dimensions figure 9. jtag pod connector keep-out area 0.64" 0.88" 0.24" 0.10" 0. 15 "
adsp-ts101s ?12? rev. 0 the output pins can be three-stated during normal operation. the dsp three-states all outputs du ring reset, allowing these pins to get to their internal pull-up or pull-down state. some output pins (control signals) have a pu ll-up or pull-down that maintains a known value during transitions between different drivers. table 3. pin definitions?clocks and reset signal type description lclk_n i local clock reference. connect this pin to v ref as shown in figure 5 . lclk_p i local clock input. dsp clock in put. the instruction cycle rate = n lclk, where n is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6. see clock domains on page 9. lclkrat2?0 1 i (pd 2 ) lclk ratio. the dsp?s core cloc k (instruction cycle rate) = n lclk, where n is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6 as shown in table 4 . these pins must have a constant value while the dsp is powered. sclk_n i system clock referen ce. connect this pin to v ref as shown in figure 5 . sclk_p i system clock input. the dsp?s system input clock for cluster bus. this pin must be connected to the same clock source as lclk_p. see clock domains on page 9. sclkfreq 3 i (pu 2 ) sclk frequency. sclkfreq = 1 is requ ired. the sclkfreq pin must have a constant value while the dsp is powered. reset i/a reset. sets the dsp to a known state an d causes program to be in idle state. reset must be asserted at specified time according to the type of reset operation. for details, see reset and booting on page 8 . a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state 1 the internal pull-down may not be sufficient. a stronger pull-down may be necessary. 2 see electrical characteristics on page 20 . 3 the internal pull-up may not be sufficient. a stronger pull-up may be necessary. table 4. lclk ratio lclkrat2?0 ratio 000 (default) 2 001 2.5 010 3 011 3.5 100 4 101 5 110 6 111 reserved
?13? rev. 0 adsp-ts101s table 5. pin definitions?external port bus controls signal type description addr31?0 1 i/o/t address bus. the dsp issu es addresses for accessing memo ry and peripherals on these pins. in a multipro cessor system, the bus master drives addresses for accessing internal memory or i/o processor registers of other adsp-ts101s dsps. the dsp inputs addresses when a host or an other dsp accesses it s internal memory or i/o processor registers. data63?0 1 i/o/t external data bus. the dsp drives and r eceives data and instruct ions on these pins. rd 2 i/o/t (pu 3 ) memory read. rd is asserted whenever the dsp re ads from any slave in the system, excluding sdram. when the dsp is a slave, rd is an input and indicates read transactions that acces s its internal memory or universa l registers. in a multiprocessor system, the bus master drives rd . the rd pin changes concurrently with addr pins. wrl 2 i/o/t (pu 3 ) write low. wrl is asserted in two cases: when the adsp-ts101s writes to an even address word of external memory or to another external bus agent; and when the adsp-ts101s writes to a 32- bit zone (host, memory, or dsp programmed to 32-bit bus). an external master (host or dsp) asserts wrl for writing to a dsp?s low word of internal memory. in a multiproces sor system, the bus master drives wrl . the wrl pin changes concurrently with addr pins. when the dsp is a slave, wrl is an input and indicates write transactions that access its internal memo ry or universal registers. wrh 2 i/o/t (pu 3 ) write high. wrh is asserted when the adsp-ts101s writes a long word (64 bits) or writes to an odd address word of external memory or to another external bus agent on a 64-bit data bus. an external master (host or another dsp) must assert wrh for writing to a dsp?s high word of 64-bit data bus. in a multiprocessing system, the bus master drives wrh . the wrh pin changes concurrently with addr pins. when the dsp is a slave, wrh is an input and indica tes write transactions th at access its internal memory or universal registers. ack i/o/t acknowledge. external slave devices can deassert ack to add wait states to external memory accesses. ack is used by i/o devi ces, memory controller s, and other periph- erals on the data phase. the dsp can deassert ack to add wa it states to read accesses of its internal memory. the adsp-ts101s does not drive ack during slave writes. therefore, an external (approximately 10 k ? ) pull-up is required. bms 2, 4 o/t (pu/pd 3 ) boot memory select. bms is the chip select for boot eprom or flash memory. during reset, the dsp uses bms as a strap pin (eboot) for eprom boot mode. when the dsp is configured to boot from eprom, bms is active during the boot sequence. pull-down enabled during reset (asserted); pull-up enabled after reset (deasserted). in a multiprocessor system, the dsp bus master drives bms . for details see reset and booting on page 8 and the eboot signal description in table 16 on page 19 . a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state
adsp-ts101s ?14? rev. 0 ms1C0 2 o/t (pu 3 ) memory select. ms0 or ms1 is asserted whenever the dsp accesses memory banks 0 or 1, respectively. ms1C0 are decoded memory address pi ns that change concurrently with addr pins. when addr31:26 = 0b000010, ms0 is asserted. when addr31:26 = 0b000011, ms1 is asserted. in multipro cessor systems, the master dsp drives ms1C0 . msh 2 o/t (pu 3 ) memory select host. msh is asserted whenever the dsp accesses the host address space (addr31:28 0b0000). msh is a decoded memory address pin that changes concurrently with addr pins. in a mu ltiprocessor system, the bus master dsp drives msh . brst 2 i/o/t (pu 3 ) burst. the current bus master (dsp or host) asse rts this pin to indicate that it is reading or writing data associated with consecutive addresses. a slave device can ignore addresses after the first one and increment an internal address counter after each transfer. for host-to- dsp burst accesses, the dsp incr ements the address automati- cally while brst is asserted. 1 the address and data buses may float for several cycles during bus mastership transitions between a tigersharc dsp and a host. floating in this case means that these inputs are not driven by any source and that dc-biased terminations are not present. it is not necessary to ad d pull-ups as there are no reliability issues and the worst-case power consumption for thes e floating inputs is negligible. unconnected address pins may r equire pull-ups or pull- downs to avoid erroneous slave accesses, depending on the system. unconnected data pins may be left floating. 2 the internal pull-up may not be sufficient. a stronger pull-up may be necessary. 3 see electrical characteristics on page 20 . 4 the internal pull-down may not be sufficient. a stronger pull-down may be necessary. table 6. pin definitions?external port arbitration signal type description br7C0 i/o multiprocessing bus reques t pins. used by the dsps in a multiprocesso r system to arbitrate for bus mastership. each dsp drives its own brx line (corresponding to the value of its id2?0 inputs) and monitors all others. in systems with fewer than eight dsps, set the unused brx pins high. id2?0 1 i (pd 2 ) multiprocessor id. indicates the dsp?s id. from the id, the dsp determines its order in a multiprocessor system. these pins also indicate to the dsp which bus request ( br0 ? br7 ) to assert when requesting the bus: 000 = br0 , 001 = br1 , 010 = br2 , 011 = br3 , 100 = br4 , 101 = br5 , 110 = br6 , or 111 = br7 . id2?0 must have a constant value during system operatio n and can change during reset only. bm 1 o (pd 2 ) bus master. the current bus master dsp asserts bm . for debugging only. at reset this is a strap pin. for more information, see table 16 on page 19 . boff i back off. a deadlock situat ion can occur when the host and a dsp try to read from each other?s bus at the same time. when deadlock occurs, the host can assert boff to force the dsp to relinquish the bus before completing its outstanding transaction. buslock 3 o/t (pu 2 ) bus lock indication. provides an indication that the cu rrent bus master has locked the bus. hbr i host bus request. a host must assert hbr to request control of the dsp?s external bus. when hbr is asserted in a multiprocessing system, the bus master relinquishes the bus and asserts hbg once the outstanding tr ansaction is finished. a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state table 5. pin definitions?external port bus controls (continued) signal type description a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state
?15? rev. 0 adsp-ts101s hbg 3 i/o/t (pu 2 ) host bus grant. acknowledges hbr and indicates that the ho st can take control of the external bus. when re linquishing the bus, the ma ster dsp three-states the addr31?0, data63?0, msh , mssd , ms1C0 , rd , wrl , wrh , bms , brst , flyby , ioen , ras , cas , sdwe , sda10, sdcke, ldqm and hdqm pins, and the dsp puts the sdram in self -refresh mode. the dsp asserts hbg until the host deasserts hbr . in multiprocessor sy stems, the current bus master dsp drives hbg , and all slave dsps monitor hbg . cpa i/o (o/d) core priority access. asserted while the dsp?s core accesses external memory. this pin enables a slave dsp to interrupt a ma ster dsp?s background dma transfers and gain control of the external bus for core-initiated transactions. cpa is an open drain output, connected to all dsps in the system. the cpa pin has an internal 500 ? pull- up resistor, which is only enabled on the dsp with id2?0 = 0. if not required in the system, leave cpa unconnected (external pull-ups will be required for id1?id7). dpa i/o (o/d) dma priority access. asserted whil e a high priority ds p dma channel accesses external memory. this pin enables a high priority dma channel on a slave dsp to interrupt transfers of a normal priority dma channel on a master dsp and gain control of the external bus fo r dma-initiated transactions. dpa is an open drain output, connected to all dsps in the system. the dpa pin has an internal 500 ? pull-up resistor, which is only enabled on the dsp with id2?0 = 0. if not required in the system, leave dpa unconnected (externa l pull-ups will be required for ids 1 through 7). 1 the internal pull-down may not be sufficient. a stronger pull-down may be necessary. 2 see electrical characteristics on page 20 . 3 the internal pull-up may not be sufficient. a stronger pull-up may be necessary. table 7. pin definitions?ex ternal port dma/flyby signal type description dmar3C0 i/a dma request pins. enable external i/o devices to request dma services from the dsp. in response to dmarx , the dsp performs dma tr ansfers according to the dma channel?s initialization. the dsp ignores dma requests from uninitialized channels. flyby 1 o/t (pu 2 ) flyby mode. when a dsp dma channel is initiated in flyby mode, it generates flyby transactions on the external bus. during flyby transactions, the dsp asserts flyby , which signals the source or destination i/o device to latch the next data or strobe the current data, respectively, and to prepare for the next da ta on the next cycle. ioen 1 o/t (pu 2 ) i/o device output enable. enables the output buffers of an external i/o device for flyby transactions between the device an d external memory. active on flyby transactions. a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd= internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state 1 the internal pull-up may not be sufficient. a stronger pull-up may be necessary. 2 see electrical characteristics on page 20 . table 6. pin definitions?external port arbitration (continued) signal type description a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state
adsp-ts101s ?16? rev. 0 table 8. pin definitions?external port sdram controller signal type description mssd 1 i/o/t (pu 2 ) memory select sdram. mssd is asserted whenever the dsp accesses sdram memory space. mssd is a decoded memory address pin that is asserted whenever the dsp issues an sdram command cycle (access to addr31:26 = 0b000001). in a multiprocessor system, th e master dsp drives mssd . ras 1 i/o/t (pu 2 ) row address select. when sampled low, ras indicates that a row address is valid in a read or write of sdram. in other sdram accesses, ras defines the type of operation to execute accord ing to sdram specification. cas 1 i/o/t (pu 2 ) column address select. when sampled low, cas indicates that a column address is valid in a read or write of sd ram. in other sdram accesses, cas defines the type of operation to execute accord ing to the sdram specification. ldqm 1 o/t (pu 2 ) low word sdram data mask. when ldqm sampled high, the dsp three-states the sdram dq buffers. ldqm is va lid on sdram transactions when cas is asserted and is inactive on read transactions. on write transactions, ldqm is active when accessing an odd addres s word on a 64-bit memory bu s to disable the write of the low word. hdqm 1 o/t (pu 2 ) high word sdram data mask. when hdqm sampled high, the dsp three-states the sdram dq buffers. hdqm is va lid on sdram transactions when cas is asserted and is inactive on read transactio ns. on write transactio ns, hdqm is active when accessing an even addr ess in word accesses or is active when memory is configured for a 32-bit bus to disa ble the write of the high word. sda10 1 o/t (pu 2 ) sdram address bit 10 pin. separate a10 signals enable sdra m refresh operation while the dsp executes no n-sdram transactions. sdcke 1, 3 i/o/t (pu/pd 2 ) sdram clock enable. activates the sdram clock for sdram self-refresh or suspend modes. a slave dsp in a multiproces sor system does not have the pull-up or pull-down. a master dsp (or id=0 in a single processor system) has a 100 k ? pull- up before granting the bus to the host, ex cept when the sdram is put in self-refresh mode. in self-refresh mode, the master has a 100 k ? pull-down before granting the bus to the host. sdwe 1 i/o/t (pu 2 ) sdram write enable. when sampled low while cas is active, sdwe indicates an sdram write access. when sampled high while cas is active, sdwe indicates an sdram read access. in other sdram accesses, sdwe defines the type of operation to execute according to sdram specification. a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state 1 the internal pull-up may not be sufficient. a stronger pull-up may be necessary. 2 see electrical characteristics on page 20 . 3 the internal pull-down may not be sufficient. a stronger pull-down may be necessary. table 9. pin definitions?jtag port signal type description emu o (o/d) emulation. conn ected to the dsp?s jtag emulator target board connector only. tck i test clock (jtag). provides an asynchronous clock for jtag scan. tdi 1 i (pu 2 ) test data input (jtag). a serial data input of the scan path. a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state
?17? rev. 0 adsp-ts101s tdo o/t test data output (jtag). a serial data output of the scan path. tms 1 i (pu 2 ) test mode select (jtag). used to control the test state machine. trst 1 i/a (pu 2 ) test reset (jtag). resets the test state machine. trst must be asserted or pulsed low after power-up for proper device op eration. for more information, see reset and booting on page 8 . 1 the internal pull-up may not be sufficient. a stronger pull-up may be necessary. 2 see electrical characteristics on page 20 . table 10. pin definitions?flags, interrupts, and timer signal type description flag3?0 1 i/o/a (pd 2 ) flag pins. bidirectional input/output pins can be used as program conditions. each pin can be configured individually for input or for output. flag3?0 are inputs after power-up and reset. irq3C0 3 i/a (pu 2 ) interrupt request. when asserted, the ds p generates an interrupt. each of the irq3C0 pins can be independently set for edge triggere d or level sensitive operation. after reset, these pins are disa bled unless the irq3C0 strap option is initialized for booting. tmr0e 1 o (pd 2 ) timer 0 expires. this output pulses for fo ur sclk cycles whenever timer 0 expires. at reset this is a strap pin. for more information, see table 16 on page 19 . a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state 1 the internal pull-down may not be sufficient. a stronger pull-down may be necessary. 2 see electrical characteristics on page 20 . 3 the internal pull-up may not be sufficient. a stronger pull-up may be necessary. table 11. pin definitions?link ports signal type description l0dat7?0 1 i/o link0 data 7?0 l1dat7?0 1 i/o link1 data 7?0 l2dat7?0 1 i/o link2 data 7?0 l3dat7?0 1 i/o link3 data 7?0 l0clkout o link0 clock/acknowledge output l1clkout o link1 clock/acknowledge output l2clkout o link2 clock/acknowledge output l3clkout o link3 clock/acknowledge output l0clkin i/a link0 clock/acknowledge input l1clkin i/a link1 clock/acknowledge input l2clkin i/a link2 clock/acknowledge input l3clkin i/a link3 clock/acknowledge input l0dir o link0 direction. (0 = input, 1 = output) a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state table 9. pin definitions?jtag port (continued) signal type description a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state
adsp-ts101s ?18? rev. 0 l1dir o link1 direction. (0 = input, 1 = output) l2dir 2 o (pd 3 ) link2 direction. (0 = input, 1 = output) at reset this is a strap pin. for more information, see table 16 on page 19 . l3dir o (pd 3 ) link3 direction. (0 = input, 1 = output) 1 the link port data pins, if connected or floated for extended periods (for example, token slave with no token master), do not r equire pull-ups or pull-downs as there are no reliability issues and the worst-case power consumption for these floating inputs is negligible. floating in th is case means that these inputs are not driven by any source and that dc-biased terminations are not present. 2 the internal pull-down may not be sufficient. a stronger pull-down may be necessary. 3 see electrical characteristics on page 20 . table 12. pin definitions?impedance and drive strength control signal type description controlimp2?1 1 controlimp0 2 i (pu 3 ) i (pd 3 ) impedance control. for ad c (address/data/controls) and link (all link port outputs) signals, the controlimp2?0 pins control impedance as shown in table 13 . these pins enable or disable dig_ctrl mode. when dig_ctrl: 0 = disabled (maximum drive strength) 1 = enabled (use ds 2?0 drive strength selection) ds2?0 1 i (pu 3 ) digital drive strength select ion. selected as shown in table 14 . for drive strength calculation, see output drive currents on page 28 . a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state 1 the internal pull-up may not be sufficient. a stronger pull-up may be necessary. 2 the internal pull-down may not be sufficient. a stronger pull-down may be necessary. 3 see electrical characteristics on page 20 . table 11. pin definitions?link ports (continued) signal type description a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state table 13. control impedance selection controlimp2?0 adc dig_ctrl link dig_ctrl 000 0 0 001 0 0 010 0 1 011 reserved reserved 100 1 0 101 reserved reserved 110 (default) 1 1 111 reserved reserved table 14. drive strength selection ds2?0 drive strength 000 strength 0 001 strength 1 010 strength 2 011 strength 3 100 strength 4 101 strength 5 110 strength 6 111 (default) strength 7
?19? rev. 0 adsp-ts101s strap pin function descriptions some pins have alternate functions at reset. strap options set dsp operating modes. during reset, the dsp samples the strap option pins. strap pins have an approximately 100 k ? pull-down for the default value. if a strap pin is not connected to an external pull-up or logic load, the dsp sa mples the default value during reset. if strap pins are connected to logic inputs, a stronger external pull-down may be required to ensure default value depending on leakage and/or low level input current of the logic load. to set a mode other than the default mode, connect the strap pin to a sufficiently stronger external pull-up. table 16 lists and describes each of the dsp?s strap pins. table 15. pin definitions?power, ground, and reference signal type description v dd pv dd pins for internal logic. v dd_a pv dd pins for analog circuits. pay critical attention to bypassing this supply. v dd_io pv dd pins for i/o buffers. v ref i reference voltage defines the trip point for all input buffers, except reset , irq3C0 , dmar3C0 , id2?0, controlimp2?0, tck, tdi, tms, and trst . the value is 1.5 v 100 mv (which is the ttl trip point). v ref can be connected to a power supply or set by a voltage divider circuit. the vo ltage divider should have an hf decoupling capacitor (1 nf hf sm d) connected to v ss . tie the decoupling capacitor between v ref input and v ss , as close to the dsp? s pins as possible. see filtering reference voltage and clocks on page 9. v ss g ground pins. v ss_a g ground pins for analog circuits. a = asynchronous; g = ground; i = input; o = output; o/d = open drain output; p = power supply; pd = internal pull-down approximately 100 k ? ; pu = internal pull-up approximately 100 k ? ; t = three-state table 16. pin definitions?i/o strap pins signal on pin? description eboot bms eprom boot. 0 = boot from eprom immediately after reset (default) 1 = idle after reset and wait for an external device to boot dsp through the external port or a link port irqen bm interrupt enable. 0 = disable and set irq3C0 interrupts to level sensitive after reset (default) 1 = enable and set irq3C0 interrupts to edge sensitive immediately after reset tm1 l2dir test mode 1. 0 = required setting during reset. 1 = reserved. tm2 tmr0e test mode 2. 0 = required setting during reset. 1 = reserved.
adsp-ts101s ?20? rev. 0 specifications recommended operating conditions parameter test conditions min typ max unit v dd internal supply voltage 1.14 1.26 v v dd_a analog supply voltage 1.14 1.26 v v dd_io i/o supply voltage 3.15 3.45 v t case case operating temperature ?40 +85 oc v ih high level input voltage 1 1 applies to input and bidirectional pins. @ v dd , v dd_io = max 2 v dd_io + 0.5 v v il low level input voltage 1 @ v dd , v dd_io = min ?0.5 +0.8 v i dd v dd supply current for typical activity 2 2 for details on typical activity used for these measurements, see ee-169, estimating power for the adsp-ts101s . @ cclk = 250 mhz, v dd =1.25 v, t case = 25oc 1.2 a i dd_io v dd_io supply current for ty pi c a l ac t i vi ty 2 @ sclk = 100 mhz, v dd_io =3.3v, t case =25oc 137 ma v ref voltage reference 1.4 1.6 v specifications subject to change without notice. electrical characteristics parameter test conditions min max unit v oh high level output voltage 1 1 applies to output and bidirectional pins. @v dd_io =min, i oh = ?2 ma 2.4 v v ol low level output voltage 1 @v dd_io =min, i ol =4 ma 0.4 v i ih high level input current 2 2 applies to input pins without internal pull-downs (pd). @v dd_io =max, v in =v dd_io max 10 a i ihp high level input current (pd) 3 3 applies to input pins with internal pull-downs (pd). @v dd_io =max, v in =v dd_io max 17.2 44.5 a i il low level input current 4 4 applies to input pins without internal pull-ups (pu). @v dd_io =max, v in =0v 10 a i ilp low level input current (pu) 5 5 applies to input pins with internal pull-ups (pu). @v dd_io =max, v in =0v ?69 ?23 a i ozh three-state leakage current high 6, 7 6 applies to three-stateable pins without internal pull-downs (pd). 7 applies to open drain (od) pins with 500 ? pull-ups (pu). @v dd_io =max, v in =v dd_io max 10 a i ozhp three-state leakage current high (pd) 8 8 applies to three-stateable pins with internal pull-downs (pd). @v dd_io =max, v in =v dd_io max 17.2 44.5 a i ozl three-state leakage current low 9 9 applies to three-stateable pins without internal pull-ups (pu). @v dd_io =max, v in =0 v 10 a i ozlp three-state leakage current low (pu) 10 10 applies to three-stateable pins with internal pull-ups (pu). @v dd_io =max, v in =0v ?69 ?23 a i ozlo three-state leakage current low (od) 7 @v dd_io =max, v in = 0 v ?9.8 ?4.6 a c in input capacitance 11, 12 11 applies to all signals. 12 guaranteed but not tested. @f in =1mhz, t case =25c, v in =2.5 v 5 pf specifications subject to change without notice.
?21? rev. 0 adsp-ts101s absolute maximum ratings esd sensitivity internal (core) supply voltage (v dd ) 1 . . . ?0.3 v to +1.40 v 1 stresses greater than those listed ab ove may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog (pll) supply voltage (v dd_a ) 1 . . ?0.3 v to +1.40 v external (i/o) supply voltage (v dd_io ) 1 . . . ?0.3 v to +4.6 v input voltage 1 . . . . . . . . . . . . . . . . . ?0.5 v to v dd_io +0.5 v output voltage swing 1 . . . . . . . . . . ?0.5 v to v dd_io +0.5 v storage temperature range 1 . . . . . . . . . . . ?65oc to +150oc caution esd (electrostatic discharge) sensitive devi ce. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-ts101s feat ures proprietary esd protection circuitry, permanent damage may occur on devices su bjected to high energy electrostatic discharges. therefore, proper esd precautio ns are recommended to avoid performance degradation or loss of functionality.
adsp-ts101s ?22? rev. 0 timing specifications with the exception of link port, dmar3C0 , and irq3C0 pins, all ac timing for the adsp-ts101s is relative to a reference clock edge. because input setup/hold, output valid/hold, and output enable/disable times are relative to a clock edge, the timing data for the adsp-ts101s has few calculated (formula-based) values. for information on ac timing, see general ac timing on page 22 . for information on link port transfer timing, see link ports data transfer and token switch timing on page 25 . general ac timing timing is measured on signals wh en they cross the 1.5 v level as described in figure 10 on page 24 . all delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. the ac asynchronous timing data for the irq3C0 and dmar3C0 pins appears in table 17 . the general ac timing data appears in table 18 and table 19 . all ac specifications are measured with the load specified in figure 25 on page 30 , and with the output drive strength set to strength 4. in order to calculate the output valid and hold times for different load conditions and/or output drive strengths, refer to figure 26 on page 30 through figure 33 on page 31 (rise and fall time vs. load capacitance) and figure 34 on page 31 (output valid vs. load capa citance vs. drive strength). table 17. ac asynchronous signal specifications (a ll values in this table are in nanoseconds) name description pulsewidth low (min) pulsewidth high (min) irq3C0 1 interrupt request input t cclk + 3 ns ? dmar3C0 1 dma request output t cclk + 4 ns t cclk + 4 ns tmr0e timer 0 expired output ? 4 t sclk ns flags3?0 1, 2 flag pins input 3 t cclk ns 3 t cclk ns trst jtag test reset input 1 ns ? 1 these input pins do not need to be synchronized to a clock reference. 2 for output specifications, see table 19 . table 18. reference clocks signal type description speed grade (mhz) clock cycle min (ns) clock cycle max (ns) clock high min (ns) clock low min (ns) skew to lclk max (ps) input jitter 1 to l e r a n c e (ps) cclk 2, 3 ? core clock 250 4.0 12.5 ? ? ? ? lclk_p 4, 5, 6 input local clock 250 cr 4.0 cr 12.5 {40% to 60% duty cycle} ? 100 sclk_p 5, 7, 8 input system clock, sclkfreq = 1 all greater of 10 or cclk 2 20 {40% to 60% duty cycle} 50 100 tck 9 input test clock (jtag) all greater of 30 or cclk 4 ? 12.5 12.5 ? ? 1 actual input jitter should be combined with ac specifications for accurate timing analysis. 2 cclk is the internal dsp clock or instruction cycle time. the period of this clock is equal to th e local clock (lclk_p) period divided by the local clock ratio (lclkrat2?0). for information on available internal dsp clock rates, see the ordering guide on page 40 . 3 the period of cclk is t cclk . 4 the core clock ratio (cr) is 2, 2.5, 3, 3.5, 4, 5, or 6 as set by the lclkrat2?0 pins. for more information, see table 4 on page 12 . 5 see clock domains on page 9. 6 the period of lclk is t lclk . 7 for more information, see table 3 on page 12 . 8 the period of sclk is t sclk . 9 the period of tck is t tck .
?23? rev. 0 adsp-ts101s table 19. ac signal specifications?all valu es in this table are in nanoseconds. name description input setup (min) input hold (min) output valid (max) 1 output hold (min) output enable (min) 2 output disable (max) 2 reference clock addr31?0 external address bus 2.2 0.5 4.2 1.0 0.9 2.5 sclk data63?0 external data bus 2.2 0.5 4.2 1.0 0.9 2.5 sclk msh memory select host line ? ? 4.2 1.0 0.9 2.5 sclk mssd memory select sdram line 2.2 0.5 4.2 1.0 0.9 2.5 sclk ms1C0 memory select for static blocks ? ? 4.2 1.0 0.9 2.5 sclk rd memory read 2.2 0.5 4.2 1.0 0.9 2.5 sclk wrl write low word 2.2 0.5 4.2 1.0 0.9 2.5 sclk wrh write high word 2.2 0.5 4.2 1.0 0.9 2.5 sclk ack acknowledge for data 2.2 0.5 4.2 1.0 0.9 2.5 sclk sdcke sdram clock enable 2.2 0.5 4.2 1.0 0.9 2.5 sclk ras row address select 2.2 0.5 4.2 1.0 0.9 2.5 sclk cas column address select 2.2 0.5 4.2 1.0 0.9 2.5 sclk sdwe sdram write enable 2.2 0.5 4.2 1.0 0.9 2.5 sclk ldqm low word sdram data mask ? ? 4.2 1.0 0.9 2.5 sclk hdqm high word sdram data mask ? ? 4.2 1.0 0.9 2.5 sclk sda10 sdram addr10 ? ? 4.2 1.0 0.9 2.5 sclk hbr host bus request 2.20.5????sclk hbg host bus grant 2.2 0.5 4.2 1.0 0.9 2.5 sclk boff back off request 2.20.5????sclk buslock bus lock ? ? 4.2 1.0 0.9 2.5 sclk brst burst pin 2.2 0.5 4.2 1.0 0.9 2.5 sclk br7C0 multiprocessing bus reques t pins 2.2 0.5 4.2 1.0 ? ? sclk flyby flyby pin ? ? 4.2 1.0 0.9 2.5 sclk ioen flyby pin ? ? 4.2 1.0 0.9 2.5 sclk cpa 3, 4 core priority access 2.2 0.5 5.8 ? ? 2.5 sclk dpa 3, 4 dma priority access 2.2 0.5 5.8 ? ? 2.5 sclk bms 5 boot memory select ? ? 4.2 1.0 0.9 2.5 sclk flag3?0 6 flag pins ? ? 4.2 1.0 1.0 4.0 sclk tmr0e 5 timer 0 expired ??4.21.0??sclk reset 4, 7 global reset pin ??????sclk tms 4 test mode select (jtag) 1.51.0????tck tdi 4 test data input (jtag) 1.51.0????tck tdo test data output (jtag) ? ? 6.0 1.0 1.0 5.0 tck_fe 8 trst 4, 7, 9 test reset (jtag) ??????tck bm 5 bus master debug aid only ? ? 4.2 1.0 ? ? sclk emu 10 emulation ??5.5??5.0tck or lclk jtag_sys_in 11 system input 1.511.0????tck jtag_sys_out 12 system output ??16.0???tck_fe 8 id2?0 9 chip id ? must be constant ??????? controlimp2?0 9 static pins ? must be constant ???????
adsp-ts101s ?24? rev. 0 ds2?0 9 static pins ? must be constant ??????? lclkrat2?0 9 static pins ? must be constant ??????? sclkfreq 9 static pins ? must be constant ??????? 1 the output valid (max) value in this column applies for the stand ard 30 pf capacitive load used in testing. to see how output va lid varies with capacitive loading, see figure 34 on page 31 . 2 the external port protocols employ bus idle cycles for bus mastersh ip transitions as well as slav e address boundary crossings t o avoid any potential bus contention. the apparent driver overlap, due to output di sables being larger than output enables, is not actual. 3 cpa and dpa pins are open drains and have 0.5 k ? internal pull-ups. 4 these input pins have schmitt triggers and therefore do not nee d to be synchronized to a clock reference. these synchronous spe cifications only apply for recognition in the current clock reference cycle. 5 this pin is a strap option. during reset, an internal resistor pulls the pin low. 6 for input specifications, see table 17 . 7 for additional requirement details, see reset and booting on page 8 . 8 tck_fe indicates tck falling edge. 9 these pins may change only during reset; recommend connecting it to v dd_io /v ss . 10 reference clock depends on function. 11 system inputs are: irq3C0 , bms , lclkrat2?0, sclkfreq, bm , tmr0e, flag3?0, id2?0, brst , wrh , wrl , rd , mssd , sdcke, sdwe , cas , ras , addr31?0, data63?0, dpa , cpa , hbg , boff , hbr , ack, br7C0 , l0clkin, l0dat7?0, l1cl kin, l1dat7?0, l2clkin, l2dat7?0, l2dir, l3clkin, l3da t7?0, ds2?0, controlimp2?0, reset , dmar3C0 . 12 system outputs are: bms , bm , buslock , tmr0e, flag3?0, flyby , ioen , msh , brst , wrh , wrl , rd , ms1C0 , hdqm, ldqm, mssd , sdcke, sdwe , cas , ras , addr31?0, data63?0, dpa , cpa , hbg , ack, br7C0 , l0clkout, l0dat7?0, l0di r, l1clkout, l1dat7?0, l1dir, l2clkout, l2da t7?0, l2dir, l3clkout , l3dat7?0, l3dir, emu . figure 10. general ac parameters timing table 19. ac signal specifications?all values in this table are in nanoseconds. (continued) name description input setup (min) input hold (min) output valid (max) 1 output hold (min) output enable (min) 2 output disable (max) 2 reference clock reference clock input signal output signal three-state output valid output hold output enable output disable input hold input setup 1.5v 1.5v 1.5v pulsewidth 1.5v asynchonous input or output signal
?25? rev. 0 adsp-ts101s link ports data transfer and token switch timing table 20 , table 21 , table 22 , and table 23 with figure 11 , figure 12 , figure 13 , and figure 14 provide the timing specifi- cations for the link ports data transfer and token switch. table 20. link ports?transmit parameter min max unit timing requirements t conns 1 connectivity pulse setup 2 t cclk + 3.5 ns t conns 2 connectivity pulse setup 8 ns t conniw 3 connectivity pulse input width t l x clk_t x + 1 ns t acks acknowledge setup 0.5 t l x clk_t x ns switching characteristics t l x clk_t x 4 transmit link clock period 0.9 lr t cclk 1.1 lr t cclk ns t l x clkh_t x 1 transmit link clock width high 0.33 t l x clk_t x 0.66 t l x clk_t x ns t l x clkh_t x 2 transmit link clock width high 0.4 t l x clk_t x 0.6 t l x clk_t x ns t l x clkl_t x 1 transmit link clock width low 0.33 t l x clk_t x 0.66 t l x clk_t x ns t l x clkl_t x 2 transmit link clock width low 0.4 t l x clk_t x 0.6 t l x clk_t x ns t dirs lxdir transmit setup 0.5 t l x clk_t x 2 t l x clk_t x ns t dirh lxdir transmit hold 0.5 t l x clk_t x 2 t l x clk_t x ns t dos 1 lxdat7?0 output setup 0.25 t l x clk_t x ? 1 ns t doh 1 lxdat7?0 output hold 0.25 t l x clk_t x ? 1 ns t dos 2 lxdat7?0 output setup 0.17 t l x clk_t x ? 1 ns t doh 2 lxdat7?0 output hold 0.17 t l x clk_t x ? 1 ns t ldoe lxdat7?0 output enable 1 ns t ldod 5 lxdat7?0 output disable 1 ns 1 the formula for this parameter applies when lr is 2. 2 the formula for this parameter applies when lr is 3, 4, or 8. 3 lxclkin shows the connectivity pulse with each of the three possible transitions to ?acknowledge.? after a connectivity pulse l ow minimum, lxclkin may [1] return high and remain high for ?acknowledge,? [2] return high and subsequently go low (meeting tacks) for ?not acknowl edge,? or [3] remain low for ?not acknowledge.? 4 the link clock ratio (lr) is 2, 3, 4, or 8 as set by the spd bits in the lctlx register. 5 this specification applies to the last data byte or the ?dummy? byte that follows the ve rification byte if enabled. for more in formation, see the tigersharc dsp hardware specification . figure 11. link ports?transmit lxclkout lxclkin lxdir lxdat7?0 1 2 3 4 0 5 6 7 8 9 10 11 12 13 14 15 t lxclkl_tx t lxclkh_tx t dirs t lxclk_tx t conns t dos t doh t dos t acks t doh t conniw t dirh t ldod t ldoe
adsp-ts101s ?26? rev. 0 table 21. link ports?receive parameter min max unit timing requirements t l x clk_r x 1 receive link clock period 0.9 lr t cclk 1.1 lr t cclk ns t l x clkh_r x 2 receive link clock width high 0.33 t l x clk_r x 0.66 t l x clk_r x ns t l x clkh_r x 3 receive link clock width high 0.4 t l x clk_r x 0.6 t l x clk_r x ns t l x clkl_r x 2 receive link clock width low 0.33 t l x clk_r x 0.66 t l x clk_r x ns t l x clkl_r x 3 receive link clock width low 0.4 t l x clk_r x 0.6 t l x clk_r x ns t dis lxdat7?0 input setup 0.6 ns t dih lxdat7?0 input hold 0.6 ns switching characteristics t connv connectivity pulse valid 0 2.5 t l x clk_r x ns t connow connectivity pulse output width 1.5 t l x clk_r x ns 1 the link clock ratio (lr) is 2, 3, 4, or 8 as set by the spd bits in the lctlx register. 2 the formula for this parameter applies when lr is 2. 3 the formula for this parameter applies when lr is 3, 4, or 8. figure 12. link ports?receive table 22. link ports?token switch, token master parameter min max unit timing requirements t reqi token request input width 5.0 t l x clk_r x ns t tkrq token request from token enable 1 3.0 t l x clk_t x ns switching characteristics t tkeno token switch enable output 8.0 t l x clk_t x ns t reqo token request output width 2 6.0 t l x clk_t x ns 1 for guaranteeing token switch during token enable. 2 lxclkout shows both possible responses to the token request: [1 ] a ?token grant? (lxclkout rem ains high), and [2] a ?token regr et? (lxclkout goes low). figure 13. link ports?tok en switch, token master lxclkin lxclkout lxdat7?0 lxdir 1 2 3 4 5 6 7 8 0 9 10 11 12 13 14 15 t lxclk_rx t connv t lxclkh_rx t lxclkl_rx t connow t dis t dih t dis t dih lxclkin lxclkout 14 15 t tkeno t reqo t tkrq t reqi
?27? rev. 0 adsp-ts101s table 23. link ports?token switch, token requester parameter min max unit timing requirements t tkeni 1 to k e n s w i t c h e n a b l e i n p u t 8 . 0 t l x clk_r x ns switching characteristics t reqo token request output width 2 6.0 t l x clk_r x ns 1 required whenever there is a break in transmission. 2 lxclkout shows both possible responses to the token request: [1 ] a ?token grant? (lxclkout rem ains high), and [2] a ?token regr et? (lxclkout goes low). figure 14. link ports?token switch, token requester lxclkin for token regret lxclkout for token grant 0 1 2 3 lxclkin for token grant 14 12 13 15 lxclkout for token regret 14 12 13 15 t tkeni t tkrq t reqo t reqo t tkeni t tkrq t reqo
adsp-ts101s ?28? rev. 0 output drive currents figure 15 through figure 22 show typical i?v characteristics for the output drivers of the adsp-ts101s. the curves in these diagrams represent the current dr ive capability of the output drivers as a function of output voltage over the range of drive strengths. power dissipation total power dissipation has two co mponents, one due to internal circuitry (i dd ) and one due to the switching of external output drivers (i dd_io ). for details on internal and external power calculation issues including: power vector definitions, current usage descriptions, and formulas, see the ee-169: estimating power for the adsp- ts101s on the analog devices website?use site search on ?ee- 169? ( www.analog.com ). this document is updated regularly to keep pace with silicon revisions. figure 15. typical drive currents at strength 0 figure 16. typical drive currents at strength 1 source (v dd_io )voltage?v 03.5 0.5 1.0 1.5 2.0 2.5 3.0 s o u r c e ( v d d _ i o ) c u r r e n t ? m a ?5 0 5 v dd_io = 3.15v, +85c ?10 ?15 ?20 ?25 ?30 10 15 20 25 30 strength 0 v dd_io =3.3v,+25c v dd_io =3.45v,?40c i ol i oh v dd_io =3.15v,+85c v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c source (v dd_io )voltage?v 03.5 0.5 1.0 1.5 2.0 2.5 3.0 s o u r c e ( v d d _ i o ) c u r r e n t ? m a ?10 0 10 v dd_io = 3.15v, +85c ?20 ?30 ?40 ?50 ?70 20 30 40 50 60 strength 1 v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c i ol i oh v dd_io =3.15v,+85c v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c ?60 figure 17. typical drive currents at strength 2 figure 18. typical drive currents at strength 3 figure 19. typical drive currents at strength 4 source (v dd_io )voltage?v 03.5 0.5 1.0 1.5 2.0 2.5 3.0 s o u r c e ( v d d _ i o ) c u r r e n t ? m a ?20 0 20 v dd_io = 3.15v, +85c ?40 ?60 ?80 ?100 40 60 80 strength 2 v dd_io = 3.3v, +25c v dd_io =3.45v,?40c i ol i oh v dd_io =3.15v,+85c v dd_io =3.3v,+25c v dd_io =3.45v,?40c source (v dd_io )voltage?v 03.5 0.5 1.0 1.5 2.0 2.5 3.0 s o u r c e ( v d d _ i o ) c u r r e n t ? m a ?25 0 25 v dd_io = 3.15v, +85c ?50 ?75 ?100 ?125 50 75 100 125 strength 3 v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c i ol i oh v dd_io =3.15v,+85c v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c source (v dd_io )voltage?v 03.5 0.5 1.0 1.5 2.0 2.5 3.0 s o u r c e ( v d d _ i o ) c u r r e n t ? m a ?20 0 20 v dd_io = 3.15v, +85c ?40 ?60 ?80 ?120 ?160 40 60 80 120 140 strength 4 v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c i ol i oh v dd_io =3.15v,+85c v dd_io =3.3v,+25c v dd_io =3.45v,?40c 100 ?100 ?140
?29? rev. 0 adsp-ts101s test conditions the test conditions for timing parameters appearing in table 19 on page 23 include output disable time, output enable time, and capacitive loading. the timing specifications for the dsp apply for the voltage reference levels in figure 23 . output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the following equation: the output disable time t dis is the difference between t measured_dis and t decay as shown in figure 24 . the time t measured_dis is the interval from when the reference signal switches to when the output voltage decays ? v from the measured output high or output low voltage. the t decay value is calculated with test loads c l and i l , and with ? v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the time for the volt age on the bus to ramp by ? v is dependent on the capacitive load, c l , and the drive current, i d . this ramp time can be approximated by the following equation: figure 20. typical drive currents at strength 5 figure 21. typical drive currents at strength 6 figure 22. typical drive currents at strength 7 source (v dd_io )voltage?v 03.5 0.5 1.0 1.5 2.0 2.5 3.0 s o u r c e ( v d d _ i o ) c u r r e n t ? m a ?20 0 20 v dd_io = 3.15v, +85c ?40 ?60 ?80 ?120 ?180 40 60 80 120 160 strength 5 v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c i ol i oh v dd_io =3.15v,+85c v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c 140 100 ?100 ?160 ?140 source (v dd_io )voltage?v 03.5 0.5 1.0 1.5 2.0 2.5 3.0 s o u r c e ( v d d _ i o ) c u r r e n t ? m a ?20 0 20 v dd_io = 3.15v, +85c ?40 ?60 ?80 ?100 ?220 40 60 80 100 180 strength 6 v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c i ol i oh v dd_io =3.15v,+85c v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c 120 140 160 ?120 ?140 ?160 ?180 ?200 source (v dd_io )voltage?v 03.5 0.5 1.0 1.5 2.0 2.5 3.0 s o u r c e ( v d d _ i o ) c u r r e n t ? m a ?20 0 20 v dd_io = 3.15v, +85c ?40 ?60 ?80 ?100 ?220 40 60 80 100 220 strength 7 v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c i ol i oh v dd_io =3.15v,+85c v dd_io =3.3v,+25c v dd_io = 3.45v, ?40c 120 140 160 180 200 ?120 ?140 ?160 ?180 ?200 figure 23. voltage re ference levels for ac measurements (except ou tput enable/disable) figure 24. output enable/disable input or output 1.5v 1.5v reference signal t dis output starts driving v oh (measured) ? v v ol (measured) + v t measured_dis v oh (measured) v ol (measured) 2.0v 1.0v high impedance state. test conditions cause this voltage to be approximately 1.5v. output stops driving t decay t ena t measured_ena t ramp t decay c l v ? i l --------------- = t ramp c l v ? i d --------------- =
adsp-ts101s ?30? rev. 0 the output enable time t ena is the difference between t measured_ena and t ramp as shown in figure 24 . the time t measured_ena is the interval from when the reference signal switches to when the output voltage ramps ? v from the measured three-stated output level. the t ramp value is calculated with test load c l , drive current i d , and with ? v equal to 0.5 v. capacitive loading output valid and hold are based on standard capacitive loads: 30 pf on all pins (see figure 25 ). the delay and hold specifica- tions given should be derated by a drive strength related factor for loads other than the nominal value of 30 pf. figure 26 through figure 33 show how output rise time varies with capac- itance. figure 34 graphically shows how output valid varies with load capacitance. (note that this graph or derating does not apply to output disable delays; see output disable time on page 29 .) the graphs of figure 26 through figure 34 may not be linear outside the ranges shown. figure 25. equivalent device loading for ac measurements (inclu des all fixtures) figure 26. typical output ri se and fall time (10%?90%, v dd_io = 3.3 v) vs. load capacitance at strength 0 1.5v to output pin 30pf 50 0 102030405060708090100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ? n s load capacitance ? pf rise time y = 0.2015x + 3.8869 strength 0 (v dd_io =3.3v) fall time y = 0.174x + 2.6931 figure 27. typical output ri se and fall time (10%?90%, v dd_io = 3.3 v) vs. load capa citance at strength 1 figure 28. typical output ri se and fall time (10%?90%, v dd_io = 3.3 v) vs. load capa citance at strength 2 figure 29. typical output ri se and fall time (10%?90%, v dd_io = 3.3 v) vs. load capa citance at strength 3 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ? n s load capacitance ? pf rise time y = 0.1349x + 1.9955 fall time y = 0.1163x + 1.4058 strength 1 (v dd_io =3.3v) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ? n s load capacitance ? pf rise time y = 0.1304x + 0.8427 fall time y = 0.1144x + 0.7025 strength 2 (v dd_io =3.3v) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ? n s load capacitance ? pf rise time y = 0.1082x + 1.3123 fall time y = 0.0912x + 1.2048 strength 3 (v dd_io =3.3v)
?31? rev. 0 adsp-ts101s figure 30. typical output ri se and fall time (10%?90%, v dd_io = 3.3 v) vs. load capacitance at strength 4 figure 31. typical output ri se and fall time (10%?90%, v dd_io = 3.3 v) vs. load capacitance at strength 5 figure 32. typical output ri se and fall time (10%?90%, v dd_io = 3.3 v) vs. load capacitance at strength 6 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ? n s load capacitance ? pf rise time y = 0.1071x + 0.9877 fall time y = 0.0798x + 1.0743 strength 4 (v dd_io =3.3v) 0 102030405060708090100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ? n s load capacitance ? pf rise time y = 0.1001x + 0.7763 fall time y = 0.0793x + 0.8691 strength 5 (v dd_io =3.3v) 0 102030405060708090100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ? n s load capacitance ? pf rise time y = 0.0946x + 1.2187 fall time y = 0.0906x + 0.4597 strength 6 (v dd_io =3.3v) figure 33. typical output ri se and fall time (10%?90%, v dd_io = 3.3 v) vs. load capa citance at strength 7 figure 34. typical output valid (v dd_io = 3.3 v) vs. load capacitance at max case te mperature and strength 0?7 1 1 the line equations for the output valid versus load capacitance are: strength 0: y = 0.0956x + 3.5662 strength 1: y = 0.0523x + 3.2144 strength 2: y = 0.0433x + 3.1319 strength 3: y = 0.0391x + 2.9675 strength 4: y = 0.0393x + 2.7653 strength 5: y = 0.0373x + 2.6515 strength 6: y = 0.0379x + 2.1206 strength 7: y = 0.0399x + 1.9080 0 102030405060708090100 0 5 10 15 20 25 r i s e a n d f a l l t i m e s ? n s load capacitance ? pf strength 7 (v dd_io =3.3v) rise time y = 0.0907x + 1.0071 fall time y = 0.09x + 0.3134 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 o u t p u t v a l i d ? n s load capacitance ? pf strength 0?7 (v dd_io =3.3v) 0 1 2 3 4 5 6 7
adsp-ts101s ?32? rev. 0 environmental conditions the adsp-ts101s is rated for pe rformance over the extended commercial temperature range, t case = ?40c to +85c. thermal characteristics the adsp-ts101s is packaged in a 19 mm 19 mm and 27 mm 27 mm plastic ball grid array (pbga). the adsp- ts101s is specified for a case temperature (t case ). to ensure that the t case data sheet specification is not exceeded, a heat sink and/or an air flow source may be used. see table 24 and table 25 for thermal data. table 24. thermal characteristics for 19 mm 19 mm package parameter condition typical unit ja 1 1 the determination of ja is system dependent and is based on a number of factors including device power dissipation, package thermal resistance, board thermal characteristics, ambient temperature, and air flow. airflow 2 = 0 m/s 2 per jedec jesd51-2 procedure using a four layer board (compliant with jedec jesd51-9). 16.6 c/w airflow 3 = 1 m/s 3 per semi test method g38-87 using a four layer board (compliant with jedec jesd51-9). 14.0 c/w airflow 3 = 2 m/s 12.9 c/w jc ?6.7c/w jb ?5.8c/w table 25. thermal characteristics for 27 mm 27 mm package parameter condition typical unit ja 1 1 the determination of ja is system dependent and is based on a number of factors including device power dissipation, package thermal resistance, board thermal characteristics, ambient temperature, and air flow. airflow 2 = 0 m/s 2 per jedec jesd51-2 procedure using a four layer board (compliant with jedec jesd51-9). 13.8 c/w airflow 3 = 1 m/s 3 per semi test method g38-87 using a four layer board (compliant with jedec jesd51-9). 11.7 c/w airflow 3 = 2 m/s 10.8 c/w jc ?3.1c/w jb ?5.9c/w
?33? rev. 0 adsp-ts101s 484-ball pbga pin configurations table 26. 484-ball (19 mm 19 mm) pbga pin assignments pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic a1 v ss b1 data21 c1 data23 d1 data24 e1 data25 a2 data14 b2 data18 c2 data17 d2 data19 e2 data22 a3 data11 b3 data12 c3 data15 d3 data16 e3 data20 a4 data8 b4 data13 c4 data9 d4 v dd_io e4 v dd_io a5 data4 b5 data7 c5 data10 d5 v dd e5 v dd a6 data1 b6 data5 c6 data6 d6 v dd e6 v dd a7 l0dir b7 data2 c7 data3 d7 v dd_io e7 v dd_io a8 l0clkin b8 nc c8 data0 d8 v dd_io e8 v dd a9 l0dat6 b9 l0dat7 c9 l0clkout d9 v dd_io e9 v dd a10 l0dat3 b10 l0dat4 c10 l0dat5 d10 v dd_io e10 v dd a11 l0dat1 b11 l0dat0 c11 l0dat2 d11 v dd_io e11 v dd_io a12 v ss b12 v ss c12 lclk_p d12 v dd_io e12 v dd a13 lclk_n b13 v dd_a c13 v ss d13 v dd_io e13 v dd_io a14 v ss_a b14 v ss_a c14 v dd_a d14 v dd_io e14 v dd a15 sclk_n b15 v ss c15 ds0 d15 v dd_io e15 v dd_io a16 sclk_p b16 ds1 c16 ds2 d16 v dd e16 v dd a17 controlimp2 b17 controlimp0 c17 v ref d17 v dd_io e17 v dd_io a18 controlimp1 b18 dmar2 c18 trst d18 v dd e18 v dd_io a19 reset b19 dmar0 c19 dmar3 d19 v dd_io e19 v dd_io a20 dmar1 b20 tms c20 tck d20 tdo e20 bm a21 emu b21 tdi c21 irq3 d21 irq2 e21 bms a22 v ss b22 irq1 c22 irq0 d22 lclkrat1 e22 lclkrat2 f1 data29 g1 l3dat1 h1 l3dat2 j1 l3dat5 k1 l3clkout f2 data30 g2 data28 h2 l3dat0 j2 l3dat3 k2 l3dat7 f3 data26 g3 data27 h3 data31 j3 l3dat4 k3 l3dat6 f4 v dd_io g4 v dd h4 v dd j4 v dd_io k4 v dd_io f5 v dd_io g5 v dd h5 v dd j5 v dd_io k5 v dd_io f6 v ss g6 v ss h6 v ss j6 v ss k6 v ss f7 v ss g7 v ss h7 v ss j7 v ss k7 v ss f8 v ss g8 v ss h8 v ss j8 v ss k8 v ss f9 v ss g9 v ss h9 v ss j9 v ss k9 v ss f10 v ss g10 v ss h10 v ss j10 v ss k10 v ss f11 v ss g11 v ss h11 v ss j11 v ss k11 v ss f12 v ss g12 v ss h12 v ss j12 v ss k12 v ss f13 v ss g13 v ss h13 v ss j13 v ss k13 v ss f14 v ss g14 v ss h14 v ss j14 v ss k14 v ss f15 v ss g15 v ss h15 v ss j15 v ss k15 v ss f16 v ss g16 v ss h16 v ss j16 v ss k16 v ss f17 v dd g17 v ss h17 v ss j17 v ss k17 v ss f18 v dd_io g18 v dd h18 v dd_io j18 v dd k18 v dd f19 v dd_io g19 v dd_io h19 v dd_io j19 v dd_io k19 v dd_io f20 lclkrat0 g20 flag3 h20 flag1 j20 id0 k20 ioen f21 sclkfreq g21 buslock h21 flag2 j21 id2 k21 flyby f22 tmr0e g22 flag0 h22 id1 j22 msh k22 wrl
adsp-ts101s ?34? rev. 0 l1 l3clkin m1 l1dat0 n1 l1dat3 p1 l1dat4 r1 l1dat6 l2 nc m2 l1dat2 n2 l1dat5 p2 l1clkout r2 data32 l3 l3dir m3 l1dat1 n3 l1dat7 p3 l1clkin r3 data33 l4 v dd_io m4 v dd_io n4 v dd_io p4 v dd_io r4 v dd_io l5 v dd m5 v ss n5 v dd_io p5 v dd r5 v dd l6 v ss m6 v ss n6 v ss p6 v ss r6 v ss l7 v ss m7 v ss n7 v ss p7 v ss r7 v ss l8 v ss m8 v ss n8 v ss p8 v ss r8 v ss l9 v ss m9 v ss n9 v ss p9 v ss r9 v ss l10 v ss m10 v ss n10 v ss p10 v ss r10 v ss l11 v ss m11 v ss n11 v ss p11 v ss r11 v ss l12 v ss m12 v ss n12 v ss p12 v ss r12 v ss l13 v ss m13 v ss n13 v ss p13 v ss r13 v ss l14 v ss m14 v ss n14 v ss p14 v ss r14 v ss l15 v ss m15 v ss n15 v ss p15 v ss r15 v ss l16 v ss m16 v ss n16 v ss p16 v ss r16 v ss l17 v ss m17 v ss n17 v ss p17 v ss r17 v ss l18 v dd_io m18 v dd_io n18 v dd p18 v dd_io r18 v dd l19 v dd_io m19 v dd n19 v dd_io p19 v dd_io r19 v dd_io l20 brst m20 hdqm n20 sdwe p20 addr31 r20 addr28 l21 wrh m21 ms0 n21 mssd p21 ras r21 addr29 l22 rd m22 ms1 n22 ldqm p22 sdcke r22 cas t1 l1dir u1 nc v1 data34 w1 data40 y1 data42 t2 data36 u2 data38 v2 data41 w2 data43 y2 data45 t3 data37 u3 data39 v3 data35 w3 data46 y3 l2dat5 t4 v dd_io u4 v dd_io v4 v dd_io w4 v dd_io y4 data48 t5 v dd u5 v dd v5 v dd w5 v dd_io y5 data52 t6 v ss u6 v ss v6 v dd w6 v dd_io y6 data58 t7 v ss u7 v ss v7 v dd_io w7 v dd_io y7 data60 t8 v ss u8 v ss v8 v dd w8 v dd_io y8 data63 t9 v ss u9 v ss v9 v dd w9 v dd_io y9 l2dat4 t10 v ss u10 v ss v10 v dd w10 v dd_io y10 l2clkout t11 v ss u11 v ss v11 v dd w11 v dd_io y11 nc t12 v ss u12 v ss v12 v dd_io w12 v dd_io y12 br4 t13 v ss u13 v ss v13 v dd w13 v dd_io y13 ack t14 v ss u14 v ss v14 v ss w14 v dd_io y14 cpa t15 v ss u15 v ss v15 v dd w15 v dd_io y15 addr0 t16 v ss u16 v ss v16 v dd w16 v dd_io y16 br 7 t17 v ss u17 v ss v17 v dd w17 v dd_io y17 hbg t18 v dd u18 v dd v18 v dd w18 v dd_io y18 addr1 t19 v dd_io u19 v dd_io v19 v dd_io w19 v dd_io y19 addr11 t20 addr23 u20 addr30 v20 addr14 w20 addr12 y20 addr21 t21 addr25 u21 addr22 v21 addr19 w21 addr17 y21 addr18 t22 addr27 u22 addr26 v22 addr24 w22 addr20 y22 addr16 table 26. 484-ball (19 mm 19 mm) pbga pin assignments (continued) pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic
?35? rev. 0 adsp-ts101s aa1 data44 aa12 br2 ab1 v ss ab12 br0 aa2 data50 aa13 br6 ab2 data53 ab13 br1 aa3 data47 aa14 hbr ab3 data55 ab14 br3 aa4 data49 aa15 dpa ab4 data56 ab15 br5 aa5 data51 aa16 addr2 ab5 data59 ab16 boff aa6 data54 aa17 addr5 ab6 data62 ab17 addr3 aa7 data57 aa18 addr8 ab7 l2dat1 ab18 addr4 aa8 data61 aa19 sda10 ab8 l2dat2 ab19 addr6 aa9 l2dat0 aa20 addr10 ab9 l2dat6 ab20 addr7 aa10 l2dat3 aa21 addr13 ab10 l2clkin ab21 addr9 aa11 l2dat7 aa22 addr15 ab11 l2dir ab22 v ss 484-ball pbga pin configurat ions (top view, summary) table 26. 484-ball (19 mm 19 mm) pbga pin assignments (continued) pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic 20 18 16 14 12 10 8 6 24 22 19 17 21 15 13 11 9 57 3 1 r p n m l k j h g f e d c b a y w v u t ab aa top view v dd v dd_io v ss signal v dd_a v ss_a key:
adsp-ts101s ?36? rev. 0 625-ball pbga pin configurations table 27. 625-ball (27 mm 27 mm) pbga pin assignments pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic a1 v ss b1 v ss c1 v ss d1 v ss e1 data23 a2 data17 b2 v ss c2 data20 d2 v ss e2 data22 a3 data14 b3 data16 c3 data21 d3 data19 e3 v ss a4 data11 b4 data13 c4 data18 d4 v dd_io e4 v dd_io a5 data9 b5 data12 c5 data15 d5 v dd_io e5 v dd_io a6 data7 b6 data10 c6 data8 d6 v dd_io e6 v dd a7 data4 b7 data5 c7 data6 d7 v dd_io e7 v dd a8 data1 b8 data2 c8 data3 d8 v dd_io e8 v dd_io a9 l0dir b9 nc c9 data0 d9 v dd_io e9 v dd_io a10 l0dat7 b10 l0clkout c10 l0clkin d10 v dd_io e10 v dd a11 l0dat4 b11 l0dat5 c11 l0dat6 d11 v dd_io e11 v dd a12 l0dat1 b12 l0dat2 c12 l0dat3 d12 v dd_io e12 v dd_io a13 lclk_n b13 v ss c13 l0dat0 d13 v dd_io e13 v dd_io a14 lclk_p b14 v ss c14 v ss_a d14 v dd_io e14 v dd a15 v dd_a b15 v ss_a c15 v dd_a d15 v dd_io e15 v dd a16 sclk_n b16 sclk_p c16 v ss d16 v dd_io e16 v dd_io a17 v ref b17 v ss c17 ds0 d17 v dd_io e17 v dd_io a18 ds1 b18 ds2 c18 controlimp0 d18 v dd_io e18 v dd a19 controlimp2 b19 controlimp1 c19 dmar1 d19 v dd_io e19 v dd a20 reset b20 dmar3 c20 tdi d20 v dd_io e20 v dd_io a21 dmar2 b21 dmar0 c21 irq2 d21 v dd_io e21 v dd_io a22 emu b22 irq3 c22 lclkrat0 d22 v dd_io e22 v dd_io a23 trst b23 tck c23 lclkrat1 d23 bms e23 v ss a24 tms b24 irq1 c24 irq0 d24 v ss e24 sclkfreq a25 v ss b25 tdo c25 v ss d25 v ss e25 lclkrat2 f1 data26 g1 data29 h1 l3dat0 j1 l3dat3 k1 l3dat6 f2 data25 g2 data28 h2 data31 j2 l3dat2 k2 l3dat5 f3 data24 g3 data27 h3 data30 j3 l3dat1 k3 l3dat4 f4 v dd_io g4 v dd_io h4 v dd_io j4 v dd_io k4 v dd_io f5 v dd_io g5 v dd h5 v dd j5 v dd_io k5 v dd_io f6 v dd g6 v dd h6 v dd j6 v dd k6 v dd f7 v dd g7 v ss h7 v ss j7 v ss k7 v ss f8 v dd g8 v ss h8 v ss j8 v ss k8 v ss f9 v dd g9 v ss h9 v ss j9 v ss k9 v ss f10 v dd g10 v ss h10 v ss j10 v ss k10 v ss f11 v dd g11 v ss h11 v ss j11 v ss k11 v ss f12 v dd g12 v ss h12 v ss j12 v ss k12 v ss f13 v dd g13 v ss h13 v ss j13 v ss k13 v ss f14 v dd g14 v ss h14 v ss j14 v ss k14 v ss f15 v dd g15 v ss h15 v ss j15 v ss k15 v ss f16 v dd g16 v ss h16 v ss j16 v ss k16 v ss f17 v dd g17 v ss h17 v ss j17 v ss k17 v ss f18 v dd g18 v ss h18 v ss j18 v ss k18 v ss f19 v dd g19 v ss h19 v ss j19 v ss k19 v ss f20 v dd g20 v dd h20 v dd j20 v dd k20 v dd f21 v dd g21 v dd h21 v dd_io j21 v dd_io k21 v dd f22 v dd_io g22 v dd_io h22 v dd_io j22 v dd_io k22 v dd_io f23 bm g23 flag3 h23 flag0 j23 id0 k23 nc f24 buslock g24 flag2 h24 id2 j24 nc k24 nc f25 tmr0e g25 flag1 h25 id1 j25 nc k25 nc
?37? rev. 0 adsp-ts101s l1 l3clkin m1 l1dat0 n1 l1dat2 p1 l1dat5 r1 l1clkout l2 l3clkout m2 nc n2 nc p2 l1dat4 r2 l1dat7 l3 l3dat7 m3 l3dir n3 l1dat1 p3 l1dat3 r3 l1dat6 l4 v dd_io m4 v dd_io n4 v dd_io p4 v dd_io r4 v dd_io l5 v dd m5 v dd n5 v dd_io p5 v dd_io r5 v dd l6 v dd m6 v dd n6 v dd p6 v dd r6 v dd l7 v ss m7 v ss n7 v ss p7 v ss r7 v ss l8 v ss m8 v ss n8 v ss p8 v ss r8 v ss l9 v ss m9 v ss n9 v ss p9 v ss r9 v ss l10 v ss m10 v ss n10 v ss p10 v ss r10 v ss l11 v ss m11 v ss n11 v ss p11 v ss r11 v ss l12 v ss m12 v ss n12 v ss p12 v ss r12 v ss l13 v ss m13 v ss n13 v ss p13 v ss r13 v ss l14 v ss m14 v ss n14 v ss p14 v ss r14 v ss l15 v ss m15 v ss n15 v ss p15 v ss r15 v ss l16 v ss m16 v ss n16 v ss p16 v ss r16 v ss l17 v ss m17 v ss n17 v ss p17 v ss r17 v ss l18 v ss m18 v ss n18 v ss p18 v ss r18 v ss l19 v ss m19 v ss n19 v ss p19 v ss r19 v ss l20 v dd m20 v dd n20 v dd p20 v dd r20 v dd l21 v dd m21 v dd_io n21 v dd_io p21 v dd r21 v dd l22 v dd_io m22 v dd_io n22 v dd_io p22 v dd_io r22 v dd_io l23 nc m23 ioen n23 wrh p23 ms1 r23 ldqm l24 nc m24 msh n24 wrl p24 ms0 r24 nc l25 flyby m25 brst n25 rd p25 hdqm r25 mssd t1 nc u1 data34 v1 data37 w1 data40 y1 data43 t2 l1dir u2 data33 v2 data36 w2 data39 y2 data42 t3 l1clkin u3 data32 v3 data35 w3 data38 y3 data41 t4 v dd_io u4 v dd_io v4 v dd_io w4 v dd_io y4 v dd_io t5 v dd u5 v dd_io v5 v dd_io w5 v dd y5 v dd t6 v dd u6 v dd v6 v dd w6 v dd y6 v dd t7 v ss u7 v ss v7 v ss w7 v ss y7 v dd t8 v ss u8 v ss v8 v ss w8 v ss y8 v dd t9 v ss u9 v ss v9 v ss w9 v ss y9 v dd t10 v ss u10 v ss v10 v ss w10 v ss y10 v dd t11 v ss u11 v ss v11 v ss w11 v ss y11 v dd t12 v ss u12 v ss v12 v ss w12 v ss y12 v dd t13 v ss u13 v ss v13 v ss w13 v ss y13 v dd t14 v ss u14 v ss v14 v ss w14 v ss y14 v dd t15 v ss u15 v ss v15 v ss w15 v ss y15 v dd t16 v ss u16 v ss v16 v ss w16 v ss y16 v dd t17 v ss u17 v ss v17 v ss w17 v ss y17 v dd t18 v ss u18 v ss v18 v ss w18 v ss y18 v dd t19 v ss u19 v ss v19 v ss w19 v ss y19 v dd t20 v dd u20 v dd v20 v dd w20 v dd y20 v dd t21 v dd_io u21 v dd_io v21 v dd w21 v dd y21 v dd_io t22 v dd_io u22 v dd_io v22 v dd_io w22 v dd_io y22 v dd_io t23 sdcke u23 cas v23 addr31 w23 addr28 y23 addr26 t24 nc u24 nc v24 addr30 w24 nc y24 addr25 t25 sdwe u25 ras v25 addr29 w25 addr27 y25 addr24 table 27. 625-ball (27 mm 27 mm) pbga pin assignments (continued) pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic
adsp-ts101s ?38? rev. 0 aa1 data46 ab1 data49 ac1 v ss ad1 v ss ae1 v ss aa2 data45 ab2 data48 ac2 v ss ad2 v ss ae2 v ss aa3 data44 ab3 data47 ac3 data50 ad3 v ss ae3 v ss a a 4 v dd_io a b 4 v dd_io ac4 data51 ad4 data52 ae4 data53 aa5 v dd_io a b 5 v dd_io ac5 data54 ad5 data55 ae5 data56 a a 6 v dd_io a b 6 v dd_io ac6 data57 ad6 data58 ae6 data59 a a 7 v dd a b 7 v dd_io ac7 data60 ad7 data61 ae7 data62 a a 8 v dd a b 8 v dd_io ac8 data63 ad8 l2dat0 ae8 l2dat1 a a 9 v dd_io a b 9 v dd_io ac9 l2dat2 ad9 l2dat3 ae9 l2dat4 aa10 v dd_io ab10 v dd_io ac10 l2dat5 ad10 l2dat6 ae10 l2dat7 aa11 v dd ab11 v dd_io ac11 l2clkout ad11 l2clkin ae11 l2dir aa12 v dd ab12 v dd_io ac12 nc ad12 br0 ae12 br1 aa13 v dd_io ab13 v dd_io ac13 br2 ad13 br3 ae13 br4 aa14 v dd_io ab14 v dd_io ac14 br5 ad14 br6 ae14 br7 aa15 v dd ab15 v dd_io ac15 ack ad15 hbr ae15 boff aa16 v dd ab16 v dd_io ac16 hbg ad16 cpa ae16 dpa aa17 v dd_io ab17 v dd_io ac17 addr0 ad17 addr1 ae17 addr2 aa18 v dd_io ab18 v dd_io ac18 addr3 ad18 addr4 ae18 addr5 aa19 v dd ab19 v dd_io ac19 addr6 ad19 addr7 ae19 addr8 aa20 v dd ab20 v dd_io ac20 addr9 ad20 sda10 ae20 addr10 aa21 v dd_io ab21 v dd_io ac21 addr11 ad21 addr12 ae21 addr13 aa22 v dd_io ab22 v dd_io ac22 addr14 ad22 addr15 ae22 v ss aa23 addr23 ab23 addr20 ac23 v ss ad23 v ss ae23 v ss aa24 addr22 ab24 addr19 ac24 addr17 ad24 v ss ae24 v ss aa25 addr21 ab25 addr18 ac25 addr16 ad25 v ss ae25 v ss 625-ball pbga pin configurat ions (top view, summary) table 27. 625-ball (27 mm 27 mm) pbga pin assignments (continued) pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic top view 19 17 21 23 25 15 13 11 9 57 3 1 20 18 16 14 12 10 8 6 24 22 24 r p n m l k j h g f e d c b a y w v u t ae ad ac ab aa v dd v dd_io v ss signal v dd_a v ss_a key:
?39? rev. 0 adsp-ts101s outline dimensions the adsp-ts101s is available in a 19 mm 19 mm, 484-ball pbga package with 22 rows of balls (b-484); the dsp also is available in a 27 mm 27 mm, 625-ball pbga package with 25 rows of balls (b-625). 484-ball pbga (b-484) 1 3 5 7 9 11 15 13 17 19 21 2 4 6 8 10 12 14 16 20 18 22 r p n m l k j h g f e d c b a y aa ab w v u t 0.80 bsc sq ball pitch 1.10 bsc 19.10 19.00 sq 18.90 16.80 bsc sq 19.10 19.00 18.90 19.10 19.00 18.90 17.05 16.95 16.85 top view 2.50 max detail a notes: 1. all dimensions are in millimeters. 2. the actual position of the ball grid is within 0.25mm of its ideal position relative to the package edges. 3. the actual position of each ball is within 0.10mm of its ideal position relative to the ball grid. 4. center dimensions are nominal. seating plane 1.30 max 0.20 max detail a 0.55 0.50 0.45 ball diameter 0.65 0.55 0.45 0.40 min 17.05 16.95 16.85 bottom view 1.10 bsc
adsp-ts101s ?40? rev. 0 printed in u.s.a. c03164?0?9/02(0) ordering guide 625-ball pbga (b-625) part number 1, 2, 3, 4 1 s indicates 1.2 and 3.3 v supplies. 2 a indicates ?40c to +85c temperature. 3 b = plastic ball grid array (pbga) package. 4 1-000 indicates b-625 package and 250 mhz speed grade, a nd 2-000 indicates b-484 package and 250 mhz speed grade. temperature range (case) core clock (cclk) rate 5 5 the instruction rate runs at the internal dsp clock (cclk) rate. on-chip sram operating voltage package ADSP-TS101SAB1-000 ?40c to +85c 250 mhz 6m bit 1.2 v dd 3.3 v dd_io (b-625) 6 6 the b-625 package measures 27 mm 27 mm. adsp-ts101sab2-000 ?40c to +85c 250 mhz 6m bit 1.2 v dd 3.3 v dd_io (b-484) 7 7 the b-484 package measures 19 mm 19 mm. 1.00 bsc sq ball pitch 0.70 0.60 0.50 ball diameter 24.20 24.00 23.80 2.50 max detail a notes: 1. all dimensions are in millimeters. 2. the actual position of the ball grid is within 0.25mm of its ideal position relative to the package edges. 3. the actual position of each ball is within 0.10mm of its ideal position relative to the ball grid. 4. center dimensions are nominal. 5. this package complies with the jedec ms-034 specification, but uses tighter tolerances than the maximums allowed in that specification. seating plane 1.25 max 0.20 max detail a 0.65 0.55 0.45 0.40 min 27.20 27.00 sq 26.80 7 9531 11 13 15 17 21 19 23 25 6 8 10 12 14 16 18 20 24 22 42 r p n m l k j h g f e d c b a y w v u t ae ad ac ab aa 24.00 bsc sq 24.20 24.00 23.80 27.20 27.00 26.80 27.20 27.00 26.80 top view bottom view 1.50 bsc sq 1.50 bsc sq

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