View HY57V161610DTC-I_2809826.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hy57v161610d-i 2 banks x 512k x 16 bit synchronous dram this document is a general produc t description and is subject to change without not ice. hynix semiconductor does not assume an y responsibility for use of circuits described. no patent licenses are implied rev. 0.3/mar. 02 1 description the hynix hy57v161610d is a 16,777,216-bi ts cmos synchronous dram, ideally suited for the mobile applications which require low power consumption and industrial te mperature range. hy57v161610d is organized as 2banks of 524,288x16. hy57v161610d is offering fully synchronous operation refere nced to a positive edge clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high band- width. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read late ncy of 1,2 or 3), the numb er of consecutive read or write cycles initiated by a single cont rol command (burst length of 1,2,4, 8 or full page), and the burst count sequence(sequential or interleave). a bu rst of read or write cycles in progre ss can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (this pipeline design is not restricted by a `2n` rule.) features ? single 3.0v to 3.6v power supply note1) ? all device pins are compatible with lvttl interface ? jedec standard 400mil 50pin tsop-ii with 0.8mm of pin pitch ? all inputs and outputs referenced to positive edge of system clock ? data mask function by udqm/ldqm ? internal two banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 and full page for sequence burst - 1, 2, 4 and 8 for interleave burst ? programmable cas latency ; 1, 2, 3 clocks ordering information part no. clock frequency organization interface package hy57v161610dtc-55i 183mhz 2banks x 512kbits x 16 lvttl 400mil 50pin tsop ii hy57v161610dtc-6i 166mhz hy57v161610dtc-7i 143mhz hy57v161610dtc-10i 100mhz
hy57v161610d-i rev. 0.3/mar. 02 2 pin configuration v ss dq15 dq14 vssq dq13 dq12 vddq dq11 dq10 vssq dq9 dq8 vddq nc udqm clk cke nc a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v dd dq0 dq1 v ssq dq2 dq3 v ddq dq4 dq5 v ssq dq6 vddq /w e /cas /ras /cs a11 a10 a0 a1 a2 a3 v dd 50pin tsop ii 400mil x 825mil 0.8mm pin pitch 27 26 dq7 ldqm v ss dq15 dq14 vssq dq13 dq12 vddq dq11 dq10 vssq dq9 dq8 vddq nc udqm clk cke nc a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v dd dq0 dq1 v ssq dq2 dq3 v ddq dq4 dq5 v ssq dq6 vddq /w e /cas /ras /cs a11 a10 a0 a1 a2 a3 v dd 50pin tsop ii 400mil x 825mil 0.8mm pin pitch 27 26 dq7 ldqm pin description pin pin name description clk clock the system clock input. al l other inputs are referenced to the sdram on the rising edge of clk. cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh. cs chip select command input enable or mask except clk, cke and dqm ba bank address select either one of banks during both ras and cas activity. a0 ~ a10 address row address : ra0 ~ ra10, column address : ca0 ~ ca7 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation. refer function truth table for details ldqm, udqm data input/output mask dqm control output buffer in read mode and mask input data in write mode dq0 ~ dq15 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for internal circuit and input buffer v ddq /v ssq data output power/ground power supply for dq nc no connection no connection
hy57v161610d-i rev. 0.3/mar. 02 3 functional block diagram 1mx16 synchronous dram column addr. latch & counter burst length counter refresh interval timer refresh counter dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 address register i/o control test mode mode register self refresh counter column decoder sense amp & i/o gates 512kx16 bank 0 column decoder sense amp & i/o gates 512kx16 bank 1 ras cas cs we udqm ldqm cke precharge overflow column active row active address[0:10] clk ba(a11) state machine row decoder row addr. latch/predecoder auto/self refresh ref. addr.[0:11] data input/output buffers row addr. latch/predecoder
hy57v161610d-i rev. 0.3/mar. 02 4 absolute maximum ratings note : operation at above absolute maximum ra ting can adversely affect device reliability. dc operating condition (ta= -40 c to 85 c ) note : 1.all voltages are referenced to v ss = 0v. 2.v dd (min) is 3.15v when hy57v161610dtc-7i operates at cas latency=2 3.v ih (max) is acceptable 4.6v ac pulse width with 10ns of duration. 4.v il (min) is acceptable -1.5v ac pulse width with 10ns of duration. ac operating condition (ta= - 40 c to 85 c , v dd =3.0v to 3.6v, v ss =0v) note : 1. output load to measure access times is equi valent to two ttl gates and one capacitance(30pf). for details, refer to ac/dc output load circuit. 2. v dd (min) is 3.15v when hy57v161610dtc-7i operates at cas latency=2 and tck2=8.9ns parameter symbol rating unit ambient temperature t a - 40 ~ 85 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature time t solder 260 10 c sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1, 2 input high voltage v ih 2.0 3.0 v dd + 0.3 v 1, 4 input low voltage v il -0.5 0 0.8 v 1, 5 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for access time measurement cl 30 pf 1
hy57v161610d-i rev. 0.3/mar. 02 5 capacitance (ta=25 c , f=1mhz) output load circuit dc characteristics i (ta= - 40 c to 85 c ) note : 1.v dd (min) is 3.15v when hy57v161610dtc-7i operates at cas latency=2 and tck2=8.9ns. 2.v in = 0 to 3.6v, all other pins are not under test = 0v 3.d out is disabled, v out =0 to 3.6v parameter pin symbol min max unit input capacitance clk c i1 2.5 4 pf a0 ~ a10, ba cke, cs , ras , cas , we , udqm, ldqm c i2 2.5 5 pf data input / output capacitance dq0 ~ dq15 c i/o 46.5pf parameter symbol min. max unit note power supply voltage v dd 3.0 3.6 v 1 input leakage current il -1 1 ua 2 output leakage current io -1 1 ua 3 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol -0.4vi ol =+4ma vtt=1.4v rt=250 ? 30pf output dc output load circuit 30pf output ac output load circuit
hy57v161610d-i rev. 0.3/mar. 02 6 dc characteristics ii (ta= -40 c to 85 c , v dd =3.0v to 3.6v, v ss =0v note1,2 ) note : 1.v dd (min) is 3.15v when hy57v161610dtc-7i operates at cas latency=2 and tck2=8.9ns. 2.i dd1 and i dd4 depend on output loading and cycle rates. spec ified values are measured with the output open. parameter symbol test condition speed unit note -55i -6i -7i -10i operating current idd1 burst length=1, one bank active tras tras(min),trp trp(min), io=0ma 130 120 110 110 ma precharge standby current in power down mode idd2p cke vil(max), tck = min. 1 ma idd2ps cke vil(max), tck = 1 precharge standby current in non power down mode idd2n cke vih(min), cs vih(min), tck = min input signals are changed one time during 2clks. all other pins vdd-0.2v or 0.2v 20 ma idd2ns cke vih(min), tck = input signals are stable. 15 active standby current in power down mode idd3p cke vil(max), tck = min 30 ma idd3ps cke vil(max), tck = 30 active standby current in non power down mode idd3n cke vih(min), cs vih(min), tck = min input signals are changed one time during 2clks. all other pins vdd- 0.2v or 0.2v 50 ma idd3ns cke vih(min), tck = input signals are stable 30 burst mode operating current idd4 tck tck(min), tras tras(min), io=0ma all banks active cl=3 130 120 110 90 ma 2 cl=2 110 110 110 - auto refresh current idd5 trrc trrc(min), all banks active 130 110 110 110 ma self refresh current idd6 cke 0.2v 2ma
hy57v161610d-i rev. 0.3/mar. 02 7 ac characteristics (ta= - 40 c to 85 c , v dd =3.0v to 3.6v, v ss =0v note1,2 ) note : 1.v dd (min) is 3.15v when hy57v161610dtc-7i operates at cas latency=2 and tck2=8.9ns. 2.tck2 is 8.9ns only when tac2 is 7.9ns in hy57v161610dtc-6i and hy57v161610dtc-7i. 3.assume tr / tf (input rise and fall time ) is 1ns. parameter symbol -55i -6i -7i -10i unit note min max min max min max min max system clock cycle time cl=3 tck3 5.5 6 - 7 - 10 - ns cl=2 tck2 - 10 - 10 - 12 - 2 clock high pulse width tchw 2 2 - 2.5 - 3 - ns 3 clock low pulse width tclw 2 2 - 2.5 - 3 - ns 3 access time from clock cl=3 tac3 5 - 5.5 - 6 - 7 ns cl=2tac2 -6-6-7 2 data-out hold time toh 2 2 - 2.5 - 2.5 - ns data-input setup time tds 1.5 1.5 - 1.75 -2.5- ns 3 data-input hold time tdh 1 1 - 1 - 1 - ns 3 address setup time tas 1.5 1.5 - 1.75 -2.5- ns 3 address hold time tah 1 1 - 1 - 1 - ns 3 cke setup time tcks 1.5 1.5 - 1.75 -2.5- ns 3 cke hold time tckh 1 1 - 1 - 1 - ns 3 command setup time tcs 1.5 1.5 - 1.75 -2.5- ns 3 command hold time tch 1 1 - 1 - 1 - ns 3 clk to data output in low z- time tolz 2 2-2-2-ns clk to data output in high z- time tohz 25.52627310ns
hy57v161610d-i rev. 0.3/mar. 02 8 ac characteristics (ta= - 40 c to 85 c , v dd =3.0v to 3.6v, v ss =0v note1,2 )) note : 1. v dd (min) is 3.15v when hy57v161610dtc-7i operates at cas latency=2 and tck2=8.9ns. 2. a new command can be given trrc after self refresh exit. paramter symbol -55i -6i -7i -10i unit note min max min max min max min max ras cycle time operation trc 55 60 - 70 - 70 - ns auto refresh trrc 55 60 - 70 - 80 - ns ras to cas delay trcd 16.5 18 - 20 - 20 - ns ras active time tras 38.5 100k 40 100k 45 100k 45 100k ns ras precharge time trp 3 3-3-2-clk ras to ras bank active delay trrd 2 2 - 2 - 2 - clk cas to cas bank active delay tccd 1 1 - 1 - 1 - clk write command to data-in delay twtl 0 0 - 0 - 0 - clk data-in to precharge command tdpl 1 1 - 1 - 1 - clk data-in to active command tdal 4 4 - 4 - 3 - clk dqm to data-in hi-z tdqz 2 2 - 2 - 2 - clk dqm to data mask tdqm 0 0 - 0 - 0 - clk mrs to new command tmrd 2 2 - 2 - 2 - clk precharge to data output hi-z tproz 3 3 - 3 - 3 - clk power down exit time tpde 1 1 - 1 - 1 - clk self refresh exit time tsre 1 1 - 1 - 1 - clk 2 refresh time tref 64 64 - 64 - 64 - ms
hy57v161610d-i rev. 0.3/mar. 02 9 device operating option table hy57v161610dtc-55i hy57v161610dtc-6i hy57v161610dtc-7i hy57v161610dtc-10i cas latency trcd tras trc trp tac toh 183mhz 3clks 3clks 7clks 10clks 3clks 5ns 2ns 166mhz 3clks 3clks 7clks 10clks 3clks 5.5ns 2ns cas latency trcd tras trc trp tac toh 166mhz 3clks 3clks 7clks 10clks 3clks 5.5ns 2ns 143mhz 3clks 3clks 7clks 10clks 3clks 5.5ns 2.5ns cas latency trcd tras trc trp tac toh 143mhz 3clks 3clks 7clks 10clks 3clks 5.5ns 2.5ns 100mhz 2clks 2clks 5clks 7clks 2clks 7ns 2.5ns cas latency trcd tras trc trp tac toh 100mhz 3clks 2clks 5clks 7clks 2clks 7ns 2.5ns 83mhz 2clks 2clks 4clks 6clks 2clks 7ns 2.5ns
hy57v161610d-i rev. 0.3/mar. 02 10 command truth table note : 1. exiting self refresh occurs by asyn chronously bringing cke from low to high. 2. x=do not care, l=low, h=high, ba=bank address, ra= row address, ca=column address, opcode=operand code, nop=no operation. command cken-1 cken cs ras cas we dqm a 0 ~a 9 a10/ ap ba note mode register set h x llllx op code no operation h x hxxx xx lhhh bank active h x l l h h x row address v read h x lhlhx column address l v read with auto precharge h write hxlhllx column address l v write with auto precharge h precharge all bank hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x u/ldqm h x v x auto refresh h h l l l h x x burst-read-single-write h x llllx a9 pin high (other pins op code) self refresh 1 entry h l lllhx x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
hy57v161610d-i rev. 0.3/mar. 02 11 package information 400mil 50pin thin smal l outline package (tc) 1mx16 synchronous dram unit : mm(inch) 10.059(0.3960) 10.262(0.4040) 11.735(0.4620) 11.938(0.4700) 0.150(0.0059) 0.050(0.0020) 21.057(0.8290) 20.879(0.8220) 0.646 ref 1.2(0.0472) 1.0(0.0394) 0.8(0.0315 bsc) 0.45(0.0177) 0.30(0.0118) 0~5deg gage plane 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0118)

▲Up To Search▲

Price & Availability of HY57V161610DTC-I

	To Download HY57V161610DTC-I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .