C performance analysis tools C traffic scripting tools f &:duh'hyhorsphqw6\vwhp C compact pci chassis C powerpc-based host application module C one or more c-5 switching modules C various physical interface modules (oc-3, oc-12, oc-48, gigabit ethernet, ethernet/oc-3 combination, and so on) C support for fabric and other coprocessor modules C complete hardware reference designs another aspect of the development environment is the comprehensive cus- tomer support from c-port, which includes hands-on training and web access for all your support needs at www.cportcorp.com. 8qlyhuvdo1hwzrunlqj$ssolfdwlrqv the c-5 np can support a wide breadth of applications from access to edge to core, such as: ? multiservice access platforms (msaps) ? digital subscriber line access multiplexor (dslam) ? cable and wireless head-end systems ? man cpe and head-end equipment ? ethernet/ip/frame relay/atm interworking ? internet access switch/routers ? load balancing web server switches ? optical edge switch/routers and add/ drop multiplexors ? ip gigabit/terabit routers ? wan customer premises equipment (cpe) the following sections provide examples of three applications using the c-5 np . ([dpsoh 2swlfdo(gjh6zlwfk5rxwhu the new breed of switch-routers designed for edge new world carrier networks often support atm and ip as the core protocols, frame relay as an access protocol, and are also beginning to implement the emerging mpls stan- dard. each of these protocols must be supported across a number of interface types ranging from clear channel t1/t3 links, sonet oc-3/oc-12 links, and 10/ 100 and gigabit ethernet connections. in addition to the basic protocols and inter- face types, these switch-routers need to provide advanced network services such as ip quality of service (qos), virtual private networks (vpns), and security firewalls. this broad combination of protocols, interfaces, and services presents a difficult challenge to network equipment vendors, especially in light of time-to- market constraints. traditional approaches require separate hardware design efforts, each balancing a mix of asics, application specific standard products (assps), and general-purpose cpus for each inter- face type and protocol. a system design delivering the proto- cols and interfaces needed by this switch-router normally requires many individual hardware designs, along with limited reuse of software (protocol and services) across the various interfaces. a multi-year, phased product rollout is the typical result. the c-5 np enables a new approach that delivers this broad solution set within a single hardware architecture. a single c-5 np-based interface card design can be built with a variety of different phy interface types (for example, t1, t3, oc-3, oc-12, 10/100 ethernet, and gigabit ethernet) to create a common platform. software for atm, ip , mpls, and frame relay can be implemented within the c-5 np (running forwarding plane software) along with a host processor, such as the powerpc? (running the control/manage- ment plane software). these protocols can be provided independently per card, switch fabric/ optical network multiple protocols (implemented through software) multiple line interfaces single line card architecture c-5 np oc-48 oc-192 phy phy oc-12 oc-3 ds3 ds1 gbe 10/100 multiple daughter interface cards ip atm (& ima) mpls frame relay vast range of solutions optical edge switch-router line card solution 2yhuylhz the c-5 tm network processor (np), the first member of the c-port tm family of network processors, is specially designed for networking applications. its high-level of programmability and wire- speed performance make it the best foundation for building networking prod- ucts and services. the c-5 np incorporates an unprece- dented combination of functionality, computing power, and data bandwidth in a flexible, patent-pending architecture. this architecture supports complete pro- grammability from layer 2 through layer 7 of the osi model, allowing the c-5 np to be used in a wide range of networking applications. in addition, the c-5 nps simple programming model and advanced development tools enable you to get to market sooner with clearly dif- ferentiated products. cell and packet processing, table lookup processing, and queue management functions are all integrated into the c-5 np architecture. with the addition of physical interfaces, memory (for payload, circuit/routing tables, and payload descriptor queues), and minimal support logic, the c-5 np can be used to implement intelligent, high-performance, mixed media, multiport, multiprotocol switches and routers. stable programming interfaces, a complete development environment, and third-party support through motor- olas smart networks alliance contribute to a fully integrated platform approach that can solve a wide range of communi- cations tasks and simplify the develop- ment of full-featured networking applications. 3urjudppdelolw\dqg3huirupdqfh the c-5 np provides the forwarding plane intelligence for best-in-class networking products. it supports a variety of networking tasks such as traffic classification and policy enforce- ment in addition to switching, routing, and interworking functions. advanced networking services can be developed and deployed efficiently and effectively under software control. each c-5 np provides up to 5gbps of bandwidth and more than 3,000 mips of computing power to satisfy both todays 3urgxfw%ulhi &1hwzrun3urfhvvru f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
network i/o 5gbps host i/o 2gbps internal i/o 60gbps fabric i/o 5gbps cp0 cp1 cp15 xp fp tlu qmu bmu sram or ext. qm sdram 18 integrated processors available for value-added networking intelligence 3 optimized coprocessors offload specialized networking tasks that are common across applications c-5 np high functional integration sram or ext. tle phy phy phy phy c-5 np c-5 np c-5 np phy c-5 np c-5 np fabric system scaling csix standard custom interconnects glueless fabric alliances physical layer (ds1 to oc-48 rates) t/e-carrier, ethernet, pos, atm, sonet, fr, dwdm, fibrechannel, ... 5gbps aggregate bandwidth 10gbps aggregate bandwidth terabits of aggregate bandwidth network intelligence traffic classification policy management vpn and mpls services quality of service switching/routing interworking, ... scalable network intelligence and tomorrows demanding communica- tions requirements. the c-5 nps 5gbps of bandwidth gives you non-blocking throughput and the 3,000 mips of com- puting power allows you to add services throughout the protocol stack all at wire-speed. you can use more than one c-5 np per device to increase both your bandwidth and computing power. in addition, multi- ple c-5 nps can be used in conjunction with a switching fabric to implement large scale switching systems. with two c-5 nps, you can scale your system up to 10gbps aggregate bandwidth. by adding multiple c-5 nps and a fabric interface, you can achieve terabits per second of aggregate band- width. 6lqjoh&kls $ufklwhfwxuh the c-5 nps highly integrated architec- ture employs dedi- cated processors for value-added net- working intelligence and a series of coprocessors that off-load many com- mon networking-specific tasks. this architecture allows the processors and coprocessors to support concurrent pro- cessing, which helps the c-5 np to deliver software flexibility at hardware speeds. the c-5 nps sixteen programmable &kdqqho3urfhvvruv &3v are responsible for receiving, processing, and transmit- ting cells and packets. the c-5 nps five coprocessors operate as shared resources for the cps and each other and perform a range of networking-specific tasks. the coprocessors are: ? ([hfxwlyh3urfhvvru ;3 for managing the c-5 np , and coordinating the c-5 np and external processors ? )deulf3urfhvvru )3 for scaling the c-5 np with industry leading fabrics ? 7deoh/rrnxs8qlw 7/8 for implementing complex table searches and updates ? 4xhxh0dqdjhphqw8qlw 408 for integrating queue control and man- agement ? %xiihu0dqdjhphqw8qlw %08 for providing fast, flexible memory manage- ment three independent data buses provide 60gbps internal communication paths between the processors and coproces- sors, further supporting concurrent processing. 6fdodeoh3huirupdqfhzlwk3dudooho dqg3lsholqhg3urfhvvlqj the channel processors (cps) can be combined in several ways to increase processing power, bandwidth, through- put, or all three. typically one cp is assigned to each port for medium band- width applications (fast ethernet to oc-3). note that a single cp provides full duplex wire-speed processing. to scale serial bandwidth capabilities, the cps can be aggregated into parallel clus- ters for wider data streams while still maintaining the same simple software model. both techniques can be applied simultaneously and are supported by sophisticated hardware mechanisms, minimizing the complexity of software development. single cp application cp parallel processing cp pipelined processing cp0 cp1 cp2 cp0 cp3 cp0 cp1 cpn parallel and pipelined processing 3rzhuixo,qwhooljhqw3urfhvvlqj(qjlqhv each channel processor (cp) contains a risc core plus dual parallel serial data processors (sdps). together these com- ponents act as powerful communica- tions building blocks that can be customized through standard software and that enable more than three billion risc cycles per second to be used for value-added services. cell and packet processing is pipelined using special- purpose memories that loosely couple these processors. specific forwarding functions supporting different wire-speed network interfaces, line speeds, and protocols are imple- mented using the c/c++ programmable risc core. the risc core specifically manages: ? characterization and classification ? policy enforcement ? traffic scheduling the programmable sdps handle com- mon, time-consuming tasks such as: ? programmable field parsing, extrac- tion (including header validation), inser- tion, and deletion ? crc validation/calculation ? framing and encoding/decoding )oh[leoh/rzhu&rvw1hwzrun ,qwhuidfhv the c-5 nps architecture supports a variety of industry- standard serial and parallel proto- cols and individual port data rates from ds1 (1.544mbps) to oc-48. integrated functions including macs and sonet framers speed system development, simplify device design, and lower total system costs. the physical interfaces of the c-5 np are programmed on a per port basis, enabling a single c-5 np to simultaneously support a wide variety of physical interface types. 6lpsoh3urjudpplqj0rgho the c-5 np is programmed using stan- dard c/c++ languages rather than con- figurable state-machines or proprietary languages, thus providing a true and sim- ple programming model. in addition, the c-5 nps standard risc instruction set enhances code portability and enables use of standard development tools. the key to a simple programming model, however, is an open set of standard pro- gramming interfaces. c-ports c-ware applications program- ming interfaces (c-ware apis) simplify communications soft- ware development and efficiently leverage the power of the c-5 np . similar to apis in the computing world, the c-ware apis hide the sophisticated hardware of the c-5 np and abstract the most com- mon network task building blocks, such as physical interface management, data forwarding, table lookups, buffer management, queuing operations, and so on. programming to the c-ware apis ensures software com- patibility and scalability from generation to generation of the c-port family of network processors. &rpsuhkhqvlyh'hyhorsphqw (qylurqphqw the c-port development environment supplies a comprehensive set of tools and support services that enhance vendor productivity in the design, development, debugging, and perfor- mance tuning of c-5 enabled networking products. the development environment consists of: f &:duh6riwzduh7rrovhw C applications library of reference networking software C application programming interfaces (apis) C functional and performance accurate simulator C industry standard gnu-based compiler and debugger control data table lookup extract space merge space serial data processor (receive) serial data processor (transmit) channel processor risc core memory channel processor block diagram multi-channel hdlc controller atm cell delineator sonet framer ppp (hdlc) framer sonet framer 10/100 ethernet mac gigabit ethernet mac virtually any protocol serial data processor programmable line interfaces liu t/e-carrier framers gbe phy 10/100 phy oc-x phy associated phy oc-x phy f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
c-5, c-port, the c-port logo, and c-ware are all trade- marks of c-port corporation; motorola is a regis- tered trademark of motorola, inc.; ibm and powerpc are a trademarks of international business machines corporation and used under license there- from. vxworks is a registered trademark of wind river systems; power x networks is a trademark and terachannel is a registered trademark of power x limited. classipi is a trademark of pmc-sierra. C5NP-PB/d rev 0 october 2001 for more information about the c-ware software toolset, please contact your local motorola sales representative or call (800) 521-6274. you can also visit motorolas smart networks web site at: zzzprwrurodfrpvpduwqhwzrunv or even mixed within a card for per-port service provisioning by the service pro- vider customer. you basically change the 'personality' of the c-5 np by download- ing a new program. in addition, you can connect these line cards through best-in-class switching fabrics from members of motorola's smart networks alliance, such as power x networks? and ibm?. the c-5 np has a glueless interface to both the power x terachannel ? switch fabric and the ibm packet routing switch fabric, in addition to conforming to standard utopia 2 and 3 interfaces. thus, one basic hardware design, matched with many different phy interfaces, yields a vast range of different solutions leveraging a common platform. by using the c-5 np's universality, a multi-year phased product delivery can be radically condensed, offering a massive time-to-market competitive advantage. ([dpsoh +ljk)xqfwlrq(wkhuqhw ,36zlwfk as enterprise networking has consoli- dated on ip , the desire to leverage intelli- gent ethernet switching for advanced functions (such as server load balancing, firewalling, accounting, address transla- tion, and specific qos) has increased. these layer 3 through layer 7 switching capabilities have become critical to a number of enterprise and public net- working applications. while the intellectual property of devices implementing these functions is typically in the system software, the complex packet parsing, classification, and pro- cessing tasks have required system ven- dors to choose between low throughput or complex hardware development using piece-part assps or dedicated asics. as a result, many networking vendors have had difficulty meeting the market demands for performance and adapting to new functionality and standards. the c-5 np enables imple- mentation of these advanced functions in soft- ware and with the necessary perfor- mance (support- ing 10/100 and gigabit ethernet interfaces in addi- tion to various wan interfaces). the c-5 channel processors (cps) han- dle complex packet parsing of any infor- mation anywhere within a packet. the flexibility and pipelined capacity of the c-5 table lookup unit (tlu) enables simultaneous complex searches for implementation of virtually any required packet classification. the resulting classi- fication information can be used for any number of tasks implemented in c and c++ languages on the risc cores in the channel processors, enabling unprece- dented functionality and adaptability for the enterprise network. the powerful c-5 tlu can be off-loaded for even more complex classification tasks (such as extended access control lists and url matching) through a glue- less connection to an external classifica- tion coprocessor, such as the classipi? processor from pmc-sierra, a member of motorola's smart networks alliance. ([dpsoh (gjh$70,qwhuzrunlqj today's public atm networks must deliver frame relay interworking, ip transport, and a range of native atm services with interfaces ranging from sub-t1/e1 through t3/e3, with growth toward oc-3 and higher. connections to the core network are typically oc-3 or oc-12 speeds. in more traditional designs edge switches combine assps such as fram- ers, hdlc controllers, and sar devices, with general-purpose cpus. while the cpu software provides some application flexibility, separate line cards are typically required for each interface type. urls, ... tcp/udp ports ip addresses vlan ids mac addresses per flow accounting, traffic policing, shaping, network address translation, server address proxies, ... 802.1d tables, ip routing tables, flow id tables, custom tables, ... packet classification packet parsing packet processing xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx channel processor table lookup unit 10/100 ethernet, gigabit ethernet, oc-3/oc-12 pos integrated classification enables high-function designs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
these designs face a number of limitations: ? frame processing is limited by the cpu performance. a generous esti- mate of top-end performance for frame relay or ip is up to 350,000 frames per second (though typically far worse), which is approximately one- third of wire-speed performance for one ds3 (assuming 8-byte frame relay frames). ? density is limited by processing perfor- mance, pci bandwidth, and compo- nent board space. a generous best- case design might support up to five ds3s. ? system cost is driven by the assp costs, with complex hdlc controllers and oc-12 sars typically costing hun- dreds of dollars for each part. the c-5 np breaks through these limita- tions by integrating these functions into a single chip. channel processors are dedicated to atm, sar, hdlc multiplex- ing and demultiplexing, frame relay, and ip functions, enabling wire-speed operations. the c-5 np implementation offers clear benefits: ? density of up to 10 ds3s is easily achieved, enabled by the processing power, internal bandwidth, and integra- tion of a single c-5 np . ? wire-speed performance can be achieved even for 10 individual ds3 links (over 7 million frames per sec- ond), delivering over 20 times the per- formance of general-purpose cpu- based designs. ? system costs are dramatically reduced, both through integration of multiple, expensive components and provision of much higher port densities. ? the same hardware and software architecture scales to higher speeds, up to oc-48, enabling extensive lever- age across the product line for improved time-to-market and lower support costs. 6xppdu\ the c-5 np is a revolutionary break- through for networking vendors and their customers. its unique combination of complete programmability and wire- speed performance provides the best foundation for building value-added networking products and services for the 21 st century. memory memory memory t-carrier framers xn t-carrier framers atm port oc-12 hdlc controller hdlc controller aal5 sar aal5 sar system control cpu memory memory atm interworking with costly multi-part design pci bus c-5 np pci bus to host processor t-carrier framers xn t-carrier framers atm port oc-12 hdlc cp hdlc cp tlu/qmu/ bmu 60gbps aal5 sar cps fabric processor frf/atm ip cps executive processor memories atm interworking with the c-5 np &13)hdwxuh+ljkoljkwv )hdwxuh )xqfwlrq c-5 np general concurrent network processing ? 16 channel processors for cell/packet processing ? five coprocessors for networking-specific tasks: - executive processor (supervisory tasks) - fabric processor (high-speed fabric interface management) - table lookup unit (networking lookups) - queue management unit (queue control) - buffer management unit (payload storage) throughput ? 5gbps aggregate internal bandwidth ? three internal buses with 60gbps aggregate bandwidth processing power ? over 3000 mips layout ? single chip system ? ball grid array (bga) package channel processor (cp) physical interfaces ? up to 16 (user configurable) physical protocols supported ? 10mb ethernet (rmii) ? 100mb ethernet (rmii) ? 1gb ethernet (gmii and tbi) ?oc-3c ? oc-12/oc-12c ?oc-48 ? fibrechannel ? t1/e1 (with external framers/multiplexors) ? t3/e3 (with external framers/multiplexors) risc core ? 32-bit c/c++ programmable, standard instruction set programmable serial data processors (sdps) ? two sdps (one receive and one transmit) per cp executive processor (xp) risc core ? c/c++ programmable, standard instruction set external interfaces ? 32-bit, 33/66mhz pci ? serial prom interface ? two-wire serial bus interface (400kbps) fabric processor (fp) interface type ? conforms to utopia (levels 2 and 3) interface standards, and seamless compatibility with power x and ibm fabrics interface bandwidth ? transmit and receive full-duplex at up to 3200mbps each direction table lookup unit (tlu) number of lookups per second ? 133m maximum external memory size ? up to 16mb maximum (8mb x 18) queue management unit (qmu) internal mode ? up to 512 queues ? automated multicast elaboration buffer management unit (bmu) buffer memory width ? 139 bit (128 bits data, 9 bits ecc, 2 bits control) buffer memory size ? up to 128mb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
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