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ics for communications atm layer processor alp pxb 4350 e version 1.1 data sheet 08.2000 ds 1
3;%( 5hylvlrq+lvwru\&xuuhqw9huvlrq previous version: preliminary data sheet 09.98 (ds 2) page (in previous version) page (in current version) subjects (major changes since last revision) the data sheet has been reorganized. i om ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of infineon technologies ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , digitape ? are trademarks of infineon technologies ag. all other brand or product names, hardware or software names are trademarks or registered trademarks of their respective companies or organizations. for questions on technology, delivery and prices please contact the infineon technologies of- fices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com. (glwlrq this edition was realized using the software system framemaker a . 3xeolvkhge\ ,qilqhrq7hfkqrorjlhv$* 6& %dodqvwud?h 0?qfkhq ? infineon technologies ag 2000. all rights reserved. $wwhqwlrqsohdvh as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for ap- plications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the infineon technologies companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. 3dfnlqj please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. &rpsrqhqwvxvhglqolihvxssruwghylfhvruv\vwhpvpxvwehh[suhvvo\dxwkrul]hgiruvxfksxusrvh critical components 1 of infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be ex- pected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or main- tain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered.
3;%( 7deohri&rqwhqwv 3djh data sheet 3 08.2000 2yhuylhz 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 )xqfwlrqdo'hvfulswlrq 2.1 core functions and interfaces of the alp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2 functional description of user data flow in up- and downstream direction . . . . 28 2.3 address reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.1 internal address reduction circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.2 external address reduction circuit (came device) . . . . . . . . . . . . . . . . . . . . . 33 2.3.3 processing of the header structure by the alp . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3.3.1 house keeping (hk) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4 policing in upstream direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.1 the leaky bucket (lb) algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.2 general configuration of the polu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.2.1 operation mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4.2.2 operation mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.4.2.3 operation mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.4.2.4 operation mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.4.3 calculation of polu parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.4.4 example for polu configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.5 traffic measurement unit for up- and downstream direction . . . . . . . . . . . . . . . 46 2.5.1 traffic measurement data transfer via dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.6 utopia functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.7 oam functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.8 programmable cell filter functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.9 configuration of alp via microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5hjlvwhu'hvfulswlrq 3.1 overview of the alp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2 transfer register general mapping to dwords . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.2.1 read/write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.2.1.1 write transfer registers (wdr0l/wdr0h..wdral/wdrah) . . . . . . . . . . . . . 69 3.2.1.2 read transfer registers (rdr0l/rdr0h..rdral/rdrah) . . . . . . . . . . . . . . 70 3.3 mapping of transfer register to internal / external rams . . . . . . . . . . . . . . . . . 71 3.3.1 policing ram (poluram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.3.1.1 policing ram : dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.3.1.2 policing ram : dword1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.3.1.3 policing ram : dword2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.1.4 policing ram : dword3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.1.5 policing ram : dword4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.1.6 policing ram : dword5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.1.7 policing ram : dword6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.1.8 policing ram : dword7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.3.1.9 policing ram : dword8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.3.1.10 policing ram : dword9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.3.1.11 policing ram: dword10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3;%( 7deohri&rqwhqwv 3djh data sheet 4 08.2000 3.3.2 connection ram upstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.3.2.1 connection ram upstream: dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.3.3 connection ram downstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.3.1 connection ram downstream : dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.3.2 connection ram downstream : dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.3.3 connection ram downstream : dword2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.4 traffic measurement ram (port table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.3.4.1 port table upstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.3.4.2 port table downstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.4 cell type filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.4.1 register for programmable cell type filter 1 in upstream . . . . . . . . . . . . . . . . 85 3.4.1.1 byte 1 and 2 of cell type filter 1 : dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.4.1.2 byte 3 and 4 of cell type filter 1 : dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.4.1.3 byte 5 and 6 of cell type filter 1 : dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.4.1.4 byte 7 of cell type filter 1 : dword 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.4.2 register for programmable cell type filter 2 in upstream . . . . . . . . . . . . . . . . 86 3.4.2.1 byte 1 and 2 of cell type filter 2 : dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.4.2.2 byte 3 and 4 of cell type filter 2 : dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.4.2.3 byte 5 and 6 of cell type filter 2 : dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.4.2.4 byte 7 of cell type filter 2 : dword 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.4.3 register for programmable cell type filter 1 in downstream . . . . . . . . . . . . . . 87 3.4.3.1 byte 1 and 2 of cell type filter 1 : dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.4.3.2 byte 3 and 4 of cell type filter 1 : dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.4.3.3 byte 5 and 6 of cell type filter 1 : dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.4.3.4 byte 7 of cell type filter 1 : dword 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.4.4 register for programmable cell type filter 2 in downstream . . . . . . . . . . . . . . 88 3.4.4.1 byte 1 and 2 of cell type filter 2 : dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.4.2 byte 3 and 4 of cell type filter 2 : dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.4.3 byte 5 and 6 of cell type filter 2 : dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.4.4 byte 7 of cell type filter 2 : dword 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.5 port configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.5.1 port configuration uni (uniportl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.5.2 port configuration uni (uniporth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.6 came data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.6.1 camadrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.6.2 camadrh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.7 polu configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.7.1 polu configuration register (p_conrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.7.2 polu configuration register (p_conrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.8 version register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.8.1 verl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.8.2 verh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.9 transmit cell registers 0..26 (txr0..26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.9.1 transmit cell register 0 (txr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.9.2 transmit cell register 1 (txr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.9.3 transmit cell register 2 (txr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.9.4 transmit cell registers 3..26 (txr3..txr26) . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.9.5 configuration of transmit cell buffer (txr_config) . . . . . . . . . . . . . . . . . . . . 97
3;%( 7deohri&rqwhqwv 3djh data sheet 5 08.2000 3.10 receive register/receive cell buffer (rxr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.11 header capture/protocol monitoring register set 0 ... 3 upstream . . . . . . . . . . 99 3.11.1 protocol monitoring buffer 0...3 upstream (prmonr0a_u..3a_u) . . . . . . . . . 99 3.11.2 protocol monitoring buffer 0...3 upstream (prmonr0b_u..3b_u) . . . . . . . . . 99 3.11.3 protocol monitoring buffer 0...3 upstream (prmonr0c_u..3c_u) . . . . . . . . 100 3.12 header capture/protocol monitoring register set downstream . . . . . . . . . . . 100 3.12.1 protocol monitoring buffer 0 downstream (prmonra_d) . . . . . . . . . . . . . . . 100 3.12.2 protocol monitoring buffer downstream (prmonrb_d) . . . . . . . . . . . . . . . . 101 3.12.3 protocol monitoring buffer downstream (prmonrc_d) . . . . . . . . . . . . . . . . 101 3.13 protocol monitoring configuration register (headcapen) . . . . . . . . . . . . . . 101 3.14 configuration of portspecific counters upstream . . . . . . . . . . . . . . . . . . . . . . 102 3.14.1 port specific counter configuration upstream (portconf0_u..7_u) . . . . . 102 3.14.2 enpotic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.15 configuration of portspecific counters downstream . . . . . . . . . . . . . . . . . . . . 104 3.15.1 portconf0_d ... 7_d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.15.2 enpotoc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.16 utopia configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.16.1 utopia configuration (conut1a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.16.2 utopia configuration (conut1b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.16.3 utopia configuration (conut1c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.16.4 utopia configuration (conut2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.16.5 utopia configuration (conut3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.17 utopia downstream queue overflow indication registers . . . . . . . . . . . . . . 109 3.17.1 ut_qov1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.17.2 ut_qov2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.18 configuration of header translation/special enable bits . . . . . . . . . . . . . . . . . 110 3.18.1 adred_vpim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.18.2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.19 command register (cmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.20 status registers for header capture/came . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.20.1 status register for header capture (statr) . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.20.2 status register for came (cstatr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.21 interrupt status registers/interrupt mask registers . . . . . . . . . . . . . . . . . . . . . 115 3.21.1 interrupt status register (isr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.21.2 interrupt status register (isr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3.21.3 interrupt mask register (imr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.21.4 interrupt mask register (imr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.22 came interrupt status register (csir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.23 rwr mask register (rmw_mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.24 cell type recognition configuration registers . . . . . . . . . . . . . . . . . . . . . . . . 123 3.24.1 uct_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.24.2 dct_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 3.25 reset configuration register (rmw_conf) . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.26 address register for cmr commands (adr) . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.27 scan configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.27.1 sc_conr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.27.2 sc_conr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.28 dma configuration/read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3;%( 7deohri&rqwhqwv 3djh data sheet 6 08.2000 3.28.1 dconr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.28.2 dmar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 3.29 test register/special modes (testr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.30 polu status registers (p_statr0..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.30.1 p_statr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.30.2 p_statr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.30.3 p_statr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.31 came valid intermediate lci (camvilci) . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.32 dma range registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.32.1 dma_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.32.2 dma_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.33 bist registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.33.1 bist mode register 1 (bistmode1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.33.2 bist mode register 2 (bistmode2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.33.3 bist active register (bistdone) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.33.4 bist result register (bisterror) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 2shudwlrq 4.1 multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.2 utopia configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.3 ram access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.4 came access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.5 policing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.6 connection setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.7 cell insertion and extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.8 dma configuration and access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 ,qwhuidfh'hvfulswlrq 5.1 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.2 external ram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.3 microprocessor and control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.4 jtag/boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.5 clock and reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.6 came interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 5.6.1 data structure at came data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 5.7 test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 (ohfwulfdo&kdudfwhulvwlfv 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3 dc characteristics for all interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.4 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.5.1 clock and reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.5.2 dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.5.3 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.5.4 sram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
3;%( 7deohri&rqwhqwv 3djh data sheet 7 08.2000 6.5.5 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.5.5.1 microprocessor write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.5.5.2 microprocessor read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.5.6 boundary-scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.5.7 ac characteristics of came interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 3dfndjh2xwolqhv 5hihuhqfhv 8.1 acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3;%( /lvwri)ljxuhv 3djh data sheet 8 08.2000 figure 1: chipset configuration for main atm layer functionality . . . . . . . . . . . . . . . . . . . 11 figure 2: chipset configuration for main atm layer functionality plus full oam . . . . . . . . 12 figure 3: chipset configuration for main atm layer functionality plus full oam and arbitrary header translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4: miniswitch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5: line card configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6: alp logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7: alp pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8: alp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9: cell header structure used by the atm chip set . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10: mapping rule for transparent vpcs (vpi 3 vpimin) . . . . . . . . . . . . . . . . . . . . 31 figure 11: mapping rule for terminated vpcs (vpi < vpimin) . . . . . . . . . . . . . . . . . . . . . 31 figure 12: lci structure for 4 ports with a vci- and vpi bundle size of 128 . . . . . . . . . . . 32 figure 13: vpi/vci range needed for usage of internal arc . . . . . . . . . . . . . . . . . . . . . . 33 figure 14: address reduction with came . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 15: cell header format at the phy-alp utopia interface . . . . . . . . . . . . . . . . . . 37 figure 16: cell header format at the atm-alp utopia interface . . . . . . . . . . . . . . . . . . 37 figure 17: leaky bucket algorithm (according to itu-t i.371) . . . . . . . . . . . . . . . . . . . . . . 39 figure 18: polu operation mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19: polu operation mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20: polu operation mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 21: polu operation mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 22: data structure in the external connramup and connramdo ram for each lci value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 23: traffic measurement at the port, vpc and vcc level . . . . . . . . . . . . . . . . . . . 48 figure 24: dma for fast traffic measurement data transfer . . . . . . . . . . . . . . . . . . . . . . . 49 figure 25: relationship between link rate, switch port rate and atm user cell rate . . 50 figure 26: utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 27: utopia interface configuration for 4*6 phys at the phy side . . . . . . . . . . . . 52 figure 28: possible address group configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 29: example of an address group configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 30: types of connection points for f4 and f5 oam flow . . . . . . . . . . . . . . . . . . . . 56 figure 31: consequent actions on oam cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 32: configuration of the connection points for nodes with switching fabric . . . . . . 57 figure 33: configuration of the connection points for nodes without switching fabric . . . 58 figure 34: processing for ais, rdi, cc and cca oam cells . . . . . . . . . . . . . . . . . . . . . . . 58 figure 35: processing for lb oam cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 36: cell format extracted from alp to microprocessor . . . . . . . . . . . . . . . . . . . . . . 59 figure 37: cell format inserted from microprocessor into the alp upstream direction without header translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 38: cell format checked for programmable cell filter . . . . . . . . . . . . . . . . . . . . . . . 62 figure 39: access to the internal and external rams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 40: example for spatial multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 41: utopia interface configuration with slave mode at the atm side . . . . . . . . . 146 figure 42: utopia interface configuration with master mode at the atm side . . . . . . . . 147 figure 43: utopia interface configuration with master mode for tx and slave mode for rx direction at the atm side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 44: connection ram upstream interface signals . . . . . . . . . . . . . . . . . . . . . . . . . 150
3;%( /lvwri)ljxuhv 3djh data sheet 9 08.2000 figure 45: microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 46: jtag/boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 47: clock and reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 48: came interface for 16k connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 49: came interface for 8k connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 50: input/output waveform for ac measurements . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 51: clock and reset interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 52: dma interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 53: sram interface generic timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 54: microprocessor write cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 55: microprocessor read cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 56: boundary-scan test interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 57: example of execution timing for write command (request #4) . . . . . . . . . . . 179 figure 58: came read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 59: came write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 60: sorts of packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3;%( /lvwri7deohv 3djh data sheet 10 08.2000 table 1: pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 2: relationship between network requirements and configuration parameters . . 30 table 3: policing operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 4: definition of services (itu-t and atm-forum) . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5: example for configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 6: traffic measurement at vcc level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 7: traffic measurement at vpc level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 8: traffic measurement counters at port level . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 9: polling order of port numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 10: example for port number 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 11: recommended f4 and f5 configuration and consequent action on oam and rm cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 12: truth table for cell filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 13: alp registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 14: utopia interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 15: possible ram configurations of the alp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 16: microprocessor interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 17: boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 18: alp boundary scan table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 19: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 20: operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 21: dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 22: capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 23: clock and reset interface ac timing characteristics . . . . . . . . . . . . . . . . . . . 173 table 24: clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 25: clock and reset interface ac timing characteristics . . . . . . . . . . . . . . . . . . . 174 table 26: sram interface ac timing characteristics for 80pf load . . . . . . . . . . . . . . . 175 table 27: microprocessor write cycle ac timing characteristics . . . . . . . . . . . . . . . . . . 176 table 28: microprocessor read cycle ac timing characteristics . . . . . . . . . . . . . . . . . . 177 table 29: boundary-scan test interface ac timing characteristics . . . . . . . . . . . . . . . . 178 table 30: duration of command execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 31: parameters for read/write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 32: thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
3;%( data sheet 1-11 08.2000 2yhuylhz 2yhuylhz the pxb 4350 e atm layer processor alp is a member of the infineon atm622 chip set. the whole chip set consists of: ? pxb 4330 e atm buffer manager abm ? pxb 4340 e atm oam processor aop ? pxb 4350 e atm layer processor alp ? pxb 4360 f content addressable memory element came main atm layer functionality is achieved with only two chips, alp and abm. the combination of these two devices provides elementary atm functionality like header translation, policing, oam support, multicast and traffic management (fig.1). the functionality is upgradeable to full oam support by the aop (fig.2) and to arbitrary header translation by came (fig.3). )ljxuh &klsvhwfrqiljxudwlrqirupdlq$70od\huixqfwlrqdolw\ utopia pol. ram pointer ram cell ram phys conn. ram conn. ram cell ram utopia utopia switch (loop) pxb 4350 e alp pxb 4330 e abm
3;%( data sheet 1-12 08.2000 2yhuylhz )ljxuh &klsvhwfrqiljxudwlrqirupdlq$70od\huixqfwlrqdolw\soxvixoo2$0 )ljxuh &klsvhwfrqiljxudwlrqirupdlq$70od\huixqfwlrqdolw\soxvixoo2$0dqgdu elwudu\khdghuwudqvodwlrq utopia utopia utopia pol. ram pointer ram cell ram phys conn. ram conn. ram conn. ram conn. ram cell ram s wit ch switch (loop) pxb 4330 e abm pxb 4350 e alp pxb 4340 e aop utopia utopia utopia pol. ram pointer ram cell ram phys conn. ram came conn. ram conn. ram conn. ram cell ram s wit ch switch (loop) pxb 4330 e abm pxb 4350 e alp pxb 4340 e aop
3;%( data sheet 1-13 08.2000 2yhuylhz the atm 622 layer devices can be used as .... ...a full switch in: adsl concentrators / multiplexers (dslam) access multiplexers access concentrators multiservice switches ...line card in: workgroup switches edge switches core switches )ljxuh 0lqlvzlwfkfrqiljxudwlrq $/3 $23 utopia utopia $%0 utopia
3;%( data sheet 1-14 08.2000 2yhuylhz )ljxuh /lqhfdugfrqiljxudwlrq due to their most flexible scaling facilities, feature set and throughput the infineon atm622 layer chips are the ideal devices for almost any atm system. $/3 $23 utopia utopia $%0 utopia 6zlwfk
p-bga-456 data sheet 1-15 08.2000 $70/d\hu3urfhvvru $/3 3;%( 9huvlrq &026 7\sh 3dfndjh pxb 4350 e bga-456 )hdwxuhv 3huirupdqfh ? performance up to stm-4/oc-12 equivalent atm layer processing ? throughput up to 687 mbit/s bi-directional ? up to 16384 connections in both directions (vpc/ vcc) +hdghu7udqvodwlrq ? header verification and discarding of unallocated pn/ vpi/vcis ? address reduction in upstream direction (pn/vpi/vcis -> lci); two modes Cbuilt-in, programmable, versatile address reduction Coptional external address reduction ? header translation in downstream direction (lci -> pn/vpi/vcis) 3rolflqjiru8svwuhdp'luhfwlrq ? policing according to itu-t i.371 and atm forum uni specification ? upc/npc function capability on a per connection basis for up to 16384 connections ? modification of adjusted upc/npc parameters on a per established connection basis without additional cell losses ? up to 3 leaky buckets (lb) per connection with 2 parallel branches: branch 1 containing lb1 and optionally lb2; branch 2 containing lb3 ? 4 leaky bucket configurations selectable per connection ? flexible policing of each port specific cell flow (user data, f4 rm, f5 rm, f4 segment oam, f5 segment oam, f4 end-to-end oam, f5 end-to-end oam) with sw programmable control flags indicating whether the flow is policed in branch 1, branch 2 or is not policed at all ? cdv tolerance (i.e. size of pcr leaky bucket) up to 4s ? maximum burst size (mbs) given by the size of scr leaky bucket of up to 2 10 s ?2 32 pcr values ranging between 1 cell/s and 1,620,000 cells/s. pcr and scr can be adjusted with a granularity of at least 2 -10 cells/s 0xowlfdvwlqgrzqvwuhdpgluhfwlrq ? spatial (different ports) and logical (different vpi/vci for one port) multicast light
3;%( data sheet 1-16 08.2000 2yhuylhz 2$00dqdjhphqwiruxsdqggrzqvwuhdp ? oam levels and flows (f4/f5) according to itu-t/i.610 and bellcore gr-1248-core ? extraction and insertion of oam, rm and 2 programmable cell types for both up- and downstream direction via a 12 cell extraction and 1 cell insertion buffer to the microprocessor ? supported oam cells are ais, rdi, continuity check and loopback cells ? check and generation of crc-10 for incoming and outgoing cells ? extraction point can be configured as originating, intermediate or terminating point for f4 and f5 flow (segment and end-to-end) ? cell processing options as forwarding, dropping, copying and discarding of cells at the extraction and insertion point 7udiilf0hdvxuhphqwiruxsdqggrzqvwuhdp ? traffic measurement (can be dis/enabled) according to bellcore gr-1248 ? traffic measurement intervals of at least 44 minutes ? at vcc level Ctotal incoming and outgoing cells Ctotal incoming and outgoing cells with clp=0 Ctotal discarded cells due to upc/npc with clp=1 and clp=0 for incoming cells respectively Ctotal tagged cells due to upc/npc for incoming cells ? at vpc level Cvpc specific total incoming and outgoing cells Cvpc specific total incoming and outgoing cells with clp=0 ? at port level Ctotal discarded cells due to unallocated pn/vpi/vci Ctotal incoming cells with non-zero gfc field Ctotal incoming and outgoing cells Ctotal incoming and outgoing oam/rm cells enabled per connection 8723,$,qwhuidfh ? multiport utopia [ ] level 1 and level 2 interface in up- and downstream direction according to atm forum, utopia level 2 specification for up to 24 ports ? phy side is master, atm side is master/slave configurable for both tx and rx direction ? utopia frequency up to 51.84 mhz ? statistical demultiplexing with 64 cell shared buffer for up to 24 queues with flexible queue size at utopia downstream transmit interface ? support of up to 24 phys with one queue respectively ? in addition to the utopia-pn a second pn in udf1 is supported for enhanced phy addressing ([whuqdo665$0 ? policing data ssram; can be omitted if policing is not needed. ? connection data upstream ssram; can be omitted if traffic statistic and oam is not needed. ? connection data downstream ssram; mandatory for header translation and multicast ? all ssrams scale with the number of connections; usable pipelined burst ssram types: Ce.g. toshiba tc55v1325ff-7 1mssram(32k*32) or tc55v2325ff-7 2m(64k*32).
3;%( data sheet 1-17 08.2000 2yhuylhz 0lfurfrpsxwhu,qwhuidfh ? intel 386 ex microprocessor interface ? support of dma for fast data transfer between external ram and microprocessor %rxqgdu\6fdq ? boundary scan support according to jtag ,qwhuqdo/rrsv ? internal hardwired loop: upstream to downstream and downstream to upstream 7hfkqrorj\ ? bga-456 package ? 0,35 m cmos ? typ. power dissipation 1.7 w ? extended temperature range -40 c to 85 c
3;%( data sheet 1-18 08.2000 2yhuylhz /rjlf6\pero )ljxuh $/3/rjlf6\pero pxb 4350 e microprocessor interface, 16bit test / jtag interface utopia receive interface clock and reset interface utopia transmit interface downstream connection ram interface upstream connection ram interface utopia receive interface utopia transmit interface slave/master master address control 1m .. 4m ssram 1m .. 6m ssram policing data connection data content adressable memory element (came) (optional) alp 1m .. 4m ssram
3;%( data sheet 1-19 08.2000 2yhuylhz 3lq&rqiljxudwlrq (bottom view) )ljxuh $/33lq&rqiljxudwlrq
3;%( data sheet 1-20 08.2000 2yhuylhz 3lq'hilqlwlrqvdqg)xqfwlrqv the following explanations applies for all pins of a field in the table respectively: ? pins with a 1) attached are connected with an internal pull up resistor. ? pins with a 2) attached are connected with an internal pull down resistor. ? pins with a 3) attached are 5v compatible. ? pins with a 4) attached are tristate when not active. ? pins with a 5) attached are open drain output. 7deoh 3lq'hilqlwlrqvdqg)xqfwlrqv 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq *hqhudoslqv ad17 reset i chip reset ac16 sysclk i core operating clock a11 utphyclk i utopia clock at phy side. r26 utatmclk i utopia clock at atm side. ad25 2) ramvers i selection of 1m (low) or 2m (high) ssram- type. 8723,$5hfhlyh,qwhuidfhxsvwuhdpslqv c15, d14, b15, a16, c16, b16, d15, a17, c17, b17, d16, a18, c18, b18, d17, a19 2) 3) rxdatu (15:0) i receive data from phy side. c15 corresponds to rxdatu(15) ... a19 corresponds to rxdatu(0). c14, a14, b14, a15 3) rxadru (3:0) o address to phy side. c14 corresponds to rxadru(3) ... a15 corresponds to rxadru(0). c13 2) 3) rxprtyu i odd parity of rxdatu(15:0) from phy side. c12, d13, a13, b13 3) rxenbu (3:0) o enable signal to phy side. c12 corresponds to rxenbu (3) ... b13 corresponds to rxenbu (0). c11, d12, a12, b12 2) 3) rxclavu (3:0) i cell available signal from phy side. c11 corresponds to rxclavu(3) ... b12 corresponds to rxclavu(0). b11 2) 3) rxsocu i start of cell signal from phy side.
3;%( data sheet 1-21 08.2000 2yhuylhz 8723,$7udqvplw,qwhuidfhgrzqvwuhdpslqv d8, c7, a7, b7, d9, a8, c8, b8, a9, c9, d10, b9, a10, c10, d11, b10 3) txdatd (15:0) o transmit data to phy side. d8 corresponds to txdatd(15) ... b10 corresponds to txdatd(0). b5, c6, a6, b6 3) txadrd (3:0) o address to phy side. b5 corresponds to txadrd(3) ... b6 corresponds to txadrd(0). d7 3) txprtyd o odd parity to phy side. d6, b4, a5, c5 3) txenbd (3:0) o enable signal to phy side. d6 corresponds to txenbd (3) ... c5 corresponds to txenbd (0). d5, b3, a4, c4 2) 3) txclavd (3:0) i cell available signal from phy side. d5 corresponds to txclavd(3) ... c4 corresponds to txclavd(0). a3 3) txsocd o start of cell signal to phy side. 8723,$5hfhlyh,qwhuidfhgrzqvwuhdpslqv v24, v25, u23, w26, w24, w25, v23, y26, y24, y25, w23, aa26, aa24, aa25, y23, ab26 2) 3) rxdatd (15:0) i receive data from atm side. v24 corresponds to rxdatd(15) ... ab26 corresponds to rxdatd(0). u26, u24, u25, t23 3) rxadrd (3:0) i/o address from atm side. u26 corresponds to rxadrd(3) ... t23 corresponds to rxadrd(0). v26 1) 3) rxprtyd i odd parity of rxdatd(15:0) from atm side. t26, t24, t25, r23 3) rxenbd (3:0) i/o enable signals from atm side. t26 corresponds to rxenbd (3) ... r23 corresponds to rxenbd (0). ab24, ab25, aa23, ac26 3) 4) rxclavd (3:0) i/o cell available signal to atm side. ab24 corresponds to rxclavd(3) ... ac26 corresponds to rxclavd(0). r25 2) 3) rxsocd i start of cell signal from atm side. 7deoh 3lq'hilqlwlrqvdqg)xqfwlrqv 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq
3;%( data sheet 1-22 08.2000 2yhuylhz r24 rxms i selects master (high) or slave (low) mode for utopia rx downstream. 8723,$7udqvplw,qwhuidfhxsvwuhdpslqv k24, l23, k25, l26, l25, l24, m23, m26, m25, m24, n23, n26, n25, n24, p24, p26 3) 4) txdatu (15:0) o transmit data to atm side. k24 corresponds to txdatu(15) ... p26 corresponds to txdatu(0). g25, j23, h26, h24 3) txadru (3:0) i/o address from atm side. g25 corresponds to txadru(3) ... h24 corresponds to txadru(0). k26 3) 4) txprtyu o odd parity of txdatu(15:0) to atm side. f25, h23, g24, g26 3) txenbu (3:0) i/o enable signal from atm side. f25 corresponds to txenbu (3) ... g26 corresponds to txenbu (0). j26, j24, k23, j25 3) 4) txclavu (3:0) i/o cell available signal to atm side. j26 corresponds to txclavu(3) ... j25 corresponds to txclavu(0). h25 3) 4) txsocu o start of cell signal from atm side. p23 txms i selects master (high) or slave (low) mode for utopia tx upstream. 0lfursurfhvvru,qwhuidfhslqv c19, b19, d18, a20, c20, b20, d19, a21, c21, b21, d20, a22, c22, b22, d21, a23 3) 4) mpdat (15:0) i/o data to/ from microprocessor. c19 corresponds to mpdat(15) ... a23 corresponds to mpdat(0). f23, d25, e26, e24, g23, e25, f24, f26 3) mpadr (7:0) i address to microprocessor. f23 corresponds to mpadr(7) ... f26 corresponds to mpadr(0). d24 3) mpwr i write enable from microprocessor. d26 3) mprd i read enable from microprocessor. b24 3) mpcs i chip select from microprocessor. a24 3) 5) mpint o interrupt request to microprocessor. 7deoh 3lq'hilqlwlrqvdqg)xqfwlrqv 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq
3;%( data sheet 1-23 08.2000 2yhuylhz b23 3) 4) mpdreq o dma request to microprocessor. c23 3) 4) mprdy o ready output signal for mpdat write/ read to microprocessor. d22 3) mpdack i m p dma acknowledge 5$0,qwhuidfh665$0slqv af6, ad6, ae6, ac7, af5, ad5, ae5, ac6, af4, ad4, ae4, ac5, af3, ae3, af2, ad1, ab4, ad2 ramadr (17:0) o common address to all external rams. af6 corresponds to ramadr(17) ... ad2 corresponds to ramadr(0). 8svwuhdp&rqqhfwlrq5$0,qwhuidfhslqv ab2, aa3, aa1, aa2, w4, y3, y1, y2, v4, w1, w3, w2, v1, v3, u4, v2, u1, u3, t4, u2, t1, t2, t3, r4, r1, r2, r3, p4, p1, p2, p3, n3 rdatu (31:0) i/o data to/ from connection ram upstream incl. parity bit. ab2 corresponds to rdatu(31) ... n3 corresponds to rdatu(0). ab3, y4 rscu (1:0) o upstream ram address status control. ab3 corresponds to rscu (1) and y4 corresponds to rscu (0). ab1 radvu o upstream ram advance input. aa4, ac2 rceu (1:0) o upstream ram chip enable. aa4 corresponds to rceu (1) and ac2 corresponds to rceu (0). ac3 rgwu o upstream ram global write. ac1 roeu o upstream ram output enable. 7deoh 3lq'hilqlwlrqvdqg)xqfwlrqv 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq
3;%( data sheet 1-24 08.2000 2yhuylhz 3rolflqj5$0,qwhuidfhslqv m4, k1, k3, k2, l4, j1, j3, j2, k4, h1, h3, h2, j4, g1, g3, g2, h4, f1, f3, f2, g4, e1, e3, e2, f4, d1, d3, d2, e4, c1, c2, b1 poldat (31:0) i/o multiplexed data to/ from policing-ram/ testbus incl. parity bit. m4 corresponds to poldat(31) ... b1 corresponds to poldat(0). l1, l3, l2 polad sc (2:0) o address status control to policing ram. l1 corresponds to poladsc (2) ... l2 corresponds to poladsc (0). m2 poladv o advance input to policing ram. m1, m3, n4 polce (2:0) o chip enable to policing ram. m1 corresponds to polce (2) ... n4 corresponds to polce (0). n2 polgw o global write to policing ram. n1 poloe o output enable to policing ram. 'rzqvwuhdp&rqqhfwlrq5$0,qwhuidfhslqv ad15, ac14, af14, ae14, ad14, ad13, af13, ae13, af12, ad12, ac13, ae12, af11, ad11, ae11, ac12, af10, ad10, ae10, ac11, af9, ad9, ae9, ac10, af8, ad8, ae8, ac9, af7, ad7, ae7, ac8 rdatd (31:0) i/o data to/ from connection ram downstream incl. parity bit. ad15 corresponds to rdatd(31) ... ac8 corresponds to rdatd(0). 7deoh 3lq'hilqlwlrqvdqg)xqfwlrqv 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq
3;%( data sheet 1-25 08.2000 2yhuylhz af15, ae15 rscd (1:0) o downstream ram address status control. af15 corresponds to rscd (1) and ae15 corresponds to rscd (0). ac15 radvd o downstream ram advance input. ae16, ad16 rced (1:0) o downstream ram chip enable. ae16 corresponds to rced (1) and ad16 corresponds to rced (0). af16 rgwd o downstream ram global write. ae17 roed o downstream ram output enable. $gguhvv5hgxfwlrq&lufxlw,qwhuidfh&$0(slqv ae22, ad21, af21, ae21, ac19, ad20, af20, ae20, ac18, af19, ad19, ae19, af18, ad18, ac17, ae18, af17 2) 4) arcdat (16:0) i/o data from/to came incl. parity bit. ae22 corresponds to arcdat(16) ... af17 corresponds to arcdat(0). ae23, af22, ad22, ac20 arcadr (3:0) o address to came. ae23 corresponds to arcadr(3) ... ac20 corresponds to arcadr(0). ac21 arcres o reset to came. ad23 arccs o chip select to came. af23 arcwe o write enable to came. ae24 arcoe o output enable to came. ac22 arcclk o clock to came is half of the alp core frequency given by sysclk. -7$*,qwhuidfhslqv c25 1) trst i boundary scan reset c26 1) tdi i test data input p25 1) tck i test clock e23 1) tms i test mode select a25 4) tdo o test data output 7deoh 3lq'hilqlwlrqvdqg)xqfwlrqv 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq
3;%( data sheet 1-26 08.2000 2yhuylhz 7hvw,qwhuidfhslqv ac25 1) outtri i puts all outputs except tdo into tristate mode. ac24 uttri i puts all utopia outputs into tristate mode. af24 2) smode i has to be connected to ground. ae26 2) senab i has to be connected to ground. ad26 alpiidd i has to be connected to ground. ab23 ndtro o 3lq1r )xqfwlrq 6xsso\slqv e7, e9, e11, e13, e14, e16, e18, e20, g5, g22, j5, j22, l5, l22, n5, n22, p5, p22, t5, t22, v5, v22, y5, y22, ab7, ab9, ab11, ab13, ab14, ab16, ab18, ab20 vdd a1, a2, a26, b2, b25, b26, c3, c24, d4, d23, e5, e6, e8, e10, e12, e15, e17, e19, e21, e22, f5, f22, h5, h22, k5, k22, l11, l12, l13, l14, l15, l16, m5, m11, m12, m13, m14, m15, m16, m22, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, r5, r11, r12, r13, r14, r15, r16, r22, t11, t12, t13, t14, t15, t16, u5, u22, w5, w22, aa5, aa22, ab5, ab6, ab8, ab10, ab12, ab15, ab17, ab19, ab21, ab22, ac4, ac23, ad3, ad24, ae1, ae2, ae25, af1, af25, af26 vss 8qfrqqhfwhgslqvslqv - unconnected pins 7deoh 3lq'hilqlwlrqvdqg)xqfwlrqv 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq
3;%( data sheet 2-27 08.2000 )xqfwlrqdo'hvfulswlrq )xqfwlrqdo'hvfulswlrq &ruh)xqfwlrqvdqg,qwhuidfhvriwkh$/3 the atm layer processor (alp) is a device which has a bidirectional data transfer throughput of 687 mbit/s for up to 16384 connections. the alp performs header translation, traffic measurement and a simple oam fault management function in both directions. additionally a policing unit is implemented in upstream and a logical multicast and buffer management unit is implemented in downstream direction. the utopia interface at the ingress and engress side transfers the standardized atm cell format. the connection specific data for policing, traffic measurement and oam can be stored in external rams. if these functions are not needed the related rams can be omitted. for header translation in downstream direction an external ram is mandatory. in upstream direction either an external address reduction circuit like the infineon technologies chip came pxb 4360 e or an internal address reduction circuit (arc) can be used for the conversion of the pn/pi/vci into a local connection identifier (lci). the internal arc is limited in the arbitrary usage of the vpi and vci range. )ljxuh $/3%orfn'ldjudp utopia upstream transmit utopia upstream receive upstream connection ram access block came access block cell type recognition address reduction header translation cell filter upstream add/ drop register utopia downstream transmit utopia downstream receive cell filter downstream header translation multicast light traffic measurement downstream downstream connection ram access block multiplex buffer c access block data busses cell streams cell type recog- nition traffic measurement upstream policing policing ram access block
3;%( data sheet 2-28 08.2000 )xqfwlrqdo'hvfulswlrq )xqfwlrqdo'hvfulswlrqrixvhugdwdiorzlqxsdqggrzqvwuhdpgluhfwlrq throughout this specification the term port is used in the meaning given by the utopia specification [1]. upstream means the direction towards the switching network, downstream towards the physical layer device (phy). upstream: in the upstream direction the cells are taken from the phy-devices into the input utopia buffer, which performs the speed adaptation between the utopia clock and the internal alp clock. subsequently the header of the cell is extracted and used for address reduction together with the port number. the resulting reduced address is called local connection identifier (lci). it uniquely identifies the connection during processing in the atm layer. in order to make the lci accessible to the following atm layer devices (e.g. aop, abm) it is mapped into the header of the cell. additionally the so-called housekeeping (hk) bits are mapped into the cell header (udf1 byte), which carry infineon technologies proprietary cell identification (e.g.: cross office check) evaluated by the atm layer devices within the system. the mapping of new contents into the header is called header translation (ht). in the alp the lci is used as address for accessing the external rams containing the connection specific data. two other functions performed upon the upstream cell flow are traffic measurement and policing. in case of traffic measurement the various traffic counters are read from the external connection ram (connramup), updated and stored back. the policing unit (polu) reads the variables, constants and flags needed by the upc/npc algorithm, performs it and stores the updated state variables back into the policing ram (poluram). if an overflow of the contracted bit rate happens, cells will be discarded or tagged depending on the chosen configuration. both, policing and traffic measurement, require a preliminary cell type recognition, which uses the cell header and the connection configuration flags read from connramup. if not discarded, the cell with the new header (including lci and hk) exits alp through the output utopia interface. downstream: after the cell has passed the input utopia buffer the lci is extracted from the header and used to address the external connection ram (connramdo), which contains the new vpi,vci and pn as well as the traffic counters for downstream direction. in case of the header translation the restored vpi, vci and pn are mapped into the header as defined by the external atm utopia cell format. for special low end applications there is a possibility to perform a so-called multicast-light function, which means broadcasting the incoming cell to different ports and/or connections, in exchange for lower performance. the traffic measurements downstream are performed in a similar way as in upstream direction. the outgoing cell is intermediately stored in the utopia output buffer until the addressed phy device is able to receive it. $gguhvv5hgxfwlrq the alp and the other members of the infineon technologies 622mbit atm chip set use an internal address identifier beside the switching element for all atm related functions. the internal address identifier is named lci and has an address width of 14 bits which supports up to 16k connections for the stm-4 link. two modes are supported by the alp to reduce the address range. the first mode needs an external address reduction circuit (came device pxb 4360 e) which translates any arbitrary address, inside the address range from 0 to 2 32 -1, into another arbitrary address inside the address range from 0 to 2 14 -1. the configuration of the external arc (came device) has to be done for each established connection separately.
3;%( data sheet 2-29 08.2000 )xqfwlrqdo'hvfulswlrq herewith the pn, vpi and vci of an incoming cell are converted into an lci. this mode is the most flexible translation mechanism which is not always needed if the vpi and vci is in a predefined address range as used e.g. in the access network area or in a lan environment. for such applications an internal address reduction circuit was built in which can be used in a second mode. the internal arc can be configured with only three parameters for all connections which determine the range of the pn, vpi and vci for the calculation of the lci. the cell header structure used by the infineon technologies atm chip set is shown in iljxuh . )ljxuh &hoo+hdghu6wuxfwxuhxvhge\wkh$70&kls6hw the lci is used by the alp to address the connection specific entries stored in the external connramup and poluram in upstream direction and connramdo in downstream direction. connramup stores information for oam, traffic measurement and header translation for each connection. it is also sw configurable (see vhfwlrq page 75) whether the connection is valid (see vcon_up) or not which is a useful feature for both set up and release procedure. herewith an established connection can be configured and tested before it is valid for the user. the release of a connection can be done immediately and afterwards all connection specific data can be read out for billing purposes. the cell arrival of an invalid connection can cause two actions. either an interrupt is generated (see vld_err_u/d, vhfwlrq page 117) and the cell is discarded or the cell is transmitted (see vlderren_u/d, vhfwlrq page 133) without interrupt generation. utopia level 2 16-bit lci(11:0) vpi(11:0) vci(11:0) pti c pn(5:0) vpi vpi vci vci vci pt c udf/pn vci(15:12) c pti vci(11:0) lci hk(2:0) pn(2:0) lci generation pn, vpi and vci reduction vci(15:12) 715 0 13 0 15 0 0 0 13 utopia level 2 16-bit lci lci a b shown mapping according to an external arc or an internal arc b a alp alp abm aop phy hk: house keeping bits, proprietary use, should be '111' pn: only used by iwe8 device
3;%( data sheet 2-30 08.2000 )xqfwlrqdo'hvfulswlrq ,qwhuqdo$gguhvv5hgxfwlrq&lufxlw the usage and configuration of the internal arc is sw-controlled via the mode and adred_vpim register (see vhfwlrq page 110). the cam flag in register mode selects the usage of the internal or external arc (came device). for the internal arc the range of the pn, vpi and vci for the calculation of the lci is determined by the three parameters p_numb, m_numb and vpimin. the source of the pn, which can be derived either from the utopia address or the pn inside the udf1 of a cell, is selected by the flag pn_source_u. using internal arc requires an assignement of vpi and vci to a logical connection in an order which accommodates the mapping scheme of the alp (see iljxuh ). the mapping rule has the following concept. the vpcs are divided into two groups. the first group contains the terminated vpcs and the second group the transparent vpcs. the vpi values of the terminated vpcs are lower than the value of the parameter vpimin. the vpi values of the transparent vpcs are greater than or equal to the value of the parameter vpimin. the number of vccs from each terminated vpc is determined by the ratio of the blocksize (bls) to maximum pn max . the number of transparent vpcs is equal to the number of vccs of each terminated vpc minus vpimin. the sw is responsible for the correct selection of the parameters p_numb, m_numb and vpimin. the meaning of parameters is the following: ? the blocksize bls = number of ports * number of vccs within a terminated vpc = 2 m_numb . ? the maximum number of ports pn max = 2 p_numb . ? the maximum of vccs in a terminated vpc = vcc max = 2 (m_numb - p_numb) = bls/pn max please note that, ? since a vpc block size is equal to a vcc block size, vpc max = vcc max . ? the terminated vpis < vpimin, the transparent vpis >= vpimin. the principle of the internal arc is explained on an example where 4 ports are supported by the alp. each port transports 128 vpcs and 128 vccs per vpc. 20 vpcs are terminated at the atm switch. the calculation of the three parameters and the mapping rules for the calculation of the lci is shown in wdeoh , iljxuh and . according to the requirement of 20 terminated vpcs the value of vpimin is 21. the external ram can store 32 blocks of the given block size (16k / bls). these blocks should be divided in up to 31 blocks with terminated vpcs (0..30) and one block with transparent vpcs. however for the most efficient usage of the external ram the value of vpimin should be 31. the example is continued with these new parameters. two mapping rules exist for the mapping of transparent and terminated vpcs. 7deoh 5hodwlrqvklsehwzhhq1hwzrun5htxluhphqwvdqg&rqiljxudwlrq3dudphwhuv 1hwzrun5htxluhphqwv &rqiljxudwlrq3dudphwhu 4 ports p_numb = 2 128 vccs per terminated vpc bls = 4ports * 128 vccs = 512 -> m_numb = 9 128 vpcs split into 20 terminated and 108 transparent vpcs vpimin = 21
3;%( data sheet 2-31 08.2000 )xqfwlrqdo'hvfulswlrq )ljxuh 0dsslqj5xohiru7udqvsduhqw93&v93, 3 93,0,1 )ljxuh 10 shows that the lci value of the transparent vpcs is gathered only from the vpi and the pn range. the lci range is in the interval between lci max and lci max -2 m_numb (maximum number of transparent vpc over all ports) . inside the lci range only the lcis from the vpcs with a vpi value greater than or equal to vpimin are generated. the lci value from the transparent vpcs with a vpi value between 0 and vpmin-1 is not generated because the internal acr mechanism switches to the other mapping rule depicted in iljxuh . in this case the lci value of the terminated vpcs is gathered from the pn, vpi and vci range. )ljxuh 0dsslqj5xohiru7huplqdwhg93&v93,93,0,1 the bit field of the pn and vpi not mapped into the lci must be zero in the header of the incoming cell. otherwise the cell will be discarded. the same is true for the not mapped bit fields of the vci of the cell with vpi < vpimin. the mapping rule gives the following lci structure. the lci address range is divided into two sections. the upper section contains the lci which corresponds to the vpi of the transparent virtual path connections. in this section the lcis for the vpi interval between 0 and 30 are not generated (vpis 3 vpimin). 9&, 0 15 m_numb - p_numb = 7 93, 0 11 0 31 5 p_numb =2 /&, 0 13 mp 11 1 11 m_numb - p_numb = 7 9&, 0 15 m_numb - p_numb = 7 93, 0 11 0 31 5 v_min = min(12,14-m) p_numb =2 /&, 0 13 mp 00 0 0 0 00 00 0 0 0 00 0 0 00 00
3;%( data sheet 2-32 08.2000 )xqfwlrqdo'hvfulswlrq )ljxuh /&,6wuxfwxuhiru3ruwvzlwkd9&,dqg93,%xqgoh6l]hri this lci range can be used to store the connection specific traffic measurement data for the terminated vpcs which are addressed by the lci2_up pointer. for detailed explanation see vhfwlrq page 46. the lower section contains the lci corresponding to the vpi and vci values of the terminated virtual path connections. the lsbs of the lci contain the phy numbers pn so the ascending lci-values are cyclically associated with the phys. details of the lci structure are depicted in iljxuh . in the following a second example is shown to explain the difference between the usage of the external arc (came device) and the internal arc. it is shown that it only depends on the vpi and vci range whether the internal or external arc (came device) is selected. the scenario is that 2 physical lines are connected to the alp via the utopia interface at port 1 and 2. a) at port 1: there are transmitted 10 terminated and 205 not terminated vpcs. vpi = 0 contains 73 vccs (vci = 0...72),.... and vpi = 9 contains 40 vccs (vci = 0...39). b) at port 2: there are transmitted 1 terminated and 180 not terminated vpcs. vpi = 0 contains 86 vccs (vci = 0...85). for the selected vpi and vci values the external arc (came device) has to be used. the internal arc can be used if different vpi/vci values are chosen for the same number of transmitted vpcs and vccs. the steps for the selection of the right vpi and vci values are depicted in iljxuh . in this example the vpi values for the first not terminated vpc have to be shifted to vpimin = 16. additionally the number of all vccs of each terminated vpc has to be the same as the number of all transmitted vpcs. vpc block for vpi*=0-127 512 entries 0 16383 vcc block for vpi=0 512 entries vci=127 : vci=1 vci=0 pn=3 pn=2 pn=1 pn=0 pn=3 pn=2 pn=1 pn=0 vpi=127 : vpi=1 vpi=0 pn=3 pn=2 pn=1 pn=0 pn=3 pn=2 pn=1 pn=0 16383 16382 16381 16380 15875 15874 15873 15873 515 514 513 512 3 2 1 0 lci values vcc block for vpi=1 512 entries vcc block for vpi=30 512 entries vci=127 : vci=1 vci=0 * vpi entries 0..30 contain vp-specific data for terminated vps 4 ports each with 31 terminated vpc each c ont aining 128 vccs 4 ports each with 128 not terminated vpcs
3;%( data sheet 2-33 08.2000 )xqfwlrqdo'hvfulswlrq )ljxuh 93,9&,5dqjhqhhghgiru8vdjhri,qwhuqdo$5& the number of vpcs being equal to the number of vccs is 256. using such vpi/vci values we can serve up to 4 ports each transmitting 4096 connections. the difference between the two scenarios is that the internal arc has predefined ranges of vpi and vci which are not completely used. ([whuqdo$gguhvv5hgxfwlrq&lufxlw&$0(ghylfh the address reduction circuit can be a content addressable memory or a pointer look-up circuit which reads the pn, vpi and vci and delivers the corresponding lci as a search result. infineon technologies provides a content addressable memory element came pxb 4360 e. the alp supports the configuration, test and search in the external arc operation mode (came device, see iljxuh ). the configuration of the external arc (came device) is sw controlled. the cam flag of the mode register (see vhfwlrq page 110) selects the usage of the external arc (came device). for the setup of each connection the corresponding lci, pn, vpi and vci are written from the microprocessor into the adr (see vhfwlrq page 128), camadrl register (see vhfwlrq page 90) and camadrh register (see vhfwlrq page 90). furthermore it can be defined whether this entry belongs to a connection of a terminated vpc and whether the entry is valid which is indicated by the p_ip and vcon bits respectively in the adr register. subsequently the came-write command of the cmr (see vhfwlrq page 111) register invokes the writing of the adr, camadrl and camadrh register successively to the external arc (came device). after a number of cycles needed for the command execution of the came the alp reads the status information from the came and writes it into the cstatr register (see vhfwlrq page 114). an indication for the execution of the came-write command is delivered to the cmr register. in the cstatr register two alarm 9&, 93, 9&, 93, 9&, 93, 3ruw 3ruw 9&, 93, 3ruw 3ruw 5dqjhri whuqlpdwhg93v 5dqjhri qrw whuqlpdwhg93v $ 6hdufkwkheljjhvw93dqg9&%xqgoh %ljjhvw93%xqgohfrqwdlqv93v %ljjhvw9&%xqgohfrqwdlqv9&v %xqgohvl]hzlooeh urxqghgwr 1 % 'hwhuplqhwkhkljkhvwqxpehuriwkhwhuplqdwhg93 +ljkhvw93qxpehulv 1xpehuriwhuplqdwhg93vlvurxqghgwr 1 qrwxvhg qrwxvhg
3;%( data sheet 2-34 08.2000 )xqfwlrqdo'hvfulswlrq indications are foreseen for the came-write mode. first alarm is generated by the came if a pn, vpi, vci and lci iswritten into the came which already exists. such an entry is refused by the came. the second alarm is generated by the came if a valid connection (vcon in the came) is overwritten. this means the pn, vpi and vci for an active lci is changed without switching down the vcon of the lci in the previous step. this has to be prevented because the connection has to be released before an new connection with the same lci is set up. in this case the came has to refuse the entry. )ljxuh $gguhvv5hgxfwlrqzlwk&$0( the alp supports a came-read mode into the cmr register to verify the values of the pn, vpi, vci, p_ip and vcon for each lci defined in the adr register, which are written into the camadrl and camadrh registers. to test the external arc (came device) a test mode is supported by the alp. in this mode the test commands are written into the adr register and transferred to the came with the test command in the cmr register. after test command execution the alp reads the status information and writes it into the cstatr register. two test cases are foreseen to identify failures in the internal memory of the came. after the configuration of the memory banks with a predefined value the contents of the memory banks are read and compared. in case of a difference an alarm indication test read fault is activated in the cstatr register. the same can be done using a search command which detects memory locations with different contents. for this case the alarm indication test search fault is activated in the cstatr register. upon cell arrival the alp invokes the came search command either for the user cells or for the oam f4 flow cells of a terminated vpc. the pn, vpi and vci are written to the external arc 32 16 1 0 don't care valid valid valid 0 0 8191 lci (vcc) lci (vpc) p_ip match bit 0..31 match bit 16..31 or pn vpi vci pn (3:0) vpi (11:0) vci (15:0)
3;%( data sheet 2-35 08.2000 )xqfwlrqdo'hvfulswlrq (came device). after the execution of the search command which needs a number of cycles the alp reads the lci, vcon, p_ip and status information. the status information is written into the csir register and the lci is written into the cell header. the source of the pn which can be either the utopia address or the pn in the udf1 of the cell is determined by the pn_source_u in the mode register. the number of pn(5:0) bits used for the came is defined by p_numb in the mode register and has to be in the interval between 4 and 6. for p_numb equal to 4 the contents of camadrh(16:0) are gathered from pn (3:0) and vpi (11:0) which is used for nni application. if the number of pn bits is increased then (16 - (number of pn bits)) least significant vpi bits are mapped into the camadrh register. in case of a failure all internal errors in the came during the address reduction are signalled by the cam_err interrupt in the isr1 register (see vhfwlrq page 117). the status information is written into the csir register (see vhfwlrq page 121). information on parity errors at the came interface, mismatch or multimatch as a response of the came search command and other failure cases are given. the vcon bit in the came defines whether the connection is valid or not. for not valid lcis the alp will discard or forward the cell depending on the nodis_cam flag in the testr (see vhfwlrq page 133) register. for oam f4 cells the came delivers an lci of any of the vccs contained in the vpc. a short summary of all sw related control, interrupt and status registers is given below for orientation. the detailed description can be founded in vhfwlrq page 64. control bits of the internal register 02'( : ? the usage of the internal or external address reduction circuit is determined by the &$0 bit. ? the 3b180% bits define how many bits of the port number are used to derive the lci. the port number is used by both the internal and external acr. ? the 0b180% bits define the block size used by the internal acr to derive the lci. the 31b6285&(b8 bit selects whether the utopia address or the pn in the udf1 of the cell header is used as the source of the port number. control bits of the internal register $'5('b93,0 : ? 93,0,1 bits define the lowest vpi value of all transparent vpcs. this parameter is only used by the internal arc. the value of vpis above the value of the lowest vpi belong to the group of transparent vpcs (not terminated vpc). control bits of the register $'5 : ? $'5 bits correspond to the value of the lci for the operation of the external arc (came device). ? 3b,3 bit indicates whether the connection point is a path intermediate point of a transparent vpc or an termination point of the vpc. ? 9&21 bit indicates whether the connection is valid or not. control bits of the registers &$0$'5/ and &$0$'5+ : ? 9&, bits correspond to the value of the vci for the operation of the external arc (came device). ? 31 bits correspond to the value of the pn for the operation of the external arc (came device). ? 93, bits correspond to the value of the vpi for the operation of the external arc (came device).
3;%( data sheet 2-36 08.2000 )xqfwlrqdo'hvfulswlrq control bits of the internal register &05 : ? 035(4'() bits control both the reading from and the writing to the external arc (came device) and connramup. the data transfer to the external arc (came device) occurs via the internal registers adr, camadrl and camadrh. the data transfer to the external connramup occurs via the internal registers adr, wdrxl/h and rdrxl/h. besides the separate transfer to the adr and connramup it is also possible to write the data to both units simultaneously. the addressing of the wdrxl/h occurs via the lci in the internal adr register which is also used for programming, testing and operation of the external adr. ? 675(4 bit invokes the command and indicates the finishing of the command which is defined by the 035(4'() bits. status bits of the internal register &67$75 : ? 67$786 bits give a detailed status report of the external arc (came device) after the microprocessor request. alarm indication bits of the internal register ,65 : ? &$0b(55 bit gives an interrupt if errors occur during the address reduction in the external arc (came device). status bits of the internal register &6,5 : ? 67$786 bits give a detailed failure report of the external arc (came device) whenever the interrupt cam_err is generated. configuration bit of the test register 7(675 : ? the bit 12',6b&$0 determines whether a cell is discarded or not if the connection is not configured in the external arc (came device) for this cell. test bits of the test register &$09,/&, : ? the bits /&, are the response to the lci value from the external arc (came device) in the test mode. ? the bit 3b,3 is the response to the p-ip value from the external arc (came device) in the test mode. ? the bit 9&21 is the response to the vcon value from the external arc (came device) in the test mode. 3urfhvvlqjriwkh+hdghu6wuxfwxuhe\wkh$/3 the header format of the atm cells which are received and transmitted at the 16 bit utopia interface at the phy side is depicted in iljxuh . according to the standardized cell format [1], the alp optionally supports a second proprietary port number information in the udf1 (word2(8:15)). in upstream direction the alp can extract the port number either from the utopia address or from the udf1 in the cell header. in downstream direction the alp can provide two port numbers simultaneously. the first port number is transmitted via the utopia address and the second via the pn in the udf1. this is a useful feature especially for low bit rate lines were up to 64 ports can be supported with one queue and a single utopia address. however it is necessary that the phy device translates the second pn in the udf1 into the corresponding pn of the physical line. the infineon technologies chip iwe8 (pxb4220) supports this feature. the contents of the new generated cell in downstream direction come from the external ram (connramdown).
3;%( data sheet 2-37 08.2000 )xqfwlrqdo'hvfulswlrq )ljxuh &hoo+hdghu)rupdwdwwkh3+<$/38723,$,qwhuidfh the header format of the atm cells which are received and transmitted at the 16 bit utopia interface at the atm side is depicted in iljxuh . the contents of the new generated cell in upstream direction come from the internal or external address reduction circuit (lci), the external ram connramup (hk) and the policing unit (clp) depending on the nonconformance test. )ljxuh &hoo+hdghu)rupdwdwwkh$70$/38723,$,qwhuidfh +rxvh.hhslqj+.%lwv within the infineon atm chip set the use of house keeping (hk) bits is possible. these three bits are included in the cell header in upstream direction and evaluated only in downstream direction. these bits are used to perform a kind of node internal oam processing which is infineon proprietary. the alp only supports three combinations. with hk = "111" the incoming cell is a user cell, i.e. all cells without special hk functions. when a user cells arrives at the alp, it is forwarded to the utopia interface. cells with hk = "010" are dynamic bandwith allocation (dba) cells, which are needed for traffic management. these cells are dropped to the microprocessor. the last supported hk = "100" defines cross office check (coc) cells. these cells are used to verify the functionality of the network node. they are dropped to the microprocessor when arriving at the alp. because the hk is only defined in the infineon atm chip set, all cells with hks should not leave the network node. therefore all cells with not supported hks are discarded. the hk function can be disabled using bit hk_dis in register dct_config (see vhfwlrq page 125). bit:1514131211109876543210 0 vpi(11:0) or gfc(3:0) and vpi(7:0) vci(15:12) 1 vci(11:0) pt(2:0) clp 2 pn(5:0) udf2 word bit:1514131211109876543210 0 lci(11:0) vci(15:12) 1 vci(11:0) pt(2:0) clp 2 lci(13:12) hk(2:0) pn(2:0) udf2 word
3;%( data sheet 2-38 08.2000 )xqfwlrqdo'hvfulswlrq 3rolflqjlq8svwuhdp'luhfwlrq at the announcement of a connection request, an acceptance algorithm checks in atm networks if enough capacity is available on the transmission line in order to transmit the user data at the desired bit rate assuring quality of services objectives. the connection acceptance algorithm usually requires separate policing of sustainable cell rate (scr, atm-forum) and peak cell rate (pcr, itu). the policing function checks if the cells of the incoming cell stream are conforming to the negotiated connection parameters in order to guarantee the transmission quality for each network user. if the contracted cell rate is exceeded the cell is either discarded or tagged (changing the clp bit from 0 for high priority cells to 1 for low priority cells, i.e. increasing the cell loss probability.). policing at the entrance of the public network is called usage parameter control (upc); policing between two networks is called network parameter control (npc). the upc/npc algorithm implemented in the alp is functionally equivalent to the generic cell rate algorithm (i.e. leaky bucket or virtual scheduling algorithm, abbreviated gcra, lb or vsa) as defined in the atm forum, uni specification and the itu-t recommendation i.371. the policing unit of the alp has a upc/npc function capability on a per connection basis for up to 16384 connections. the general configuration and the alarm indication of the policing unit is determined by the internal registers of the alp (p_conrl [ vhfwlrq page 91], p_conrh [ vhfwlrq page 92], sc_conr1 [ vhfwlrq page 129], sc_conr2 [ vhfwlrq page 129], isr1 [ vhfwlrq page 117] and testr [ vhfwlrq page 133]). the connection specific configuration of the leacky bucket (lb) units and the corresponding policing parameters are stored in the external poluram (dword 0-10 [ vhfwlrq 3.3.1.1 - 3.3.1.11, page 71 - page 73]). the counter values of the nonconforming cells are stored in the external ssram (connramup) [ vhfwlrq page 75] for traffic measurement. 7kh/hdn\%xfnhw/%$ojrulwkp the principle of the leaky bucket can be viewed as a finite capacity bucket whose real-valued content drains out at a continuous rate of one unit of content per time unit and whose content is increased by the increment t for each conforming cell. equivalently, it can be viewed as the work load in a finite capacity queue or as a real-valued counter. if at a cell arrival the counter of the bucket is less than or equal to the limit value t , then the cell is conforming; otherwise, the cell is non-conforming. the capacity of the bucket (the upper bound of the counter) is (t+ t ). tracing the steps of the continuous-state leaky bucket algorithm (see iljxuh ), at the arrival time of the first cell t a (1), the content of the bucket is set to zero and the last conformance time lct is set to t a (1). at the next arrival time of the k th cell t a (k), first the content of the bucket is provisionally updated to the value x, which equals the content of the bucket after the arrival of the last conforming cell x minus the amount the bucket has drained since the arrival, [t a (k)-lct]. if x is less than or equal to the limit value t , then the cell is conforming and the bucket content x is set to x (or to 0 if x is negative) plus the increment t, and the last conformance time lct is set to the current time t a (k). if x is greater than the limit value t , then the cell is non-conforming and the values of x and lct are unchanged.
3;%( data sheet 2-39 08.2000 )xqfwlrqdo'hvfulswlrq )ljxuh /hdn\%xfnhw$ojrulwkpdffruglqjwr,787, to realize a number of different sevices defined by atm-forum and itu, the alp provides a set of three leaky buckets, organized in two parallel branches. the first upper branch contains an lb1 and optionally an lb2 in serial. herewith the parameters of the services can be realized. the second down branch contains the lb3. the lower branch is not necessary for the realisation of atm-forum and itu-t services. therefore lb3 can be disabled and is provide for additional parameters. for each connection the leaky bucket configuration and the policing parameters, containing the three parameters w min , delta and y (see vhfwlrq page 43), are stored in the external policing ram (poluram, see vhfwlrq page 71). the poluram entry for a connection contains 11 dwords. the dwords 0 to 9 contain the policing parameters, dword10 the configuration parameters. up to four different modes are selectable per connection via the mode bits. the policing configuration modes are summarized in wdeoh , page 40 and are depicted in the vhfwlrq page 41 (mode 0), vhfwlrq page 42 (mode 1), vhfwlrq page 42 (mode 2) and vhfwlrq page 43 (mode 3). the context between policing modes and the services of atm-forum and itu is shown in wdeoh . &rqwlqxrxvvwdwhohdn\ exfnhwdojrulwkp x value of the leaky bucket counter x' auxiliary variable lct last conformance time at the time of arrival t a of the first cell of the connection to cross the given interface, x = 0 and lct = t a . arrival of a cell at time t a x' = x - (t a -lct) non-conforming cell x' > t ? x = max(0,x') + t lct = t a conforming cell next cell yes no
3;%( data sheet 2-40 08.2000 )xqfwlrqdo'hvfulswlrq for each connection the microprocessor can configure which cells should be policed. therefore register mode consists a set of 2-bit flags for seven different cell types. using these flags it is choosen, if the according cell type is policed (and in which branch) or not. if all cell types in a connection are not policed by setting the flag bits to 00, the connection is defined as not configured. in this case an interrupt is generated if a cell for this connection is detected by the polu. using bits dis_u/d the microprocessor is able to select, which branch for the leaky bucket is used. *hqhudo&rqiljxudwlrqriwkh32/8 the operation of the polu is controlled by the microprocessor via the p_conrl and p_conrh registers. the valid_conf bit is used to indicate that the data has been changed 7deoh 3rolflqj2shudwlrq0rghv 0rgh 7djjlqj /% /% /% 0 yes scr (0) pcr (0+1) pcr (0+1) 1 no scr (0) pcr (0+1) pcr (0+1) 2 no scr (0+1) pcr (0+1) pcr (0+1) 3 no pcr (0+1) disabled pcr (0+1) 7deoh 'hilqlwlrqri6huylfhv,787dqg$70)ruxp ,787 $70)ruxp 0rgh service parameters service parameters dbr pcr (0+1) pcr (oam) cbr pcr (0+1) pcr (oam) 3 sbr1 pcr (0+1) scr (0+1) vbr1 pcr (0+1) scr (0+1) 2 sbr2 pcr (0+1) scr (0) vbr2 pcr (0+1) scr (0) 1 sbr3 pcr (0+1) scr (0) tagging optional vbr3 pcr (0+1) scr (0) tagging optional 0 abt/dt abt/it pcr (0+1) scr (0+1) pcr (rm) pcr (oam) 2 ubr1 pcr (0+1) 3 ubr2 pcr (0+1) tagging optional not supported abr pcr (0+1) mcr (0+1) abr pcr (0) mcr (0) icr (0) acr (0) for itu : 3 for atm : not supported
3;%( data sheet 2-41 08.2000 )xqfwlrqdo'hvfulswlrq by the microprocessor and that the polu has accepted and executed the command. two operation modes, namely test operation mode (tom) and normal operation mode, are implemented. a reset of the alp puts the polu in tom with no policing is enabled. after initializing the poluram (all 0) and the establishment of a connection the polu can be operated in the normal operation mode by setting the tom bit in register p_conrl. for all connections the tagging and discarding of cells can be suppressed resprectively via the bits taginh and disinh. using the scan registers sc_conr1 and sc_conr2 the range of policed lcis is defined. the polu can only be operated after the activation of the polu refresh mechanism which is activated with the polu_refr_en bit. the testr register provides two bits for the handling of incorrect cells. the selection whether a cell is discarded or not if the cell generates a parity error at the poluram interface is done using bit parerren_polu. such an error is indicated via the interrupt status register bit polu_parerr_u. it doesnt matter if discarded or not, for these cells no policing occurs. the second bit, povlderren, determines whether a cell is discarded or not if the connection is not configured for this cell. this error generates an interrupt which is indicated by the interrupt status register bit polvld_err. a connection is not configured if all values of the cell policing option flags are 00. a connection is defined as configured if all values of the cell policing option flags are 11. for both cases the policing is not active. 2shudwlrq0rgh )ljxuh 32/82shudwlrq0rgh this mode is the only one in which the priority of non-conforming cells is changed to lower priority (cell is tagged). when this mode is configured, e.g. for sbr.3 (itu) or vbr.3 (atm- forum) services, the values for the lb1 are calculated with the scr(0)-parameter and the values for lb2 with the pcr(0+1)-parameter. cells with clp=1 bypass the lb1. only cells with clp=0 are policed by the lb1. the resulting cell stream, consists of the conforming clp(0) cells and the not policed cells with clp(1), run through the policing with lb2. mode = 00 s clp=1 clp=0 tag non-conforming clp 0 cells as clp 1 leaky bucket 1 leaky bucket 2 discard non- conforming cells (clp0+1) conforming (clp0+1)
3;%( data sheet 2-42 08.2000 )xqfwlrqdo'hvfulswlrq 2shudwlrq0rgh )ljxuh 32/82shudwlrq0rgh this mode is configured for e.g. sbr.2 (itu) or vbr.2 (atm-forum) services. the values for the lb1 are calculated with the scr(0)-parameter and the values for lb2 with the pcr(0+1)- parameter. cells with clp=1 bypass the lb1. only cells with clp=0 are policed by the lb1. in this mode, no tagging is available. so the non-conforming cells are discarded. the resulting cell stream, consists of the conforming clp(0) cells and the not policed cells with clp(1), run through the policing with lb2. 2shudwlrq0rgh )ljxuh 32/82shudwlrq0rgh in mode 2 the values for the lb1 are calculated with the scr(0+1)-parameter and the values for lb2 with the pcr(0+1)-parameter. this mode is selected e.g. for sbr.1 (itu) or vbr.1 (atm-forum) service. the complete cell stream (cells with clp=0 and clp=1) is policed by the mode = 01 s clp=1 clp=0 leaky bucket 1 leaky bucket 2 discard non- conforming cells (clp0+1) conforming (clp0+1) discard non- conforming cells (clp0) mode = 10 clp0+1 leaky bucket 2 discard non- conforming cells (clp0+1) conforming (clp0+1) leaky bucket 1 discard non- conforming cells (clp0+1) conforming (clp0+1)
3;%( data sheet 2-43 08.2000 )xqfwlrqdo'hvfulswlrq lb1. the resulting cell stream is conforming to the scr(0+1) and is afterwards policed by lb2. now, the resulting cell stream is conforming to the pcr(0+1). additionally the lb3 can be declared for pcr(oam) policing (for abt services by itu). 2shudwlrq0rgh )ljxuh 32/82shudwlrq0rgh this mode is used e.g. for dbr (itu), cbr or ubr1 (atm-forum) services. the values for the lb1 are calculated with the pcr(0+1)-parameter. the lb2 is disabled in this mode, the cell stream passes it without policing actions. the complete cell stream is policed by the lb1. the non-conforming cells are discarded. for dbr and cbr the lb3 can be configured for policing the pcr (oam). &dofxodwlrqri32/83dudphwhuv the policing parameters for the leaky bucket are derived from the pcr, scr, mbs and tagging indication provided from the signalling message. the cdvt is provided by the network operator via mutual agreements between network operator and user or via signalling message. the l x and t x parameters for scr and pcr are calculated with the same formula. therefore the index in the formula is named xcr, where x stands for peak (p) or sustainable (s). according to itu up to 16384 xcr values l xcr are defined which range from 1cell/s to 4.29077gcell/s. the relative difference between any pair of successive l xcr value is smaller than 2 -9 . note : x stands for rounding up to the nearest integer value. mode = 11 clp0+1 leaky bucket 2 conforming (clp0+1) leaky bucket 1 discard non- conforming cells (clp0+1) conforming (clp0+1) disabled m x cr log 2 xcr sig 1023 ------------------ ? ?? 9 + = k x cr xcr sig 2 m xcr 9 C -------------------- 512 C =
3;%( data sheet 2-44 08.2000 )xqfwlrqdo'hvfulswlrq l xcr = 2 m xcr (1+k xcr /512) [cells/second] 0 m xcr 31 0 k xcr 511 the reciprocal value of l xcr gives the corresponding peak emission interval value t xcr. due to the non-linearity an extra bit is needed for the exponent. t xcr is calculated as: this gives 16384 peak emission interval values t xcr ranging between 0.9995 and 2.33*10 -10 seconds. the relative difference between any pair of l xcr and t xcr is smaller than 0.0997%. for the non-conformance test of a connection two policing parameters are needed by the polu for configuration of the leaky buckets. these are the value of 'howd , the decrement parameter, and : plq , comparable to the limit value of the leaky bucket. the two parameters are stored between word3 [ vhfwlrq page 72] and word10 [ vhfwlrq page 73] in the external ram (poluram) and are calculated as: delta = t/t z = xcr z /xcr w min = t /t z t z is the peak emission interval for the cell processing of the alp. for a sysclk with 51.84mhz and 32 cycles for one cell, the peak emission interval t z for one cell is 617.28ns. the corresponding xcr is 1,620,000 cells per second. delta is the cell emission interval normalized to the cell processing period. it has 2 32 values and a granularity of 2 -11 . as a result a granularity of 2 -10 cells/s of the pcr or scr can be adjusted. w min is the ratio between the cdv parameter t and the emission interval for one cell t z . t can also be derived from the signalling parameters mbs, t scr and t pcr as: t x cr 2 m x cr 1 + () C 1 1023 k ' x cr C 1024 ------------------------------------- - + ? ? ?? onds sec = k ' pcr 2047 k x cr 512 C k x cr 512 + --------------------------------------------- 1 + = 0m x cr 31 0k x cr 511 t ibt mbs 1 C () t scr t pcr C () [] onds sec =
3;%( data sheet 2-45 08.2000 )xqfwlrqdo'hvfulswlrq ([dpsohiru32/8frqiljxudwlrq this example is according to to the specification for unstructured circuit emulation service of the atm forum and itu. this service e.g. handles cbr traffic using aal1 with 47 bytes per cell at a data rate of 2.048mbit/s for e1, which results in a peak cell rate of 5446.8cell/s (= pcr sig ). according to i.371 the m and k parameters are calculated according: the value of both parameters has to be round up. as a result m pcr =12 and k pcr =169. with the formula given in vhfwlrq the parameters are: k pcr =508 (rounding down), t pcr = 183.463 m s and l pcr =5448cells/s. be aware that the inverse value of t pcr (which is 5450.68cells/s) is higher than the value of l pcr . the polu parameter delta (t pcr /t z ) is 297.21006. the cell cycle time t z is 617.28ns. the value of the lsb of delta is 2 -11 . herewith delta is encoded as 949ae h (= delta*2 11 , round down). the polu parameter w min ( t pcr /t z ) is 1215 if the cdvt is 750s at the uni. the encoding of the w min is 25f800 h (= w min *2 11 ). the configuration and parameter values for polu are as follow: 7deoh ([dpsohiru&rqiljxudwlrq the user cells are policed in the upper branch at lb1. discarding is enabled. the lb2 is disabled. the oam and rm cell types are not policed (transparent bypass). the lb3 can be optionally used for a separate oam policing. delta 3 and w min3 is derived from the pcr (oam) and t pcr(oam) values as shown above. the fxseg_u/d and/or fxe2e_u/d has to be set to 01 and the dis_u/d to 00. 6huylfh 3dudphwhuv iru(&lufxlw(pxodwlrq zlwk m v&'97dwwkh 81, 32/8&rqiljxudwlrq3dudphwhuv dbr pcr (0+1) t pcr(0+1) mode = 3 delta 1 = 949ae h w min1 = 25f800 h delta 2 = 0 w min2 = 0 delta 3 = 0 w min3 = 0 user_u/d = 10 f4rm_u/d = 00 f5rm_u/d = 00 f4seg_u/d = 00 f4e2e_u/d = 00 f5seg_u/d = 00 f5e2e_u/d = 00 dis_u/d = 01 m pcr pcr sig 1023 ------------------- - ? ?? 2 log 9 + = k pcr pcr sig 2 m pcr 9 C --------------------- - 512 C =
3;%( data sheet 2-46 08.2000 )xqfwlrqdo'hvfulswlrq 7udiilf0hdvxuhphqw8qlwiruxsdqggrzqvwuhdpgluhfwlrq the alp provides several traffic counters which can be used for accounting management (i.e. billing), for observation of the atm cell traffic behavior as well as for protocol monitoring measurement. traffic measurement is implemented at vcc, vpc and port level and fulfills the bellcore requirements gr-1248-core. the alp supports a minimum measurement interval of at least 44 minutes. the connection specific data as well as the traffic measurement data of the vccs, transparent and terminated vpcs are stored in the external connramup and connramdo rams. the port specific traffic measurement data are stored in the internal port table of the alp. after the address reduction the connection specific data and traffic measurement counter values are read from the external connection ram which is addressed via the lci value of the cell. for the upstream direction 8 dwords and for the downstream direction 7 dwords are read. the data structure is depicted in iljxuh . )ljxuh 'dwd6wuxfwxuhlqwkh([whuqdo&2115$083dqg&2115$0'25$0iruhdfk /&,9doxh subsequently both the traffic measurement (tic, tic0 in upstream and toc, toc0 in downstream) and policing (tdc0, tdc1 and ttc) counter values are updated with respect to the identified cell type for vcc and transparent vpc. additionally the alp reads from a second lci2 address the traffic measurement (vp_tic, vp_tic0 in upstream and vp_toc, vp_toc0 in downstream) counter values for the terminated vpcs. the lci2 is stored in the connection specific data addressed by the lci. the value of the lci2 is identical for all vccs which are transported in a common terminated vpc. after counter update all counter values are stored back in the external connramup and connramdo. for transparent vpcs it is possible to set lci2 to the value of lci. herewith the counter values ti/ocs and vp_ti/oc are lci_n ht_cd_up lci_m tic ht_cd_do_l tic0 ht_cd_do_h tdc1 mc_ptr tdc0 toc ttc toc0 vp_tic vp_toc vp_tic0 vp_toc0 connramup connramdo these are the connection specific data these counter values are updated with the lci addressing and correspond to the vcc and transparent vpc these policing counter values are updated with the lci addressing and correspond to the vcc and transparent vpc. these counter values are updated with the lci2 addressing and correspond to the terminated vpc.
3;%( data sheet 2-47 08.2000 )xqfwlrqdo'hvfulswlrq identical and the memory usage is reduced. the cell types and the corresponding name of counters are given in wdeoh for the vcc level and in wdeoh for the vpc level. two kind of traffic measurement counters are implemented for the port level. the first group of counters is fixedly allocated to the utopia ports 0..15 and counts the total number of incoming cells in upstream direction (potic, see vhfwlrq page 79) and the total number of outgoing cells in downstream direction (potoc, see vhfwlrq page 82). the fixed counters can be enabled or disabled via register endpotc (see vhfwlrq page 103) for upstream direction and register enpotoc (see vhfwlrq page 105) for downstream direction. the second group consists of eight countersets for each direction, which can be flexibly allocated to the ports 0..23. in upstream direction the countersets contain four counters, named poti_ci, pdc_ci, poticn_ci and poticor_ci. potic_ci counts the total number of incoming cells at port i. pdc_ci summarizes the total number of discarded cells due to unallocated pn/vpi/vci at port i. the total number of incoming cells with a non-zero gfc field at port i is counted by poticn_ci. and poticor_ci shows the number of total incoming oam/ rm cells at port i. these counters are stored in the traffic measurement ram, which is also called port table. the structure of the port table is shown in vhfwlrq page 79. the pn allocation to the counterset and their configuration is controlled by registers portconfn_u ( vhfwlrq page 102) for upstream direction. in downstream direction, the countersets include two counters, which are potoc_ci and potocor_ci. using potoc_ci the total number of outgoing cells at port i is available and potocor_ci counts the total number of outgoing oam/rm cells at port i. the pn allocation in downstream direction and the configuration of the countersets is done via registers portconfn_d ( vhfwlrq page 104). it is selectable for each counterset, which counter should be enabled or disabled. if two or more countersets are allocated to one port, only the counterset with the lowest number is active. this case is given after reset, because at this event all eight countersets are assigned to port 7deoh 7udiilf0hdvxuhphqwdw9&&/hyho &hoo7\sh &rxqwhudqg5$0 total incoming cells tic in connramup total outgoing cells toc in connramdo total incoming cells with clp=0 tic0 in connramup total outgoing cells with clp=0 toc0 in connramdo total discarded incoming cells due to upc/ npc with clp=1 tdc1 in connramup total discarded incoming cells due to upc/ npc with clp=0 tdc0 in connramup total tagged incoming cells due to upc/npc ttc in connramup 7deoh 7udiilf0hdvxuhphqwdw93&/hyho &hoo7\sh &rxqwhudqg5$0 total incoming cells vp_tic in connramup total outgoing cells vp_toc in connramdo total incoming cells with clp=0 vp_tic0 in connramup total outgoing cells with clp=0 vp_toc0 in connramdo
3;%( data sheet 2-48 08.2000 )xqfwlrqdo'hvfulswlrq number 0. the cell types and the corresponding name of counters are given in wdeoh for the port level. an overview of the traffic measurement capability is depicted in iljxuh . )ljxuh 7udiilf0hdvxuhphqwdwwkh3ruw93&dqg9&&/hyho the traffic measurement can be activated by a sw flag en_traf_meas_up/do in the external connramup/do for each connection at the vcc and vpc level. at the port level it is configurable with the sw flag oam_cnt_u ( vhfwlrq page 102) in the alp register whether the tm counter poticor counts the oam or rm cells in upstream direction. furthermore the sw flag inc_timc_ssd ( vhfwlrq page 75) in the connramup define per connection whether this specific connection is counted. for the downstream direction the sw flag oam_cnt_d ( vhfwlrq page 104) in the alp register selects whether the tm counter potocor_ci counts the oam, rm or both discarded f5rm and pti (111) cells. the sw flags inc_tomc_ssd and inc_tof5rmc_ssd ( vhfwlrq 7deoh 7udiilf0hdvxuhphqw&rxqwhuvdw3ruw/hyho &hoo7\sh q>@iruhdfkfrxqwhuvhw &rxqwhuriwkh3ruw wdeoh total incoming cells due to unallocated pn/vpi/vci at port number defined in cnt_portn_u pdc_cn total incoming cells with non-zero gfc-field at port number defined in cnt_portn_u poticn_cn total incoming cells at port number defined in cnt_portn_u potic_cn total incoming oam or rm cells enabled per connection at port number defined in cnt_portn_u poticor_cn total outgoing cells at port number defined in cnt_portn_u potoc_cn total outgoing oam, rm or discarded f5rm cells enabled per connection at port number defined in cnt_portn_u potocor_cn 7udiilf0hdvxuhphqw3urfhvvru 1 24 port mux port specific counting of total incoming and outgoing cells total incoming cells with non-zero gfc field* total discarded incoming cells due to unallocated pn/vpi/vci* total incoming and outgoing oam/rm cells* * only for 8 ports vpc mux 1n vcc mux 1m virtual path specific counting of total incoming and outgoing cells total incoming and outgoing cells with clp = 0 enable / disable traffic measurement according to bellcore gr-1248-core virtual connection specific counting of total incoming and outgoing cells total incoming cells with clp = 0 total discarded incoming cells due to upc/npc with clp = 0 and clp = 1 total tagged incoming cells due to upc/npc
3;%( data sheet 2-49 08.2000 )xqfwlrqdo'hvfulswlrq page 77) in the connramdo define per connection whether this specific connection is counted in the potoc_ci and potocor_ci. herewith it is possible that one, some or all connections running on this port are counted. 7udiilf0hdvxuhphqwgdwdwudqvihuyld'0$ the alp supports a dma mechanism for fast data transfer of the connection specific counters at vcc and vpc level from connramup and connramdo to the microprocessor ram. the alp internal condition for a dma access is the occurence of an empty cycle that means no cell is available at the utopia receive interface. this has to be considered for system design (amount of user cells, utopia frequency, core frequency of alp). in downstream direction it is possible to force empty cycles by setting bit force_ec_d in register conut3 to generate backpressure to the preceding asic that stores the cells in its buffer queues (see vhfwlrq page 108). )ljxuh '0$iru)dvw7udiilf0hdvxuhphqw'dwd7udqvihu in upstream direction it has to be considered in the system design (utopia frequency, alp frequency and atm user cell rate) that there is a trade off between switch port usage and microprocessor access time to connramup and connramdo. for phy devices up to stm- 4 equivalent there is no restriction for the alp as each 10th cell will be an empty cell. for the alp this means no cell at the utopia interface. due to the fact that idle cells can also be transmitted in the stm-4 signal but not via the utopia interface the number of empty cells will be higher. the empty cell will be used for configuration and dma access. problems will occur only if the utopia interface is overbooken. the relationship between link rate, switch port rate and user cell rate is shown in iljxuh . lci = 0 lci = 16383 lci_min lci_max ht_cd_up tic tic0 tdc0 ttc vp_tic tdc1 vp_tic0 lci_n lci = 0 lci = 16383 lci_min lci_max ht_cd_do_l ht_cd_do_h mc_ptr toc0 vp_toc toc vp_toc0 lci_m dma up connramup connramdo dmar 015 dma do microprocessor ram alp 031 these 7 counters are read with 1 dma access these 4 counters are read with 1 dma access
3;%( data sheet 2-50 08.2000 )xqfwlrqdo'hvfulswlrq )ljxuh 5hodwlrqvklsehwzhhq/lqn5dwh6zlwfk3ruw5dwhdqg$708vhu&hoo5dwh the dma is controlled by three registers called dma_min ( vhfwlrq page 136), dma_max ( vhfwlrq page 136) and dconr ( vhfwlrq page 130) . dmamin and dmamax determine the range of lcis which counters are read to the microprocessor ram via dma. the dma is performed lci-wise with one dma access transferring all counters of one lci. the order of the dma accesses is from lci_min to lci_max. using bit dma_ud in register dconr the direction (up- or downstream) can be selected. by setting bit dma_start in the same register the mircoprocessor can start the dma. this bit is reset by the alp when the dma process has finished, therefore the microprocessor has to poll this bit until it is reset. after the dma access is done the microprocessor can get the counter values by reading the dmar register ( vhfwlrq page 132). after the bit dma_start of the dconr register is set, the write access to dmamin, dmamax and dconr except the dma_start bit is blocked. this guarantees that the configuration of dma cannot be changed during the complete dma cycle. the microprocessor can stop the dma by clearing dma_start. as a result the dma is finished and the dma processor of the alp is reset. the dma for a single lci_n occures during an empty cell cycle. the transfer between alp and microprocessor is controlled by the hw pins mpdreq and mpdack . mpdreq is active after all connection specific traffic measurement counters are written into the dma buffer of the alp and becomes inactive after the contents of the dma buffer are read out by the microprocessor via the dmar register. the next dma cycle for lci_n+1 is initiated either by the mpdack signal from the microprocessor or by the alp. the delay time between two consecutive dma depends on the occurrence of the next suitable empty cell cycle. this can lead to a large load on the microprocessor bus if enough empty cycles are available so that the processes with lower priority than the dma are blocked. therefore the minimum delay between two dma accesses can be configured by the dma_wait bit in register testr ( vhfwlrq page 133) and by the dma_delay variable in the dconr register. using the reset bits ctrn_res in the conr register the microprocessor can reset each counter value separately for the specified lcis. when the values are read to the dma buffer, the counters are reset. a guide line for dma is given in chapter 4. stm-4 phy-device stm-4 link rate is 622.08mbit/s stm-4 atm-layer-device utopia level 2 interface 16bit utopia level 2 interface 16bit user cells idle cells soh poh payload is atm cells only user cell transfer physical link bitrates: stm-4 = 622.08mbit/s payload = 599.04 mbit/s switch port bitrate: utopia = 686.88mbit/s physical implementation: only user cell transfer signal structure:: stm-4 = utopia load of 0.872 => each 10th cell is an emty cell or even better as no idle cell is transmitted via utopia
3;%( data sheet 2-51 08.2000 )xqfwlrqdo'hvfulswlrq 8723,$)xqfwlrqdolw\ the alp provides an utopia level 2 interface with multiplexed status polling according to [2] at the phy and the atm side. at the phy side the receive and transmit utopia interface has master capability. at the atm side the hardware pins rxms and txms select for the receive and transmit direction of the utopia interface whether it acts as an utopia master or slave (see iljxuh ). )ljxuh 8723,$,qwhuidfh the multiplexed status polling of the alp supports up to 4 independent clav/enable line pairs. this has the advantage that all phys can be polled during one cell cycle. additionally 4 utopia level 1 devices with a tristate rx-data bus can be supported by the alp. during one cell cycle up to 12 utopia addresses are scanned which gives a maximum capacitance of 48 ports with the 4 clav/enable line pairs. the alp supports 24 ports. an example for the alp configuration $/3 receive upstream master transmit downstream master transmit upstream master/slave receive downstream master/slave 8svwuhdp&hoo)orz 'rzqvwuhdp&hoo)orz atm (a) phy (p) phy (p) atm (a) 3+< 6lgh $70 6lgh rxdatu(15:0) rxsocu rxprtyu rxclavu(3:0) rxenbu(3:0) rxadru(3:0) utphyclk txdatd(15:0) txsocd txprtyd txclavd(3:0) txenbd(3:0) txadrd(3:0) utatmclk rxdatd(15:0) rxsocd rxprtyd rxclavd(3:0) rxenbd(3:0) rxadrd(3:0) txdatu(15:0) txsocu txprtyu txclavu(3:0) txenbu(3:0) txadru(3:0) txms rxms
3;%( data sheet 2-52 08.2000 )xqfwlrqdo'hvfulswlrq with 4 phy-devices connected with the 4 clav/enable line pairs is given in iljxuh . in this example 24 lines, each with a data transfer rate of 25.6 mbit/s result in a total throughput of 614.4 mbit/s, are supported by the alp. )ljxuh 8723,$,qwhuidfh&rqiljxudwlrqiru 3+ 3;%( data sheet 2-53 08.2000 )xqfwlrqdo'hvfulswlrq )ljxuh 3rvvleoh$gguhvv*urxs&rqiljxudwlrqv herewith the alp supports: ? 4 phy devices without utopia address (utopia level 1) or with up to 6 port addresses ? 3 phy devices with up to 8 port addresses ? 2 phy devices with up to 12 port addresses the poll cycle is identical in all modes, i.e. the address lines output all addresses from 0 to 11 in ascending order during one cell cycle. for each address output at the address lines all phys are polled. the polling order is shown in wdeoh . if the address is greater than the number of multiports at the device, the associated clavx is set to 0. the real multiport number depends on the selected mode. the polling sequence of the next polling cycle depends on the current transmitting phy, e.g. if port 5 is the current transmitter the next polling sequence starts in 4x6 mode with port 11. 7deoh 3roolqj2ughuri3ruw1xpehuv 0rgh 3roolqj2ughuri3ruwqxpehuv 4x6 0 6 12 18 1 7 13 19 2 8 14 20 3 9 15 21 4 10 16 22 5 11 17 23 3x8 0 8 16 1 9 17 2 10 18 3 11 19 4 12 20 5 13 21 6 14 22 7 15 23 2x12 0 12 1 13 2 14 3 15 4 16 5 17 6 18 7 19 8 20 9 21 10 22 11 23 1x4 01234 support for up to 24 ports scanned round robin 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 11 12 19 20 23 21 22 0 address -, clav 0 address -, clav 1 address -, clav 2 address -, clav 3 address 0, clav 0 address 1, clav 0 address 2, clav 0 address 3, clav 0 address 4, clav 0 address 5, clav 0 address 0, clav 1 address 1, clav 1 address 2, clav 1 address 3, clav 1 address 4, clav 1 address 5, clav 1 address 0, clav 2 address 1, clav 2 address 2, clav 2 address 3, clav 2 address 4, clav 2 address 5, clav 2 address 0, clav 3 address 1, clav 3 address 2, clav 3 address 3, clav 3 address 4, clav 3 address 5, clav 3 address 0, clav 0 address 1, clav 0 address 2, clav 0 address 3, clav 0 address 4, clav 0 address 5, clav 0 address 6, clav 0 address 7, clav 0 address 2, clav 1 address 3, clav 1 address 4, clav 1 address 5, clav 1 address 0, clav 1 address 1, clav 1 address 6, clav 1 address 7, clav 1 address 2, clav 2 address 3, clav 2 address 4, clav 2 address 5, clav 2 address 0, clav 2 address 1, clav 2 address 6, clav 2 address 7, clav 2 address 0, clav 0 address 1, clav 0 address 2, clav 0 address 3, clav 0 address 4, clav 0 address 5, clav 0 address 6, clav 0 address 7, clav 0 address 10, clav 0 address 11, clav 0 address 0, clav 1 address 1, clav 1 address 8, clav 0 address 9, clav 0 address 2, clav 1 address 3, clav 1 address 6, clav 1 address 7, clav 1 address 8, clav 1 address 9, clav 1 address 4, clav 1 address 5, clav 1 address 10, clav 1 address 11, clav 1 configuration for 4 phy-devices with utopia level 1 configuration for 4 phy-devices with 6 multiports configuration for 3 phy-devices with 8 multiports configuration for 2 phy-devices with 12 multiports
3;%( data sheet 2-54 08.2000 )xqfwlrqdo'hvfulswlrq depending on the selected mode different clav/enable lines and addresses are associated to a special port. as an example for port number 9, the following table shows that 3 different addresses and clav/enable lines are activated for 4 different address group configurations. the configuration of 4 utopia level 1 interfaces is not possible as the port number 9 is not in the port address range 0 to 3.: )ljxuh depicts the address group configuration at the phy and atm side of two alps connected to one aop. this is a possible scenario for access network system architecture. as it can be seen it is not necessary that the address group configuration is identical at the phy and the atm side of the alp, aop or abm. however it is required that the port number range from 0 to 23 is shared by the number of alps and each port number is used only once. the sw is responsible that the used port number range is covered by the address group configuration. )ljxuh ([dpsohridq$gguhvv*urxs&rqiljxudwlrq the alp has a shared memory buffer of 64 cells for the downstream direction. up to 24 queues share the memory buffer. the queue number range of 0 to 23 corresponds to the port number range. the addressing of the ports or queues occurs via the utopia address and the clav/ enable pairs which are converted into the port number depending on the address group configuration. one threshold which is identical for all queues can be adjusted via the sw configuration bits ut_thresh in register conut3. herewith a port specific backpressure signal can be given to the utopia receive interface in downstream direction if the filling level of the queue is greater than or equal to the queue threshold. the error indication which is related to the utopia interface is given in register isr0. an interrupt indication bov is generated if the 63rd cell is stored in the shared buffer and an interrupt indication qov is generated if one or more queues have an overflow status. a detailed queue overflow indication is provided in the 7deoh ([dpsohiru3ruw1xpehu &rqiljxudwlrqriwkh8723,$,qwhuidfh utopia address 3 1 9 - clav/enable line 1 1 0 - 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 11 12 19 20 23 21 22 0 clav 0 clav 1 clav 2 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 11 12 19 20 23 21 22 0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 11 12 19 20 23 21 22 0 clav 0 clav 0 clav 1 clav 3 clav 3 clav 1 clav 2 clav 2 alp alp clav 0 clav 3 clav 1 clav 2 aop clav 0 clav 1 clav 0 clav 1 clav 0 clav 3 clav 1 clav 2
3;%( data sheet 2-55 08.2000 )xqfwlrqdo'hvfulswlrq register ut_qo1/2 (see sdjh ) by the indication bits qov_i. parity errors at the phy side of the receive and transmit utopia interface generate an interrupt ut_parerr_u/d. the occurrence of a start of cell error or cell length error at the receive utopia interface in up- and downstream direction generates an interrupt ut_cellerr_u/d. an overflow at the utopia receive fifo in upstream direction is detected via the interrupt flag utrxfifo_ov_u. for diagnosis the alp has 4 protocol monitoring register sets prmonr0..3x_u for upstream direction and one protocol monitoring register set prmonrx_d for downstream direction to buffer the last discarded cell due to atm cell header error. an atm cell header error occurs if either an error in the external address reduction circuit came is indicated or if a parity error appears at the connramdo interface. for both cases an interrupt cam_err and ram_parerr_d indication is given in register isr1. each register set can be enabled by sw flags en0_u, en1_u, en2_u, en3_u and en_d in the register headcapen (see sdjh ). the 4 registers for upstream direction are related to the 4 clav groups. in downstream direction only one register set is related to all clav groups. an indication is given by the interrupt bit pmo_hlog in register isr0 if one or more cells are stored in the prmonr registers. a detailed status indication for each prmonr register is given by the sw flags pmo_hloh0_u, pmo_hloh1_u, pmo_hloh2_u, pmo_hloh3_u and pmo_hloh_d in register statr (see sdjh ). the indication bit is reset after the complete read out of the cell header by the microprocessor.
3;%( data sheet 2-56 08.2000 )xqfwlrqdo'hvfulswlrq 2$0)xqfwlrqdolw\ the alp supports together with the external microprocessor an oam light function for low cost applications where no aop is used. the oam light function covers the ais, rdi, cc, cca and lb handling for f4 and f5 flow according itu [7] and bellcore [8]. not supported are the oam functions for connections quality measurement (pm). the oam light function can be disabled by the sw flag oam_en in the register dct/uct_config (see page 123) for up- and downstream direction if the aop is used. in this mode all oam cells are forwarded to the aop without crc-10 checking. in the oam light mode the type of the connection point and the consequent oam cell processing can be defined and the crc-10 checking and generation is performed for the extracted and inserted oam cells. for the f4 and f5 oam flow the connection point can be configurated via sw bits f4/f5pt_cfg in the connramup/do ram as intermediate point ip, originating segment point osp, originating end-to-end point oep, terminating segment point tsp and terminating end-to-end point tep for each connection. additionally a connection point can be also defined as not existing. the following )ljxuh depicts the different types of connection points and the corresponding possible segment and end-to-end flows for f4 and f5 oam flow. )ljxuh 7\shvri&rqqhfwlrq3rlqwviru)dqg)2$0)orz the consequent actions for the oam cells at the connection points can be configurated via sw. at the termination points it is configurable for each defined and undefined oam cell type whether it is discarded or dropped. the corresponding sw flags ar/cc/lb_disc in the alp register dct/uct_config has an influence on all connections. )ljxuh &rqvhtxhqw$fwlrqvrq2$0&hoov at the intermediate points it is configurable whether the ais, rdi, cc and cca cells are copied or forwarded and whether the lb cells are dropped or forwarded. the corresponding sw flags ar/cc_ip_copy and lb_ip_drop in the connramup/do are connection specific. segment 1 osp end-to-end tep oep ip tsp tsp osp segment 2 ip segment 3 osp tsp ip 12345678 m 3,qwhuidfh alp utopia utopia m 3,qwhuidfh alp utopia utopia forward discard drop alp utopia utopia m 3,qwhuidfh copy alp utopia utopia m 3,qwhuidfh
3;%( data sheet 2-57 08.2000 )xqfwlrqdo'hvfulswlrq for each connection point only one f4 and one f5 connection point can be defined by the f4pt_cfg and f5pt_cfg bits. this has an influence to the alp configuration if two adjacent segment boarders are located at the same network node. this case is illustrated in the following )ljxuh and where in network node 3 a segment is terminated and the next is originated. for a transparent and terminated vp the termination point vp-tsp/ep is configured at the ingress and the originating point vp-osp/ep is configured at the engress side of the node. a configuration of a termination and origination for the same f4 or f5 flow at one node side is not possible. )ljxuh shows a network node with a switching fabric and several alps at the ingress and engress side of the network node. )ljxuh shows a low cost network node with a single alp and no additional switching fabric which is used as an atm-multiplexors for up to 622mbit/s throughput in access networks. )ljxuh &rqiljxudwlrqriwkh&rqqhfwlrq3rlqwviru1rghvzlwk6zlwfklqj)deulf segment 1 segment 2 subscriber lines service node line vp-tep vc-ip service node line vp-oep vc-osp vp-tsp vc-tsp asm switching fabric alp alp alp 135 tsp osp vp-osp
3;%( data sheet 2-58 08.2000 )xqfwlrqdo'hvfulswlrq )ljxuh &rqiljxudwlrqriwkh&rqqhfwlrq3rlqwviru1rghvzlwkrxw6zlwfklqj)deulf the normal oam processing of the alp is the insertion of oam cells via the insertion buffer by the microprocessor at the oep and osp. at the ip the oam cell is forwarded without any processing and is automatically dropped via the extraction buffer to the microprocessor at the tep and tsp. with the connection specific flags ar_ip_copy and cc_ip_copy the ais, rdi, cc and cca cells are copied to the microprocessor for monitoring purpose at the ip. the oam flow is depicted in )ljxuh . with the connection specific flags lb_ip_drop the lb cells are dropped to the microprocessor. after the lb processing the lb cell is reinserted. the dropping is necessary as the microprocessor has to check the lb-identification number which is located at the payload of the lb cell. )ljxuh 3urfhvvlqjiru$,65',&&dqg&&$2$0&hoov segment 1 segment 2 subscriber lines alp 135 tsp osp vp-osp service node line vp-tep vp-tsp vp-oep vp-oep vc-tsp vc-osp alp utopia m 3,qwhuidfh alp alp alp utopia ins. extr. utopia utopia utopia utopia m 3,qwhuidfh ins. extr. ais/rdi/cc copy =0 ais/rdi/cc copy =1 oep or osp ip ip tep or tsp utopia m 3,qwhuidfh ins. extr. m 3,qwhuidfh ins. extr. utopia
3;%( data sheet 2-59 08.2000 )xqfwlrqdo'hvfulswlrq the )ljxuh depicts the oam flow processing for lb cells. with the cell type specific flags ar_disc, cc_disc, lb_disc and undef_disc in the register dct/uct_config the ais, rdi, cc, cca, lb and undefined oam cells can be discarded at the tep and tsp in order to minimize the processor load in failure case. )ljxuh 3urfhvvlqjiru/%2$0&hoov a check of error detection code (crc-10) is performed by the utopia receive interface in up- and downstream direction for every oam cell and an edc error is indicated by the edc_err_u/d bits in the isr1 register. the false oam cells are discarded or forwarded according to the configuration by the crc_nodisc bit in the dct/uct_config register. the oam cells and the information on the identified cell type is extracted via the receive cell buffer register rxr (see page 97) to the microprocessor. the oam cell has a 56byte format which includes the cell type information in word 27 bit(15:10) as depicted in )ljxuh . the receive cell buffer stores up to 12 cells and an indication bit rxr_ustr in isr1 register is set until all cells are read out by the microprocessor and is afterwards reset automatically by the alp. )ljxuh &hoo)rupdwh[wudfwhgiurp$/3wr0lfursurfhvvru the insertion of oam cells is performed via the transmit cell registers 0 to 26 (see page 94) by the microprocessor. the cell format is 56 bytes as in receive direction however the cell type field in word 28 is not used. an e bit in udf2 (5) controls the generation of the crc-10 for outgoing oam cells at the utopia transmit interface. for inserted non-oam cells the crc-10 generation can be disabled. for oam/rm cells passing the alp no further crc-10 is generated. the cell structure is depicted in )ljxuh for the alp upstream direction without header translation. the other scenario are described in the txr2 register description (see page 95). the insertion of the cell from the transmit cell buffer into the cell stream is initiated bit:1514131211109876543210 0 header_1 header_2 1 header_3 header_4 2 udf1 udf2 3 payload_1 payload_2 4 payload_3 payload_4 :: : 26 payload_47 payload_48 27 celltype(5:0) unused word alp utopia m 3,qwhuidfh alp alp alp utopia ins. extr. utopia utopia utopia utopia oep or osp m 3,qwhuidfh ins. extr. ip ip tep or tsp m 3,qwhuidfh ins. extr. lb drop = 0 lb drop = 1 utopia utopia ins. extr. m 3,qwhuidfh
3;%( data sheet 2-60 08.2000 )xqfwlrqdo'hvfulswlrq by the start_tr bit in txr_config register (see page 97). )ljxuh &hoo)rupdwlqvhuwhgiurp0lfursurfhvvrulqwrwkh$/38svwuhdp'luhfwlrq zlwkrxw+hdghu7udqvodwlrq the following table gives an overview of the consequent actions on the oam and rm cells in dependence on the configuration of the connection points at the f4 and f5 flow. if no connection point is defined (f4-no and f5-no) no useful action is guaranteed. in this case the f4 configuration has a higher priority than the f5 configuration. . dro: dropping; dis: discarding; f4/f5: f4/f5 end-to-end cell; f4s/f5s: f4/f5 segment cell; bit:1514131211109876543210 0 header_1 header_2 1 header_3 header_4 2 lci hk unused e pnut 3 payload_1 payload_2 4 payload_3 payload_4 :: : 26 payload_47 payload_48 27 unused unused word 7deoh 5hfrpphqghg)dqg)&rqiljxudwlrqdqg&rqvhtxhqw$fwlrqrq2$0dqg 50fhoov &rqqhfwlrq3rlqw &rqvhtxhqw$fwlrqv f4 f5 oam rm, f5res f4-no f5-no no action no action f4-no f5-oep dis-f4 & dis-f5 no action f4-no f5-osp dis-f4 & dis-f5s no action f4-no f5-ip dis-f4 no action f4-no f5-tsp dis-f4 & dro-f5s no action f4-no f5-tep dis-f4 & dro-f5 no action f4-oep no dis-f5 no action f4-oep f5-oep dis-f4 & dis-f5 no action f4-oep f5-osp dis-f4 & dis-f5s no action f4-oep f5-ip dis-f4 no action f4-oep f5-tsp dis-f4 & dro-f5 no action f4-osp dont care dis-f4s & f5=user f5=user f4-ip dont care f5=user f5=user f4-tsp dont care dro-f4s & f5=user f5=user f4-tep f5-no dro-f4 & dis-f5 no action f4-tep f5-osp dro-f4 & dis-f5s no action f4-tep f5-ip dro-f4 no action f4-tep f5-tsp dro-f4 & dro-f5s no action f4-tep f5-tep dro-f4 & dro-f5 no action
3;%( data sheet 2-61 08.2000 )xqfwlrqdo'hvfulswlrq in downstream direction the discarding of the house keeping cells for proprietary oam functions and of both the f5rm and f5res (pti=111) at tep can be enabled or disabled by the hk_dis and f5rm_disc flags in the dct/uct_config register. the f5rm and f5res discard function is needed if the phy device cannot handle these cell types. 3urjudppdeoh&hoo)lowhu)xqfwlrqdolw\ the alp has two fully programmable and maskable cell type filters for up- and downstream direction that can be configurated to forward, discard, drop or copy the filtered cell. each programmable cell filter can be enabled or disabled via the sw flag pcf1/2_en and the corresponding actions on the filtered cell are configurated via sw bits pcf1/2_act in the dct/ uct_config register respectively. the data format of the cell filter and the cell mask structure is written from the microprocessor via the wdr0-3 (see page 69) write registers to the cell filter. the cell filter compares bit by bit the first seven bytes of each cell with the seven bytes of the unmasked cell filter. masked bits of the cell filter are not compared. the following 7deoh shows the matching conditions for the cell filter. the cell filter match if the comparison of all bits of the extended cell header matches. after the matching the corresponding action on the filtered cell (forward, discard, drop or copy) depends on the status of the crc-10 check and the sw flag crc_1/2_nodisc in register dct/ uct_config. the action on the filtered cell is performed if no crc-10 failure occur or if the discarding of cells with crc-10 failure is disabled by the sw flag crc_1/2_nodisc which is recommended for all user cells extracted by the cell filter. the reason is that user cells have normally no crc-10. the programmable cell filter 1 and 2 as well as the cell type filter for oam light has different priorities which influence the cell processing if all three cell filters match for the same incoming cell. the priority is as follow: ? programmable and maskable cell filter 1 has highest priority if matching (prio 1) ? programmable and maskable cell filter 2 has medium priority if matching (prio 2) ? cell filter for other cells as oam cell has lowest priority if matching (prio 3) the filter with the highest priority determines the cell processing. the sw is responsible for the reasonable programming of the cell filters because the priority mechanism can lead to misinserted cells in case of oam light. &dxwlrq : at a f4 tep the oam filter will drop the f4 end-to-end oam cell if oam light is enabled. a programmable cell filter configurated for the same f4 end-to-end oam cell with the cell action ?forward has a higher priority than the oam cell filter so that this cell is forwarded. this leads to a misinserted oam cell. 7deoh 7uxwk7deohiru&hoo)lowhu &rpsdulvrqri&hoo+hdghu%lw[\zlwk 3urjudppdeoh&hoo)lowhu%lw[\ 3urjudppdeoh&hoo 0dvn%lw[\ 0dwfkiru%lw[\ dont care 0 yes cell header bit(x,y) = cell filter bit(x,y) 1 yes cell header bit(x,y) 1 cell filter bit(x,y) 1 no
3;%( data sheet 2-62 08.2000 )xqfwlrqdo'hvfulswlrq the extended cell header format checked by the programmable cell filter is depicted in )ljxuh . the payload_1 contains informations on the oam type (ais, rdi, cc, cca, lb or undefined). )ljxuh &hoo)rupdwfkhfnhgiru3urjudppdeoh&hoo)lowhu bit:76543210 1 up: gfc/vpi; down: lci up: vpi; down: lci 2 up: vpi; down: lci vci 3vci 4vci pticlp 5 udf1 6 udf2 7 payload_1
3;%( data sheet 2-63 08.2000 )xqfwlrqdo'hvfulswlrq &rqiljxudwlrqri$/3yld0lfursurfhvvru the alp is configurated via the write and read registers wdr and rdr (see page 69) by the microprocessor. the wdr and rdr registers consist of 11 dwords (32bit) which are connected with the 16 bit data bus of the microprocessor interface. the cmr register (see page 111) controls the access of the microprocessor to the external rams (poluram, connramup and connramdo), the external address reduction circuit came, the internal port tables for traffic measurement and the internal programmable cell filters 1 and 2. the address of the rams, came and port table is transferred via the adr register (see page 128). for the programming of the poluram all 11 dwords of the wdr and rdr registers are used. for the connramup only 8 dwords, for the connramdo only 7 dwords, for the port tables only 8 dwords and for the programmable cell filter only 4 dwords are used. the lci address of all rams and the port table address is written into the adr register. the addressing of the programmable cell filters is controlled directly by the cmr. the came contents is transferred via the camadr register and the lci address via the adr register. additionally a read modify write mask register rmw (see page 122) is implemented for the case that only parts of the dwords shall be changed. the start of the specific request is initiated by the sw flag streq which is reset by the alp when the command is finished. the alp registers are programmed as usual. the structure of register and the address and data flow for the access to the internal and external rams is depicted in )ljxuh . )ljxuh $ffhvvwrwkh,qwhuqdodqg([whuqdo5$0v adr address register wdr/rdr and camadr for write/read transfer rmw mask register mask filter port table up- and downstream address m p data selection programmable cell type filter 1 downstream programmable cell type filter 2 upstream programmable cell type filter 1 downstream programmable cell type filter 1 upstream came (external arc) poluram connramup connramdo 0 2 3 4 5 6 7 1 0 2 3 4 5 6 7 1 $/3 cmr control register
3;%( data sheet 3-64 08.2000 5hjlvwhu'hvfulswlrq 5hjlvwhu'hvfulswlrq 2yhuylhzriwkh$/35hjlvwhu 7deoh $/35hjlvwhuv2yhuylhz dggu kh[ uhjlvwhu ghvfulswlrq uhvhw ydoxh 3 vhh sdjh 5hdg:ulwh5hjlvwhuv 00 wdr0l write register 0 undef. r/w 69 01 wdr0h write register 0 undef. r/w 69 ... ... ... 14 wdral write register a undef. r/w 69 15 wdrah write register a undef. r/w 69 16 rdr0l read register 0 undef. r/w 70 17 rdr0h read register 0 undef. r/w 70 ... ... ... 2a rdral read register a undef. r/w 70 2b rdrah read register a undef. r/w 70 3ruw&rqiljxudwlrq5hjlvwhuv 2e uniportl port configuration (uni) 0000 r/w 89 2f uniporth port configuration (uni) 0000 r/w 89 &$0('dwd5hjlvwhuv 32 camadrl data which is to store into the came 0000 r/w 90 33 camadrh data which is to store into the came 0000 r/w 90 32/8&rqiljxudwlrq5hjlvwhu 36 p_conrl polu configuration register 00ff r/w 91 37 p_conrh polu configuration register 0000 r/w 92 9huvlrq5hjlvwhu 40 verl low/high word of version numberv 9063 r 93 41 verh low/high word of version numberv 523b r 93
3;%( data sheet 3-65 08.2000 5hjlvwhu'hvfulswlrq 7udqvplw5hjlvwhuv&hoo,qvhuwlrq%xiihu7;5&rqiljxudwlrq5hjlvwhu 50 txr0 transmit cell register 0 0000 r/w 94 51 txr1 transmit cell register 1 0000 r/w 94 52 txr2 transmit cell register 2 0000 r/w 95 53 txr3 transmit cell register 3: payload 0/ payload 1 0000 r/w 96 ... ... ... ... 6a txr26 transmit cell register 26: payload 46/ payload 47 0000 r/w 96 6b txr_config configuration of transmit cell buffer 0000 r/w 97 5hfhlyh5hjlvwhu5hfhlyh&hoo%xiihu 70 rxr receive cell buffer access undef. r 97 +hdghu&dswxuh3urwrfro0rqlwrulqj5hjlvwhu6hw8svwuhdp 72 prmonr0a_u protocol monitoring buffer 0 upstream 0000 r 99 73 prmonr0b_u protocol monitoring buffer 0 upstream 0000 r 99 74 prmonr0c_u protocol monitoring buffer 0 upstream 0000 r 100 ... ... ... 7b prmonr3a_u protocol monitoring buffer 3 upstream 0000 r 99 7c prmonr3b_u protocol monitoring buffer 3 upstream 0000 r 99 7d prmonr3c_u protocol monitoring buffer 3 upstream 0000 r 100 +hdghu&dswxuh3urwrfro0rqlwrulqj5hjlvwhu6hw'rzqvwuhdp 7e prmonra_d protocol monitoring buffer downstream 0000 r 100 7f prmonrb_d protocol monitoring buffer downstream 0000 r 101 80 prmonrc_d protocol monitoring buffer downstream 0000 r 101 3urwrfro0rqlwrulqj&rqiljxudwlrq5hjlvwhu 81 headcapen enables header capturing 0000 r/w 101 7deoh $/35hjlvwhuv2yhuylhz dggu kh[ uhjlvwhu ghvfulswlrq uhvhw ydoxh 3 vhh sdjh
3;%( data sheet 3-66 08.2000 5hjlvwhu'hvfulswlrq &rqiljxudwlrqri3ruwvshflilf&rxqwhuv8svwuhdp 84 portconf0_u port specific counter configuration upstream 0000 r/w 102 ... ... ... 8b portconf7_u port specific counter configuration upstream 0000 r/w 102 8c enpotic enables port specific counter potic 0000 r/w 103 &rqiljxudwlrqri3ruwvshflilf&rxqwhuv'rzqvwuhdp 8d portconf0_d port specific counter configuration down- stream 0000 r/w 104 ... ... ... 94 portconf7_d port specific counter configuration downstream 0000 r/w 104 95 enpotoc enables port specific counter potoc 0000 r/w 105 8723,$&rqiljxudwlrq5hjlvwhuv 96 conut1a utopia configuration 0000 r/w 105 97 conut1b utopia configuration 0000 r/w 106 98 conut1c utopia configuration 0000 r/w 106 99 conut2 utopia configuration 0000 r/w 106 9a conut3 utopia configuration 003f r/w 108 8723,$'rzqvwuhdp4xhxh2yhuiorz,qglfdwlrq5hjlvwhuv 9b ut_qov1 utopia queue overflow (downstream) 0000 r*) 109 9c ut_qov2 utopia queue overflow; buffer overflow (downstream) 0000 r*) 109 &rqiljxudwlrq2i+hdghu7udqvodwlrq6shfldo(qdeoh%lwv 9e adred_vpim minimal vpi used in arc without came 0000 r/w 110 9f mode configuration of address reduction, header translation and traffic measurement; enable writing of testr and bistmode 0000 r/w 110 7deoh $/35hjlvwhuv2yhuylhz dggu kh[ uhjlvwhu ghvfulswlrq uhvhw ydoxh 3 vhh sdjh
3;%( data sheet 3-67 08.2000 5hjlvwhu'hvfulswlrq &rppdqg5hjlvwhu a0 cmr m p-request definition 0000 r/w 111 6wdwxv5hjlvwhuv)ru+hdghu&dswxuh&$0( a1 statr status of protocol monitoring 0000 r 113 a2 cstatr status of came after m p request 0000 r 114 ,qwhuuxsw6wdwxv5hjlvwhuv,qwhuuxsw0dvn5hjlvwhuv a3 isr0 interrupt status register 0000 r*) 115 a4 isr1 interrupt status register 0000 r*) 117 a5 imr0 interrupt mask register 0000 r/w 118 a6 imr1 interrupt mask register 0000 r/w 120 &$0(,qwhuuxsw6wdwxv5hjlvwhu a7 csir status of came after interrupt; port number after interrupts 0000 r*) 121 5:50$6.5(*,67(5 a9 rmw_mask mask of single words at read/write accesses 0000 r/w 122 &hoo7\sh5hfrjqlwlrq&rqiljxudwlrq5hjlvwhuv aa uct_config action on receiving oam-cells upstream 0000 r/w 123 ab dct_config action on receiving oam-cells downstream 0000 r/w 125 50:5hvhw&rqiljxudwlrq5hjlvwhu ac rmw_conf reset of single words in the read/modify/ write block 0000 r/w 127 $gguhvv5hjlvwhu)ru&05&rppdqgv ad adr address of a m p request 0000 r/w 128 7deoh $/35hjlvwhuv2yhuylhz dggu kh[ uhjlvwhu ghvfulswlrq uhvhw ydoxh 3 vhh sdjh
3;%( data sheet 3-68 08.2000 5hjlvwhu'hvfulswlrq 1rwh 6lqjohelwvriwklvuhjlvwhuduhuhvhwwdeohe\zulwlqjd?wrwkhp 5hjlvwhulvuhvhwdwhdfkzulwhdffhvv 6fdq&rqiljxudwlrq5hjlvwhuv ae sc_conr1 configuration of polu refresh 0000 r/w 129 af sc_conr2 configuration of polu refresh 0000 r/w 129 '0$&rqiljxudwlrq5hdg5hjlvwhu b0 dconr configuration of dma 0000 r/w 130 b1 dmar dma fifo access undef. r 132 7hvw5hjlvwhu6shfldo0rghv b2 testr test configuration 0000 r/w 133 32/86wdwxv5hjlvwhuv b3 p_statr0 polu status register 0 0000 r 135 b4 p_statr1 polu status register 1 0000 r 135 b5 p_statr2 polu status register 2 0000 r 135 &$0(9dolg,qwhuphgldwh/&, b6 camvilci response from address reduction test 0000 r 136 '0$5dqjh5hjlvwhuv b8 dma_min lower lci of dma 0000 r/w 136 b9 dma_max upper lci of dma 0000 r/w 136 %,675hjlvwhuv ba bistmode1 bist mode register 1 0000 r/w 137 bb bistmode2 bist mode register 2 0000 r/w 138 bc bistdone bist active register 0000 r 139 bd bisterror bist result register 01ff r/w**) 140 7deoh $/35hjlvwhuv2yhuylhz dggu kh[ uhjlvwhu ghvfulswlrq uhvhw ydoxh 3 vhh sdjh
3;%( data sheet 3-69 08.2000 5hjlvwhu'hvfulswlrq 7udqvihu5hjlvwhu*hqhudo0dsslqjwr'zrugv 5hdg:ulwh5hjlvwhuv register set used for all read/write m p-requests (see cmr-register 6hfwlrq page 111). they are used as an shadow image of the specified data block. wdr (write data register): contents of wdr registers are transferred to the destination selected in register cmr. rdr (read data register): contents of the source selected in register cmr are transferred to rdr registers. 1rwh $wzulwhdffhvvhvwrdqh[whuqdo5$0elwriwkhfruuhvsrqglqj:'5uhjlvwhulvxvhgwrfrqwurowkhsdulw\ jhqhudwlrqdviroorzv elw jhqhudwhuljkwsdulw\iruwklvzrug elw jhqhudwhzurqjsdulw\iruwklvzrug $w uhdg dffhvvhv iurp dq h[whuqdo 5$0 wkh uhvxow ri wkh sdulw\ fkhfn lv zulwwhq lqwr elw ri wkh fruuhvsrqglqj5'5uhjlvwhu7khfrglqjlvdviroorzv elw sdulw\fkhfnlvrnd\iruwklvzrug elw sdulw\fkhfnidlohgiruwklvzrug :ulwh7udqvihu5hjlvwhuv:'5/:'5+:'5$/:'5$+ read/write address 00 h ..15 h value after reset undefined 'zrug 10 register wdrah / address 15 h register wdral / address 14 h 9 register wdr9h / address 13 h register wdr9l / address 12 h 8 register wdr8h / address 11 h register wdr8l / address 10 h 7 register wdr7h / address 0f h register wdr7l / address 0e h 6 register wdr6h / address 0d h register wdr6l / address 0c h 5 register wdr5h / address 0b h register wdr5l / address 0a h 4 register wdr4h / address 09 h register wdr4l / address 08 h 3 register wdr3h / address 07 h register wdr3l / address 06 h 2 register wdr2h / address 05 h register wdr2l / address 04 h 1 register wdr1h / address 03 h register wdr1l / address 02 h 0 register wdr0h / address 01 h register wdr0l / address 00 h
3;%( data sheet 3-70 08.2000 5hjlvwhu'hvfulswlrq 5hdg7udqvihu5hjlvwhuv5'5/5'5+5'5$/5'5$+ read/write address 16 h ..2b h value after reset undefined 'zrug 10 register rdrah / address 2b h register rdral / address 2a h 9 register rdr9h / address 29 h register rdr9l / address 28 h 8 register rdr8h / address 27 h register rdr8l / address 26 h 7 register rdr7h / address 25 h register rdr7l / address 24 h 6 register rdr6h / address 23 h register rdr6l / address 22 h 5 register rdr5h / address 21 h register rdr5l / address 20 h 4 register rdr4h / address 1f h register rdr4l / address 1e h 3 register rdr3h / address 1d h register rdr3l / address 1c h 2 register rdr2h / address 1b h register rdr2l / address 1a h 1 register rdr1h / address 19 h register rdr1l / address 18 h 0 register rdr0h / address 17 h register rdr0l / address 16 h
3;%( data sheet 3-71 08.2000 5hjlvwhu'hvfulswlrq 0dsslqjri7udqvihu5hjlvwhuwr,qwhuqdo([whuqdo5$0v 3rolflqj5$032/85$0 1rwh 7khvwelwlvdozd\vdsdulw\ryhudgguhvvdqggdwd 3rolflqj5$0'zrug bit 31 parity bit of dword0 odd parity over address and data. y1(30:0) policing variable of lb1. 1rwh ,qlwldol]hgzlwkdoo??dwwkhhvwdeolvkphqwridfrqqhfwlrq'rq?wfkdqjhwkhydoxhgxulqjqrupdosrolflqj rshudwlrq 3rolflqj5$0'zrug bit 31 parity bit of dword1 odd parity over address and data. y2(18:0) policing variable of lb2. 1rwh ,qlwldol]hgzlwkdoo??dwwkhhvwdeolvkphqwridfrqqhfwlrq'rq?wfkdqjhwkhydoxhgxulqjqrupdosrolflqj rshudwlrq y1(42:31) policing variable of lb1. 1rwh ,qlwldol]hgzlwkdoo??dwwkhhvwdeolvkphqwridfrqqhfwlrq'rq?wfkdqjhwkhydoxhgxulqjqrupdosrolflqj rshudwlrq 'zrug 10 31 27 f5e2 e_u/ d(1:0) f4e2 e_u/ d(1:0) f5se g_u/ d(1:0) f4se g_u/ d(1:0) f5r m_u/ d(1:0) f4r m_u/ d(1:0) use r_u/ d(1:0) mod e(1:0) dis_ u/ d(1:0) delta3(31:23) 9 31 delta3(22:0) delta2(31:24) 8 31 delta2(23:0) delta1(31:25) 7 31 delta1(24:0) wmin3(33:28) 631 wmin3(27:0) wmin2 (33:31) 5 31 wmin2(30:0) 4 31 wmin1(41:11) 3 31 wmin1(10:0) y3(34:15) 2 31 y3(14:0) y2(34:19) 1 31 y2(18:0) y1(42:31) 0 31 y1(30:0) cmr(4:0) = 00000
3;%( data sheet 3-72 08.2000 5hjlvwhu'hvfulswlrq 3rolflqj5$0'zrug bit 31 parity bit of dword2 odd parity over address and data. y3(14:0) policing variable of lb3. 1rwh ,qlwldol]hgzlwkdoo??dwwkhhvwdeolvkphqwridfrqqhfwlrq'rq?wfkdqjhwkhydoxhgxulqjqrupdosrolflqj rshudwlrq y2(34:19) policing variable of lb2. 1rwh ,qlwldol]hgzlwkdoo??dwwkhhvwdeolvkphqwridfrqqhfwlrq'rq?wfkdqjhwkhydoxhgxulqjqrupdosrolflqj rshudwlrq 3rolflqj5$0'zrug bit 31 parity bit of dword3 odd parity over address and data. wmin1(10:0) policing parameter w min1 of lb1 wmin1(10:0) is fractional value of w min1 . lsb of w min1 (wmin1(0)) is 2 -11 . y3(34:15) policing variable of lb3. 1rwh ,qlwldol]hgzlwkdoo??dwwkhhvwdeolvkphqwridfrqqhfwlrq'rq?wfkdqjhwkhydoxhgxulqjqrupdosrolflqj rshudwlrq 3rolflqj5$0'zrug bit 31 parity bit of dword4 odd parity over address and data. wmin1(41:11) policing parameter w min1 of lb1 wmin1(41:11) is integer value of w min1 . msb of w min1 (wmin1(41)) is 2 31 . 3rolflqj5$0'zrug bit 31 parity bit of dword5 odd parity over address and data. wmin2(30:0) policing parameter w min2 of lb2 wmin2(10:0) is fractional value of w min2 . lsb of w min2 (wmin2(0)) is 2 -11 . wmin2(30:11) is integer value of w min2 . 3rolflqj5$0'zrug bit 31 parity bit of dword6 odd parity over address and data. wmin3(27:0) policing parameter w min3 of lb3 wnim3(10:0) is fractional value of w min3 . lsb of w min3 (wmin3(0)) is 2 -11 . wmin3(27:11) is integer value of w min3 . wmin2(33:31) msb of w min2 (wmin2(33)) is 2 23 .
3;%( data sheet 3-73 08.2000 5hjlvwhu'hvfulswlrq 3rolflqj5$0'zrug bit 31 parity bit of dword7 odd parity over address and data. delta1(24:0) policing parameter delta 1 of lb1 delta1(10:0) is fractional value of delta 1 . lsb of delta 1 (delta1(0)) is 2 -11 . delta1(24:11) is integer value of delta 1 . wmin3(33:28) msb of w min3 (wmin3(33)) is 2 23 . 3rolflqj5$0'zrug bit 31 parity bit of dword8 odd parity over address and data. delta2(23:0) policing parameter delta2 of lb2 delta2(10:0) is fractional value of delta 2 . lsb of delta 2 (delta2(0)) is 2 -11 . delta2(23:11) is integer value of delta 2 . delta1(31:25) policing parameter delta 1 of lb1 msb of delta 1 (delta1(31)) is 2 21 . 3rolflqj5$0'zrug bit 31 parity bit of dword9 odd parity over address and data. delta3(22:0) policing parameter delta 3 of lb3 delta3(10:0) is fractional value of delta 3 . lsb of delta 3 (delta3(0)) is 2 -11 . delta3(22:11) is integer value of delta 3 . delta2(31:24) policing parameter delta 2 of lb2 msb of delta 2 (delta2(31)) is 2 21 . 3rolflqj5$0'zrug bit 31 parity bit of dword10 odd parity over address and data. bit 30:28 not used. bit 27 show_param used only for testing. dont change the contents. f5e2e_u/d(1:0) coding of f5 end to end cell policing option flags: f4e2e_u/d(1:0) coding of f4 end to end cell policing option flags: 00 no policing. 01 down path (lb3). 10 upper path (lb1 and lb2) 11 no policing. 00 no policing. 01 down path (lb3). 10 upper path (lb1 and lb2) 11 no policing.
3;%( data sheet 3-74 08.2000 5hjlvwhu'hvfulswlrq f5seg_u/d(1:0) coding of f5 segment cell policing option flags: f4seg_u/d(1:0) coding of f4 segment cell policing option flags: f5rm_u/d(1:0) coding of f5rm cell policing option flags: f4rm_u/d(1:0) coding of f4rm cell policing option flags: user_u/d(1:0) coding of user cell policing option flags: mode(1:0) polu operating mode. 00 no policing. 01 down path (lb3). 10 upper path (lb1 and lb2) 11 no policing. 00 no policing. 01 down path (lb3). 10 upper path (lb1 and lb2) 11 no policing. 00 no policing. 01 down path (lb3). 10 upper path (lb1 and lb2) 11 no policing. 00 no policing. 01 down path (lb3). 10 upper path (lb1 and lb2) 11 no policing. 00 no policing. 01 down path (lb3). 10 upper path (lb1 and lb2) 11 no policing. 00 tagging option is on parameters of lb1 are: scr 0 and mbs 0 parameter of lb2 is: pcr 0+1 parameter of lb3 is: pcr 0+1 01 tagging option is off parameters of lb1 are: scr 0 and mbs 0 parameter of lb2 is: pcr 0+1 parameter of lb3 is: pcr 0+1 10 tagging option is off parameters of lb1 are: scr 0+1 and mbs 0+1 parameter of lb2 is: pcr 0+1 parameter of lb3 is: pcr 0+1 11 tagging option is off parameters of lb1 are: pcr 0+1 parameter of lb2 is: disabled parameter of lb3 is: pcr 0+1
3;%( data sheet 3-75 08.2000 5hjlvwhu'hvfulswlrq dis_u/d(1:0) disable connection flag for upper/down path. 1rwh 'lvdeolqjphdqv7khvwdwhyduldeohvdqgwkhfrxqwhuvriwkhqrqfrqiruplqjfhoovduhxsgdwhgexwwkh fhoovduhqhlwkhuglvfdughgruwdjjhg delta3(31:23) policing parameter delta 3 of lb3 msb of delta 3 (delta3(31)) is 2 21 . &rqqhfwlrq5$08svwuhdp &rqqhfwlrq5$08svwuhdp'zrug header translation connection data up. bit 31 parity odd parity over address and data (look at remarks for read/write registers in alp registers detailed description). bit 30 p_ip reserved for future functions. bit 29 not used. bit 28 cc_ip_copy 00 normal policing 01 down path disabled 10 upper path disabled 11 down and upper path disabled 'zrug 7 vpc specific total incoming cells with clp=0 (= p_tic0) 6 vpc specific total incoming cells (= p_tic) 5 counter (total tagged cells) (= ttc) 4 counter (total discarded cells with clp=0) (= tdc0) 3 counter (total discarded cells with clp=1) (= tdc1) 2 total incoming cells with clp=0 (= tic0) 1 total incoming cells (= tic) 03130 28 f5pt_ cfg(2:0) f4pt_ cfg(2:0) 21 20 19 hk(2:0) 15 14 lci2_up(13:0) cmr(4:0) = 00001 0 forward cells 1 continuity check (cc) oam cells are copied at intermediate points (ip) (used for oam light).
3;%( data sheet 3-76 08.2000 5hjlvwhu'hvfulswlrq f5pt_cfg(2:0) f5 (channel specific) point configuration (used for oam light). the subsequent layer point codings are possible : f4pt_cfg(2:0) f4 (path specific) point configuration (used for oam light). the subsequent layer point codings are possible : bit 21 lb_ip_drop default lb action on ip points (used by cell type recognition) : bit 20 ar_ip_copy default oam action on ip points (used by cell type recognition) : bit 19 vcon_up hk(2:0) house keeping bits. bit 15 inc_timc_ssd bit 14 en_traf_meas_up lci2_up(13:0) f4 data pointer. 000 no f5 layer point 010 f5 oep (originating end point) 011 f5 osp (originating segment point) 100 f5 ip (intermediate point) 110 f5 tsp (terminating segment point) 111 f5 tep (terminating end point) 000 no f4 layer point 010 f4 oep (originating end point) 011 f4 osp (originating segment point) 100 f4 ip (intermediate point) 110 f4 tsp (terminating segment point) 111 f4 tep (terminating end point) 0 forward cells. 1 drop oam cells of type lb at intermediate points. 0 forward cells. 1 copy oam cells of type ais/rdi at intermediate points. 0 invalid connection. 1 valid connection indicated. 1 increment the total incoming management cells special studies counter upstream at cell emission on this vc. 1 enable traffic measurements (independently of vcon).
3;%( data sheet 3-77 08.2000 5hjlvwhu'hvfulswlrq &rqqhfwlrq5$0grzqvwuhdp &rqqhfwlrq5$0grzqvwuhdp'zrug header translation connection data down (flags, lci2, pn). bit 31 parity odd parity over address and data (look at remarks for read/write registers in alp registers detailed description). bit 30 p_ip f5cfg(2:0) f5 (channel specific) point configuration (used for oam light). the subsequent layer point codings are possible : f4cfg(2:0) f4 (path specific) point configuration (used for oam light). the subsequent layer point codings are possible : 'zrug 6 vp specific total outgoing cells with clp=0 (= p_toc0) 5 vpc specific total outgoing cells (= p_toc) 4 total outgoing cells with clp=0 (= toc0) 3 total outgoing cells (= toc) 231 pn_ut_do (4:0) 14 next_lci(13:0) 1 31 30 29 28 vpi_do(11:0) vci_do(15:0) 03130 f5cfg (2:0) f4cfg (2:0) 23 22 pnudf(5:0) 15 14 lci2_do(13:0) cmr(4:0) = 00010 0 path end point. 1 path intermediate point. at path intermediate points only a vpi header translation takes place. 000 no f5 layer point 010 f5 oep (originating end point) 011 f5 osp (originating segment point) 100 f5 ip (intermediate point) 110 f5 tsp (terminating segment point) 111 f5 tep (terminating end point) 000 no f4 layer point 010 f4 oep (originating end point) 011 f4 osp (originating segment point) 100 f4 ip (intermediate point) 110 f4 tsp (terminating segment point) 111 f4 tep (terminating end point)
3;%( data sheet 3-78 08.2000 5hjlvwhu'hvfulswlrq bit 23 en_traf_meas_do bit 22 vcon_do pnudf(5:0) new portnumber (pn) that is mapped into the udf1 field of the outgoing cell header (mapping will be always done independently of selected portnumber mode). bit 15 inc_tof5rmc_ssd increment the total outgoing resource management cells special studies counter downstream (counter potocor) at f5 rm cell emission on this vc. bit 14 inc_tomc_ssd increment the total outgoing cells special studies counter downstream (counter potocor) at cell emission on this vc. lci2_do(13:0) the lci2 is a f4 data pointer which addresses the path specific counters. &rqqhfwlrq5$0grzqvwuhdp'zrug header translation connection data down (vpi,vci). bit 31 parity odd parity over address and data. bit 30 cc_ip_copy bit 29 lb_ip_drop default lb action on ip points (used by cell type recognition) : bit 28 ar_ip_copy default oam action on ip points (used by cell type recognition) : vpi_do(11:0) new vpi for header translation. vci_do(15:0) new vci for header translation. &rqqhfwlrq5$0grzqvwuhdp'zrug lci of the following connection in the multicast chain. bit 31 parity odd parity over address and data. bit 30:21 not used. pn_ut_do(4:0) ut-pn, used if mode(11) = 0. bit 15 not used. 1 enable traffic measurements of all connection specific counters of this specific connection (independently of vcon-bit). 1 indicates that this connection is valid. 0 forward cells. 1 copy oam cells of type cca/cc at intermediate points. 0 forward cells. 1 drop oam cells of type lb at intermediate points. 0 forward cells. 1 copy oam cells of type ais/rdi at intermediate points.
3;%( data sheet 3-79 08.2000 5hjlvwhu'hvfulswlrq bit 14 mc_anchor next_lci(13:0) lci of the following connection in the multicast chain. 7udiilf0hdvxuhphqw5$03ruw7deoh 3ruw7deoh8svwuhdp 0 indicates the end of the linked list in mc. 1 the next_lci pointer (b.13..0) is valid. 'zrug 47 counter potic_f for : total incoming cells at port number 15 ... ... 32 counter potic_0 for : total incoming cells at port number 0 31 counter poticor_c7 for : total incoming oam or rm cells enabled per connection at port number cntport7_u 30 counter potic_c7 for : total incoming cells at port number cntport7_u 29 counter poticn_c7 for : total incoming cells with non-zero gfc-field at port number cntport7_u 28 counter pdc_c7 for : total discarded cells due to unallocated pn/vpi/vci at port number cntport7_u ... ... 3 counter poticor_c0 for : total incoming oam or rm cells enabled per connection at port number cntport0_u 2 counter potic_c0 for : total incoming cells at port number cntport0_u 1 counter poticn_c0 for : total incoming cells with non-zero gfc-field at port number cntport0_u 0 counter pdc_c0 for : total discarded cells due to unallocated pn/vpi/vci at port number cntport0_u cmr(4:0) = 00011;
3;%( data sheet 3-80 08.2000 5hjlvwhu'hvfulswlrq $gguhvvlqjyld/&,ri$'5uhjlvwhu $gguhvv 'zrug 0 h 0 - 7 1 h 8 - 15 2 h 16 - 23 3 h 24 - 31 4 h 32 - 39 5 h 40 - 47 6 h - 3fff h no action 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'zrug &rxqwhu 'zrug &rxqwhu 0 pdc_c0 0 pdc_c2 1 poticn_c0 1 poticn_c2 2 potic_c0 2 potic_c2 3 poticor_c0 3 poticor_c2 4 pdc_c1 4 pdc_c3 5 poticn_c1 5 poticn_c3 6 potic_c1 6 potic_c3 7 poticor_c1 7 poticor_c3 8 - a not used 8 - a not used
3;%( data sheet 3-81 08.2000 5hjlvwhu'hvfulswlrq 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'zrug &rxqwhu 'zrug &rxqwhu 0 pdc_c4 0 pdc_c6 1 poticn_c4 1 poticn_c6 2 potic_c4 2 potic_c6 3 poticor_c4 3 poticor_c6 4 pdc_c5 4 pdc_c7 5 poticn_c5 5 poticn_c7 6 potic_c5 6 potic_c7 7 poticor_c5 7 poticor_c7 8 - a not used 8 - a not used 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'zrug &rxqwhu 'zrug &rxqwhu 0 potic_0 0 potic_8 1 potic_1 1 potic_9 2 potic_2 2 potic_a 3 potic_3 3 potic_b 4 potic_4 4 potic_c 5 potic_5 5 potic_d 6 potic_6 6 potic_e 7 potic_7 7 potic_f 8 - a not used 8 - a not used
3;%( data sheet 3-82 08.2000 5hjlvwhu'hvfulswlrq 3ruw7deoh'rzqvwuhdp read out with cmr register. tm counters addressed by lci value of adr register. 'zrug 31 counter potoc_f for : total outgoing cells at port number 15 ... ... 16 counter potoc_0 for : total outgoing cells at port number 0 15 counter potocor_c7 for : total outgoing oam or rm cells or discarded f5rm cells enabled per connection at port number cntport7_d 14 counter potoc_c7 for : total outgoing cells at port number cntport7_d ... ... 1 counter potocor_c0 for : total outgoing oam or rm cells or discarded f5rm cells enabled per connection at port number cntport0_d 0 counter potoc_c0 for : total outgoing cells at port number cntport0_d cmr(4:0) = 00100; $gguhvvlqjyld/&,ri$'5uhjlvwhu $gguhvv 'zrug 0 h 0 - 7 1 h 8 - 15 2 h 16 - 23 3 h 24 - 31 4 h - 3fff h no action
3;%( data sheet 3-83 08.2000 5hjlvwhu'hvfulswlrq 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'zrug &rxqwhu 'zrug &rxqwhu 0 potoc_c0 0 potoc_c4 1 potocor_c0 1 potocor_c4 2 potoc_c1 2 potoc_c5 3 potocor_c1 3 potocor_c5 4 potoc_c2 4 potoc_c6 5 potocor_c2 5 potocor_c6 6 potoc_c3 6 potoc_c7 7 potocor_c3 7 potocor_c7 8 - a not used 8 - a not used 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'dwdwriurp5'5:'5uhjlvwhudw dgguhvv + lq$'5uhjlvwhu 'zrug &rxqwhu 'zrug &rxqwhu 0 potoc_0 0 potoc_8 1 potoc_1 1 potoc_9 2 potoc_2 2 potoc_a 3 potoc_3 3 potoc_b 4 potoc_4 4 potoc_c 5 potoc_5 5 potoc_d 6 potoc_6 6 potoc_e 7 potoc_7 7 potoc_f 8 - a not used 8 - a not used
3;%( data sheet 3-84 08.2000 5hjlvwhu'hvfulswlrq &hoo7\sh)lowhu5hjlvwhuv read/write address controlled by cmr command value after reset occur via m p initialization data structure of extended cell header... up/down celltype 11 015 02 0 7 07 07 0 vpi vci pt c udf1 udf2 1st payload ...is compared with data structure of masked cell filter : u1ct_filth1 _u1(7:0) ct_filth2 _u1(7:0) ct_filth3 _u1(7:0) ct_filth4 _u1(7:0) ct_filtu1 _u1(7:0) ct_filtu2 _u1(7:0) ct_filtp1 _u1(7:0) u1ct_filth1 _u1(15:8) ct_filth2 _u1(15:8) ct_filth3 _u1(15:8) ct_filth4 _u1(15:8) ct_filtu1 _u1(15:8) ct_filtu2 _u1(15:8) ct_filtp1 _u1(15:8) u2ct_filth1 _u2(7:0) ct_filth2 _u2(7:0) ct_filth3 _u2(7:0) ct_filth4 _u2(7:0) ct_filtu2 _u2(7:0) ct_filtu2 _u2(7:0) ct_filtp1 _u2(7:0) u2ct_filth1 _u2(15:8) ct_filth2 _u2(15:8) ct_filth3 _u2(15:8) ct_filth4 _u2(15:8) ct_filtu2 _u2(15:8) ct_filtu2 _u2(15:8) ct_filtp1 _u2(15:8) d1ct_filth1 _d1(7:0) ct_filth2 _d1(7:0) ct_filth3 _d1(7:0) ct_filth4 _d1(7:0) ct_filtd1 _d1(7:0) ct_filtu2 _d1(7:0) ct_filtp1 _d1(7:0) d1ct_filth1 _d1(15:8) ct_filth2 _d1(15:8) ct_filth3 _d1(15:8) ct_filth4 _d1(15:8) ct_filtd1 _d1(15:8) ct_filtu2 _d1(15:8) ct_filtp1 _d1(15:8) d2ct_filth1 _d2(7:0) ct_filth2 _d2(7:0) ct_filth3 _d2(7:0) ct_filth4 _d2(7:0) ct_filtd2 _d2(7:0) ct_filtu2 _d2(7:0) ct_filtp1 _d2(7:0) d2ct_filth1 _d2(15:8) ct_filth2 _d2(15:8) ct_filth3 _d2(15:8) ct_filth4 _d2(15:8) ct_filtd2 _d2(15:8) ct_filtu2 _d2(15:8) ct_filtp1 _d2(15:8) 70707070707070
3;%( data sheet 3-85 08.2000 5hjlvwhu'hvfulswlrq 5hjlvwhuiru3urjudppdeoh&hoo7\sh)lowhulq8svwuhdp 1rwh 0dvnelw ??lvgrq?wfduh ??xvh)lowhuelwirufrpsdulvrq %\whdqgri&hoo7\sh)lowhu'zrug ct_filth2_u1(15:8) filter1 for header byte 2. ct_filth2_u1(7:0) mask for filter 1 for header byte 2. ct_filth1_u1(15:8) filter1 for header byte 1. ct_filth1_u1(7:0) mask for filter 1 for header byte 1. %\whdqgri&hoo7\sh)lowhu'zrug ct_filth4_u1(15:8) filter1 for header byte 4. ct_filth4_u1(7:0) mask for filter 1 for header byte 4. ct_filth3_u1(15:8) filter1 for header byte 3. ct_filth3_u1(7:0) mask for filter 1 for header byte 3. %\whdqgri&hoo7\sh)lowhu'zrug ct_filtu2_u1(15:8) filter1 for udf2. ct_filtu2_u1(7:0) mask for filter udf2. ct_filtu1_u1(15:8) filter1 for udf1. ct_filtu1_u1(7:0) mask for filter 1 udf1. %\whri&hoo7\sh)lowhu'zrug bit (31:16) not used. ct_filtp1_u1(15:8) filter1 for payload byte 1. ct_filtp1_u1(7:0) mask for filter 1 for payload byte 1. 'zrug 3 ct_filtp1_u1(15:0) 2 ct_filtu1_u1(15:0) ct_filtu2_u1(15:0) 1 ct_filth3_u1(15:0) ct_filth4_u1(15:0) 0 ct_filth1_u1(15:0) c t_filth2_u1(15:0) cmr(4:0) = 00101; write/read depicted data format to/from wdr0..3/rdr0..3 registers.
3;%( data sheet 3-86 08.2000 5hjlvwhu'hvfulswlrq 5hjlvwhuiru3urjudppdeoh&hoo7\sh)lowhulq8svwuhdp 1rwh 0dvnelw ??lvgrq?wfduh ??xvh)lowhuelwirufrpsdulvrq %\whdqgri&hoo7\sh)lowhu'zrug ct_filth2_u2(15:8) filter2 for header byte 2. ct_filth2_u2(7:0) mask for filter 2 for header byte 2. ct_filth1_u2(15:8) filter2 for header byte 1. ct_filth1_u2(7:0) mask for filter 2 for header byte 1. %\whdqgri&hoo7\sh)lowhu'zrug ct_filth4_u2(15:8) filter2 for header byte 4. ct_filth4_u2(7:0) mask for filter 2 for header byte 4. ct_filth3_u2(15:8) filter2 for header byte 3. ct_filth3_u2(7:0) mask for filter 2 for header byte 3. %\whdqgri&hoo7\sh)lowhu'zrug ct_filtu2_u2(15:8) filter2 for udf2. ct_filtu2_u2(7:0) mask for filter udf2. ct_filtu1_u2(15:8) filter2 for udf1. ct_filtu1_u2(7:0) mask for filter 2 udf1. %\whri&hoo7\sh)lowhu'zrug bit (31:16) not used. ct_filtp1_u2(15:8) filter2 for payload byte 1. ct_filtp1_u2(7:0) mask for filter 2 for payload byte 1. 'zrug 3 ct_filtp1_u2(15:0) 2 ct_filtu1_u2(15:0) ct_filtu2_u2(15:0) 1 ct_filth3_u2(15:0) ct_filth4_u2(15:0) 0 ct_filth1_u2(15:0) c t_filth2_u2(15:0) cmr(4:0) = 00110; write/read depicted data format to/from wdr0..3/rdr0..3 registers.
3;%( data sheet 3-87 08.2000 5hjlvwhu'hvfulswlrq 5hjlvwhuiru3urjudppdeoh&hoo7\sh)lowhulq'rzqvwuhdp 1rwh 0dvnelw ??lvgrq?wfduh ??xvh)lowhuelwirufrpsdulvrq %\whdqgri&hoo7\sh)lowhu'zrug ct_filth2_d1(15:8) filter1 for header byte 2. ct_filth2_d1(7:0) mask for filter 1 for header byte 2. ct_filth1_d1(15:8) filter1 for header byte 1. ct_filth1_d1(7:0) mask for filter 1 for header byte 1. %\whdqgri&hoo7\sh)lowhu'zrug ct_filth4_d1(15:8) filter1 for header byte 4. ct_filth4_d1(7:0) mask for filter 1 for header byte 4. ct_filth3_d1(15:8) filter1 for header byte 3. ct_filth3_d1(7:0) mask for filter 1 for header byte 3. %\whdqgri&hoo7\sh)lowhu'zrug ct_filtu2_d1(15:8) filter1 for udf2. ct_filtu2_d1(7:0) mask for filter udf2. ct_filtu1_d1(15:8) filter1 for udf1. ct_filtu1_d1(7:0) mask for filter 1 udf1. %\whri&hoo7\sh)lowhu'zrug bit (31:16) not used. ct_filtp1_d1(15:8) filter1 for payload byte 1. ct_filtp1_d1(7:0) mask for filter 1 for payload byte 1. 'zrug 3 ct_filtp1_d1(15:0) 2 ct_filtu1_d1(15:0) ct_filtu2_d1(15:0) 1 ct_filth3_d1(15:0) ct_filth4_d1(15:0) 0 ct_filth1_d1(15:0) c t_filth2_d1(15:0) cmr(4:0) = 01110; write/read depicted data format to/from wdr0..3/rdr0..3 registers.
3;%( data sheet 3-88 08.2000 5hjlvwhu'hvfulswlrq 5hjlvwhuiru3urjudppdeoh&hoo7\sh)lowhulq'rzqvwuhdp 1rwh 0dvnelw ??lvgrq?wfduh ??xvh)lowhuelwirufrpsdulvrq %\whdqgri&hoo7\sh)lowhu'zrug ct_filth2_d2(15:8) filter2 for header byte 2. ct_filth2_d2(7:0) mask for filter 2 for header byte 2. ct_filth1_d2(15:8) filter2 for header byte 1. ct_filth1_d2(7:0) mask for filter 2 for header byte 1. %\whdqgri&hoo7\sh)lowhu'zrug ct_filth4_d2(15:8) filter2 for header byte 4. ct_filth4_d2(7:0) mask for filter 2 for header byte 4. ct_filth3_d2(15:8) filter2 for header byte 3. ct_filth3_d2(7:0) mask for filter 2 for header byte 3. %\whdqgri&hoo7\sh)lowhu'zrug ct_filtu2_d2(15:8) filter2 for udf2. ct_filtu2_d2(7:0) mask for filter udf2. ct_filtu1_d2(15:8) filter2 for udf1. ct_filtu1_d2(7:0) mask for filter 2 udf1. %\whri&hoo7\sh)lowhu'zrug bit (31:16) not used. ct_filtp1_d2(15:8) filter2 for payload byte 1. ct_filtp1_d2(7:0) mask for filter 2 for payload byte 1. 'zrug 3 ct_filtp1_d2(15:0) 2 ct_filtu1_d2(15:0) ct_filtu2_d2(15:0) 1 ct_filth3_d2(15:0) ct_filth4_d2(15:0) 0 ct_filth1_d2(15:0) c t_filth2_d2(15:0) cmr(4:0) = 01111; write/read depicted data format to/from wdr0..3/rdr0..3 registers.
3;%( data sheet 3-89 08.2000 5hjlvwhu'hvfulswlrq 3ruw&rqiljxudwlrq5hjlvwhuv with these registers every port can be configured individually as uni (user to network interface) with reduced 8 bit address range or nni (network to network interface) with full address range of up to 12 bit. 3ruw&rqiljxudwlrq81,81,3257/ read/write address 2e h value after reset 0000 h uni(15:0) 3ruw&rqiljxudwlrq81,81,3257+ read/write address 2f h value after reset 0000 h unused(15:8) fixed to zero. uni(23:16) uni(15:8) uni(7:0) 0 nni-port (i.e. up to 12 bits of vpi will be used for address reduction depending on the number of port number bits t see mode register 6hfwlrq page 110) 1 uni-port (i.e. only 8 bit of vpi will be used for address reduction) unused uni(23:16) 0 nni-port (i.e. up to 12 bits of vpi will be used for dress reduction depending on the number of port number bits t see mode register 6hfwlrq page 110) 1 uni-port (i.e. only 8 bit of vpi will be used at address reduction)
3;%( data sheet 3-90 08.2000 5hjlvwhu'hvfulswlrq &$0('dwd5hjlvwhuv these registers are programmed with the full-length input address (pn / vpi / vci) of 32 bit length which shall be assigned to the reduced lci (local connection identifier) of 14 bit length in the came. &$0$'5/ read/write address 32 h value after reset 0000 h camadrl(15:0) data (i.e. vci) which is stored in the came under the address lci specified in the adr register. responds of the came for the following came commands defined in cmr register (see sdjh ) : &$0$'5+ read/write address 33 h value after reset 0000 h camadrh(15:0) data (i.e. pn / vpi) which is stored in the came under the address lci specified in the adr register. responds of the came for the following came commands defined in cmr register (see sdjh ) : camadrl(15:8) camadrl(7:0) 00111 read a line from the came ... 01000 write a line into the came ... 01001 write a line into the came and one entry to connection ... 01011 came test ... camadrh(15:8) camadrh(7:0) 00111 read a line from the came ... 01000 write a line into the came ... 01001 write a line into the came and one entry to connection ...
3;%( data sheet 3-91 08.2000 5hjlvwhu'hvfulswlrq 32/8&rqiljxudwlrq5hjlvwhu with p_conr_l and p_conr_h the polu (policing unit) is configured for normal mode as well as for test modes. in the test mode show selected policing values ... the results are loaded in the registers p_statr0 ... p_statr2. 32/8&rqiljxudwlrq5hjlvwhu3b&215/ read/write address 36 h value after reset 00ff h 1rwh 7kh frqwhqwv ri 3b&215/ dqg 3b&215+ zloo eh wudqvihuuhg wrjhwkhu wr wkh 32/8 rqo\ li elw 9$/,'b&21)lq3b&215+lvvhwwr com(9:0) only for test. dont change the contents for normal policing operation. tom inc count inh(2:0) disc inh tag inh com(9:2) com(1:0) tom inc count inh(2:0) disc inh tag inh 0 normal operation mode. 1 test operation mode (only for testing). 0 the corresponding ph_incr_counter-pulse is suppressed for all connections. 1 the pulse is transmitted. 0 cell discard indication is suppressed for all connections. 1 cell discard enabled. 0 tag cell indication is suppressed for all connections. 1 tagging is enabled.
3;%( data sheet 3-92 08.2000 5hjlvwhu'hvfulswlrq 32/8&rqiljxudwlrq5hjlvwhu3b&215+ read/write address 37 h value after reset 0000 h 1rwh 7kh frqwhqwv ri 3b&215/ dqg 3b&215+ zloo eh wudqvihuuhg wrjhwkhu wr wkh 32/8 rqo\ li elw 9$/,'b&21)lq3b&215+lvvhwwr valid_conf com(24:10) only for test. dont change the contents for normal policing operation. valid_ conf com(24:18) com(17:10) 0 the content of the register has already been transferred to the polu. 1 the register has been written into by the m p, but it has qrw been synchronized by the polu yet.
3;%( data sheet 3-93 08.2000 5hjlvwhu'hvfulswlrq 9huvlrq5hjlvwhu the version register provides a version number for system management purposes. the version number is identical with the boundary scan id code. 9(5/ read address 40 h value after reset 9069 h verl(15:0) version of the alp (low part): 1001 0000 0110 1001 9(5+ read address 41 h value after reset 523b h verh(15:0) version of the alp (high part): 0101 0010 0011 1011 verl(15:8) verl(7:0) verh(15:8) verh(7:0)
3;%( data sheet 3-94 08.2000 5hjlvwhu'hvfulswlrq 7udqvplw&hoo5hjlvwhuv7;5 these are registers used by m p to insert a cell into the cell flow upstream or downstream. 7udqvplw&hoo5hjlvwhu7;5 read/write address 50 h value after reset 0000 h word0(15:0) upstream with header translation: uni: gfc[3:0] / vpi[7:0] / vci[15:12] nni: vpi[11:0] / vci[15:12] upstream without header translation: lci[11:0] / vci[15:12] downstream with header translation: lci[11:0] / vci[15:12] downstream without header translation: uni: gfc[3:0] / vpi[7:0] / vci[15:12] nni: vpi[11:0] / vci[15:12] 7udqvplw&hoo5hjlvwhu7;5 read/write address 51 h value after reset 0000 h word1(15:0) vci[11:0] / pti[2:0] / clp word0(15:8) word0(7:0) word1(15:8) word1(7:0)
3;%( data sheet 3-95 08.2000 5hjlvwhu'hvfulswlrq 7udqvplw&hoo5hjlvwhu7;5 read/write address 52 h value after reset 0000 h word2(15:0) upstream without header translation: lci[13:12] / hk[2:0] / unused[4:0] / e / pnut[4:0] upstream with header translation: unused[1:0] / pnphy[5:0](*) / unused[1:0] / e / pnut[4:0](*) downstream without header translation: unused[1:0] / pnphy[5:0] / unused[1:0] / e / pnut[4:0] downstream with header translation: lci[13:12] / unused[7:0] / e / pnut[4:0] : 1rwh 31vrxufhdvsurjudpphglq02'(uhjlvwhu word2(15:8) word2(7:0) e error detection code (crc10): 0 no action. 1 perform edc. pnut[4:0] absolute port number utopia. pnphy[5:0] port number of phy-device: 0..63 for an applications. 0..7 for padack applications.
3;%( data sheet 3-96 08.2000 5hjlvwhu'hvfulswlrq 7udqvplw&hoo5hjlvwhuv7;57;5 read/write address 53 h ...6a h value after reset 0000 h (for all) $ggu 1dph 53 txr3 payload byte 0 payload byte 1 54 txr4 payload byte 2 payload byte 3 55 txr5 payload byte 4 payload byte 5 56 txr6 payload byte 6 payload byte 7 57 txr7 payload byte 8 payload byte 9 55 txr8 payload byte 10 payload byte 11 59 txr9 payload byte 12 payload byte 13 5a txr10 payload byte 14 payload byte 15 5b txr11 payload byte 16 payload byte 17 5c txr12 payload byte 18 payload byte 19 5d txr13 payload byte 20 payload byte 21 5e txr14 payload byte 22 payload byte 23 5f txr15 payload byte 24 payload byte 25 60 txr16 payload byte 26 payload byte 27 61 txr17 payload byte 28 payload byte 29 62 txr18 payload byte 30 payload byte 31 63 txr19 payload byte 32 payload byte 33 64 txr20 payload byte 34 payload byte 35 65 txr21 payload byte 36 payload byte 37 66 txr22 payload byte 38 payload byte 39 67 txr23 payload byte 40 payload byte 41 68 txr24 payload byte 42 payload byte 43 66 txr25 payload byte 44 payload byte 45 6a txr26 payload byte 46 payload byte 47
3;%( data sheet 3-97 08.2000 5hjlvwhu'hvfulswlrq &rqiljxudwlrqri7udqvplw&hoo%xiihu7;5b&21),* read/write address 6b h value after reset 0000 h unused(15:3) fixed to zero. transm_dir hton start_tr 1rwh ,wlvvwurqjo\uhfrpphqghgqrwwrvwduwwkhwudqvplvvlrqxsvwuhdpzklohwkh875;),)2b29b8elwlvvhw wrlqsxwtxhxhryhuiorzri8723,$uhfhlyhxsvwuhdplqwhuidfh ,wlvvwurqjo\uhfrpphqghgqrwwrvwduwwkhwudqvplvvlrqgrzqvwuhdpzklohwkh%29elwri,65ruwkh 87b429elwriwkhfruuhvsrqglqjsruwlvvhwwrexiihutxhxhryhuiorzrivwdwlvwlfdoghpxowlsoh[lqjexiihu lq8723,$wudqvplwgrzqvwuhdplqwhuidfh 5hfhlyh5hjlvwhu5hfhlyh&hoo%xiihu5;5 read address 70 h value after reset undefined this 16 bit read-only register is used for access to the receive cell buffer. there is one common receive cell buffer for up- and downstream direction that can store 12 cells at maximum. with rxr the receive cell buffer is read in the order octet number 0 to octet number 55. 1rwh &hoov zlwk khdghu wudqvodwlrq lqvhuwhg e\ wkh m 3 yld 7udqvplw &hoo %xiihu fdq gluhfwo\ eh gursshg wr 5hfhlyh&hoo%xiihu &hoovzlwkrxwkhdghuwudqvodwlrqlqvhuwhge\wkh m 3yld7udqvplw&hoo%xiihufdqqrwehgursshgwr5hfhlyh &hoo%xiihu+rzhyhuiruwhvwsxusrvhvwklvfdqehdfklhyhge\gluhfwo\iruzduglqjdfhooiurp7;5wr5;5 xvlqjelwriuhjlvwhu7(675/223b7;5; unused unused transm_ dir hton start _tr 0 transmit a cell upstream. 1 transmit a cell downstream. 0 without header translation. 1 header translation on. 0 no action. 1 start transmission from transmit cell buffer txr (this bit is reset by the asic after transmission). word n(15:8) word n(7:0)
3;%( data sheet 3-98 08.2000 5hjlvwhu'hvfulswlrq word 0(15:8) upstream: uni: gfc[3:0] / vpi[7:4] nni: vpi[11:4] downstream: lci[11:4] word 0(7:0) upstream: vpi[3:0] / vci[15:12] downstream: lci[3:0] / vci[15:12] word 1(15:8) vci[11:4] word 1(7:0) vci[3:0] / pti[2:0] / clp word 2(15:8) upstream: unused[1:0] / pnphy[5:0]. downstream: lci[13:12] / hk[2:0] / unused[2:0]. 1rwh 313+<>@uhsuhvhqwvwkhsruwqxpehuri,:(lqxsvwuhdpgluhfwlrq word 2(7:0) unused[1:0] / d / pnut[4:0] word 3(15:8) payload byte 0. word 3(7:0) payload byte 1. ... ... word 26(15:8) payload byte 46. word 26(7:0) payload byte 47. word 27(15:8) celltype[5:0] / unused[1:0] pnphy[5:0] port number of phy-device: 0..63 for an applications. d direction: 0 downstream 1upstream pnut[4:0] absolute port number utopia. celltype[5:2] 0000 user cell. 0001 rm (resource management) cell. 0010 pcf1 (extracted by programmable cell filter 1) cell. 0011 pcf2 (extracted by programmable cell filter 2) cell. 0100 f5res (f5 reserved for future functions with pti=111) cell (only downstream). 0101 coc (cross office check) cell (only downstream). 0111 dba (dynamic bandwidth allocation) cell. 1000 ais (alarm indication signal) cell. 1001 rdi (remote defect indication) cell. 1010 cca (continuity check activation) cell.
3;%( data sheet 3-99 08.2000 5hjlvwhu'hvfulswlrq word 27(7:0) unused[7:0] +hdghu&dswxuh3urwrfro0rqlwrulqj5hjlvwhu6hw8svwuhdp for the upstream direction 4 protocol monitoring register sets are provided, one for each clav/ enable-group. at the ports specified in the headcapen-register always the header of the last cell discarded due to atm cell header error is logged in the corresponding prmonr-buffer. additionally the flag hlog in the statr-register is set. during readout of one prmonr-buffer the buffer is locked. so every readout of a prmonr-buffer has to be completed! 3urwrfro0rqlwrulqj%xiihu8svwuhdp350215$b8$b8 read address 72 h, 75 h , 78 h , 7b h value after reset 0000 h udf1(7:0) user defined byte1 (unused[1:0] / pnphy[5:0]). udf2(7:0) user defined byte2 (clav-group[1:0] / 1 / pnut[4:0]). 3urwrfro0rqlwrulqj%xiihu8svwuhdp350215%b8%b8 read address 73 h, 76 h , 79 h , 7c h value after reset 0000 h vci(11:0) virtual channel identifier pti(2:0) payload type identifier clp cell loss priority 1011 cc (continuity check) cell. 1100 lb (loop back) cell. 1111 undef (undefined oamtype) cell. celltype[1] 0 seg (segment) cell 1 ete (end_to_end) cell celltype[0] 0 f4 (virtual path) cell 1 f5 (virtual channel) cell udf1(7:0) udf2(7:0) vci(11:4) vci(3:0) pti(2:0) clp
3;%( data sheet 3-100 08.2000 5hjlvwhu'hvfulswlrq 3urwrfro0rqlwrulqj%xiihu8svwuhdp350215&b8&b8 read address 74 h, 77 h , 7a h , 7d h value after reset 0000 h gfc(3:0)/vpi(11:8)at uni: generic flow control (gfc) at nni: virtual path identifier (vpi) vpi(7:0) virtual path identifier vci(15:12) virtual channel identifier +hdghu&dswxuh3urwrfro0rqlwrulqj5hjlvwhu6hw'rzqvwuhdp for the downstream direction only 1 protocol monitoring register set is provided for all clav/ enable-groups. the header of cells discarded due to internal cell header error is logged in the prmonr-buffer. additionally the flag hlog in the statr-register is set. during readout of one prmonr-buffer the buffer is locked. so every readout of the prmonr-buffer has to be completed! 3urwrfro0rqlwrulqj%xiihu'rzqvwuhdp350215$b' read address 7e h value after reset 0000 h udf1(7:0) user defined field 1: udf2(7:0) port number from utopia rx downstream: gfc(3:0) / vpi(11:8) vpi(7:4) vpi(3:0) vci(15:12) udf1(7:0) udf2(7:0) 7:6 two msbits of local connection identifier (lci (13:12)). 5:3 hk bits. 4:0 pn_ut_dn(4:0).
3;%( data sheet 3-101 08.2000 5hjlvwhu'hvfulswlrq 3urwrfro0rqlwrulqj%xiihu'rzqvwuhdp350215%b' read address 7f h value after reset 0000 h vci(11:0) virtual channel identifier. pti(2:0) payload type identifier. clp cell loss priority. 3urwrfro0rqlwrulqj%xiihu'rzqvwuhdp350215&b' read address 80 h value after reset 0000 h lci(11:0) local connection identifier. vci(15:12) virtual channel identifier. 3urwrfro0rqlwrulqj&rqiljxudwlrq5hjlvwhu+($'&$3(1 read/write address 81 h value after reset 0000 h this register enables/disables the protocol monitoring sets upstream and downstream. unused(10:0) fixed to zero. en_d vci(11:4) vci(3:0) pti(2:0) clp lci(11:4) lci(3:0) vci(15:12) unused unused en_d en3_u en2_u en1_u en0_u 0 disables capturing of cells from clav-group 0-3 in register prmonr_d. 1 enables capturing of cells from clav-group 0-3 in register prmonr_d.
3;%( data sheet 3-102 08.2000 5hjlvwhu'hvfulswlrq en3_u en2_u . en1_u en0_u &rqiljxudwlrqri3ruwvshflilf&rxqwhuv8svwuhdp the portspecific counters are stored in an asic internal ram. the contents of this ram are not affected by a sw-reset. every counter has 32 bit length. in case of an overflow the counters remain on the maximum count value of ffff. for each port0 .. 15 a total incoming cell (potic)-counter is provided, while port16 .. 23 dont have a total incoming cell-counter. additionally eight port specific countersets with special counters are provided which can be assigned to any port by the registers portconf0 .. 7_u. if two of these eight countersets are configured to count cells from the same port only the counterset with the lower number will be active. 3ruw6shflilf&rxqwhu&rqiljxudwlrq8svwuhdp3257&21)b8b8 read/write address 84...8b h value after reset 0000 h 0 disables capturing of cells from clav-group3 in register prmonr3_u. 1 enables capturing of cells from clav-group3 in register prmonr3_u. 0 disables capturing of cells from clav-group2 in register prmonr2_u. 1 enables capturing of cells from clav-group2 in register prmonr2_u. 0 disables capturing of cells from clav-group1 in register prmonr1_u. 1 enables capturing of cells from clav-group1 in register prmonr1_u. 0 disables capturing of cells from clav-group0 in register prmonr0_u. 1 enables capturing of cells from clav-group0 in register prmonr0_u. unused cnt_potic or_all cnt_potic oam_ cnt_u cnt_ poticor cnt_por teni_u cnt_porti_u(5:0)
3;%( data sheet 3-103 08.2000 5hjlvwhu'hvfulswlrq 1rwh 3'&b&l7rwdoglvfdughgfhoovgxhwrxqdoorfdwhg3193,9&,dwsruwl 327,&1b&l7rwdolqfrplqjfhoovzlwkqrq]hur*)&ilhogdwsruwl 327,&b&l7rwdolqfrplqjfhoovdwsruwl 327,&25b&l 7rwdo lqfrplqj 2$050 fhoov dw sruw l %\ wkh iodj ,1&b7,0&b66' zrug elw ri &rqqhfwlrq5$0xsvwuhdpwklvfrxqwhufdqehfrqqhfwlrqvshflilfdoo\hqdeohg unused(4:0) fixed to zero. cnt_poticor_all define the number of connections which are counted: cnt_potic oam_cnt_u configures the poticor counter: cnt_poticor cnt_porteni_u cnt_porti_u(5:0) upstream portnumber of the port at which cells will be counted in the counters: pdc_ci, poticn_ci, potic_ci, poticor_ci. (1327,& read/write address 8c h value after reset 0000 h 1rwh 327,&7rwdolqfrplqjfhoov enpotic(15:0) enables counter potic at port 0-15. 0 counts cells in poticor_ci for specific connections enabled by the flag inc_timc_ssd in the connection ram. 1 counts cells in poticor_ci for all connections independently of flag inc_timc_ssd in the connection ram. 0 disables the potic_ci counter. 1 enables the potic_ci counter. 0 count rm cells in poticor_ci. 1 count oam cells in poticor_ci. 0 disables the poticor_ci counter. 1 enables the poticor_ci counter. 0 disables the counters pdc_ci and poticn_ci. 1 enables the counters pdc_ci and poticn_ci. enpotic(15:8) enpotic(7:0)
3;%( data sheet 3-104 08.2000 5hjlvwhu'hvfulswlrq &rqiljxudwlrqri3ruwvshflilf&rxqwhuv'rzqvwuhdp the portspecific counters are stored in an asic internal ram. the contents of this ram are not affected by a sw-reset. every counter has 32 bit length. in case of an overflow the counters remain on the maximum count value of ffff. for each port0 .. 15 a total incoming cell-counter is provided, while port16 .. 23 have no total incoming cell-counter. additionally eight port specific countersets with special counters are provided which can be assigned to any port by the registers portconf0 .. 7_d. if two of these eight countersets are configured to count cells from the same port only the counterset with the lower number will be active. 3257&21)b'b' read/write address 8d h ...94 h value after reset 0000 h 1rwh 3272&b&l7rwdorxwjrlqjfhoovdwsruwl 3272&25b&l7rwdorxwjrlqj2$050glvfdughg)50fhoovdwsruwl%\wkhiodj,1&b72)50&b66' zrugelwri&rqqhfwlrq5dpgrzqvwuhdpwklvfrxqwhufdqehfrqqhfwlrqvshflilfdoo\hqdeohg unused(5:1) fixed to zero. cnt_potocor_all cnt_potoc unused cnt_poto cor_all cnt_ potoc oam_ cnt_d(1) oam_ cnt_d(0) unused cnt_porti_d(5:0) 0 counts cells in potocor_ci counter for specific connections enabled by the flag inc_tof5rmc_ssd or inc_tomc_ssd in the connection ram. inc_tof5rmc_ssd is evaluated if discarded f5rm and pti (111) cells are counted in the potocor_ci counter. inc_tomc_ssd is evaluated if oam or rm cells are counted in the potocor_ci counter 1 counts cells in potocor_ci counter for all connections independently of flag inc_tof5rmc_ssd or inc_tomc_ssd in the connection ram. 0 disables the potoc_ci counter. 1 enables the potoc_ci counter.
3;%( data sheet 3-105 08.2000 5hjlvwhu'hvfulswlrq oam_cnt_d(1:0)configures and enables the poticor counter: unused(0) not fixed. cnt_porti_d(5:0) downstream portnumber of the port at which cells will be counted in the counters: potoc_ci, potocor_ci. (13272& read/write address 95 h value after reset 0000 h enpotoc(15:0) enables counter potoc at port 15..0. 8723,$&rqiljxudwlrq5hjlvwhuv with these registers the enabling/disabling and the mode of all alp utopia interfaces (utrxu, uttxu, utrxd, uttxd) is configured. 8723,$&rqiljxudwlrq&2187$ read/write address 96 h value after reset 0000 h ut_port_u(15:0) 00 disables the potocor_ci counter. 01 counts oam cells and enables the potocor_ci counter. 10 counts rm cells and enables the potocor_ci counter. 11 counts discarded f5rm and pti(111) cells and enables the potocor_ci counter. enpotoc(15:8) enpotoc(7:0) ut_port_u(15:8) ut_port_u (7:0) 0 disables utopia port 15..0 upstream. 1 enables utopia port 15..0 upstream.
3;%( data sheet 3-106 08.2000 5hjlvwhu'hvfulswlrq 8723,$&rqiljxudwlrq&2187% read/write address 97 h value after reset 0000 h ut_port_d(23:16) ut_port_u(23:16) 8723,$&rqiljxudwlrq&2187& read/write address 98 h value after reset 0000 h ut_port_d(15:0) 8723,$&rqiljxudwlrq&2187 read/write address 99 h value after reset 0000 h utp_16bit ut_port_d (23:16) ut_port_u (23:16) 0 disables utopia port 23..16 downstream. 1 enables utopia port 23..16 downstream. 0 disables utopia port 23..16 upstream. 1 enables utopia port 23..16 upstream. ut_port_d(15:8) ut_port_d (7:0) 0 disables utopia port 15..0 downstream. 1 enables utopia port 15..0 downstream. utp_ 16bit utp_ par utp_config(1:0) uta_ 16bit uta_ par uta_config(1:0) unused 0 8bit data bus at phy side. 1 16bit data bus at phy side.
3;%( data sheet 3-107 08.2000 5hjlvwhu'hvfulswlrq utp_par utp_config(1:0) configuration of mode at phy side: uta_16bit uta_par uta_config(1:0) configuration of mode at atm side: unused(7:0) fixed to zero. 0 dont check parity of phy receive data. 1 check parity of phy receive data. 00 4 x 6 port 01 3 x 8 port 10 2 x 12 port 11 utopia level 1 (4 x 1 port) 0 8bit data bus at atm side. 1 16bit data bus at atm side. 0 dont check parity of atm receive data. 1 check parity of atm receive data. 00 4 x 6 port 01 3 x 8 port 10 2 x 12 port 11 utopia level 1 (4 x 1 port)
3;%( data sheet 3-108 08.2000 5hjlvwhu'hvfulswlrq 8723,$&rqiljxudwlrq&2187 read/write address 9a h value after reset 003f h force_ec_d ec_minint_d(6:0) minimal interval (in cell cycles) between 2 empty cycles downstream. this bit is only valid if force_ec_d is equal one. ut_vpn unused fixed to zero. ut_thresh(5:0) queue threshold of utopia demultiplexing buffer (each queue has the same threshold). force_ ec_d ec_minint_d(6:0) ut_vpn unused ut_thresh(5:0) 0 no forcing of empty cycles downstream. 1 force empty cycles downstream. 0 dont change incoming port number. 1 change incoming port number 0 to1 (can be used to switch between two lci ranges for redundancy purposes).
3;%( data sheet 3-109 08.2000 5hjlvwhu'hvfulswlrq 8723,$'rzqvwuhdp4xhxh2yhuiorz,qglfdwlrq5hjlvwhuv if a queue overflow occurs in the statistical demultiplexing buffer downstream, an utopia backpressure is generated for the preceding asic so that no further cells will be accepted. cells for this queue that are already inside the alp (utopia input buffer or workbench) will be still added to the queue so that blocking will be avoided. 87b429 read address 9b h value after reset 0000 h 1rwh 6lqjohelwvriwklvuhjlvwhuduhuhvhwwdeohe\zulwlqjd?wrwkhp qov(15:0) 87b429 read address 9c h value after reset 0000 h 1rwh 6lqjohelwvriwklvuhjlvwhuduhuhvhwwdeohe\zulwlqjd?wrwkhp unused(7:0) fixed to zero. qov(23:16) qov(15:8) qov (7:0) 0 no queue overflow of port 15..0 at utopia downstream phy-side. 1 queue overflow of port 15..0 at utopia downstream phy-side. unused qov (23:16) 0 no queue overflow of port 23..16 at utopia downstream phy-side. 1 queue overflow of port 23..16 at utopia downstream phy-side.
3;%( data sheet 3-110 08.2000 5hjlvwhu'hvfulswlrq &rqiljxudwlrqri+hdghu7udqvodwlrq6shfldo(qdeoh%lwv these registers configure the header translation (came or internal address reduction, number of portnumber bits), select the port number source and provide two special enable bits, one to enable all traffic measurement counters and the other to enable write access to the registers testr and bistmode1/2. $'5('b93,0 read/write address 9e h value after reset 0000 h unused(3:0) fixed to zero. vpimin(11:0) minimal vpi used in address reduction algorithm without came (only valid if bit cam in mode register is set to 1). 02'( read/write address 9f h value after reset 0000 h unused(3:2) fixed to zero. testr_en counten pn_source_d source of the portnumber downstream: pn_source_u source of the portnumber upstream: unused(1:0) fixed to zero. unused vpimin(11:8) vpimin(7:0) unused testr_en counten pn_sour ce_d pn_sour ce_u unused m_numb(3:0) p_numb(2:0) cam 0 the write access to testr-register and bist-register is disabled. 1 the testr-register and the bist-register are writable. 0 all traffic measurement counters will be stopped. 1 all traffic measurement counters will be enabled. 0 connection ram (connramdo) 1utopia 0utopia 1 udf1(5:0)
3;%( data sheet 3-111 08.2000 5hjlvwhu'hvfulswlrq m_numb(3:0) block size parameter (only valid if bit cam=1). 1rwh ,qfdvhridgguhvvuhgxfwlrqzlwkrxw&$0(3b1 80% 0 b180%ru0b180% ohdgvwrd&$0b(55 lqwhuuxswdqgdoofhoovxsvwuhdpzlooehglvfdughg p_numb(2:0) number of portnumber bits which are mapped into the lci (if bit cam=1) or pn / vpi / vci supplied to came (if cam=0; 5hpdun p_numb = 7, 6, 5 leads to cam_err interrupt, only p_numb = 4, 3, 2, 1, 0 is allowed !). cam &rppdqg5hjlvwhu&05 read/write address a0 h value after reset 0000 h the command register provides and controls all kinds of possible m p requests. swreset(3:0) 1rwh 7khzkroh$6,&lqfoxglqjuhjlvwhuvdqg8723,$lqwhuidfhvlvuhvhw2qo\wkhfrqwhqwvriwkhlqwhuqdo 5$0vsruwvshflilffrxqwhuv5:5exiihu5;5exiihuduhqrwdiihfwhg unused(3:0) fixed to zero. streq readonly mpreqdef(4:0) mp-request definition: 0 address reduction with external address reduction circuit (came device pxb 4360 e). 1 address reduction with internal address reduction circuit. swreset(3:0) unused unused streq readonly mpreqdef(4:0) 0110 software reset (leads to an internal active low reset pulse). 0 unspecified. 1 start of the specified request (the streq bit is reset by the asic when the command is finished). 0 write the specified data. 1 read the specified data. 00000 read or write one entry from/to polu ram using the lci in the adr register. 00001 read or write one entry from/to connection ram upstream using the lci in the adr register. ( 5hpdun at write accesses the new lci2 (defined in wdr0) is used to address vp specific data). 00010 read or write one entry from/to connection ram downstream using the lci in the adr register ( 5hpdun at write accesses the new lci2 (defined in wdr0) is used to address vp specific data).
3;%( data sheet 3-112 08.2000 5hjlvwhu'hvfulswlrq 00011 read or write one entry from/to port table upstream using the adr register (see appendix 1: addressing of port table counters upstream). 00100 read or write one entry from/to port table downstream using the adr register (see appendix 1: addressing of port table counters downstream). 00101 read or write cell type filter 1 upstream (see appendix 2: structure/ transmission order of cell type filters (x=u, y=1)). 00110 read or write cell type filter 2 upstream (see appendix 2: structure/ transmission order of cell type filters (x=u, y=2)). 00111 read a line from the came using the lci in the adr register, the vci in camadrl and the pn/vpi in camadrh (not vcon and p_ip, see page 3-75, 77, 128 and 136). 01000 write a line in the came using the lci in the adr register, the vci in camadrl and the pn/vpi in camadrh. 01001 write a line into the came and one entry to connection ram upstream using the lci in the adr register, the vci in camadrl and the pn/vpi in camadrh. 01010 not used. 01011 came test using adr register for came test configuration and camadrl register for came test result (see [9]). 01100 transfer upc/npc parameters from the poluram to the polu register file using the lci in the adr register. only for test purpose. 01101 transfer updated upc/npc parameters from the polu register file to the poluram using the lci in the adr register. only for test purpose. 01110 read or write cell type filter 1 downstream (see appendix 2: structure/transmission order of cell type filters (x=d, y=1)). 01111 read or write cell type filter 2 downstream (see appendix 2: structure/transmission order of cell type filters (x=d, y=2)).
3;%( data sheet 3-113 08.2000 5hjlvwhu'hvfulswlrq 6wdwxv5hjlvwhuviru+hdghu&dswxuh&$0( 6wdwxv5hjlvwhuiru+hdghu&dswxuh67$75 read address a1 h value after reset 0000 h the statr register provides the status of all protocol monitoring sets upstream and downstream. unused(10:0) fixed to zero. pmo_hlog_d pmo_hlog3_u pmo_hlog2_u pmo_hlog1_u pmo_hlog0_u unused unused pmo_ hlog_d pmo_ hlog3_u pmo_ hlog2_u pmo_ hlog1_u pmo_ hlog0_u 0 no external header has been written to prmonr_d. 1 indication that downstream an external header has been written to prmonr_d. the bit is reset by the alp after the completion of m p read access to prmonr_d. 0 no external header has been written to prmonr3_u. 1 indication that for a cell from clav-group 3 upstream an external header has been written to prmonr3_u. the bit is reset by the alp after the completion of m p read access to prmonr3_u. 0 no external header has been written to prmonr2_u. 1 indication that for a cell from clav-group 2 upstream an external header has been written to prmonr2_u. the bit is reset by the alp after the completion of m p read access to prmonr2_u. 0 no external header has been written to prmonr1_u. 1 indication that for a cell from clav-group 1 upstream an external header has been written to prmonr1_u. the bit is reset by the alp after the completion of m p read access to prmonr1_u. 0 no external header has been written to prmonr0_u. 1 indication that for a cell from clav-group 0 upstream an external header has been written to prmonr0_u. the bit is reset by the alp after the completion of m p read access to prmonr0_u.
3;%( data sheet 3-114 08.2000 5hjlvwhu'hvfulswlrq 6wdwxv5hjlvwhuiru&$0(&67$75 read address a2 h value after reset 0000 h the cstatr register provides the came status after configuration by m p via cmr register. unused(11:0) fixed to zero. status(3:0) status delivered from the came after m p requests: status[3:2] = unused unused status(3:0) 00 ok (status[1:0]=00) 01 busy (status[1:0]=00) 10 alarm: status[1:0] = 00 mismatch (at search requests). 01 multimatch (at search requests). 10 test search fault (at search requests). 00 refused entry (at write request). 01 refused line (at write request). 00 test read fault (at read request). 11 error: status[1:0] = 00 address/data bus parity error. 01 cascade error. 10 command cycle error.
3;%( data sheet 3-115 08.2000 5hjlvwhu'hvfulswlrq ,qwhuuxsw6wdwxv5hjlvwhuv,qwhuuxsw0dvn5hjlvwhuv the interrupt status registers store potential interrupt causes that occurred. the coding is as follows: 0: no interrupt cause 1: interrupt cause occurred. each interrupt status bit can be reset individually by writing a logical 1 to it. the only exception is the interrupt status bit rxr_ustr (isr1, bit9) which is reset automatically. a microprocessor interrupt is only generated if the corresponding interrupt mask bit is set to 1. ,qwhuuxsw6wdwxv5hjlvwhu,65 read address a3 h value after reset 0000 h 1rwh 6lqjohelwvriwklvuhjlvwhuduhuhvhwwdeohe\zulwlqjd?wrwkhp unused(4:1) fixed to zero. utrxfifo_ov_u cty_dis_d cty_dis_u qov unused utrxfifo _ov_u cty_dis _d cty_dis _u qov bov pmo _hlog unused ut_cell err_d ut_par err_d rxr_ov ut_cell err_u ut_par err_u 1 overflow of utopia receive interface cell buffer upstream. this interrupt is generated when the 4 cell deep utopia receive interface fifo is full and a backpressure to the phy device is generated. 1 any cell discarded due to cell type recognition downstream. 1 any cell discarded due to cell type recognition upstream. 1 overflow of one or more utopia cell queues downstream (demultiplexing buffer) at phy-side. this interrupt is generated for any port when the queue threshold (ut_thresh[5:0] in register conut3) is reached. after the interrupt a backpressure signal is generated for the affected port. all cells for this port that are already inside the asic will still be stored in the queue so that blocking of the asic is avoided. there is no queuespecific backpressure to the microprocessor txr- buffer. the sw is responsible that cells are not written to a queue in overflow state.
3;%( data sheet 3-116 08.2000 5hjlvwhu'hvfulswlrq bov pmo_hlog unused(0) fixed to zero. ut_cellerr_d ut_parerr_d rxr_ov ut_cellerr_u ut_parerr_u 1 overflow of utopia cell buffer downstream (demultiplexing buffer) at phy-side. this interrupt is generated when the 63rd cell is stored in the demultiplexing buffer (capacity 64 cells). for subsequent cells a backpressure signal will be generated so that no cells will be lost inside the asic. 1 indication that one or more cell header have been logged in the prmonr-register sets (see statr-register 6hfwlrq page 113). 1 start of cell error or cell length error at utopia receive interface downstream. start of cell error: the soc-pulse is not generated although the partner device has reported to send a cell and the enable signal has been asserted by the asic. cell length error: an additional soc-pulse is generated during the running cell transfer. 1 data parity error at utopia receive interface downstream. 1 receive cell buffer overflow. this interrupt is generated after the 1st rxr-cell is discarded because the rxr-buffer is full (capacity 12 cells). 1 start of cell or cell length error at utopia receive interface upstream. start of cell error: the soc-pulse is not generated although the phy device has reported to send a cell and has been enabled by the asic. cell length error: an additional soc-pulse is generated during the running cell transfer. 1 data parity error at utopia receive interface upstream.
3;%( data sheet 3-117 08.2000 5hjlvwhu'hvfulswlrq ,qwhuuxsw6wdwxv5hjlvwhu,65 read address a4 h value after reset 0000 h 1rwh 6lqjohelwvriwklvuhjlvwhuduhuhvhwwdeohe\zulwlqjd?wrwkhp unused(5:3) fixed to zero. polvld_err vld_err_d vld_err_u rxr_ustr unused(2) fixed to zero. edc_err_d edc_err_u unused polvld _err vld _err_d vld _err_u rxr _ustr unused edc _err_d edc _err_u cam_err unused polu_par err_u ram_par err_d ram_par err_u unused 1 connection not valid in polu-ram upstream.the cell header will not be written to prmonr0..3_u. 1 connection not valid in connection ram downstream. this interrupt is generated if the vcon_do flag of a connection (bit22 of word0 of a connection entry in connection ram downstream) is not set. the cell header will be written to prmonr_d if possible (see prmonr 6hfwlrq page 100) and the interrupt pmo_hlog is set. 1 connection not valid in connection ram upstream. this interrupt is generated if the vcon_up flag of a connection (bit19 of word0 of a connection entry in connection ram upstream) is not set. 1 cell stored in rxr-buffer. this bit is set until all cells (12 cells maximum) are read out by the mp and is afterwards reset automatically. 1 edc (crc10) error in an oam cell from utopia receive interface downstream. the interrupt is only generated if oam cell processing is enabled (see bit0 oam_en of register dct_config 6hfwlrq page 125). 1 edc (crc10) error in an oam cell from utopia receive interface upstream. the interrupt is only generated if oam cell processing is enabled (see bit0 oam_en of register uct_config 6hfwlrq pa g e 1 2 3 ) .
3;%( data sheet 3-118 08.2000 5hjlvwhu'hvfulswlrq cam_err unused(1) fixed to zero. polu_parerr_u ram_parerr_d ram_parerr_u unused(0) fixed to zero. ,qwhuuxsw0dvn5hjlvwhu,05 read/write address a5 h value after reset 0000 h for every interrupt status bit the corresponding interrupt mask bit is provided (imr0 for isr0). the interrupt mask bit controls whether the setting of an interrupt status bit leads to a microprocessor interrupt (activation of the interrupt line mpint_n). unused(4:1) fixed to zero. 1 error during address reduction in came. the affected cell is discarded. all internal errors in the came are reported by this interrupt flag. additionally the status flags from the came are written to csir register. the cell header will be written to prmonr0..3_u if possible (see prmonr 6hfwlrq page 99) and the interrupt pmo_hlog is generated. 1 error at the ram interface upstream during a read access from the external polu ram. the cell header will not be written to prmonr0 .. 3_u. 1 error at the ram interface downstream during a read access from the external connection ram downstream. during a cell cycle the corresponding cell is discarded. the cell header will be written to prmonr_d if possible (see prmonr 6hfwlrq page 100) and the interrupt pmo_hlog is generated. 1 error at the ram interface upstream during a read access from the external connection ram upstream. during a cell cycle the corresponding cell is discarded. the cell header will not be written to prmonr0 .. 3_u. unused mutrxfi fo_ov_u mcty _dis_d mcty _dis_u mqov mbov mpmo_ hlog unused mut_cell err_d mut_par err_d mrxr_ov mut_cel err_u mut_par err_u
3;%( data sheet 3-119 08.2000 5hjlvwhu'hvfulswlrq mutrxfifo_ov_u mcty_dis_d mcty_dis_u mqov mbov mpmo_hlog unused(0) fixed to zero. mut_cellerr_d mut_parerr_d mrxr_ov mut_cellerr_u mut_parerr_u 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled.
3;%( data sheet 3-120 08.2000 5hjlvwhu'hvfulswlrq ,qwhuuxsw0dvn5hjlvwhu,05 read/write address a6 h value after reset 0000 h for every interrupt status bit the corresponding interrupt mask bit is provided (imr1 for isr1). the interrupt mask bit controls whether the setting of an interrupt status bit leads to a microprocessor interrupt (activation of the interrupt line mpint_n). unused(5:3) fixed to zero. mpolvld_err mvld_err_d mvld_err_u mrxr_ustr unused(2) fixed to zero. medc_err_d medc_err_u mcam_err unused(1) fixed to zero. mpolu_parerr_u unused mpolvld _err mvld _err_d mvld _err_u mrxr _ustr unused medc _err_d medc _err_u mcam _err unused mpolu_ parerr_u mram_ parerr_d mram_ parerr_u unused 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled.
3;%( data sheet 3-121 08.2000 5hjlvwhu'hvfulswlrq mram_parerr_d mram_parerr_u unused(0) fixed to zero. &$0(,qwhuuxsw6wdwxv5hjlvwhu&6,5 read address a7 h value after reset 0000 h 1rwh 6lqjohelwvriwklvuhjlvwhuduhuhvhwwdeohe\zulwlqjd?wrwkhp this register gives detailed information about the cause of a came interrupt during normal operation (cell transfer). unused(11:0) fixed to zero. status(3:0) status delivered by the came for pn / vpi / vci specific interrupts in isr1. status[3:2] = 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. 0 microprocessor interrupt is disabled. 1 microprocessor interrupt is enabled. unused unused status(3:0) 00 ok (status[1:0]=00) 01 busy (status[1:0]=00) 10 alarm: status[1:0] = 00 mismatch (at search requests). 01 multimatch (at search requests). 10 test search fault (at search requests). 00 refused entry (at write request). 01 refused line (at write request). 00 test read fault (at read request). 11 error: status[1:0] = 00 address/data bus parity error. 01 cascade error. 10 command cycle error.
3;%( data sheet 3-122 08.2000 5hjlvwhu'hvfulswlrq 5:50dvn5hjlvwhu50:b0$6. read/write address a9 h value after reset 0000 h unused(4:0) fixed to zero. rmw_mask i i=[0..a] in both cases the old ram value is available after the execution in the rdr register: 1rwh 5($'21/ 3;%( data sheet 3-123 08.2000 5hjlvwhu'hvfulswlrq &hoo7\sh5hfrjqlwlrq&rqiljxudwlrq5hjlvwhuv the registers uct_config and dct_config configure the celltype recognition upstream and downstream: C enabling of oam light with provision of some global oam cell discard functions C enabling and configuration of programmable cell type filters C treatment of crc errors C enabling of housekeeping processing (only downstream) C provision of f5rm/f5res cell discard function for padack applications (only downstream). 8&7b&21),* read/write address aa h value after reset 0000 h unused(1:0) set to zero. crc_2_nodisc 1rwh 7klviodjlvrqo\ydolgli3&)b(1lvvhwwr?? crc_1_nodisc 1rwh 7klviodjlvrqo\ydolgli3&)b(1lvvhwwr?? crc_nodisc 1rwh 7klviodjlvrqo\ydolgli2$0b(1lvvhwwr?? pcf2_act(1:0) selected action for cell types that match pcf2: 1rwh 7khilowhuvgrqrwzrundwfhoovzklfkduhglvfdughggxhwrsrolflqj pcf2_en unused crc_2_ nodisc crc_1_ nodisc crc_ nodisc pcf2_act(1:0) pcf2_ en pcf1_act(1:0) pcf1_ en undef_ nodisc lb_ disc cc_ disc ar_ disc oam_ en 0 discard cells due to crc errors if matching pcf2. 1 discard no cells due to crc errors if matching pcf2. 0 discard cells due to crc errors if matching pcf1. 1 discard no cells due to crc errors if matching pcf1. 0 discard oam cells due to crc errors. 1 discard no oam cells due to crc errors. 00 forward 01 discard 10 drop 11 copy 0 disables pcf2 (programmable cell filter 2). 1 enables pcf2 (programmable cell filter 2).
3;%( data sheet 3-124 08.2000 5hjlvwhu'hvfulswlrq pcf1_act(1:0) selected action for cell types that match pcf1: 1rwh 7khilowhuvgrqrwzrundwfhoovzklfkduhglvfdughggxhwrsrolflqj pcf1_en undef_nodisc lb_disc cc_disc ar_disc oam_en 1rwh )rupruhghwdlovorrndwghvfulswlrqri?2$0/ljkw? 00 forward 01 discard 10 drop 11 copy 0 disables pcf1 (programmable cell filter 1). 1 enables pcf1 (programmable cell filter 1). 0 discards cells with undefined oamtype at end points (tsp,tep). 1 drops cells with undefined oamtype at end points (tsp,tep). 0 drops lb cells at end points (tsp,tep). 1 discards lb cells at end points (tsp,tep). 0 drops cc/cca cells at end points (tsp,tep). 1 discards cc/cca cells at end points (tsp,tep). 0 drops ais/rdi cells at end points (tsp,tep). 1 discards ais/rdi cells at end points (tsp,tep). 0 disables oam cell processing. 1 enables oam cell processing (oam light).
3;%( data sheet 3-125 08.2000 5hjlvwhu'hvfulswlrq '&7b&21),* read/write address ab h value after reset 0000 h f5rm_disc 1rwh 6shfldo3$'$&.dssolfdwlrq)50dqg)b37, ??)5(6fhoovduhrqo\glvfdughgdw)hqgsrlqwv 7(3 hk_dis 1rwh +rxvh.hhslqjlvd6lhphqvsursulhwdu\lqvlghqrghpdlqwhqdqfhsurfhgxuh crc_2_nodisc 1rwh 7klviodjlvrqo\ydolgli3&)b(1lvvhwwr?? crc_1_nodisc 1rwh 7klviodjlvrqo\ydolgli3&)b(1lvvhwwr?? crc_nodisc 1rwh 7klviodjlvrqo\ydolgli2$0b(1lvvhwwr?? pcf2_act(1:0) selected action for cell types that match pcf2: pcf2_en f5rm_ disc hk_dis crc_2_ nodisc crc_1_ nodisc crc_ nodisc pcf2_act(1:0) pcf2_ en pcf1_act(1:0) pcf1_en undef_ nodisc lb_ disc cc_ disc ar_ disc oam_ en 0 discard no f5rm and f5_pti=111 (f5res) cells. 1 discard f5rm and f5_pti=111 (f5res) cells. 0 enables house keeping (hk) processing. 1 disables house keeping (hk) processing. 0 discard cells due to crc errors if matching pcf2. 1 discard no cells due to crc errors if matching pcf2. 0 discard cells due to crc errors if matching pcf1. 1 discard no cells due to crc errors if matching pcf1. 0 discard oam cells due to crc errors. 1 discard no oam cells due to crc errors. 00 forward 01 discard 10 drop 11 copy 0 disables pcf2 (programmable cell filter 2). 1 enables pcf2 (programmable cell filter 2).
3;%( data sheet 3-126 08.2000 5hjlvwhu'hvfulswlrq pcf1_act(1:0) selected action for cell types that match pcf1: pcf1_en undef_nodisc lb_disc cc_disc ar_disc oam_en 1rwh )rupruhghwdlovorrndwghvfulswlrqri?2$0/ljkw? 00 forward 01 discard 10 drop 11 copy 0 disables pcf1 (programmable cell filter 1). 1 enables pcf1 (programmable cell filter 1). 0 discards cells with undefined oamtype at end points (tsp,tep). 1 drops cells with undefined oamtype at end points (tsp,tep). 0 drops lb cells at end points (tsp,tep). 1 discards lb cells at end points (tsp,tep). 0 drops cc/cca cells at end points (tsp,tep). 1 discards cc/cca cells at end points (tsp,tep). 0 drops ais/rdi cells at end points (tsp,tep). 1 discards ais/rdi cells at end points (tsp,tep). 0 disables oam cell processing. 1 enables oam cell processing (oam light).
3;%( data sheet 3-127 08.2000 5hjlvwhu'hvfulswlrq 5hvhw&rqiljxudwlrq5hjlvwhu50:b&21) read/write address ac h value after reset 0000 h the rwr reset register is useful to reset a ram entry or parts of a ram entry to 0, because it is not required to write the 0 into all wdr registers. additionally in the rmw_mask register the source for the next write access has to be selected, that is: 0: for the words that shall be reset 1: for the words, that shall not be changed, the source is the rdr-buffer (no change, old word is written back). unused(4:0) fixed to zero. rmw_res_i i=[0..a]: unused rmw_ res_a rmw_ res_9 rmw_ res_8 rmw_ res_7 rmw_ res_6 rmw_ res_5 rmw_ res_4 rmw_ res_3 rmw_ res_2 rmw_ res_1 rmw_ res_0 0 normal write access without reset. 1 reset (to 0) word i of the read/write data at a write access.
3;%( data sheet 3-128 08.2000 5hjlvwhu'hvfulswlrq $gguhvv5hjlvwhuiru&05&rppdqgv$'5 read/write address ad h value after reset 0000 h the adr register is programmed with the source/destination of several m p commands of the cmr register. the p_ip and the vcon bit are only valid for came entries. p_ip is used for a reduced search request (only pn / vpi) at path intermediate points. vcon indicates whether a came entry presents a valid connection. in case that for a incoming cell the vcon bit of the came entry is 0, in normal mode (no programming of bit nodis_cam in register testr) the cell will be discarded and a interrupt is generated. vcon valid connection flag (used at write accesses to came): p_ip path intermediate point flag (used at write accesses to came): adr(13:0) address of a m p request (see cmr-register 6hfwlrq page 111). it may contain lci, port table-address or cell filter number. vcon p_ip adr(13:8) adr(7:0) 0 connection not valid. 1 connection valid. 0 address reduction is performed over pn / vpi / vci. 1 path intermediate point; address reduction is performed only over pn / vpi.
3;%( data sheet 3-129 08.2000 5hjlvwhu'hvfulswlrq 6fdq&rqiljxudwlrq5hjlvwhuv the scan configuration registers define the range of lcis (from lci_min to lci_max) that is refreshed by the polu. starting of the polu refresh has to be done in the following order: 1. write sc_conr1 with lcimin and polu_refr_en=0 2. write sc_conr2 with lcimax 3. write sc_conr1 with lcimin and with polu_refr_en=1. 6&b&215 read/write address ae h value after reset 0000 h unused fixed to zero. polu_refr_en lci_min(13:0) lower limit of lcis processed by polu refresh. 6&b&215 read/write address af h value after reset 0000 h unused fixed to zero. lci_max(13:0) upper limit of lcis processed by polu refresh. unused polu_ refr_en lci_min(13:8) lci_min(7:0) 0 no policing refresh. 1 policing refresh in the range between lci_min and lci_max. unused lci_max(13:8) lci_max(7:0)
3;%( data sheet 3-130 08.2000 5hjlvwhu'hvfulswlrq '0$&rqiljxudwlrq5hdg5hjlvwhu the dma can be performed either for connramup or for connramdo controlled by dma_ud (bit 0 of dconr). to read the counters from connramup and connramdo the following steps are necessary: C load register dma_min with lcimin C load register dma_max with lcimax C load register dconr with bit dma_ud=0 and dma_start=1 t starts dma upstream C wait until dma upstream is complete (bit dma_start=0) C load register dma_min with lcimin (only if lcimin is different for dma downstream) C load register dma_max with lcimax (only if lcimax is different for dma downstream) C load register dconr with bit dma_ud=1 and dma_start=1 t starts dma downstream C wait until dma downstream is complete (bit dma_start=0). '&215 read/write address b0 h value after reset 0000 h ctr7_res ctr6_res ctr5_res ctr4_res ctr3_res ctr7_ res ctr6_ res ctr5_ res ctr4_ res ctr3_ res ctr2_ res ctr1_ res dma_ delay(6) dma_delay(5:0) dma_ start dma_ ud 0 dont reset counter. 1 reset counter p_tic0 (upstream) after dma read. 0 dont reset counter. 1 reset counter p_tic (upstream) after dma read. 0 dont reset counter. 1 reset counter ttc (upstream) after dma read. 0 dont reset counter. 1 reset counter tdc0 (upstream) or p_toc0 (downstream) after dma read. 0 dont reset counter. 1 reset counter tdc1 (upstream) or p_toc (downstream) after dma read.
3;%( data sheet 3-131 08.2000 5hjlvwhu'hvfulswlrq ctr2_res ctr1_res dma_delay(6:0)delay between two dma requests. delay = (0,1,2,...,127) * 2 * cellcycle. 1rwh 7khvhelwvfdqehxvhgwrdyrlg'0$exuvwvrqwkh m 3exv dma_start this bit is reset by the asic after completion of the dma; i.e. after the last one of the connections between lcimin (in register dma_min) and lcimax (in register dma_max) has been read out by m p. while dma_start=1 it is not possible to write the registers dconr, dma_min and dma_max with the exception of bit dma_start. writing a 0 to dma_start resets the running dma. dma_ud 1rwh $frpsohwh'0$pxvwehvsolwlqd'0$xsvwuhdpdqgd'0$grzqvwuhdp 0 dont reset counter. 1 reset counter tic0 (upstream) or toc0 (downstream) after dma read. 0 dont reset counter. 1 reset counter tic (upstream) or toc (downstream) after dma read. 0 dma complete. 1start dma. 0 dma in upstream direction. 1 dma in downstream direction.
3;%( data sheet 3-132 08.2000 5hjlvwhu'hvfulswlrq '0$5 read address b1 h value after reset undefined this 16 bit register is used to read from the dma fifo. there the words are stored with 32 bit length (= dword). to read one dword from the dma fifo requires two read accesses to the register dmar. for the upstream direction the dma fifo is read in the following order : dword 1(15:0) connection ram upstream (tic counter). dword 1(31:16) connection ram upstream (tic counter). dword 2(15:0) connection ram upstream (tic0 counter). dword 2(31:16) connection ram upstream (tic0 counter). dword 3(15:0) connection ram upstream (tdc1 counter). dword 3(31:16) connection ram upstream (tdc1 counter). dword 4(15:0) connection ram upstream (tdc0 counter). dword 4(31:16) connection ram upstream (tdc0 counter). dword 5(15:0) connection ram upstream (ttc counter). dword 5(31:16) connection ram upstream (ttc counter). dword 6(15:0) connection ram upstream (p_tic counter). dword 6(31:16) connection ram upstream (p_tic counter). dword 7(15:0) connection ram upstream (p_tic0 counter). dword 7(31:16) connection ram upstream (p_tic0 counter). for the downstream direction the dma fifo is read in the following order : dword 3(15:0) connection ram downstream (toc counter). dword 3(31:16) connection ram downstream (toc counter). dword 4(15:0) connection ram downstream (toc0 counter). dword 4(31:16) connection ram downstream (toc0 counter). dword 5(15:0) connection ram downstream (p_toc counter). dword 5(31:16) connection ram downstream (p_toc counter). dword 6(15:0) connection ram downstream (p_toc0 counter). dword 6(31:16) connection ram downstream (p_toc0 counter). dword n(15:8/31:24) dword n(7:0/23:16)
3;%( data sheet 3-133 08.2000 5hjlvwhu'hvfulswlrq 7hvw5hjlvwhu6shfldo0rghv7(675 read/write address b2 h value after reset 0000 h the register testr provides special modes like loops, the disabling of cell discard functions and multicast. to prevent disturbing of normal mode operation by chance, the write access to the testr-register is only possible if bit testr_en in the mode-register is set to 1! unused fixed to zero. loop_txrx every change from 0 to 1 starts the transmission of the contents of the txr- registers to the rxr-registers. in case of rxr-overflow no interrupt is generated and the contents of rxr is overwritten! hw_loop_trans testint nodis_cam cells not valid in came: povlderren cells not valid in polu-ram: vlderren_d cells not valid in connection ram downstream: parerren_d cells generating a parity error at connection ram downstream: parerren_u cells generating a parity error at connection ram upstream: unused loop_ txrx hw_loop _trans testint nodis_ cam povld erren vlderr en_d parerr en_d parerr en_u vlderr en_u parerr en_polu dma_ wait mc_dis loopdu loopud 0 the hw-loops are not transparent, i.e. the cell stream is only looped back. 1 the hw-loops are transparent, i.e. the cell stream is not only looped back but also forwarded to transmit utopia. 0 all interrupt sources are enabled. 1 all interrupt sources are disabled: every new write access to the rxr- register will generate a new interrupt with a different interrupt flag (gives the opportunity to test interrupts regardless whether interrupts occur). 0 cells will not leave utopia. 1 discard no cells (and no interrupt generated). 0 discard no cells. 1 discard cells. 0 cells will not leave utopia. 1 discard no cells (and no interrupt generated). 0 cells will not leave utopia. 1 discard no cells (and no interrupt generated). 0 cells will not leave utopia. 1 discard no cells (and no interrupt generated).
3;%( data sheet 3-134 08.2000 5hjlvwhu'hvfulswlrq vlderren_u cells not valid in connection ram upstream: parerren_polucells generating a parity error at polu ram: dma_wait 1rwh 7klvelwdoorzvdgdswdwlrqwr,qwho(;'0$wlplqj mc_dis loopdu 1rwh :lwkwkhelw+:b/223b75$16wkhorrsfdqehfrqiljxuhgdvwudqvsduhqwruqrwwudqvsduhqw loopud 1rwh :lwkwkhelw+:b/223b75$16wkhorrsfdqehfrqiljxuhgdvwudqvsduhqwruqrwwudqvsduhqw 0 cells will not leave utopia. 1 discard no cells (and no interrupt generated). 0 no polu action. 1 cells will be discarded, no policing. 0 no dma-request inactive time. 1 min. 32 cycles dma-request inactive time between two active phases on the mpdreq_n pin. 0 enables multicast (downstream). 1 disables/interrupts multicast (downstream). 0 no loop. 1 insert test loop downstream to upstream (during loop in downstream direction only the functionality cell transfer with header translation is possible; other functions like cell insertion, multicast, etc. are not available). 0 no loop. 1 insert test loop upstream to downstream (during loop in downstream direction only the functionality cell transfer with header translation is possible; other functions like cell insertion, multicast, etc. are not available).
3;%( data sheet 3-135 08.2000 5hjlvwhu'hvfulswlrq 32/86wdwxv5hjlvwhuv3b67$75 3b67$75 read address b3 h value after reset 0000 h word(15:0) only for test. dont change the contents for normal policing operation. 3b67$75 read address b4 h value after reset 0000 h word(15:0) only for test. dont change the contents for normal policing operation. 3b67$75 read address b5 h value after reset 0000 h word(15:0) only for test. dont change the contents for normal policing operation. word(15:8) word(7:0) word(15:8) word(7:0) word(15:8) word(7:0)
3;%( data sheet 3-136 08.2000 5hjlvwhu'hvfulswlrq &$0(9dolg,qwhuphgldwh/&,&$09,/&, read address b6 h value after reset 0000 h the address reduction test is only started via the command read a line in the came in the cmr register. 1rwh 5hvsrqvhri& $0(lvzulwwhqwr& $09,/&, vcon valid connection flag (also in read mode). p_ip path intermediate point flag (also in read mode). lci(13:0) lci '0$5dqjh5hjlvwhuv dma_min and dma_max define the range of lcis that is processed by dma according to the settings in the register dconr. '0$b0,1 read/write address b8 h value after reset 0000 h unused fixed to zero. lci_min(13:0) lowest lci (lcimin) of lci range processed by dma. '0$b0$; read/write address b9 h value after reset 0000 h unused fixed to zero. lci_max(13:0) highest lci (lcimax) of lci range processed by dma. vcon p_ip lci(13:8) lci(7:0) unused lci_min(13:8) lci_min(7:0) unused lci_max(13:8) lci_max(7:0)
3;%( data sheet 3-137 08.2000 5hjlvwhu'hvfulswlrq %,675hjlvwhuv the bist is normally used for test purposes of the asic vendor. inside the alp the signals bistdone and bisterror are stored in registers so that the bist can be used for an initial ram test (only asic internal rams). with the bist signals stored in registers the bist test is only a go/no go test. it is not possible to determine which ram parts are faulty. a bist test of all internal rams is performed in the following order: C set bit testr_en in the mode register to 1 C check the reset values of the bist registers (bistmode1/2=bistdone=0000hex; bisterror=0fffhex) C bist self test: set the mode bits of all rams to 01 (the bist self test starts toggling of the bisterror signals. the first 0-state on these signals is captured by the bisterror register to indicate that a bist error has occurred.) C wait for about 100 clock cycles C control the bisterror register (bisterror=0000hex); that means a bist error has occurred and has been recognized for every internal ram t the control logic is able to detect bist errors C reset the bist self test for all internal rams (bistmode1/2=0000hex) C reset the bisterror register (this register is reset with any write access) C check reset of bisterror register (bisterror=0fffhex) C bist test: set the mode bits of all rams to 10 C wait until the bistdone bit of every internal ram is set (bistdone=0fffhex) C check whether bist errors occurred (bisterror /= 0fffhex). to prevent disturbing of normal mode operation by chance, the write access to the bistmode1/ 2-register is only possible if bit testr_en in the mode-register is set to 1! after completion of bist test a software-reset (see cmr-register 6hfwlrq page 111) has to be started because the bist affects also the control ram (ncp ram) of the demultiplexing buffer in the utopia transmit downstream interface which leads to a malfunction. %,670rgh5hjlvwhu%,6702'( read/write address ba h value after reset 0000 h 1rwh $fwlrqviru%lvwprgh bist_trm(1:0) bist_rxr(1:0) bist_ncp(1:0) bist_uttxd1(1:0) bist_uttxd0(1:0) bist_utrxd(1:0) bist_uttxu(1:0) bist_utrxu(1:0) ,qdfwlyh 7hvwri%,67 6wduw%,67 'ldjqrvlvqrwxvhg
3;%( data sheet 3-138 08.2000 5hjlvwhu'hvfulswlrq bist_trm(1:0) bistmode for trm ram. traffic measurement port table not modified at sw reset. bist_rxr(1:0) bistmode for rxr ram. rx 12 cell extraction buffer not modified at sw reset. bist_ncp(1:0) bistmode for uttxd ncp ram (utopia-address-ram). set to 0 with sw reset. bist_uttxd1(1:0) bistmode for uttxd buffer ram 1. utopia tx-downstream shared memory buffer of 64 cells. set to 0 with sw reset. bist_uttxd0(1:0) bistmode for uttxd buffer ram 0. utopia tx-downstream shared memory buffer of 64 cells. set to 0 with sw reset. bist_utrxd(1:0) bistmode for utrxd buffer ram. utopia rx-downstream cell fifo. set to 0 with sw reset. bist_uttxu(1:0) bistmode for uttxu buffer ram. utopia tx-upstream cell fifo. set to 0 with sw reset. bist_utrxu(1:0) bistmode for utrxu buffer ram. utopia rx-upstream cell fifo. set to 0 with sw reset. %,670rgh5hjlvwhu%,6702'( read/write address bb h value after reset 0000 h 1rwh $fwlrqviru%lvwprgh unused fixed to zero. unused bist_rwr1(1:0) bist_rwr0(1:0) bist_ucw1(1:0) bist_ucw0(1:0) ,qdfwlyh 7hvwri%,67 6wduw%,67 'ldjqrvlvqrwxvhg
3;%( data sheet 3-139 08.2000 5hjlvwhu'hvfulswlrq bist_rwr1(1:0) bistmode for rwr ram 1. m p read/write not modified at sw reset. bist_rwr0(1:0) bistmode for rwr ram 0. m p read/write not modified at sw reset. bist_ucw1(1:0) bistmode for ucw ram 1. upstream workbench not modified at sw reset. bist_ucw0(1:0) bistmode for ucw ram 0. upstream workbench not modified at sw reset. %,67$fwlyh5hjlvwhu%,67'21( read address bc h value after reset 0000 h unused fixed to zero. bistdone_rwr1 bistdone_rwr0 bistdone_ucw1 bistdone_ucw0 bistdone_trm bistdone_rxr bistdone_ncp unused bistdone _rwr1 bistdone _rwr0 bistdone _ucw1 bistdone _ucw0 bistdone _trm bistdone _rxr bistdone _ncp bistdone _uttxd1 bistdone _uttxd0 bistdone _utrxd bistdone _uttxu bistdone _utrxu 0 bistmode for rwr ram 1 is busy. 1 bistmode for rwr ram 1 is done. 0 bistmode for rwr ram 0 is busy. 1 bistmode for rwr ram 0 is done. 0 bistmode for ucw ram 1 is busy. 1 bistmode for ucw ram 1 is done. 0 bistmode for ucw ram 0 is busy. 1 bistmode for ucw ram 0 is done. 0 bistmode for trm ram is busy. 1 bistmode for trm ram is done. 0 bistmode for rxr ram is busy. 1 bistmode for rxr ram is done. 0 bistmode for uttxd ncp ram is busy. 1 bistmode for uttxd ncp ram is done.
3;%( data sheet 3-140 08.2000 5hjlvwhu'hvfulswlrq bistdone_uttxd1 bistdone_uttxd0 bistdone_utrxd bistdone_uttxu bistdone_utrxu %,675hvxow5hjlvwhu%,67(5525 read/write address bd h value after reset 01ff h 1rwh 7khuhjlvwhulvuhvhwwhgdwhyhu\zulwhdffhvvlielw7(675b(1lq02'(uhjlvwhulvhtxdo unused fixed to zero. bisterr_rwr1 bisterr_rwr0 bisterr_ucw1 0 bistmode for uttxd buffer ram is busy. 1 bistmode for uttxd buffer ram is done. 0 bistmode for uttxd buffer ram 0 is busy. 1 bistmode for uttxd buffer ram 0 is done. 0 bistmode for utrxd buffer ram is busy. 1 bistmode for utrxd buffer ram is done. 0 bistmode for uttxu buffer ram is busy. 1 bistmode for uttxu buffer ram is done. 0 bistmode for utrxu buffer ram is busy. 1 bistmode for utrxu buffer ram is done. unused bisterr_ rwr1 bisterr_ rwr0 bisterr_ ucw1 bisterr_ ucw0 bisterr_ trm bisterr_ rxr bisterr_ ncp bisterr_ uttxd1 bisterr_ uttxd0 bisterr_ utrxd bisterr_ uttxu bisterr_ utrxu 0 bisterror for rwr ram 1 occurred. 1 no bisterror. 0 bisterror for rwr ram 0 occurred. 1 no bisterror. 0 bisterror for ucw ram 1 occurred. 1 no bisterror.
3;%( data sheet 3-141 08.2000 5hjlvwhu'hvfulswlrq bisterr_ucw0 bisterr_trm bisterr_rxr bisterr_ncp bisterr_uttxd1 bisterr_uttxd0 bisterr_utrxd bisterr_uttxu bisterr_utrxu 0 bisterror for ucw ram 0 occurred. 1 no bisterror. 0 bisterror for trm ram occurred. 1 no bisterror. 0 bisterror for rxr ram occurred. 1 no bisterror. 0 bisterror for uttxd ncp ram occurred. 1 no bisterror. 0 bisterror for uttxd buffer ram 1 occurred. 1 no bisterror. 0 bisterror for uttxd buffer ram 0 occurred. 1 no bisterror. 0 bisterror for utrxd buffer ram occurred. 1 no bisterror. 0 bisterror for uttxu buffer ram occurred. 1 no bisterror. 0 bisterror for utrxu buffer ram occurred. 1 no bisterror.
3;%( data sheet 4-142 08.2000 2shudwlrq 2shudwlrq 0xowlfdvw the multicast light functionality is a sequential multicast. a multicast cell, arrived at the input cell queue of the utopia transmit interface downstream, is hold in the first entry of the input queue and copied to the output shared buffer queues given by the linked list structure in connramdo. the indication for a multicast cell is bit mc_anchor in dword2 of connramdo (see vhfwlrq page 78). the cell is copied to the queues/ports given by the pn of each lci included in the linked list. the alp supports spatial and logical multicast. when the selected lcis include different ports/queues it is a spatial multicast. if the selected lcis are defined for the same port/queue it is a logical multicast. the example in iljxuh describes a spatial multicast into three queues. )ljxuh ([dpsohiru6sdwldo0xowlfdvw to initiate a multicast, the microprocessor has to set the mc_anchor bit in dword2 of the connection entry in connramup. the next_lci entry in dword2 defines the lci of the following connection in the multicast chain. this lci has to be valid if the mc_anchor bit is set. otherwise this entry is "dont care". queue 1 queue 2 queue 24 input cell queue from utopia multicast cell output shared buffer downstream connection ram vpia/vcia/pna=1 next_lcib mc_anchor=1 vpib/vcib/pnb=2 next_lcic mc_anchor=1 vpic/vcic/pnc=24 next_lci=don't care mc_anchor=0 lcia from cell in queue lcib from ram entry of lcia lcic from ram entry of lcib lci pointer cell 1..3 = identical copies of the same cell with different headers and port numbers cell 1 cell 2 cell 3 ... ... ...
3;%( data sheet 4-143 08.2000 2shudwlrq 8723,$&rqiljxudwlrq the alp provides five registers for utopia interface configuration. the registers conut1a-c (see vhfwlrq page 105, vhfwlrq page 106 and vhfwlrq page 106) are used to enable/disable each of the 24 utopia ports in both upstream and downstream direction. the register conut2 (see vhfwlrq page 106) is used to set the data bus width (8 or 16 bit) and the utopia mode (level 1 or 2) on the phy and the atm side. to enable the forced inserting of empty cell cycles in downstream direction and to set the queue threshold of the utopia buffer the register conut3 (see vhfwlrq page 108) is used. the microprocessor can monitor the status of the utopia interface via the two utopia status registers ut_qov1 and ut_qov2 (see vhfwlrq page 109 and vhfwlrq page 109). these registers indicate on which queue an overflow occured. 5$0$ffhvv the microprocessor cannot access the external rams (poluram and connram) directly. it has to use the read and write transfer registers of the alp. the alp uses a read-modify-write type access. read-modify-write-access : first write the lci to register adr (see vhfwlrq page 128) and the new contents for this lci to the write registers from wdr0l to wdrah (see vhfwlrq page 69). to select the dwords of the selected entry which should not be changed (read-only) set the associated mask bits in the mask register rmw_mask (see vhfwlrq page 122). using bits mpreqdef in the command register cmr (see vhfwlrq page 111) the source ram must be selected. set bit readonly to 0 and the start bit streq to 1. setting the last mentioned bit starts the read-modify-write process. the microprocessor now has to poll the streq bit. when the alp finished the ram access, this bit will be reset. after that, the microprocessor can read the old ram entries via the read registers from rdr0l to rdrah (see vhfwlrq page 69). read-only-access : first write the lci to register adr (see vhfwlrq page 128). the source ram must be selected by using bits mpreqdef in the command register cmr (see vhfwlrq page 111). set the bit readonly to 1 and the start bit streq to 1. note, that the bit readonly has a higher priority than the mask register bits. therefore the mask register has no effect during a read-only-access. the setting of the last bit starts the read-modify-write process. the microprocessor now has to poll the streq bit. when the alp has finished the ram access, this bit will be reset. after that, the microprocessor can read the old ram entries via the read registers from rdr0l to rdrah (see vhfwlrq page 69). &$0($ffhvv the microprocessor is responsible for the configuration of the external address reduction circuit came. therefore a write access to the came is necessary and can be done via a set of five registers which are provided by the alp. first the microprocessor writes the lci of the connection to the address register adr (see vhfwlrq page 128). the vci of the connection is written to register camadrl (see vhfwlrq page 90). the vpi and the pn are written to register camadrh (see vhfwlrq page 90). after this the microprocessor has to set register cmr (see vhfwlrq page 111) to value 0x0048 (write line to came and start transfer). the transfer is finished after bit streq is reset by the alp. by reading register
3;%( data sheet 4-144 08.2000 2shudwlrq cstatr (see vhfwlrq page 114) status information about the came after a microprocessor access are available. 3rolflqj&rqiljxudwlrq to configurate the policing unit and to start the policing process execute the following steps. the policing unit has the capability of policing 16384 connections independently. because of that, the leaky bucket algorithm has to be defined for each policed connection. this has to be done via the entries in the poluram, which consists of 11 dwords (see vhfwlrq page 71). with the dwords 0 to 10 the variables of the leaky buckets algorithm are defined. dword 10 is used for setting f4/f5 policing options, polu operation mode and policing path definition. the poluram access is done as described in vhfwlrq page 143. set the polu to normal mode via bit tom in the polu configuration register p_conrl (see vhfwlrq page 91). besides tagging and discarding of cells via the polu can be disabled with this register (bits disc_inh and tag_inh). the contents of the p_conrl register are transferred to the polu by setting bit valid_conf in register p_conrh (see vhfwlrq page 92). after this the lci range of the connections which should policed has to be defined using registers sc_conr1 and sc_conr2 (see vhfwlrq page 129 and vhfwlrq page 129). first write the lower lci (lcimin) to register sc_conr1 with bit polu_refr_en = 0. then write the upper lci (lcimax) to register sc_conr2. to enable the policing write lcimin to register sc_conr1 with bit polu_refr_en = 1. to stop the policing the microprocessor has to reset this bit again. &rqqhfwlrq6hwxs the following steps are required to set up a connection through the alp using the came (here e.g. for upstream direction). write the lci for the connection to the address register adr (see vhfwlrq page 128). the vci of the connection is written to the came address register camadrl (see vhfwlrq page 90). the pn and the vpi of the connection are written to the came address register camadrh (see vhfwlrq page 90). write the connection specific parameters to the write registers wdr0l and wdr0h (register see vhfwlrq page 69; for connection specific parameters see vhfwlrq page 75, dword0). if oam light functions are not used, set all oam parameters to 0. set bit vcon_up to indicate a valid connection and bit en_traf_meas_up when traffic measurement should be enabled for this connection. set registers from wdr1l to wdr6h to value 0x0000. herewith the counters are reset. write the value 0x0049 to the command register cmr (see vhfwlrq page 111). this has the effect of writing one line into the came and one entry to the connramup using the lci in register adr, the vci in register camadrl and the pn and vci in register camadrh. the connramup is written to with the contents of the write transfer registers (wdrxx). &hoo,qvhuwlrqdqg([wudfwlrq to insert user defined cells the alp provides one set of 27 registers from txr0 to txr26 (see vhfwlrq page 94). these registers can be programmed by the microprocessor. the registers from txr0 to txr2 are used to program the cell header and registers from txr3 to txr26 are used to insert the payload. after data is written to the transmit cell registers, the microprocessor can control the insertion via the configuration of the transmit cell buffer register txr_config (see vhfwlrq page 94). using bit transm_dir it is selectable whether the cell is inserted in up- or in downstream direction. bit hton is used to enable header translation.
3;%( data sheet 4-145 08.2000 2shudwlrq by setting bit start_tr the insertion starts. after the cell is inserted, the alp resets bit start_tr. it is strongly recommended not to start the transmission in upstream direction while the bit utrxfifo_ov_u in register isr0 is set to 1 (see vhfwlrq page 115). when this bit is set, an input queue overflow of the utopia receive interface upstream occurs. it is also strongly recommended not to start the transmission in downstream direction while bit bov in the register isr0 or bit ut_qov of the corresponding port (see vhfwlrq page 109 and vhfwlrq page 109) are set to 1. this indicates a buffer/queue overflow in the utopia transmit interface downstream. any cells copied or dropped from the cell stream can be read from the aop by the processor with 27 reads to the rxr register. the reads do not need to be consecutive. with bit rxr_ustr set to 1 the alp indicates that a cell is stored in the cell receive buffer. after read out the complete set of cells, this bit is reset by alp automatically. '0$&rqiljxudwlrqdqg$ffhvv the alp supports dma for a fast transfer of connection counter information from connramup and connramdo to the microprocessor ram. the microprocessor can control the dma access via three registers called dma_min, dma_max and dconr (see vhfwlrq page 136, vhfwlrq page 136 and vhfwlrq page 130). first write the range of lci values for dma transfer to the dma_min (lower lci value) and dma_max (upper lci value). then configure the dconr register, i.e. select the counters which will be reset by the dma, the delay between two dma bursts on the microprocessor bus using bits dma_delay and the direction on which the counters should read out by bit dma_ud (up- or downstream). when the dma is configurated set bit dma_start to initiate the dma transfer. with the external pin mpdreq = 0 the alp indicates that a new lci entry has been written into the alp dma buffer. the microprocessor response with setting mpack to 0. than the microprocessor can read out the connection counters by 14 read accesses to dmar in upstream or 8 read accesses to dmar in downstream direction. the inactive time between two read accesses (duration of high on mprd) must be at least one alp sysclk cycle. with mpdreq = 1 the alp indicates that the dma buffer is empty. the microprocessor has to set mpack to 1 for the dma can performe the next lci. when the next lci entry has been written to the alp dma buffer, the pin mpdreq becomes active again. the microprocessor has to repeat the read out procedure until the alp finished the dma access and indicates this state by reseting bit dma_start. note, that a fast transfer can be accomplished by connecting the external pin mpdack permanently high.
3;%( data sheet 5-146 08.2000 ,qwhuidfh'hvfulswlrq ,qwhuidfh'hvfulswlrq 8723,$,qwhuidfh utopia handshaking at the phy side: ? if one of the ports of the upstream receive line is selected (rxadru) by the alp and this port is able to transmit one cell, rxclavu is asserted. by asserting rxenbu the alp forces the transmission of a whole cell. rxsocu indicates the start of cell. ? in downstream direction the alp selects one port and if the port is able to receive one cell txclavd is asserted. when the transmission to this port starts, txenbd and the txsocd is set. utopia handshaking at the atm side: ? for the upstream transmit line the alp represents one of 24 ports. its valid port address is programmable. if the alp is selected and txclavu is asserted, then txenbu is set, if one cell is available for transmission. ? the cells downstream can be received from up to 24 ports. the selected alp with programmable port address asserts rxclavd, if it is able to receive one cell. when the transmission to this port starts, rxenbd and rxsocd is set. in the following figures three utopia configurations with the corresponding system architecture are depicted. )ljxuh depicts the alp between the phys and an other atm layer device e.g. aop, abm or asp. for this application the utopia interface at the atm side is in slave mode. )ljxuh and depicts an alp between phys used as multiplexor for access networks or backbone applications. )ljxuh 8723,$,qwhuidfh&rqiljxudwlrqzlwk6odyh0rghdwwkh$706lgh rxprtyu rxdatu(15:0) rxsocu rxclavu(3:0) rxadru(3:0) rxenbu(3:0) rx utopia slave downstream rx utopia master tx utopia slave txdatu(15:0) txsocu txadru(3:0) txenbu(3:0) txclavu(3:0) txprtyu txdatd(15:0) txsocd txadrd(3:0) txenbd(3:0) txclavd(3:0) txprtyd rxprtyd rxdatd(15:0) rxsocd rxclavd(3:0) rxadrd(3:0) rxenbd(3:0) utopia master atm-layer device stm-1 6 x 25.6 mbit/s 1 6 6 x 25.6 mbit/s 1 6 alp stm-1 tx utopia master upstream utopia master
3;%( data sheet 5-147 08.2000 ,qwhuidfh'hvfulswlrq )ljxuh 8723,$,qwhuidfh&rqiljxudwlrqzlwk0dvwhu0rghdwwkh$706lgh )ljxuh 8723,$,qwhuidfh&rqiljxudwlrqzlwk0dvwhu0rghiru7[dqg6odyh0rghiru 5['luhfwlrqdwwkh$706lgh rxprtyu rxdatu(15:0) rxsocu rxclavu(3:0) rxadru(3:0) rxenbu(3:0) rx utopia master downstream rx utopia master tx utopia master txdatu(15:0) txsocu txadru(3:0) txenbu(3:0) txclavu(3:0) txprtyu txdatd(15:0) txsocd txadrd(3:0) txenbd(3:0) txclavd(3:0) txprtyd rxprtyd rxdatd(15:0) rxsocd rxclavd(3:0) rxadrd(3:0) rxenbd(3:0) utopia slave stm-4 framer stm-1 6 x 25.6 mbit/s 1 6 6 x 25.6 mbit/s 1 6 alp stm-1 tx utopia master upstream rxprtyu rxdatu(15:0) rxsocu rxclavu(3:0) rxadru(3:0) rxenbu(3:0) rx utopia slave downstream rx utopia master tx utopia master txdatu(15:0) txsocu txadru(3:0) txenbu(3:0) txclavu(3:0) txprtyu txdatd(15:0) txsocd txadrd(3:0) txenbd(3:0) txclavd(3:0) txprtyd rxprtyd rxdatd(15:0) rxsocd rxclavd(3:0) rxadrd(3:0) rxenbd(3:0) stm-1 iwe8 1 8 1 8 alp tx utopia master upstream iwe8 iwe8 1 8
3;%( data sheet 5-148 08.2000 ,qwhuidfh'hvfulswlrq the following table gives an overview over the utopia signals: xx=rx: receive line / xx=tx: transmit line y=u: upstream / y=d: downstream zzz=phy: phy side / zzz=atm: atm side %dfnsuhvvxuh0hfkdqlvp backpressure means that cell transmission is disabled even if cells are available from the transmitting port of the preceding asic. in this case no rxenbu / rxclavd is set by the alp in response to an asserted rxclavu / txenbd . upstream line: a backpressure is only asserted if an adjacent asic asserts a backpressure to the alp. downstream line: a backpressure is asserted by the alp if an empty cell cycle time slot is needed, e.g. for microprocessor request or for cell insertion from the microprocessor add buffer, or in case of queue or buffer overflow of the statistical demultiplexing buffer. a phy overflow leads only indirectly to a backpressure when the corresponding queue of the statistical multiplexing buffer overflows. $/37kurxjksxw nominally the alp can cope with an utopia frequency of up to f utopia =51,84 mhz. however the average net cell rate over utopia interface should be significantly lower due to the limits imposed by the time needed for internal data processing at the chosen alp core frequency f core . the maximal allowed net utopia throughput is given by: b utmax = f core * 53 *8 / 32 bit/s {atm cell: 53 * 8 bit} {internal clock cycles per atm cell: 32} for f core = 51,84 mhz we get b utmax = 686,88 mbit/s. however with this throughput no empty cell time slots in the alp core will occur which are necessary for microprocessor access to external rams, insertion of cells from the add buffer as well as the refresh of policing data. the latter one reduces the maximum allowed net throughput by about 1%, while the time needed for completing microprocessor requests is inversely proportional to the frequency of empty cell time slots. in order to be able to read out e.g. the 7deoh 8723,$,qwhuidfh6ljqdov xxdaty(15:0) data bus xxadry(3:0) address xxprtyy data path parity xxenby (3:0) enable xxclavy(3:0) cell available xxsocy start of cell utzzzclk utopia clock
3;%( data sheet 5-149 08.2000 ,qwhuidfh'hvfulswlrq billing counters of 16384 connections within a time interval smaller then 0,5 seconds, the maximal allowed net throughput has to be reduced by a further 3%. ([whuqdo5$0,qwhuidfh the alp chip involves three ram interfaces, connramup and poluram for the upstream and connramdo for the downstream part. the ram interfaces support access to the external synchronous srams using bidirectional 32 bit data bus. the msb of the data bus is used as parity signal. depending on the maximum number of connections supported two ram types can be configured by the hw pin ad25 (ramver). connected to ground selects the 1m ssram(32k*32) and to high selects the 2m ssram (64k*32). the selection is identical for all three ram interfaces. the toshiba ram types tc55v1325ff-7 for 1m ssram and tc55v2325ff-7 for 2m ssram are recommended. other ram types should fulfil the specification of toshiba. &2115$083 connramup is used to store: C traffic counters. C parts of the internal header (namely hk bits). C control flags and internal pointers. the connection data for one lci requires 8 x 32bit words in the upstream connection ram, so the whole connramup has a capacity of 4mbit for 16k connections or 2 mbit for 8k connections. up to 2 ssrams are supported. 32/85$0 the poluram is used to store: C state variables and constant parameters of the policing algorithm. C control flags for upc/npc configuration. the policing data for one lci requires 11 x 32bit words in the policing ram, so the whole poluram has a capacity of 6mbit for 16k connections or 3 mbit for 8k connections. the poluram can be omitted if no upc/npc is required. up to 3 ssrams are supported.
3;%( data sheet 5-150 08.2000 ,qwhuidfh'hvfulswlrq )ljxuh &rqqhfwlrq5$08svwuhdp,qwhuidfh6ljqdov io(31:0) adsc adv gw oe ce adsp zz ce 2 bwe ce 2 bw1 bw2 bw3 bw4 mode conn ram up rda tu(31: 0) sysclk conn ram do polu ram rda td(31: 0) poldat(31:0) io(31:0) adsc adv gw oe ce adsp zz gnd +3.3 v ce 2 gnd bwe +3.3 v ce2 +3.3 v bw1 bw2 bw3 bw4 mode adsp zz gnd +3.3 v ce 2 gnd bwe +3.3 v ce2 +3.3 v bw1 bw2 bw3 bw4 mode adsp zz gnd +3.3 v ce 2 gnd bwe +3.3 v ce2 +3.3 v bw1 bw2 bw3 bw4 mode clk a(14:0) io(31:0) adsc adv gw oe ce clk a(14:0) io(31:0) adsc adv gw oe ce clk a(14:0) ? ? ? rama dr(14: 0) 32k x 32bit sram 32k x 32 bit sra m 32k x 32bit sram rama dr(17:1 5) pxb 4350 e alp 10 k w 10 k w 10 k w 1 k w 1 k w 1 k w 10 k w 10 k w 10 k w 10 k w 10 k w 10 k w 226 w 226 w 226 w poloe pol gw polce(2:0) pol adv p ola dsc( 2: 0) ro ed rgwd rced( 1: 0) rad vd rscd( 1: 0) roeu rgwu rceu(1 :0) rad vu rs cu(1 : 0)
3;%( data sheet 5-151 08.2000 ,qwhuidfh'hvfulswlrq &2115$0'2 the connramdo is used to store: C traffic counters. C the external header (i.e pn, vpi and vci). C for multicast light the pointer to the next entry of the linked list. C control flags and internal pointers. the connection data for one lci requires 7 x 32bit words in the downstream connection ram, so the whole connramdo has a capacity of 4mbit for 16k connections or 2 mbit for 8k connections. up to 2 ssrams are supported. the following table shows all possible ram configurations of the alp for the usage of the 1m and 2m ssrams types depending on the selection of ram types controlled by the hw-pin ramvers and the number of needed connections. the poluram is not fully used for the support of 8k connections with 2m ssrams. 0lfursurfhvvrudqg&rqwuro,qwhuidfh )ljxuh 0lfursurfhvvru,qwhuidfh the alp chip has an asynchronous microprocessor interface. the interface consists of an 16 bit wide common data bus with 8 address lines as required for interfacing 80x86 processors. bytewise access is not supported. the asynchronous bus access is working with a handshake mechanism for data flow control. during the inactive state the data bus is switched to high 7deoh 3rvvleoh5$0&rqiljxudwlrqvriwkh$/3 number of supported connections 16k 8k hw-pin ramver (ad25) 0 for 1m 1 for 2m 0 for 1m 1 for 2m number of connramup -221 number of connramdo -221 number of poluram -332 mpdat(15:0) mpadr(7:0) mpwr mprd mpcs mpint mprdy mpdreq mpdack 3;%( $/3 plfursurfhvvru l(;
3;%( data sheet 5-152 08.2000 ,qwhuidfh'hvfulswlrq impedance, it becomes active only when chip select is active.the pins mpdreq and mpdack are used for dma access. when dma buffer is not empty, the alp set the mpdreq pin to zero. the microprocessor can now read the dmar register and give a receipt by setting mpdack to zero. if dma buffer is empty, mpdreq will be one. 7deoh 0lfursurfhvvru,qwhuidfh6ljqdov 6ljqdo 'hvfulswlrq mpdat(15:0) bidirectional common data bus between the microprocessor and the alp. its signals will be tristated when mpcs or mprdy is high. mpadr(7:0) address bus for the interface. mpwr write signal for the interface (active low). mprd read signal for the interface (active low). mpcs chip select signal used to address the alp (active low). mpint interrupt request (active low). this pin is an open drain output. mpdreq dma request signal indicating that data is to be read out from the dma buffer (active low). after the falling edge of the last possible read access (which empties the receive buffer), the mpdreq pin becomes inactive within 60ns to avoid an additional read access of the microprocessor. mprdy ready output signal for microprocessor write and read access (active high). this pin is put low by the alp immediately after the falling edge of the microprocessor read or write signals mprd /mpwr and remains inactive until the alp has put or get the required data via the bus mpdat(15:0). during the first clock period after the low-high change it is driven high by the asic. afterwards it is held high by a pull-up. during the inactive time of mprdy the microprocessor performs wait states.
3;%( data sheet 5-153 08.2000 ,qwhuidfh'hvfulswlrq -7$*%rxqgdu\6fdq,qwhuidfh )ljxuh -7$*%rxqgdu\6fdq,qwhuidfh the jatg/boundary scan pins trst , tdi, tck, tms, and tdo are required for board test purposes. the boundary scan is conformal to ieee 1149.1a (jtag) serial test bus protocol and the specification [7]. the id code of the alp can be read out from the boundary scan identity code register. the boundary scan id number is 523b9069h. additionally internal control pads are provided to switch specific output or input/output pins to tristate. 1rwh&rqwurosdglvdfwlyhkljkdqgvzlwfkhvwkhfruuhvsrqglqjslqrujurxsrislqvwrwulvwdwh 7deoh %rxqgdu\6fdq,qwhuidfh trst asynchronous reset for the test-access-port-controller tdi test data input with internal pull-up resistor tck test clock with internal pull-up resistor tms test mode select input with internal pull-up resistor tdo test data output 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh 0b24mpcs i 1a24mpint o 2d22mpdack i 3 - control pad for mpdreq - 4 b23 mpdreq o tdo 3;%( $/3 tms tdi tck trst
3;%( data sheet 5-154 08.2000 ,qwhuidfh'hvfulswlrq 5 - control pad for mprdy - 6 c23 mprdy o 7 - control pad for mpdat(15:0) - 8 a23 mpdat(0) i/o 10 d21 mpdat(1) i/o 12 b22 mpdat(2) i/o 14 c22 mpdat(3) i/o 16 a22 mpdat(4) i/o 18 d20 mpdat(5) i/o 20 b21 mpdat(6) i/o 22 c21 mpdat(7) i/o 24 a21 mpdat(8) i/o 26 d19 mpdat(9) i/o 28 b20 mpdat(10) i/o 30 c20 mpdat(11) i/o 32 a20 mpdat(12) i/o 34 d18 mpdat(13) i/o 36 b19 mpdat(14) i/o 38 c19 mpdat(15) i/o 40 a19 rxdatu(0) i 41 d17 rxdatu(1) i 42 b18 rxdatu(2) i 43 c18 rxdatu(3) i 44 a18 rxdatu(4) i 45 d16 rxdatu(5) i 46 b17 rxdatu(6) i 47 c17 rxdatu(7) i 48 a17 rxdatu(8) i 49 d15 rxdatu(9) i 50 b16 rxdatu(10) i 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-155 08.2000 ,qwhuidfh'hvfulswlrq 51 c16 rxdatu(11) i 52 a16 rxdatu(12) i 53 b15 rxdatu(13) i 54 d14 rxdatu(14) i 55 c15 rxdatu(15) i 56 - control pad for rxadru(3:0), rxenbu (3:0), txdatd(15:0), txadrd(3:0), txprtyd, txenbd (3:0) and txsocd - 57 a15 rxadru(0) o 58 b14 rxadru(1) o 59 a14 rxadru(2) o 60 c14 rxadru(3) o 61 c13 rxprtyu i 62 b13 rxenbu (0) o 63 a13 rxenbu (1) o 64 d13 rxenbu (2) o 65 c12 rxenbu (3) o 66 b12 rxclavu(0) i 67 a12 rxclavu(1) i 68 d12 rxclavu(2) i 69 c11 rxclavu(3) i 70 b11 rxsocu i 71 a11 utphyclk i 72 b10 txdatd(0) o 73 d11 txdatd(1) o 74 c10 txdatd(2) o 75 a10 txdatd(3) o 76 b9 txdatd(4) o 77 d10 txdatd(5) o 78 c9 txdatd(6) o 79 a9 txdatd(7) o 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-156 08.2000 ,qwhuidfh'hvfulswlrq 80 b8 txdatd(8) o 81 c8 txdatd(9) o 82 a8 txdatd(10) o 83 d9 txdatd(11) o 84 b7 txdatd(12) o 85 a7 txdatd(13) o 86 c7 txdatd(14) o 87 d8 txdatd(15) o 88 b6 txadrd(0) o 89 a6 txadrd(1) o 90 c6 txadrd(2) o 91 b5 txadrd(3) o 92 d7 txprtyd o 93 c5 txenbd (0) o 94 a5 txenbd (1) o 95 b4 txenbd (2) o 96 d6 txenbd (3) o 97 c4 txclavd(0) i 98 a4 txclavd(1) i 99 b3 txclavd(2) i 100 d5 txclavd(3) i 101 a3 txsocd o 102 - control pad for poldat(31:0) - 103 b1 poldat(0) i/o 105 c2 poldat(1) i/o 107 c1 poldat(2) i/o 109 e4 poldat(3) i/o 111 d2 poldat(4) i/o 113 d3 poldat(5) i/o 115 d1 poldat(6) i/o 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-157 08.2000 ,qwhuidfh'hvfulswlrq 117 f4 poldat(7) i/o 119 e2 poldat(8) i/o 121 e3 poldat(9) i/o 123 e1 poldat(10) i/o 125 g4 poldat(11) i/o 127 f2 poldat(12) i/o 129 f3 poldat(13) i/o 131 f1 poldat(14) i/o 133 h4 poldat(15) i/o 135 g2 poldat(16) i/o 137 g3 poldat(17) i/o 139 g1 poldat(18) i/o 141 j4 poldat(19) i/o 143 h2 poldat(20) i/o 145 h3 poldat(21) i/o 147 h1 poldat(22) i/o 149 k4 poldat(23) i/o 151 j2 poldat(24) i/o 153 j3 poldat(25) i/o 155 j1 poldat(26) i/o 157 l4 poldat(27) i/o 159 k2 poldat(28) i/o 161 k3 poldat(29) i/o 163 k1 poldat(30) i/o 165 m4 poldat(31) i/o 167 l2 poladsc (0) o 168 l3 poladsc (1) o 169 l1 poladsc (2) o 170 m2 poladv o 171 n4 polce (0) o 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-158 08.2000 ,qwhuidfh'hvfulswlrq 172 m3 polce (1) o 173 m1 polce (2) o 174 n2 polgw o 175 n1 poloe o 176 - control pad for rdatu(31:0) - 177 n3 rdatu(0) i/o 179 p3 rdatu(1) i/o 181 p2 rdatu(2) i/o 183 p1 rdatu(3) i/o 185 p4 rdatu(4) i/o 187 r3 rdatu(5) i/o 189 r2 rdatu(6) i/o 191 r1 rdatu(7) i/o 193 r4 rdatu(8) i/o 195 t3 rdatu(9) i/o 197 t2 rdatu(10) i/o 199 t1 rdatu(11) i/o 201 u2 rdatu(12) i/o 203 t4 rdatu(13) i/o 205 u3 rdatu(14) i/o 207 u1 rdatu(15) i/o 209 v2 rdatu(16) i/o 211 u4 rdatu(17) i/o 213 v3 rdatu(18) i/o 215 v1 rdatu(19) i/o 217 w2 rdatu(20) i/o 219 w3 rdatu(21) i/o 221 w1 rdatu(22) i/o 223 v4 rdatu(23) i/o 225 y2 rdatu(24) i/o 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-159 08.2000 ,qwhuidfh'hvfulswlrq 227 y1 rdatu(25) i/o 229 y3 rdatu(26) i/o 231 w4 rdatu(27) i/o 233 aa2 rdatu(28) i/o 235 aa1 rdatu(29) i/o 237 aa3 rdatu(30) i/o 239 ab2 rdatu(31) i/o 241 y4 rscu (0) o 242 ab3 rscu (1) o 243 ab1 radvu o 244 ac2 rceu (0) o 245 aa4 rceu (1) o 246 ac3 rgwu o 247 ac1 roeu o 248 ad2 ramadr(0) o 249 ab4 ramadr(1) o 250 ad1 ramadr(2) o 251 af2 ramadr(3) o 252 ae3 ramadr(4) o 253 af3 ramadr(5) o 254 ac5 ramadr(6) o 255 ae4 ramadr(7) o 256 ad4 ramadr(8) o 257 af4 ramadr(9) o 258 ac6 ramadr(10) o 259 ae5 ramadr(11) o 260 ad5 ramadr(12) o 261 af5 ramadr(13) o 262 ac7 ramadr(14) o 263 ae6 ramadr(15) o 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-160 08.2000 ,qwhuidfh'hvfulswlrq 264 ad6 ramadr(16) o 265 af6 ramadr(17) o 266 - control pad for rdatd(31:0) - 267 ac8 rdatd(0) i/o 269 ae7 rdatd(1) i/o 271 ad7 rdatd(2) i/o 273 af7 rdatd(3) i/o 275 ac9 rdatd(4) i/o 277 ae8 rdatd(5) i/o 279 ad8 rdatd(6) i/o 281 af8 rdatd(7) i/o 283 ac10 rdatd(8) i/o 285 ae9 rdatd(9) i/o 287 ad9 rdatd(10) i/o 289 af9 rdatd(11) i/o 291 ac11 rdatd(12) i/o 293 ae10 rdatd(13) i/o 295 ad10 rdatd(14) i/o 297 af10 rdatd(15) i/o 299 ac12 rdatd(16) i/o 301 ae11 rdatd(17) i/o 303 ad11 rdatd(18) i/o 305 af11 rdatd(19) i/o 307 ae12 rdatd(20) i/o 309 ac13 rdatd(21) i/o 311 ad12 rdatd(22) i/o 313 af12 rdatd(23) i/o 315 ae13 rdatd(24) i/o 317 af13 rdatd(25) i/o 319 ad13 rdatd(26) i/o 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-161 08.2000 ,qwhuidfh'hvfulswlrq 321 ad14 rdatd(27) i/o 323 ae14 rdatd(28) i/o 325 af14 rdatd(29) i/o 327 ac14 rdatd(30) i/o 329 ad15 rdatd(31) i/o 331 ae15 rscd (0) o 332 af15 rscd (1) o 333 ac15 radvd o 334 ad16 rced (0) o 335 ae16 rced (1) o 336 af16 rgwd o 337 ae17 roed o 338 ac16 sysclk i 339 ad17 reset i 340 - control pad for arcdat(16:0) - 341 af17 arcdat(0) i/o 343 ae18 arcdat(1) i/o 345 ac17 arcdat(2) i/o 347 ad18 arcdat(3) i/o 349 af18 arcdat(4) i/o 351 ae19 arcdat(5) i/o 353 ad19 arcdat(6) i/o 355 af19 arcdat(7) i/o 357 ac18 arcdat(8) i/o 359 ae20 arcdat(9) i/o 361 af20 arcdat(10) i/o 363 ad20 arcdat(11) i/o 365 ac19 arcdat(12) i/o 367 ae21 arcdat(13) i/o 369 af21 arcdat(14) i/o 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-162 08.2000 ,qwhuidfh'hvfulswlrq 371 ad21 arcdat(15) i/o 373 ae22 arcdat(16) i/o 375 ac20 arcadr(0) o 376 ad22 arcadr(1) o 377 af22 arcadr(2) o 378 ae23 arcadr(3) o 379 ac21 arcres o 380 ad23 arccs o 381 af23 arcwe o 382 ae24 arcoe o 383 ac22 arcclk o 384 af24 smode i 385 ae26 senab i 386 ad25 ramvers i 387 - control pad for rxclavd(0) - 388 - control pad for rxclavd(1) - 389 - control pad for rxclavd(2) - 390 - control pad for rxclavd(3) - 391 ac26 rxclavd(0) i/o 393 aa23 rxclavd(1) i/o 395 ab25 rxclavd(2) i/o 397 ab24 rxclavd(3) i/o 399 ab26 rxdatd(0) i 400 y23 rxdatd(1) i 401 aa25 rxdatd(2) i 402 aa24 rxdatd(3) i 403 aa26 rxdatd(4) i 404 w23 rxdatd(5) i 405 y25 rxdatd(6) i 406 y24 rxdatd(7) i 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-163 08.2000 ,qwhuidfh'hvfulswlrq 407 y26 rxdatd(8) i 408 v23 rxdatd(9) i 409 w25 rxdatd(10) i 410 w24 rxdatd(11) i 411 w26 rxdatd(12) i 412 u23 rxdatd(13) i 413 v25 rxdatd(14) i 414 v24 rxdatd(15) i 415 v26 rxprtyd i 416 - control pad for rxadrd(3:0) and rxenbd (3:0) - 417 t23 rxadrd(0) i/o 419 u25 rxadrd(1) i/o 421 u24 rxadrd(2) i/o 423 u26 rxadrd(3) i/o 425 r23 rxenbd (0) i/o 427 t25 rxenbd (1) i/o 429 t24 rxenbd (2) i/o 431 t26 rxenbd (3) i/o 433 r25 rxsocd i 434 p23 txms i 435 r24 rxms i 436 r26 utatmclk i 437 - control pad for txdatu(15:0), txprtyu and txsocu - 438 p26 txdatu(0) o 439 p24 txdatu(1) o 440 n24 txdatu(2) o 441 n25 txdatu(3) o 442 n26 txdatu(4) o 443 n23 txdatu(5) o 444 m24 txdatu(6) o 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-164 08.2000 ,qwhuidfh'hvfulswlrq 445 m25 txdatu(7) o 446 m26 txdatu(8) o 447 m23 txdatu(9) o 448 l24 txdatu(10) o 449 l25 txdatu(11) o 450 l26 txdatu(12) o 451 k25 txdatu(13) o 452 l23 txdatu(14) o 453 k24 txdatu(15) o 454 k26 txprtyu o 455 - control pad for txclavu(0) - 456 - control pad for txclavu(1) - 457 - control pad for txclavu(2) - 458 - control pad for txclavu(3) - 459 j25 txclavu(0) i/o 461 k23 txclavu(1) i/o 463 j24 txclavu(2) i/o 465 j26 txclavu(3) i/o 467 h25 txsocu o 468 - control pad for txadru(3:0) and txenbu (3:0) - 469 h24 txadru(0) i/o 471 h26 txadru(1) i/o 473 j23 txadru(2) i/o 475 g25 txadru(3) i/o 477 g26 txenbu (0) i/o 479 g24 txenbu (1) i/o 481 h23 txenbu (2) i/o 483 f25 txenbu (3) i/o 485 f26 mpadr(0) i 486 f24 mpadr(1) i 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh
3;%( data sheet 5-165 08.2000 ,qwhuidfh'hvfulswlrq &orfn$qg5hvhw,qwhuidfh )ljxuh &orfndqg5hvhw,qwhuidfh alp system clock (sysclk): the alp system (core) clock range is 25 mhz up to 51.84 mhz. reset input signal (reset ): the reset signal is fed in via a lvttl-compatible input. with low level (gnd) it causes an asynchronous reset of the internal circuit. the reset must be asserted for a minimum of four clock cycles. after the reset is accepted the outputs are hold in inactive state and all bidirectional i/os are switched to tristate until reset is released. at the low to high transition on the reset line follows an internal synchronous reset. utopia clocks (utphyclk, utatmclk): two utopia clock inputs (one for the phy- and one for the atm- side), independent from each other and from sysclk, must be provided. the frequency of the utopia clocks must be lower than or equal to sysclk. 487 e25 mpadr(2) i 488 g23 mpadr(3) i 489 e24 mpadr(4) i 490 e26 mpadr(5) i 491 d25 mpadr(6) i 492 f23 mpadr(7) i 493 d24 mpwr i 494 d26 mprd i 7deoh $/3%rxqgdu\6fdq7deoh %rxqgdu\6fdq 1xpehu 3,11u 6ljqdo1dph 7\sh 3;%( $/3 reset utphyclk sysclk utatmclk arcres arcclk
3;%( data sheet 5-166 08.2000 ,qwhuidfh'hvfulswlrq came clock (arcclk): it is derived from sysclk by dividing frequency by a factor of two. came reset output signal (arcres ): it is a lvcmos low active output. it is asserted by alp for four sysclk periods after the rising edge of reset . &$0(,qwhuidfh )ljxuh &$0(,qwhuidfhirun&rqqhfwlrqv arcclk arccs arcwe arcoe arcres arcadr(3:0) arcdat(16:0) clk cs we oe res adr(3:0) dat(16:0) en16 dat(32:17) 1k w gnd came alp clk cs we oe res adr(3:0) dat(16:0) en16 dat(32:17) 1k w gnd came ca ca 1k w gnd + 3.3 v 10k w + 3.3 v 10k w ci(2:0) co(2:0) (master) (slave) c o(2:0) c i(2:0 ) + 3.3 v 10k w
3;%( data sheet 5-167 08.2000 ,qwhuidfh'hvfulswlrq )ljxuh &$0(,qwhuidfhirun&rqqhfwlrqv for the address reduction of the 32 bit input address consisting of concatenated pn/vpi/vci values down to the 14 bit lci up to two parallel cascaded came chips are supported. from the alps perspective they behave like a single chip. in nni mode the sum of the length of pn (up to 6 bit), vpi (12bit) and vci (16bit) exceed 32bit, which can be maximally processed by came. in this case only the (16 - (number of pn bits)) least significant vpi bits are mapped into the input address. during the connection setup the cames are initialized by sw, i.e. the input addresses (pn/vpi/ vci) of valid connections are stored at the addresses of the corresponding lcis. at cell arrival an inverse operation is performed: the pn/vpi/vci value of the cell is passed to the cames, which search for an corresponding entry and return its lci. in some important cases (e.g. the alp is configurated as an intermediate point of a virtual path, or f4-oam cells are received at a virtual path terminating point) pure pn/vpi translation takes place and the vci part is ignored. arcclk is half of the alp core frequency given by sysclk. arcclk arccs arcwe arcoe arcres arcadr(3:0) ar cdat(16:0) clk cs we oe res adr(3:0) dat(16:0) en16 dat(32:17) 1k w came ca + 3.3 v ci(2:0) co(2:0) (master) alp 1 k w gnd gnd 10 k w
3;%( data sheet 5-168 08.2000 ,qwhuidfh'hvfulswlrq 'dwd6wuxfwxuhdw&$0('dwd%xv came data bit(16) is used as parity line and completes the arcdat(1:15) and acradr(0:3) to odd parity. 6hdufksurfhvvlqjiru2$0))orz 6hdufksurfhvvlqjiruxvhufhoov 6hdufksurfhvvlqjdfwlydwhgyldwkhplfursurfhvvru bit:1514131211109876543210 write to address c h pn(3:0) vpi(11:0) wait for command execution read from address 6 h v i lci(13:0) read from address e h s3 s2 s1 s0 bit:1514131211109876543210 write to address d h pn(3:0) vpi(11:0) write to address 5 h vci(15:0) wait for command execution read from address 6 h v i lci(13:0) read from address e h s3 s2 s1 s0 bit:1514131211109876543210 write to address e h pn(3:0) vpi(11:0) write to address 6 h vci(15:0) wait for command execution read from address 6 h v i lci(13:0) read from address e h s3 s2 s1 s0
3;%( data sheet 5-169 08.2000 ,qwhuidfh'hvfulswlrq &$0(:ulwhfrppdqgirufrqiljxudwlrqriwkhfrqqhfwlrq &$0(5hdgfrppdqgiruyhulilfdwlrqriwkhfrqqhfwlrqhqwu\ &$0(7hvwdqg&rqiljxudwlrqfrppdqg 7hvw,qwhuidfh there are several additional test pins provided for board test. please let them unconnected or connected to ground as described in section 1.4, part "additional testpins". bit:1514131211109876543210 write to address 2 h v i lci(13:0) write to address b h pn(3:0) vpi(11:0) write to address 3 h vci(15:0) wait for command execution read from address 6 h read from address e h s3 s2 s1 s0 bit:1514131211109876543210 write to address 0 h lci(13:0) wait for command execution read from address 1 h pn(3:0) vpi(11:0) read from address 9 h vci(15:0) read from address 6 h vi read from address e h s3 s2 s1 s0 bit:1514131211109876543210 write to address 7 h testmode(13:0) wait for command execution read from address 7 h testmode(13:0) read from address f h s3 s2 s1 s0
3;%( data sheet 6-170 08.2000 (ohfwulfdo&kdudfwhulvwlfv (ohfwulfdo&kdudfwhulvwlfv $evroxwh0d[lpxp5dwlqjv 1rwh 6wuhvvhv deryh wkrvh olvwhg khuh pd\ fdxvh shupdqhqw gdpdjh wr wkh ghylfh ([srvxuh wr devroxwh pd[lpxpudwlqjfrqglwlrqviruh[whqghgshulrgvpd\diihfwghylfhuholdelolw\ 2shudwlqj&rqglwlrqv 7deoh $evroxwh0d[lpxp5dwlqjv 3dudphwhu 6\pero /lplw9doxhv 8qlw storage temperature 7 s -40 to 125 c junction temperature 7 j max. 125 c supply voltage 9 dd -0.3 to 3.9 v input voltage for 3.3v pads 9 in -1.0 to 9 dd +0.3 v input voltage for 5v compatible pads 9 in -1.0 to 6.5 v output voltage 9 out v dc input currents , in -10 to 10 m a power dissipation 3 v 1.7 w 7deoh 2shudwlqj&rqglwlrqv 3dudphwhu 6\pero /lplw9doxhv 8qlw supply voltage 9 dd 3.14 to 3.47 v ground 9 ss 0v ambient temperature under bias 7 a -45 to 85 c junction temperature 7 j max. 110 c
3;%( data sheet 6-171 08.2000 (ohfwulfdo&kdudfwhulvwlfv '&&kdudfwhulvwlfvirudoo,qwhuidfhv 1rwh 7kh olvwhg fkdudfwhulvwlfv duh hqvxuhg ryhu wkh rshudwlqj udqjh ri wkh lqwhjudwhg flufxlw 7\slfdo fkdudfwhulvwlfv vshfli\ phdq ydoxhv h[shfwhg ryhu wkh surgxfwlrq vsuhdg ,i qrw rwkhuzlvh vshflilhg w\slfdofkdudfwhulvwlfvdsso\dw 7 $ &dqgwkhjlyhqvxsso\yrowdjh 7deoh '&&kdudfwhulvwlfv 3dudphwhu 6\pero /lplw9doxhv 8qlw 7hvw&rqglwlrq plq w\s pd[ supply voltage 9 dd 3.14 3.3 3.47 v input low voltage 9 il 9 ss -0.5 0.8 v input high voltage 9 ih 2.0 9 dd +0.3 v lvttl (3.3v) 2.0 5.5 v 5-volt compatible switching threshold 9 t 1.4 2.0 v input current , in -10 -1..+1 10 m a 9 in = 9 dd or 9 ss 35 115 222 m a 9 in = 9 dd for inputs with pulldown resistors -35 -115 -214 m a 9 in = 9 ss for inputs with pullup resistors output high voltage 9 oh 2.4 9 dd v , oh = - 4 ma output low voltage 9 ol 0.2 0.4 v , oh = 4 ma three-state output leakage current , oz -10 -1..+1 10 m a input capacitance & in 2.5 5 pf output capacitance & out 25 pf
3;%( data sheet 6-172 08.2000 (ohfwulfdo&kdudfwhulvwlfv &dsdflwdqfhv $&&kdudfwhulvwlfv 7 a = -40 to 85 c , 9 cc = 3.3 v 5 % , 9 ss = 0 v all inputs are driven to 9 ih = 2.4 v for a logical 1 and to 9 il = 0.4 v for a logical 0 all outputs are measured at 9 h = 2.0 v for a logical 1 and at 9 l = 0.8 v for a logical 0 the ac testing input/output waveforms are shown below. )ljxuh ,qsxw2xwsxw:dyhirupiru$&0hdvxuhphqwv 7deoh &dsdflwdqfhv 3dudphwhu 6\pero /lplw9doxhv 8qlw plq pd[ input capacitance & in 2.5 5 pf output capacitance & out 25pf load capacitance at: utopia phy side ramadr(17:0) mpdat(15:0), mprd poluramdat(31:0) other outputs & fo1 & fo2 & fo3 & fo4 & fo5 85 85 50 40 30 pf pf pf pf pf test points ac_int.ds4 v h device under test c load = 50 pf max v h v l v l
3;%( data sheet 6-173 08.2000 (ohfwulfdo&kdudfwhulvwlfv &orfndqg5hvhw,qwhuidfh )ljxuh &orfndqg5hvhw,qwhuidfh7lplqj'ldjudp 7deoh &orfndqg5hvhw,qwhuidfh$&7lplqj&kdudfwhulvwlfv 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 1 7 sysclk : period sysclk 19.3 ns 1a ) sysclk : frequency sysclk 51.84 mhz 2 delay sysclk to arcclk 3 15 ns 3 7 arcclk : period arcclk 38.6 ns 3a ) arcclk : frequency arcclk 25.92 mhz 4 pulse width reset low 5 7 sysclk 7deoh &orfn)uhtxhqflhv 3dudphwhu 6\pero /lplw9doxhv 8qlw plq pd[ core-clock sysclk 25 51.84 mhz utopia clock at phy-side utphyclk < i sysclk mhz utopia clock at atm-side utatmclk < i sysclk mhz m p clock 1) 1) supplied only to i386ex p < i sysclk /2 mhz sysclk arcclk reset 1 2 3 4
3;%( data sheet 6-174 08.2000 (ohfwulfdo&kdudfwhulvwlfv '0$,qwhuidfh )ljxuh '0$,qwhuidfh7lplqj'ldjudp 8723,$,qwhuidfh the ac characteristic of the utopia interface fulfils the utopia standard [1 and 2]. 7deoh &orfndqg5hvhw,qwhuidfh$&7lplqj&kdudfwhulvwlfv 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 1 7 clk2 : period clk2 40 ns 1a ) clk2 : frequency clk2 25 mhz 2 7 rdmpdreq 90 ns 3 7 sysclk : period sysclk 7 sysclk ns 4 7 rdmpack 200 ns 12345678 386ex: clk2 2 3 4 t1 t2 t2 ph2 ph1 ph2 ph1 ph2 ph1 ph2 1 386ex: clkout 386ex: rd mpdack mpdreq
3;%( data sheet 6-175 08.2000 (ohfwulfdo&kdudfwhulvwlfv 65$0,qwhuidfh )ljxuh 65$0,qwhuidfh*hqhulf7lplqj'ldjudp 1rwh 7kh665$0lqwhuidfhlvghvljqhgwrixoilowkh7rvkled665$0vshflilfdwlrq7\sh7&9))0 665$0n[ru7\sh7&9))0665$0n[,irwkhu665$0?vduhxvhgsohdvh fkhfnzkhwkhuwkhvhduhfrpsoldqwwr7rvkled7kh$/3grhvqrwxvhwkh%:($'63dqg6qr r]hprgh 7deoh 65$0,qwhuidfh$&7lplqj&kdudfwhulvwlfvirus)/rdg 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 1 7 sysclk : period sysclk 19.3 ns 1a ) sysclk : frequency sysclk 51.84 mhz 2 sysclk low pulse width 40 60 % 3 sysclk high pulse width 40 60 % 4 delay sysclk rising to adsc , adv , a(14:0), gw , ce , oe 215ns 5 delay sysclk rising to rdatx / poldat output 215ns 6 setup time rdatx / poldat input before sysclk rising (all read cycles) 10 ns 7 hold time rdatx / poldat input after sysclk rising (all read cycles) 2ns 1 23 4 5 7 6 sysclk adsc, adv, a(17:0) rdatx / poldat input rdatx / poldat output gw, ce, oe
3;%( data sheet 6-176 08.2000 (ohfwulfdo&kdudfwhulvwlfv 0lfursurfhvvru,qwhuidfh 0lfursurfhvvru:ulwh&\foh )ljxuh 0lfursurfhvvru:ulwh&\foh7lplqj'ldjudp 7deoh 0lfursurfhvvru:ulwh&\foh$&7lplqj&kdudfwhulvwlfv 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 1 setup time mpadr before mpcs low 0 ns 2 setup time mpcs before mpwr low 0 ns 3 delay mprdy low after mpwr low 1 15 ns 4 mpdat setup time before mpwr high 5 ns 5 pulse width mprdy low 3 x 7 clock 4 x 7 clock ns 6 mprdy high to mpwr high 10 ns 7 hold time mpdat after mpwr high 5 ns 8 hold time mpcs after mpwr high 5 ns 9 hold time mpadr after mpwr high 5 ns mpcs mpdat 1 mpadr mpwr mprdy 4 3 2 9 8 7 5 itd4 6
3;%( data sheet 6-177 08.2000 (ohfwulfdo&kdudfwhulvwlfv 0lfursurfhvvru5hdg&\foh )ljxuh 0lfursurfhvvru5hdg&\foh7lplqj'ldjudp 7deoh 0lfursurfhvvru5hdg&\foh$&7lplqj&kdudfwhulvwlfv 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 1 setup time mpadr before mpcs low 0 ns 2 setup time mpcs before mprd low 0 ns 3 delay mprdy low after mprd low 1 15 ns 4 pulse width mprdy low 4 x 7 clock 5 x 7 clock ns 5 mpdat valid before mprdy high 5 ns 6 mprdy high to mprd high 5 ns 7 hold time mpdat after mprd high 2 ns 8 hold time mpcs after mprd high 5 ns 9 hold time mpadr after mprd high 5 ns 10 delay mprd low to mpdat low impedance 115ns 11 delay mprd high to mpdat high impedance 115ns
3;%( data sheet 6-178 08.2000 (ohfwulfdo&kdudfwhulvwlfv %rxqgdu\6fdq7hvw,qwhuidfh )ljxuh %rxqgdu\6fdq7hvw,qwhuidfh7lplqj'ldjudp 7deoh %rxqgdu\6fdq7hvw,qwhuidfh$&7lplqj&kdudfwhulvwlfv 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 1 7 tck : period tck 100 ns 1a ) tck : frequency tck 10 mhz 2 setup time tms, tdi before tck rising 10 ns 3 hold time tms, tdi after tck rising 10 ns 4 delay tck falling to tdo valid 10 ns 5 delay tck falling to tdo high impedance 10 ns 6 pulse width trst low 200 ns itt10215 1 2 4 5 trst tdi tck 3 6 tms tdo
3;%( data sheet 6-179 08.2000 (ohfwulfdo&kdudfwhulvwlfv $&&kdudfwhulvwlfvri&$0(,qwhuidfh )ljxuh ([dpsohri([hfxwlrq7lplqjiru:ulwh&rppdqg5htxhvw 7deoh 'xudwlrqri&rppdqg([hfxwlrq 3dudphwhu /lplw9doxhv 8qlw plq w\s pd[ cell processing search, pn/vpi reduction 13 clock cycles cell processing search, pn/vpi/vci reduction 14 clock cycles search request by the microprocessor 14 clock cycles came write command 10 clock cycles came read command 13 clock cycles test and configuration of the came 9 clock cycles arcclk arccs arcoe arcwe arcadr(3:0) arcdat(16:0) 12 n-1 n start (first write) end (last read)
3;%( data sheet 6-180 08.2000 (ohfwulfdo&kdudfwhulvwlfv )ljxuh &$0(5hdg&\foh )ljxuh &$0(:ulwh&\foh arcclk arccs arcoe arcwe 4 arcadr(3:0) arcdata(16:0) sysclk 4 4 4 4 4 4 4 4 6 5 1 2 3 arcclk arccs arcoe arcwe arcadr(3:0) arcdata(16:0) sysclk 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3
3;%( data sheet 6-181 08.2000 (ohfwulfdo&kdudfwhulvwlfv 7deoh 3dudphwhuviru5hdg:ulwh$ffhvv 1r 3dudphwhu /lplw9doxhv 8qlw plq w\s pd[ 1 arcclk frequency 0.01 25.92 mhz 2 arcclk low pulse width 40 60 % 3 arcclk high pulse width 40 60 % 4 path delay syclk to arcclk, arccs , arcwe , arcoe, arcadr, and arcdat 315ns 5 setup time of arcdat in read cycle to sysclk - 5ns 6 hold time of arcdat in read cycle from sysclk - 4ns
3;%( data sheet 7-182 08.2000 3dfndjh2xwolqhv 3dfndjh2xwolqhv 3%*$ (plastic ball grid array) gpa05990 )ljxuh 6ruwvri3dfnlqj package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
3;%( data sheet 7-183 08.2000 3dfndjh2xwolqhv 7deoh 7khupdo5hvlvwdqfh 3dudphwhu 6\pero /lplw9doxhv 8qlw junction to case 5 thjc 3.8 k/w junction to ambient air without air flow 5 thja 18.7 k/w junction to ambient air with air flow 1.0 m/s 5 thja 16.2 k/w junction to ambient air with air flow 2.0 m/s 5 thja 15.2 k/w junction to ambient air with air flow 3.0 m/s 5 thja 14.4 k/w
3;%( data sheet 8-184 08.2000 5hihuhqfhv 5hihuhqfhv 1. utopia level 1 specification version 2.01, march 21, 1994, atm forum 2. utopia level 2 specification version 1.0, june 1995, atm forum 3. ieee 1596.3 standard for low-voltage differential signals for sci, draft 1.3, nov. 95 4. joint test action group jtag standard ieee std. 1149.1 5. t. worster, w. fischer, s. davis, a. hayter, buffering and flow control for statistical multiplexing in an atm switch, international switching symposium iss95, april 1995 6. atm networks: concepts, protocols, applications, h?ndel, schr?der, huber, addison- wesley, 1994, isbn 0-201-42274-3 7. itu-t recommendation i.610 b-isdn operation and maintenance principles and functions, 11/95 8. bellcore ta-nwt 1248 9. pxb 4360 e came, data sheet 04.2000 ds2 $furq\pv ? abm = pxb 4330 e $ tm % uffer 0 anager ? abr = $ vailable % it 5 ate ? abt = $ tm % lock 7 ransfer ? ais = $ larm , ndication 6 ignal (oam function) ? alp = pxb 4350 e $ tm / ayer 3 rocessor ? aop = pxb 4340 e $ tm 2 am 3 rocessor ? arc = $ ddress 5 eduction & ircuit (came pxb 4360 e) ?bip-16 = % it , nterleaved 3 arity, 16 bit ?br = % ackward 5 eporting (pm function) ? byte = octet = 8 bit ? came = & ontent $ ddressable 0 emory ( lement ?cc = & ontinuity & heck (oam function) ?cca = & ontinuity & heck $ ctivation ?cdv = & ell ' elay 9 ariation ?clp = & ell / oss 3 riority of standardized atm cell ?dbr = ' eterministic % it 5 ate ? double word = 32 bit ? f4 = virtual path layer ? f5 = virtual channel layer ? fifo = ) irst- l n- i irst- r ut buffer ?fm = ) orward 0 onitoring (pm cell type) ?hk = + ouse . eeping bits of udf1 field in utopia cell format ?ht = + eader 7 ranslation ? i/o = , nput / 2 utput ? icc = , nternal & ontinuity & heck (proprietary oam function) ?ip = , ntermediate 3 oint ?itu-t = , nternational 7 elecommunications 8 nion - 7 elecommunications standardization sector ? iwe8 = pxb 4220 , nter z orking ( lement for 8 channels ?lb = / oop e ack (oam function) ?lb = / eaky % ucket ?lci = / ocal & onnection , dentifier
3;%( data sheet 8-185 08.2000 5hihuhqfhv ? lic = / ine , nterface & ard or line interface circuit ? loc = / oss 2 f & ontinuity (oam state) ?lps = / ine 3 rotection 6 witching ?lsb = / east 6 ignificant % it ?mbs = 0 aximum % urst 6 ize ? mcr = 0 inimum & ell 5 ate ?npc = 1 etwork 3 arameter & ontrol ? octet = byte = 8 bit ?oam = 2 peration d nd 0 aintenance ?oep = 2 riginating ( nd 3 oint ?osp = 2 riginating 6 egment 3 oint ? pcr = 3 eak & ell 5 ate ?pm = 3 erformance 0 onitoring (oam function) ?pn = 3 ort 1 umber ?pti = 3 ayload 7 ype , ndication field of standardized atm cell ?ram = 5 andom $ ccess 0 emory ?rdi = 5 emote ' efect , ndication (oam function) ?rm = 5 esource 0 anagement cell ? rwr ram = p read/write ram ? rxr ram = rx 12 cell extraction buffer ? scr = 6 ustainable & ell 5 ate ? ssram = 6 ynchronous 6 tatic 5$0 ?tbd = w o e e g efined ? tep = 7 erminating ( nd 3 oint ?tm = 7 raffic 0 anagement ?trm ram = 7u affic 0 easurement port table ? ucw ram = upstream workbench ?upc = 8 ser 3 arameter & ontrol ?utopia = 8 niversal 7 est and 2s eration , nterface for $ tm ? utrxd buffer = 87 opia 5[ - g ownstream cell fifo ? utrxu buffer = 87 opia 5[ - x pstream cell fifo ? uttxd buffer = 87 opia 7[ - g ownstream shared memory buffer ? uttxu buffer = 87 opia 7[ - x pstream cell fifo ?vc- = 9 irtual & hannel specific ? vcc = 9 irtual & hannel & onnection ?vci = 9 irtual & hannel , dentifier of standardized atm cell ? vp- = 9 irtual 3 ath specific ? vpc = 9 irtual 3 ath & onnection ? vpi = 9 irtual 3 ath , dentifier of standardized atm cell ? word = 16 bit

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