1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com hi-reliability product edi88128cs 128kx8 monolithic sram, smd 5962-89598 features n access times of 15*, 17, 20, 25, 35, 45, 55ns n cs and oe functions for bus control n 2v data retention (edi88128lps) n ttl compatible inputs and outputs n fully static, no clocks n organized as 128kx8 n commercial, industrial and military temperature ranges n thru-hole and surface mount packages jedec pinout ? 32 pin ceramic dip, 400 mil (package 102) ? 32 pin ceramic dip, 600 mil (package 9) ? 32 lead ceramic zip (package 100) ? 32 lead ceramic soj (package 140) ? 32 pad ceramic lcc (package 141) ? 32 lead ceramic flatpack (package 142) n single +5v ( 10%) supply operation 32 zip top view february 2000 rev. 10 pin description i/o 0-7 data inputs/outputs a 0-16 address inputs we write enable cs chip select oe output enable v cc power (+5v 10%) v ss ground nc not connected block diagram memory array address buffer address decoder i/o circuits a -16 i/o -7 we cs oe fig. 1 pin configuration the edi88128cs is a high speed, high performance, 128kx8 megabit density monolithic cmos static ram. the device has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. an automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. a low power version with 2v data retention (edi88128lps) is also available for battery back-up opperation. military product is available compliant to mil-prf-38535. * 15ns access time is advanced information, contact factory for availability. 32 dip 32 soj 32 lcc 32 flatpack top view 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 v cc a15 nc we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a i/o i/o1 i/o2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v cc a15 nc we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a i/o i/o1 i/o2 v ss
2 white electronic designs corporation ? (602) 437-1520 ? ww.whiteedc.com edi88128cs absolute maximum ratings parameter unit voltage on any pin relative to vss -0.5 to 7.0 v operating temperature t a (ambient) commercial 0 to +70 c industrial -40 to +85 c military -55 to +125 c storage temperature, plastic -65 to +150 c power dissipation 1.5 w output current 20 ma junction temperature, t j 175 c recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v input high voltage v ih 2.2 vcc +0.5 v input low voltage v il -0.3 +0.8 v parameter symbol condition max unit lcc address lines c i v in = vcc or vss, f = 1.0mhz 612pf data lines c o v out = vcc or vss, f = 1.0mhz 814pf these parameters are sampled, not 100% tested. capacitance (t a = +25 c) truth table oe cs we mode output power x h x standby high z icc 2 , icc3 h l h output deselect high z icc 1 l l h read data out icc 1 x l l write data in icc 1 note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol conditions units min typ max input leakage current i li v in = 0v to v cc 5 m a output leakage current i lo v i/o = 0v to v cc 10 m a (15-17ns) 300 ma operating power supply current i cc1 we, cs = v il , i i/o = 0ma, min cycle (20ns) 225 ma (25-55ns) 200 ma standby (ttl) power supply current i cc2 cs 3 v ih , v in v il , v in 3 v ih (17-55ns) 25 ma (15ns) 60 ma cs 3 v cc -0.2v cs (17-55ns) 3 10 ma full standby power supply current i cc3 v in 3 vcc -0.2v or v in 0.2v cs (15ns) 15 ma lps 5 ma output low voltage v ol i ol = 8.0ma 0.4 v output high voltage v oh i oh = -4.0ma 2.4 v note: dc test conditions: v il = 0.3v, v ih = vcc -0.3v dc characteristics (v cc = 5v, t a = -55 c to +125 c) csoj, zip, dip, flatpack
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128cs input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2) 30pf 480 w vcc q figure 1 figure 2 255 w 5pf 480 w vcc q 255 w ac test conditions ac characteristics C read cycle (15 to 20ns) (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) symbol 15ns* 17ns 20ns parameter jedec alt. min max min max min max units read cycle time t avav t rc 15 17 20 ns address access time t avqv t aa 15 17 20 ns chip enable access time t elqv t acs 15 17 20 ns chip enable to output in low z (1) t elqx t clz 333ns chip disable to output in high z (1) t ehqz t chz 8810ns output hold from address change t avqx t oh 000ns output enable to output valid t glqv t oe 668ns output enable to output in low z (1) t glqx t olz 000ns output disable to output in high z(1) t ghqz t ohz 668ns chip enable to power up (1) t elicch t pu 000ns chip enable to power down (1) t ehiccl t pd 15 17 20 ns 1. this parameter is guaranteed by design but not tested. ac characteristics C read cycle (25 to 55ns) (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) symbol 25ns 35ns 45ns 55ns parameter jedec alt. min max min max min max min max units read cycle time t avav t rc 25 35 45 55 ns address access time t avqv t aa 25 35 45 55 ns chip enable access time t elqv t acs 25 35 45 55 ns chip enable to output in low z (1) t elqx t clz 3333ns chip disable to output in high z (1) t ehqz t chz 12 20 20 20 ns output hold from address change t avqx t oh 0000ns output enable to output valid t glqv t oe 10 15 20 25 ns output enable to output in low z (1) t glqx t olz 0000ns output disable to output in high z(1) t ghqz t ohz 10 15 20 20 ns chip enable to power up (1) t elicch t pu 0000ns chip enable to power down (1) t ehiccl t pd 25 35 45 55 ns 1. this parameter is guaranteed by design but not tested.
4 white electronic designs corporation ? (602) 437-1520 ? ww.whiteedc.com edi88128cs ac characteristics C write cycle (12 to 20ns) (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) symbol 15ns* 17ns 20ns parameter jedec alt. min max min max min max units write cycle time t avav t wc 15 17 20 ns chip enable to end of write t elwh t cw 12 13 15 ns t eleh t cw 12 13 15 ns address setup time t avwl t as 000ns t avel t as 000ns address valid to end of write t avwh t aw 12 13 15 ns t aveh t aw 12 13 15 ns write pulse width t wlwh t wp 12 13 15 ns t wleh t wp 12 13 15 ns write recovery time t whax t wr 000ns t ehax t wr 000ns data hold time t whdx t dh 000ns t ehdx t dh 000ns write to output in high z (1) t wlqz t whz 08 08010ns data to write time t dvwh t dw 7710ns t dveh t dw 7710ns output active from end of write (1) t whqx t wlz 333ns 1. this parameter is guaranteed by design but not tested. ac characteristics C write cycle (25 to 55ns) (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) symbol 25ns 35ns 45ns 55ns parameter jedec alt. min max min max min max min max units write cycle time t avav t wc 25 35 45 55 ns chip enable to end of write t elwh t cw 20 25 35 45 ns t eleh t cw 20 25 35 45 ns address setup time t avwl t as 00 00ns t avel t as 00 00ns address valid to end of write t avwh t aw 20 25 35 45 ns t aveh t aw 20 25 35 45 ns write pulse width t wlwh t wp 20 30 30 35 ns t wleh t wp 20 30 30 35 ns write recovery time t whax t wr 00 55ns t ehax t wr 00 55ns data hold time t whdx t dh 00 00ns t ehdx t dh 00 00ns write to output in high z (1) t wlqz t whz 010013 015020ns data to write time t dvwh t dw 15 20 20 25 ns t dveh t dw 15 20 20 25 ns output active from end of write (1) t whqx t wlz 33 33ns 1. this parameter is guaranteed by design but not tested.
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128cs address data i/o read cycle 1 (we high; oe, cs low) t avqx t avqv t avav data 2 address 1 address 2 data 1 address data i/o read cycle 2 (we high) t avqv t elqv t glqv t elqx t glqx t avav t ehqz t ghqz oe icc cs t elicch t ehiccl ws32k32-xhx fig. 2 timing waveform - read cycle fig. 4 write cycle - cs controlled fig. 3 write cycle - we controlled address data in write cycle 2, cs controlled t aveh t eleh t ehax t wleh t dveh t ehdx t avav data valid high z we cs data out t avel address data in write cycle 1, we controlled t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z we cs data out
6 white electronic designs corporation ? (602) 437-1520 ? ww.whiteedc.com edi88128cs characteristic sym conditions min typ max units low power version only data retention voltage v dd v dd = 2.0v 2 C C v data retention quiescent current i ccdr cs 3 v dd -0.2v C 0.5 2 ma chip disable to data retention time (1) t cdr v in 3 v dd -0.2v 0 C C ns operation recovery time (1) t r or v in 0.2v t avav *C Cns note: 1. parameter guaranteed by design, but not tested. * read cycle time data retention characteristics (edi88128lpa only) (t a = -55 c to +125 c) ws32k32-xhx fig. 5 data retention - cs controlled data retention, cs controlled data retention mode t r vcc cs t cdr cs = v dd -0.2v v dd 4.5v 4.5v
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128cs package 9: 32 pin sidebrazed ceramic dip (600mils wide) all dimensions are in inches pin 1 indicator 0.020 0.016 0.175 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 1.616 1.584 0.061 0.017 0.600 nom 0.060 0.040 0.620 0.600 package 100: 32 lead ceramic zip all dimensions are in inches 0.050 0.155 0.125 0.040 min 31 x 0.050 = 1.550 0.040 0.020 0.500 max 1.65 max 0.125 max 0.100 nom package 102: 32 pin sidebrazed ceramic dip (400mils wide) all dimensions are in inches pin 1 indicator 0.020 0.016 0.175 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 0.420 0.400 1.616 1.584 0.061 0.017 0.400 nom 0.060 0.040
8 white electronic designs corporation ? (602) 437-1520 ? ww.whiteedc.com edi88128cs package 142: 32 pin ceramic flatpack all dimensions are in inches pin 1 0.019 0.015 0.040 0.030 0.290 0.270 0.116 0.100 0.050
typ 0.420 0.400 1.00 r e 0.045 0.020 0.007 0.003 0.830 0.810 0.370 0.250 package 140: 32 lead ceramic soj all dimensions are in inches 0.108 0.088 0.05 0 ty p 0.440 0.430 0.840 0.820 0.155 0.120 0.040 0.030 0.379 ref package 141: 32 pad ceramic lcc all dimensions are in inches 0.096 0.080 0.050 typ 0.405 0.395 0.840 0.820 0.02 8 0.02 2
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi88128cs ordering information white electronic designs sram organization, 128kx8 technology: cs = cmos standard power lps = low power access time (ns) package type: c = 32 lead sidebrazed dip, 600 mil (package 9) f = 32 lead ceramic flatpack (package 142) l = 32 pad ceramic lcc (package 141) n = 32 lead ceramic soj (package 140) t = 32 lead sidebrazed dip, 400 mil (package 102) z = 32 lead ceramic zip (package 100) device grade: b = mil-std-883 compliant m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c edi 8 8 128 cs x x x
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