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? s14066 lsi53c876/876e pci to dual channel scsi multifunction controller technical manual march 2001 version 2.1
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?cer is prohibited. document db14-000167-00, first edition (march 2001) this document describes the lsi logic lsi53c876/876e pci to dual channel scsi multifunction controller and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 1996C2001 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, tolerant, sdms, symplicity, and scripts are registered trademarks or trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies.
preface iii preface this book is the primary reference and technical manual for the lsi logic lsi53c876/876e pci to dual channel scsi multifunction controller. it contains a complete functional description for the product and includes complete physical and electrical speci?cations. this technical manual assumes the user is familiar with the current and proposed standards for scsi and pci. for additional background information on these topics, please refer to the list of reference materials provided in the related publications list. audience this manual assumes some prior knowledge of current and proposed scsi and pci standards. organization this document has the following chapters and appendixes: chapter 1, general description , includes general information about the lsi53c876/876e. chapter 2, functional description , describes the main functional areas of the chip in more detail, including the interfaces to the scsi bus and external memory. chapter 3, signal descriptions , contains pin diagrams and signal descriptions. chapter 4, registers , describes each bit in the operating registers, and is organized by register address. chapter 5, scsi scripts instruction set , de?nes the scsi scripts instructions supported by the lsi53c876/876e.
iv preface chapter 6, electrical characteristics , contains the electrical characteristics and ac timing diagrams. appendix a, register summary , is a register summary. appendix b, external memory interface diagram examples , contains serveral example interface drawings for connecting the lsi53c876 to external roms. related publications for background please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-199x (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2) or x3.253 (scsi-3 parallel interface) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface lsi logic world wide web home page www.lsil.com
preface v pci special interest group 2575 n. e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344 scsi scripts? processors programming guide, order number s14044.a conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x for example, 0x32cf. binary numbers are indicated by the pre?x 0b for example, 0b0011.0010.1100.1111. revision record revision date remarks 1.0 9/96 prelimiary technical manual. 2.0 11/97 revised technical manual. 2.1 3/01 all product names changed from sym to lsi.
vi preface
contents vii contents chapter 1 general description 1.1 wide ultra scsi bene?ts 1-4 1.2 tolerant ? technology 1-4 1.3 lsi53c876 bene?ts 1-5 1.3.1 pci performance 1-5 1.3.2 scsi performance 1-5 1.3.3 testability 1-6 1.3.4 integration 1-7 1.3.5 reliability 1-7 chapter 2 functional description 2.1 pci functional description 2-3 2.1.1 pci addressing 2-3 2.1.2 pci bus commands and functions supported 2-4 2.1.3 internal arbiter 2-10 2.1.4 pci cache mode 2-11 2.2 scsi functional description 2-13 2.2.1 two scsi controllers 2-13 2.2.2 scripts processor 2-13 2.2.3 jtag boundary scan testing 2-16 2.2.4 scsi loopback mode 2-17 2.2.5 parity options 2-17 2.2.6 dma fifo 2-20 2.2.7 scsi bus interface 2-24 2.2.8 synchronous operation 2-30 2.2.9 designing a wide ultra scsi system 2-32 2.2.10 interrupt handling 2-33 2.2.11 chained block moves 2-40 2.3 parallel rom interface 2-43
viii contents 2.4 serial eeprom interface 2-45 2.4.1 mode a operation 2-45 2.4.2 mode b operation 2-46 2.4.3 mode c operation 2-46 2.4.4 mode d operation 2-48 2.5 power management 2-48 2.5.1 power state d0 2-49 2.5.2 power state d1 2-49 2.5.3 power state d2 2-49 2.5.4 power state d3 2-50 chapter 3 signal descriptions 3.1 pci interface signals 3-6 3.1.1 system signals 3-6 3.1.2 address and data signals 3-7 3.1.3 interface control signals 3-8 3.1.4 arbitration signals 3-9 3.1.5 error reporting signals 3-9 3.1.6 pci interrupt signals 3-10 3.1.7 gpio interface signals 3-11 3.2 scsi bus interface signals 3-13 3.2.1 scsi bus interface signal 3-13 3.2.2 scsi bus interface 3-14 3.3 rom/flash interface signals 3-18 3.4 test interface signals 3-19 3.5 power and ground signals 3-20 3.5.1 isolated power supplies 3-21 3.6 mad bus programming 3-21 chapter 4 registers 4.1 pci con?guration registers 4-1 4.2 scsi registers 4-20 chapter 5 scsi scripts instruction set 5.1 low level register interface mode 5-1 5.2 high level scsi scripts mode 5-2 5.2.1 sample operation 5-3
contents ix 5.3 block move instruction 5-6 5.3.1 first dword 5-6 5.3.2 second dword 5-13 5.4 i/o instruction 5-13 5.4.1 first dword 5-13 5.4.2 second dword 5-22 5.5 read/write instructions 5-22 5.5.1 first dword 5-22 5.5.2 second dword 5-24 5.5.3 read-modify-write cycles 5-24 5.5.4 move to/from sfbr cycles 5-25 5.6 transfer control instructions 5-27 5.6.1 first dword 5-27 5.6.2 second dword 5-34 5.7 memory move instructions 5-34 5.7.1 read/write system memory from scripts 5-36 5.7.2 second dword 5-36 5.7.3 third dword 5-36 5.8 load and store instructions 5-38 5.8.1 first dword 5-39 5.8.2 second dword 5-40 chapter 6 electrical characteristics 6.1 dc characteristics 6-1 6.2 3.3 v pci dc characteristics 6-7 6.3 tolerant technology electrical characteristics 6-8 6.4 ac characteristics 6-12 6.4.1 pci and external memory interface timings 6-15 6.4.2 pci and external memory interface timing 6-54 6.4.3 scsi interface timing 6-55 6.5 package diagrams 6-60 appendix a register summary appendix b external memory interface diagram examples
x contents index customer feedback figures 1.1 typical lsi53c876 system application 1-2 1.2 typical lsi53c876 board application 1-3 2.1 lsi53c876 block diagram 2-2 2.2 parity checking/generation 2-20 2.3 dma fifo sections 2-20 2.4 lsi53c876 host interface scsi data paths 2-24 2.5 lsi53c876 differential wiring diagram 2-27 2.6 regulated termination 2-29 2.7 determining the synchronous transfer rate 2-32 2.8 block move and chained block move instructions 2-40 3.1 lsi53c876 208-pin pqfp diagram 3-2 3.2 lsi53c876 256-ball bga diagram (top view) 3-3 3.3 lsi53c876 functional signal grouping 3-4 5.1 scripts overview 5-5 5.2 block move instruction register 5-8 5.3 i/o instruction register 5-16 5.4 read/write instruction register 5-23 5.5 transfer control instruction 5-29 5.6 memory move instruction 5-37 5.7 load and store instruction format 5-41 6.1 rise and fall time test conditions 6-10 6.2 scsi input filtering 6-10 6.3 hysteresis of scsi receivers 6-10 6.4 input current as a function of input voltage 6-11 6.5 output current as a function of output voltage 6-11 6.6 clock timing 6-12 6.7 reset input 6-13 6.8 interrupt output 6-14 6.9 con?guration register read 6-17 6.10 con?guration register write 6-18 6.11 target read (not from external memory) 6-19
contents xi 6.12 target write (not from external memory) 6-20 6.13 target read, from external memory 6-22 6.14 target write, from external memory 6-26 6.15 opcode fetch, nonburst 6-29 6.16 opcode fetch, burst 6-31 6.17 back-to-back read 6-33 6.18 back-to-back write 6-35 6.19 burst read 6-38 6.20 burst write 6-42 6.21 read cycle, normal/fast memory ( 3 128 kbytes), single byte access 6-44 6.22 write cycle, normal/fast memory ( 3 128 kbytes), single byte access 6-45 6.23 read cycle, normal/fast memory ( 3 128 kbyte), multiple byte access 6-46 6.24 write cycle, normal/fast memory ( 3 128 kbyte), multiple byte access 6-48 6.25 read cycle, slow memory ( 3 128 kbytes) 6-50 6.26 write cycle, slow memory ( 3 128 kbytes) 6-51 6.28 read cycle, 16 kbytes rom 6-52 6.27 read cycle, 16 kbytes rom 6-52 6.29 write cycle, 16 kbytes rom 6-53 6.30 initiator asynchronous send 6-55 6.31 initiator asynchronous receive 6-56 6.32 target asynchronous send 6-57 6.33 target asynchronous receive 6-57 6.34 initiator and target synchronous transfers 6-58 6.35 256-pin pbga (gu) mechanical drawing 6-61 6.36 208-pin pqfp (p9) mechanical drawing (sheet 1 of 2) 6-62 b.1 64 kbyte interface with 200 ns memory b-1 b.2 64 kbyte interface with 150 ns memory b-2 b.3 256 kbyte interface with 150 ns memory b-3 b.4 512 kbyte interface with 150 ns memory b-4 tables 2.1 pci bus commands and encoding types 2-4 2.2 bits used for parity control and generation 2-18 2.3 scsi parity control 2-19
xii contents 2.4 scsi parity errors and interrupts 2-19 2.5 differential mode 2-25 2.6 parallel rom support 2-44 2.7 mode a serial eeprom data format 2-46 2.8 mode c serial eeprom data format 2-47 2.9 power states 2-48 3.1 system signals 3-6 3.2 address and data signals 3-7 3.3 interface control signals 3-8 3.4 arbitration signals 3-9 3.5 error reporting signals 3-9 3.6 pci interrupt signals 3-10 3.7 scsi gpio function a signals 3-11 3.8 scsi gpio function b signals 3-12 3.9 scsi bus interface signal 3-13 3.10 scsi function a interface signals 3-14 3.11 scsi function b interface signals 3-15 3.12 scsi function a differential control signals 3-16 3.13 scsi function b differential control signals 3-17 3.14 rom/flash interface signals 3-18 3.15 test interface signals 3-19 3.16 power and ground signals 3-20 3.17 decode of mad pins 3-22 4.1 pci to scsi con?guration register map 4-2 4.2 lsi53c876 scsi register address map 4-21 4.3 examples of synchronous transfer periods for scsi-1 transfer rates 4-35 4.4 example transfer periods for fast scsi and wide ultra scsi transfer rates 4-35 4.5 maximum synchronous offset 4-36 4.6 scsi synchronous data fifo word count 4-46 5.1 scripts instructions 5-3 5.2 read/write instructions 5-25 6.1 absolute maximum stress ratings 6-2 6.2 operating conditions 6-2 6.3 scsi signalssd[15:0]/, sdp[1:0]/, sreq/, sack/ 6-3 6.4 scsi signalssmsg, si_o/, sc_d/, satn/, sbsy/, ssel/, srst/ 6-3
contents xiii 6.5 input signalsclk, sclk, gnt/, idsel, rst/, testin, diffsens 6-3 6.6 capacitance 6-4 6.7 output signalsinta/, intb/ 6-4 6.8 output signalssdir[15:0], sdirp0, sdirp1, bsydir, seldir, rstdir, tgs, igs, mas/[1:0], mce/, moe/_testout, mwe/ 6-4 6.9 output signalreq/ 6-5 6.10 output signalserr/ 6-5 6.11 bidirectional signalsad[31:0], c_be/[3:0], frame/, irdy/, trdy/, devsel/, stop/, perr/, par 6-5 6.12 bidirectional signalsgpio0_fetch/, gpio1_master/, gpio2, gpio3, gpio4 6-6 6.13 bidirectional signalsmad[7:0] 6-6 6.14 input signalstdi, tms, tck 6-6 6.15 output signaltdo 6-7 6.16 bidirectional signalsad[31:0], c_be[3:0]/, frame/, irdy/, trdy/, devsel/, stop/, perr/, par 6-7 6.17 input signalsclk, gnt/, idsel, rst/, 6-7 6.18 output signalsinta/, intb, req/ 6-8 6.19 output signalserr/ 6-8 6.20 tolerant technology electrical characteristics 6-9 6.21 clock timing 6-12 6.22 reset input 6-13 6.23 interrupt output 6-14 6.24 3.3 v pci timing 6-16 6.25 con?guration register read 6-17 6.26 con?guration register write 6-18 6.27 target read (not from external memory) 6-19 6.28 target write (not from external memory) 6-20 6.29 target read (from external memory) 6-21 6.30 target write (from external memory) 6-25 6.31 opcode fetch, nonburst 6-28 6.32 opcode fetch, burst 6-30 6.33 back-to-back read 6-32 6.34 back-to-back write 6-34 6.35 burst read 6-37 6.36 burst write 6-41
xiv contents 6.37 read cycle, norma/fast memory ( 3 128 kbytes), single byte access 6-44 6.38 write cycle, normal/fast memory ( 3 128 kbytes), single byte access 6-45 6.39 read cycle, slow memory ( 3 128 kbytes) 6-50 6.40 write cycle, slow memory ( 3 128 kbytes) 6-51 6.41 write cycle, 16 kbytes rom 6-53 6.42 lsi53c876 pci and external memory interface timing 6-54 6.43 initiator asynchronous send 6-55 6.44 initiator asynchronous receive 6-56 6.45 target asynchronous send 6-57 6.46 target asynchronous receive 6-57 6.47 scsi-1 transfers (se, 5.0 mbytes/s) 6-58 6.48 scsi-2 fast transfers (10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 40 mhz clock 6-59 6.49 scsi-2 fast-20 se transfers (20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), 80 mhz clock) with clock doubled internally 6-59 a.1 con?guration registers a-1 a.2 scsi registers a-2
lsi53c876/876e pci to dual channel scsi multifunction controller 1-1 chapter 1 general description this chapter includes the following sections: section 1.1, wide ultra scsi bene?ts section 1.2, tolerant ? technology section 1.3, lsi53c876 bene?ts this manual combines information for the lsi53c876 and lsi53c876e, which are a pci to dual scsi controllers. the lsi53c876e is a minor modi?cation of the existing lsi53c876 product. it has all of the functionality of the lsi53c876 with the addition of features to enable it to comply with the microsoft pc 97 hardware design guide. speci?cally, the lsi53c876e has a power management support enhancement. because there are only slight differences between them, the lsi53c876 and lsi53c876e are referred to as lsi53c876 throughout this technical manual. only the new enhancements are referred to as lsi53c876e. the lsi53c876 pci to dual channel scsi multifunction controller is a pci 2.1 compliant device. it implements two lsi53c875 pci to ultra scsi controllers on a single chip. the lsi53c876 presents only one load to the pci bus, and it uses one req/ - gnt/ signal pair in arbitration for pci bus mastership. two packaging options are available. the 208-pin plastic quad flat pack (pqfp) provides a differential single-ended (se) scsi interface on scsi function a and an se interface on scsi function b. the 256-bump ball grid array (bga) provides a differential se interface on both scsi function a and scsi function b. the lsi53c876 has a local memory bus for storage of the devices bios rom in flash memory or standard eproms. the lsi53c876 supports programming of local flash memory for updates to bios or scripts? programs.
1-2 general description the lsi53c876 reduces the requirement for system bios support and pci bus bandwidth. it also supports the wide ultra scsi standard. the lsi53c876 performs wide ultra scsi transfers or fast scsi transfers, and it improves performance by optimizing pci bus utilization. figure 1.1 illustrates a typical lsi53c876 system and figure 1.2 illustrates a typical lsi53c876 board application. figure 1.1 typical lsi53c876 system application fixed disk, optical disk, printer, tape, and other peripherals fixed disk, optical disk, printer, tape, and other peripherals one pci bus load pci graphic accelerator pci sound card memory controller memory pci bus interface controller central processing unit (cpu) typical pci computer system architecture processor bus lsi53c876 pci to wide ultra scsi function a and lsi53c876 pci to wide ultra scsi function b scsi bus scsi bus
1-3 figure 1.2 typical lsi53c876 board application the lsi53c876 integrates a high-performance scsi core, a pci bus master dma core, and the lsi logic scsi scripts processor to meet the ?exibility requirements of scsi, fast scsi, and wide ultra scsi standards. it is designed to implement multithreaded i/o algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent controller designs. the lsi53c876 is fully supported by the lsi logic storage device management system (sdms?), a software package that supports the advanced scsi protocol interface (aspi). sdms software provides bios and driver support for hard disk, tape, removable media products, and cd-rom under the major pc operating systems. in addition, lsi logic provides a symplicity? i 2 o hardware device module for the lsi53c876 to support the device in i 2 o-ready systems. the symplicity i 2 o architecture is compliant with the i 2 o speci?cation. i 2 o is a split driver architecture that increases system ef?ciency by transferring i/o intensive processing tasks from the host cpu to intelligent peripheral platforms. flash eeprom serial eeprom function a serial eeprom function b memory control block lsi53c876 pci to dual channel scsi multifunction function a 68 pin wide scsi connector scsi data, parity, and control signals function b 68 pin wide scsi connector scsi data, parity, and control signals pci interface pci address, data, parity and control signals memory address/data bus a_gpio/[1:0] b_gpio/[1:0] controller
1-4 general description 1.1 wide ultra scsi bene?ts wide ultra scsi is an extension of the scsi-3 family of standards that expands the bandwidth of the scsi bus and allows faster synchronous scsi transfer rates. when enabled, wide ultra scsi performs 40 megatransfers per second during an i/o operation, resulting in approximately twice the synchronous transfer rates of fast scsi. the lsi53c876 can perform ultra scsi synchronous transfers at 20 mbytes/s. it can also perform wide ultra scsi transfers at 40 mbytes/s. this advantage is most noticeable in heavily loaded systems or large block size requirements, such as video on-demand and image processing. an advantage of wide ultra scsi is that it signi?cantly improves scsi bandwidth while preserving existing hardware and software investments. the lsi53c876 is compatible with all existing lsi53c875 software. 1.2 tolerant ? technology the lsi53c876 features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. active negation is enabled by setting bit 7 in the scsi test three (stest3) register. tolerant receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption. tolerant receivers ?lter the scsi bus signals to eliminate unwanted transitions, without the long signal delay associated with rc-type input ?lters. this improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with scsi operations. tolerant input signal ?ltering is a built in feature of the lsi53c876 and all lsi logic fast scsi and ultra scsi devices. the bene?ts of tolerant technology include increased immunity to noise on the deasserting signal edge, better performance due to balanced duty cycles, and improved fast scsi transfer rates. in addition, tolerant scsi devices do not cause glitches on the scsi bus at power-up or
lsi53c876 bene?ts 1-5 power-down, so other devices on the bus are also protected from data corruption. tolerant technology is compatible with both the alternative one and alternative two termination schemes proposed by the american national standards institute (ansi). 1.3 lsi53c876 bene?ts this section provides an overview of the lsi53c876 features and bene?ts. it contains information on pci performance , scsi performance , testability , integration , and reliability . 1.3.1 pci performance to improve scsi performance, the lsi53c876: complies with pci 2.1 speci?cation presents a single electrical load to the pci bus (true pci multifunction device). supports 32-bit word data bursts with variable burst lengths of 2, 4, 8, 16, 32, 64 or 128 dwords across the pci bus. prefetches up to 8 dwords of scsi scripts. bursts scsi scripts opcode fetches across the pci bus. performs zero wait-state bus master data bursts up to 132 mbytes/s (@ 33 mhz). supports pci cache line size register. supports pci write and invalidate, read line, and read multiple commands. complies with pci bus power management speci?cation (lsi53c876e) revision 1.0. 1.3.2 scsi performance to improve scsi performance, the lsi53c876: includes 4 kbytes internal ram on each channel for scripts instruction storage. wide ultra scsi se interface.
1-6 general description performs wide ultra scsi synchronous transfers as fast as 40 mbytes/s. supports 536-byte dma fifo for more effective pci and scsi bus utilization. supports 16 levels of scsi synchronous offset. supports variable block size and scatter/gather data transfers minimizes scsi i/o start latency. performs complex bus sequences without interrupts, including restore data pointers. reduces interrupt service routine overhead through a unique interrupt status reporting method. supports load and store scripts instructions to increase the performance of data transfers to and from chip registers. supports target disconnect and later reconnect with no interrupt to the system processor. supports multithreaded i/o algorithms in scsi scripts with fast i/o context switching. supports expanded register move instructions. compatible with lsi53c875 software (drivers and scripts). enables ultra scsi with 40 mhz scsi clock input with integrated clock doubler. 1.3.3 testability the lsi53c876 contains these testability features: all scsi signals accessible through programmed i/o. scsi loopback diagnostics. scsi bus signal continuity checking. support for single step mode operation. test mode (and-tree) to check pin continuity to the board.
lsi53c876 bene?ts 1-7 1.3.4 integration the lsi53c876 contains these integration features: dual channel scsi multifunction controller. 3.3 v/5 v pci interface. full 32-bit pci dma bus master. memory-to-memory move instructions allow use as a third-party pci bus dma controller. high-performance scsi core. integrated scripts processor. 1.3.5 reliability the lsi53c876 contains these reliability features: 2 kv esd protection on scsi signals. typical 300 mv scsi bus hysteresis. protection against bus re?ections due to impedance mismatches. controlled bus assertion times (reduces emi, improves reliability, and eases fcc certi?cation). latch-up protection greater than 150 ma. voltage feed-through protection (minimum leakage current through scsi pads). power and ground isolation of i/o pads and internal chip logic. tolerant technology, which provides: C active negation of scsi data, parity, request, and acknowledge signals for improved fast scsi transfer rates. C input signal ?ltering on scsi receivers improves data integrity, even in noisy cabling environments.
1-8 general description
lsi53c876/876e pci to dual channel scsi multifunction controller 2-1 chapter 2 functional description chapter 2 is divided into the following sections: section 2.1, pci functional description section 2.2, scsi functional description section 2.3, parallel rom interface section 2.4, serial eeprom interface section 2.5, power management the lsi53c876 is a multifunction device composed of the following modules: pci interface two independent pci-to-wide ultra scsi controllers rom/flash memory controller serial eeprom controller figure 2.1 illustrates the relationship between these modules.
2-2 functional description figure 2.1 lsi53c876 block diagram 4 kbyte scripts ram 8 dword scripts prefetch buffer operating registers scsi scripts processor 536 byte dma fifo scsi fifo and scsi control block tolerant drivers and receivers pci master and slave control block, pci con?guration registers (2 sets), and scsi function arbitration wide ultra scsi controller serial eeprom controller and autocon?guration rom/flash memory control local bus memory 4 kbyte scripts ram 8 dword scripts prefetch buffer scsi scripts processor 536 byte dma fifo scsi fifo and scsi control block tolerant drivers and receivers wide ultra scsi controller operating registers pci bus scsi function b wide ultra scsi bus scsi function a wide ultra scsi bus rom/flash memory bus 2-wire serial eeprom bus 2-wire serial eeprom bus
pci functional description 2-3 2.1 pci functional description the lsi53c876 implements two pci-to-wide ultra scsi controllers in a single package. this con?guration presents only one load to the pci bus and uses one req/ - gnt/ pair to arbitrate for pci bus mastership. however, separate interrupt signals are generated for scsi function a and scsi function b. 2.1.1 pci addressing there are three physical pci-de?ned address spaces: con?guration space i/o space memory space 2.1.1.1 con?guration space two independent sets of con?guration space registers are de?ned, one set for each scsi function. the con?guration registers are accessible only by system bios during pci con?guration cycles. the con?guration space is a contiguous 256 x 8-bit set of addresses. decoding c_be/[3:0] determines if a pci cycle is intended to access con?guration register space. the idsel bus signal is a chip select that allows access to the con?guration register space only. a con?guration read/write cycle without idsel is ignored. the eight lower order address bits ad[7:0], are used to select a speci?c 8-bit register. since the lsi53c876 is a pci multifunction device, ad[10:8] decodes either scsi function a con?guration register (ad [10:8] = 000 binary) or scsi function b con?guration register (ad [10:8] = 001 binary). the host processor uses this con?guration space to initialize the lsi53c876. at initialization time, each pci device is assigned a base address for memory accesses and i/o accesses. in the case of the lsi53c876, the upper 24 bits of the address are selected. on every access, the lsi53c876 compares its assigned base addresses with the value on the address/data bus during the pci address phase. if the upper 24 bits match, the access is for the lsi53c876 and the low-order eight bits de?ne the register being accessed. a decode of c_be/[3:0] determines which registers and what type of access is to be performed.
2-4 functional description i/o space C the pci speci?cation de?nes i/o space as a contiguous 32-bit i/o address that is shared by all system resources, including the lsi53c876. the base address register zero (i/o) register determines which 256-byte i/o area this device occupies. memory space C the pci speci?cation de?nes memory space as a contiguous 32-bit memory address that is shared by all system resources, including the lsi53c876. the base address register one (memory) register determines which 256-byte memory area this device occupies. each scsi function uses a 4 k script ram memory space. the base address register two (memory) register determines the 4 kbyte memory area occupied by scripts ram. 2.1.2 pci bus commands and functions supported bus commands indicate to the target the type of transaction the master is requesting. bus commands are encoded on the c_be/[3:0] lines during the address phase. pci bus commands and encoding types appear in table 2.1 . table 2.1 pci bus commands and encoding types c_be[3:0] command type supported as master supported as slave 0b0000 interrupt acknowledge no no 0b0001 special cycle no no 0b0010 i/o read yes yes 0b0011 i/o write yes yes 0b0100 reserved n/a n/a 0b0101 reserved n/a n/a 0b0110 memory read yes yes 0b0111 memory write yes yes 0b1000 reserved n/a n/a 0b1001 reserved n/a n/a
pci functional description 2-5 2.1.2.1 interrupt acknowledge command the lsi53c876 does not respond to this command as a slave and it never generates this command as a master. 2.1.2.2 special cycle command the lsi53c876 does not respond to this command as a slave and it never generates this command as a master. 2.1.2.3 i/o read command the i/o read command reads data from an agent mapped in i/o address space. all 32 address bits are decoded. 2.1.2.4 i/o write command the i/o write command writes data to an agent mapped in i/o address space. all 32 address bits are decoded. 2.1.2.5 reserved command the lsi53c876 does not respond to this command as a slave and it never generates this command as a master. 0b1010 con?guration read no yes 0b1011 con?guration write no yes 0b1100 memory read multiple yes 1 no (defaults to 0110) 0b1101 dual address cycle (dac) no no 0b1110 memory read line yes 1 no (defaults to 0110) 0b1111 memory write and invalidate yes 2 no (defaults to 0111) 1. see the dma mode (dmode) register. 2. see the chip test three (ctest3) register. table 2.1 pci bus commands and encoding types (cont.) c_be[3:0] command type supported as master supported as slave
2-6 functional description 2.1.2.6 memory read command the memory read command reads data from an agent mapped in the memory address space. the target is free to do an anticipatory read for this command only if it can guarantee that such a read has no side effects. 2.1.2.7 memory write command the memory write command writes data to an agent mapped in the memory address space. when the target returns ready, it assumes responsibility for the coherency (which includes ordering) of the subject data. 2.1.2.8 con?guration read command the con?guration read command reads the con?guration space of each agent. an agent is selected during a con?guration access when its idsel signal is asserted and ad[1:0] are 0b00. during the address phase of a con?guration cycle, ad[7:2] address one of the 64 dword registers (where byte enables address of the bytes within each dword) in the con?guration space of each device and ad[31:11] are logical dont cares to the selected agent. ad[10:8] indicate which device of a multifunction agent is being addressed. 2.1.2.9 con?guration write command the con?guration write command transfers data to the con?guration space of each agent. an agent is selected when its idsel signal is asserted and ad[1:0] are 0b00. during the address phase of a con?guration cycle, the ad[7:2] lines address the 64 dword registers (where byte enables address of the bytes within each dword) in the con?guration space of each device, and ad[31:11] are logical dont cares to the selected agent. ad[10:8] indicate which device of a multifunction agent is addressed. 2.1.2.10 memory read multiple command this command is identical to the memory read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. the lsi53c876 supports pci read multiple functionality and issues read multiple commands on the pci
pci functional description 2-7 bus when the read multiple mode is enabled. this mode is enabled by setting bit 2 (ermp) of the dma mode (dmode) register. if cache mode is enabled, a read multiple command is issued on all read cycles, except opcode fetches, when the following conditions are met: the clse bit (cache line size enable, bit 7, dma control (dcntl) register) and the ermp bit (enable read multiple, bit 2, dma mode (dmode) register) are set. the cache line size register for each function contains a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the dma mode (dmode) burst size. the number of bytes to transfer at the time a cache boundary is reached is at least twice the full cache line size. the chip is aligned to a cache line boundary. when these conditions are met, the chip issues a read multiple command instead of a memory read during all pci read cycles. burst size selection C the read multiple command reads in multiple cache lines of data in a single bus ownership. the number of cache lines to read is a multiple of the cache line size speci?ed in revision 2.1 of the pci speci?cation. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size determined from the dma mode (dmode) burst size bits, and the chip test five (ctest5) , bit 2. 2.1.2.11 dual address cycles (dacs) command the lsi53c876 does not respond to this command as a slave, and it never generates this command as a master. 2.1.2.12 memory read line command this command is identical to the memory read command, except that it additionally indicates that the master intends to fetch a complete cache line. this command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading up to a cache line boundary rather than a single memory cycle. the read line function in the previous lsi53c8xx chips is modi?ed in the lsi53c876 to re?ect the pci cache line size register speci?cations. the functionality of the enable read
2-8 functional description line bit ( dma mode (dmode) register, bit 3) is modi?ed to more resemble the write and invalidate mode in terms of conditions that must be met before a read line command is issued. however, the read line option operates exactly like the previous lsi53c8xx chips when cache mode is disabled by a clse bit reset or when certain conditions exist in the chip (explained below). if cache mode is disabled, read line commands are issued on every read data transfer, except opcode fetches, as in previous lsi53c8xx chips. if cache mode is enabled, a read line command is issued on all read cycles, except opcode fetches, when the following conditions are met: the clse (cache line size enable, bit 7, dma control (dcntl) register) and erl (enable read line, bit 3, dma mode (dmode) register) bits are set. the cache line size register for each function must contain a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the dma mode (dmode) burst size. the number of bytes to be transferred at the time a cache boundary is reached is equal to or greater than the dma mode (dmode) burst size. the chip is aligned to a cache line boundary. when these conditions are met, the chip issues a read line command instead of a memory read during all pci read cycles. otherwise, it issues a normal memory read command. read multiple with read line enabled C when both the read multiple and read line modes are enabled, the read line command is not issued if the above conditions are met. instead, a read multiple command is issued, even though the conditions for read line are met. if the read multiple mode is enabled and the read line mode is disabled, read multiple commands are issued if the read multiple conditions are met.
pci functional description 2-9 2.1.2.13 memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the master intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size register at address 0x0c in the pci con?guration space. the lsi53c876 enables memory write and invalidate cycles when bit 0 (wrie) in the chip test three (ctest3) register and bit 4 (wie) in the pci command register are set. when the following conditions are met, memory write and invalidate commands are issued: the clse bit (cache line size enable, dma control (dcntl) register, bit 7), wrie bit (write and invalid enable, chip test three (ctest3) register, bit 0), and pci con?guration command register, bit 4 are set. the cache line size register for each function contains a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the dma mode (dmode) burst size. the chip has enough bytes in the dma fifo to complete at least one full cache line burst. the chip is aligned to a cache line boundary. when these conditions are met, the lsi53c876 issues a write and invalidate command instead of a memory write command during all pci write cycles. multiple cache line transfers C the write and invalidate command can write multiple cache lines of data in a single bus ownership. the chip issues a burst transfer as soon as it reaches a cache line boundary. the size of the transfer is not automatically the cache line size, but rather a multiple of the cache line size as speci?ed in revision 2.1 of the pci speci?cation. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size determined from the dma mode (dmode) burst size bits, and chip test five (ctest5) , bit 2. if multiple cache line size transfers are not desired, set the dma mode (dmode) burst size to exactly the cache line size and the chip only issues single cache line transfers.
2-10 functional description after each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, no larger than the dma mode (dmode) burst size. the most likely scenario of this scheme is that the chip selects the dma mode (dmode) burst size after alignment, and issues bursts of this size. the burst size is, in effect, throttled down toward the end of a long memory move or block move transfer until only the cache line size burst size is left. the chip ?nishes the transfer with this burst size. latency C in accordance with the pci speci?cation, the chip's latency timer is ignored when issuing a write and invalidate command such that when a latency time-out occurs, the lsi53c876 continues to transfer up to a cache line boundary. at that point, the chip relinquishes the bus, and ?nishes the transfer at a later time using another bus ownership. if the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. pci target retry C during a write and invalidate transfer, if the target device issues a retry (stop with no trdy, indicating that no data was transferred), the chip relinquishes the bus and immediately tries to ?nish the transfer on another bus ownership. the chip issues another write and invalidate command on the next ownership, in accordance with the pci speci?cation. pci target disconnect C during a write and invalidate transfer, if the target device issues a disconnect the lsi53c876 relinquishes the bus and immediately tries to ?nish the transfer on another bus ownership. the chip does not issue another write and invalidate command on the next ownership unless the address is aligned. 2.1.3 internal arbiter the pci to scsi controller uses a single req/ - gnt/ signal pair to arbitrate for access to the pci bus. the lsi53c876 uses a round robin arbitration scheme to allow both scsi functions to arbitrate for pci bus access. an internal arbiter circuit allows the different bus mastering functions resident in the chip to arbitrate among themselves for the privilege of arbitrating for pci bus access. there are two independent bus mastering functions inside the lsi53c876, one for each of the scsi functions.
pci functional description 2-11 2.1.4 pci cache mode the lsi53c876 supports the pci speci?cation for an 8-bit cache line size register located in the pci con?guration space. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands read line, read multiple, and write and invalidate are each software enabled or disabled to allow the user full ?exibility in using these commands. 2.1.4.1 selection of cache line size the cache logic for each bus mastering function selects a cache line size based on the values for the burst size in the dma mode (dmode) register, and the pci cache line size register, whichever is appropriate. note: each bus mastering function does not automatically use the value in its pci cache line size register as the cache line size value. the chip scales the value of the cache line size register down to the nearest binary burst size allowed by the chip (2, 4, 8, 16, 32, 64, or 128). the scsi function compares this value to the dmode burst size, then selects the smaller as the value for the cache line size. 2.1.4.2 alignment the lsi53c876 uses the calculated line size value to monitor the current address for alignment to the cache line size. when it is not aligned, the chip attempts to align to the cache boundary by using a smart aligning scheme. this means that it attempts to use the largest burst size possible that is less than the cache line size, to reach the cache boundary quickly with no over?ow. this process is a stepping mechanism that steps up to the highest possible burst size based on the current address. the stepping process begins at a 4 dword boundary. the lsi53c876 ?rst tries to align t oa4dword boundary (0x0000, 0x0010, 0x0020, etc.) by using single dword transfers (no bursting). once this boundary is reached the chip evaluates the current alignment to various burst sizes allowed, and selects the largest possible as the next burst size, while not exceeding the cache line size. the chip then issues this burst and re-evaluates the alignment to various burst sizes, again selecting the
2-12 functional description largest possible while not exceeding the cache line size, as the next burst size. this stepping process continues until the chip reaches the cache line size boundary or runs out of data. once a cache line boundary is reached, the chip uses the cache line size as the burst size from then on, except in the case of multiples (explained below). the alignment process is ?nished at this point. example: cache line size = 16, current address = 0x01 C the chip is not aligned to a 4 dword cache boundary (the stepping threshold), so it issues four single dword transfers (the ?rst is a 3-byte transfer). at address 0x10, the chip is aligned to a 4-dword boundary, but not aligned to any higher burst size boundaries that are less than the cache line size. so, the part issues a burst of 4. at this point, the address is 0x20, and the chip evaluates that it is aligned not only t oa4dword boundary, but also to an 8 dword boundary. it selects the highest, 8, and bursts 8 dwords. at this point, the address is 0x40, which is a cache line size boundary. alignment stops, and the burst size from then on is switched to 16. 2.1.4.3 memory move misalignment the lsi53c876 does not operate in a cache alignment mode when a memory move instruction type is issued and the read and write addresses are different distances from the nearest cache line boundary. for example, if the read address is 0x21f and the write address is 0x42f, and the cache line size is 8, the addresses are byte aligned, but they are not the same distance from the nearest cache boundary. the read address is 1 byte from the cache boundary 0x220 and the write address is 17 bytes from the cache boundary 0x440. in this situation, the chip does not align to cache boundaries.
scsi functional description 2-13 2.2 scsi functional description 2.2.1 two scsi controllers the lsi53c876 provides two scsi controllers on a single chip. each scsi controller provides a scsi function that supports an 8-bit or 16-bit bus. each supports ultra scsi synchronous transfer rates up to 40 mbytes/s, ultra scsi synchronous transfer rates up to 20 mbytes/s, and asynchronous transfer rates up to 14 mbytes/s on a wide scsi bus. the scsi functions are programmed with scsi scripts, making it easy to ?ne tune the system for speci?c mass storage devices or scsi-2 requirements. the lsi53c876 offers low-level register access or a high-level control interface. like ?rst generation scsi devices, the lsi53c876 is accessed as a register-oriented device. error recovery and diagnostic procedures use the ability to sample and/or assert any signal on the scsi bus. in support of scsi loopback diagnostics, each scsi core may perform a self-selection and operate as both an initiator and a target. the lsi53c876 is controlled by the integrated scripts processor through a high-level logical interface. commands controlling the scsi core are fetched out of the main host memory or local memory. these commands instruct the scsi core to select, reselect, disconnect, wait for a disconnect, transfer information, change bus phases and, in general, implement all aspects of the scsi protocol. the scripts processor is a special high-speed processor optimized for scsi protocol. 2.2.2 scripts processor the scsi scripts processor allows both dma and scsi commands to be fetched from host memory or internal scripts ram. algorithms written in scsi scripts control the actions of the scsi and dma cores. the scripts processor executes complex scsi bus sequences independently of the host cpu. algorithms may be designed to tune scsi bus performance, to adjust to new bus device types (such as scanners, communication gateways, etc.), or to incorporate changes in the scsi-2 or scsi-3 logical bus de?nitions
2-14 functional description without sacri?cing i/o performance. scsi scripts are hardware independent, so they can be used interchangeably on any host or cpu system bus. 2.2.2.1 internal scripts ram the lsi53c876 has 4 kbytes (1024 x 32 bits) of internal, general purpose ram. the ram is designed for scripts program storage, but is not limited to this type of information. when the chip fetches scripts instructions or table indirect information from the internal ram, these fetches remain internal to the chip and do not use the pci bus. other types of access to the ram by the chip use the pci bus, as if they were external accesses. the mad5 pin disables the 4 k internal ram. to disable the internal ram, connect a 4.7 k w resistor between the mad5 pin and v ss (ground). the scripts ram powers up enabled by default. the ram can be relocated by the pci system bios anywhere in 32-bit address space. the base address register two (memory) register in pci con?guration space contains the base address of the internal ram. this register is similar to the rom base address register in pci con?guration space. to simplify loading of the scripts instructions, the base address of the ram appears in the scratch register b (scratchb) register when bit 3 of the chip test two (ctest2) register is set. the ram is byte accessible from the pci bus and is visible to any bus mastering device on the bus. external accesses to the ram (by the cpu) follow the same timing sequence as a standard slave register access, except that the required target wait-states drop from 5 to 3. a complete set of development tools is available for writing custom drivers with scsi scripts. for more information on the scsi scripts instructions supported by the lsi53c876, see chapter 5, scsi scripts instruction set. 2.2.2.2 prefetching scripts instructions when enabled by setting the prefetch enable bit (bit 5) in the dma control (dcntl) register, the prefetch logic in the lsi53c876 fetches 8 dwords of instructions. the prefetch logic automatically determines the maximum burst size that it can perform based on the burst length as determined by the values in the dma mode (dmode) register. if the unit cannot perform bursts of at least four dwords, it disables itself. while the
scsi functional description 2-15 chip is prefetching scripts instructions, the pci cache line size register value does not have any effect and the read line, read multiple, and write and invalidate commands are not used. note: this feature is only useful if fetching scripts instructions from main memory. due to the short access time of scripts ram, prefetching is not necessary when fetching instructions from this memory. the lsi53c876 may ?ush the contents of the prefetch unit under certain conditions, listed below, to ensure that the chip always operates from the most current version of the scripts instruction. when one of these conditions apply, the contents of the prefetch unit are automatically ?ushed. on every memory move instruction. the memory move instruction often places modi?ed code directly into memory. to make sure that the chip executes all recent modi?cations, the prefetch unit ?ushes its contents and loads the modi?ed code every time a instruction is issued. to avoid inadvertently ?ushing the prefetch unit contents, use the no flush option for all memory move operations that do not modify code within the next 8 dwords. for more information on this instruction, refer to chapter 5, scsi scripts instruction set. on every store instruction. the store instruction may also be used to place modi?ed code directly into memory. to avoid inadvertently ?ushing the prefetch unit contents use the no flush option for all store operations that do not modify code within the next 8 dwords. on every write to the dma scripts pointer (dsp) register. on all transfer control instructions when the transfer conditions are met. this is necessary because the next instruction to execute is not the sequential next instruction in the prefetch unit. when the prefetch flush bit ( dma control (dcntl) register , bit 6) is set. the unit ?ushes whenever this bit is set. the bit is self-clearing. 2.2.2.3 opcode fetch burst capability setting the burst opcode fetch enable bit (bit 1) in the dma mode (dmode) register (0x38) causes the lsi53c876 to burst in the ?rst two dwords of all instruction fetches. if the instruction is a memory-to-
2-16 functional description memory move, the third dword is accessed in a separate ownership. if the instruction is an indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move, the chip uses two accesses to obtain the four dwords required, in two bursts of two dwords each. note: this feature is only useful if prefetching is disabled and scripts instructions are fetched from main memory. due to the short access time of scripts ram, burst opcode fetching is not necessary when fetching instructions from this memory. 2.2.2.4 load/store instructions the lsi53c876 supports the load and store instruction type, which simpli?es the movement of data between memory and the internal chip registers. it also enables the chip to transfer bytes to addresses relative to the data structure address (dsa) register. for more information on the load and store instructions, refer to chapter 5, scsi scripts instruction set. 2.2.3 jtag boundary scan testing the lsi53c876 includes support for jtag boundary scan testing in accordance with the ieee 1149.1 speci?cation with one exception, which is explained in this section. this device accepts all required boundary scan instructions including the optional clamp, high-z, and idcode instructions. the lsi53c876 uses an 8-bit instruction register to support all boundary scan instructions. the data registers included in the device are the boundary data register, the idcode register, and the bypass register. this device can handle a 10 mhz tck frequency for tdo and tdi. due to design constraints, the rst/ pin (system reset) always 3-states the scsi pins when it is asserted. boundary scan logic does not control this action, and this is not compliant with the speci?cation. there are two solutions that resolve this issue:
scsi functional description 2-17 1. use the rst/ pin as a boundary scan compliance pin. when the pin deasserts, the device is boundary scan compliant and when it asserts, the device is noncompliant. to maintain compliance the rst/ pin must be driven high. 2. when rst/ asserts during boundary scan testing the expected output on the scsi pins must be the high-z condition, and not what is contained in the boundary scan data registers for the scsi pin output cells. 2.2.4 scsi loopback mode the lsi53c876 loopback mode allows testing of both initiator and target functions and, in effect, lets the chip communicate with itself. when the loopback enable bit is set in the scsi test two (stest2) register, bit 4, the lsi53c876 allows control of all scsi signals, whether the chip is operating in the initiator or target mode. for more information on this mode of operation, refer to the scsi scripts processors programming guide . 2.2.5 parity options the lsi53c876 implements a ?exible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the scsi bus to test parity error recovery procedures. table 2.2 de?nes the bits that are involved in parity control and observation. table 2.3 describes the parity control function of the enable parity checking and assert scsi even parity bits in the scsi control one (scntl1) register, bit 2. table 2.4 describes the options available when a parity error occurs. figure 2.2 shows where parity checking is done in the lsi53c876.
2-18 functional description table 2.2 bits used for parity control and generation bit name location description assert satn/ on parity errors scsi control zero (scntl0) , bit 1 causes the lsi53c876 to automatically assert satn/ when it detects a parity error while operating as an initiator. enable parity checking scsi control zero (scntl0) , bit 3 enables the lsi53c876 to check for parity errors. the lsi53c876 checks for odd parity. assert even scsi parity scsi control one (scntl1) , bit 2 determines the scsi parity sense generated by the lsi53c876 to the scsi bus. disable halt on satn/ or a parity error (target mode only) scsi control one (scntl1) , bit 5 causes the lsi53c876 not to halt operations when a parity error is detected in target mode. enable parity error interrupt scsi interrupt enable zero (sien0) , bit 0 determines whether the lsi53c876 generates an interrupt when it detects a scsi parity error. parity error scsi interrupt status zero (sist0) , bit 0 this status bit is set whenever the lsi53c876 detects a parity error on the scsi bus. status of scsi parity signal scsi status zero (sstat0) , bit 0 this status bit represents the active high current state of the scsi sdp0 parity signal. scsi sdp1 signal scsi status two (sstat2) , bit 0 this bit represents the active high current state of the scsi sdp1 parity signal. latched scsi parity scsi status two (sstat2) , bit 3 and scsi status one (sstat1) , bit 3 these bits re?ect the scsi odd parity signal corresponding to the data latched into the scsi input data latch (sidl) register. master parity error enable chip test four (ctest4) , bit 3 enables parity checking during master data phases. master data parity error dma status (dstat) , bit 6 set when the lsi53c876, as a pci master, detects a target device signaling a parity error during a data phase. master data parity error interrupt enable dma interrupt enable (dien) , bit 6 by clearing this bit, a master data parity error does not cause assertion of inta/ (or intb/), but the status bit is set in the dma status (dstat) register.
scsi functional description 2-19 table 2.3 scsi parity control epc aesp description 0 0 does not check for parity errors. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 0 1 does not check for parity errors. parity is generated when sending scsi data. asserts even parity when sending scsi data. 1 0 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 1 1 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts even parity when sending scsi data. 1. key: epc = enable parity checking (bit 3, scsi control zero (scntl0) ). asep = assert scsi even parity (bit 2, scsi control one (scntl1) ). table 2.4 scsi parity errors and interrupts dph par description 0 0 halts when a parity error occurs in the target or initiator mode and does not generate an interrupt. 0 1 halts when a parity error occurs in the target mode and generates an interrupt in target or initiator mode. 1 0 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is not generated. 1 1 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is generated. key: dhp = disable halt on satn/ or parity error (bit 5, scsi control one (scntl1) . par = parity error (bit 0, scsi interrupt enable zero (sien0) .
2-20 functional description figure 2.2 parity checking/generation 2.2.6 dma fifo the dma fifo is 4 bytes wide by 134 transfers deep. the dma fifo is illustrated in figure 2.3 . the default dma fifo size is 88 bytes to assure compatibility with older products in the lsi53c8xx family. the dma fifo size may be set to 536 bytes by setting the dma fifo size bit, bit 5, in the chip test five (ctest5) register. figure 2.3 dma fifo sections pci interface** dma fifo* (32 bits x 134) sodl register* scsi interface** x s pci interface** dma fifo* (32 bits x 134) sidl register* scsi interface** g x pci interface** dma fifo* (32 bits x 134) sodl register* scsi interface** x s sodr register* pci interface** dma fifo* (32 bits x 134) scsi interface** g x scsi fifo* (8 or 16 bits x 16) x * = no parity protection ** = parity protected asynchronous scsi send asynchronous scsi receive synchronous scsi send synchronous scsi receive x - check parity g - generate 32-bit even pci parity s - generate 8-bit odd scsi parity 134 transfers deep . . . 32 bytes wide 8 bits byte lane 3 8 bits byte lane 2 8 bits byte lane 1 8 bits byte lane 0 134 transfers deep . . . . . . 32 bytes wide 8 bits byte lane 3 8 bits byte lane 2 8 bits byte lane 1 8 bits byte lane 0
scsi functional description 2-21 the lsi53c876 automatically supports misaligned dma transfers. a 536-byte fifo allows the lsi53c876 to support 2, 4, 8, 16, 32, 64, or 128 dword bursts across the pci bus interface. 2.2.6.1 data paths the data path through the lsi53c876 depends on whether data is being moved into or out of the chip, and whether scsi data is being transferred asynchronously or synchronously. figure 2.4 shows how data is moved to/from the scsi bus in each of the different modes. the following steps determine if any bytes remain in the data path when the chip halts an operation: asynchronous scsi send C step 1. if the dma fifo size is set to 88 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between 0 and 88. if the dma fifo size is set to 536 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo (dfifo) register. and the result with 0x3ff for a byte count between 0 and 536. step 2. read bit 5 in the scsi status zero (sstat0) and scsi status two (sstat2) registers to determine if any bytes are left in the scsi output data latch (sodl) register. if bit 5 is set in the sstat0 or sstat2 register, then the least signi?cant byte or the most signi?cant byte in the scsi output data latch (sodl) register is full, respectively. checking this bit also reveals bytes left in the scsi output data latch (sodl) register from a chained move operation with an odd byte count.
2-22 functional description synchronous scsi send C step 1. if the dma fifo size is set to 88 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between 0 and 88. if the dma fifo size is set to 536 bytes (bit 5 of the chip test five (ctest5) register it set), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo (dfifo) register. and the result with 0x3ff for a byte count between 0 and 536. step 2. read bit 5 in the scsi status zero (sstat0) and scsi status two (sstat2) registers to determine if any bytes are left in the scsi output data latch (sodl) register. if bit 5 is set in the sstat0 or sstat2 register, then the least signi?cant byte or the most signi?cant byte in the scsi output data latch (sodl) register is full, respectively. checking this bit also reveals bytes left in the scsi output data latch (sodl) register from a chained move operation with an odd byte count. step 3. read bit 6 in the scsi status zero (sstat0) and scsi status two (sstat2) registers to determine if any bytes are left in the sodr register. if bit 6 is set in the scsi status zero (sstat0) or scsi status two (sstat2) register, then the least signi?cant byte or the most signi?cant byte in the sodr register is full, respectively. asynchronous scsi receive C step 1. if the dma fifo size is set to 88 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between 0 and 88.
scsi functional description 2-23 if the dma fifo size is set to 536 bytes (bit 5 of the chip test five (ctest5) register is set), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo (dfifo) register. and the result with 0x3ff for a byte count between 0 and 536. step 2. read bit 7 in the scsi status zero (sstat0) and scsi status two (sstat2) register to determine if any bytes are left in the scsi input data latch (sidl) register. if bit 7 is set in the sstat0 or sstat2, then the least signi?cant byte or the most signi?cant byte is full, respectively. step 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit ( scsi control two (scntl2) , bit 0) to determine whether a byte is left in the scsi wide residue (swide) register. synchronous scsi receive C step 1. if the dma fifo size is set to 88 bytes, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with ox7f for a byte count between 0 and 88. if the dma fifo size is set to 536 bytes (bit 5 of the chip test five (ctest5) register is set), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo (dfifo) register. and the result with 0x3ff for a byte count between 0 and 536. step 2. read the scsi status one (sstat1) register and examine bits [7:4], the binary representation of the number of valid bytes in the scsi fifo, to determine if any bytes are left in the scsi fifo. step 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit ( scsi control two (scntl2) , bit 0) to determine whether a byte is left in the scsi wide residue (swide) register.
2-24 functional description figure 2.4 shows how data is moved to/from the scsi bus in each of the different modes. figure 2.4 lsi53c876 host interface scsi data paths 2.2.7 scsi bus interface all scsi signals are active low. the lsi53c876 contains the se output drivers and can be connected directly to the scsi bus. each output is isolated from the power supply to ensure that a powered-down lsi53c876 has no effect on an active scsi bus (cmos voltage feed-through phenomena). tolerant technology provides signal ?ltering at the inputs of sreq/ and sack/ to increase immunity to signal re?ections. 2.2.7.1 differential mode in differential mode, the sdir[15:0], sdirp[1:0], igs, tgs, rstdir, bsydir, and seldir signals control the direction of external differential pair transceivers. the lsi53c876 is placed in differential mode by setting the dif bit, bit 5 of the scsi test two (stest2) register (0x4e). setting this bit 3-states the bsy/, sel/, and rst/ pads so they can be used as pure input pins. when tolerant active negation is enabled, the recommended resistor value on the req/, ack/, msg/, c_d/, i_o/, pci interface dma fifo (32 bits x 134) sodl register scsi interface pci interface dma fifo (32 bits x 134) sidl register scsi interface pci interface dma fifo (32 bits x 134) sodl register scsi interface sodr register pci interface dma fifo (32 bits x 134) scsi interface scsi fifo (8 or 16 bits x 16) asynchronous scsi send asynchronous scsi receive synchronous scsi send synchronous scsi receive swide register swide register
scsi functional description 2-25 atn/, sd[15:0], and sdp[1:0]/ signals is 1.5 k w . in addition to the standard scsi lines, the following signals de?ned in table 2.5 are used during differential operation by the lsi53c876: see figure 2.5 for an example differential wiring diagram, in which the lsi53c876 is connected to the ti sn75976a differential transceiver. the recommended value of the pull-up resistor on the req/, ack/, msg/, c/d/, i/o/, atn/, sd[15:0]/, sdp0/, and sdp1/ lines is 680 w when the active negation portion of lsi logic tolerant technology is not enabled. when tolerant technology is enabled, the recommended resistor value on the req/, ack/, sd[7:0]/, and sdp0/ signals is 1.5 k w. the electrical characteristics of these pins change when tolerant is enabled, permitting a higher resistor value. to interface the lsi53c876 to the sn75976a, connect the dir pins, as well as igs and tgs, of the lsi53c876 directly to the transceiver enables (nde/re/). these signals control the direction of the channels on the sn75976a. the scsi bidirectional control and data pins (sd[15:0]/, sdp0/, sdp1/, req/, ack/, msg/, i_o/, c_d/, and atn/) of the lsi53c876 connect to the bidirectional data pins (na) of the sn75976a with a pull-up resistor. the three remaining pins, sel/, bsy/, and rst/ are connected to the sn75976a with a pull-down resistor. the pull-down resistors are required table 2.5 differential mode signal function bsydir, seldir, rstdir active high signals used to enable the differential drivers as outputs for scsi signals bsy/, sel/, and rst/, respectively. sdir[15:0], sdirp[1:0] active high signals used to control direction of the differential drivers for scsi data and parity lines, respectively. igs active high signal used to control direction of the differential driver for initiator group signals atn/ and ack/. tgs active high signal used to control direction of the differential drivers for target group signals msg/, c/d/, i/o/, and req/. diffsens input to the lsi53c876 used to detect the presence of an se device on a differential system. if a logical zero is detected on this pin, then it is assumed that an se device is on the bus and all scsi outputs will be 3-stated to avoid damage to the transceiver.
2-26 functional description when the pins (na) of the sn75976a are con?gured as inputs. when the data pins are inputs, the resistors provide a bias voltage to both the lsi53c876 pins (sel/, bsy/, and rst/) and the sn75976a data pins. because the sel/, bsy/, and rst/ pins on the lsi53c876 are inputs only, this con?guration allows for the sel/, bsy/, and rst/ scsi signals to be asserted on the scsi bus. the differential pairs on the scsi bus are reversed when connected to the sn75976a, due to the active low nature of the scsi bus. the pull-up value should be no lower than the transceiver i ol can tolerate, but not so high as to cause rc timing problems. note: use the ti sn75976a differential transceivers to achieve ultra scsi transfer rates. 8-bit/16-bit scsi and the differential interface C in an 8-bit scsi bus, the sd[15:8] pins on the lsi53c876 should be pulled up with a 1.5 k w . resistor or terminated like the rest of the scsi bus lines. this is very important, as errors may occur during reselection if these lines are left ?oating.
scsi functional description 2-27 figure 2.5 lsi53c876 differential wiring diagram sdirp0 sdir7 sdir6 sdir5 sdir4 sdir3 sdir2 sdir1 sdir0 sdp/ sd7/ sd6/ sd5/ sd4/ sd3/ sd2/ sd1/ sd0/ seldir bsydir rstdir sel/ bsy/ rst/ req/ ack/ msg/ c/d/ i/o/ atn/ tgs igs 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re cde0 cde1 cde2 bsr cre 1b+ 1b- 2b+ 2b- 3b+ 3b- 4b+ 4b- 5b+ 5b- 6b+ 6b- 7b+ 7b- 8b+ 8b- 9b+ 9b- sn75976a #1 sd0/ sd1/ sd7/ sdp0/ sdir0 sdir1 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re cde0 cde1 cde2 bsr cre 1b+ 1b- 2b+ 2b- 3b+ 3b- 4b+ 4b- 5b+ 5b- 6b+ 6b- 7b+ 7b- 8b+ 8b- 9b+ 9b- diffsens seldir bsydir rstdir sel/ bsy/ rst/ req/ ack/ msg/ c_d/ i_o/ atn/ -sel (42) +sel (41) -bsy (34) +bsy (33) -rst (38) +rst (37) -req (46) +req (45) -ack (36) +ack (35) -msg (40) +msg (39) -c/d (44) +c/d (43) -i/o (48) +i/o (47) -atn (30) +atn (29) -db0 (4) +db0 (3) -db1 (6) +db1 (5) -db2 (8) +db2 (7) -db3 (10) +db3 (9) -db4 (12) +db4 (11) -db5 (14) +db5 (13) -db6 (16) +db6 (15) -db7 (18) +db7 (17) -dbp (20) +dbp (19) lsi538760 scsi bus vdd 1.5 k 1.5 k w diffsens (pin 21) schottky diode diffsens vdd vdd vdd 1.5 k w vdd 1.5 k w 1.5 k w 1.5 k w sn75976a #2 sd2/ sd3/ sdir2 sd4/ sd5/ sd6/ sdir3 sdir4 sdir5 sdir6 sdir7 sdirp0
2-28 functional description figure 2.5 lsi53c876 differential wiring diagram (cont.) 2.2.7.2 terminator networks the terminator networks provide the biasing needed to pull signals to an inactive voltage level, and to match the impedance seen at the end of the cable with the characteristic impedance of the cable. terminators must be installed at the extreme ends of the scsi chain, and only at the ends. no system should ever have more or less than two terminators installed and active. scsi host adapters should provide a means of accommodating terminators. there should be a means of disabling termination. se cables can use a 220 w pull-up to the terminator power supply (term power) line and a 330 w pull-down to ground. because of the high-performance nature of the lsi53c876, regulated (or active) termination is recommended. figure 2.6 shows a unitrode active terminator. for additional information, refer to the scsi-2 speci?cation. tolerant technology active negation can be used with either termination network. sdirp0/1 sdir15 sdir14 sdir13 sdir12 sdir11 sdir10 sdir9 sdir8 sdp1/ sd15/ sd14/ sd13/ sd12/ sd11/ sd10/ sd9/ sd8/ sd8/ sd9/ sd15/ sdp1/ sdir8 sdir9 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re cde0 cde1 cde2 bsr cre 1b+ 1b- 2b+ 2b- 3b+ 3b- 4b+ 4b- 5b+ 5b- 6b+ 6b- 7b+ 7b- 8b+ 8b- 9b+ 9b- -db0 (4) +db0 (3) -db1 (6) +db1 (5) -db2 (8) +db2 (7) -db3 (10) +db3 (9) -db4 (12) +db4 (11) -db5 (14) +db5 (13) -db6 (16) +db6 (15) -db7 (18) +db7 (17) -dbp (20) +dbp (19) lsi538760 diffsens vdd 1.5 k w sn75976a #3 sd10/ sd11/ sdir10 sd12/ sd13/ sd14/ sdir11 sdir12 sdir13 sdir14 sdir15 sdirp1 diffsens diffsens (cont.) to scsi bus
scsi functional description 2-29 note: if the lsi53c876 is to be used in a design with only an 8-bit scsi bus, all 16 data lines must still be terminated or pulled high. active termination is required for wide ultra scsi synchronous transfers. figure 2.6 regulated termination terml1 terml2 terml3 terml4 terml5 terml6 terml7 terml8 terml9 terml10 terml11 terml12 terml13 terml14 terml15 terml16 terml17 terml18 sd0 (j1.40) sd1 (j1.41) sd2 (j1.42) sd3 (j1.43) sd4 (j1.44) sd5 (j1.45) sd6 (j1.46) sd7 (j1.47) sdp (j1.48) atn (j1.55) bsy (j1.57) ack (j1.58) rst (j1.59) msg (j1.60) sel (j1.61) c/d (j1.62) req (j1.63) i/o (j1.64) 20 21 22 23 24 25 26 27 28 3 4 5 6 7 8 9 10 11 19 disconnect reg_out 2 2.85 v uc5601qp c1 c2 notes: c1 - 10 m f smt c2 - 0.1 m f smt c3 - 2.2 m f smt j1 - 68-pin, high density p connector terml1 terml2 terml3 terml4 terml5 terml6 terml7 terml8 terml9 sd15 (j1.38) sd14 (j1.37) sd13 (j1.36) sd12 (j1.35) sd11 (j1.68) sd10 (j1.67) sd9 (j1.66) sd8 (j1.65) sdp1 (j1.39) 10 9 8 7 3 2 1 16 15 reg_out 14 uc5603dp c3 6 disconnect
2-30 functional description 2.2.8 synchronous operation the lsi53c876 can transfer synchronous scsi data in both initiator and target modes. the scsi transfer (sxfer) register controls both the synchronous offset and the transfer period. it may be loaded by the cpu before scripts execution begins, from within scripts using a table indirect i/o instruction, or with a read-modify-write instruction. the lsi53c876 can receive data from the scsi bus at a synchronous transfer period as short as 50 ns, regardless of the transfer period used to send data. the chip can receive data at one-fourth of the divided sclk frequency. depending on the sclk frequency, the negotiated transfer period, and the synchronous clock divider, the chip can send synchronous data at intervals as short as 50 ns for ultra scsi, 100 ns for fast scsi, and 200 ns for scsi-1. 2.2.8.1 determining the data transfer rate synchronous data transfer rates are controlled by bits in two different registers of the lsi53c876. following is a brief description of the bits. figure 2.7 illustrates the clock division factors used in each register, and the role of the register bits in determining the transfer rate. 2.2.8.2 scsi control three (scntl3) register, bits [6:4] (scf[2:0]) the scf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. the output from this divider controls the rate at which data can be received; this rate must not exceed 80 mhz. the receive rate is one-fourth of the divider output. 2.2.8.3 scsi control three (scntl3) register, bits [2:0] (ccf[2:0] the ccf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the asynchronous scsi controller logic. this divider must be set according to the input clock frequency in the table. 2.2.8.4 scsi transfer (sxfer) register, bits [7:5] (tp[2:0]) the tp[2:0] bits determine the scsi synchronous transfer period when sending synchronous scsi data in either initiator or target mode.
scsi functional description 2-31 2.2.8.5 wide ultra scsi synchronous transfers wide ultra scsi is an extension of current fast scsi synchronous transfer speci?cations. it allows synchronous transfer periods to be negotiated down as low as 50 ns, which is half the 100 ns period allowed under fast scsi. this allows a maximum transfer rate of 40 mbytes/s on a 16-bit scsi bus. the lsi53c876 requires that the 40 mhz clock is doubled by the internal clock doubler (see the scsi test one (stest1) register description) to perform wide ultra scsi transfers. in addition, the following bit values affect the chips ability to support wide ultra scsi synchronous transfer rates: clock conversion factor bits, scsi control three (scntl3) register bits [2:0] and synchronous clock conversion factor bits, scntl3 register bits [6:4]. these ?elds now support a value of 101 (binary), allowing the sclk frequency to be divided down by 4. this allows systems with a 40 mhz clock to operate at fast scsi-2 transfer rates as well as wide ultra scsi rates, if needed. wide ultra scsi mode enable bit, scsi control three (scntl3) register, bit 7. setting this bit enables wide ultra scsi synchronous transfers in systems that have a 40 mhz clock using the internal clock doubler. tolerant enable bit, scsi test three (stest3) register, bit 7. setting this bit enables active negation.
2-32 functional description figure 2.7 determining the synchronous transfer rate 2.2.9 designing a wide ultra scsi system migrating an existing scsi design from fast scsi to wide ultra scsi requires minor software modi?cations as well as consideration for some hardware design guidelines. since wide ultra scsi is based on existing scsi standards, it can use existing software programs as long as the software is able to negotiate for wide ultra scsi synchronous transfer rates. in the area of hardware, the primary area of concern in se systems is to maintain signal integrity at high data transfer rates. to assure reliable operation at wide ultra scsi transfer speeds, follow the system design parameters recommended in the wide ultra scsi parallel interface draft standard. chapter 6, electrical characteristics, contains wide ultra sclk scf divider ccf divider synchronous divider asynchronous scsi logic divide by 4 scf2 scf1 scf0 scf divisor 0011 0 1 0 1.5 0112 1003 0003 tp2 tp1 tp0 xferp divisor 0004 0015 0106 0117 1008 1019 11010 11111 ccf2 ccf1 ccf0 divisor 0011 0 1 0 1.5 0112 1003 0003 example: sclk = 40 mhz, scf = 1, xferp = 4, scsi transfer rate = 10 mhz, ccf = 2 this point must not exceed 80 mhz receive clock this point must not exceed 25 mhz (40 mhz 1 = synchronous core rate) (40 mhz 4 = 10 mhz synchronous rate = 10 mbytes/s on an 8-bit scsi bus) send clock to scsi bus clk doubler 40 mhz
scsi functional description 2-33 scsi timing information. in addition to the guidelines in the draft standard, make the following software and hardware adjustments to accommodate wide ultra scsi transfers: set the wide ultra scsi enable bit to enable wide ultra scsi transfers. set the tolerant enable bit, bit 7 in the scsi test three (stest3) register, whenever the wide ultra scsi enable bit is set. do not extend the sreq/sack ?ltering period with scsi test two (stest2), bit 1. use a 40 mhz scsi clock with an internal clock doubler. 2.2.10 interrupt handling the scripts processors in the lsi53c876 performs most functions independently of the host microprocessor. however, certain interrupt situations must be handled by the external microprocessor. this section explains all aspects of interrupts as they apply to the lsi53c876. 2.2.10.1 polling and hardware interrupts the external microprocessor is informed of an interrupt condition by polling or hardware interrupts. polling means that the microprocessor must continually loop and read a register until it detects a bit set that indicates an interrupt. this method is the fastest, but it wastes cpu time that could be used for other system tasks. the preferred method of detecting interrupts in most systems is hardware interrupts. in this case, the lsi53c876 asserts the interrupt request (inta/ or intb/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine. a hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.2.10.2 registers the registers in the lsi53c876 that are used for detecting or de?ning interrupts are the interrupt status (istat) , scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , dma status (dstat) , scsi interrupt enable zero (sien0) , scsi interrupt enable one (sien1) , dma control (dcntl) , and dma interrupt enable (dien) .
2-34 functional description istat C the interrupt status (istat) is the only register that can be accessed as a slave during scripts operation. therefore, it is the register that is polled when polled interrupts are used. it is also the ?rst register that should be read after the inta/ (or intb/) pin is asserted in association with a hardware interrupt. the intf (interrupt-on-the-fly) bit should be the ?rst interrupt serviced. it must be written to one to be cleared. this interrupt must be cleared before servicing any other interrupts. if the sip bit in the interrupt status (istat) register is set, then a scsi-type interrupt has occurred and the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers should be read. if the dip bit in the interrupt status (istat) register is set, then a dma-type interrupt has occurred and the dma status (dstat) register should be read. scsi-type and dma-type interrupts may occur simultaneously, so in some cases both sip and dip may be set. sist0 and sist1 C the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers contain the scsi-type interrupt bits. reading these registers determines which condition or conditions caused the scsi-type interrupt, and clears that scsi interrupt condition. if the lsi53c876 is receiving data from the scsi bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the dma fifo to memory before generating the interrupt. if the lsi53c876 is sending data to the scsi bus and a fatal scsi interrupt condition occurs, data could be left in the dma fifo. because of this the dma fifo empty (dfe) bit in dma status (dstat) should be checked. if this bit is cleared, set the clf (clear dma fifo) and csf (clear scsi fifo) bits before continuing. the clf bit is bit 2 in chip test three (ctest3) . the csf bit is bit 1 in scsi test three (stest3) . dstat C the dma status (dstat) register contains the dma-type interrupt bits. reading this register determines which condition or conditions caused the dma-type interrupt, and clears that dma interrupt condition. bit 7 in dma status (dstat) , dfe, is purely a status bit; it will not generate an interrupt under any circumstances and is not cleared
scsi functional description 2-35 when read. dma interrupts ?ush neither the dma nor scsi fifos before generating the interrupt, so the dfe bit in the dma status (dstat) register should be checked after any dma interrupt. if the dfe bit is cleared, then the fifos must be cleared by setting the clf (clear dma fifo) and csf (clear scsi fifo) bits, or ?ushed by setting the flf (flush dma fifo) bit. sien0 and sien1 C the scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) registers are the interrupt enable registers for the scsi interrupts in scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) . dien C the dma interrupt enable (dien) register is the interrupt enable register for dma interrupts in dma status (dstat) . dcntl C when bit 1 in this register is set, the inta/ (or intb/) pin is not asserted when an interrupt condition occurs. the interrupt is not lost or ignored, but merely masked at the pin. clearing this bit when an interrupt is pending immediately causes the inta/ (or intb/) pin to assert. as with any register other than interrupt status (istat) , this register cannot be accessed except by a scripts instruction during scripts execution. 2.2.10.3 fatal vs. nonfatal interrupts a fatal interrupt, as the name implies, always causes the scripts to stop running. all nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. interrupt masking is discussed section 2.2.10.4, masking. all dma interrupts (indicated by the dip bit in interrupt status (istat) and one or more bits in dma status (dstat) being set) are fatal. some scsi interrupts (indicated by the sip bit in the interrupt status (istat) and one or more bits in scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) being set) are nonfatal. when the lsi53c876 is operating in the initiator mode, only the function complete (cmp), selected (sel), reselected (rsl), general purpose timer expired (gen), and handshake-to-handshake timer expired (hth) interrupts are nonfatal.
2-36 functional description when operating in target mode cmp, sel, rsl, target mode: satn/ active (m/a), gen, and hth are nonfatal. refer to the description for the disable halt on a parity error or satn/ active (target mode only) (dhp) bit in the scsi control one (scntl1) register to con?gure the chips behavior when the satn/ interrupt is enabled during target mode operation. the interrupt-on-the-fly interrupt is also nonfatal, since scripts can continue when it occurs. the reason for nonfatal interrupts is to prevent scripts from stopping when an interrupt occurs that does not require service from the cpu. this prevents an interrupt when arbitration is complete (cmp set), when the lsi53c876 is selected or reselected (sel or rsl set), when the initiator asserts atn (target mode: satn/ active), or when the general purpose or handshake-to-handshake timers expire. these interrupts are not needed for events that occur during high-level scripts operation. 2.2.10.4 masking masking an interrupt means disabling or ignoring that interrupt. interrupts can be masked by clearing bits in the scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) (for scsi interrupts) registers or dien (for dma interrupts) register. how the chip responds to masked interrupts depends on: whether polling or hardware interrupts are being used; whether the interrupt is fatal or nonfatal; and whether the chip is operating in the initiator or target mode. if a nonfatal interrupt is masked and that condition occurs, the scripts do not stop, the appropriate bit in the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) is still set, the sip bit in the istat is not set, and the inta/ (or intb/) pin is not asserted. see section 2.2.10.3, fatal vs. nonfatal interrupts, for a list of the nonfatal interrupts. if a fatal interrupt is masked and that condition occurs, then the scripts still stop, the appropriate bit in the dma status (dstat) , scsi interrupt status zero (sist0) ,or scsi interrupt status one (sist1) register is set, and the sip or dip bits in the istat is set, but the inta/ (or intb/) pin is not asserted.
scsi functional description 2-37 when the chip is initialized, enable all fatal interrupts if you are using hardware interrupts. if a fatal interrupt is disabled and that interrupt condition occurs, the scripts halts and the system never knows it unless it times out and checks the istat after a certain period of inactivity. if you are polling the interrupt status (istat) instead of using hardware interrupts, then masking a fatal interrupt makes no difference since the sip and dip bits in the istat inform the system of interrupts, not the inta/ (or intb/) pin. masking an interrupt after inta/ (or intb/) is asserted does not cause deassertion of inta/ (or intb/). 2.2.10.5 stacked interrupts the lsi53c876 stacks interrupts if they occur one after the other. if the sip or dip bits in the interrupt status (istat) register are set (?rst level), then there is already at least one pending interrupt, and any future interrupts are stacked in extra registers behind the scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) registers (second level). when two interrupts have occurred and the two levels of the stack are full, any further interrupts set additional bits in the extra registers behind sist0, sist1, and dstat. when the ?rst level of interrupts are cleared, all the interrupts that came in afterward move into the sist0, sist1, and dstat. after the ?rst interrupt is cleared by reading the appropriate register, the inta/ (or intb/) pin is deasserted for a minimum of three clks; the stacked interrupts move into the sist0, sist1, or dstat; and the inta/ (or intb/) pin is asserted once again. since a masked nonfatal interrupt does not set the sip or dip bits, interrupt stacking does not occur. a masked, nonfatal interrupt still posts the interrupt in sist0, but does not assert the inta/ (or intb/) pin. since no interrupt is generated, future interrupts move right into the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) instead of being stacked behind another interrupt. when another condition occurs that generates an interrupt, the bit corresponding to the earlier masked nonfatal interrupt is still set.
2-38 functional description a related situation to interrupt stacking is when two interrupts occur simultaneously. since stacking does not occur until the sip or dip bits are set, there is a small timing window in which multiple interrupts can occur but are not stacked. these could be multiple scsi interrupts (sip set), multiple dma interrupts (dip set), or multiple scsi and multiple dma interrupts (both sip and dip set). as previously mentioned, dma interrupts do not attempt to ?ush the fifos before generating the interrupt. it is important to set either the clear dma fifo (clf) and clear scsi fifo (csf) bits if a dma interrupt occurs and the dma fifo empty (dfe) bit is not set. this is because any future scsi interrupts are not posted until the dma fifo is cleared of data. these locked out scsi interrupts are posted as soon as the dma fifo is empty. 2.2.10.6 halting in an orderly fashion when an interrupt occurs, the lsi53c876 attempts to halt in an orderly fashion. if the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a bus fault. execution does not begin, but the dma scripts pointer (dsp) points to the next instruction since it is updated when the current instruction is fetched. if the dma direction is a write to memory and a scsi interrupt occurs, the lsi53c876 attempts to ?ush the dma fifo to memory before halting. under any other circumstances only the current cycle is completed before halting, so the dfe bit in dma status (dstat) register should be checked to see if any data remains in the dma fifo. scsi sreq/sack handshakes that have begun are completed before halting. the lsi53c876 attempts to clean up any outstanding synchronous offset before halting. in the case of transfer control instructions, once instruction execution begins it continues to completion before halting. if the instruction is a jump/call when/if , the dma scripts pointer (dsp) is updated to the transfer address before halting. all other instructions may halt before completion.
scsi functional description 2-39 2.2.10.7 sample interrupt service routine the following is a sample of an interrupt service routine for the lsi53c876. it can be repeated if polling is used, or should be called when the inta/ (or intb/) pin is asserted during hardware interrupts. 1. read interrupt status (istat) . 2. if the intf bit is set, it must be written to a one to clear this status. 3. if only the sip bit is set, read scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) to clear the scsi interrupt condition and get the scsi interrupt status. the bits in the sist0 and sist1 tell which scsi interrupts occurred and determine what action is required to service the interrupts. 4. if only the dip bit is set, read the dma status (dstat) to clear the interrupt condition and get the dma interrupt status. the bits in the dstat tells which dma interrupts occurred and determine what action is required to service the interrupts. 5. if both the sip and dip bits are set, read scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) to clear the scsi and dma interrupt condition and get the interrupt status. if using 8-bit reads of the sist0, sist1, and dstat registers to clear interrupts, insert a 12 clk delay between the consecutive reads to ensure that the interrupts clear properly. both the scsi and dma interrupt conditions should be handled before leaving the interrupt service routine. it is recommended that the dma interrupt is serviced before the scsi interrupt, because a serious dma interrupt condition could in?uence how the scsi interrupt is acted upon. 6. when using polled interrupts, go back to step 1 before leaving the interrupt service routine, in case any stacked interrupts moved in when the ?rst interrupt was cleared. when using hardware interrupts, the inta/ (or intb/) pin is asserted again if there are any stacked interrupts. this should cause the system to re-enter the interrupt service routine.
2-40 functional description 2.2.11 chained block moves since the lsi53c876 has the capability to transfer 16-bit wide scsi data, a unique situation occurs when dealing with odd bytes. the chained move (chmov) scripts instruction along with the wide scsi send (wss) and wide scsi receive (wsr) bits in the scsi control two (scntl2) register are used to facilitate these situations. the chained block move instruction is illustrated in figure 2.8 . figure 2.8 block move and chained block move instructions chmov 5, 3 when data_out moves ?ve bytes from address 0x03 in the host memory to the scsi bus. bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in the low-order byte of the scsi output data latch (sodl) register and is combined with the ?rst byte of the following move instruction. move 5, 9 when data_out moves ?ve bytes from address 0x09 in the host memory to the scsi bus. 0x03 0x02 0x01 0x00 0x07 0x06 0x05 0x04 0x0b 0x0a 0x09 0x08 0x0f 0x0e 0x0d 0x0c 0x13 0x12 0x11 0x10 0x04 0x03 0x06 0x05 0x09 0x07 0x0b 0x0a 0x0d 0x0c 32 bits 16 bits host memory scsi bus 00 04 08 0c 10
scsi functional description 2-41 2.2.11.1 wide scsi send bit the wss bit is set whenever the scsi controller is sending data (data-out for initiator or data-in for target), and the controller detects a partial transfer at the end of a chained block move scripts instruction (this ?ag is not set if a normal block move instruction is used). under this condition, the scsi controller does not send the low-order byte of the last partial memory transfer across the scsi bus. instead, the low-order byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register and the wss ?ag is set. the hardware uses the wss ?ag to determine what behavior must occur at the start of the next data send transfer. when the wss ?ag is set at the start of the next transfer, the ?rst byte (the high-order byte) of the next data send transfer is married with the stored low-order byte in the scsi output data latch (sodl) register; and the two bytes are sent out across the bus, regardless of the type of block move instruction (normal or chained). the ?ag is automatically cleared when the married word is sent. the ?ag is alternately cleared through scripts or by the microprocessor. also, the microprocessor or scripts can use this bit for error detection and recovery purposes. 2.2.11.2 wide scsi receive bit the wsr bit is set whenever the scsi controller is receiving data (data-in for initiator or data-out for target) and the controller detects a partial transfer at the end of a block move or chained block move scripts instruction. when wsr is set, the high order byte of the last scsi bus transfer is not transferred to memory. instead, the byte is temporarily stored in the scsi wide residue (swide) register. the hardware uses the wsr bit to determine what behavior must occur at the start of the next data receive transfer. the bit is automatically cleared at the start of the next data receive transfer. the bit can alternatively be cleared by the microprocessor or through scripts. also, the microprocessor or scripts can use this bit for error detection and recovery purposes. 2.2.11.3 swide register this register stores data for partial byte data transfers. for receive data, the scsi wide residue (swide) register holds the high-order byte of a partial scsi transfer that has not yet been transferred to memory. this
2-42 functional description stored data may be a residue byte (and therefore ignored) or it may be valid data that is transferred to memory at the beginning of the next block move instruction. 2.2.11.4 sodl register for send data, the low-order byte of the scsi output data latch (sodl) register holds the low-order byte of a partial memory transfer which has not yet been transferred across the scsi bus. this stored data is usually married with the ?rst byte of the next data send transfer, and both bytes are sent across the scsi bus at the start of the next data send block move command. 2.2.11.5 chained block move scripts instruction a chained block move scripts instruction is primarily used to transfer consecutive data send or data receive blocks. using the chained block move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. behavior of the chained block move instruction varies slightly for sending and receiving data. for receive data (data-in for initiator or data-out for target), a chained block move instruction indicates that if a partial transfer occurred at the end of the instruction, the wsr ?ag is set. the high-order byte of the last scsi transfer is stored in the scsi wide residue (swide) register rather than transferred to memory. the contents of the scsi wide residue (swide) register should be the ?rst byte transferred to memory at the start of the chained block move data stream. since the byte count always represents data transfers to/from memory (as opposed to the scsi bus), the byte transferred out of the scsi wide residue (swide) register is one of the bytes in the byte count. if the wsr bit is cleared when a receive data chained block move instruction is executed, the data transfer occurs similar to that of the regular block move instruction. whether the wsr bit is set or cleared, when a normal block move instruction is executed, the contents of the scsi wide residue (swide) register are ignored and the transfer takes place normally. for n consecutive wide data receive block move instructions, the 2nd through the nth block move instructions should be chained block moves.
parallel rom interface 2-43 for send data (data-out for initiator or data-in for target), a chained block move instruction indicates that if a partial transfer terminates the chained block move instruction, the last low-order byte (the partial memory transfer) should be stored in the lower byte of the scsi output data latch (sodl) register and not sent across the scsi bus. without the chained block move instruction, the last low-order byte would be sent across the scsi bus. the starting byte count represents data bytes transferred from memory but not to the scsi bus when a partial transfer exists. for example, if the instruction is an initiator chained block move data out of ?ve bytes (and wss is not previously set), ?ve bytes are transferred out of memory to the scsi controller, four bytes are transferred from the scsi controller across the scsi bus, and one byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register waiting to be married with the ?rst byte of the next block move instruction. regardless of whether a chained block move or normal block move instruction is used, if the wss bit is set at the start of a data send command, the ?rst byte of the data send command is assumed to be the high-order byte and is married with the low-order byte stored in the stored in the lower byte of the scsi output data latch (sodl) register before the two bytes are sent across the scsi bus. for n consecutive wide data send block move commands, the ?rst through the (nth C 1) block move instructions should be chained block moves. 2.3 parallel rom interface the lsi53c876 supports up to one megabyte of external memory in binary increments from 16 kbytes, to allow the use of expansion rom for add-in pci cards. both functions of the device share the rom interface. this interface is designed for low speed operations such as downloading instruction code from rom; it is not intended for dynamic activities such as executing instructions. system requirements include the lsi53c876, two or three external 8-bit address holding registers (hct273 or hct374), and the appropriate memory device. the 4.7 k w pull-down resistors on the mad bus require hc or hct external components to be used. if in-system flash rom updates are required, a 7406 (high voltage open collector inverter), a mtd4p05, and several passive components are also needed. the memory size and speed is determined by pull-down resistors on the 8-bit bidirectional memory bus at power-up. the lsi53c876 senses this
2-44 functional description bus shortly after the release of the reset signal and con?gures the rom base address register and the memory cycle state machines for the appropriate conditions. the external memory interface works with a variety of rom sizes and speeds. an example set of interface drawings is in appendix b, external memory interface diagram examples. the lsi53c876 supports a variety of sizes and speeds of expansion rom, using pull-down resistors on the mad[3:0] pins. the encoding of pins mad[3:1] allows the user to de?ne how much external memory is available to the lsi53c876. table 2.6 shows the memory space associated with the possible values of mad[3:1]. the mad[3:1] pins are fully de?ned in chapter 3, signal descriptions. to use one of the con?gurations mentioned above in a host adapter board design, put 4.7 k w pull-down resistors on the mad pins corresponding to the available memory space. for example, to connect to a 32 kbytes external rom, use pull-downs on mad[3] and mad[2]. if the external memory interface is not used, then no external resistors are necessary since there are internal pull-ups on the mad bus. the internal pull-up resistors are disabled when external pull-down resistors are detected, to reduce current drain. table 2.6 parallel rom support mad[3:1] available memory space 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present
serial eeprom interface 2-45 the lsi53c876 allows the system to determine the size of the available external memory using the expansion rom base address register in pci con?guration space. for more information on how this works, refer to the pci speci?cation or the expansion rom base address register description in chapter 4, registers. mad[0] is the slow rom pin. when pulled down, it enables two extra clock cycles of data access time to allow use of slower memory devices. the external memory interface also supports updates to flash memory. 2.4 serial eeprom interface the lsi53c876 implements an interface that allows attachment of a serial eeprom device to the gpio0 and gpio1 pins for each scsi function. there are several modes of operation. these relate to the serial eeprom and the subsystem id register and subsystem vendor id register for each scsi function. these modes are programmable through the mad6 and mad7 pins which are sampled at power-up or hard reset. 2.4.1 mode a operation no pull-down on mad6, no pull-down on mad7. in this mode, gpio0 is the serial data signal (sda) and gpio1 is the serial clock signal (scl). certain data in the serial eeprom is automatically loaded into chip registers at power-up or hard reset. the format of the serial eeprom data is de?ned in table 2.7 . if the eeprom is not present, or the checksum fails, the subsystem id and subsystem vendor id registers read back all zeros. at power-up or hard reset, only ?ve bytes are loaded into the chip from locations 0x00 through 0x04. the subsystem id and subsystem vendor id registers are read only, in accordance with the pci speci?cation, with a default value of all zeros.
2-46 functional description 2.4.2 mode b operation a 4.7 k pull-down on mad6, no pull-down on mad7. in this mode, gpio0 and gpio1 are each de?ned as either the sda or the scl, since both pins are controlled through software. no data is automatically loaded into chip registers at power-up or hard reset. the subsystem id register and subsystem vendor id register are read/write, in violation of the pci speci?cation, with a default value of all zeros. 2.4.3 mode c operation a 4.7 k pull-down on mad6, and a 4.7 k pull-down on mad7. in this mode, gpio1 is the sda and gpio0 is the scl. certain data in the serial eeprom is automatically loaded into chip registers at power-up or hard reset. table 2.7 mode a serial eeprom data format byte name description 0x00 svid(0) subsystem vendor id , lsb. this byte is loaded into the least signi?cant byte of the subsystem vendor id register in the appropriate pci con?guration space at chip power-up or hard reset. 0x01 svid(1) subsystem vendor id , msb. this byte is loaded into the most signi?cant byte of the subsystem vendor id register in the appropriate pci con?guration space at chip power-up or hard reset. 0x02 sid(0) subsystem id , lsb. this byte is loaded into the least signi?cant byte of the subsystem id register in the appropriate pci con?guration space at chip power-up or hard reset. 0x03 sid(1) subsystem id , msb. this byte is loaded into the most signi?cant byte of the subsystem id register in the appropriate pci con?guration space at chip power-up or hard reset. 0x04 cksum checksum. this 8-bit checksum is formed by adding, bytewise, each byte contained in locations 0x00C0x03 to the seed value 0x55, and then taking the 2s complement of the result. 0x05C0xff rsv reserved. 0x100Ceom ud user data.
serial eeprom interface 2-47 the format of the serial eeprom data is de?ned in table 2.8 . if the eeprom is not present, or the checksum fails, the subsystem id and subsystem vendor id registers read back all zeros. at power-up or hard reset, only ?ve bytes are loaded into the chip from locations 0xfb through 0xff. the subsystem id and subsystem vendor id registers are read only, in accordance with the pci speci?cation, with a default value of all zeros. before implementing mode c, contact lsi logic for additional information. table 2.8 mode c serial eeprom data format byte name description 0x00C0xfa ud0 user data. 0xfb svid(0) subsystem vendor id , lsb. this byte is loaded into the least signi?cant byte of the subsystem vendor id register in the appropriate pci con?guration space at chip power-up or hard reset. 0xfc svid(1) subsystem vendor id , msb. this byte is loaded into the most signi?cant byte of the subsystem vendor id register in the appropriate pci con?guration space at chip power-up or hard reset. 0xfd sid(0) subsystem id , lsb. this byte is loaded into the least signi?cant byte of the subsystem id register in the appropriate pci con?guration space at chip power-up or hard reset. 0xfe sid(1) subsystem id , msb. this byte is loaded into the most signi?cant byte of the subsystem id register in the appropriate pci con?guration space at chip power-up or hard reset. 0xff cksum checksum. this 8-bit checksum is formed by adding, bytewise, each byte contained in locations 0x00C0x03 to the seed value 0x55, and then taking the 2s complement of the result. 0x100Ceom ud user data.
2-48 functional description 2.4.4 mode d operation no pull-down on mad6, and a 4.7 k pull-down on mad7. the subsystem id and the subsystem vendor id are automatically set to 0x1000. this allows the oem to have a non-zero value in the registers without requiring a serial eeprom on the board. 2.5 power management the lsi53c876e complies with the pci bus power management interface speci?cation, revision 1.0. the pci function power states d0, d1, d2, and d3 are de?ned in that speci?cation. d0 is the maximum powered state, and d3 is the minimum powered state. power state d3 is further categorized as d3hot or d3cold. the lsi53c876e power states shown in table 2.9 are independently controlled through two power state bits that are located in the pci con?guration space register 0x44. although the pci bus power management interface speci?cation does not allow power state transitions d2 to d1, d3 to d2, or d3 to d1, the lsi53c876e hardware places no restriction on transitions between power states. as the device transitions from one power level to a lower one, the attributes that occur from the higher power state level are carried over into the lower power state level. for example, d1 disables the scsi clk. therefore, d2 will include this attribute as well as the attributes de?ned table 2.9 power states con?guration register 0x44 bits [1:0] power state function 00 d0 maximum power 01 d1 disables scsi clock 10 d2 coma mode 11 d3 minimum power
power management 2-49 in the power state d2 section. the pci function power states d0, d1, d2, and d3 are described below. power state actions are separate for each function. 2.5.1 power state d0 power state d0 is the maximum power state and is the power-up default state for each function. 2.5.2 power state d1 power state d1 is a lower power state than d0. in this state, the lsi53c876 core is placed in the snooze mode and the scsi clk is disabled. in the snooze mode, a scsi reset does not generate an /irq signal. however, by setting the wakeup interrupt enable bit (bit 3 in the scsi interrupt enable one (sien1) register), then a scsi reset generates an /irq signal, but scsi clk is still disabled. 2.5.3 power state d2 power state d2 is a lower power state than d1. in this state, the lsi53c876 core is placed in the coma mode. the following pci con?guration space command register enable bits are suppressed: i/o space enable memory space enable bus mastering enable serr perr thus, the memory and i/o spaces cannot be accessed, and the lsi53c876 cannot be a pci bus master. furthermore, scsi and dma interrupts are disabled when in power state d2. if changed from power state d2 to power state d1 or d0, the previous values of the pci command register are restored. also, any pending interrupts before the function entered power state d2 are asserted.
2-50 functional description 2.5.4 power state d3 power state d3 is the minimum power state, which includes subsettings called d3hot and d3cold. d3hot allows the device to transition to d0 using software. the lsi53c876e is considered to be in power state d3cold when power is removed from the device. d3cold can transition to d0 by applying v cc and resetting the device. power state d3 is a lower power level than power state d2. in this state, the lsi53c876 core is placed in the coma mode. furthermore, the functions soft reset is continually asserted while in power state d3, which clears all pending interrupts and 3-states the scsi bus. in addition, the devices pci command register is cleared. if both lsi53c876e functions are placed in power state d3, the phase lock loop (pll) is disabled, which results in further power savings.
lsi53c876/876e pci to dual channel scsi multifunction controller 3-1 chapter 3 signal descriptions this chapter presents the lsi53c876 pin con?guration and signal de?nitions using tables and illustrations. figure 3.1 and figure 3.2 are the pin diagrams for all versions of the lsi53c876 and figure 3.3 is the functional signal grouping. the pin de?nitions are presented in table 3.1 through table 3.16 . this chapter is divided into the following sections: section 3.1, pci interface signals section 3.2, scsi bus interface signals section 3.3, rom/flash interface signals section 3.4, test interface signals section 3.5, power and ground signals section 3.6, mad bus programming
3-2 signal descriptions figure 3.1 lsi53c876 208-pin pqfp diagram 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 36 37 38 39 40 42 44 46 48 50 52 lsi53c876 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 41 43 45 47 49 51 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 121 120 119 118 117 115 113 111 109 107 105 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 116 114 112 110 108 106 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 192 193 194 195 196 198 200 202 204 206 208 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 197 199 201 203 205 207 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 88 89 90 91 92 94 96 98 100 102 104 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 93 95 97 99 101 103 note: nc pins are not connected. ad26 vss ad25 ad24 c_be3/ vdd-io idsel ad23 vss ad22 ad21 ad20 vdd-io ad19 vss ad18 ad17 ad16 vss c_be2/ frame/ vdd-io irdy/ vss trdy/ devsel/ nc stop/ vss perr/ vdd-io serr/ pa r c_be1/ vss ad15 ad14 ad13 vdd-io ad12 vss ad11 ad10 ad9 vss ad8 vdd-io c_be0/ ad7 ad8 vss ad5 a_s07/ a_sdp0/ a_satn/ vss-s a_sbsy/ a_sack/ a_srst/ a_smsg/ a_ssel/ vss-s a_sc_0/ a_sreq/ a_si_0/ a_sd8/ vss-s a_sd9/ a_sd10/ a_sd11/ vdd a_sdir8 a_sdir9 a_sdir10 a_sdir11 vss a_bsydir vdd-c a_rstdir vss-c a_seldir a_ios a_tgs a_diffens vdd b_sd12/ b_sd13/ b_sd14/ vss-s b_sd15/ b_sdp1/ b_sd0/ b_sd1/ vss-s b_sd2/ b_sd3/ b_sd4/ b_sd5/ vss-s b_sd6/ b_sd7/ b_sdp0/ b_satn/ vss-s ad27 ad28 vdd-a0 ad29 vss ad30 ad31 vdd-c req/ gnt/ vss-c clk rst/ inta/ intb/ mce/ masq/ moe/_testout mwe/ mas1/ vss a_sdir12 vdd a_sdir13 a_sdir14 a_sdir15 a_sdir0 a_sdir1 a_sdir2 a_sdir3 vss a_sdir4 a_sdir5 a_sdir6 a_sdir7 a_sdirp0/1 vdd a_sd12/ a_sd13/ a_sd14/ vss-s a_sd15/ a_sdp1/ a_sd0/ a_sd1/ vss-s a_sd2/ a_sd3/ a_sd4/ a_sd5/ vss-s a_sd6/ ad4 ad3 vdd-10 ad2 vss ad1 ad0 tck tdi tms td0 vdd-c sclk testin/ vss-c a_gpio0_fetch/ a_gpio1_master/ a_gpio2 a_gpio3 vss a_gpio4 mad7 vdd mad6 mad5 nc mad4 mad3 mad2 mad1 mad0 b_gpio1_fetch/ vss b_gpio1_master b_gpio2 b_gpio3 b_gpio3 vdd b_sd11/ b_sd10/ b_sd9/ vss-s b_sd8/ b_si_0/ b_sreq/ b_sc_d/ vss-s b_ssel/ b_smsg/ b_srst/ b_sack/ b_sbsy/ 208l pqfp top view
3-3 figure 3.2 lsi53c876 256-ball bga diagram (top view) ) a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 vss ad27 ad30 req/ rst/ mce/ mwe/ b_igs b_sdir13 vdd a_sdir13 a_sdir0 a_sdir4 a_sdir7 a_sd12/ a_sdp1/ a_sd2 a_sd3 a_sd6/ a_sd7/ b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 ad26 ad28 vdd-io ad31 gnt/ inta/ moe/_to mas1/ vdd a_sdir12 a_sdir15 a_sdir1 a_sdir5 a_dirp0/1 a_sd13/ a_sd0/ a_sd4/ a_sd5 a_sdp0/ a_satn/ c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 ad24 vss nc ad29 vdd-c vss-c intb/ mas0/ b_sdir12 b_sdir15 a_sdir14 a_sdir2 a_sdir6 vdd a_sd15/ a_sd1/ nc nc a_sbsy/ a_srst/ d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 c_be3/ ad25 nc vss vss nc clk vss b_tgs b_sdir14 nc a_sdir3 vss a_sd14/ nc nc vss nc a_smsg/ a_sc_d/ e1 e2 e3 e4 e17 e18 e19 e20 ad23 idsel vdd-io nc a_sack/ a_ssel/ a_sreq/ a_sd9/ f1 f2 f3 f4 f17 f18 f19 f20 ad21 ad22 vss nc nc a_si_o/ a_sd10/ vdd g1 g2 g3 g4 g17 g18 g19 g20 ad19 vdd-io ad20 nc a_sd8/ a_sd11/ a_sdir8 a_sdir9 h1 h2 h3 h4 h17 h18 h19 h20 ad17 ad18 vss vss vss a_sdir10 a_sdir11 a_bsydir j1 j2 j3 j4 j17 j18 j19 j20 frame/ c_be2/ vss ad16 vdd-c a_rstdir vss-c a_seldir k1 k2 k3 k4 k17 k18 k19 k20 vss vdd-io irdy/ nc a_igs a_tgs a_difsen vdd l1 l2 l3 l4 l17 l18 l19 l20 trdy/ devsel/ nc stop/ nc b_sdir1 b_sdir2 b_sdir0 m1 m2 m3 m4 m17 m18 m19 m20 vss perr/ vdd-io serr/ b_sdir6 b_sdir5 b_sdir4 b_sdir3 n1 n2 n3 n4 n17 n18 n19 n20 par c_be1/ vss vss vss vdd b_dirp0/1 b_sdir7 p1 p2 p3 p4 p17 p18 p19 p20 ad15 ad14 vdd-io ad11 b_sd0/ b_sd14/ b_sd13/ b_sd12/ r1 r2 r3 r4 r17 r18 r19 r20 ad13 ad12 ad10 nc nc b_sd1/ b_sdp1/ b_sd15/ t1 t2 t3 t4 t17 t18 t19 t20 vss ad9 ad8 nc nc b_sd4/ b_sd3/ b_sd2/ u1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 vss vdd-io nc vss vss nc vdd-c vss mad7 nc b_gpio0 b_gpio4 vss vdd nc b_sc_d/ vss nc b_sd7/ b_sd5 v1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 c_be0/ ad7 nc ad2 tck vdd-c vss-c a_gpio2 vdd mad4 mad0 b_gpio3 b_rstdir b_sdir9 b_sd11/ b_sd8/ b_ssel/ nc b_sdp0/ b_sd6/ w1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 ad6 vss ad4 vdd-io tdi sclk a_gpio0 a_gpio3 mad6 nc mad1 b_gpio2 b_seldir b_sdir11 b_sdir8 b_sd10/ b_si_o/ b_smso/ b_sack/ b-satn/ y1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 ad5 ad3 ad1 ad0 tms testin/ a_gpio1 a_gpio4 mad5 mad3 mad2 b_gpio1 vdd b_bsydir b_sdir10 b_difsen b_sd9/ b_sreq/ b_srst/ b_sbsy/
3-4 signal descriptions figure 3.3 lsi53c876 functional signal grouping clk rst ad[31:0] c_be/[3:0] pa r frame/ trdy/ irdy/ stop/ devsel/ idsel req/ gnt/ serr/ perr/ sclk a_sd[15:0]/ a_sdp[1:0]/ a_sc_d/ a_si_o/ a_smsg/ a_sreq/ a_sack/ a_sbsy/ a_satn/ a_srst/ a_ssel/ address system interface arbitration error scsi function a scsi bus interface rom/flash memory interface lsi53c876 pci bus interface scsi function b gpio mwe/ mce/ moe_testout mas0/ mas1/ mad[7:0] inta/ intb/ interrupt a_gpio0_fetch/ a_gpio1_master/ a_gpio2 a_gpio3 a_gpio4 a_sctrl/ scsi function a gpio b_gpio0_fetch/ b_gpio1_master/ b_gpio2 b_gpio3 b_gpio4 b_sd[15:0]/ b_sdp[1:0]/ b_sc_d/ b_si_o/ b_smsg/ b_sreq/ b_sack/ b_sbsy/ b_satn/ b_srst/ b_ssel/ a_sdir[15:0]/ a_sdirp0/1 a_bsydir a_seldir a_rstdir a_diffsens a_igs a_tgs testin/ tck tms tdi tdo scsi function b scsi bus interface scsi function a differential control test interface b_sctrl/ b_sdir[15:0]/ b_sdirp0/1 b_bsydir b_seldir b_rstdir b_diffsens b_igs b_tgs scsi function b differential control (256 bga only) and data control reporting
3-5 the lsi53c876 signals are divided into three primary interfaces: pci interface scsi interface rom/flash memory interface a slash (/) at the end of the signal name indicates that the active state occurs when the signal is at a low voltage. when the slash is absent, the signal is active at a high voltage. there are ?ve signal type de?nitions: i input, a standard input only signal. o output, a standard output driver (typically a totem pole output). i/o input and output (bidirectional). t/s 3-state, a bidirectional, 3-state input/output signal. s/t/s sustained 3-state, an active low 3-state signal owned and driven by one and only one agent at a time.
3-6 signal descriptions 3.1 pci interface signals the pci interface signals are organized into the following functional groups: system signals , address and data signals , interface control signals , arbitration signals , error reporting signals , pci interrupt signals , and gpio interface signals . 3.1.1 system signals table 3.1 describes the signals for the system signals group. table 3.1 system signals name pin no. type strength description clk 197, d7 i n/a clock provides timing for all transactions on the pci bus and is an input to every pci device. all other pci signals are sampled on the rising edge of clk, and other timing parameters are de?ned with respect to this edge. clock can optionally serve as the scsi core clock, but this may effect fast scsi transfer rates. rst/ 196, a5 i n/a reset forces the pci sequencer of each device to a known state. all t/s and s/t/s signals are forced to a high impedance state, and all internal logic is reset. the rst/ input is synchronized internally to the rising edge of clk. the clk input must be active while rst/ is active to properly reset the device.
pci interface signals 3-7 3.1.2 address and data signals table 3.2 describes the signals for the address and data signals group. table 3.2 address and data signals name pin no. type strength description ad[31:0] 202, 203, 205, 207, 208, 1, 3, 4, 8, 10, 11, 12, 14, 16, 17, 18, 36, 37, 38, 40, 42, 43, 44, 46, 49, 50, 52, 53, 54, 56, 58, 59 b4, a3, c4, b2, a2, b1, d2, c1, e1, f2, f1, g3, g1, h2, h1, j4, p1, p2, r1, r2, p4, r3, t2, t3, v2, w1, y1, w3, y2, v4, y3, y4 t/s 16 ma pci physical dword address and data are multiplexed on the same pci pins. during the ?rst clock of a transaction, ad[31:0] contain a physical byte address. during subsequent clocks, ad[31:0] contain data. a bus transaction consists of an address phase followed by one or more data phases. pci supports both read and write bursts. ad[7:0] de?ne the least signi?cant byte, and ad[31:24] de?ne the most signi?cant byte. c_be/[3:0] 5, 20, 34, 48 d1, j2, n2, v1 t/s 16 ma pci bus command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, c_be/[3:0] de?ne the bus command. during the data phase, c_be/[3:0] are used as byte enables. the byte enables determine which byte lanes carry meaningful data. c_be/[0] applies to byte 0, and c_be/[3] to byte 3. par 33, n1 t/s 16 ma pci parity is the even parity bit that protects the ad[31:0] and c_be/[3:0] lines. during address phase, both the address and command bits are covered. during data phase, both data and byte enables are covered.
3-8 signal descriptions 3.1.3 interface control signals table 3.3 describes the signals for the interface control signals group. table 3.3 interface control signals name pin no. type strength description frame/ 21, j1 s/t/s 16 ma pci cycle frame is driven by the current master to indicate the beginning and duration of an access. frame/ is asserted to indicate that a bus transaction is beginning. while frame/ is deasserted, either the transaction is in the ?nal data phase or the bus is idle. trdy/ 25, l1 s/t/s 16 ma pci target ready indicates the target agents (selected devices) ability to complete the current data phase of the transaction. trdy/ is used with irdy/. a data phase is completed on any clock when used with irdy/. a data phase is completed on any clock when both trdy/ and irdy/ are sampled asserted. during a read, trdy/ indicates that valid data is present on ad[31:0]. during a write, it indicates that the target is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. irdy/ 23, k3 s/t/s 16 ma pci initiator ready indicates the initiating agents (bus masters) ability to complete the current data phase of the transaction. irdy/ is used with trdy/. a data phase is completed on any clock when both irdy/ and trdy/ are sampled asserted. during a write, irdy/ indicates that valid data is present on ad[31:0]. during a read, it indicates that the master is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. stop/ 28, l4 s/t/s 16 ma pci stop indicates that the selected target is requesting the master to stop the current transaction. devsel/ 26, l2 s/t/s 16 ma pci device select indicates that the driving device has decoded its address as the target of the current access. as an input, it indicates to a master whether any device on the bus has been selected. idsel 7, e2 i n/a initialization device select is used as a chip select in place of the upper 24 address lines during con?guration read and write transactions.
pci interface signals 3-9 3.1.4 arbitration signals table 3.4 describes the signals for the arbitration signals group. 3.1.5 error reporting signals table 3.5 describes the signals for the error reporting signals group. table 3.4 arbitration signals name pin no. type strength description req/ 200, a4 o 16 ma pci request indicates to the system arbiter that this agent desires use of the pci bus. both scsi functions share the gnt/ signal. gnt/ 199, b5 i n/a grant indicates to the agent that access to the pci bus has been granted. both scsi functions share the gnt/ signal. table 3.5 error reporting signals name pin no. type strength description perr/ 30, m2 s/t/s 16 ma pci parity error may be pulsed active by an agent that detects a data parity error. perr/ can be used by any agent to signal data corruption. however, on detection of a perr/ pulse, the central resource may generate a nonmaskable interrupt to the host cpu, which often implies the system is unable to continue operation once error processing is complete. serr/ 32, m4 o 16 ma pci system error is an open drain output is used to report address parity errors.
3-10 signal descriptions 3.1.6 pci interrupt signals table 3.6 describes the signals pci interrupt signals group. table 3.6 pci interrupt signals name pin no. type strength description inta/ 195, b6 o 16 ma pci interrupt function a. this signal, when asserted low, indicates an interrupting condition in scsi function a and that service is required from the host cpu. the output drive of this pin is open drain with an internal weak pull-up. if the scsi function b interrupt is rerouted at power-up using the inta/ enable sense resistor (pull-down on mad4), then this signal indicates an interrupt in either scsi function a or scsi function b. intb/ 194, c7 o 16 ma pci interrupt function b. this signal, when asserted low, indicates an interrupting condition in scsi function b and that service is required from the host cpu. the output drive of this pin is open drain with an internal weak pull-up. this interrupt can be rerouted at power-up using the inta/ enable sense resistor (pull-down on mad4). this causes the lsi53c876 to program the scsi function b pci register interrupt pin (3d) to 0x01.
pci interface signals 3-11 3.1.7 gpio interface signals table 3.7 describes the signals for the scsi gpio function a signals group. table 3.7 scsi gpio function a signals name pin no. type strength description a_gpio0_ fetch/ 68, w7 i/o 16 ma scsi function a general purpose i/o pin 0. optionally, when driven low, indicates that the next bus request is for an opcode fetch. this pin is programmable at power-up through the mad[7:6] pins to serve as either the data or clock signal for the serial eeprom interface. a_gpio1_ master/ 69, y7 i/o 16 ma scsi function a general purpose i/o pin 1. optionally, when driven low, indicates that the lsi53c876 is bus master. this pin is programmable at power-up through the mad[7:6] pins to serve as either the data or clock signal for the serial eeprom interface. a_gpio2 70, v8 i/o 16 ma scsi function a general purpose i/o pin 2. this pin is a general purpose i/o pin that powers up as an input. a_gpio3 71, w8 i/o 16 ma scsi function a general purpose i/o pin 3. a_gpio3 powers up as an input. currently our drivers use a_gpio3 as a means to detect diffsense. a_gpio4 73, y8 i/o 16 ma scsi function a general purpose i/o pin 4. a_gpio4 powers up as an output. it can be used as the enable line for vpp, the 12 v power supply to the external flash memory interface.
3-12 signal descriptions table 3.8 describes the signals for the scsi gpio function b signals group. table 3.8 scsi gpio function b signals name pin no. type strength description b_gpio0_ fetch/ 84, u11 i/o 16 ma scsi function b general purpose i/o pin 0. optionally, when driven low, indicates that the next bus request is for an opcode fetch. this pin is programmable at power-up through the mad[7:6] pins to serve as either the data or clock signal for the serial eeprom interface. b_gpio1_ master/ 86, y12 i/o 16 ma scsi function b general purpose i/o pin 1. optionally, when driven low, indicates that the lsi53c876 is bus master. this pin is programmable at power-up through the mad[7:6] pins to serve as either the data or clock signal for the serial eeprom interface. b_gpio2 87, w12 i/o 16 ma scsi function b general purpose i/o pin 2. b _ gpio2 powers up as an input. b_gpio3 88, v12 i/o 16 ma scsi function b general purpose i/o pin 3. b_gpio3 powers up as an input. currently our drivers use b_gpio3 as a means to detect diffsense. b_gpio4 89, u12 i/o 16 ma scsi function b general purpose i/o pin 4. b_gpio4 powers up as an output. it can be used as the enable line for vpp, the 12 v power supply to the external flash memory interface.
scsi bus interface signals 3-13 3.2 scsi bus interface signals the scsi bus interface signals section contains tables describing the signals for the following signal groups: scsi bus interface signal and scsi bus interface . 3.2.1 scsi bus interface signal table 3.9 describes the scsi bus interface signal. table 3.9 scsi bus interface signal name pin no. type strength description sclk 65, w6 i n/a scsi clock is used to derive all scsi-related timings. the speed of this clock is determined by the application requirements. in some applications, sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, tie the sclk pin low. for ultra scsi operations, the clock supplied to sclk must be at 40 mhz. the frequency is doubled to create the 80 mhz clock required by both scsi functions.
3-14 signal descriptions 3.2.2 scsi bus interface table 3.10 describes the signals for the scsi function a signals group. table 3.10 scsi function a interface signals name pin no. type strength description a_sd[15:0]/, a_sdp[1:0]/ 167, 169, 170, 171, 139, 140, 141, 143, 156, 157, 159, 160, 161, 162, 164, 165, 166, 155, c15, d14, b15, a15, g18, f19, e20, g17, a20, a19, b18, b17, a18, a17, c16, b16, a16, b19 i/o 48 ma scsi scsi function a data includes the following data lines and parity signals: a_sd/[15:0] (16-bit scsi data bus), and a_sdp/[1:0] (scsi data parity bits). a_sctrl/ 146, 144, 149, 145, 151, 152, 154, 150, 148, d20, f18, d19, e19, e17, c19, b20, c20, e18 i/o 48 ma scsi scsi function a control includes the following signals: a_sc_d/ scsi phase line, command/data a_si_o/ scsi phase line, input/output a_smsg/ scsi phase line, message a_sreq/ data handshake line from target device a_sack/ data handshake signal from initiator device a_sbsy/ scsi bus arbitration signal, busy a_satn/ scsi attention, the initiator is requesting a message out phase a_srst/ scsi bus reset a_ssel/ scsi bus arbitration signal, select device
scsi bus interface signals 3-15 table 3.11 describes the signals for the scsi function b signals group. table 3.11 scsi function b interface signals name pin no. type strength description b_sd/[15:0], b_sdp/[1:0] 119, 121, 122, 123, 91, 92, 93, 95, 108, 109, 111, 112, 113, 114, 116, 117, 118, 107, r20, p18, p19, p20, v15, w16, y17, v16, u19, v20, u20, t18, t19, t20, r18, p17, r19, v19 i/o 48 ma scsi scsi function b data includes the following data lines and parity signals: b_sd/[15:0] (16-bit scsi data bus), and b_sdp/[1:0] (scsi data parity bits). b_sctrl/ 98, 96, 101, 97, 103, 104, 106, 102, 100, u16, w17, w18, y18, w19, y20, w20, y19, v17 i/o 48 ma scsi scsi function b control includes the following signals: b_sc_d/ scsi phase line, command/data b_si_o/ scsi phase line, input/output b_smsg/ scsi phase line, message b_sreq/ data handshake line from target device b_sack/ data handshake signal from initiator device b_sbsy/ scsi bus arbitration signal, busy b_satn/ scsi attention, the initiator is requesting a message out phase b_srst/ scsi bus reset b_ssel/ scsi bus arbitration signal, select device
3-16 signal descriptions table 3.12 describes the signals for the scsi function a differential control signals group. table 3.12 scsi function a differential control signals name pin no. type strength description a_sdir[15:0]/ 183, 184, 185, 187, 134, 135, 136, 137, 174, 175, 176, 177, 179, 180, 181, 182, b11, c11, a11, b10, h19, h18, g20, g19, a14, c13, b13, a13, d12, c12, b12, a12 o 4 ma driver direction control for scsi function a data lines. a_sdirp0/1 173, b14 o 4 ma driver direction control for scsi function a parity line. a_bsydir 132, h20 o 4 ma driver enable control for scsi function a sbsy/ signal. a_seldir 128, j20 o 4 ma driver enable control for scsi function a ssel/ signal. a_rstdir 130, j18 o 4 ma driver enable control for scsi function a srst/ signal. a_diffsens 125, k19 i n/a scsi function a differential sense. this pin detects the presence of an se device on a differential system. when external differential transceivers are used and a zero is detected on this pin, all scsi function a chip outputs are 3-stated to avoid damage to the transceivers. tie this pin high during se operation. the normal value of this pin is 1. a_igs 127, k17 o 4 ma scsi function a direction control for initiator driver group. a_tgs 126, k18 o 4 ma scsi function a direction control for target driver group.
scsi bus interface signals 3-17 table 3.13 describes the signals for the scsi function b differential control signals group. table 3.13 scsi function b differential control signals name pin no. type strength description b_sdir[15:0]/ c10, d10, a9, c9, w14, y15, v14, w15, n20, m17, m18, m19, m20, l19, l18, l20 o 4 ma driver direction control for scsi function b data lines. b_sdirp0/1 n19 o 4 ma driver direction control for scsi function b parity line. b_bsydir y14 o 4 ma driver enable control for scsi function b sbsy/ signal. b_seldir w13 o 4 ma driver enable control for scsi function b ssel/ signal. b_rstdir v13 o 4 ma driver enable control for scsi function b srst/ signal. b_diffsens y16 i n/a scsi function b differential sense. this pin detects the presence of an se device on a differential system. when external differential transceivers are used and a zero is detected on this pin, all scsi function b chip outputs are 3-stated to avoid damage to the transceivers. tie this pin high during se operation. the normal value of this pin is 1. b_igs a8 o 4 ma scsi function b direction control for initiator driver group. b_tgs d9 o 4 ma scsi function b direction control for target driver group.
3-18 signal descriptions 3.3 rom/flash interface signals table 3.14 describes the signals for the rom/flash interface signals group. table 3.14 rom/flash interface signals name pin no. type strength description mas0/ 190, c8 o 4 ma memory address strobe 0 . this pin is used to latch in the least signi?cant address byte of an external eprom or flash memory. since the lsi53c876e moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?ip-?ops which are used to assemble up to a 20-bit address for the external memory. if an external memory requires more than 16 bits of addressing as speci?ed by the pull-down resistors at power-up and bit 0 in the expansion rom base address register, see the external memory interface diagram for proper usage. mas1/ 189, b8 o 4 ma memory address strobe 1. this pin is used to latch in the address byte corresponding to address bits [15:8] of an external eprom or flash memory. since the lsi53c876e moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?ip-?ops which assemble up to a 20-bit address for the external memory. if an external memory requires more than 16 bits of addressing as speci?ed by the pull-down resistors at power-up and bit 0 in the expansion rom base address register, see the external memory interface diagram for proper usage. mad[7:0] 74, 76, 77, 79, 80, 81, 82, 83, u9, w9, y9, v10, y10, y11, w11, v11 i/o 4 ma memory address/data bus. this bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a 20-bit address for an external eprom or flash memory. this bus will put out the least signi?cant byte ?rst and ?nishes with the most signi?cant bits. it is also used to write data to a flash memory or read data into the chip from external eprom/flash memory. all mad pins have internal pull-up resistors.
test interface signals 3-19 3.4 test interface signals table 3.15 describes the signals for the test interface signals group. mwe/ 191, a7 o 4 ma memory write enable. this pin is used as a write enable signal to an external flash memory. moe/_testout 192, b7 o 4 ma memory output enable. this pin is used as an output enable signal to an external eprom or flash memory during read operations. it is also used to test the connectivity of the lsi53c876e signals in the and-tree test mode. this pin is only driven as the test out function when the testin/ pin is driven low. mce/ 193, a6 o 4 ma memory chip enable. this pin is used as a chip enable signal to an external eprom or flash memory device. table 3.14 rom/flash interface signals (cont.) name pin no. type strength description table 3.15 test interface signals name pin no. type strength description testin/ 66, y6 i n/a test in. when this pin is driven low, the lsi53c876e connects all inputs and outputs to an and-tree. the scsi control signals and data lines are not connected to the tree. the output of the and-tree is connected to the test out pin (moe/_testout). when the testin/ pin is driven low internal pull-ups are enabled on all input, output, and bidirectional pins; all output and bidirectional pins signals are 3-stated; and the moe/_testout pin is enabled. connectivity is tested by driving one of the lsi53c876e pins low. the moe/_testout should respond by also driving low. tck 60, v5 i n/a test clock. this pin provides the clock for the jtag test logic. it has a static pull-up. tms 62, y5 i n/a test mode select . the signal received at tms is decoded by the tap controller to control jtag test operations. it has a static pull-up.
3-20 signal descriptions 3.5 power and ground signals table 3.16 describes the signals for the power and ground signals group. tdi 61, w5 i n/a test data in. serial test instructions are received by the jtag test logic at this pin. it has a static pull-up. tdo 63, v6 o n/a test data out. this pin is the serial output for test instructions and data from the jtag test logic. table 3.15 test interface signals (cont.) table 3.16 power and ground signals name pin no. type strength description v dd -io 6, 13, 22, 31, 39, 47, 55, 206, b3, e3, g2, k2, m3, p3, u2, w4 p n/a power for pci bus drivers/receivers. v ss 2, 9, 15, 19, 24, 29, 35, 41, 45, 51, 57, 204, a1, c2, d4, d5, d8, d13, d17, f3, h3, h4, h17, j3, k1, m1, n3, n4, n17, t1, u1, u4, u5, u8, u13, u17, w2 g n/a ground for pci bus drivers/receivers. v dd -s 90, 124, 138, 172, a10, b9,c14, f20, k20, n18, u14, v9, y13 p n/a power for scsi bus drivers/receivers. v ss -s 94, 99, 105, 110, 115, 120, 142, 147, 153, 158, 163, 168 g n/a ground for scsi bus drivers/receivers. v dd -c 64, 131, 201, c5, j17, u7 p n/a power for core logic. v ss -c 67, 129, 198, c6, j19, v7 g n/a ground for core logic. v dd 75, 186 p n/a power for other i/o. v ss 72, 85, 133, 178, 188 g n/a ground for other i/o.
mad bus programming 3-21 3.5.1 isolated power supplies the i/o driver pad rows and digital core have isolated power supplies as delineated by the "i/o" and "core" extensions on their respective v ss and v dd names. these power and ground pins should be connected directly to the primary power and ground planes of the circuit board. bypass capacitors of 0.01 m f should be applied between adjacent v ss and v dd pairs wherever possible. do not connect bypass capacitors between v ss and v dd pairs that cross power and ground bus boundaries. 3.6 mad bus programming the mad[7:0] pins, in addition to serving as the address/data bus for the local memory interface, also are used to program power-up options for the chip. a particular option is programmed by connecting a 4.7 k w resistor between the appropriate mad(x) pin and v ss . the pull-down resistors require that hc or hct external components are used for the memory interface. mad[7] C serial eeprom programmable option. please refer to section 2.4, serial eeprom interface, in chapter 2, functional description, for details. mad[6] C serial eeprom programmable option. please refer to section 2.4, serial eeprom interface, in chapter 2, functional description, for details. mad[5] C scripts ram disable. mad[4] C inta/ routing enable. placing a pull-down resistor on this pin causes scsi function b interrupt requests to appear on the inta/ pin, along with scsi function a interrupt requests, instead of on intb/. placing a pull-down resistor on this pin also causes the scsi function b interrupt pin register (0x3d) in pci con?guration space to be programmed to 0x01 instead of 0x02. mad[3:1] C used to set the size of the external expansion rom device attached. encoding for these pins are listed in the following table (0 indicates a pull-down resistor is attached, 1 indicates no pull-down resistor attached).
3-22 signal descriptions mad[0] C the slow rom pin. when pulled down, it enables two extra cycles of data access time to allow use of slower memory devices. note: all mad pins have internal pull-up resistors. table 3.17 decode of mad pins mad[3:1] available memory space 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present
lsi53c876/876e pci to dual channel scsi multifunction controller 4-1 chapter 4 registers this chapter describes all lsi53c876 registers and is divided into the following sections: section 4.1, pci con?guration registers section 4.2, scsi registers 4.1 pci con?guration registers the pci con?guration registers are accessed by performing a con?guration read/write to the device with its idsel pin asserted and the appropriate value in ad[10:8] during the address phase of the transaction. scsi function a is identi?ed by a binary value of 000b, and scsi function b by a value of 001b. each scsi channel contains the same register set with identical default values, except the interrupt pin register. table 4.1 shows the pci con?guration registers implemented by the lsi53c876. all pci-compliant devices, such as the lsi53c876, must support the vendor id , device id , command , and status registers. support of other pci-compliant registers is optional. in the lsi53c876, registers that are not supported are not writable and return all zeros when read. only those registers and bits that are currently supported by the lsi53c876 are described in this chapter.
4-2 registers table 4.1 pci to scsi con?guration register map 31 16 15 0 device id vendor id 0x00 status command 0x04 class code revision id 0x08 not supported header type latency timer cache line size 0x0c base address register zero (i/o) scsi operating registers 0x10 base address register one (memory) bits [31:0] scsi operating registers 0x14 base address register two (memory) 0x18 not supported 0x1c not supported 0x20 not supported 0x24 reserved 0x28 subsystem id subsystem vendor id 0x2c expansion rom base address 0x30 reserved capabilities pointer 0x34 reserved 0x38 max_lat min_gnt interrupt pin 1 1. each scsi function contains the same register set with identical default values. one exception is the interrupt pin register. note: shaded areas are reserved or represent the lsi53c876e capabilities. interrupt line 0x3c power management capabilities next item pointer capability id 0x40 data pmcsr bse power management control/status 0x44
pci con?guration registers 4-3 register: 0x00 vendor id read only vid vendor id [15:0] this ?eld identi?es the manufacturer of the device. the vendor id is 0x1000. register: 0x02 device id read only did device id [15:0] this ?eld identi?es the particular device. the lsi53c876 device id is 0x000f. register: 0x04 command read/write the command register provides coarse control over a devices ability to generate and respond to pci cycles. when a zero is written to this register, the lsi53c876 is logically disconnected from the pci bus for all accesses except con?guration accesses. 15 0 vid 1111000000000000 15 0 did 0000000000000000 15 9 8 7 6 5 4 3 2 1 0 rse r eper r wie r ebm ems eis 0 0 0 0 0 0 00 00 00 00 00
4-4 registers r reserved [15:9] se serr/ enable 8 this bit enables the serr/ driver. serr/ is disabled when this bit is cleared. the default value of this bit is zero. this bit and bit 6 must be set to report address parity errors. in the lsi53c876e, this bit is suppressed in power state d2. r reserved 7 eper enable parity error response 6 this bit allows a scsi function of the lsi53c876e to detect parity errors on the pci bus and report these errors to the system. only data parity checking is enabled and disabled with this bit. the lsi53c876 always generates parity for the pci bus. in the lsi53c876e, this bit is suppressed in power state d2. r reserved 5 wie write and invalidate enable 4 this bit allows a scsi function of the lsi53c876 to generate write and invalidate commands on the pci bus. the wrie bit in the chip test three (ctest3) register must also be set for the scsi function to generate write and invalidate commands. r reserved 3 ebm enable bus mastering 2 this bit controls the ability of a scsi function to act as a master on the pci bus. a value of zero disables this device from generating pci bus master accesses. a value of one allows the scsi function to behave as a bus master. the scsi function must be a bus master in order to fetch scripts instructions and transfer data. in the lsi53c876e, this bit is suppressed in power state d2. ems enable memory space 1 this bit controls the ability of a scsi function to respond to memory space accesses. a value of zero disables the device response. a value of one allows a scsi function of the lsi53c876 to respond to memory space accesses at the address range speci?ed by the base address reg- ister one (memory) and base address register two
pci con?guration registers 4-5 (memory) registers in the scsi functions pci con?guration space. in the lsi53c876e, this bit is suppressed in power state d2. eis enable i/o space 0 this bit controls a scsi functions response to i/o space accesses. a value of zero disables the device response. a value of one allows the lsi53c876 to respond to i/o space accesses at the address range speci?ed by the base address register zero (i/o) register in the scsi functions pci con?guration space. in the lsi53c876e, this bit is suppressed in power state d2. register: 0x06 status read/write reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is cleared whenever the register is written, and the data in the corresponding bit location is a one. for instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. dpe detected parity error (from slave) 15 this bit is set by the a scsi function of the lsi53c876 whenever it detects a data parity error, even if data parity error handling is disabled. sse signaled system error 14 this bit is set whenever the device asserts the serr/ signal. rma received master abort (from master) 13 a master device should set this bit whenever its transaction (except for special cycle) is terminated with master abort. rta received target abort (from master) 12 a master device should set this bit whenever its transaction is terminated by target abort. 15 14 13 12 11 10 9 8 7 5 4 3 0 dpe sse rma rta r dt[1:0] dpr rnc r 0000 0000 0 0 01 0 0 0 0
4-6 registers r reserved 11 dt[1:0] devsel/ timing [10:9] these bits encode the timing of devsel/. these are encoded as: these bits are read only and should indicate the slowest time that a device asserts devsel/ for any bus command except con?guration read and con?guration write. in the scsi functions of the lsi53c876, 0b01 is supported. dpr data parity reported 8 this bit is set when the following conditions are met: the bus agent asserted perr/ itself or observed perr/ asserted. the agent setting this bit acted as the bus master for the operation in which the error occurred. the parity error response bit in the command register is set. r reserved [7:5] nc new capabilities 4 this bit is set to indicate a list of extended capabilities such as pci power management. this bit is read only. r reserved [3:0] 0b00 fast 0b01 medium 0b10 slow 0b11 reserved
pci con?guration registers 4-7 register: 0x08 revision id read only rid revision id [7:0] this ?eld speci?es device and revision identi?ers. the value of this register is 0x00110111 or 0x37. register: 0x09 class code read only cc class code [23:0] this register is used to identify the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?es a speci?c register level programming interface. the value of this register is 0x010000, which identi?es a scsi controller. register: 0x0c cache line size read/write cls cache line size [7:0] this register speci?es the system cache line size in units of 32-bit words. the value in this register is used by the device to determine whether to use write and invalidate or write commands for performing write cycles, and whether to use read, read line, or read multiple 7 0 rid 00110111 23 0 cc 000011110000000000000000 7 0 cls 00000000
4-8 registers commands for performing read cycles as a bus master. devices participating in the caching protocol use this ?eld to know when to retry burst accesses at cache line boundaries. these devices can ignore the pci cache support lines (sdone and sb0/) when this register is cleared to 0. if this register is programmed to a number which is not a power of 2, the device will not use pci performance commands to perform data transfers. register: 0x0d latency timer read/write lt latency timer [7:0] the latency timer register speci?es, in units of pci bus clocks, the value of the latency timer for this pci bus master. the scsi functions of the lsi53c876 support this timer. all eight bits are writable, allowing latency values of 0C255 pci clocks. use the following equation to calculate an optimum latency value for the scsi functions of the lsi53c876. latency = 2 + (burst size x (typical wait states + 1)) values greater than optimum are also acceptable. register: 0x0e header type read only ht header type [7:0] this register identi?es the layout of bytes 0x10 through 0x3f in con?guration space and also whether or not the device contains multiple functions. since the lsi53c876 is a multifunction controller the value of this register is 0x80. 7 0 lt 00000000 7 0 ht 00000000
pci con?guration registers 4-9 register: 0x0f bist read only this register is used for control and status of bist. since the lsi53c876 does not support bist, this register is read only and always returns a value of 0x00. bist bist capable 7 start start bist 6 r reserved [5:4] cc completion code [3:0] register: 0x10 base address register zero (i/o) read/write bar0 base address register zero - i/o [31:0] this 32-bit register has bit zero hardwired to one. bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into i/o space. for detailed information on the operation of this register, refer to the pci speci?cation. this base address register zero (i/o) register maps scsi operating registers into i/o space. 7 6543 0 bist capable start bist r completion code 00 0 00000 31 0 bar0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1
4-10 registers register: 0x14 base address register one (memory) read/write bar1 base address register one [31:0] this register has bit zero hardwired to zero. for detailed information on the operation of this register, refer to the pci speci?cation. this base address register one (memory) register maps scsi operating registers into memory space. register: 0x18 base address register two (memory) read/write bar2 base address register two [31:0] this register has bit zero hardwired to zero. the other bits are used to map the 4 kbyte scripts ram into memory space. this register is enabled only if the internal scripts ram is enabled. the internal scripts ram is disabled by connecting a 4.7 k w resistor between mad5 and ground, which is sensed immediately after a chip reset. scripts ram is also disabled by setting the enable memory space bit to zero in the scsi pci con?guration command register, bit 1. if mad5 is left unconnected, an internal pull-up enables the scripts ram and this base address register. if enabled, as with all base address registers, initialize this base address register to a value that does not con?ict with other memory resources. otherwise, memory con?icts may occur. for detailed information on the operation of this register, refer to the pci speci?cation. 31 0 bar1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 31 0 bar2 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0
pci con?guration registers 4-11 register: 0x2c subsystem vendor id read only svid subsystem vendor id [15:0] this register uniquely identi?es the vendor manufacturing the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from another vendors cards, even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). this register loads automatically at power-up from an external serial eeprom if in operating mode a and the load from eeprom is successful. the 16-bit value that should be stored in the external serial eeprom for this register is the vendors pci vendor id and must be obtained from the pci special interest group (sig). if in operating mode d, this register is loaded with a default value of 0x1000. if an error occurs during a load from eeprom or if the operating mode is b, this register defaults to a value of 0x0000. see section 2.4, serial eeprom interface, in chapter 2, functional description, for information about the values to load in this register. 15 0 svid if eeprom not enabled mode a 0000000000000000 if eeprom note enabled mode d 1111000000000000 eeprom value if eeprom enabled xxxxxxxxxxxxxxxx
4-12 registers register: 0x2e subsystem id read only sid subsystem id [15:0] this register uniquely identi?es the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). this register loads automatically at power-up from an external serial eeprom if in operating mode a and the load from eeprom is successful. the 16-bit value that should be stored in the external serial eeprom for this register is vendor speci?c. if in operating mode d, this register is loaded with a default value of 0x1000. if an error occurs during a load from eeprom or if the operating mode is b, this register defaults to a value of 0x0000. see section 2.4, serial eeprom interface, in chapter 2, functional description, for information about the values to load in this register. 15 0 sid if eeprom not enabled mode a 0000000000000000 if eeprom note enabled mode d 1111000000000000 eeprom value if eeprom enabled xxxxxxxxxxxxxxxx
pci con?guration registers 4-13 register: 0x30 expansion rom base address read/write erba expansion rom base address [31:0] this four-byte register handles the base address and size information for the expansion rom. it functions exactly like the base address registers, except that the encoding of the bits is different. the upper 21 bits correspond to the upper 21 bits of the expansion rom base address. the expansion rom enable bit, bit 0, is the only bit de?ned in this register. this bit controls whether or not the device accepts accesses to its expansion rom. when the bit is set, address decoding is enabled, and a device is used with or without an expansion rom depending on the system con?guration. to access the external memory interface, also set the memory space bit in the command register. the host system detects the size of the external memory by ?rst writing the expansion rom base address register with all ones and then reading back the register. the scsi functions of the lsi53c876 respond with zeros in all dont care locations. the ones in the remaining bits represent the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register, when written with ones and read back, returns ones in the upper 17 bits. the rom is accessed through the mad bus which is common to both scsi functions in this device. 31 0 erba 00000000000000000000000000000000
4-14 registers register: 0x34 capabilities pointer read only cp capabilities pointer [7:0] this register provides an offset into the functions pci con?guration space for the location of the ?rst item in the capabilities linked list. only the lsi53c876e sets this register to 0x40. register: 0x3c interrupt line read/write il interrupt line [7:0] this register can communicate interrupt line routing information. post software writes the routing information into this register as it con?gures the system. the value in this register tells which input of the system interrupt controller(s) the devices interrupt pin is connected to. values in this register are speci?ed by system architecture. 7 0 cp 01000000 7 0 il 00000000
pci con?guration registers 4-15 register: 0x3d interrupt pin read only ip interrupt pin [7:0] this register is unique to each scsi function. it tells which interrupt pin the device uses. its value is set to 0x01 for the function a inta/ signal, and 0x02 for the function b intb/ signal at power-up. the function b intb/ value is set to 0x01 if mad[4] is pulled low. register: 0x3e min_gnt read only mg min_gnt [7:0] this register speci?es the desired settings for latency timer values. min_gnt speci?es how long a burst period the device needs. the value speci?ed in these registers is in units of 0.25 microseconds. the lsi53c876 scsi function sets this register to 0x11. 7 0 ip scsi function a 00000001 scsi function b if mad[4] pulled low 00000001 scsi function b if mad[4] not pulled low 00000010 7 0 mg 00010001
4-16 registers register: 0x3f max_lat read only ml max_lat [7:0] this register indicates the desired settings for latency timer values. max_lat speci?es how often the device needs to gain access to the pci bus. the value speci?ed in these registers is in units of 0.25 microseconds. the lsi53c876 scsi function sets this register to 0x40. register: 0x40 capability id read only cid cap_id [7:0] this register indicates the type of the current data structure. this register applies to the lsi53c876e only, which sets this register to a value of 0x01, indicating the power management data structure. 7 0 ml 01000000 7 0 cid 00000001
pci con?guration registers 4-17 register: 0x41 next item pointer read only nip next_item_ptr [7:0] this register describes the location of the next item in the functions capability list. this register applies only to the lsi53c876e, which sets this register to a value of 0x00, indicating that power management is the last capability in the linked list of extended capabilities. register: 0x42 power management capabilities read only this register applies to the lsi53c876e only and indicates the power management capabilities. pmes[4:0] pme support [15:11] this ?eld is always set to 00000b because the lsi53c876e does not provide a pme signal. d2s d2 support 10 the lsi53c876e sets this bit to indicate that it supports the d2 power management state. d1s d1 support 9 the lsi53c876e sets this bit to indicate that it supports the d1 power management state. r reserved [8:6] dsi device speci?c initialization 5 this bit is set to 0 to indicate that the lsi53c876e requires no special initiation before the generic class device driver is able to use it. 7 0 nip 00000000 15 11 10 9 8 6 5 4 3 2 0 pmes[4:0] d2s d1s r dsi aps pmec ver[2:0] 0 000 0 1 1 0 0 000 0 111
4-18 registers aps auxiliary power source 4 because the lsi53c876e does not provide a pme signal, this bit always returns a 0, indicating that no auxiliary power source is required to support the pme signal in the d3cold power management state. pmec pme clock 3 this ?eld is always set to 00000b because the lsi53c876e does not provide a pme signal. ver version [2:0] this ?eld is set to 001b to indicate that the lsi53c876e complies with revision 1.0 of the pci power management interface speci?cation. register: 0x44 power management control/status read/write this register applies to the lsi53c876e only and indicates the power management control and status descriptions. pst pme status 15 the lsi53c876e always returns a zero for this bit, indicating that pme signal generation is not supported from d3cold. dscl data scale [14:13] the lsi53c876e does not support the data register. therefore, this ?eld is always set to 00b. dslt data select [12:9] the lsi53c876e does not support the data register. therefore, this ?eld is always set to 0000b. pen pme enable 8 the lsi53c876e always returns a zero for this bit to indicate that pme assertion is disabled. 15 14 13 12 9 8 7 2 1 0 pst dscl dslt pen r pws 00000000 0 0 0 0 0 000
pci con?guration registers 4-19 r reserved [7:2] pws power state [1:0] this two bit ?eld determines the current power state for the function and is used to set the function to a new power state. the de?nition of the ?eld values are: see section 2.5, power management, in chapter 2, functional description, of this document for descriptions of the power management states. register: 0x46 pmcsr bse read only bse bridge support extensions [7:0] this register applies only to the lsi53c876e and can support pci bridge speci?c functionality if required. the default value always returns 0x00. 0b00 d0 0b01 reserved 0b10 reserved 0b11 d3 hot 7 0 bse 00000000
4-20 registers register: 0x47 data read only data data [7:0] this register applies only to the lsi53c876e and provides an optional mechanism for the function to report state-dependent operating data. the lsi53c876e returns 0x00 as the default value. 4.2 scsi registers this section contains descriptions of all lsi53c876 scsi registers. table 4.2 , the register map, lists registers by operating and con?guration addresses. the terms set and assert refer to bits that are programmed to a binary one. similarly, the terms deassert, clear, and reset refer to bits that are programmed to a binary zero. write any bits marked as reserved to zero; mask all information read from them. reserved bit functions may change at any time. unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by setting the bit. the bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset. note: the only register that the host cpu can access while the lsi53c876 is executing scripts is the interrupt status (istat) register. attempts to access other registers interferes with the operation of the chip. however, all operating registers are accessible with scripts. all read data is synchronized and stable when presented to the pci bus. 7 0 data 00000000
scsi registers 4-21 table 4.2 lsi53c876 scsi register address map 31 16 15 0 scntl3 scntl2 scntl1 scntl0 0x00 gpreg sdid sxfer scid 0x04 sbcl ssid socl sfbr 0x08 sstat2 sstat1 sstat0 dstat 0x0c dsa 0x10 reserved istat 0x14 ctest3 ctest2 ctest1 ctest0 0x18 temp 0x1c ctest6 ctest5 ctest4 dfifo 0x20 dcmd dbc 0x24 dnad 0x28 dsp 0x2c dsps 0x30 scratcha 0x34 dcntl sbr dien dmode 0x38 adder 0x3c sist1 sist0 sien1 sien0 0x40 gpcntl macntl swide slpar 0x44 respid1 respid0 stime1 stime0 0x48 stest3 stest2 stest1 stest0 0x4c reserved sidl 0x50 reserved sodl 0x54 reserved sbdl 0x58 scratch b 0x5c scratch c 0x60 scratch d 0x64 scratch e 0x68 scratch f 0x6c scratch g 0x70 scratch h 0x74 scratch i 0x78 scratch j 0x7c
4-22 registers register: 0x00 scsi control zero (scntl0) read/write arb[1:0] arbitration mode bits 1 and 0 [7:6] simple arbitration 1. the lsi53c876 waits for a bus free condition to occur. 2. it asserts sbsy/ and its scsi id (contained in the scsi chip id (scid) register) onto the scsi bus. if the ssel/ signal is asserted by another scsi device, the lsi53c876 deasserts sbsy/, deasserts its id, and sets the lost arbitration bit (bit 3) in the scsi status zero (sstat0) register. 3. after an arbitration delay, the cpu should read the scsi bus data lines (sbdl) register to check if a higher priority scsi id is present. if no higher priority id bit is set, and the lost arbitration bit is not set, the lsi53c876 wins arbitration. 4. once the lsi53c876 wins arbitration, ssel/ must be asserted using the scsi output control latch (socl) for a bus clear plus a bus settle delay (1.2 m s) before a low level selection is performed. full arbitration, selection/reselection 1. the lsi53c876 waits for a bus free condition. 76543210 arb[1:0] start watn epc r aap trg 11000 x00 arb1 arb0 arbitration mode 0 0 simple arbitration 0 1 reserved 1 0 reserved 1 1 full arbitration, selection/reselection
scsi registers 4-23 2. it asserts sbsy/ and its scsi id (the highest priority id stored in the scsi chip id (scid) register) onto the scsi bus. 3. if the ssel/ signal is asserted by another scsi device or if the lsi53c876 detects a higher priority id, the lsi53c876 deasserts bsy, deasserts its id, and waits until the next bus free state to try arbitration again. 4. the lsi53c876 repeats arbitration until it wins control of the scsi bus. when it wins, the won arbitration bit is set in the scsi status zero (sstat0) register, bit 2. 5. the lsi53c876 performs selection by asserting the following onto the scsi bus: ssel/, the targets id (stored in the scsi destination id (sdid) register), and the lsi53c876 id (stored in the scsi chip id (scid) register). 6. after a selection is complete, the function complete bit is set in the scsi interrupt status zero (sist0) register, bit 6. 7. if a selection time-out occurs, the selection time-out bit is set in the scsi interrupt status one (sist1) register, bit 2. start start sequence 5 when this bit is set, the lsi53c876 starts the arbitration sequence indicated by the arbitration mode bits. the start sequence bit is accessed directly in low level mode; during scsi scripts operations, this bit is controlled by the scripts processor. do not start an arbitration sequence if the connected (con) bit in the scsi control one (scntl1) register, bit 4, indicates that the lsi53c876 is already connected to the scsi bus. this bit is automatically cleared when the arbitration sequence is complete. if a sequence is aborted, check bit 4 in the scntl1 register to verify that the lsi53c876 is not connected to the scsi bus. watn select with satn/ on a start sequence 4 when this bit is set and the lsi53c876 scsi function is in initiator mode, the satn/ signal is asserted during
4-24 registers selection of a scsi target device. the satn/ signal informs the target that the lsi53c876 scsi function has a message to send. if a selection time-out occurs while attempting to select a target device, satn/ is deasserted at the same time ssel/ is deasserted. when this bit is cleared, the satn/ signal is not asserted during selection. when executing scsi scripts, this bit is controlled by the scripts processor, but manual setting is possible in low level mode. epc enable parity checking 3 when this bit is set, the scsi data bus is checked for odd parity when data is received from the scsi bus in either the initiator or target mode. if a parity error is detected, bit 0 of the scsi interrupt status zero (sist0) register is set and an interrupt may be generated. if the lsi53c876 scsi function is operating in initiator mode and a parity error is detected, assertion of satn/ is optional, but the transfer continues until the target changes phase. when this bit is cleared, parity errors are not reported. r reserved 2 aap assert satn/ on parity error 1 when this bit is set, the lsi53c876 scsi function automatically asserts the satn/ signal upon detection of a parity error. satn/ is only asserted in initiator mode. the satn/ signal is asserted before deasserting sack/ during the byte transfer with the parity error. also set the enable parity checking bit for the lsi53c876 scsi function to assert satn/ in this manner. a parity error is detected on data received from the scsi bus. if the assert satn/ on parity error bit is cleared or the enable parity checking bit is cleared, satn/ is not automatically asserted on the scsi bus when a parity error is received. trg target mode 0 this bit determines the default operating mode of the lsi53c876 scsi function. the user must manually set the target or initiator mode. this is done using the scripts language ( set target or clear target ).
scsi registers 4-25 when this bit is set, the chip is a target device by default. when this bit is cleared, the lsi53c876 scsi function is an initiator device by default. note: writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes. register: 0x01 scsi control one (scntl1) read/write exc extra clock cycle of data setup 7 when this bit is set, an extra clock period of data setup is added to each scsi send data transfer. the extra data setup time can provide additional system design margin, though it affects the scsi transfer rates. clearing this bit disables the extra clock cycle of data setup time. setting this bit only affects scsi send operations. adb assert scsi data bus 6 when this bit is set, the lsi53c876 scsi function drives the contents of the scsi output data latch (sodl) register onto the scsi data bus. when the lsi53c876 scsi function is an initiator, the scsi i/o signal must be inactive to assert the sodl contents onto the scsi bus. when the lsi53c876 scsi function is a target, the scsi i/o signal must be active to assert the sodl contents onto the scsi bus. the contents of the sodl register can be asserted at any time, even before the lsi53c876 scsi function is connected to the scsi bus. clear this bit when executing scsi scripts. it is normally used only for diagnostics testing or operation in low level mode. dhp disable halt on parity error or atn (target only) 5 the dhp bit is only de?ned for target mode. when this bit is cleared, the lsi53c876 scsi function halts the scsi data transfer when a parity error is detected or when the satn/ signal is asserted. if satn/ or a parity error is received in the middle of a data transfer, the 76543210 exc adb dhp con rst aesp iarb sst 00000000
4-26 registers lsi53c876 scsi function may transfer up to three additional bytes before halting to synchronize between internal core cells. during synchronous operation, the lsi53c876 scsi function transfers data until there are no outstanding synchronous offsets. if the lsi53c876 scsi function is receiving data, any data residing in the dma fifo is sent to memory before halting. when this bit is set, the lsi53c876 scsi function does not halt the scsi transfer when satn/ or a parity error is received. con connected 4 this bit is automatically set any time the lsi53c876 scsi function is connected to the scsi bus as an initiator or as a target. it is set after the lsi53c876 scsi function successfully completes arbitration or when it has responded to a bus initiated selection or reselection. this bit is also set after the chip wins simple arbitration when operating in low level mode. when this bit is cleared, the lsi53c876 scsi function is not connected to the scsi bus. the cpu can force a connected or disconnected condition by setting or clearing this bit. this feature is used primarily during loopback mode. rst assert scsi rst/ signal 3 setting this bit asserts the srst/ signal. the srst/ output remains asserted until this bit is cleared. the 25 m s minimum assertion time de?ned in the scsi speci?cation must be timed out by the controlling microprocessor or a scripts loop. aesp assert even scsi parity (force bad parity) 2 when this bit is set, the lsi53c876 scsi function asserts even parity. it forces a scsi parity error on each byte sent to the scsi bus from the chip. if parity checking is enabled, then the lsi53c876 scsi function checks data received for odd parity. this bit is used for diagnostic testing and is cleared for normal operation. it is useful to generate parity errors to test error handling functions. iarb immediate arbitration 1 setting this bit causes the scsi core to immediately begin arbitration once a bus free phase is detected
scsi registers 4-27 following an expected scsi disconnect. this bit is useful for multithreaded applications. the arb[1:0] bits in the scsi control zero (scntl0) register are set for full arbitration and selection before setting this bit. arbitration is retried until won. at that point, the lsi53c876 scsi function holds bsy and sel asserted, and waits for a select or reselect sequence. the immediate arbitration bit is reset automatically when the selection or reselection sequence is completed, or times out. during the time between the assertion of the iarb bit and the completion of a perform select/reselect instruction, dma interrupts are disabled. therefore, interrupt instructions placed between the assertion of the iarb bit and the perform select/reselect instruction are not executed. an unexpected disconnect condition clears iarb without attempting arbitration. see the scsi disconnect unexpected bit ( scsi control two (scntl2) , bit 7) for more information on expected versus unexpected disconnects. it is possible to abort an immediate arbitration sequence. first, set the abort bit in the interrupt status (istat) register. then one of two things eventually happens: the won arbitration bit ( scsi status zero (sstat0) , bit 2) is set. in this case, the immediate arbitration bit needs to be cleared. this completes the abort sequence and disconnects the chip from the scsi bus. if it is not acceptable to go to bus free phase immediately following the arbitration phase, it is possible to perform a low level selection instead. the abort completes because the lsi53c876 scsi function loses arbitration. this is detected by the clearing of the immediate arbitration bit. do not use the lost arbitration bit ( scsi status zero (sstat0) , bit 3) to detect this condition. in this case take no further action. sst start scsi transfer 0 this bit is automatically set during scripts execution. it causes the scsi core to begin a scsi transfer, including sreq/sack handshaking. the determination of whether the transfer is a send or receive is made according to the
4-28 registers value written to the i/o bit in scsi output control latch (socl) . this bit is self-clearing. do not set it for low level operation. note: writing to this register while not connected may cause the loss of a selection/reselection by resetting the connected bit. register: 0x02 scsi control two (scntl2) read/write sdu scsi disconnect unexpected 7 this bit is valid in the initiator mode only. when this bit is set, the scsi core is not expecting the scsi bus to enter the bus free phase. if it does, an unexpected disconnect error is generated (see the unexpected disconnect bit in the scsi interrupt status zero (sist0) register, bit 2). during normal scripts mode operation, this bit is set automatically whenever the scsi core is reselected, or successfully selects another scsi device. the sdu bit should be cleared with a register write (move 0x00 to scsi control two (scntl2) ) before the scsi core expects a disconnect to occur, normally prior to sending an abort, abort tag, bus device reset, clear queue or release recovery message, or before deasserting sack/ after receiving a disconnect command or command complete message. chm chained mode 6 this bit determines whether or not the scsi core is programmed for chained scsi mode. this bit is automatically set by the chained block move (chmov) scripts instruction and is automatically cleared by the block move scripts instruction (move). chained mode primarily transfers consecutive wide data blocks. using chained mode facilitates partial receive transfers and allows correct partial send behavior. when this bit is set and a data transfer ends on an odd byte 76543210 sdu chm slpmd slphben wss vue0 vue1 wsr 000000x0
scsi registers 4-29 boundary, the lsi53c876 scsi function stores the last byte in the scsi wide residue (swide) register during a receive operation, or in the scsi output data latch (sodl) register during a send operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer is completed. for more information, see section 2.2.11, chained block moves, in chapter 2, functional description. slpmd slpar mode bit 5 if this bit is cleared, the scsi longitudinal parity (slpar) register functions as a byte-wide longitudinal parity register. if this bit is set, the slpar functions as a word-wide longitudinal parity function. the high or low byte of the slpar word is accessible through the scsi longitudinal parity (slpar) register. which byte is accessible is controlled by the slphen bit. slphben slpar high byte enable 4 if this bit is cleared, the low byte of the slpar word is present in the slpar register. if this bit is set, the high byte of the slpar word is present in the scsi longitu- dinal parity (slpar) register. wss wide scsi send 3 when read, this bit returns the value of the wide scsi send (wss) ?ag. asserting this bit clears the wss ?ag. this clearing function is self-clearing. when the wss ?ag is high following a wide scsi send operation, the scsi core is holding a byte of chain data in the scsi output data latch (sodl) register. this data becomes the ?rst low-order byte sent when married with a high-order byte during a subsequent data send transfer. performing a scsi receive operation clears this bit. also, performing any nonwide transfer clears this bit. vue0 vendor unique enhancement, bit 0 2 this bit is a read only value indicating whether the group code ?eld in the scsi instruction is standard or vendor unique. if cleared, the bit indicates standard group codes; if set, the bit indicates vendor unique group codes. the value in this bit is reloaded at the beginning of all asynchronous target receives.
4-30 registers vue1 vendor unique enhancement, bit 1 1 this bit disables the automatic byte count reload during block move instructions in the command phase. if this bit is cleared, the device reloads the block move byte count if the ?rst byte received is one of the standard group codes. if this bit is set, the device does not reload the block move byte count, regardless of the group code. wsr wide scsi receive 0 when read, this bit returns the value of the wide scsi receive (wsr) ?ag. setting this bit clears the wsr ?ag. this clearing function is self-clearing. the wsr ?ag indicates that the scsi core received data from the scsi bus, detected a possible partial transfer at the end of a chained or nonchained block move command, and temporarily stored the high-order byte in the scsi wide residue (swide) register rather than passing the byte out the dma channel. the hardware uses the wsr status ?ag to determine what behavior must occur at the start of the next data receive transfer. when the ?ag is set, the stored data in swide may be residue data, valid data for a subsequent data transfer, or overrun data. the byte is read as normal data by starting a data receive transfer. performing a scsi send operation clears this bit. also, performing any nonwide transfer clears this bit.
scsi registers 4-31 register: 0x03 scsi control three (scntl3) read/write use ultra scsi enable 7 setting this bit enables ultra scsi synchronous transfers. the default value of this bit is 0. set this bit only when the transfer rate exceeds 10 megatransfers/s. when this bit is set, the signal ?ltering period for sreq/ and sack/ automatically changes to 15 ns, regardless of the value of the extend req/ack filtering bit in the scsi test two (stest2) register. scf[2:0] synchronous clock conversion factor [6:4] these bits select a factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. write these to the same value as the clock conversion factor bits below unless fast scsi operation is desired. see the scsi transfer (sxfer) register description for examples of how the scf bits are used to calculate synchronous transfer periods. see the table under the description of bits [7:5] of the scsi transfer (sxfer) register for the valid combinations. note; for additional information on how the synchronous transfer rate is determined, refer to chapter 2, functional descrip- tion. ews enable wide scsi 3 when this bit is clear, all information transfer phases are assumed to be eight bits, transmitted on sd[7:0]/, sdp0/. when this bit is asserted, data transfers are done 16 bits at a time, with the least signi?cant byte on sd[7:0]/, sdp/ and the most signi?cant byte on sd[15:8]/, sdp1/. command, status, and message phases are not affected by this bit. 76 432 0 use scf[2:0] ews ccf[2:0] 00000000
4-32 registers ccf[2:0] clock conversion factor [2:0] these bits select a factor by which the frequency of sclk is divided before being presented to the scsi core. the synchronous portion of the scsi core can be run at a different clock rate for fast scsi, using the synchronous clock conversion factor bits. the bit encoding is displayed in the table below. all other combinations are reserved. note: it is important that these bits are set to the proper values to guarantee that the lsi53c876 meets the scsi timings as de?ned by the ansi speci?cation. register: 0x04 scsi chip id (scid) read/write r reserved 7 rre enable response to reselection 6 when this bit is set, the lsi53c876 scsi function is enabled to respond to bus-initiated reselection at the chip id in the response id zero (respid0) and response id scf2 ccf2 scf1 ccf1 scf0 ccf0 factor frequency scsi clock (mhz) 0 0 0 sclk/3 50.01C75.0 0 0 1 sclk/1 16.67C25.0 0 1 0 sclk/1.5 25.01C37.5 0 1 1 sclk/2 37.51C50.0 1 0 0 sclk/3 50.01C75.0 1 0 1 sclk/4 75.01-80.00 1 1 0 sclk/6 120 1 1 1 sclk/8 160 76543 0 r rre sre r enc[3:0] x00 x0000
scsi registers 4-33 one (respid1) registers. note that the chip does not automatically recon?gure itself to initiator mode as a result of being reselected. sre enable response to selection 5 when this bit is set, the lsi53c876 scsi function is able to respond to bus-initiated selection at the chip id in the response id zero (respid0) and response id one (respid1) registers. note that the chip does not automatically recon?gure itself to target mode as a result of being selected. r reserved 4 enc encoded chip scsi id [3:0] these bits store the lsi53c876 scsi function encoded scsi id. this is the id which the chip asserts when arbitrating for the scsi bus. the ids that the lsi53c876 scsi function responds to when selected or reselected are con?gured in the response id zero (respid0) and response id one (respid1) registers. the priority of the 16 possible ids, in descending order is: register: 0x05 scsi transfer (sxfer) read/write when using table indirect i/o commands, bits [7:0] of this register are loaded from the i/o data structure. for additional information on how the synchronous transfer rate is determined, refer to chapter 2, functional description. highest lowest 7654321015141312111098 754 0 tp[2:0] mo[4:0] 000x0000
4-34 registers tp[2:0] scsi synchronous transfer period [7:5] these bits determine the scsi synchronous transfer period used by the lsi53c876 scsi function when sending synchronous scsi data in either the initiator or target mode. these bits control the programmable dividers in the chip. for wide ultra scsi transfers, the ideal transfer period is 4, and 5 is acceptable. setting the transfer period to a value greater than 5 is not recommended. the synchronous transfer period the lsi53c876 should use when transferring scsi data is determined in the following example. the lsi53c876 is connected to a hard disk which can transfer data at 10 mbytes/s synchronously. the lsi53c876 scsi functions sclk is running at 40 mhz. the synchronous transfer period (sxferp) is found as follows: sxferp = period/sscp + extcc period = 1 ? frequency = 1 ? 10 mbytes/s = 100 ns sscp = 1 ? sscf = 1 ? 40 mhz = 25 ns (this scsi synchronous core clock is determined in scsi control three (scntl3) , bits [6:4], extcc = 1 if scsi control one (scntl1) , bit 7 is asserted and the lsi53c876 is sending data. extcc = 0 if the lsi53c876 is receiving data.) sxferp = 100 ? 25=4 tp2 tp1 tp0 xferp 0004 0015 0106 0117 1008 1019 11010 11111
scsi registers 4-35 where: mo[4:0] max scsi synchronous offset [4:0] these bits describe the maximum scsi synchronous offset used by the lsi53c876 scsi function when transferring synchronous scsi data in either initiator or target mode. table 4.5 describes the possible combinations and their relationship to the synchronous data offset used by the lsi53c876 scsi function. these bits determine the lsi53c876 scsi functions method of transfer for data-in and data-out phases only; all other information transfers occur asynchronously. sxferp synchronous transfer period. sscp scsi synchronous core period. sscf scsi synchronous core frequency. extcc extra clock cycle of data setup. table 4.3 examples of synchronous transfer periods for scsi-1 transfer rates clk (mhz) scsi clk ? scntl3 bits [6:4] xferp synch. transfer period (ns) synch. transfer rate (mbytes/s) 40 ? 4 4 200 5 80 ? 2 4 200 5 table 4.4 example transfer periods for fast scsi and wide ultra scsi transfer rates clk (mhz) scsi clk ? scntl3 bits [6:4] xferp synch. transfer period (ns) synch. transfer rate (mbytes/s) 80 ? 1 4 50 20 80 ? 2 4 100 10 40 ? 1 4 100 10
4-36 registers register: 0x06 scsi destination id (sdid) read/write r reserved [7:4] enc encoded destination scsi id [3:0] writing these bits sets the scsi id of the intended initiator or target during scsi reselection or selection phases, respectively. when executing scripts, the scripts processor writes the destination scsi id to this register. the scsi id is de?ned by the user in a table 4.5 maximum synchronous offset mo4 mo3 mo2 mo1 mo0 synchronous offset 0 0 0 0 0 0-asynchronous 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 1 x x x 1 reserved 1 x x 1 x reserved 1 x 1 x x reserved 1 1 x x x reserved 7430 r enc[3:0] x x x x0000
scsi registers 4-37 scripts select or reselect instruction. the value written is the binary-encoded id. the priority of the 16 possible ids, in descending order, is: register: 0x07 general purpose (gpreg) read/write the general purpose register drives and senses values on the general purpose i/o pins. if both scsi function gpreg registers de?ne a single gpio pin as an output, the results are indeterminate. r reserved [7:5] gpio[4:0] general purpose i/o [4:0] these bits are programmed through the general purpose pin control (gpcntl) register as inputs, outputs, or to perform special functions. as an output, these pins enable or disable external terminators. it is also possible to program these signals as live inputs and sense them through a scripts register to register move instruction. gpio[2:0] default as inputs and gpio4 defaults as an output pin. when con?gured as inputs, an internal pull-up is enabled. it is possible to use gpio4 to enable or disable v pp , the 12 v power supply to the external ?ash memory. this bit powers up with the power to the external memory disabled. the lsi logic pci to scsi host adapters use the gpio4 pin in the process of ?ashing a new sdms rom. highest lowest 765432101514131211098 754 0 r gpio[4:0] x x x0xxxx
4-38 registers lsi logic sdms software uses the gpio0 pin to toggle scsi device leds, turning on the led whenever the lsi53c876 scsi function is on the scsi bus. sdms software drives this pin low to turn on the led, or drives it high to turn off the led. lsi logic software also uses the gpio[1:0] signals to access serial eeprom. gpio1 is used as a clock, with the gpio0 pin serving as data. register: 0x08 scsi first byte received (sfbr) read/write 1b scsi first byte received [7:0] this register contains the ?rst byte received in any asynchronous information transfer phase. for example, when a lsi53c876 scsi function is operating in initiator mode, this register contains the ?rst byte received in the message-in, status, and data-in phases. when a block move instruction is executed for a particular phase, the ?rst byte received is stored in this register, even if the present phase is the same as the last phase. the ?rst byte received value for a particular input phase is not valid until after a move instruction is executed. this register is also the accumulator for register read-modify-writes with the sfbr as the destination. this allows bit testing after an operation. the sfbr is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. to load the sfbr with a byte stored in system memory, the byte must ?rst be moved to an intermediate lsi53c876 scsi function register (such as the scratch register), and then to the sfbr. 7 0 1b 00000000
scsi registers 4-39 this register also contains the state of the lower eight bits of the scsi data bus during the selection phase if the com bit in the dma control (dcntl) register is clear. if the com bit is cleared, do not access this register using scripts operation, as nondeterminate operations may occur. this includes scripts read/write operations and conditional transfer control instructions that initialize the scsi first byte received (sfbr) register. register: 0x09 scsi output control latch (socl) read/write req assert scsi req/ signal 7 ack assert scsi ack/ signal 6 bsy assert scsi bsy/ signal 5 sel assert scsi sel/ signal 4 atn assert scsi atn/ signal 3 msg assert scsi msg/ signal 2 c/d assert scsi c_d/ signal 1 i/o assert scsi i_o/ signal 0 this register is used primarily for diagnostic testing or programmed i/o operation. it is controlled by the scripts processor when executing scsi scripts. socl is used only when transferring data using programmed i/o. some bits are set (1) or reset (0) when executing scsi scripts. do not write to the register once the lsi53c876 scsi function starts executing normal scsi scripts. 76543210 req ack bsy sel atn msg c/d i/o 00000000
4-40 registers register: 0x0a scsi selector id (ssid) read only val scsi valid 7 if val is asserted, then the two scsi ids are detected on the bus during a bus-initiated selection or reselection, and the encoded destination scsi id bits below are valid. if val is deasserted, only one id is present and the contents of the encoded destination id are meaningless. r reserved [6:4] enid encoded destination scsi id [3:0] reading the ssid register immediately after the lsi53c876 scsi function is selected or reselected returns the binary-encoded scsi id of the device that performed the operation. these bits are invalid for targets that are selected under the single initiator option of the scsi-1 speci?cation. this condition is detected by examining the val bit above. 76 43 0 val r enid[3:0] 0 x x x0000
scsi registers 4-41 register: 0x0b scsi bus control lines (sbcl) read only req sreq/ status 7 ack sack/ status 6 bsy sbsy/ status 5 sel ssel/ status 4 atn satn/ status 3 msg smsg/ status 2 c/d sc_d/ status 1 i/o si_o/ status 0 this register returns the scsi control line status. a bit is set when the corresponding scsi control line is asserted. these bits are not latched; they are a true representation of what is on the scsi bus at the time the register is read. the resulting read data is synchronized before being presented to the pci bus to prevent parity errors from being passed to the system. this register is used for diagnostics testing or operation in low level mode. 76543210 req ack bsy sel atn msg c/d i/o xxxxxxxx
4-42 registers register: 0x0c dma status (dstat) read only reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the lsi53c876 scsi functions stacks interrupts). the dip bit in the interrupt status (istat) register is also cleared. it is possible to mask dma interrupt conditions individually through the dma interrupt enable (dien) register. when performing consecutive 8-bit reads of the dma status (dstat) , scsi interrupt status zero (sist0) , and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure that the interrupts clear properly. see chapter 2, functional description, for more information on interrupts. dfe dma fifo empty 7 this status bit is set when the dma fifo is empty. it is possible to use it to determine if any data resides in the fifo when an error occurs and an interrupt is generated. this bit is a pure status bit and does not cause an interrupt. mdpe master data parity error 6 this bit is set when the lsi53c876 scsi function as a master detects a data parity error, or a target device signals a parity error during a data phase. this bit is completely disabled by the master parity error enable bit (bit 3 of chip test four (ctest4) ). bf bus fault 5 this bit is set when a pci bus fault condition is detected. a pci bus fault can only occur when the lsi53c876 scsi function is bus master, and is de?ned as a cycle that ends with a bad address or target abort condition. 76543210 dfe mdpe bf abrt ssi sir r iid 100000 x0
scsi registers 4-43 abrt aborted 4 this bit is set when an abort condition occurs. an abort condition occurs when a software abort command is issued by setting bit 7 of the interrupt status (istat) register. ssi single step interrupt 3 if the single step mode bit in the dma control (dcntl) register is set, this bit is set and an interrupt is generated after successful execution of each scripts instruction. sir scripts interrupt instruction received 2 this status bit is set whenever an interrupt instruction is evaluated as true. r reserved 1 iid illegal instruction detected 0 this status bit is set any time an illegal or reserved instruction opcode is detected, whether the lsi53c876 scsi function is operating in single step mode or automatically executing scsi scripts. any of the following conditions during instruction execution also set this bit: the lsi53c876 scsi function is executing a wait disconnect instruction and the scsi req line is asserted without a disconnect occurring. a block move instruction is executed with 0x000000 loaded into the dma byte counter (dbc) register, indicating there are zero bytes to move. during a transfer control instruction, the compare data (bit 18) and compare phase (bit 17) bits are set in the dma byte counter (dbc) register while the lsi53c876 scsi function is in target mode. during a transfer control instruction, the carry test bit (bit 21) is set and either the compare data (bit 18) or compare phase (bit 17) bit is set. a transfer control instruction is executed with the reserved bit 22 set. a transfer control instruction is executed with the wait for valid phase bit (bit 16) set while the chip is in target mode.
4-44 registers a load/store instruction is issued with the memory address mapped to the operating registers of the chip, not including rom or ram. a load/store instruction is issued when the register address is not aligned with the memory address. a load/store instruction is issued with bit 5 in the dma command (dcmd) register cleared or bits 3 or 2 set. a load/store instruction when the count value in the dma byte counter (dbc) register is not set at 1 to 4. a load/store instruction attempts to cross a dword boundary. a memory move instruction is executed with one of the reserved bits in the dma command (dcmd) register set. a memory move instruction is executed with the source and destination addresses not aligned. register: 0x0d scsi status zero (sstat0) read only ilf sidl least signi?cant byte full 7 this bit is set when the least signi?cant byte in the scsi input data latch (sidl) register contains data. data is transferred from the scsi bus to the sidl register before being sent to the dma fifo and then to the host bus. the sidl register contains scsi data received asynchronously. synchronous data received does not ?ow through this register. orf sodr least signi?cant byte full 6 this bit is set when the least signi?cant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the scsi logic uses the sodr as a second storage register when 76543210 ilf orf olf aip loa woa rst/ sdp0/ 00000000
scsi registers 4-45 sending data synchronously. it is not readable or writable by the user. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. olf sodl least signi?cant byte full 5 this bit is set when the least signi?cant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bus to the scsi output data latch (sodl) register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. aip arbitration in progress 4 arbitration in progress (aip = 1) indicates that the lsi53c876 scsi function has detected a bus free condition, asserted bsy, and asserted its scsi id onto the scsi bus. loa lost arbitration 3 when set, loa indicates that the lsi53c876 scsi function has detected a bus free condition, arbitrated for the scsi bus, and lost arbitration due to another scsi device asserting the sel/ signal. woa won arbitration 2 when set, woa indicates that the lsi53c876 scsi function has detected a bus free condition, arbitrated for the scsi bus and won arbitration. the arbitration mode selected in the scsi control zero (scntl0) register must be full arbitration and selection to set this bit. rst/ scsi rst/ signal 1 this bit reports the current status of the scsi rst/ signal, and the rst signal (bit 3) in the scsi control one (scntl1) register. this bit is not latched and may change as it is read.
4-46 registers sdp0/ scsi sdp0/ parity signal 0 this bit represents the active high current status of the scsi sdp0/ parity signal. this signal is not latched and may change as it is read. register: 0x0e scsi status one (sstat1) read only ff[3:0] fifo flags [7:4] these four bits, along with scsi status two (sstat2) , bit 4, de?ne the number of bytes or words that currently reside in the lsi53c876 scsi synchronous data fifo as shown in table 4.6 . these bits are not latched and they will change as data moves through the fifo. because the fifo can only hold either 16 bytes or 16 words, values over 16 cannot occur. . 7 43210 ff[3:0] sdpol msg c_d i_o 0000xxxx table 4.6 scsi synchronous data fifo word count ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo 000000 000011 000102 000113 001004 001015 001106 001117 010008 010019
scsi registers 4-47 sdp0l latched scsi parity 3 this bit re?ects the scsi parity signal (sdp0/), corresponding to the data latched in the scsi input data latch (sidl) register. it changes when a new byte is latched into the least signi?cant byte of the sidl register. this bit is active high, in other words, it is set when the parity signal is active. msg scsi msg/ signal 2 c_d scsi c_d/ signal 1 i_o scsi i_o/ signal 0 these three scsi phase status bits (msg, c_d, and i_o) are latched on the asserting edge of sreq/ when operating in either initiator or target mode. these bits are set when the corresponding signal is active. they are useful when operating in low level mode. 0101010 0101111 0110012 0110113 0111014 0111115 1000016 table 4.6 scsi synchronous data fifo word count (cont.) ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo
4-48 registers register: 0x0f scsi status two (sstat2) read only ilf1 sidl most signi?cant byte full 7 this bit is set when the most signi?cant byte in the scsi input data latch (sidl) register contains data. data is transferred from the scsi bus to the scsi input data latch register before being sent to the dma fifo and then to the host bus. the scsi input data latch (sidl) register contains scsi data received asynchronously. synchronous data received does not ?ow through this register. orf1 sodr most signi?cant byte full 6 this bit is set when the most signi?cant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the scsi logic uses the sodr register as a second storage register when sending data synchronously. it is not accessible to the user. this bit determines how many bytes reside in the chip when an error occurs. olf1 sodl most signi?cant byte full 5 this bit is set when the most signi?cant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. 76543210 ilf orf1 olf1 ff4 spl1 r ldsc sdp1 0000x x1x
scsi registers 4-49 ff4 fifo flags, bit 4 4 this is the most signi?cant bit in the scsi fifo flags ?eld, with the rest of the bits in scsi status one (sstat1) . for a complete description of this ?eld, see the de?nition for scsi status one (sstat1) bits [7:4]. spl1 latched scsi parity for sd[15:8] 3 this active high bit re?ects the scsi odd parity signal corresponding to the data latched into the most signi?cant byte in the scsi input data latch (sidl) register. r reserved 2 ldsc last disconnect 1 this bit is used in conjunction with the connected (con) bit in scsi control one (scntl1) . it allows the user to detect the case in which a target device disconnects, and then some scsi device selects or reselects the lsi53c876 scsi function. if the connected bit is asserted and the ldsc bit is asserted, a disconnect is indicated. this bit is set when the connected bit in scntl1 is off. this bit is cleared when a block move instruction is executed while the connected bit in scntl1 is on. sdp1 scsi sdp1 signal 0 this bit represents the active high current state of the scsi sdp1 parity signal. it is unlatched and may change as it is read. registers: 0x10C0x13 data structure address (dsa) read/write dsa data structure address [31:0] this 32-bit register contains the base address used for all table indirect calculations. the dsa register is usually loaded prior to starting an i/o, but it is possible for a scripts memory move to load the dsa during the i/o. 31 0 dsa xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
4-50 registers during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. register: 0x14 interrupt status (istat) read/write this is the only register that is accessible by the host cpu while a lsi53c876 scsi function is executing scripts (without interfering in the operation of the function). it polls for interrupts if hardware interrupts are disabled. read this register after servicing an interrupt to check for stacked interrupts. for more information on interrupt handling refer to chapter 2, functional description. abrt abort operation 7 setting this bit aborts the current operation under execution by the lsi53c876 scsi function. if this bit is set and an interrupt is received, clear this bit before reading the dma status (dstat) register to prevent further aborted interrupts from being generated. the sequence to abort any operation is: 1. set this bit. 2. wait for an interrupt. 3. read the interrupt status (istat) register. 4. if the scsi interrupt pending bit is set, then read the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) register to determine the cause of the scsi interrupt and go back to step 2. 5. if the scsi interrupt pending bit is clear, and the dma interrupt pending bit is set, then write 0x00 value to this register. 6. read the dma status (dstat) register to verify the aborted interrupt and to see if any other interrupting conditions have occurred. 76543210 abrt srst sigp sem con intf sip dip 00000000
scsi registers 4-51 srst software reset 6 setting this bit resets the lsi53c876 scsi function. all operating registers are cleared to their respective default values and all scsi signals are deasserted. setting this bit does not assert the scsi rst/ signal. this reset does not clear the id mode bit or any of the pci con?guration registers. this bit is not self-clearing; it must be cleared to clear the reset condition (a hardware reset also clears this bit). sigp signal process 5 sigp is a r/w bit that is writable at any time, and polled and reset using chip test two (ctest2) . the sigp bit is used in various ways to pass a ?ag to or from a running scripts instruction. the only scripts instruction directly affected by the sigp bit is wait for selection/reselection. setting this bit causes that instruction to jump to the alternate address immediately. the instructions at the alternate jump address should check the status of sigp to determine the cause of the jump. the sigp bit is usable at any time and is not restricted to the wait for selection/reselection condition. sem semaphore 4 the scripts processor may set this bit using a scripts register write instruction. an external processor may also set it while the lsi53c876 scsi function is executing a scripts operation. this bit enables the scsi function to notify an external processor of a prede?ned condition while scripts are running. the external processor may also notify the lsi53c876 scsi function of a prede?ned condition and the scripts processor may take action while scripts are executing. con connected 3 this bit is automatically set any time the lsi53c876 scsi function is connected to the scsi bus as an initiator or as a target. it is set after successfully completing selection or when the lsi53c876 scsi function responds to a bus-initiated selection or reselection. it is also set after the scsi function wins arbitration when operating in low level mode. when this bit is clear, the lsi53c876 scsi function is not connected to the scsi bus.
4-52 registers intf interrupt-on-the-fly 2 this bit is asserted by an intfly instruction during scripts execution. scripts programs do not halt when the interrupt occurs. this bit can be used to notify a service routine, running on the main processor while the scripts processor is still executing a scripts program. if this bit is set when the interrupt status (istat) register is read it is not automatically cleared. to clear this bit, write it to a one. the reset operation is self-clearing. if the intf bit is set but sip or dip are not set, do not attempt to read the other chip status registers. an interrupt-on-the-fly interrupt must be cleared before servicing any other interrupts indicated by sip or dip. this bit must be written to one in order to clear it after it has been set. sip scsi interrupt pending 1 this status bit is set when an interrupt condition is detected in the scsi portion of the lsi53c876 scsi function. the following conditions cause a scsi interrupt to occur: a phase mismatch (initiator mode) or satn/ becomes active (target mode) an arbitration sequence completes a selection or reselection time-out occurs the lsi53c876 scsi function is selected the lsi53c876 scsi function is reselected a scsi gross error occurs an unexpected disconnect occurs a scsi reset occurs a parity error is detected the handshake-to-handshake timer is expired the general purpose timer is expired to determine exactly which condition(s) caused the interrupt, read the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers.
scsi registers 4-53 dip dma interrupt pending 0 this status bit is set when an interrupt condition is detected in the dma portion of the lsi53c876 scsi function. the following conditions cause a dma interrupt to occur: a pci parity error is detected a bus fault is detected an abort condition is detected a scripts instruction is executed in single step mode a scripts interrupt instruction is executed an illegal instruction is detected. to determine exactly which condition(s) caused the interrupt, read the dma status (dstat) register register: 0x18 chip test zero (ctest0) read/write r reserved [7:3] ap[2:0] arbitration priority [2:0] these bits are the priority used for gaining access to the pci bus through the internal arbiter in the lsi53c876 scsi function. valid arbitration priority values are 0 (lowest priority) through 7 (highest priority). 7320 r ap[2:0] 0 x x x x111
4-54 registers register: 0x19 chip test one (ctest1) read only fmt[3:0] byte empty in dma fifo [7:4] these bits identify the bottom bytes in the dma fifo that are empty. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is empty, then fmt3 is set. since the fmt ?ags indicate the status of bytes at the bottom of the fifo, if all fmt bits are set, the dma fifo is empty. ffl[3:0] byte full in dma fifo [3:0] these status bits identify the top bytes in the dma fifo that are full. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is full then ffl3 is set. since the ffl ?ags indicate the status of bytes at the top of the fifo, if all ffl bits are set, the dma fifo is full. register: 0x1a chip test two (ctest2) read only ddir data transfer direction 7 this status bit indicates which direction data is being transferred. when this bit is set, the data is transferred from the scsi bus to the host bus. when this bit is clear, the data is transferred from the host bus to the scsi bus. sigp signal process 6 this bit is a copy of the sigp bit in the interrupt status (istat) register (bit 5). the sigp bit signals a running scripts instruction. when this register is read, the sigp bit in the istat register is cleared. 7430 fmt[3:0] ffl[3:0] 11110000 76543210 ddir sigp cio cm srtch teop dreq dack 00xx0001
scsi registers 4-55 cio con?gured as i/o 5 this bit is de?ned as the con?guration i/o enable status bit. this read only bit indicates if the chip is currently enabled as i/o space. note: both bits 4 and 5 may be set if the chip is dual-mapped. cm con?gured as memory 4 this bit is de?ned as the con?guration memory enable status bit. this read only bit indicates if the chip is currently enabled as memory space. note: both bits 4 and 5 may be set if the chip is dual-mapped. srtch scratcha/b operation 3 this bit controls the operation of the scratch register a (scratcha) and scratch register b (scratchb) registers. when it is set, scratchb contains the ram base address value from the pci con?guration ram base address register. this is the base address for the 4 kbytes internal ram. in addition, the scratcha register displays the memory-mapped based address of the chip operating registers. when this bit is cleared, the scratch register a (scratcha) and scratch register b (scratchb) registers return to normal operation. bit 3 is the only writable bit in this register. all other bits are read only. when modifying this register, all other bits must be written to zero. do not execute a read-modify- write to this register. teop scsi true end of process 2 this bit indicates the status of the lsi53c876 scsi functions internal teop signal. the teop signal acknowledges the completion of a transfer through the scsi portion of the lsi53c876 scsi function. when this bit is set, teop is active. when this bit is clear, teop is inactive. dreq data request status 1 this bit indicates the status of the lsi53c876 scsi functions internal data request signal (dreq). when this bit is set, dreq is active. when this bit is clear, dreq is inactive.
4-56 registers dack data acknowledge status 0 this bit indicates the status of the lsi53c876 scsi functions internal data acknowledge signal (dack/). when this bit is set, dack/ is inactive. when this bit is clear, dack/ is active. register: 0x1b chip test three (ctest3) read/write v[3:0] chip revision level [7:4] these bits identify the chip revision level for software purposes. it should have the same value as the lower nibble of the pci revision id register. flf flush dma fifo 3 when this bit is set, data residing in the dma fifo is transferred to memory, starting at the address in the dma next address (dnad) register. the internal dmawr signal, controlled by the chip test five (ctest5) register, determines the direction of the transfer. this bit is not self-clearing; clear it once the data is successfully transferred by the lsi53c876 scsi function. note: polling of fifo ?ags is allowed during ?ush operations. clf clear dma fifo 2 when this bit is set, all data pointers for the dma fifo are cleared. any data in the fifo is lost. after the lsi53c876 scsi function successfully clears the appropriate fifo pointers and registers, this bit automatically clears. note: this bit does not clear the data visible at the bottom of the fifo. 7 43210 v[3:0] flf clf fm wrie xxxx0000
scsi registers 4-57 fm fetch pin mode 1 when set, this bit causes the fetch/ pin to deassert during indirect and table indirect read operations. fetch/ is only active during the opcode portion of an instruction fetch. this allows the storage of scripts in a prom while data tables are stored in ram. if this bit is not set, fetch/ is asserted for all bus cycles during instruction fetches. wrie write and invalidate enable 0 this bit, when set, causes the issuing of write and invalidate commands on the pci bus whenever legal. the write and invalidate enable bit in the pci con?guration command register must also be set in order for the chip to generate write and invalidate commands. registers: 0x1cC0x1f temporary (temp) read/write temp temporary [31:0] this 32-bit register stores the return instruction address pointer from the call instruction. the address pointer stored in this register is loaded into the dma scripts pointer (dsp) register when a return instruction is executed. this address points to the next instruction to execute. do not write to this register while the lsi53c876 scsi function is executing scripts. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. 31 0 temp xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
4-58 registers register: 0x20 dma fifo (dfifo) read/write bo byte offset counter [7:0] these bits, along with bits [1:0] in the chip test five (ctest5) register, indicate the amount of data transferred between the scsi core and the dma core. it determines the number of bytes in the dma fifo when an interrupt occurs. these bits are unstable while data is being transferred between the two cores. once the chip has stopped transferring data, these bits are stable. the dfifo register counts the number of bytes transferred between the dma core and the scsi core. the dma byte counter (dbc) register counts the number of bytes transferred across the host bus. the difference between these two counters represents the number of bytes remaining in the dma fifo. the following steps determine how many bytes are left in the dma fifo when an error occurs, regardless of the transfer direction: if the dma fifo size is set to 88 bytes, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dfifo register. if the dma fifo size is set to 536 bytes (using bit 5 of the ctest register), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which is made up of the ctest register (bits 1 and 0) and the dma fifo (dfifo) register (bits [7:0]). if the dma fifo size is set to 88 bytes, and the result with 0x7f for a byte count between zero and 64. if the dma fifo size is set to 536 bytes, and the result with 0x3ff for a byte count between zero and 536. 7 0 bo x0000000
scsi registers 4-59 register: 0x21 chip test four (ctest4) read/write bdis burst disable 7 when set, this bit causes the lsi53c876 scsi function to perform back-to-back cycles for all transfers. when this bit is cleared, back-to-back transfers for opcode fetches and burst transfers for data moves are performed. zmod high impedance mode 6 setting this bit causes the lsi53c876 scsi function to place all output and bidirectional pins into a high impedance state. in order to read data out of the lsi53c876 scsi function, clear this bit. this bit is intended for board-level testing only. do not set this bit during normal system operation. to use this feature set the bit in both scsi function a and scsi function b. zsd scsi data high impedance 5 setting this bit causes the lsi53c876 scsi function to place the scsi data bus sd[15:0] and the parity lines sdp[1:0] in a high impedance state. in order to transfer data on the scsi bus, clear this bit. srtm shadow register test mode 4 setting this bit allows access to the shadow registers used by memory-to-memory move operations. when this bit is set, register accesses to the temporary (temp) and data structure address (dsa) registers are directed to the shadow copies stemp (shadow temp) and sdsa (shadow dsa). the registers are shadowed to prevent them from being overwritten during a memory-to-memory move operation. the data structure address (dsa) and temporary (temp) registers contain the base address used for table indirect calculations, and the address pointer for a call or return instruction, respectively. this bit is intended for manufacturing diagnostics only and should not be set during normal operations. 765432 0 bdis zmod zsd srtm mpee fbl[2:0] 00000000
4-60 registers mpee master parity error enable 3 setting this bit enables parity checking during master data phases. a parity error during a bus master read is detected by the lsi53c876 scsi function. a parity error during a bus master write is detected by the target, and the lsi53c876 scsi function is informed of the error by the perr/ pin being asserted by the target. when this bit is cleared, the lsi53c876 scsi function does not interrupt if a master parity error occurs. this bit is cleared at power-up. fbl[2:0] fifo byte control [2:0] these bits steer the contents of the chip test six (ctest6) register to the appropriate byte lane of the 32-bit dma fifo. if the fbl2 bit is set, then fbl1 and fbl0 determine which of four byte lanes can be read or written. when cleared, the byte lane which is read or written is determined by the current contents of the dma next address (dnad) and dma byte counter (dbc) registers. each of the four bytes that make up the 32-bit dma fifo is accessed by writing these bits to the proper value. for normal operation, fbl2 must equal zero. fbl2 fbl1 fbl0 dma fifo byte lane pins 0 x x disabled n/a 1 0 0 0 d[7:0] 1 0 1 1 d[15:8] 1 1 0 2 d[23:16] 1 1 1 3 d[31:24]
scsi registers 4-61 register: 0x22 chip test five (ctest5) read/write adck clock address incrementor 7 setting this bit increments the address pointer contained in the dma next address (dnad) register. the dnad register is incremented based on the dnad contents and the current dbc value. this bit automatically clears itself after incrementing the dma next address (dnad) register. bbck clock byte counter 6 setting this bit decrements the byte count contained in the 24-bit dma byte counter (dbc) register. it is decremented based on the dbc contents and the current dnad value. this bit automatically clears itself after decrementing the dbc register. dfs dma fifo size 5 this bit controls the size of the dma fifo. when clear, the dma fifo appears as only 88 bytes deep. when set, the dma fifo size increases to 536 bytes. using an 88-byte fifo allows software written for other lsi53c8xx family chips to properly calculate the number of bytes residing in the chip after a target disconnect. the default value of this bit is zero. masr master control for set or reset pulses 4 this bit controls the operation of bit 3. when this bit is set, bit 3 asserts the corresponding signals. when this bit is reset, bit 3 deasserts the corresponding signals. do not change this bit and bit 3 in the same write cycle. ddir dma direction 3 setting this bit either asserts or deasserts the internal dma write (dmawr) direction signal depending on the current status of the masr bit in this register. asserting the dmawr signal indicates that data is transferred from the scsi bus to the host bus. deasserting the dmawr signal transfers data from the host bus to the scsi bus. 76543210 adck bbck dfs masr ddir bl2 bo[9:8] 00000000
4-62 registers bl2 burst length, bit 2 2 this bit works with bits 6 and 7 in the dma mode (dmode) register to determine the burst length. for complete de?nitions of this ?eld, refer to the descriptions of dmode bits 6 and 7. this bit is disabled if an 88-byte fifo is selected by clearing the dma fifo size bit. bo[9:8] dma fifo byte offset counter, bits [9:8] [1:0] these are the upper two bits of the dfboc. refer to the dfboc register description for encodings of the bo[9:0] bits. register: 0x23 chip test six (ctest6) read/write df dma fifo [7:0] writing to this register writes data to the appropriate byte lane of the dma fifo as determined by the fbl bits in the chip test four (ctest4) register. reading this register unloads data from the appropriate byte lane of the dma fifo as determined by the fbl bits in the ctest4 register. data written to the fifo is loaded into the top of the fifo. data read out of the fifo is taken from the bottom. to prevent dma data from being corrupted, this register should not be accessed before starting or restarting scripts operation. write this register only when testing the dma fifo using the chip test four (ctest4) register. writing to this register while the test mode is not enabled produces unexpected results. 7 0 df 00000000
scsi registers 4-63 registers: 0x24C0x26 dma byte counter (dbc) read/write dbc dma byte counter [23:0] this 24-bit register determines the number of bytes transferred in a block move instruction. while sending data to the scsi bus, the counter is decremented as data is moved into the dma fifo from memory. while receiving data from the scsi bus, the counter is decremented as data is written to memory from the lsi53c876 scsi function. the dbc counter is decremented each time data is transferred on the pci bus. it is decremented by an amount equal to the number of bytes that are transferred. the maximum number of bytes that can be transferred in any one block move command is 16,777,215 bytes. the maximum value that can be loaded into the dma byte counter (dbc) register is 0xffffff. if the instruction is a block move and a value of 0x000000 is loaded into the dma byte counter (dbc) register, an illegal instruction interrupt occurs if the lsi53c876 scsi function is not in target mode, command phase. the dma byte counter (dbc) register also holds the least signi?cant 24 bits of the ?rst dword of a scripts fetch, and to hold the offset value during table indirect i/o scripts. for a complete description see chapter 5, scsi scripts instruction set. the power-up value of this register is indeterminate. 23 0 dbc xxxxxxxxxxxxxxxxxxxxxxxx
4-64 registers register: 0x27 dma command (dcmd) read/write dcmd dma command [7:0] this 8-bit register determines the instruction for the lsi53c876 scsi function to execute. this register has a different format for each instruction. for a complete description see chapter 5, scsi scripts instruction set. registers: 0x28C0x2b dma next address (dnad) read/write dnad dma next address [31:0] this 32-bit register contains the general purpose address pointer. at the start of some scripts operations, its value is copied from the dma scripts pointer save (dsps) register. its value may not be valid except in certain abort conditions. the default value of this register is zero. registers: 0x2cC0x2f dma scripts pointer (dsp) read/write dsp dma scripts pointer [31:0] to execute scsi scripts, the address of the ?rst scripts instruction must be written to this register. in 7 0 dcmd 01xxxxxx 31 0 dnad 00000000000000000000000000000000 31 0 dsp 00000000000000000000000000000000
scsi registers 4-65 normal scripts operation, once the starting address of the script is written to this register, scripts are automatically fetched and executed until an interrupt condition occurs. in single step mode, there is a single step interrupt after each instruction is executed. the dma scripts pointer (dsp) register does not need to be written with the next address, but the start dma bit (bit 2, dma control (dcntl) register) must be set each time the step interrupt occurs to fetch and execute the next scripts command. when writing this register eight bits at a time, writing the upper eight bits begins execution of scsi scripts. the default value of this register is zero. registers: 0x30C0x33 dma scripts pointer save (dsps) read/write dsps dma scripts pointer save [31:0] this register contains the second dword of a scripts instruction. it is overwritten each time a scripts instruction is fetched. when a scripts interrupt instruction is executed, this register holds the interrupt vector. the power-up value of this register is indeterminate. 31 0 dsps xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
4-66 registers register: 0x34 scratch register a (scratcha) read/write scratcha scratch register a [31:0] this is a general purpose, user-de?nable scratch pad register. apart from cpu access, only register read/write and memory moves into the scratch register alter its contents. the power-up value of this register is indeterminate. a special mode of this register is enabled by setting the bae bit in the chip test five (ctest5) register. if this bit is set, the scratch register a (scratcha) register returns the memory base address of the chip registers on the upper 24 bits of the data bus when the scratcha register is read. writes to the scratcha register are unaffected. resetting the bae bit causes the scratcha register to return to normal operation. register: 0x38 dma mode (dmode) read/write bl[1:0] burst length [7:6] these bits control the maximum number of transfers performed per bus ownership, regardless of whether the transfers are back-to-back, burst, or a combination of both. the lsi53c876 scsi function asserts the bus request (req/) output when the dma fifo can accommodate a transfer of at least one burst size of data. bus request (req/) is also asserted during start-of- transfer and end-of-transfer cleanup and alignment, even if less than a full burst of transfers is performed. the lsi53c876 scsi function inserts a fairness delay of four clks between burst transfers (as set in bl[1:0]) 31 0 scratcha xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 76543210 bl[1:0] siom diom er ermp bof man 00000000
scsi registers 4-67 during normal operation. the fairness delay is not inserted during pci retry cycles. this gives the cpu and other bus master devices the opportunity to access the pci bus between bursts. siom source i/o memory enable 5 this bit is de?ned as an i/o memory enable bit for the source address of a memory move or block move command. if this bit is set, then the source address is in i/o space; and if cleared, then the source address is in memory space. this function is useful for register-to-memory operations using the memory move instruction when a lsi53c876 scsi function is i/o mapped. bits 4 and 5 of the chip test two (ctest2) register determine the con?guration status of the lsi53c876 scsi function. diom destination i/o memory enable 4 this bit is de?ned as an i/o memory enable bit for the destination address of a memory move or block move command. if this bit is set, then the destination address is in i/o space; and if cleared, then the destination address is in memory space. this function is useful for memory-to-register operations using the memory move instruction when a lsi53c876 scsi function is i/o mapped. bits 4 and 5 of the chip test two (ctest2) register determine the con?guration status of the lsi53c876 scsi function. bl2 (ctest5 bit 2) bl1 bl0 burst length 0 0 0 2-transfer burst 0 0 1 4-transfer burst 0 1 0 8-transfer burst 0 1 1 16-transfer burst 1 0 0 32-transfer burst 1 1 0 1 64-transfer burst 1 1 1 0 128-transfer burst 1 1 1 1 reserved 1. only valid if the fifo size is set to 536 bytes.
4-68 registers erl enable read line 3 this bit enables a pci read line command. if this bit is set and the chip is about to execute a read cycle other than an opcode fetch, then the command is 0b1110. ermp enable read multiple 2 if this bit is set and cache mode is enabled, a read multiple command is used on all read cycles when it is legal. bof burst opcode fetch enable 1 setting this bit causes the lsi53c876 scsi function to fetch instructions in burst mode. speci?cally, the chip bursts in the ?rst two dwords of all instructions using a single bus ownership. if the instruction is a memory-to- memory move type, the third dword is accessed in a subsequent bus ownership. if the instruction is an indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move type, the chip accesses the remaining two dwords in a subsequent bus ownership, thereby fetching the four dwords required in two bursts of two dwords each. if prefetch is enabled, this bit has no effect. this bit also has no effect on fetches out of scripts ram. man manual start mode 0 setting this bit prevents the lsi53c876 scsi function from automatically fetching and executing scsi scripts when the dma scripts pointer (dsp) register is written. when this bit is set, the start dma bit in the dma control (dcntl) register must be set to begin scripts execution. clearing this bit causes the lsi53c876 scsi function to automatically begin fetching and executing scsi scripts when the dma scripts pointer (dsp) register is written. this bit normally is not used for scsi scripts operations.
scsi registers 4-69 register: 0x39 dma interrupt enable (dien) read/write r reserved 7 mdpe master data parity error 6 bf bus fault 5 abrt aborted 4 ssi single step interrupt 3 sir scripts interrupt instruction received 2 r reserved 1 iid illegal instruction detected 0 this register contains the interrupt mask bits corresponding to the interrupting conditions described in the dma status (dstat) register. an interrupt is masked by clearing the appropriate mask bit. masking an interrupt prevents inta/ (for function a) or intb/ (for function b) from being asserted for the corresponding interrupt, but the status bit is still set in the dstat register. masking an interrupt does not prevent setting the istat dip. all dma interrupts are considered fatal, therefore scripts stops running when this condition occurs, whether or not the interrupt is masked. setting a mask bit enables the assertion of inta/, or intb/, for the corresponding interrupt. (a masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through; interrupt stacking begins when either the istat sip or dip bit is set.) the inta/ and intb/ outputs are latched. once asserted, they remain asserted until the interrupt is cleared by reading the appropriate status register. masking an interrupt after the inta/, or intb/, output is asserted does not cause deassertion of inta/, or intb/. for more information on interrupts, see chapter 2, functional description. 76543210 r mdpe bf abrt ssi sir r iid x00000 x0
4-70 registers register: 0x3a scratch byte register (sbr) read/write sbr scratch byte register [7:0] this is a general purpose register. apart from cpu access, only register read/write and memory moves into this register alter its contents. the default value of this register is zero. this register is called the dma watchdog timer on previous lsi53c8xx family products. register: 0x3b dma control (dcntl) read/write clse cache line size enable 7 setting this bit enables the lsi53c876 scsi function to sense and react to cache line boundaries set up by the dma mode (dmode) or pci cache line size register, whichever contains the smaller value. clearing this bit disables the cache line size logic and the lsi53c876 scsi function monitors the cache line size using the dma mode (dmode) register. pff prefetch flush 6 setting this bit causes the prefetch unit to ?ush its contents. the bit clears after the ?ush is complete. pfen prefetch enable 5 setting this bit enables the prefetch unit if the burst size is equal to or greater than four. for more information on scripts instruction prefetching, see chapter 2, func- tional description. 7 0 sbr 00000000 76543210 clse pff pfen ssm intm std intd com 00000000
scsi registers 4-71 ssm single step mode 4 setting this bit causes the lsi53c876 scsi function to stop after executing each scripts instruction, and generate a single step interrupt. when this bit is cleared the lsi53c876 scsi function does not stop after each instruction. it continues fetching and executing instructions until an interrupt condition occurs. for normal scsi scripts operation, keep this bit clear. to restart the lsi53c876 scsi function after it generates a scripts step interrupt, read the interrupt status (istat) and dma status (dstat) registers to recognize and clear the interrupt. then set the start dma bit in this register. intm inta mode 3 when set, this bit enables a totem pole driver for the inta/, or intb/ pin. when cleared, this bit enables an open drain driver for the inta/, or intb/, pin with an internal weak pull-up. this bit is reset at power up. the bit should remain clear to retain full pci compliance. std start dma operation 2 the lsi53c876 scsi function fetches a scsi scripts instruction from the address contained in the dma scripts pointer (dsp) register when this bit is set. this bit is required if the lsi53c876 scsi function is in one of the following modes: manual start mode C bit 0 in the dma mode (dmode) register is set single step mode C bit 4 in the dma control (dcntl) register is set when the lsi53c876 scsi function is executing scripts in manual start mode, the start dma bit must be set to start instruction fetches, but need not be set again until an interrupt occurs. when the lsi53c876 scsi function is in single step mode, set the start dma bit to restart execution of scripts after a single step interrupt. irqd inta, intb disable 1 setting this bit disables the inta (for scsi function a), or intb (for scsi function b) pin. clearing the bit enables normal operation. as with any other register
4-72 registers other than interrupt status (istat) , this register cannot be accessed except by a scripts instruction during scripts execution. for more information on the use of this bit in interrupt handling, see chapter 2, functional description. com lsi53c700 family compatibility 0 when the com bit is cleared, the lsi53c876 scsi function behaves in a manner compatible with the lsi53c700 family; selection/reselection ids are stored in both the scsi selector id (ssid) and scsi first byte received (sfbr) registers. this bit is not effected by a software reset. if the com bit is cleared, do not access this register using scripts operation as nondeterminate operations may occur. (this includes scripts read/write operations and conditional transfer control instructions that initialize the scsi first byte received (sfbr) register.) when the com bit is set, the id is stored only in the scsi selector id (ssid) register, protecting the sfbr from being overwritten if a selection/reselection occurs during a dma register-to-register operation. register: 0x3cC0x3f adder sum output (adder) read only adder adder sum output [31:0] this register contains the output of the internal adder, and is used primarily for test purposes. the power-up value for this register is indeterminate. 31 0 adder xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
scsi registers 4-73 register: 0x40 scsi interrupt enable zero (sien0) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status zero (sist0) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts, see chapter 2, functional description. m/a scsi phase mismatch - initiator mode; scsi atn condition - target mode 7 setting this bit allows the lsi53c876 to generate an interrupt when a phase mismatch or atn condition occurs. in initiator mode, this bit is set when the scsi phase asserted by the target and sampled during sreq/ does not match the expected phase in the scsi output control latch (socl) register. this expected phase is automatically written by scsi scripts. in target mode, this bit is set when the initiator asserts satn/. see the disable halt on parity error or satn/ condition bit in the scsi control one (scntl1) register for more information on when this status is actually raised. cmp function complete 6 setting this bit allows the lsi53c876 to generate an interrupt when a full arbitration and selection sequence has completed. sel selected 5 setting this bit allows the lsi53c876 to generate an interrupt when the lsi53c876 has been selected by another scsi device. set the enable response to selection bit in the scsi chip id (scid) register for this to occur. 76543210 m/a cmp sel rsl sge udc rst par 00000000
4-74 registers rsl reselected 4 setting this bit allows the lsi53c876 to generate an interrupt when the lsi53c876 has been reselected by another scsi device. set the enable response to reselection bit in the scsi chip id (scid) register for this to occur. sge scsi gross error 3 setting this bit allows the lsi53c876 to generate an interrupt when a scsi gross error occurs. the following conditions are considered scsi gross errors: data under?ow C reading the scsi fifo when no data is present. data over?ow C writing the scsi fifo while it is full. offset under?ow C receiving a sack/ pulse in target mode before the corresponding sreq/ is sent. offset over?ow C receiving an sreq/ pulse in the initiator mode, and exceeding the maximum offset (de?ned by the mo[3:0] bits in the scsi transfer (sxfer) register). a phase change in the initiator mode, with an outstanding sreq/sack offset. residual data in scsi fifo C starting a transfer other than synchronous data receive with data left in the scsi synchronous receive fifo. udc unexpected disconnect 2 setting this bit allows the lsi53c876 to generate an interrupt when an unexpected disconnect occurs. this condition only occurs in the initiator mode. it happens when the target to which the lsi53c876 is connected disconnects from the scsi bus unexpectedly. see the scsi disconnect unexpected bit in the scsi control two (scntl2) register for more information on expected versus unexpected disconnects. any disconnect in low level mode causes this condition.
scsi registers 4-75 rst scsi reset condition 1 setting this bit allows the lsi53c876 to generate an interrupt when the srst/ signal has been asserted by the lsi53c876 or any other scsi device. this condition is edge-triggered, so multiple interrupts cannot occur because of a single srst/ pulse. par scsi parity error 0 setting this bit allows the lsi53c876 to generate an interrupt when the lsi53c876 detects a parity error while receiving or sending scsi data. see the disable halt on parity error or satn/ condition bits in the scsi control one (scntl1) register for more information on when this condition is actually raised. register: 0x41 scsi interrupt enable one (sien1) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status one (sist1) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts, refer to chapter 2, functional description. r reserved [7:4] wie wakeup interrupt enable 3 setting this bit allows the lsi53c876e to enable /irq on scsi reset. sto selection or reselection time-out 2 setting this bit allows the lsi53c876 to generate an interrupt when a selection or reselection time-out occurs. see the description of the scsi timer zero (stime0) register bits [3:0] for more information on the time-out periods. 7 43210 r wie sto gen hth x x x x0000
4-76 registers gen general purpose timer expired 1 setting this bit allows the lsi53c876 to generate an interrupt when the general purpose timer has expired. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. hth handshake-to-handshake timer expired 0 setting this bit allows the lsi53c876 to generate an interrupt when the handshake-to-handshake timer has expired. the time measured is the scsi request-to- request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake-to-handshake timer. register: 0x42 scsi interrupt status zero (sist0) read only reading the sist0 register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable zero (sien0) register or not. each bit set indicates occurrence of the corresponding condition. reading the sist0 clears the interrupt status. reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the lsi53c876 scsi functions stacks interrupts). scsi interrupt conditions are individually masked through the scsi interrupt enable zero (sien0) register. when performing consecutive 8-bit reads of the dma status (dstat) , scsi interrupt status zero (sist0) , and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure the interrupts clear properly. also, if reading the registers when both the istat sip and dip bits may not be set, read the scsi interrupt status zero (sist0) and scsi interrupt 76543210 m/a cmp sel rsl sge udc rst par 00000000
scsi registers 4-77 status one (sist1) registers before the dma status (dstat) register to avoid missing a scsi interrupt. for more information on interrupts, refer to chapter 2, functional description. m/a initiator mode: phase mismatch; target mode: satn/ active 7 in the initiator mode, this bit is set if the scsi phase asserted by the target does not match the instruction. the phase is sampled when sreq/ is asserted by the target. in target mode, this bit is set when the satn/ signal is asserted by the initiator. cmp function complete 6 this bit is set when an arbitration only or full arbitration sequence is completed. sel selected 5 this bit is set when the lsi53c876 scsi function is selected by another scsi device. the enable response to selection bit must be set in the scsi chip id (scid) register (and the respid register must hold the chips id) for the lsi53c876 scsi function to respond to selection attempts. rsl reselected 4 this bit is set when the lsi53c876 scsi function is reselected by another scsi device. the enable response to reselection bit must be set in the scsi chip id (scid) register (and the respid register must hold the chips id) for the lsi53c876 scsi function to respond to reselection attempts. sge scsi gross error 3 this bit is set when the lsi53c876 scsi function encounters a scsi gross error condition. the following conditions can result in a scsi gross error condition: data under?ow C reading the scsi fifo when register when no data is present. data over?ow C writing too many bytes to the scsi fifo, or the synchronous offset causes overwriting the scsi fifo. offset under?ow C the lsi53c876 scsi function is operating in target mode and a sack/ pulse is received when the outstanding offset is zero.
4-78 registers offset over?ow C the other scsi device sends a sreq/ or sack/ pulse with data which exceeds the maximum synchronous offset de?ned by the scsi transfer (sxfer) register. a phase change occurs with an outstanding synchronous offset when the lsi53c876 scsi function is operating as an initiator. residual data in the synchronous data fifo C a transfer other than synchronous data receive is started with data left in the synchronous data fifo. udc unexpected disconnect 2 this bit is set when the lsi53c876 scsi function is operating in initiator mode and the target device unexpectedly disconnects from the scsi bus. this bit is only valid when the lsi53c876 scsi function operates in the initiator mode. when the scsi function operates in low level mode, any disconnect causes an interrupt, even a valid scsi disconnect. this bit is also set if a selection time-out occurs (it may occur before, at the same time, or stacked after the sto interrupt, since this is not considered an expected disconnect). rst scsi rst/ received 1 this bit is set when the lsi53c876 scsi function detects an active srst/ signal, whether the reset is generated external to the chip or caused by the assert srst/ bit in the scsi control one (scntl1) register. this scsi reset detection logic is edge-sensitive, so that multiple interrupts are not generated for a single assertion of the srst/ signal. par parity error 0 this bit is set when the lsi53c876 scsi function detects a parity error while receiving scsi data. the enable parity checking bit (bit 3 in the scsi control zero (scntl0) register) must be set for this bit to become active. the lsi53c876 scsi function always generates parity when sending scsi data.
scsi registers 4-79 register: 0x43 scsi interrupt status one (sist1) read only reading the sist1 register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable one (sien1) register or not. each bit that is set indicates an occurrence of the corresponding condition. reading the sist1 clears the interrupt condition. r reserved [7:3] sto selection or reselection time-out 2 the scsi device which the lsi53c876 scsi function is attempting to select or reselect does not respond within the programmed time-out period. see the description of the scsi timer zero (stime0) register, bits [3:0], for more information on the time-out timer. gen general purpose timer expired 1 this bit is set when the general purpose timer expires. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. hth handshake-to-handshake timer expired 0 this bit is set when the handshake-to-handshake timer expires. the time measured is the scsi request to request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake-to-handshake timer. 7 3210 r sto gen hth x x x x x000
4-80 registers register: 0x44 scsi longitudinal parity (slpar) read/write slpar scsi longitudinal parity [7:0] this register performs a bytewise longitudinal parity check on all scsi data received or sent through the scsi core. if one of the bytes received or sent (usually the last) is the set of correct even parity bits, slpar should go to zero (assuming it started at zero). as an example, suppose that the following three data bytes and one check byte are received from the scsi bus (all signals are shown active high): a one in any bit position of the ?nal slpar value would indicate a transmission error. the scsi longitudinal parity (slpar) register also generates the check bytes for scsi send operations. if the slpar register contains all zeros prior to sending a block move, it contains the appropriate check byte at the end of the block move. this byte must then be sent across the scsi bus. note: writing any value to this register resets it to zero. 7 0 slpar xxxxxxxx data bytes running slpar C 00000000 1. 11001100 11001100 (xor of word 1) 2. 01010101 10011001 (xor of word 1 and 2) 3. 00001111 10010110 (xor of word 1, 2 and 3) even parity >>> 10010110 4. 10010110 00000000
scsi registers 4-81 the longitudinal parity checks are meant to provide an added measure of scsi data integrity and are entirely optional. this register does not latch scsi selection/reselection ids under any circumstances. the default value of this register is zero. the longitudinal parity function normally operates as a byte function. during 16-bit transfers, the high and low bytes are xored together and then xored into the current longitudinal parity value. by setting the slpmd bit in the scsi control three (scntl3) register, the longitudinal parity function is made to operate as a word-wide function. during 16-bit transfers, the high byte of the scsi bus is xored with the high byte of the current longitudinal parity value, and the low byte of the scsi bus is xored with the low byte of the current longitudinal parity value. in this mode, the 16-bit longitudinal parity value is accessed a byte at a time through the scsi longitudinal parity (slpar) register. which byte is accessed is controlled by the slphben bit in the scsi control three (scntl3) register. register: 0x45 scsi wide residue (swide) read/write swide scsi wide residue [7:0] after a wide scsi data receive operation, this register contains a residual data byte if the last byte received was never sent across the dma bus. it represents either the ?rst data byte of a subsequent data transfer, or it is a residue byte which should be cleared when an ignore wide residue message is received. it may also be an overrun data byte. the power-up value of this register is indeterminate. 7 0 swide xxxxxxxx
4-82 registers register: 0x46 memory access control (macntl) read/write typ[3:0] chip type [7:4] these bits identify the chip type for software purposes. this technical manual applies to devices that have these bits set to 0x70. r reserved [3:0] register: 0x47 general purpose pin control (gpcntl) read/write this register determines if the pins controlled by the general purpose (gpreg) are inputs or outputs. bits [4:0] in gpcntl correspond to bits [4:0] in the gpreg register. when the bits are enabled as inputs, an internal pull-up is also enabled. if either scsi function general purpose pin control (gpcntl) register has a gpio pin set as an output, the pin is enabled as an output. if both the scsi function gpreg registers de?ne a single gpio pin as an output, the results are indeterminate. me master enable 7 the internal bus master signal is presented on gpio1 if this bit is set, regardless of the state of bit 1 (gpio1_en). fe fetch enable 6 the internal opcode fetch signal is presented on gpio0 if this bit is set, regardless of the state of bit 0 (gpio0_en). 7430 typ[3:0] r 0111 x x x x 7654 210 me fe r gpio[4:2] gpio[1:0] 00 x01111
scsi registers 4-83 r reserved 5 gpio[4:2] gpio enable [4:2] general purpose control, corresponding to bit 4 in the general purpose (gpreg) register and the gpio4 pin. gpio4 powers-up as a general purpose output, and gpio[3:2] power-up as general purpose inputs. gpio[1:0] gpio enable [1:0] these bits power-up set, causing the gpio1 and gpio0 pins to become inputs. clearing these bits causes gpio[1:0] to become outputs. register: 0x48 scsi timer zero (stime0) read/write hth handshake-to-handshake timer period [7:4] these bits select the handshake-to-handshake time-out period, the maximum time between scsi handshakes (sreq/ to sreq/ in target mode, or sack/ to sack/ in initiator mode). when this timing is exceeded, an interrupt is generated and the hth bit in the scsi interrupt status one (sist1) register is set. the following table contains time-out periods for the handshake-to-handshake timer, the selection/reselection timer (bits [3:0]), and the general purpose timer ( scsi timer one (stime1) , bits [3:0]). for a more detailed explanation of interrupts, refer to chapter 2, functional description. 743 0 hth[3:0] sel[3:0] 00000000
4-84 registers sel selection time-out [3:0] these bits select the scsi selection/reselection time-out period. when this timing (plus the 200 m s selection abort time) is exceeded, the sto bit in the scsi interrupt sta- tus one (sist1) register is set. for a more detailed explanation of interrupts, refer to chapter 2, functional description. hth[7:4] sel[3:0] gen[3:0] 1 minimum time-out (80 mhz clock) with scale factor bit cleared minimum time-out (80 mhz clock) with scale factor bit set 0000 disabled disabled 0001 100 m s 1.6 ms 0010 200 m s 3.2 ms 0011 400 m s 6.4 ms 0100 800 m s 12.8 ms 0101 .6 ms 25.6 ms 0110 3.2 ms 51.2 ms 0111 6.4 ms 102.4 ms 1000 12.8 ms 204.8 ms 1001 25.6 ms 409.6 ms 1010 51.2 ms 819.2 ms 1011 102.4 ms 1.6 s 1100 204.8 ms 3.2 s 1101 409.6 ms 6.4 s 1110 19.2 ms 12.8 s 1111 1.6+ s 25.6 s 1. these values are correct if the ccf bits in the scsi control three (scntl3) register are set according to the valid combinations in the bit description.
scsi registers 4-85 register: 0x49 scsi timer one (stime1) read/write r reserved 7 hthba handshake-to-handshake timer bus activity enable 6 setting this bit causes this timer to begin testing for scsi req/, ack/ activity as soon as sbsy/ is asserted, regardless of the agents participating in the transfer. gensf general purpose timer scale factor 5 setting this bit causes this timer to shift by a factor of 16. refer to the scsi timer zero (stime0) register description for details. hthsf handshake-to-handshake timer scale factor 4 setting this bit causes this timer to shift by a factor of 16. refer to the scsi timer zero (stime0) register description for details. gen[3:0] general purpose timer period [3:0] these bits select the period of the general purpose timer. the time measured is the time between enabling and disabling of the timer. when this timing is exceeded, the gen bit in the scsi interrupt status one (sist1) register is set. refer to the table under scsi timer zero (stime0) , bits [3:0], for the available time-out periods. note: to reset a timer before it expires and obtain repeatable delays, the time value must be written to zero ?rst, and then written back to the desired value. this is also required when changing from one time value to another. 76543 0 r hthba gensf hthsf gen[3:0] x0000000
4-86 registers register: 0x4a response id zero (respid0) read/write respid0 response id zero [7:0] respid0 and respid1 contain the selection or reselection ids. in other words, these two 8-bit registers contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most signi?cant bit of respid1 representing id 15 and the least signi?cant bit of respid0 representing id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the response id one (respid1) and response id zero (respid0) registers. however, the chip can arbitrate with only one id value in the scsi chip id (scid) register. register: 0x4b response id one (respid1) read/write respid1 response id one [15:8] respid0 and respid1 contain the selection or reselection ids. in other words, these two 8-bit registers contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most signi?cant bit of respid1 representing id 15 and the least signi?cant bit of respid0 representing id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the 7 0 id xxxxxxxx 15 8 id xxxxxxxx
scsi registers 4-87 response id one (respid1) and response id zero (respid0) registers. however, the chip can arbitrate with only one id value in the scsi chip id (scid) register. register: 0x4c scsi test zero (stest0) read only ssaid[3:0] scsi selected as id [7:4] these bits contain the encoded value of the scsi id that the lsi53c876 scsi function is selected or reselected as during a scsi selection or reselection phase. these bits are read only and contain the encoded value of 0C15 possible ids that could be used to select the lsi53c876 scsi function. during a scsi selection or reselection phase when a valid id is put on the bus, and the lsi53c876 scsi function responds to that id, the selected as id is written into these bits. these bits are used with the respid registers to allow response to multiple ids on the bus. slt selection response logic test 3 this bit is set when the lsi53c876 scsi function is ready to be selected or reselected. this does not take into account the bus settle delay of 400 ns. this bit is used for functional test and fault purposes. art arbitration priority encoder test 2 this bit is always set when the lsi53c876 scsi function exhibits the highest priority id asserted on the scsi bus during arbitration. it is primarily used for chip level testing, but it may be used during low level mode operation to determine if the lsi53c876 scsi function won arbitration. soz scsi synchronous offset zero 1 this bit indicates that the current synchronous sreq/, sack/ offset is zero. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. when this bit is set, the lsi53c876 7 43210 ssaid[3:0] slt art soz som 00000x11
4-88 registers scsi function, as an initiator, is waiting for the target to request data transfers. if the lsi53c876 scsi function is a target, then the initiator has sent the offset number of acknowledges. som scsi synchronous offset maximum 0 this bit indicates that the current synchronous sreq/, sack/ offset is the maximum speci?ed by bits [3:0] in the scsi transfer (sxfer) register. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. when this bit is set, the lsi53c876 scsi function, as a target, is waiting for the initiator to acknowledge the data transfers. if the lsi53c876 scsi function is an initiator, then the target has sent the offset number of requests. register: 0x4d scsi test one (stest1) read/write sclk scsi clock 7 when set, this bit disables the external sclk (scsi clock) pin, and the chip uses the pci clock as the internal scsi clock. if a transfer rate of 10 mbytes/s (or 20 mbytes/s on a wide scsi bus) is desired on the scsi bus, this bit must be cleared and a 40 mhz external sclk must be provided. iso scsi isolation mode 6 this bit allows the lsi53c876 scsi function to put the scsi bidirectional and input pins into a low power mode when the scsi bus is not in use. when this bit is set, the scsi bus inputs are logically isolated from the scsi bus. r reserved [5:4] dblen sclk doubler enable 3 this bit, when reset, powers down the internal clock doubler circuit, which doubles the sclk 40 mhz clock to an internal 80 mhz scsi clock required for wide ultra 76543210 sclk siso r dblen dblsel r 00 x x00 x x
scsi registers 4-89 scsi operation. both the sclk doubler enable dblen and sclk double select dblsel bits must be set in either scsi function to get the internal 80 mhz scsi clock. dblsel sclk doubler select 2 this bit, when set, selects the output of the internal clock doubler for use as the internal scsi clock. when reset, this bit selects the clock presented on sclk for use as the internal scsi clock. r reserved [1:0] the lsi53c876 scsi clock doubler doubles a 40 mhz scsi clock, increasing the frequency to 80 mhz. follow these steps to use the clock doubler. 1. set the sclk doubler enable bit ( scsi test one (stest1) , bit 3). 2. wait 20 m s. 3. halt the scsi clock by setting the halt scsi clock bit ( scsi test three (stest3) , bit 5). 4. set the clock conversion factor using the scf and ccf ?elds in the scsi control three (scntl3) register. 5. set the sclk doubler select bit ( scsi test one (stest1) , bit 2). 6. clear the halt scsi clock bit.
4-90 registers register: 0x4e scsi test two (stest2) read/write sce scsi control enable 7 setting this bit allows assertion of all scsi control and data lines through the scsi output control latch (socl) and scsi output data latch (sodl) registers regardless of whether the lsi53c876 scsi function is con?gured as a target or initiator. note: do not set this bit during normal operation, since it could cause contention on the scsi bus. it is included for diagnostic purposes only. rof reset scsi offset 6 setting this bit clears any outstanding synchronous sreq/sack offset. set this bit if a scsi gross error condition occurs and to clear the offset when a synchronous transfer does not complete successfully. the bit automatically clears itself after resetting the synchronous offset. dif differential mode 5 setting this bit allows the lsi53c876 scsi function to interface to external differential transceivers. its only real effect is to 3-state the sbsy/, ssel/, and srst/ pads for use as pure inputs. clearing this bit enables se operation. set this bit in the initialization routine if the differential pair interface is used. slb scsi loopback mode 4 setting this bit allows the lsi53c876 scsi function to perform scsi loopback diagnostics. that is, it enables the scsi core to simultaneously perform as both the initiator and the target. 76543210 sce rof dif slb szm aws ext low 00000000
scsi registers 4-91 szm scsi high impedance mode 3 setting this bit places all the open drain 48 ma scsi drivers into a high impedance state. this is to allow internal loopback mode operation without affecting the scsi bus. aws always wide scsi 2 when this bit is set, all scsi information transfers are done in 16-bit wide mode. this includes data, message, command, status, and reserved phases. normally, deassert this bit since 16-bit wide message, command, and status phases are not supported by the scsi speci?cations. ext extend sreq/sack filtering 1 lsi logic tolerant scsi receiver technology includes a special digital ?lter on the sreq/ and sack/ pins which causes the disregarding of glitches on deasserting edges. setting this bit increases the ?ltering period from 30 ns to 60 ns on the deasserting edge of the sreq/ and sack/ signals. note: never set this bit during fast scsi (greater than 5 megatransfers per second) operations, because a valid assertion could be treated as a glitch. low scsi low level mode 0 setting this bit places the lsi53c876 scsi function in low level mode. in this mode, no dma operations occur, and no scripts execute. arbitration and selection may be performed by setting the start sequence bit as described in the scsi control zero (scntl0) register. scsi bus transfers are performed by manually asserting and polling scsi signals. clearing this bit allows instructions to be executed in scsi scripts mode. note: it is not necessary to set this bit for access to the scsi bit-level registers ( scsi output data latch (sodl) , scsi bus control lines (sbcl) , and input registers).
4-92 registers register: 0x4f scsi test three (stest3) read/write te tolerant enable 7 setting this bit enables the active negation portion of lsi logic tolerant technology. active negation causes the scsi request, acknowledge, data, and parity signals to be actively deasserted, instead of relying on external pull-ups, when the lsi53c876 scsi function is driving these signals. active deassertion of these signals occurs only when the lsi53c876 scsi function is in an information transfer phase. when operating in a differential environment or at fast scsi timings, tolerant active negation should be enabled to improve setup and deassertion times. active negation is disabled after reset or when this bit is cleared. for more information on lsi logic tolerant technology, see chapter 1, general description. note: set this bit if the enable ultra scsi bit in scsi control three (scntl3) is set. str scsi fifo test read 6 setting this bit places the scsi core into a test mode in which the scsi fifo is easily read. reading the least signi?cant byte of the scsi output data latch (sodl) register causes the fifo to unload. the functions are summarized in the table below. 76543210 te str hsc dsi diff ttm csf stw 0000x000 register name register operation fifo bits fifo function sodl read [15:0] unload sodl0 read [7:0] unload sodl1 read [15:8] none
scsi registers 4-93 hsc halt scsi clock 5 asserting this bit causes the internal divided scsi clock to come to a stop in a glitchless manner. this bit is used for test purposes or to lower i dd during a power-down mode. dsi disable single initiator response 4 if this bit is set, the lsi53c876 scsi function ignores all bus-initiated selection attempts that employ the single initiator option from scsi-1. in order to select the lsi53c876 scsi function while this bit is set, the lsi53c876 scsi functions scsi id and the initiators scsi id must both be asserted. assert this bit in scsi-2 systems so that a single bit error on the scsi bus is not interpreted as a single initiator response. checkhi check high parity 3 if this bit is set, all devices in the scsi system implementation are assumed to be 16-bit. this causes the lsi53c876 to always check the parity bit for scsi ids [15:8] during bus-initiated selection or reselection, assuming parity checking has been enabled. if an 8-bit scsi device attempts to select the lsi53c876 while this bit is set, the chip ignores the selection attempt. this is because the parity bit for ids [15:8] is undriven. see the description of the enable parity checking bit in the scsi control zero (scntl0) register for more information. ttm timer test mode 2 asserting this bit facilitates testing of the selection time-out, general purpose, and handshake-to-handshake timers by greatly reducing all three time-out periods. setting this bit starts all three timers and if the respective bits in the scsi interrupt enable one (sien1) register are asserted, the lsi53c876 scsi function generates interrupts at time-out. this bit is intended for internal manufacturing diagnosis and should not be used. csf clear scsi fifo 1 setting this bit causes the full ?ags for the scsi fifo to be cleared. this empties the fifo. this bit is self-clearing. in addition to the scsi fifo pointers, the scsi input data latch (sidl) , scsi output data latch (sodl) , and sodr full bits in the scsi status zero (sstat0) and scsi status two (sstat2) are cleared.
4-94 registers stw scsi fifo test write 0 setting this bit places the scsi core into a test mode in which the fifo is easily read or written. while this bit is set, writes to the least signi?cant byte of the scsi output data latch (sodl) register cause the entire word contained in this register to be loaded into the fifo. writing the least signi?cant byte of the sodl register causes the fifo to load. these functions are summarized in the table below. register: 0x50C0x51 scsi input data latch (sidl) read only sidl scsi input data latch [15:0] this register is used primarily for diagnostic testing, programmed i/o operation, or error recovery. data received from the scsi bus can be read from this register. data can be written to the scsi output data latch (sodl) register and then read back into the lsi53c876 by reading this register to allow loopback testing. when receiving scsi data, the data ?ows into this register and out to the host fifo. this register differs from the scsi bus data lines (sbdl) register; sidl contains latched data and the sbdl always contains exactly what is currently on the scsi data bus. reading this register causes the scsi parity bit to be checked, and causes a parity error interrupt if the data is not valid. the power-up values are indeterminate. register name register operation fifo bits fifo function sodl write [15:0] unload sodl0 write [7:0] unload sodl1 write [15:8] none 15 0 sidl xxxxx x x x x xxx x xxx
scsi registers 4-95 registers: 0x54C0x55 scsi output data latch (sodl) read/write sodl scsi output data latch [15:0] this register is used primarily for diagnostic testing or programmed i/o operation. data written to this register is asserted onto the scsi data bus by setting the assert data bus bit in the scsi control one (scntl1) register. this register can send data using programmed i/o. data ?ows through this register when sending data in any mode. it is also used to write to the synchronous data fifo when testing the chip. the power-up value of this register is indeterminate. registers: 0x58C0x59 scsi bus data lines (sbdl) read only sbdl scsi bus data lines [15:0] this register contains the scsi data bus status. even though the scsi data bus is active low, these bits are active high. the signal status is not latched and is a true representation of exactly what is on the data bus at the time the register is read. this register is used when receiving data using programmed i/o. this register can also be used for diagnostic testing or in low level mode. the power-up value of this register is indeterminate. 15 0 sodl xxxxx x x x x xxx x xxx 15 0 sbdl xxxxx x x x x xxx x xxx
4-96 registers registers: 0x5cC0x5f scratch register b (scratchb) read/write scratchb scratch register b [31:0] this is a general purpose user de?nable scratch pad register. apart from cpu access, only register read/write and memory moves directed at the scratch register alter its contents. when bit 3 in the chip test two (ctest2) register is set, this register contains the base address for the 4 kbytes internal ram. setting chip test two (ctest2) , bit 3 only causes the base address to appear in the scratchb register; any information previously in the register remains intact. any writes to this register while the bit is set pass through to the actual scratch register b (scratchb) register. the power-up values are indeterminate. registers: 0x60C0x7f scratch registers cCj (scratchcCscratchj) read/write these registers are general purpose scratch registers for user-de?ned functions. they are accessible through read-modify-write functions. 31 0 scratchb xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
lsi53c876/876e pci to dual channel scsi multifunction controller 5-1 chapter 5 scsi scripts instruction set after power up and initialization, the lsi53c876 can be operated in the low level register interface mode or in the high level scsi scripts mode. chapter 5 is divided into the following sections: section 5.1, low level register interface mode section 5.2, high level scsi scripts mode section 5.3, block move instruction section 5.4, i/o instruction section 5.5, read/write instructions section 5.6, transfer control instructions section 5.7, memory move instructions section 5.8, load and store instructions 5.1 low level register interface mode with the low level register interface mode, the user has access to the dma control logic and the scsi bus control logic. an external processor has access to the scsi bus signals and the low level dma signals, which allows creation of complicated board level test algorithms. the low level interface is useful for backward compatibility with scsi devices that require certain unique timings or bus sequences to operate properly. another feature allowed at the low level is loopback testing. in loopback mode, the scsi core can be directed to talk to the dma core to test internal data paths all the way out to the chips pins.
5-2 scsi scripts instruction set 5.2 high level scsi scripts mode to operate in the scsi scripts mode, the lsi53c876 requires only a scripts start address. the start address must be at a dword (four byte) boundary. this aligns subsequent scripts at a dword boundary since all scripts are 8 or 12 bytes long. instructions are fetched until an interrupt instruction is encountered, or until an unexpected event (such as a hardware error) causes an interrupt to the external processor. once an interrupt is generated, the lsi53c876 halts all operations until the interrupt is serviced. then, the start address of the next scripts instruction is written to the dma scripts pointer (dsp) register to restart the automatic fetching and execution of instructions. the scsi scripts mode of execution allows the lsi53c876 to make decisions based on the status of the scsi bus, which of?oads the microprocessor from servicing the numerous interrupts inherent in i/o operations. given the rich set of scsi oriented features included in the instruction set, and the ability to re-enter the scsi algorithm at any point, this high level interface is all that is required for both normal and exception conditions. switching to low level mode for error recovery is not required. the following types of scripts instructions are implemented in the lsi53c876 as shown in table 5.1 :
high level scsi scripts mode 5-3 each instruction consists of two or three 32-bit words. the ?rst 32-bit word is always loaded into the dma command (dcmd) and dma byte counter (dbc) registers, the second into the dma scripts pointer save (dsps) register. the third word, used only by memory move instructions, is loaded into the temporary (temp) shadow register. in an indirect i/o or move instruction, the ?rst two 32-bit opcode fetches are followed by one or two more 32-bit fetch cycles. 5.2.1 sample operation the following example describes execution of a scripts block move instruction. the host cpu, through programmed i/o, gives the dma scripts pointer (dsp) register (in the operating register ?le) the starting address in main memory that points to a scsi scripts program for execution. loading the dma scripts pointer (dsp) register causes the lsi53c876 to fetch its ?rst instruction at the address just loaded. this fetch is from main memory or the internal ram, depending on the address. table 5.1 scripts instructions instruction description block move block move instruction moves data between the scsi bus and memory. i/o or read/write i/o or read/write instructions cause the lsi53c876 to trigger common scsi hardware sequences, or to move registers. transfer control transfer control instruction allows scripts instructions to make decisions based on real time scsi bus conditions. memory move memory move instruction causes the lsi53c876 to execute block moves between different parts of main memory. load and store load and store instructions provide a more ef?cient way to move data to/from memory from/to an internal register in the chip without using the memory move instruction.
5-4 scsi scripts instruction set the lsi53c876 typically fetches two dwords (64 bits) and decodes the high order byte of the ?rst dword as a scripts instruction. if the instruction is a block move, the lower three bytes of the ?rst dword are stored and interpreted as the number of bytes to move. the second dword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed. for a scsi send operation, the lsi53c876 waits until there is enough space in the dma fifo to transfer a programmable size block of data. for a scsi receive operation, it waits until enough data is collected in the dma fifo for transfer to memory. at this point, the lsi53c876 requests use of the pci bus again to transfer the data. when the lsi53c876 is granted the pci bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the pci bus. the lsi53c876 stays off the pci bus until the fifo can again hold (for a write) or has collected (for a read) enough data to repeat the process. the process repeats until the internally stored byte count has reached zero. the lsi53c876 releases the pci bus and then performs another scripts instruction fetch cycle, using the incremented stored address maintained in the dma scripts pointer (dsp) register. execution of scripts instructions continues until an error condition occurs or an interrupt scripts instruction is received. at this point, the lsi53c876 interrupts the host cpu and waits for further servicing by the host system. it can execute independent block move instructions specifying new byte counts and starting locations in main memory. in this manner, the lsi53c876 performs scatter/gather operations on data without requiring help from the host program, generating a host interrupt, or programming of an external dma controller. an overview of this process is presented in figure 5.1 .
high level scsi scripts mode 5-5 figure 5.1 scripts overview system processor system memory (or internal ram) scsi initiator write example select atn0, alt_addr move 1, identify_msg_buf, when msg_out move 6, cmd_buf, when cmd move 512, data_buf, when data_out move 1, stat_in_buf, when status move 1, msg_in_buf, when msg_in move scntl2 & 7f to scntl2 clear ack wait disconnect alt2 int 10 data structure message buffer command buffer data buffer status buffer lsi53c876 scsi bus write dsp fetch scripts data (data is not fetched across system bus if internal ram is enabled.) s y s t e m b u s
5-6 scsi scripts instruction set 5.3 block move instruction performing a block move instruction, bit 5, source i/o - memory enable (siom) and bit 4, destination i/o - memory enable (diom) in the dma mode (dmode) register determines whether the source/destination address resides in memory or i/o space. when data is moved onto the scsi bus, siom controls whether that data comes from i/o or memory space. when data is moved off of the scsi bus, diom controls whether that data goes to i/o or memory space. 5.3.1 first dword it[1:0] instruction type - block move [31:30] ia indirect addressing 29 when this bit is cleared, user data is moved to or from the 32-bit data start address for the block move instruction. the value is loaded into the chips address register and incremented as data is transferred. the address of the data to move is in the second dword of this instruction. when set, the 32-bit user data start address for the block move is the address of a pointer to the actual data buffer address. the value at the 32-bit start address is loaded into the chips dma next address (dnad) register using a third dword fetch (4-byte transfer across the host computer bus). direct addressing the byte count and absolute address are: indirect addressing use the fetched byte count, but fetch the data address from the address in the instruction. command byte count address of data command byte count address of pointer to data
block move instruction 5-7 once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. this indirect feature allows speci?cation of a table of data buffer addresses. using the scsi scripts compiler, the table offset is placed in the script at compile time. then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor. the logical i/o driver builds a structure of addresses for an i/o rather than treating each address individually. note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. tia table indirect 28 when this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the data structure address (dsa) register. both the transfer count and the source/ destination address are fetched from this location. use the signed integer offset in bits [23:0] of the second four bytes of the instruction, added to the value in the data structure address (dsa) register, to fetch ?rst the byte count and then the data address. the signed value is combined with the data structure base address to generate the physical address used to fetch values from the data structure. sign extended values of all ones for negative values are allowed, but bits [31:24] are ignored. note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. figure 5.2 illustrates the block move instruction register. command not used dont care table offset
5-8 scsi scripts instruction set figure 5.2 block move instruction register prior to the start of an i/o, load the data structure address (dsa) with the base address of the i/o data structure. any address on a long word boundary is allowed. after a table indirect opcode is fetched, the dsa is added to the 24-bit signed offset value from the opcode to generate the address of the required data; both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. for a move instruction, the 24-bit byte count is fetched from system memory. then the 32-bit physical address is brought into the lsi53c876. execution of the move begins at this point. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register 24-bit block move byte counter i/o c/d msg/ opcode table indirect addressing indirect addressing (lsi53c700 family compatible) 0 - instruction type - block move 0 - instruction type - block move
block move instruction 5-9 scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any dword boundary and may cross system segment boundaries. there are two restrictions on the placement of pointer data in system memory: the eight bytes of data in the move instruction must be contiguous, as shown below, and indirect data fetches are not available during execution of a memory-to-memory dma operation. opc opcode 27 this 1-bit ?eld de?nes the instruction to execute as a block move (move). target mode in target mode, the opcode bit defines the following operations: these instructions perform the following steps: 1. the lsi53c876 veri?es that it is connected to the scsi bus as a target before executing this instruction. 2. the lsi53c876 asserts the scsi phase signals (smsg/, sc_d/, and si_o/) as de?ned by the phase field bits in the instruction. 3. if the instruction is for the command phase, the lsi53c876 receives the ?rst command byte and decodes its scsi group code. 00 byte count physical data address opc instruction de?ned 0move 1 chmov
5-10 scsi scripts instruction set C if the scsi group code is either group 0, group 1, group 2, or group 5, then the lsi53c876 overwrites the dma byte counter (dbc) register with the length of the command descriptor block: 6, 10, or 12 bytes. C if the vendor unique enhancement 0 (vue0) bit ( scsi control two (scntl2) , bit 1) is set and the scsi group code is a vendor unique code, the lsi53c876 overwrites the dma byte counter (dbc) register with the length of the command descriptor block: 6, 10, or 12 bytes. if the vue0 bit is set, the lsi53c876 receives the number of bytes in the byte count regardless of the group code. C if any other group code is received, the dma byte counter (dbc) register is not modi?ed and the lsi53c876 requests the number of bytes speci?ed in the dma byte counter (dbc) register. if the dbc register contains 0x000000, an illegal instruction interrupt is generated. 4. the lsi53c876 transfers the number of bytes speci?ed in the dma byte counter (dbc) register starting at the address speci?ed in the dma next address (dnad) register. if the opcode bit is set and a data transfer ends on an odd byte boundary, the lsi53c876 stores the last byte in the scsi wide residue (swide) register during a receive operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer can be completed. 5. if the satn/ signal is asserted by the initiator or a parity error occurred during the transfer, the transfer can optionally be halted and an interrupt generated. the disable halt on parity error or atn bit in the scsi control one (scntl1) register controls whether the lsi53c825a halts on these conditions immediately, or waits until completion of the current move.
block move instruction 5-11 initiator mode in target mode, the opcode bit de?nes the following operations: these instructions perform the following steps: 1. the lsi53c876 veri?es that it is connected to the scsi bus as an initiator before executing this instruction. 2. the lsi53c876 waits for an unserviced phase to occur. an unserviced phase is any phase (with sreq/ asserted) for which the lsi53c876 has not yet transferred data by responding with a sack/. 3. the lsi53c876 compares the scsi phase bits in the dma command (dcmd) register with the latched scsi phase lines stored in the scsi status one (sstat1) register. these phase lines are latched when sreq/ is asserted. 4. if the scsi phase bits match the value stored in the scsi scsi status one (sstat1) register, the lsi53c876 transfers the number of bytes speci?ed in the dma byte counter (dbc) register starting at the address pointed to by the dma next address (dnad) register. if the opcode bit is cleared and a data transfer ends on an odd byte boundary, the lsi53c876 stores the last byte in the scsi wide residue (swide) register during a receive operation, or in the scsi output control latch (socl) register during a send operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer can complete. opc instruction de?ned 0 chmov 1move
5-12 scsi scripts instruction set 5. if the scsi phase bits do not match the value stored in the scsi status one (sstat1) register, the lsi53c876 generates a phase mismatch interrupt and the instruction is not executed. 6. during a message-out phase, after the lsi53c876 has performed a select with attention (or satn/ is manually asserted with a set atn instruction), the lsi53c876 deasserts satn/ during the ?nal sreq/sack/ handshake. 7. when the lsi53c876 is performing a block move for message-in phase, it does not deassert the sack/ signal for the last sreq/sack/ handshake. clear the sack/ signal using the clear sack i/o instruction. scsip[2:0] scsi phase [26:24] this 3-bit ?eld de?nes the desired scsi information transfer phase. when the lsi53c876 operates in initiator mode, these bits are compared with the latched scsi phase bits in the scsi status one (sstat1) register. when the lsi53c876 operates in target mode, it asserts the phase de?ned in this ?eld. the following table describes the possible combinations and the corresponding scsi phase. tc transfer counter [23:0] this 24-bit ?eld speci?es the number of data bytes to move between the lsi53c876 and system memory. the ?eld is stored in the dma byte counter (dbc) register. when the lsi53c876 transfers data to/from memory, the dbc register is decremented by the number of bytes msg c_d i_o scsi phase 0 0 0 data-out 0 0 1 data-in 0 1 0 command 0 1 1 status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in
i/o instruction 5-13 transferred. in addition, the dma next address (dnad) register is incremented by the number of bytes transferred. this process is repeated until the dma byte counter (dbc) register is decremented to zero. at this time, the lsi53c876 fetches the next instruction. if bit 28 is set, indicating table indirect addressing, this ?eld is not used. the byte count is instead fetched from a table pointed to by the data structure address (dsa) register. 5.3.2 second dword start address [31:0] this 32-bit ?eld speci?es the starting address of the data to move to/from memory. this ?eld is copied to the dma next address (dnad) register. when the lsi53c876 transfers data to or from memory, the dnad register is incremented by the number of bytes transferred. when bit 29 is set, indicating indirect addressing, this address is a pointer to an address in memory that points to the data location. when bit 28 is set, indicating table indirect addressing, the value in this ?eld is an offset into a table pointed to by the data structure address (dsa) . the table entry contains byte count and address information. 5.4 i/o instruction 5.4.1 first dword it[1:0] instruction type - i/o instruction [31:30] opc[2:0] opcode [29:27] the following opcode bits have different meanings, depending on whether the lsi53c876 is operating in initiator or target mode. opcode selections 101C111 are considered read/write instructions, and are described in section 5.5, read/write instructions.
5-14 scsi scripts instruction set target mode reselect instruction the lsi53c876 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. if the lsi53c876 wins arbitration, it attempts to reselect the scsi device whose id is de?ned in the destination id ?eld of the instruction. once the lsi53c876 wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move on to the next instruction before the reselection completes. it continues executing scripts until a script that requires a response from the initiator is encountered. if the lsi53c876 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the lsi53c876 to initiator mode if it is reselected, or to tar- get mode if it is selected. disconnect instruction the lsi53c876 disconnects from the scsi bus by deasserting all scsi signal outputs. wait select instruction if the lsi53c876 is selected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. opc2 opc1 opc0 instruction de?ned 0 0 0 reselect 0 0 1 disconnect 0 1 0 wait select 011 set 1 0 0 clear
i/o instruction 5-15 if reselected, the lsi53c876 fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the lsi53c876 to initiator mode when it is reselected. if the cpu sets the sigp bit in the scsi status zero (sstat0) register, the lsi53c876 aborts the wait select instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. do not set sack/ or satn/ except for testing purposes. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the arithmetic logic unit (alu) is set. note: none of the signals are set on the scsi bus in the target mode. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output con- trol latch (socl) register. do not set sack/ or satn/ except for testing purposes. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. note: none of the signals are cleared on the scsi bus in the target mode.
5-16 scsi scripts instruction set figure 5.3 i/o instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register r rr r set/clear atn/ set/clear ack/ set/clear target mode set/clear carry encoded destination id 0 encoded destination id 1 encoded destination id 2 encoded destination id 3 reserved reserved reserved reserved select with atn/ table indirect mode relative address mode opcode bit 0 opcode bit 1 opcode bit 2 1 - instruction type - i/o 0 - instruction type - i/o second 32-bit word of the i/o instruction 32-bit jump address
i/o instruction 5-17 initiator mode select instruction the lsi53c876 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. if the lsi53c876 wins arbitration, it attempts to select the scsi device whose id is de?ned in the destination id ?eld of the instruction. once the lsi53c876 wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move to the next instruction before the selection completes. it continues executing scripts until a script that requires a response from the target is encountered. if the lsi53c876 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the lsi53c876 to initiator mode if it is reselected, or to tar- get mode if it is selected. if the select with satn/ ?eld is set, the satn/ signal is asserted during the selection phase. wait disconnect instruction the lsi53c876 waits for the target to perform a legal disconnect from the scsi bus. a legal disconnect occurs when sbsy/ and ssel/ are inactive for a minimum of one bus free delay (400 ns), after the lsi53c876 receives a disconnect message or a command complete message. opc2 opc1 opc0 instruction de?ned 0 0 0 select 0 0 1 wait disconnect 0 1 0 wait reselect 0 1 1 set 1 0 0 clear
5-18 scsi scripts instruction set wait reselect instruction if the lsi53c876 is selected before being reselected, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the lsi53c876 to target mode when it is selected. if the lsi53c876 is reselected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. if the cpu sets the sigp bit in the interrupt status (istat) register, the lsi53c876 aborts the wait reselect instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are cleared, the corresponding bits in the scsi output control latch (socl) register are set. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the alu is set. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output con- trol latch (socl) register. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. ra relative addressing mode 26 when this bit is set, the 24-bit signed value in the dma next address (dnad) register is used as a relative displacement from the current dma scripts pointer (dsp) address. use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. the select and reselect instructions can contain an absolute alternate jump address or a relative transfer address. ti table indirect mode 25 when this bit is set, the 24-bit signed value in the dma byte counter (dbc) register is added to the value in the
i/o instruction 5-19 data structure address (dsa) register, and used as an offset relative to the value in the dsa register. the scsi control three (scntl3) value, scsi id, synchronous offset and synchronous period are loaded from this address. prior to the start of an i/o, load the data struc- ture address (dsa) with the base address of the i/o data structure. any address on a dword boundary is allowed. after a table indirect opcode is fetched, the data struc- ture address (dsa) is added to the 24-bit signed offset value from the opcode to generate the address of the required data. both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any dword boundary and may cross system segment boundaries. there are two restrictions on the placement of data in system memory: the i/o data structure must lie within the 8 mbytes above or below the base address. an i/o command structure must have all four bytes contiguous in system memory, as shown below. the offset/period bits are ordered as in the scsi transfer (sxfer) register. the con?guration bits are ordered as in the scsi control three (scntl3) register. use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. use bits 25 and 26 individually or in combination to produce the following conditions: con?g id offset/period 00 bit 25 bit 26 addressing mode 0 0 direct 0 1 table indirect 1 0 relative 1 1 table relative
5-20 scsi scripts instruction set direct uses the device id and physical address in the instruction. table indirect uses the physical jump address, but fetches data using the table indirect method. relative uses the device id in the instruction, but treats the alternate address as a relative jump. table relative treats the alternate jump address as a relative jump and fetches the device id, synchronous offset, and synchronous period indirectly. adds the value in bits [23:0] of the ?rst four bytes of the scripts instruction to the data structure base address to form the fetch address. sel select with atn/ 24 this bit speci?es whether satn/ is asserted during the selection phase when the lsi53c876 is executing a select instruction. when operating in initiator mode, set this bit for the select instruction. if this bit is set on any other i/o instruction, an illegal instruction interrupt is generated. command id not used not used absolute alternate address command table offset absolute alternate address command id not used not used absolute jump offset command table offset alternate jump offset
i/o instruction 5-21 r reserved [23:20] endid[3:0] encoded scsi destination id [19:16] this 4-bit ?eld speci?es the destination scsi id for an i/o instruction. r reserved [15:11] cc set/clear carry 10 this bit is used in conjunction with a set or clear instruction to set or clear the carry bit. setting this bit with a set instruction asserts the carry bit in the alu. setting this bit with a clear instruction deasserts the carry bit in the alu. tm set/clear target mode 9 this bit is used in conjunction with a set or clear instruction to set or clear target mode. setting this bit with a set instruction con?gures the lsi53c876 as a target device (this sets bit 0 of the scsi control zero (scntl0) register). clearing this bit with a clear instruction con?gures the lsi53c876 as an initiator device (this clears bit 0 of the scntl0 register). r reserved [8:7] ack set/clear sack/ 6 r reserved [5:4] atn set/clear satn/ 3 these two bits are used in conjunction with a set or clear instruction to assert or deassert the corresponding scsi control signal. bit 6 controls the scsi sack/ signal. bit 3 controls the scsi satn/ signal. setting either of these bits sets or resets the corresponding bit in the scsi output control latch (socl) register, depending on the instruction used. the set instruction is used to assert sack/ and/or satn/ on the scsi bus. the clear instruction is used to deassert sack/ and/or satn/ on the scsi bus. since sack/ and satn/ are initiator signals, they are not asserted on the scsi bus unless the lsi53c876 is operating as an initiator or the scsi loopback enable bit is set in the scsi test two (stest2) register.
5-22 scsi scripts instruction set the set/clear scsi ack/atn instruction is used after message phase block move operations to give the initiator the opportunity to assert attention before acknowledging the last message byte. for example, if the initiator wishes to reject a message, it issues an assert scsi atn instruction before a clear scsi ack instruction. r reserved [2:0] 5.4.2 second dword sa start address [31:0] this 32-bit ?eld contains the memory address to fetch the next instruction if the selection or reselection fails. if relative or table relative addressing is used, this value is a 24-bit signed offset relative to the current dma scripts pointer (dsp) register value. 5.5 read/write instructions the read/write instruction supports addition, subtraction, and comparison of two separate values within the chip. it performs the desired operation on the speci?ed register and the scsi first byte received (sfbr) register, then stores the result back to the speci?ed register or the sfbr. if the com bit ( dma control (dcntl) , bit 0) is cleared, read/write instruction cannot be used. 5.5.1 first dword instruction type - read/write instruction [31:30] the read/write instruction uses operator bits 26 through 24 in conjunction with the opcode bits to determine which instruction is currently selected. figure 5.4 illustrates the read/write instruction register.
read/write instructions 5-23 figure 5.4 read/write instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register a0 a1 a2 a3 a4 a5 a6 use data8/sfbr operator 0 operator 1 operator 2 opcode bit 0 opcode bit 1 opcode bit 2 1 - instruction type - r/w 0 - instruction type - r/w immediate data reserved (must be 0) register address
5-24 scsi scripts instruction set opc[2:0] opcode [29:27] the combinations of these bits determine if the instruction is a read/write or an i/o instruction. opcodes 0b000 through 0b100 are considered i/o instructions. o[2:0] operator [26:24] these bits are used in conjunction with the opcode bits to determine which instruction is currently selected. refer to table 5.2 for ?eld de?nitions. d8 use data 8/sfbr 23 when this bit is set, sfbr is used instead of the data8 value during a read-modify-write instruction (see table 5.2 ). this allows the user to add two register values. a[6:0] register address - a[6:0] [22:16] it is possible to change register values from scripts in read-modify-write cycles or move to/from sfbr cycles. a[6:0] selects an 8-bit source/destination register within the lsi53c876. immd immediate data [15:8] this 8-bit value is used as a second operand in logical and arithmetic functions. r reserved [7:0] 5.5.2 second dword destination address [31:0] this ?eld contains the 32-bit destination address where the data is to move. 5.5.3 read-modify-write cycles during these cycles the register is read, the selected operation is performed, and the result is written back to the source register. the add operation is used to increment or decrement register values (or memory values if used in conjunction with a memory-to-register move operation) for use as loop counters.
read/write instructions 5-25 subtraction is not available when scsi first byte received (sfbr) is used instead of data8 in the instruction syntax. to subtract one value from another when using sfbr, ?rst xor the value to subtract (subtrahend) with 0xff, and add 1 to the resulting value. this creates the 2s complement of the subtrahend. the two values are then added to obtain the difference. 5.5.4 move to/from sfbr cycles all operations are read-modify-writes. however, two registers are involved, one of which is always the scsi first byte received (sfbr) . table 5.2 shows the possible functions of this instruction. write one byte (value contained within the scripts instruction) into any chip register. move to/from the scsi first byte received (sfbr) from/to any other register. alter the value of a register with and, or, add, xor, shift left, or shift right operators. after moving values to the scsi first byte received (sfbr) , the compare and jump, call, or similar instructions are used to check the value. a move-to-sfbr followed by a move-from-sfbr is used to perform a register to register move. table 5.2 read/write instructions operator opcode 111 read-modify-write opcode 110 move to sfbr opcode 101 move from sfbr 000 move data into register. syntax: move data8 to rega move data into scsi first byte received (sfbr) register. syntax: move data8 to sfbr move data into register. syntax: move data8 to rega 001 1 shift register one bit to the left and place the result in the same register. syntax: move rega shl rega shift register one bit to the left and place the result in the scsi first byte received (sfbr) register. syntax: move rega shl sfbr shift the scsi first byte received (sfbr) register one bit to the left and place the result in the register. syntax: move sfbr shl rega
5-26 scsi scripts instruction set miscellaneous notes: ? substitute the desired register name or address for rega in the syntax examples. ? data8 indicates eight bits of data. ? use scsi first byte received (sfbr) instead of data8 to add two register values. 010 or data with register and place the result in the same register. syntax: move rega | data8 to rega or data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega | data8 to sfbr or data with sfbr and place the result in the register. syntax: move sfbr | data8 to rega 011 xor data with register and place the result in the same register. syntax: move rega xor data8 to rega xor data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega xor data8 to sfbr xor data with sfbr and place the result in the register. syntax: move sfbr xor data8 to rega 100 and data with register and place the result in the same register. syntax: move rega & data8 to rega and data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega & data8 to sfbr and data with sfbr and place the result in the register. syntax: move sfbr & data8 to rega 101 1 shift register one bit to the right and place the result in the same register. syntax: move rega shr rega shift register one bit to the right and place the result in the scsi first byte received (sfbr) register. syntax: move rega shr sfbr shift the scsi first byte received (sfbr) register one bit to the right and place the result in the register. syntax: move sfbr shr rega 110 add data to register without carry and place the result in the same register. syntax: move rega + data8 to rega add data to register without carry and place the result in the scsi first byte received (sfbr) register. syntax: move rega + data8 to sfbr add data to sfbr without carry and place the result in the register. syntax: move sfbr + data8 to rega 111 add data to register with carry and place the result in the same register. syntax: move rega + data8 to rega with carry add data to register with carry and place the result in the scsi first byte received (sfbr) register. syntax: move rega + data8 to sfbr with carry add data to sfbr with carry and place the result in the register. syntax: move sfbr + data8 to rega with carry 1. data is shifted through the carry bit and the carry bit is shifted into the data byte. table 5.2 read/write instructions (cont.) operator opcode 111 read-modify-write opcode 110 move to sfbr opcode 101 move from sfbr
transfer control instructions 5-27 5.6 transfer control instructions 5.6.1 first dword it[1:0] instruction type - transfer control instruction [31:30] opc[2:0] opcode [29:27] this 3-bit ?eld speci?es the type of transfer control instruction to execute. all transfer control instructions can be conditional. they can be dependent on a true/false comparison of the alu carry bit or a comparison of the scsi information transfer phase with the phase ?eld, and/or a comparison of the first byte received with the data compare ?eld. each instruction can operate in initiator or target mode. jump instruction the lsi53c876 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare and true/false bit ?elds. if the comparisons are true, then it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. the dsp register now contains the address of the next instruction. if the comparisons are false, the lsi53c876 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register, leaving the instruction pointer unchanged. opc2 opc1 opc0 instruction de?ned 000jump 0 0 1 call 0 1 0 return 0 1 1 interrupt 1 x x reserved
5-28 scsi scripts instruction set call instruction the lsi53c876 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register and that address value becomes the address of the next instruction. when the lsi53c876 executes a call instruction, the instruction pointer contained in the dma scripts pointer (dsp) register is stored in the temporary (temp) register. since the temp register is not a stack and can only hold one dword, nested call instructions are not allowed. if the comparisons are false, the lsi53c876 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register and the instruction pointer is not modi?ed.
transfer control instructions 5-29 figure 5.5 transfer control instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register wait for valid phase compare phase compare data jump if: true=1, false=0 interrupt on the fly carry test 0 (reserved) relative addressing mode i/o c/d msg opcode bit 0 opcode bit 1 opcode bit 2 1 - instruction type - transfer control 0 - instruction type - transfer control mask for compare data to be compared with the scsi first byte received
5-30 scsi scripts instruction set return instruction the lsi53c876 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. that address value becomes the address of the next instruction. when a return instruction is executed, the value stored in the temporary (temp) register is returned to the dma scripts pointer (dsp) register. the lsi53c876 does not check to see whether the call instruction has already been executed. it does not generate an interrupt if a return instruction is executed without previously executing a call instruction. if the comparisons are false, the lsi53c876 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register and the instruction pointer is not modi?ed. interrupt instructions the lsi53c876 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, the lsi53c876 generates an interrupt by asserting the irq/ signal. the 32-bit address ?eld stored in the dma scripts pointer save (dsps) register can contain a unique interrupt service vector. when servicing the interrupt, this unique status code allows the interrupt service routine to quickly identify the point at which the interrupt occurred. the lsi53c876 halts and the dma scripts pointer (dsp) register must be written to start any further operation. interrupt-on-the-fly instruction the lsi53c876 can do a true/false comparison of the alu carry bit or compare the phase and/or data as de?ned by the phase compare, data compare, and
transfer control instructions 5-31 true/false bit ?elds. if the comparisons are true, and the interrupt-on-the-fly bit ( interrupt status (istat) , bit 2) is set, the lsi53c876 asserts the interrupt-on-the-fly bit. scsip[2:0] scsi phase [26:24] this 3-bit ?eld corresponds to the three scsi bus phase signals which are compared with the phase lines latched when sreq/ is asserted. comparisons can be performed to determine the scsi phase actually being driven on the scsi bus. the following table describes the possible combinations and their corresponding scsi phase. these bits are only valid when the lsi53c876 is operating in initiator mode. clear these bits when the lsi53c876 is operating in the target mode. ra relative addressing mode 23 when this bit is set, the 24-bit signed value in the dma scripts pointer save (dsps) register is used as a relative offset from the current dma scripts pointer (dsp) address (which is pointing to the next instruction, not the one currently executing). the relative mode does not apply to return and interrupt scripts. jump/call an absolute address start execution at the new absolute address. msg c/d i/o scsi phase 0 0 0 data-out 0 0 1 data-in 0 1 0 command 0 1 1 status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in command condition codes absolute alternate address
5-32 scsi scripts instruction set jump/call a relative address start execution at the current address plus (or minus) the relative offset. the scripts program counter is a 32-bit value pointing to the scripts currently under execution by the lsi53c876. the next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the jump or call instruction. because it is signed (2s complement), the jump can be forward or backward. a relative transfer can be to any address within a 16 mbyte segment. the program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. scripts programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing scripts. for example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers. if a script is written using only relative transfers it does not require any run time alteration of physical addresses, and can be stored in and executed from a prom. ct carry test 21 when this bit is set, decisions based on the alu carry bit can be made. true/false comparisons are legal, but data compare and phase compare are illegal. if interrupt-on-the-fly 20 when this bit is set, the interrupt instruction does not halt the scripts processor. once the interrupt occurs, the interrupt-on-the-fly bit ( interrupt status (istat) , bit 2) is asserted. jmp jump if true/false 19 this bit determines whether the lsi53c876 branches when a comparison is true or when a comparison is false. this bit applies to phase compares, data compares, and carry tests. if both the phase compare and data command condition codes dont care alternate jump offset
transfer control instructions 5-33 compare bits are set, then both compares must be true to branch on a true condition. both compares must be false to branch on a false condition. cd compare data 18 when this bit is set, the ?rst byte received from the scsi data bus (contained in scsi first byte received (sfbr) register) is compared with the data to be compared field in the transfer control instruction. the wait for valid phase bit controls when this compare occurs. the jump if true/false bit determines the condition (true or false) to branch on. cp compare phase 17 when the lsi53c876 is in initiator mode, this bit controls phase compare operations. when this bit is set, the scsi phase signals (latched by sreq/) are compared to the phase field in the transfer control instruction. if they match, the comparison is true. the wait for valid phase bit controls when the compare occurs. when the lsi53c876 is operating in target mode this bit is set when it tests for an active scsi satn/ signal. wvp wait for valid phase 16 if the wait for valid phase bit is set, the lsi53c876 waits for a previously unserviced phase before comparing the scsi phase and data. if the wait for valid phase bit is cleared, the lsi53c876 compares the scsi phase and data immediately. dcm data compare mask [15:8] the data compare mask allows a script to test certain bits within a data byte. during the data compare, if any mask bits are set, the corresponding bit in the scsi first byte received (sfbr) data byte is ignored. for instance, a mask of 0b01111111 and data compare value of bit 19 result of compare action 0 false jump taken 0 true no jump 1 false no jump 1 true jump taken
5-34 scsi scripts instruction set 0b1xxxxxxx allows the scripts processor to determine whether or not the high order bit is set while ignoring the remaining bits. dcv data compare value [7:0] this 8-bit ?eld is the data compared against the scsi first byte received (sfbr) register. these bits are used in conjunction with the data compare mask field to test for a particular data value. if the com bit ( dma control (dcntl) , bit 0) is cleared, the value in the sfbr register may not be stable. in this case, do not use instructions using this data compare value. 5.6.2 second dword jump address [31:0] this 32-bit ?eld contains the address of the next instruction to fetch when a jump is taken. once the lsi53c876 fetches the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the dma scripts pointer (dsp) register and becomes the current instruction pointer. 5.7 memory move instructions for memory move instructions, bits 5 and 4 (siom and diom) in the dma mode (dmode) register determine whether the source or destination addresses reside in memory or i/o space. by setting these bits appropriately, data may be moved within memory space, within i/o space, or between the two address spaces. the memory move instruction is used to copy the speci?ed number of bytes from the source address to the destination address. allowing the lsi53c876 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current dma controllers. up to 16 mbytes may be transferred with one instruction. there are two restrictions:
memory move instructions 5-35 both the source and destination addresses must start with the same address alignment a[1:0]. if source and destination are not aligned, then an illegal instruction interrupt occurs. for the pci cache line size register setting to take effect, the source and destination must be the same distance from a cache line boundary. indirect addresses are not allowed. a burst of data is fetched from the source address, put into the dma fifo and then written out to the destination address. the move continues until the byte count decrements to zero, then another scripts is fetched from system memory. the dma scripts pointer save (dsps) and data structure address (dsa) registers are additional holding registers used during the memory move. however, the contents of the data structure address (dsa) register are preserved. it[2:0] instruction type C memory move [31:39] r reserved [28:25] these bits are reserved and must be zero. if any of these bits are set, an illegal instruction interrupt occurs. nf no flush 24 when this bit is set, the lsi53c876 performs a memory move without ?ushing the prefetch unit. when this bit is cleared, the memory move instruction automatically ?ushes the prefetch unit. use the no flush option if the source and destination are not within four instructions of the current memory move instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2, func- tional description. tc[23:0] transfer count [23:0] the number of bytes to transfer is stored in the lower 24 bits of the ?rst instruction word.
5-36 scsi scripts instruction set 5.7.1 read/write system memory from scripts by using the memory move instruction, single or multiple register values are transferred to or from system memory. because the lsi53c876 responds to addresses as de?ned in the base address register zero (i/o) or base address register one (memory) registers, it can be accessed during a memory move operation if the source or destination address decodes to within the chips register space. if this occurs, the register indicated by the lower seven bits of the address is taken as the data source or destination. in this way, register values are saved to system memory and later restored, and scripts can make decisions based on data values in system memory. the scsi first byte received (sfbr) is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. to load the sfbr with a byte stored in system memory, ?rst move the byte to an intermediate lsi53c876 register (for example, a scratch register), and then to the scsi first byte received (sfbr) . the same address alignment restrictions apply to register access operations as to normal memory-to-memory transfers. 5.7.2 second dword dsps register [31:0] these bits contain the source address of the memory move. 5.7.3 third dword temp register [31:0] these bits contain the destination address for the memory move. figure 5.6 illustrates the memory move instruction.
memory move instructions 5-37 figure 5.6 memory move instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register 24-bit memory move byte counter no flush 0 (reserved) 0 (reserved) 0 (reserved) 0 (reserved) 0 - instruction type - memory move 1 - instruction type - memory move 1 - instruction type - memory move 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 temp register
5-38 scsi scripts instruction set 5.8 load and store instructions the load and store instruction provides a more ef?cient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. the load and store instructions are represented by two dword opcodes. the ?rst dword contains the dma command (dcmd) and dma byte counter (dbc) register values. the second dword contains the dma scripts pointer save (dsps) value. this is either the actual memory location of where to load and store, or the offset from the data structure address (dsa) , depending on the value of bit 28 (dsa relative). a maximum of 4 bytes may be moved with these instructions. the register address and memory address must have the same byte alignment, and the count set such that it does not cross dword boundaries. the memory address may not map back to the chip, excluding ram and rom. if it does, a pci read/write cycle occurs (the data does not actually transfer to/from the chip), and the chip issues an interrupt (illegal instruction detected) immediately following. the siom and diom bits in the dma mode (dmode) register determine whether the destination or source address of the instruction is in memory space or i/o space, as illustrated in the following table. the load and store utilizes the pci commands for i/o read and i/o write to access the i/o space. bit a1 bit a0 number of bytes allowed to load and store 0 0 one, two, three or four 0 1 one, two, or three 1 0 one or two 1 1 one bit source destination siom (load) memory register diom (store) register memory
load and store instructions 5-39 5.8.1 first dword it[2:0] instruction type [31:29] these bits should be 0b111, indicating the load and store instruction. dsa dsa relative 28 when this bit is cleared, the value in the dma scripts pointer save (dsps) is the actual 32-bit memory address to perform the load and store to/from. when this bit is set, the chip determines the memory address to perform the load and store to/from by adding the 24 bit signed offset value in the dma scripts pointer save (dsps) to the data structure address (dsa) . r reserved [27:26] nf no flush (store instruction only) 25 when this bit is set, the lsi53c876 performs a store without ?ushing the prefetch unit. when this bit is cleared, the store instruction automatically ?ushes the prefetch unit. use no flush if the source and destination are not within four instructions of the current store instruction. this bit is has no effect on the load instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2, func- tional description. ls load and store 24 when this bit is set, the instruction is a load. when cleared, it is a store. r reserved 23 ra[6:0] register address [22:16] a[6:0] selects the register to load and store to/from within the lsi53c876. r reserved [15:3] bc byte count [2:0] this value is the number of bytes to load and store.
5-40 scsi scripts instruction set 5.8.2 second dword memory i/o address / dsa offset [31:0] this is the actual memory location of where to load and store, or the offset from the data structure address (dsa) register value. figure 5.7 illustrates the load and store instruction format.
load and store instructions 5-41 figure 5.7 load and store instruction format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register - memory/ i/o address/dsa offset dcmd register dbc register a0 a1 a2 a3 a4 a5 a6 0 (reserved) load/store no flush 0 - reserved 0 - reserved dsa relative 1 1 1 register address instruction type - load and store reserved (must be 0) byte count (number of bytes to load/store)
5-42 scsi scripts instruction set
lsi53c876/876e pci to dual channel scsi multifunction controller 6-1 chapter 6 electrical characteristics this section speci?es the lsi53c876 electrical and mechanical characteristics. it is divided into the following sections: section 6.1, dc characteristics section 6.2, 3.3 v pci dc characteristics section 6.3, tolerant technology electrical characteristics section 6.4, ac characteristics section 6.5, package diagrams 6.1 dc characteristics this section of the manual describes the lsi53c876 dc characteristics. table 6.1 through table 6.15 give current and voltage speci?cations. these characteristics apply whenever a vdd source of 5 v is supplied to the pins below.
6-2 electrical characteristics table 6.1 absolute maximum stress ratings symbol parameter min max unit test conditions t stg storage temperature - 55 150 cC v dd supply voltage - 0.5 7.0 v C v in input voltage v ss - 0.5 v dd +0.5 v C i lp 1 1. - 2v dc characteristics 6-3 table 6.3 scsi signalssd[15:0]/, sdp[1:0]/, sreq/, sack/ symbol parameter min max unit test conditions v ih input high voltage 1.9 v dd +0.5 v C v il input low voltage v ss - 0.5 1.0 v C v oh 1 1. tolerant active negation enabled. output high voltage 2.5 3.5 v 2.5 ma v ol output low voltage v ss 0.5 v 48 ma i oz 3-state leakage - 10 10 m aC table 6.4 scsi signalssmsg, si_o/, sc_d/, satn/, sbsy/, ssel/, srst/ symbol parameter min max unit test conditions v ih input high voltage 1.9 v dd +0.5 v C v il input low voltage v ss - 0.5 1.0 v C v ol output low voltage v ss 0.5 v 48 ma i oz 3-state leakage (srst/ only) - 10 - 500 10 - 50 m aC table 6.5 input signalsclk, sclk, gnt/, idsel, rst/, testin, diffsens symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v C v il input low voltage v ss - 0.5 0.8 v C i in input leakage - 10 10 m aC note: sclk and rst/ have 100 m a pull-ups that are enabled when testin is low. gnt/ and idsel have 25 m a pull-ups that are enabled when testin is low. testin has a 100 m a pull-up that is always enabled.
6-4 electrical characteristics table 6.6 capacitance symbol parameter min max unit test conditions c i input capacitance of input pads C 7 pf C c io input capacitance of i/o pads C 10 pf C table 6.7 output signalsinta/, intb/ symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v - 16 ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 200 - 50 m aC note: inta/ and intb/ have 100 m a pull-ups that are enabled when testin is low. inta/ and intb/ can be enabled with a register bit as an open drain output with an internal 100 m a pull-up. table 6.8 output signalssdir[15:0], sdirp0, sdirp1, bsydir, seldir, rstdir, tgs, igs, mas/[1:0], mce/, moe/_testout, mwe/ symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v - 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage - 10 10 m aC note: each of these output signals have a 100 m a pull-up that is enabled when testin is low.
dc characteristics 6-5 table 6.9 output signalreq/ symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v - 16 ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 10 10 m aC note: req/ has a 25 m a pull-up that is enabled when testin is low. table 6.10 output signalserr/ symbol parameter min max unit test conditions v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 10 10 m aC note: serr/ has a 25 m a pull-up that is enabled when testin is low. table 6.11 bidirectional signalsad[31:0], c_be/[3:0], frame/, irdy/, trdy/, devsel/, stop/, perr/, par symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v C v il input low voltage v ss - 0.5 0.8 v C v oh output high voltage 2.4 v dd v16ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 10 10 m aC note: all the signals in this table have 25 m a pull-ups that are enabled when testin is low.
6-6 electrical characteristics table 6.12 bidirectional signalsgpio0_fetch/, gpio1_master/, gpio2, gpio3, gpio4 symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v C v il input low voltage v ss - 0.5 0.8 v C v oh output high voltage 2.4 v dd v - 16 ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 200 50 m aC table 6.13 bidirectional signalsmad[7:0] symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v C v ih input high voltage - external memory pull-downs 3.85 v dd +0.5 v C v il input low voltage v ss - 0.5 0.8 v C v il input low voltage - external memory pull-downs v ss - 0.5 1.35 v C v oh output high voltage 2.4 v dd v - 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage - 200 50 m aC table 6.14 input signalstdi, tms, tck symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v C v il input low voltage v ss - 0.5 0.8 v C i in input leakage - 200 - 50 m aC
3.3 v pci dc characteristics 6-7 6.2 3.3 v pci dc characteristics table 6.16 through table 6.19 give current and voltage speci?cations. these characteristics apply whenever a vdd source of 3.3 v is supplied to the vdd-i pins of the lsi53c876. table 6.15 output signaltdo symbol parameter min max unit test conditions v oh output high voltage v dd - 0.5 v dd v - 4ma v ol output low voltage v ss 0.5 v 4 ma i oz 3-state leakage - 10 10 m aC table 6.16 bidirectional signalsad[31:0], c_be[3:0]/, frame/, irdy/, trdy/, devsel/, stop/, perr/, par symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd v dd +0.5 v C v il input low voltage - 0.5 0.3 v dd vC v oh output high voltage 0.9 v dd Cvi oh = - 0.5 ma v ol output low voltage C 0.1 v dd vi ol =1.5 ma i oz 3-state leakage - 10 10 m aC table 6.17 input signalsclk, gnt/, idsel, rst/, symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd v dd +0.5 v C v il input low voltage - 0.5 0.3 v dd vC i in input leakage - 10 10 m aC
6-8 electrical characteristics 6.3 tolerant technology electrical characteristics the lsi53c876 features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. table 6.20 provides electrical characteristics for se scsi signals. figure 6.1 through figure 6.5 provide reference information for testing scsi signals. note: tolerant applies only to the scsi bus. table 6.18 output signalsinta/, intb, req/ symbol parameter min max unit test conditions v oh output high voltage 0.9 v dd Cvi oh = - 0.5 ma v ol output low voltage C 0.1 v dd vi ol =1.5 ma i oz 3-state leakage - 10 10 m aC table 6.19 output signalserr/ symbol parameter min max unit test conditions v ol output low voltage C 0.1 v dd vi ol =1.5 ma i oz 3-state leakage - 10 10 m aC
tolerant technology electrical characteristics 6-9 table 6.20 tolerant technology electrical characteristics symbol parameter min max unit test conditions v oh 1 1. active negation outputs only: data, parity, sreq/, sack/. output high voltage 2.5 3.5 v i oh = 2.5 ma v ol output low voltage 0.1 0.5 v i ol =48ma v ih input high voltage 2.0 7.0 v C v il input low voltage - 0.5 0.8 v referenced to v ss v ik input clamp voltage - 0.66 - 0.77 v v dd = 4.75; i i = - 20 ma v th threshold, high to low 1.1 1.3 v C v tl threshold, low to high 1.5 1.7 v C v th Cv tl hysteresis 200 400 mv C i oh 1 output high current 2.5 24 ma v oh = 2.5 v i ol output low current 100 200 ma v ol = 0.5 v i osh 1 short-circuit output high current C 625 ma output driving low, pin shorted to v dd supply 2 2. single pin only; irreversible damage may occur if sustained for one second. i osl short-circuit output low current C 95 ma output driving high, pin shorted to v ss supply i lh input high leakage C 10 m a - 0.5 < v dd < 5.25 v pin = 2.7 v i ll input low leakage C - 10 m a - 0.5 < v dd < 5.25 v pin = 0.5 v r i input resistance 20 C m w scsi pins 3 3. scsi reset pin has 10 k w pull-up resistor. note: these values are guaranteed by periodic characterization; they are not 100% tested on every device. c p capacitance per pin C 10 pf pqfp t r 1 rise time, 10% to 90% 9.7 18.5 ns figure 6.1 t f fall time, 90% to 10% 5.2 14.7 ns figure 6.1 dv h /dt slew rate, low to high 0.15 0.49 v/ns figure 6.1 dv l /dt slew rate, high to low 0.19 0.67 v/ns figure 6.1 esd electrostatic discharge 2 C kv mil-std-883c; 3015-7 latch-up 150 C ma C filter delay 20 30 ns figure 6.2 extended ?lter delay 40 60 ns figure 6.2
6-10 electrical characteristics figure 6.1 rise and fall time test conditions figure 6.2 scsi input filtering figure 6.3 hysteresis of scsi receivers 2.5 v 47 w 20 pf + - req/ or ack/ input t 1 v th note: t 1 is the input ?ltering period. 1 receiving logic level 0 1.1 1.3 1.5 1.7 input voltage (volts)
tolerant technology electrical characteristics 6-11 figure 6.4 input current as a function of input voltage figure 6.5 output current as a function of output voltage +40 +20 0 - 20 - 40 - 4 0 4 8 12 16 - 0.7 v 8.2 v high-z output active input voltage (volts) input current (milliamperes) 14.4 v output sink current (milliamperes) - 800 - 600 - 400 - 200 0 012345 output voltage (volts) output source current (milliamperes) 20 40 60 80 100 012345 output voltage (volts) 0
6-12 electrical characteristics 6.4 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to section 6.1, dc characteristics ). chip timing is based on simulation at worst case voltage, temperature, and processing. this part of the chapter contains ac characteristics for the pci interface and the scsi interface. table 6.21 and figure 6.6 provide clock timing data. figure 6.6 clock timing table 6.21 clock timing symbol parameter min max unit t 1 bus clock cycle time 30 dc ns scsi clock cycle time (sclk) 1 1. this parameter must be met to ensure scsi timings are within speci?cation. 15 60 ns t 2 clk low time 2 2. duty cycle not to exceed 60/40. 11 C ns sclk low time 2 633ns t 3 clk high time 2 11 C ns sclk high time 2 633ns t 4 clk slew rate 1 C v/ns sclk slew rate 1 C ns clk, sclk t 1 t 3 t 4 t 2
ac characteristics 6-13 table 6.22 and figure 6.7 provide reset input timing data. figure 6.7 reset input table 6.22 reset input symbol parameter min max unit t 1 reset pulse width 10 C t clk t 2 reset deasserted setup to clk high 0 C ns t 3 mad setup time to clk high (for con?guring the mad bus only) 20 C ns t 4 mad hold time from clk high (for con?guring the mad bus only) 20 C ns t 1 t 2 t 3 t 4 clk rst/ mad* *when enabled valid data
6-14 electrical characteristics table 6.23 and figure 6.8 provide interrupt output timing data. figure 6.8 interrupt output table 6.23 interrupt output symbol parameter min max unit t 1 clk high to irq/ low 20 C ns t 2 clk high to irq/ high 40 C ns t 3 inta/, intb/ deassertion time 3 C clks t 1 t 2 t 3 inta/, intb/ clk
ac characteristics 6-15 6.4.1 pci and external memory interface timings figure 6.9 through figure 6.29 represent signal activity when the lsi53c876 accesses the pci bus. this section includes timing diagrams for access to three groups of external memory con?gurations. the ?rst group applies to systems with memory size of 128 kbytes and above; one byte read or write cycle, and fast or normal roms. the second group applies to systems with memory size of 128 kbytes and above, one byte read or write cycles, and slow roms. the third group applies to systems with memory size of 64 kbytes or less, one byte read or write cycles, and normal or fast rom. note: multiple byte access to the external memory bus increases the read or write cycle by 11 clocks for each additional byte. for your convenience, we have created one table with all the symbols and parameters for all the timing diagrams as well as included a table for each timing diagram. timing diagrams included in this section: con?guration register read con?guration register write target read (not from external memory) target write (not from external memory) target read, from external memory target write, from external memory opcode fetch, nonburst opcode fetch, burst back-to-back read back-to-back write burst read burst write read cycle, normal/fast memory ( 3 128 kbytes), single byte access write cycle, normal/fast memory ( 3 128 kbytes), single byte access
6-16 electrical characteristics read cycle, normal/fast memory ( 3 128 kbyte), multiple byte access write cycle, normal/fast memory ( 3 128 kbyte), multiple byte access read cycle, slow memory ( 3 128 kbytes) write cycle, slow memory ( 3 128 kbytes) read cycle, 16 kbytes rom write cycle, 16 kbytes rom 6.4.1.1 3.3 v pci timings note: when a 3.3 v source is applied to the v dd -i pins of the lsi53c876, some of the pci timing data in table 6.24 through table 6.35 will change. the 3.3 v pci timing data is listed in table 6.24 . table 6.24 3.3 v pci timing symbol parameter min max unit t 2 shared signal input hold time 1 C ns t 3 clk to shared signal output valid C 12 ns
ac characteristics 6-17 figure 6.9 con?guration register read table 6.25 con?guration register read symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 1 add in clk (driven by system) frame/ (driven by system) ad/ (driven by master-addr; lsi53c876-data) c_be/ (driven by master) pa r (driven by master-addr; lsi53c876-data) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) idsel (driven by master) devsel/ data out t 2 t 1 cmd t 2 t 1 t 2 byte enable t 2 t 1 t 3 out in t 2 t 2 t 1 t 3 t 3 t 3 t 1 t 2 t 3
6-18 electrical characteristics figure 6.10 con?guration register write table 6.26 con?guration register write symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 1 add in clk (driven by system) frame/ (driven by master) ad/ (driven by master) c_be/ (driven by master) par/ (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) idsel (driven by master) devsel/ data out t 2 t 1 cmd t 2 t 1 t 2 byte enable t 2 t 1 t 2 t 2 t 1 t 3 t 3 t 3 t 1 t 2 t 1 t 2
ac characteristics 6-19 figure 6.11 target read (not from external memory) table 6.27 target read (not from external memory) symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 1 add in clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) par/ irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ t 2 t 1 t 2 t 1 t 2 byte enable t 1 t 2 t 2 t 1 t 3 t 3 t 3 lsi53c876-data) (driven by master-addr; lsi53c876 data) cmd t 2 data out out t 3 in t 3
6-20 electrical characteristics figure 6.12 target write (not from external memory) table 6.28 target write (not from external memory) symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 1 add in clk (driven by system) frame/ (driven by master) ad/ (driven by master) c_be/ (driven by master) par/ irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ t 2 t 1 t 2 t 1 t 2 byte enable t 1 t 2 t 2 t 1 t 3 t 3 t 2 (driven by master) cmd t 2 data out t 3 t 3 t 2 t 1
ac characteristics 6-21 table 6.29 target read (from external memory) symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 160 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns
6-22 electrical characteristics figure 6.13 target read, from external memory t 1 clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ t 2 t 1 123456789 lsi53c876-data) par/ (driven by master-addr; lsi53c876-data) mad (addr driven by lsi53c876 data driven by memory) (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ add in t 1 t 2 in t 1 t 2 t 1 t 3 high order address middle order address t 11 t 12 t 13 10 cmd low order address byte enable
ac characteristics 6-23 figure 6.13 target read, from external memory (cont.) clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ 12 13 14 15 16 17 18 19 20 lsi53c876-data) par/ (driven by master-addr; lsi53c876-data) mad (addr driven by lsi53c876 data driven by memory) (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ byte enable t 3 t 2 t 3 data in t 15 21 11 t 3 data out out t 2 t 3 t 17 t 14 t 16 byte enable
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ac characteristics 6-25 table 6.30 target write (from external memory) symbol parameter 1 min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 75 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns 1. see note on page 6-16 regarding 3.3 v pci timing changes.
6-26 electrical characteristics figure 6.14 target write, from external memory t 1 clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ t 2 t 1 123456789 lsi53c876-data) par/ (driven by master-addr; lsi53c876-data) mad/ (driven by lsi53c876) (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ add in t 1 t 2 in t 1 t 2 t 1 t 3 high order address middle order address t 11 t 12 t 13 10 cmd low order address byte enable t 2 t 1 data in
ac characteristics 6-27 figure 6.14 target write, from external memory (cont.) clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ lsi53c876-data) par/ (driven by master-addr; lsi53c876-data) mad/ (driven by lsi53c876) (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ 12 13 14 15 16 17 18 19 20 byte enable t 1 t 2 t 3 data out 21 11 t 2 in t 2 t 24 byte enable data in t 2 t 3 t 21 t 26 t 23 t 20 t 25 t 22
6-28 electrical characteristics table 6.31 opcode fetch, nonburst symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 7 clk high to fetch/ low C 20 ns t 8 clk high to fetch/ high C 20 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
ac characteristics 6-29 figure 6.15 opcode fetch, nonburst clk (driven by system) gpio0_fetch/ (driven by lsi53c876) req/ (driven by lsi53c876) frame/ (driven by lsi53c876) ad/ (driven by lsi53c876 ) c_be/ (driven by lsi53c876 ) (driven by lsi53c876) par/ irdy/ (driven by lsi53c876) (driven by target) trdy/ gpio1_master/ (driven by lsi53c876) gnt/ (driven by arbiter) t 9 t 10 t 6 t 4 t 5 t 3 t 3 t 3 addr out data out addr out data out t 3 t 3 cmd be cmd be t 3 t 3 t 3 t 1 t 2
6-30 electrical characteristics table 6.32 opcode fetch, burst symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 7 clk high to fetch/ low C 20 ns t 8 clk high to fetch/ high C 20 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
ac characteristics 6-31 figure 6.16 opcode fetch, burst t 1 par/ (driven by lsi53c876- addr; target-data) clk (driven by system) gpio0_fetch/ (driven by lsi53c876) req/ (driven by lsi53c876) frame/ (driven by lsi53c876) ad/ (driven by lsi53c876- c_be/ (driven by lsi53c876) irdy/ (driven by lsi53c876) (driven by target) trdy/ gpio1_master/ (driven by lsi53c876) gnt/ (driven by arbiter) t 7 t 6 t 3 t 1 addr; target-data) (driven by target) stop/ (driven by target) devsel/ t 8 t 10 t 9 t 4 t 5 t 3 addr out cmd be in in t 3 t 3 t 2 data in t 3 out t 2 t 3 t 3 t 1 t 2 t 2 t 1 data in
6-32 electrical characteristics table 6.33 back-to-back read symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
ac characteristics 6-33 figure 6.17 back-to-back read par/ (driven by lsi53c876- addr; target-data) clk (driven by system) gpio0_fetch/ (driven by lsi53c876) req/ (driven by lsi53c876) frame/ (driven by lsi53c876) ad/ (driven by lsi53c876- c_be/ (driven by lsi53c876) irdy/ (driven by lsi53c876) (driven by target) trdy/ gpio1_master/ (driven by lsi53c876) gnt/ (driven by arbiter) t 6 t 1 addr; target-data) (driven by target) stop/ (driven by target) devsel/ t 10 t 9 t 5 in out t 2 t 1 data in t 4 t 3 addr out addr out t 3 cmd t 3 be cmd be data in in out t 3 t 1 t 2 t 3 t 2 t 1
6-34 electrical characteristics table 6.34 back-to-back write symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
ac characteristics 6-35 figure 6.18 back-to-back write par/ (driven by lsi53c876) clk (driven by system) gpio0_fetch/ (driven by lsi53c876) req/ (driven by lsi53c876) frame/ (driven by lsi53c876) ad/ (driven by lsi53c876) c_be/ (driven by lsi53c876) irdy/ (driven by lsi53c876) (driven by target) trdy/ gpio1_master/ (driven by lsi53c876) gnt/ (driven by arbiter) t 6 t 3 (driven by target) stop/ (driven by target) devsel/ t 10 t 9 t 1 t 5 addr out t 3 t 3 t 3 t 3 t 2 t 1 data out addr out data out cmd be t 3 t 3 cmd be t 2 t 3 t 4 t 3
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ac characteristics 6-37 table 6.35 burst read symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
6-38 electrical characteristics figure 6.19 burst read t 9 clk gpio0_fetch/ (driven by lsi53c876) req/ (driven by lsi53c876) frame/ (driven by lsi53c876) irdy (driven by lsi53c876) stop/ (driven by target) (driven by target) devsel/ 123456789 gpio1_master/ (driven by lsi53c876) gnt/ (driven by arbiter) ad/ (driven by lsi53c876- addr; target-data) c_be/ (driven by lsi53c876) par/ (driven by lsi53c876- addr; target-data) trdy (driven by target) t 10 t 8 t 4 t 3 addr out addr out t 3 cmd be cmd out in data in t 2 t 1 t 3 t 1 t 2 t 3 t 3 t 3 out
ac characteristics 6-39 figure 6.19 burst read (cont.) clk gpio0_fetch/ (driven by lsi53c876) req/ (driven by lsi53c876) frame/ (driven by lsi53c876) irdy/ (driven by lsi53c876) stop/ (driven by target) (driven by target) devsel/ 11 12 13 14 15 16 17 18 19 gpio1_master/ (driven by lsi53c876) gnt/ (driven by arbiter) ad/ (driven by lsi53c876- addr; target-data) c_be/ (driven by lsi53c876) par/ (driven by lsi53c876- addr; target-data) trdy/ (driven by target) addr out cmd be out in data in 10 data in be in in t 2 t 1
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ac characteristics 6-41 table 6.36 burst write symbol parameter 1 1. see note on page 6-16 regarding 3.3 v pci timing changes. min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
6-42 electrical characteristics figure 6.20 burst write t 5 t 9 clk gpio0_fetch/ (driven by lsi53c876) req/ (driven by lsi53c876) frame/ (driven by lsi53c876) irdy/ (driven by lsi53c876) stop/ (driven by target) (driven by target) devsel/ 123456 789 gpio1_master/ (driven by lsi53c876) gnt/ (driven by arbiter) ad/ (driven by lsi53c876) c_be/ (driven by lsi53c876) par/ (driven by lsi53c876) trdy/ (driven by target) t 10 t 8 t 3 addr out addr out t 3 t 3 t 3 (driven by system) t 4 data out data out t 3 t 3 be cmd be t 3 cmd t 3 t 3 t 3
ac characteristics 6-43 figure 6.20 burst write (cont.) clk gpio0_fetch/ (driven by lsi53c876) req/ (driven by lsi53c876) frame/ (driven by lsi53c876) irdy (driven by lsi53c876) stop/ (driven by target) (driven by target) devsel/ 11 12 13 14 15 16 17 18 gpio1_master/ (driven by lsi53c876) gnt/ (driven by arbiter) ad/ (driven by lsi53c876) c_be/ (driven by lsi53c876) par/ (driven by lsi53c876) trdy (driven by target) addr out (driven by system) data out data out be t 2 10 cmd be t 2
6-44 electrical characteristics figure 6.21 read cycle, normal/fast memory ( 3 128 kbytes), single byte access table 6.37 read cycle, norma/fast memory ( 3 128 kbytes), single byte access symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 160 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns clk t 19 t 12 mad/ (addr driven by (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ high order address middle address order address low order valid read data t 11 t 13 t 15 t 14 t 16 t 18 t 17 lsi53c876- data driven by memory)
ac characteristics 6-45 figure 6.22 write cycle, normal/fast memory ( 3 128 kbytes), single byte access table 6.38 write cycle, normal/fast memory ( 3 128 kbytes), single byte access symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 75 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns clk t 12 mad/ (driven by lsi53c876) (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ high order address middle address order address low order t 11 t 13 t 24 t 21 t 20 valid write data t 23 t 26 t 25 t 24
6-46 electrical characteristics figure 6.23 read cycle, normal/fast memory ( 3 128 kbyte), multiple byte access clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ lsi53c876-data) par/ (driven by master-addr; lsi53c876-data) mad/ (addr driven by lsi53c876; (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ addr in high order address 1234567 89 10 11 12 13 14 15 byte enable cmd middle order address low order address 16 in data driven by memory)
ac characteristics 6-47 figure 6.23 read cycle, normal/fast memory ( 3 128 kbyte), multiple byte access (cont.) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ lsi53c876-data) par/ (driven by master-addr; lsi53c876-data) mad/ (addr driven by lsi53c876; (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ data driven by memory) data in data byte enable low order address out data in out
6-48 electrical characteristics figure 6.24 write cycle, normal/fast memory ( 3 128 kbyte), multiple byte access clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ lsi53c876-data) par/ (driven by master-addr; lsi53c876-data) mad/ (driven by lsi53c876) (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ addr in high order address 1234567 89 10 11 12 13 14 15 byte enable cmd middle order address low order address 16 in data in data out
ac characteristics 6-49 figure 6.24 write cycle, normal/fast memory ( 3 128 kbyte), multiple byte access (cont.) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c876) stop/ (driven by lsi53c876) (driven by lsi53c876) devsel/ lsi53c876-data) par/ (driven by master-addr; lsi53c876-data) mad/ (driven by lsi53c876) (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ byte enable low order address in data in data out
6-50 electrical characteristics figure 6.25 read cycle, slow memory ( 3 128 kbytes) table 6.39 read cycle, slow memory ( 3 128 kbytes) symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 160 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns clk t 12 mad/ (addr driven by (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ high order address middle address order address low valid read data t 11 t 13 t 15 t 14 t 16 t 18 t 17 lsi53c876- data driven by memory) order t 19
ac characteristics 6-51 figure 6.26 write cycle, slow memory ( 3 128 kbytes) table 6.40 write cycle, slow memory ( 3 128 kbytes) symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 75 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns clk t 12 mad (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ high order address middle address order address low t 11 t 13 t 24 t 25 t 26 order (driven by lsi53c876) valid write data t 21 t 22 t 20 t 23
6-52 electrical characteristics figure 6.28 read cycle, 16 kbytes rom figure 6.27 read cycle, 16 kbytes rom symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 160 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns t 11 t 19 clk t 12 mad/ (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ high order address t 13 t 17 (addr driven by lsi53c876 valid read data data driven by memory) address low order t 15 t 14 t 16 t 18
ac characteristics 6-53 figure 6.29 write cycle, 16 kbytes rom table 6.41 write cycle, 16 kbytes rom symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 75 C ns t 24 mce/low to mwe/ high 120 C ns t 25 mce/low to mwe/ low 25 C ns t 26 mwe/high to mce/ high 25 C C clk t 12 mad (driven by lsi53c876) mas1/ (driven by lsi53c876) mas0/ (driven by lsi53c876) mce/ (driven by lsi53c876) mwe/ (driven by lsi53c876) moe/ high order address t 11 t 13 t 24 t 25 t 26 (driven by lsi53c876) valid write data t 21 t 20 low order address t 23 t 22
6-54 electrical characteristics 6.4.2 pci and external memory interface timing table 6.42 lists the pci and external memory interface timing data. table 6.42 lsi53c876 pci and external memory interface timing symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 7 clk high to fetch/ low C 20 ns t 8 clk high to fetch/ high C 20 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 160 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 75 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns
ac characteristics 6-55 6.4.3 scsi interface timing table 6.43 through table 6.49 and figure 6.30 through figure 6.34 describe the lsi53c876 scsi timing data. figure 6.30 initiator asynchronous send table 6.43 initiator asynchronous send symbol parameter min max unit t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sack/ asserted 55 C ns t 4 data hold from sreq/ deasserted 20 C ns sreq/ sack/ sd[15:0]/ sdp[1:0]/ t 1 t 2 t 3 t 4 n + 1 n valid n valid n + 1 n + 1
6-56 electrical characteristics figure 6.31 initiator asynchronous receive table 6.44 initiator asynchronous receive symbol parameter min max unit t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sreq/ asserted 0 C ns t 4 data hold from sack/ asserted 0 C ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ t 3 t 2 t 1 valid n valid n + 1 n + 1 n t 4 n + 1 n
ac characteristics 6-57 figure 6.32 target asynchronous send figure 6.33 target asynchronous receive table 6.45 target asynchronous send symbol parameter min max unit t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sreq/ asserted 55 C ns t 4 data hold from sack/ asserted 20 C ns table 6.46 target asynchronous receive symbol parameter min max unit t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sack/ asserted 0 C ns t 4 data hold from sreq/ deasserted 0 C ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ t 1 t 2 n + 1 valid n + 1 valid n n t 3 t 4 n n + 1 sreq/ sack/ sd[15:0]/, sdp[1:0]/ n n + 1 t 2 t 1 t 3 t 4 valid n valid n + 1 n + 1 n
6-58 electrical characteristics figure 6.34 initiator and target synchronous transfers table 6.47 scsi-1 transfers (se, 5.0 mbytes/s) symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 90 C ns t 2 send sreq/ or sack/ deassertion pulse width 90 C ns t 1 receive sreq/ or sack/ assertion pulse width 90 C ns t 2 receive sreq/ or sack/ deassertion pulse width 90 C ns t 3 send data setup to sreq/ or sack/ asserted 55 C ns t 4 send data hold from sreq/ or sack/ asserted 100 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 45 C ns sreq/ or sack/ send data sd[15:0]/, sdp[1:0]/ receive data sd[15:0]/, sdp[1:0]/ t 3 t 4 t 1 t 2 t 5 t 6 n n + 1 valid n valid n + 1 valid n valid n + 1
ac characteristics 6-59 table 6.48 scsi-2 fast transfers (10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 40 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 35 C ns t 2 send sreq/ or sack/ deassertion pulse width 35 C ns t 1 receive sreq/ or sack/ assertion pulse width 20 C ns t 2 receive sreq/ or sack/ deassertion pulse width 20 C ns t 3 send data setup to sreq/ or sack/ asserted 33 C ns t 4 send data hold from sreq/ or sack/ asserted 45 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 10 C ns table 6.49 scsi-2 fast-20 se transfers (20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), 80 mhz clock) with clock doubled internally symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 16 C ns t 2 send sreq/ or sack/ deassertion pulse width 16 C ns t 1 receive sreq/ or sack/ assertion pulse width 10 C ns t 2 receive sreq/ or sack/ deassertion pulse width 10 C ns t 3 send data setup to sreq/ or sack/ asserted 12 C ns t 4 send data hold from sreq/ or sack/ asserted 17 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 6 C ns
6-60 electrical characteristics 6.5 package diagrams figure 6.35 is the 256-pin pbga mechancial drawing and figure 6.36 is the 208-pin pqfp mechanical drawing for the lsi53c876.
package diagrams 6-61 figure 6.35 256-pin pbga (gu) mechanical drawing impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code gu.
6-62 electrical characteristics figure 6.36 208-pin pqfp (p9) mechanical drawing (sheet 1 of 2) impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code p9.
package diagrams 6-63 figure 6.36 208-pin pqfp (p9) mechanical drawing (sheet 2 of 2) impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code p9.
6-64 electrical characteristics
lsi53c876/876e pci to dual channel scsi multifunction controller a-1 appendix a register summary table a.1 lists the lsi53c876 con?guration registers by register name. table a.1 con?guration registers register name address read/write page base address register one (memory) 0x14 read/write 4-10 base address register two (memory) 0x18 read/write 4-10 base address register zero (i/o) 0x10 read/write 4-9 bist 0x0f read only 4-9 cache line size 0x0c read/write 4-7 capabilities pointer 0x34 read only 4-14 capability id 0x40 read only 4-16 class code 0x09 read only 4-7 command 0x04 read/write 4-3 data 0x47 read only 4-20 device id 0x02 read only 4-3 expansion rom base address 0x30 read/write 4-13 header type 0x0e read only 4-8 interrupt line 0x3c read/write 4-14 interrupt pin 0x3d read only 4-15 latency timer 0x0d read/write 4-8 max_lat 0x3f read only 4-16 min_gnt 0x3e read only 4-15
a-2 register summary table a.2 lists the lsi53c876 scsi registers by register name. next item pointer 0x41 read only 4-17 pmcsr bse 0x46 read only 4-19 power management capabilities 0x42 read only 4-17 power management control/status 0x44 read/write 4-18 revision id 0x08 read only 4-7 status 0x06 read/write 4-5 subsystem id 0x2e read only 4-12 subsystem vendor id 0x2c read only 4-11 vendor id 0x00 read only 4-3 table a.1 con?guration registers (cont.) register name address read/write page table a.2 scsi registers register name address read/write page adder sum output (adder) 0x3cC0x3f read only 4-72 chip test five (ctest5) 0x22 read/write 4-61 chip test four (ctest4) 0x21 read/write 4-59 chip test one (ctest1) 0x19 read only 4-54 chip test six (ctest6) 0x23 read/write 4-62 chip test three (ctest3) 0x1b read/write 4-56 chip test two (ctest2) 0x1a read only 4-54 chip test zero (ctest0) 0x18 read/write 4-53 data structure address (dsa) 0x10C0x13 read/write 4-49 dma byte counter (dbc) 0x24C0x26 read/write 4-63 dma command (dcmd) 0x27 read/write 4-64 dma control (dcntl) 0x3b read/write 4-70
register summary a-3 dma fifo (dfifo) 0x20 read/write 4-58 dma interrupt enable (dien) 0x39 read/write 4-69 dma mode (dmode) 0x38 read/write 4-66 dma next address (dnad) 0x28C0x2b read/write 4-64 dma scripts pointer (dsp) 0x2cC0x2f read/write 4-64 dma scripts pointer save (dsps) 0x30C0x33 read/write 4-65 dma status (dstat) 0x0c read only 4-42 general purpose (gpreg) 0x07 read/write 4-37 general purpose pin control (gpcntl) 0x47 read/write 4-82 interrupt status (istat) 0x14 read/write 4-50 memory access control (macntl) 0x46 read/write 4-82 response id one (respid1) 0x4b read/write 4-86 response id zero (respid0) 0x4a read/write 4-86 scratch byte register (sbr) 0x3a read/write 4-70 scratch register a (scratcha) 0x34 read/write 4-66 scratch register b (scratchb) 0x5cC0x5f read/write 4-96 scratch registers cCj (scratchcCscratchj) 0x60C0x7f read/write 4-96 scsi bus control lines (sbcl) 0x0b read only 4-41 scsi bus data lines (sbdl) 0x58C0x59 read only 4-95 scsi chip id (scid) 0x04 read/write 4-32 scsi control one (scntl1) 0x01 read/write 4-25 scsi control three (scntl3) 0x03 read/write 4-31 scsi control two (scntl2) 0x02 read/write 4-28 scsi control zero (scntl0) 0x00 read/write 4-22 scsi destination id (sdid) 0x06 read/write 4-36 table a.2 scsi registers (cont.) register name address read/write page
a-4 register summary scsi first byte received (sfbr) 0x08 read/write 4-38 scsi input data latch (sidl) 0x50C0x51 read only 4-94 scsi interrupt enable one (sien1) 0x41 read/write 4-75 scsi interrupt enable zero (sien0) 0x40 read/write 4-73 scsi interrupt status one (sist1) 0x43 read only 4-79 scsi interrupt status zero (sist0) 0x42 read only 4-76 scsi longitudinal parity (slpar) 0x44 read/write 4-80 scsi output control latch (socl) 0x09 read/write 4-39 scsi output data latch (sodl) 0x54C0x55 read/write 4-95 scsi selector id (ssid) 0x0a read only 4-40 scsi status one (sstat1) 0x0e read only 4-46 scsi status two (sstat2) 0x0f read only 4-48 scsi status zero (sstat0) 0x0d read only 4-44 scsi test one (stest1) 0x4d read/write 4-88 scsi test three (stest3) 0x4f read/write 4-92 scsi test two (stest2) 0x4e read/write 4-90 scsi test zero (stest0) 0x4c read only 4-87 scsi timer one (stime1) 0x49 read/write 4-85 scsi timer zero (stime0) 0x48 read/write 4-83 scsi transfer (sxfer) 0x05 read/write 4-33 scsi wide residue (swide) 0x45 read/write 4-81 temporary (temp) 0x1cC0x1f read/write 4-57 table a.2 scsi registers (cont.) register name address read/write page
lsi53c876/876e pci to dual channel scsi multifunction controller b-1 appendix b external memory interface diagram examples figure b.1 64 kbyte interface with 200 ns memory lsi53c876 27c128 moe/ oe mce/ ce d0 8 mad[7:0] bus d7 q0 8 a[7:0] q7 6 a[13:8] 6 v ss mas0/ mas1/ 8 notes: mad bus sense logic enabled for 16 kbytes of slow memory (200 ns device @ 33 mhz). mad[3:1] pulled low internally. hct374 d[7:0] mad3 4.7 k mad2 4.7 k mad1 4.7 k mad0 4.7 k ck 0e d0 d5 q0 q5 hct374 ck 0e
b-2 external memory interface diagram examples figure b.2 64 kbyte interface with 150 ns memory lsi53c876 27c512-15/ moe/ oe mce/ ce 8 mad[7:0] bus 8 a[7:0] 8 a[15:8] 8 v ss mas0/ mas1/ 8 notes: mad bus sense logic enabled for 64 kbytes of fast memory (150 ns device @ 33 mhz). mad3, mad1, and mad0 pulled low internally. gpio4 mwe/ v pp control + 12 v v pp we optional - for flash memory only, not required for eeproms. 28f512-15/ socket d[7:0] mad3 4.7 k mad1 4.7 k d0 d7 q0 q7 hct374 ck 0e d0 d7 q0 q7 hct374 ck 0e
external memory interface diagram examples b-3 figure b.3 256 kbyte interface with 150 ns memory lsi53c876 27c020-15/ moe/ oe mce/ ce 8 mad[7:0] bus 8 a[7:0] 8 a[15:8] 8 mas0/ mas1/ 8 notes: mad bus sense logic enabled for 256 kbytes of fast memory (150 ns device @ 33 mhz). mad[2:0] pulled low internally. the hct374s may be replaced with hct377s. gpio4 mwe/ v pp control + 12 v v pp we optional - for flash memory only, not required for eeproms. 28f020-15/ socket d[7:0] 4 4 a[17:16] v ss mad2 4.7 k mad1 4.7 k d0 d7 q0 q7 hct374 ck 0e d0 d7 q0 q7 hct374 ck 0e d0 d3 q0 q3 hct377 ck 0e mad[3:0] bus
b-4 external memory interface diagram examples figure b.4 512 kbyte interface with 150 ns memory lsi53c876 moe/ 8 mad[7:0] bus 8 a[7:0] 8 a[15:8] 8 v ss mas0/ mas1/ 8 note: mad bus sense logic enabled for 512 kbytes of slow memory (150 ns device, additional time required for hct139 @ 33 mhz). mad2 pulled low internally. the hct374s may be replaced with hct377s. gpio4 mwe/ v pp control + 12 v v pp optional - for flash memory only, not required for eeproms. d[7:0] mad0 4.7 k 3 mad2 4.7 k oe d0 a0 a16 oe d0 a0 a16 oe d0 a0 a16 oe d0 a0 a16 a b gb y0 y1 y2 y3 mce/ hct139 ce ce ce ce 27c010-15/28f010-15 sockets d0 d7 q0 q7 hct374 ck 0e d0 d7 q0 q7 hct374 ck 0e d0 d2 q0 q2 hct377 ck 0e mad[2:0] bus a16 d7 d7 d7 d7 a17 a18
lsi53c876/876e pci to dual channel scsi multifunction controller ix-1 index symbols (ad[31:0]) 3-7 (baro[31:0]) 4-10 (bart[31:0]) 4-10 (barz[31:0]) 4-9 (bse[7:0]) 4-19 (ccf[2:0]) 2-30 (cid[7:0]) 4-16 (cls[7:0]) 4-7 (cp[7:0]) 4-14 (data[7:0]) 4-20 (erba[31:0]) 4-13 (ht[7:0]) 4-8 (il[7:0]) 4-14 (ip[7:0]) 4-15 (lt[7:0]) 4-8 (mad[7:0]) 3-18 (mg[7:0]) 4-15 (ml[7:0]) 4-16 (nip[7:0]) 4-17 (sid[15:0]) 4-12 numerics 3.3/5 v pci interface 2-11 , 2-17 3-state 3-5 40 mhz clock doubler 2-31 a abort operation bit 4-50 aborted bit 4-43 , 4-69 ac characteristics 6-12 pci and external memory interface timing 6-15 scsi interface timing 6-55 active negation see tolerant technology active termination 2-28 adder register 4-72 adder sum output register 4-72 address/data bus 2-3 address/data signals 3-7 alignment 2-11 always wide scsi bit 4-91 arbitration arbitration in progress bit 4-45 arbitration mode bits 4-22 full arbitration 4-22 immediate arbitration bit 4-26 lost arbitration bit 4-45 simple arbitration 4-22 won arbitration bit 4-45 arbitration in progress bit 4-45 arbitration mode bits 4-22 arbitration pins 3-9 arbitration priority encoder test bit 4-87 aspi 1-3 assert even scsi parity bit 4-26 assert satn/ on parity error bit 4-24 assert scsi ack/ signal bit 4-39 assert scsi atn/ signal bit 4-39 assert scsi bsy/ signal bit 4-39 assert scsi c_d/ signal bit 4-39 assert scsi data bus bit 4-25 assert scsi i_o signal bit 4-39 assert scsi msg/ signal bit 4-39 assert scsi req/ signal bit 4-39 assert scsi rst/ signal bit 4-26 assert scsi sel/ signal bit 4-39 asynchronous scsi receive 2-22 asynchronous scsi send 2-21 autoconfiguration disable 3-21 b base address register one (baro[31:0]) 4-10 two (bart[31:0]) 4-10 zero - i/o (barz[31:0]) 4-9 base address register one 2-4 bidirectional 3-5 big and little endian support 2-17 bios 2-3 bios rom 1-1 block move instructions 5-6 bridge support extensions (bse[7:0]) 4-19 bsydir 3-16 burst disable bit 4-59 burst length bits 4-62 , 4-66 burst opcode fetch enable bit 4-68 burst size selection 2-7 bus command and byte enables 3-7 bus fault bit 4-42 , 4-69 byte empty in dma fifo bit 4-54 byte full in dma fifo bit 4-54 byte offset counter bits 4-58 , 4-62 c c_be/[3:0] 2-3 , 3-7 cache line size (cls[7:0]) 4-7
ix-2 index cache line size enable bit 4-70 cache mode, see pci cache mode 2-11 cap_id (cid[7:0]) 4-16 capabilities pointer (cp[7:0]) 4-14 chained block move scripts instruction 2-42 chained block moves 2-40 sodl register 2-42 swide register 2-41 wide scsi receive bit 2-41 wide scsi send bit 2-41 chained mode bit 4-28 chip revision level bits 4-56 chip test five register 4-61 chip test four register 4-59 chip test one register 4-54 chip test six register 4-62 chip test two register 4-54 chip test zero register 4-53 chip type bits 4-82 chmov 2-40 clear dma fifo 2-38 clear dma fifo bit 4-56 clear scsi fifo bit 4-93 clf 2-38 clk 3-6 clock 3-6 clock address incrementor bit 4-61 clock byte counter bit 4-61 clock conversion factor 2-31 clock conversion factor bits 4-32 clse 2-7 , 2-8 cmp 2-35 configuration read command 2-6 configuration registers base address one (memory) 4-10 base address two (memory) 4-10 base address zero (i/o) 4-9 bist 4-9 cache line size 4-7 capabilities pointer 4-14 capability id 4-16 class code 4-7 command 4-3 data 4-20 device id 4-3 expansion rom base address 4-13 header type 4-8 interrupt line 4-14 interrupt pin 4-15 latency timer 4-8 max_lat 4-16 min_gnt 4-15 next item pointer 4-17 power management capabilities 4-17 power management control/status 4-17 , 4-18 revision id 4-7 status 4-5 subsystem id 4-12 subsystem vendor id 4-11 vendor id 4-3 configuration space 2-3 configuration write command 2-6 configured as i/o bit 4-55 configured as memory bit 4-55 connected bit 4-26 , 4-51 conventions 1-7 csf 2-38 ctest0 register 4-53 ctest1 register 4-54 ctest2 register 4-54 ctest4 register 4-59 ctest5 register 4-61 ctest6 register 4-62 cycle frame 3-8 d data (data[7:0]) 4-20 data acknowledge status bit 4-56 data path 2-21 data request status bit 4-55 data structure address register 4-49 data transfer direction bit 4-54 data-in 2-42 , 2-43 data-out 2-42 , 2-43 dbc register 4-63 dcmd register 4-64 dcntl 2-35 dcntl register 4-70 designing a wide ultra scsi system 2-32 destination i/o-memory enable bit 4-67 determining the data transfer rate 2-30 device select 3-8 devsel/ 3-8 dfifo register 4-58 dien 2-35 , 2-36 dien register 4-69 differential mode operation 2-24 diffsens 3-16 , 3-17 diffsens scsi signal 6-3 dip 2-34 , 2-37 , 2-38 , 2-39 disable halt on parity error or atn 4-25 disable single initiator response bit 4-93 dma byte counter register 4-63 dma command register 4-64 dma control register 4-70 dma core 1-3 dma direction bit 4-61 dma fifo 2-9 , 2-20 , 2-34 dma fifo bits 4-62 dma fifo empty bit 4-42 dma fifo register 4-58 dma interrupt enable register 4-69 dma interrupt pending bit 4-53 dma interrupts 2-35 , 2-36 , 2-38 dma mode register 4-66 dma next address register 4-64 dma scripts pointer register 4-64 dma scripts pointer save register 4-65 dma status register 4-42 dmode register 4-66 dnad register 4-64 dsa register 4-49 dsp register 4-64 dsps register 4-65 dstat 2-34 dstat register 4-42 dual address cycles command 2-7
index ix-3 e electrical characteristics ac characteristics 6-12 dc characteristics 3.3 volt pci 6-7 tolerant technology 6-8 enable parity checking 2-17 enable parity checking bit 4-24 enable read line bit 4-68 enable read multiple bit 4-68 enable response to reselection bit 4-32 enable response to selection bit 4-33 enable wide scsi bit 4-31 encoded chip scsi id 4-33 encoded destination scsi id bit 4-40 encoded destination scsi id bits 4-36 eproms 1-1 error recording signals 3-9 even parity 2-17 expanded register move 1-6 expansion rom base address 4-13 expansion rom base address register 2-45 extend sreq/sack filtering bit 4-91 external memory configurations 6-15 external memory interface 2-44 configuration 2-44 gpio4 bit 4-37 slow memory 2-45 extra clock cycle of data setup bit 4-25 f fetch enable 4-82 fetch pin mode bit 4-57 fifo byte control bits 4-60 fifo flags bits 4-46 , 4-49 flush dma fifo bit 4-56 frame/ 3-8 function complete 2-35 function complete bit 4-73 , 4-77 g general purpose i/o pin 0 3-11 , 3-12 general purpose i/o pin 1 3-11 , 3-12 general purpose i/o pin 2 3-11 general purpose i/o pin 3 3-11 , 3-12 general purpose i/o pin 4 3-11 , 3-12 general purpose pin control register 4-82 general purpose register 4-37 general purpose timer expired bit 4-76 , 4-79 general purpose timer period bits 4-85 general purpose timer scale factor bit 4-85 gnt/ 3-9 gpcntl register 4-82 gpi00_ fetch/ 3-11 , 3-12 gpio enable bit 4-83 gpio interface signals 3-11 gpio[4:0] bits 4-37 gpio1_ master/ 3-11 , 3-12 gpio2 3-11 , 3-12 gpio3 3-11 , 3-12 gpio4 3-11 , 3-12 gpreg register 4-37 grant 3-9 h halt scsi clock bit 4-93 handshake-to-handshake timer bus activity enable bit 4-85 handshake-to-handshake timer expired bit 4-76 , 4-79 handshake-to-handshake timer period bit 4-83 hardware interrupts 2-33 header type (ht[7:0]) 4-8 high impedance mode bit 4-59 i i/o instructions 5-13 i/o read command 2-5 i/o space 2-3 , 2-4 i/o write command 2-5 idsel 2-3 , 3-8 idsel signal 2-6 igs 3-16 , 3-17 illegal instruction detected bit 4-43 immediate arbitration bit 4-26 initialization device select 3-8 initiator ready 3-8 input 3-5 instruction prefetching 2-14 prefetch enable bit 4-70 prefetch flush bit 4-70 prefetch unit flushing 2-15 instructions block move 5-6 i/o 5-13 load and store 5-38 memory move 5-34 read/write 5-22 transfer control 5-27 inta routing enable 3-21 inta/ 2-33 , 3-10 , 3-21 inta/ pin 2-36 , 2-39 intb/ 3-10 , 3-21 integration 1-7 interface control pins 3-8 internal arbiter 2-10 internal ram, see also scripts ram 2-14 internal scripts ram 2-14 interrupt line 4-14 pin (ip[7:0]) 4-15 interrupt a 3-10 interrupt b 3-10 interrupt request 2-33 interrupt status register 4-50 interrupt-on-the-fly bit 4-52 interrupts 2-33 , 2-35 fatal vs. nonfatal interrupts 2-35 halting 2-38 irq disable bit 2-35 masking 2-36 sample interrupt service routine 2-39 stacked interrupts 2-37 irdy/ 3-8 irq disable bit 4-71 istat 2-34 istat register 4-50
ix-4 index j jtag boundary scan testing 2-16 l last disconnect bit 4-49 latched scsi parity bit 4-47 latched scsi parity for sd[15:8] bit 4-49 latency 2-10 timer (lt[7:0]) 4-8 load and store instructions 5-38 no flush option 5-39 prefetch unit and store instructions 2-15 , 5-39 load and store scripts 1-6 load/store instructions 2-16 lost arbitration bit 4-45 lsi53c700 family compatibility bit 4-72 lsi53c876 benefits 1-5 m macntl register 4-82 mad bus 2-44 mad bus programming 3-21 mad[3:1] 3-22 mad pins 2-44 mad[7:0] pins 3-21 manual start mode bit 4-68 mas0/ 3-18 mas1/ 3-18 masking 2-36 master control for set or reset pulses bit 4-61 master data parity error bit 4-42 , 4-69 master enable bit 4-82 master parity error enable bit 4-60 max scsi synchronous offset bits 4-35 max_lat (ml[7:0]) 4-16 mce/ 3-19 memory access control register 4-82 memory address strobe 0 3-18 memory address strobe 1 3-18 memory address/data bus 3-18 memory chip enable 3-19 memory move instruction 2-12 memory move instructions 5-34 and scripts instruction prefetching 2-15 no flush option 2-15 memory move misalignment 2-12 memory output enable 3-19 memory read command 2-6 memory read line command 2-7 memory read multiple command 2-6 memory space 2-3 , 2-4 memory write and invalidate command 2-9 memory write command 2-6 memory write enable 3-19 min_gnt (mg[7:0]) 4-15 moe_testout 3-19 multiple cache line transfers 2-9 multithreaded i/o 1-6 mwe/ 3-19 n next_item_ptr (nip[7:0]) 4-17 no flush memory move instruction 5-35 o objectives of dma architecture 2-43 opcode fetch burst capability 2-15 opcode fetch bursting 2-15 operating registers adder sum output 4-72 chip test five 4-61 chip test four 4-59 chip test one 4-54 chip test six 4-62 chip test three 4-56 chip test two 4-54 chip test zero 4-53 data structure address 4-49 dma byte counter 4-63 dma command 4-64 dma control 4-70 dma fifo 4-58 dma interrupt enable 4-69 dma mode 4-66 dma next address 4-64 dma scripts pointer 4-64 dma scripts pointer save 4-65 dma status 4-42 general purpose 4-37 general purpose pin control 4-82 interrupt status 4-50 memory access control 4-82 response id one 4-86 response id zero 4-86 scratch register a 4-66 scratch register b 4-96 scsi bus control lines 4-41 scsi bus data lines 4-95 scsi chip id 4-32 scsi control one register 4-25 scsi control register two 4-28 scsi control three 4-31 scsi control zero 4-22 scsi destination id 4-36 scsi first byte received 4-38 scsi input data latch 4-94 scsi interrupt enable one 4-75 scsi interrupt enable zero 4-73 scsi interrupt status one 4-79 scsi interrupt status zero 4-76 scsi longitudinal parity 4-80 scsi output control latch 4-39 scsi output data latch 4-95 scsi selector id 4-40 scsi status one 4-46 scsi status two 4-48 scsi status zero 4-44 scsi test one 4-88 scsi test three 4-92 scsi test two 4-90 scsi test zero 4-87 scsi timer one 4-85 scsi timer zero 4-83 scsi transfer 4-33
index ix-5 operating registers (cont.) scsi wide residue 4-81 temporary stack 4-57 p par 3-7 parallel rom interface 2-43 parity 2-17 , 3-7 parity error 3-9 parity error bit 4-78 pci addressing 2-3 pci and external memory interface timings 6-15 symbols and parameters 6-54 pci bus commands and functions supported 2-4 pci cache line size register 2-9 pci cache mode 2-11 cache line size enable bit 4-70 enable read multiple bit 4-68 write and invalidate enable bit 4-57 pci commands 2-4 pci configuration registers 4-1 pci functional description 2-3 pci i/o space 2-4 pci interface pins 3-8 pci interface signals 3-6 pci interrupt signals 3-10 pci memory space 2-4 pci performance 1-5 pci target disconnect 2-10 pci target retry 2-10 perr/ 3-9 phase mismatch bit 4-77 physical dword address and data 3-7 polling 2-33 power management 2-48 isolated power supplies 2-50 power state d0 2-49 power state d1 2-49 power state d2 2-49 power state d3 2-50 register 0x40, capability id 4-16 register 0x41, next item pointer 4-17 register 0x42, power management capabilities 4-17 register 0x44, control/status 4-18 register 0x46, pmcsr bse 4-19 register 0x47, data 4-20 prefetch enable bit 4-70 prefetch flush bit 4-70 r ram, see also scripts ram 2-14 read line mode 2-7 read multiple with read line enabled 2-8 read/write instructions 5-22 register addresses operating registers 0x01 4-25 0x02 4-28 0x03 4-31 0x04 4-32 0x05 4-33 0x06 4-36 0x07 4-37 0x08 4-38 0x09 4-39 0x0a 4-40 0x0b 4-41 0x0c 4-42 0x0d 4-44 0x0e 4-46 0x0f 4-48 0x10C0x13 4-49 0x14 4-50 0x18 4-53 0x19 4-54 0x1a 4-54 0x1b 4-56 0x1cC0x1f 4-57 0x20 4-58 0x21 4-59 0x22 4-61 0x23 4-62 0x24C0x26 4-63 0x27 4-64 0x28C0x2b 4-64 0x2cC0x2f 4-64 0x30C0x33 4-65 0x34C0x37 4-66 0x38 4-66 0x39 4-69 0x3a 4-70 0x3b 4-70 0x3cC0x3f 4-72 0x40 4-73 0x41 4-75 0x42 4-76 0x43 4-79 0x44 4-80 0x45 4-81 0x46 4-82 0x47 4-82 0x48 4-83 0x49 4-85 0x4a 4-86 0x4b 4-86 0x4c 4-87 0x4d 4-88 0x4e 4-90 0x4f 4-92 0x50C0x51 4-94 0x54C0x55 4-95 0x58C0x59 4-95 0x5cC0x5f 4-96 0x60C0x70 4-96 register bits abort operation 4-50 aborted 4-43 , 4-69 always wide scsi 4-91 arbitration in progress 4-45 arbitration mode 4-22 arbitration priority encoder test 4-87 assert even scsi parity (force bad parity)) 4-26 assert satn/ on parity error 4-24 assert scsi ack/ signal 4-39 assert scsi atn/ signal 4-39 assert scsi bsy/ signal 4-39 assert scsi c_d/ signal 4-39 assert scsi data bus 4-25 assert scsi i_o/ signal 4-39 assert scsi msg/ signal 4-39
ix-6 index register bits (cont.) assert scsi req/ signal 4-39 assert scsi rst/ signal 4-26 assert scsi sel/ signal 4-39 burst disable 4-59 burst length 4-62 , 4-66 burst opcode fetch enable 4-68 bus fault 4-42 , 4-69 byte empty in dma fifo 4-54 byte full in dma fifo 4-54 byte offset counter 4-58 , 4-62 cache line size enable 4-70 chained mode 4-28 chip revision level 4-56 chip type 4-82 clear dma fifo 4-56 clear scsi fifo 4-93 clock address incrementor 4-61 clock byte counter 4-61 clock conversion factor 4-32 configured as i/o 4-55 configured as memory 4-55 connected 4-26 , 4-51 data acknowledge status 4-56 data request status 4-55 data transfer direction 4-54 destination i/o-memory enable 4-67 disable halt on parity error or atn 4-25 disable single initiator response 4-93 dma direction 4-61 dma fifo 4-62 dma fifo empty 4-42 dma interrupt pending 4-53 enable parity checking 4-24 enable read line 4-68 enable read multiple 4-68 enable response to reselection 4-32 enable response to selection 4-33 enable wide scsi 4-31 encoded chip scsi id, bits [3:0] 4-33 encoded destination scsi id 4-36 , 4-40 extend sreq/sack filtering 4-91 extra clock cycle of data setup 4-25 fetch enable 4-82 fetch pin mode 4-57 fifo byte control 4-60 fifo flags 4-46 , 4-49 flush dma fifo 4-56 function complete 4-73 , 4-77 general purpose timer expired 4-76 , 4-79 general purpose timer period 4-85 general purpose timer scale factor 4-85 gpio enable 4-83 gpio[4:0] 4-37 halt scsi clock 4-93 handshake-to-handshake timer bus activity enable 4-85 handshake-to-handshake timer expired 4-76 , 4-79 handshake-to-handshake timer period 4-83 high impedance mode 4-59 illegal instruction detected 4-43 , 4-69 immediate arbitration 4-26 interrupt-on-the-fly 4-52 irq disable 4-71 last disconnect 4-49 latched scsi parity 4-47 latched scsi parity for sd[15:8] 4-49 lost arbitration 4-45 lsi53c700 family compatibility 4-72 manual start mode 4-68 master control for set or reset pulses 4-61 master data parity error 4-42 , 4-69 master enable 4-82 master parity error enable 4-60 max scsi synchronous offset 4-35 parity error 4-78 phase mismatch 4-77 prefetch enable 4-70 prefetch flush 4-70 reselected 4-74 , 4-77 reset scsi offset 4-90 sack/ status 4-41 satn/ status 4-41 sbsy/ status 4-41 sc_d/ status 4-41 scripts interrupt instruction received 4-43 , 4-69 scsi c_d/ signal 4-47 scsi control enable 4-90 scsi data high impedance 4-59 scsi disconnect unexpected 4-28 scsi fifo test read 4-92 scsi fifo test write 4-94 scsi gross error 4-74 , 4-77 scsi high impedance mode 4-91 scsi i_o/ signal 4-47 scsi interrupt pending 4-52 scsi loopback mode 4-90 scsi low level mode 4-91 scsi msg/ signal 4-47 scsi parity error 4-75 scsi phase mismatch - initiator mode 4-73 scsi reset condition 4-75 scsi rst/ received 4-78 scsi rst/ signal 4-45 scsi sdp0/ parity signal 4-46 scsi sdp1 signal 4-49 scsi selected as id 4-87 scsi synchronous offset maximum 4-88 scsi synchronous offset zero 4-87 scsi synchronous transfer period 4-34 scsi true end of process 4-55 scsi valid 4-40 select with satn/ on a start sequence 4-23 selected 4-73 , 4-77 selection or reselection time-out 4-75 , 4-79 selection response logic test 4-87 selection time-out 4-84 semaphore 4-51 shadow register test mode 4-59 si_o/ status 4-41 sidl least significant byte full 4-44 sidl most significant byte full 4-48 signal process 4-51 , 4-54 single-step interrupt 4-43 , 4-69 single-step mode 4-71 slpar high byte enable 4-29 slpar mode 4-29 smsg/ status 4-41 sodl least significant byte full 4-45 sodl most significant byte full 4-48 sodr least significant byte full 4-44 sodr most significant byte full 4-48 software reset 4-51
index ix-7 register bits (cont.) source i/o-memory enable 4-67 sreq/ status 4-41 ssel/ status 4-41 start dma operation 4-71 start scsi transfer 4-27 start sequence 4-23 synchronous clock conversion factor 4-31 target mode 4-24 timer test mode 4-93 tolerant enable 4-92 ultra scsi enable 4-31 unexpected disconnect 4-74 , 4-78 wide scsi receive 4-30 wide scsi send 4-29 won arbitration 4-45 write and invalidate enable 4-57 registers 2-33 reliability 1-7 req/ 3-9 req/ - gnt/ 1-1 , 2-3 request 3-9 reselected bit 4-74 , 4-77 reserved command 2-5 reset 3-6 reset scsi offset bit 4-90 respid0 register 4-86 respid1 register 4-86 response id one register 4-86 response id zero register 4-86 revision level bits 4-56 rom 3-18 rom base address register 2-44 rom interface 2-43 rom pin 2-45 rom/flash interface signals 3-18 rst/ 3-6 rstdir 3-16 , 3-17 s sack 2-38 sack/ 3-14 , 3-15 sack/ status bit 4-41 satn/ 3-14 , 3-15 satn/ active 4-77 satn/ active bit 4-77 satn/ status bit 4-41 sbcl register 4-41 sbdl register 4-95 sbsy status bit 4-41 sbsy/ 3-14 , 3-15 sc_d/ 3-14 , 3-15 sc_d/ status bit 4-41 scatter/gather 1-6 scf[2:0] 2-30 scid register 4-32 sclk 3-13 scntl0 register 4-22 scntl1 register 4-25 scntl2 register 4-28 scntl3 register 4-31 scratcha register 4-66 scratchb register 4-96 scripts instruction 2-41 scripts interrupt instruction received bit 4-43 scripts processor 2-13 instruction prefetching 2-14 internal ram for instruction storage 2-14 performance 2-13 scripts ram 2-4 , 2-14 scsi differential mode 2-24 termination 2-28 scsi atn condition - target mode 4-73 scsi atn condition bit 4-73 scsi bus control lines register 4-41 scsi bus data lines register 4-95 scsi bus interface 2-24 scsi c_d/ signal bit 4-47 scsi chip id register 4-32 scsi clock 3-13 , 3-16 , 3-17 scsi control 3-14 , 3-15 , 3-16 , 3-17 scsi control enable bit 4-90 scsi control one register 4-25 scsi control three register 4-31 scsi control two register 4-28 scsi control zero register 4-22 scsi controller 2-13 scsi core 1-3 scsi data high impedance bit 4-59 scsi destination id register 4-36 scsi disconnect unexpected bit 4-28 scsi fifo test read bit 4-92 scsi fifo test write bit 4-94 scsi first byte received register 4-38 scsi gross error bit 4-74 , 4-77 scsi high impedance mode bit 4-91 scsi i_o/ signal bit 4-47 scsi input data latch register 4-94 scsi instructions block move 5-6 i/o 5-13 load/store 5-38 memory move 5-34 read/write 5-22 transfer control 5-27 scsi interrupt enable one register 4-75 scsi interrupt enable zero register 4-73 scsi interrupt pending bit 4-52 scsi interrupt status one register 4-79 scsi interrupt status zero register 4-76 scsi interrupts 2-38 scsi longitudinal parity register 4-80 scsi loopback mode bit 4-90 scsi low level mode bit 4-91 scsi msg/ signal bit 4-47 scsi output control latch register 4-39 scsi output data latch register 4-95 scsi parity error bit 4-75 scsi performance 1-5 scsi phase mismatch bit 4-73 scsi reset condition bit 4-75 scsi rst/ received bit 4-78 scsi rst/ signal bit 4-45 scsi scripts 1-3 scsi scripts operation 5-2 sample instruction 5-3 scsi sdp0/ parity signal bit 4-46 scsi sdp1 signal bit 4-49 scsi selected as id bits 4-87 scsi selector id register 4-40
ix-8 index scsi serial eeprom access 2-45 scsi status one register 4-46 scsi status two register 4-48 scsi status zero register 4-44 scsi synchronous offset maximum 4-88 scsi synchronous offset zero bit 4-87 scsi test one register 4-88 scsi test three register 4-92 scsi test two register 4-90 scsi test zero register 4-87 scsi timer one register 4-85 scsi timer zero register 4-83 scsi transfer register 4-33 scsi true end of process bit 4-55 scsi valid bit 4-40 scsi wide residue register 4-81 sctrl/ 3-14 , 3-15 , 3-16 , 3-17 sd/[15:0] 3-14 , 3-15 , 3-16 , 3-17 sdid register 4-36 sdir 3-16 sdir[15:0] 3-17 sdms 1-3 sdp/[1:0] 3-14 , 3-15 sel 2-35 select with satn/ on a start sequence bit 4-23 selected bit 4-73 , 4-77 selection of cache line size 2-11 selection or reselection time-out bit 4-75 , 4-79 selection response logic test bits 4-87 semaphore bit 4-51 serial eeprom interface 2-45 mode a operation 2-45 mode b operation 2-46 mode c operation 2-46 mode d operation 2-48 register 0x2c 4-11 register 0x2e 4-12 serr/ 3-9 sfbr register 4-38 shadow register test mode bit 4-59 si_o/ 3-14 , 3-15 si_o/ status bit 4-41 sidl least significant byte full bit 4-44 sidl most significant byte full bit 4-48 sidl register 4-94 sien0 2-35 sien0 register 4-73 sien1 2-35 sien1 register 4-75 sigp bit 4-51 , 4-54 single-ended operation 2-24 single-step interrupt bit 4-43 , 4-69 single-step mode bit 4-71 sip 2-34 , 2-37 , 2-38 sist0 2-34 , 2-37 , 2-39 sist0 register 4-76 sist1 2-34 , 2-37 , 2-39 sist1 register 4-79 slow rom pin 3-22 slpar high byte enable 4-29 slpar mode bit 4-29 slpar register 4-80 smsg/ 3-14 , 3-15 smsg/ status bit 4-41 socl least significant byte full bit 4-45 socl register 4-39 sodl most significant byte full bit 4-48 sodl register 4-95 sodr least significant byte full bit 4-44 sodr most significant byte full bit 4-48 software reset bit 4-51 source i/o-memory enable bit 4-67 special cycle command 2-5 sreq 2-38 sreq/ 3-14 , 3-15 sreq/ status bit 4-41 srst/ 3-14 , 3-15 ssel/ 3-14 , 3-15 ssel/ status bit 4-41 ssid register 4-40 sstat0 register 4-44 sstat1 register 4-46 sstat2 register 4-48 stacked interrupts 2-37 start dma operation bit 4-71 start scsi transfer 4-27 start sequence bit 4-23 stest0 register 4-87 stest1 register 4-88 stest2 register 4-90 stest3 register 4-92 stime0 register 4-83 stime1 register 4-85 stop 3-8 subsystem id 2-46 , 2-47 (sid[15:0]) 4-12 subsystem vendor id 2-46 , 2-47 (svid[15:0]) 4-11 swide register 4-81 sxfer register 4-33 synchronous clock conversion factor bits 4-31 synchronous data transfer rates 2-30 synchronous operation 2-30 synchronous scsi receive 2-23 synchronous scsi send 2-22 synchronous transfer period bits 4-34 system signals 3-6 t target mode bit 4-24 target ready 3-8 tck 3-19 tdi 3-20 tdo 3-20 temp register 4-57 temporary register 4-57 termination 2-28 terminator networks 2-28 testability 1-6 testin/ 3-19 tgs 3-16 , 3-17 timer test mode bit 4-93 timing diagrams 6-15 tms 3-19 tolerant enable bit 2-33 , 4-92 tolerant scsi 1-4 tolerant technology 1-7 benefits 1-4 extend sreq/sack filtering bit 4-91 tolerant enable bit 4-92 totem pole output 3-5
index ix-9 tp[2:0] 2-30 transfer control instructions 5-27 and scripts instruction prefetching 2-15 transfer rate synchronous 2-30 trdy/ 3-8 u ultra scsi 1-2 , 1-3 , 1-4 clock conversion factor bits 4-32 synchronous transfer period bits 4-34 ultra scsi enable bit 4-31 ultra scsi enable bit 4-31 ultra scsi synchronous data transfers 2-31 unexpected disconnect bit 4-74 , 4-78 v vdd 3-20 vdd-c 3-20 vdd-io 3-20 vss 3-20 vss-c 3-20 vss-s 3-20 w watn/ bit 4-23 wide scsi always wide scsi bit 4-91 chained block moves 2-40 chained mode bit 4-28 enable wide scsi bit 4-31 swide register 4-81 wide scsi receive bit 4-30 wide scsi send bit 4-29 wide scsi receive bit 4-30 wide scsi send bit 4-29 wide ultra scsi 1-4 wide ultra scsi benefits 1-4 wide ultra scsi enable bit 2-33 wide ultra scsi mode enable bit 2-31 wide ultra scsi synchronous data transfers 2-31 won arbitration bit 4-45 write and invalidate enable bit 4-57 wsr bit 2-41 wss flag 2-41
ix-10 index
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u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arkansas w. e. tel: 972.235.9953 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 california agoura hills b. m. tel: 818.865.0266 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5575 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlingtonr i. e. tel: 781.270.9400 marlborough b. m. tel: 508.480.9099 woburn b. m. tel: 781.933.9010 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 609.222.9566 pine brook w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beavertonr b. m. tel: 503.524.0787 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 philadelphia a. e. tel: 800.526.4812 b. m. tel: 215.741.4080 w. e. tel: 800.871.9953 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 washington kirkland i. e. tel: 425.820.8100 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953
direct sales representatives by state (component and boards) e. a. earle associates e. l. electrodyne - ut grp group 2000 i. s. in?nity sales, inc. ion ion associates, inc. r. a. rathsburg associ- ates, inc. sgy synergy associates, inc. arizona tempe e. a. tel: 480.921.3305 california calabasas i. s. tel: 818.880.6480 irvine i. s. tel: 714.833.0300 san diego e. a. tel: 619.278.5441 illinois elmhurst r. a. tel: 630.516.8400 indiana cicero r. a. tel: 317.984.8608 ligonier r. a. tel: 219.894.3184 plain?eld r. a. tel: 317.838.0360 massachusetts burlington sgy tel: 781.238.0870 michigan byron center r. a. tel: 616.554.1460 good rich r. a. tel: 810.636.6060 novi r. a. tel: 810.615.4000 north carolina cary grp tel: 919.481.1530 ohio columbus r. a. tel: 614.457.2242 dayton r. a. tel: 513.291.4001 independence r. a. tel: 216.447.8825 pennsylvania somerset r. a. tel: 814.445.6976 texas austin ion tel: 512.794.9006 arlington ion tel: 817.695.8000 houston ion tel: 281.376.2000 utah salt lake city e. l. tel: 801.264.8050 wisconsin muskego r. a. tel: 414.679.8250 saukville r. a. tel: 414.268.1152
sales of?ces and design resource centers lsi logic corporation corporate headquarters tel: 408.433.8000 fax: 408.433.8989 north america california costa mesa - mint technology tel: 949.752.6468 fax: 949.752.6868 irvine tel: 949.809.4600 fax: 949.809.4444 pleasanton design center tel: 925.730.8800 fax: 925.730.8700 san diego tel: 858.467.6981 fax: 858.496.0548 silicon valley tel: 408.433.8000 fax: 408.954.3353 wireless design center tel: 858.350.5560 fax: 858.350.0171 colorado boulder tel: 303.447.3800 fax: 303.541.0641 colorado springs tel: 719.533.7000 fax: 719.533.7020 fort collins tel: 970.223.5100 fax: 970.206.5549 florida boca raton tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green tel: 270.793.0010 fax: 270.793.0040 maryland bethesda tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis tel: 612.921.8300 fax: 612.921.8399 new jersey red bank tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology tel: 609.489.5530 fax: 609.489.5531 new york fairport tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh tel: 919.785.4520 fax: 919.783.8909 oregon beaverton tel: 503.645.0589 fax: 503.645.6612 texas austin tel: 512.388.7294 fax: 512.388.4171 plano tel: 972.244.5000 fax: 972.244.5001 houston tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milano lsi logic s.p.a. tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka tel: 81.6.947.5281 fax: 81.6.947.5287 korea seoul lsi logic corporation of korea ltd tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd tel: 65.334.9061 fax: 65.334.4749 tel: 65.835.5040 fax: 65.732.5047 sweden stockholm lsi logic ab tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers
international distributors australia new south wales reptechnic pty ltd tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. tel: 86.10.6804.2534 fax: 86.10.6804.2521 france rungis cedex azzurri technology france tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd tel: 852.2428.0008 fax: 852.2401.2105 eastele tel: 852.2798.8860 fax: 852.2305.0640 india bangalore spike technologies india private ltd tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo global electronics corporation tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 yokohama-city macnica corporation tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd tel: 886.2.2721.9533 fax: 886.2.2773.3756 serial semiconductor corporation, ltd tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd tel: 44.1628.826826 fax: 44.1628.829730 swindon ebv elektronik tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers

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